1 /* SuperH Ethernet device driver
3 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
4 * Copyright (C) 2008-2014 Renesas Solutions Corp.
5 * Copyright (C) 2013-2014 Cogent Embedded, Inc.
6 * Copyright (C) 2014 Codethink Limited
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * The full GNU General Public License is included in this distribution in
18 * the file called "COPYING".
21 #include <linux/module.h>
22 #include <linux/kernel.h>
23 #include <linux/spinlock.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/etherdevice.h>
27 #include <linux/delay.h>
28 #include <linux/platform_device.h>
29 #include <linux/mdio-bitbang.h>
30 #include <linux/netdevice.h>
32 #include <linux/of_device.h>
33 #include <linux/of_irq.h>
34 #include <linux/of_net.h>
35 #include <linux/phy.h>
36 #include <linux/cache.h>
38 #include <linux/pm_runtime.h>
39 #include <linux/slab.h>
40 #include <linux/ethtool.h>
41 #include <linux/if_vlan.h>
42 #include <linux/clk.h>
43 #include <linux/sh_eth.h>
44 #include <linux/of_mdio.h>
48 #define SH_ETH_DEF_MSG_ENABLE \
54 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
108 [TSU_CTRST] = 0x0004,
109 [TSU_FWEN0] = 0x0010,
110 [TSU_FWEN1] = 0x0014,
112 [TSU_BSYSL0] = 0x0020,
113 [TSU_BSYSL1] = 0x0024,
114 [TSU_PRISL0] = 0x0028,
115 [TSU_PRISL1] = 0x002c,
116 [TSU_FWSL0] = 0x0030,
117 [TSU_FWSL1] = 0x0034,
118 [TSU_FWSLC] = 0x0038,
119 [TSU_QTAG0] = 0x0040,
120 [TSU_QTAG1] = 0x0044,
122 [TSU_FWINMK] = 0x0054,
123 [TSU_ADQT0] = 0x0048,
124 [TSU_ADQT1] = 0x004c,
125 [TSU_VTAG0] = 0x0058,
126 [TSU_VTAG1] = 0x005c,
127 [TSU_ADSBSY] = 0x0060,
129 [TSU_POST1] = 0x0070,
130 [TSU_POST2] = 0x0074,
131 [TSU_POST3] = 0x0078,
132 [TSU_POST4] = 0x007c,
133 [TSU_ADRH0] = 0x0100,
134 [TSU_ADRL0] = 0x0104,
135 [TSU_ADRH31] = 0x01f8,
136 [TSU_ADRL31] = 0x01fc,
152 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
196 [TSU_CTRST] = 0x0004,
197 [TSU_VTAG0] = 0x0058,
198 [TSU_ADSBSY] = 0x0060,
200 [TSU_ADRH0] = 0x0100,
201 [TSU_ADRL0] = 0x0104,
202 [TSU_ADRH31] = 0x01f8,
203 [TSU_ADRL31] = 0x01fc,
211 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
257 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
309 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
335 [TSU_CTRST] = 0x0004,
336 [TSU_FWEN0] = 0x0010,
337 [TSU_FWEN1] = 0x0014,
339 [TSU_BSYSL0] = 0x0020,
340 [TSU_BSYSL1] = 0x0024,
341 [TSU_PRISL0] = 0x0028,
342 [TSU_PRISL1] = 0x002c,
343 [TSU_FWSL0] = 0x0030,
344 [TSU_FWSL1] = 0x0034,
345 [TSU_FWSLC] = 0x0038,
346 [TSU_QTAGM0] = 0x0040,
347 [TSU_QTAGM1] = 0x0044,
348 [TSU_ADQT0] = 0x0048,
349 [TSU_ADQT1] = 0x004c,
351 [TSU_FWINMK] = 0x0054,
352 [TSU_ADSBSY] = 0x0060,
354 [TSU_POST1] = 0x0070,
355 [TSU_POST2] = 0x0074,
356 [TSU_POST3] = 0x0078,
357 [TSU_POST4] = 0x007c,
372 [TSU_ADRH0] = 0x0100,
373 [TSU_ADRL0] = 0x0104,
374 [TSU_ADRL31] = 0x01fc,
377 static bool sh_eth_is_gether(struct sh_eth_private *mdp)
379 return mdp->reg_offset == sh_eth_offset_gigabit;
382 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
384 return mdp->reg_offset == sh_eth_offset_fast_rz;
387 static void sh_eth_select_mii(struct net_device *ndev)
390 struct sh_eth_private *mdp = netdev_priv(ndev);
392 switch (mdp->phy_interface) {
393 case PHY_INTERFACE_MODE_GMII:
396 case PHY_INTERFACE_MODE_MII:
399 case PHY_INTERFACE_MODE_RMII:
404 "PHY interface mode was not setup. Set to MII.\n");
409 sh_eth_write(ndev, value, RMII_MII);
412 static void sh_eth_set_duplex(struct net_device *ndev)
414 struct sh_eth_private *mdp = netdev_priv(ndev);
416 if (mdp->duplex) /* Full */
417 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
419 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
422 /* There is CPU dependent code */
423 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
425 struct sh_eth_private *mdp = netdev_priv(ndev);
427 switch (mdp->speed) {
428 case 10: /* 10BASE */
429 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
431 case 100:/* 100BASE */
432 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
440 static struct sh_eth_cpu_data r8a777x_data = {
441 .set_duplex = sh_eth_set_duplex,
442 .set_rate = sh_eth_set_rate_r8a777x,
444 .register_type = SH_ETH_REG_FAST_RCAR,
446 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
447 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
448 .eesipr_value = 0x01ff009f,
450 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
451 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
452 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
462 static struct sh_eth_cpu_data r8a779x_data = {
463 .set_duplex = sh_eth_set_duplex,
464 .set_rate = sh_eth_set_rate_r8a777x,
466 .register_type = SH_ETH_REG_FAST_RCAR,
468 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
469 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
470 .eesipr_value = 0x01ff009f,
472 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
473 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
474 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
485 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
487 struct sh_eth_private *mdp = netdev_priv(ndev);
489 switch (mdp->speed) {
490 case 10: /* 10BASE */
491 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
493 case 100:/* 100BASE */
494 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
502 static struct sh_eth_cpu_data sh7724_data = {
503 .set_duplex = sh_eth_set_duplex,
504 .set_rate = sh_eth_set_rate_sh7724,
506 .register_type = SH_ETH_REG_FAST_SH4,
508 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
509 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
510 .eesipr_value = 0x01ff009f,
512 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
513 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
514 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
522 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
525 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
527 struct sh_eth_private *mdp = netdev_priv(ndev);
529 switch (mdp->speed) {
530 case 10: /* 10BASE */
531 sh_eth_write(ndev, 0, RTRATE);
533 case 100:/* 100BASE */
534 sh_eth_write(ndev, 1, RTRATE);
542 static struct sh_eth_cpu_data sh7757_data = {
543 .set_duplex = sh_eth_set_duplex,
544 .set_rate = sh_eth_set_rate_sh7757,
546 .register_type = SH_ETH_REG_FAST_SH4,
548 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
549 .rmcr_value = RMCR_RNC,
551 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
552 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
553 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
556 .irq_flags = IRQF_SHARED,
563 .rpadir_value = 2 << 16,
566 #define SH_GIGA_ETH_BASE 0xfee00000UL
567 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
568 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
569 static void sh_eth_chip_reset_giga(struct net_device *ndev)
572 unsigned long mahr[2], malr[2];
574 /* save MAHR and MALR */
575 for (i = 0; i < 2; i++) {
576 malr[i] = ioread32((void *)GIGA_MALR(i));
577 mahr[i] = ioread32((void *)GIGA_MAHR(i));
581 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
584 /* restore MAHR and MALR */
585 for (i = 0; i < 2; i++) {
586 iowrite32(malr[i], (void *)GIGA_MALR(i));
587 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
591 static void sh_eth_set_rate_giga(struct net_device *ndev)
593 struct sh_eth_private *mdp = netdev_priv(ndev);
595 switch (mdp->speed) {
596 case 10: /* 10BASE */
597 sh_eth_write(ndev, 0x00000000, GECMR);
599 case 100:/* 100BASE */
600 sh_eth_write(ndev, 0x00000010, GECMR);
602 case 1000: /* 1000BASE */
603 sh_eth_write(ndev, 0x00000020, GECMR);
610 /* SH7757(GETHERC) */
611 static struct sh_eth_cpu_data sh7757_data_giga = {
612 .chip_reset = sh_eth_chip_reset_giga,
613 .set_duplex = sh_eth_set_duplex,
614 .set_rate = sh_eth_set_rate_giga,
616 .register_type = SH_ETH_REG_GIGABIT,
618 .ecsr_value = ECSR_ICD | ECSR_MPD,
619 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
620 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
622 .tx_check = EESR_TC1 | EESR_FTC,
623 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
624 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
626 .fdr_value = 0x0000072f,
627 .rmcr_value = RMCR_RNC,
629 .irq_flags = IRQF_SHARED,
636 .rpadir_value = 2 << 16,
642 static void sh_eth_chip_reset(struct net_device *ndev)
644 struct sh_eth_private *mdp = netdev_priv(ndev);
647 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
651 static void sh_eth_set_rate_gether(struct net_device *ndev)
653 struct sh_eth_private *mdp = netdev_priv(ndev);
655 switch (mdp->speed) {
656 case 10: /* 10BASE */
657 sh_eth_write(ndev, GECMR_10, GECMR);
659 case 100:/* 100BASE */
660 sh_eth_write(ndev, GECMR_100, GECMR);
662 case 1000: /* 1000BASE */
663 sh_eth_write(ndev, GECMR_1000, GECMR);
671 static struct sh_eth_cpu_data sh7734_data = {
672 .chip_reset = sh_eth_chip_reset,
673 .set_duplex = sh_eth_set_duplex,
674 .set_rate = sh_eth_set_rate_gether,
676 .register_type = SH_ETH_REG_GIGABIT,
678 .ecsr_value = ECSR_ICD | ECSR_MPD,
679 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
680 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
682 .tx_check = EESR_TC1 | EESR_FTC,
683 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
684 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
700 static struct sh_eth_cpu_data sh7763_data = {
701 .chip_reset = sh_eth_chip_reset,
702 .set_duplex = sh_eth_set_duplex,
703 .set_rate = sh_eth_set_rate_gether,
705 .register_type = SH_ETH_REG_GIGABIT,
707 .ecsr_value = ECSR_ICD | ECSR_MPD,
708 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
709 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
711 .tx_check = EESR_TC1 | EESR_FTC,
712 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
713 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
724 .irq_flags = IRQF_SHARED,
727 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
729 struct sh_eth_private *mdp = netdev_priv(ndev);
732 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
735 sh_eth_select_mii(ndev);
739 static struct sh_eth_cpu_data r8a7740_data = {
740 .chip_reset = sh_eth_chip_reset_r8a7740,
741 .set_duplex = sh_eth_set_duplex,
742 .set_rate = sh_eth_set_rate_gether,
744 .register_type = SH_ETH_REG_GIGABIT,
746 .ecsr_value = ECSR_ICD | ECSR_MPD,
747 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
748 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
750 .tx_check = EESR_TC1 | EESR_FTC,
751 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
752 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
754 .fdr_value = 0x0000070f,
755 .rmcr_value = RMCR_RNC,
763 .rpadir_value = 2 << 16,
772 static struct sh_eth_cpu_data r7s72100_data = {
773 .chip_reset = sh_eth_chip_reset,
774 .set_duplex = sh_eth_set_duplex,
776 .register_type = SH_ETH_REG_FAST_RZ,
778 .ecsr_value = ECSR_ICD,
779 .ecsipr_value = ECSIPR_ICDIP,
780 .eesipr_value = 0xff7f009f,
782 .tx_check = EESR_TC1 | EESR_FTC,
783 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
784 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
786 .fdr_value = 0x0000070f,
787 .rmcr_value = RMCR_RNC,
795 .rpadir_value = 2 << 16,
803 static struct sh_eth_cpu_data sh7619_data = {
804 .register_type = SH_ETH_REG_FAST_SH3_SH2,
806 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
814 static struct sh_eth_cpu_data sh771x_data = {
815 .register_type = SH_ETH_REG_FAST_SH3_SH2,
817 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
821 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
824 cd->ecsr_value = DEFAULT_ECSR_INIT;
826 if (!cd->ecsipr_value)
827 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
829 if (!cd->fcftr_value)
830 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
831 DEFAULT_FIFO_F_D_RFD;
834 cd->fdr_value = DEFAULT_FDR_INIT;
837 cd->rmcr_value = DEFAULT_RMCR_VALUE;
840 cd->tx_check = DEFAULT_TX_CHECK;
842 if (!cd->eesr_err_check)
843 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
846 static int sh_eth_check_reset(struct net_device *ndev)
852 if (!(sh_eth_read(ndev, EDMR) & 0x3))
858 netdev_err(ndev, "Device reset failed\n");
864 static int sh_eth_reset(struct net_device *ndev)
866 struct sh_eth_private *mdp = netdev_priv(ndev);
869 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
870 sh_eth_write(ndev, EDSR_ENALL, EDSR);
871 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
874 ret = sh_eth_check_reset(ndev);
879 sh_eth_write(ndev, 0x0, TDLAR);
880 sh_eth_write(ndev, 0x0, TDFAR);
881 sh_eth_write(ndev, 0x0, TDFXR);
882 sh_eth_write(ndev, 0x0, TDFFR);
883 sh_eth_write(ndev, 0x0, RDLAR);
884 sh_eth_write(ndev, 0x0, RDFAR);
885 sh_eth_write(ndev, 0x0, RDFXR);
886 sh_eth_write(ndev, 0x0, RDFFR);
888 /* Reset HW CRC register */
890 sh_eth_write(ndev, 0x0, CSMR);
892 /* Select MII mode */
893 if (mdp->cd->select_mii)
894 sh_eth_select_mii(ndev);
896 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
899 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
906 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
907 static void sh_eth_set_receive_align(struct sk_buff *skb)
911 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
913 skb_reserve(skb, reserve);
916 static void sh_eth_set_receive_align(struct sk_buff *skb)
918 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
923 /* CPU <-> EDMAC endian convert */
924 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
926 switch (mdp->edmac_endian) {
927 case EDMAC_LITTLE_ENDIAN:
928 return cpu_to_le32(x);
929 case EDMAC_BIG_ENDIAN:
930 return cpu_to_be32(x);
935 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
937 switch (mdp->edmac_endian) {
938 case EDMAC_LITTLE_ENDIAN:
939 return le32_to_cpu(x);
940 case EDMAC_BIG_ENDIAN:
941 return be32_to_cpu(x);
946 /* Program the hardware MAC address from dev->dev_addr. */
947 static void update_mac_address(struct net_device *ndev)
950 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
951 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
953 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
956 /* Get MAC address from SuperH MAC address register
958 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
959 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
960 * When you want use this device, you must set MAC address in bootloader.
963 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
965 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
966 memcpy(ndev->dev_addr, mac, ETH_ALEN);
968 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
969 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
970 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
971 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
972 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
973 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
977 static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
979 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
980 return EDTRR_TRNS_GETHER;
982 return EDTRR_TRNS_ETHER;
986 void (*set_gate)(void *addr);
987 struct mdiobb_ctrl ctrl;
989 u32 mmd_msk;/* MMD */
996 static void bb_set(void *addr, u32 msk)
998 iowrite32(ioread32(addr) | msk, addr);
1002 static void bb_clr(void *addr, u32 msk)
1004 iowrite32((ioread32(addr) & ~msk), addr);
1008 static int bb_read(void *addr, u32 msk)
1010 return (ioread32(addr) & msk) != 0;
1013 /* Data I/O pin control */
1014 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1016 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1018 if (bitbang->set_gate)
1019 bitbang->set_gate(bitbang->addr);
1022 bb_set(bitbang->addr, bitbang->mmd_msk);
1024 bb_clr(bitbang->addr, bitbang->mmd_msk);
1028 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1030 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1032 if (bitbang->set_gate)
1033 bitbang->set_gate(bitbang->addr);
1036 bb_set(bitbang->addr, bitbang->mdo_msk);
1038 bb_clr(bitbang->addr, bitbang->mdo_msk);
1042 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1044 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1046 if (bitbang->set_gate)
1047 bitbang->set_gate(bitbang->addr);
1049 return bb_read(bitbang->addr, bitbang->mdi_msk);
1052 /* MDC pin control */
1053 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1055 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1057 if (bitbang->set_gate)
1058 bitbang->set_gate(bitbang->addr);
1061 bb_set(bitbang->addr, bitbang->mdc_msk);
1063 bb_clr(bitbang->addr, bitbang->mdc_msk);
1066 /* mdio bus control struct */
1067 static struct mdiobb_ops bb_ops = {
1068 .owner = THIS_MODULE,
1069 .set_mdc = sh_mdc_ctrl,
1070 .set_mdio_dir = sh_mmd_ctrl,
1071 .set_mdio_data = sh_set_mdio,
1072 .get_mdio_data = sh_get_mdio,
1075 /* free skb and descriptor buffer */
1076 static void sh_eth_ring_free(struct net_device *ndev)
1078 struct sh_eth_private *mdp = netdev_priv(ndev);
1081 /* Free Rx skb ringbuffer */
1082 if (mdp->rx_skbuff) {
1083 for (i = 0; i < mdp->num_rx_ring; i++) {
1084 if (mdp->rx_skbuff[i])
1085 dev_kfree_skb(mdp->rx_skbuff[i]);
1088 kfree(mdp->rx_skbuff);
1089 mdp->rx_skbuff = NULL;
1091 /* Free Tx skb ringbuffer */
1092 if (mdp->tx_skbuff) {
1093 for (i = 0; i < mdp->num_tx_ring; i++) {
1094 if (mdp->tx_skbuff[i])
1095 dev_kfree_skb(mdp->tx_skbuff[i]);
1098 kfree(mdp->tx_skbuff);
1099 mdp->tx_skbuff = NULL;
1102 /* format skb and descriptor buffer */
1103 static void sh_eth_ring_format(struct net_device *ndev)
1105 struct sh_eth_private *mdp = netdev_priv(ndev);
1107 struct sk_buff *skb;
1108 struct sh_eth_rxdesc *rxdesc = NULL;
1109 struct sh_eth_txdesc *txdesc = NULL;
1110 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1111 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1118 memset(mdp->rx_ring, 0, rx_ringsize);
1120 /* build Rx ring buffer */
1121 for (i = 0; i < mdp->num_rx_ring; i++) {
1123 mdp->rx_skbuff[i] = NULL;
1124 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
1125 mdp->rx_skbuff[i] = skb;
1128 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
1130 sh_eth_set_receive_align(skb);
1133 rxdesc = &mdp->rx_ring[i];
1134 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
1135 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1137 /* The size of the buffer is 16 byte boundary. */
1138 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1139 /* Rx descriptor address set */
1141 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1142 if (sh_eth_is_gether(mdp) ||
1143 sh_eth_is_rz_fast_ether(mdp))
1144 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1148 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1150 /* Mark the last entry as wrapping the ring. */
1151 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
1153 memset(mdp->tx_ring, 0, tx_ringsize);
1155 /* build Tx ring buffer */
1156 for (i = 0; i < mdp->num_tx_ring; i++) {
1157 mdp->tx_skbuff[i] = NULL;
1158 txdesc = &mdp->tx_ring[i];
1159 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1160 txdesc->buffer_length = 0;
1162 /* Tx descriptor address set */
1163 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1164 if (sh_eth_is_gether(mdp) ||
1165 sh_eth_is_rz_fast_ether(mdp))
1166 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1170 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1173 /* Get skb and descriptor buffer */
1174 static int sh_eth_ring_init(struct net_device *ndev)
1176 struct sh_eth_private *mdp = netdev_priv(ndev);
1177 int rx_ringsize, tx_ringsize, ret = 0;
1179 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1180 * card needs room to do 8 byte alignment, +2 so we can reserve
1181 * the first 2 bytes, and +16 gets room for the status word from the
1184 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1185 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1186 if (mdp->cd->rpadir)
1187 mdp->rx_buf_sz += NET_IP_ALIGN;
1189 /* Allocate RX and TX skb rings */
1190 mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring,
1191 sizeof(*mdp->rx_skbuff), GFP_KERNEL);
1192 if (!mdp->rx_skbuff) {
1197 mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring,
1198 sizeof(*mdp->tx_skbuff), GFP_KERNEL);
1199 if (!mdp->tx_skbuff) {
1204 /* Allocate all Rx descriptors. */
1205 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1206 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1208 if (!mdp->rx_ring) {
1210 goto desc_ring_free;
1215 /* Allocate all Tx descriptors. */
1216 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1217 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1219 if (!mdp->tx_ring) {
1221 goto desc_ring_free;
1226 /* free DMA buffer */
1227 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1230 /* Free Rx and Tx skb ring buffer */
1231 sh_eth_ring_free(ndev);
1232 mdp->tx_ring = NULL;
1233 mdp->rx_ring = NULL;
1238 static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
1243 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1244 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1246 mdp->rx_ring = NULL;
1250 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1251 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1253 mdp->tx_ring = NULL;
1257 static int sh_eth_dev_init(struct net_device *ndev, bool start)
1260 struct sh_eth_private *mdp = netdev_priv(ndev);
1264 ret = sh_eth_reset(ndev);
1268 if (mdp->cd->rmiimode)
1269 sh_eth_write(ndev, 0x1, RMIIMODE);
1271 /* Descriptor format */
1272 sh_eth_ring_format(ndev);
1273 if (mdp->cd->rpadir)
1274 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1276 /* all sh_eth int mask */
1277 sh_eth_write(ndev, 0, EESIPR);
1279 #if defined(__LITTLE_ENDIAN)
1280 if (mdp->cd->hw_swap)
1281 sh_eth_write(ndev, EDMR_EL, EDMR);
1284 sh_eth_write(ndev, 0, EDMR);
1287 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1288 sh_eth_write(ndev, 0, TFTR);
1290 /* Frame recv control */
1291 sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR);
1293 sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER);
1296 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
1298 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1300 if (!mdp->cd->no_trimd)
1301 sh_eth_write(ndev, 0, TRIMD);
1303 /* Recv frame limit set register */
1304 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1307 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
1309 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1311 /* PAUSE Prohibition */
1312 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
1313 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1315 sh_eth_write(ndev, val, ECMR);
1317 if (mdp->cd->set_rate)
1318 mdp->cd->set_rate(ndev);
1320 /* E-MAC Status Register clear */
1321 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1323 /* E-MAC Interrupt Enable register */
1325 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1327 /* Set MAC address */
1328 update_mac_address(ndev);
1332 sh_eth_write(ndev, APR_AP, APR);
1334 sh_eth_write(ndev, MPR_MP, MPR);
1335 if (mdp->cd->tpauser)
1336 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1339 /* Setting the Rx mode will start the Rx process. */
1340 sh_eth_write(ndev, EDRRR_R, EDRRR);
1342 netif_start_queue(ndev);
1348 /* free Tx skb function */
1349 static int sh_eth_txfree(struct net_device *ndev)
1351 struct sh_eth_private *mdp = netdev_priv(ndev);
1352 struct sh_eth_txdesc *txdesc;
1356 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1357 entry = mdp->dirty_tx % mdp->num_tx_ring;
1358 txdesc = &mdp->tx_ring[entry];
1359 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
1361 /* Free the original skb. */
1362 if (mdp->tx_skbuff[entry]) {
1363 dma_unmap_single(&ndev->dev, txdesc->addr,
1364 txdesc->buffer_length, DMA_TO_DEVICE);
1365 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1366 mdp->tx_skbuff[entry] = NULL;
1369 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1370 if (entry >= mdp->num_tx_ring - 1)
1371 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1373 ndev->stats.tx_packets++;
1374 ndev->stats.tx_bytes += txdesc->buffer_length;
1379 /* Packet receive function */
1380 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1382 struct sh_eth_private *mdp = netdev_priv(ndev);
1383 struct sh_eth_rxdesc *rxdesc;
1385 int entry = mdp->cur_rx % mdp->num_rx_ring;
1386 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1387 struct sk_buff *skb;
1392 rxdesc = &mdp->rx_ring[entry];
1393 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1394 desc_status = edmac_to_cpu(mdp, rxdesc->status);
1395 pkt_len = rxdesc->frame_length;
1406 if (!(desc_status & RDFEND))
1407 ndev->stats.rx_length_errors++;
1409 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1410 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1411 * bit 0. However, in case of the R8A7740, R8A779x, and
1412 * R7S72100 the RFS bits are from bit 25 to bit 16. So, the
1413 * driver needs right shifting by 16.
1415 if (mdp->cd->shift_rd0)
1418 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1419 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1420 ndev->stats.rx_errors++;
1421 if (desc_status & RD_RFS1)
1422 ndev->stats.rx_crc_errors++;
1423 if (desc_status & RD_RFS2)
1424 ndev->stats.rx_frame_errors++;
1425 if (desc_status & RD_RFS3)
1426 ndev->stats.rx_length_errors++;
1427 if (desc_status & RD_RFS4)
1428 ndev->stats.rx_length_errors++;
1429 if (desc_status & RD_RFS6)
1430 ndev->stats.rx_missed_errors++;
1431 if (desc_status & RD_RFS10)
1432 ndev->stats.rx_over_errors++;
1434 if (!mdp->cd->hw_swap)
1436 phys_to_virt(ALIGN(rxdesc->addr, 4)),
1438 skb = mdp->rx_skbuff[entry];
1439 mdp->rx_skbuff[entry] = NULL;
1440 if (mdp->cd->rpadir)
1441 skb_reserve(skb, NET_IP_ALIGN);
1442 dma_sync_single_for_cpu(&ndev->dev, rxdesc->addr,
1445 skb_put(skb, pkt_len);
1446 skb->protocol = eth_type_trans(skb, ndev);
1447 netif_receive_skb(skb);
1448 ndev->stats.rx_packets++;
1449 ndev->stats.rx_bytes += pkt_len;
1451 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
1452 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1453 rxdesc = &mdp->rx_ring[entry];
1456 /* Refill the Rx ring buffers. */
1457 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1458 entry = mdp->dirty_rx % mdp->num_rx_ring;
1459 rxdesc = &mdp->rx_ring[entry];
1460 /* The size of the buffer is 16 byte boundary. */
1461 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1463 if (mdp->rx_skbuff[entry] == NULL) {
1464 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
1465 mdp->rx_skbuff[entry] = skb;
1467 break; /* Better luck next round. */
1468 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
1470 sh_eth_set_receive_align(skb);
1472 skb_checksum_none_assert(skb);
1473 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
1475 if (entry >= mdp->num_rx_ring - 1)
1477 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
1480 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1483 /* Restart Rx engine if stopped. */
1484 /* If we don't need to check status, don't. -KDU */
1485 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1486 /* fix the values for the next receiving if RDE is set */
1487 if (intr_status & EESR_RDE) {
1488 u32 count = (sh_eth_read(ndev, RDFAR) -
1489 sh_eth_read(ndev, RDLAR)) >> 4;
1491 mdp->cur_rx = count;
1492 mdp->dirty_rx = count;
1494 sh_eth_write(ndev, EDRRR_R, EDRRR);
1500 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1502 /* disable tx and rx */
1503 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1504 ~(ECMR_RE | ECMR_TE), ECMR);
1507 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1509 /* enable tx and rx */
1510 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1511 (ECMR_RE | ECMR_TE), ECMR);
1514 /* error control function */
1515 static void sh_eth_error(struct net_device *ndev, int intr_status)
1517 struct sh_eth_private *mdp = netdev_priv(ndev);
1522 if (intr_status & EESR_ECI) {
1523 felic_stat = sh_eth_read(ndev, ECSR);
1524 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1525 if (felic_stat & ECSR_ICD)
1526 ndev->stats.tx_carrier_errors++;
1527 if (felic_stat & ECSR_LCHNG) {
1529 if (mdp->cd->no_psr || mdp->no_ether_link) {
1532 link_stat = (sh_eth_read(ndev, PSR));
1533 if (mdp->ether_link_active_low)
1534 link_stat = ~link_stat;
1536 if (!(link_stat & PHY_ST_LINK)) {
1537 sh_eth_rcv_snd_disable(ndev);
1540 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1541 ~DMAC_M_ECI, EESIPR);
1543 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1545 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1546 DMAC_M_ECI, EESIPR);
1547 /* enable tx and rx */
1548 sh_eth_rcv_snd_enable(ndev);
1554 if (intr_status & EESR_TWB) {
1555 /* Unused write back interrupt */
1556 if (intr_status & EESR_TABT) { /* Transmit Abort int */
1557 ndev->stats.tx_aborted_errors++;
1558 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1562 if (intr_status & EESR_RABT) {
1563 /* Receive Abort int */
1564 if (intr_status & EESR_RFRMER) {
1565 /* Receive Frame Overflow int */
1566 ndev->stats.rx_frame_errors++;
1567 netif_err(mdp, rx_err, ndev, "Receive Abort\n");
1571 if (intr_status & EESR_TDE) {
1572 /* Transmit Descriptor Empty int */
1573 ndev->stats.tx_fifo_errors++;
1574 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1577 if (intr_status & EESR_TFE) {
1578 /* FIFO under flow */
1579 ndev->stats.tx_fifo_errors++;
1580 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1583 if (intr_status & EESR_RDE) {
1584 /* Receive Descriptor Empty int */
1585 ndev->stats.rx_over_errors++;
1586 netif_err(mdp, rx_err, ndev, "Receive Descriptor Empty\n");
1589 if (intr_status & EESR_RFE) {
1590 /* Receive FIFO Overflow int */
1591 ndev->stats.rx_fifo_errors++;
1592 netif_err(mdp, rx_err, ndev, "Receive FIFO Overflow\n");
1595 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1597 ndev->stats.tx_fifo_errors++;
1598 netif_err(mdp, tx_err, ndev, "Address Error\n");
1601 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1602 if (mdp->cd->no_ade)
1604 if (intr_status & mask) {
1606 u32 edtrr = sh_eth_read(ndev, EDTRR);
1609 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1610 intr_status, mdp->cur_tx, mdp->dirty_tx,
1611 (u32)ndev->state, edtrr);
1612 /* dirty buffer free */
1613 sh_eth_txfree(ndev);
1616 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1618 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1621 netif_wake_queue(ndev);
1625 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1627 struct net_device *ndev = netdev;
1628 struct sh_eth_private *mdp = netdev_priv(ndev);
1629 struct sh_eth_cpu_data *cd = mdp->cd;
1630 irqreturn_t ret = IRQ_NONE;
1631 unsigned long intr_status, intr_enable;
1633 spin_lock(&mdp->lock);
1635 /* Get interrupt status */
1636 intr_status = sh_eth_read(ndev, EESR);
1637 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1638 * enabled since it's the one that comes thru regardless of the mask,
1639 * and we need to fully handle it in sh_eth_error() in order to quench
1640 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1642 intr_enable = sh_eth_read(ndev, EESIPR);
1643 intr_status &= intr_enable | DMAC_M_ECI;
1644 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
1649 if (intr_status & EESR_RX_CHECK) {
1650 if (napi_schedule_prep(&mdp->napi)) {
1651 /* Mask Rx interrupts */
1652 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1654 __napi_schedule(&mdp->napi);
1657 "ignoring interrupt, status 0x%08lx, mask 0x%08lx.\n",
1658 intr_status, intr_enable);
1663 if (intr_status & cd->tx_check) {
1664 /* Clear Tx interrupts */
1665 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1667 sh_eth_txfree(ndev);
1668 netif_wake_queue(ndev);
1671 if (intr_status & cd->eesr_err_check) {
1672 /* Clear error interrupts */
1673 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1675 sh_eth_error(ndev, intr_status);
1679 spin_unlock(&mdp->lock);
1684 static int sh_eth_poll(struct napi_struct *napi, int budget)
1686 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1688 struct net_device *ndev = napi->dev;
1690 unsigned long intr_status;
1693 intr_status = sh_eth_read(ndev, EESR);
1694 if (!(intr_status & EESR_RX_CHECK))
1696 /* Clear Rx interrupts */
1697 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1699 if (sh_eth_rx(ndev, intr_status, "a))
1703 napi_complete(napi);
1705 /* Reenable Rx interrupts */
1706 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1708 return budget - quota;
1711 /* PHY state control function */
1712 static void sh_eth_adjust_link(struct net_device *ndev)
1714 struct sh_eth_private *mdp = netdev_priv(ndev);
1715 struct phy_device *phydev = mdp->phydev;
1719 if (phydev->duplex != mdp->duplex) {
1721 mdp->duplex = phydev->duplex;
1722 if (mdp->cd->set_duplex)
1723 mdp->cd->set_duplex(ndev);
1726 if (phydev->speed != mdp->speed) {
1728 mdp->speed = phydev->speed;
1729 if (mdp->cd->set_rate)
1730 mdp->cd->set_rate(ndev);
1734 sh_eth_read(ndev, ECMR) & ~ECMR_TXF,
1737 mdp->link = phydev->link;
1738 if (mdp->cd->no_psr || mdp->no_ether_link)
1739 sh_eth_rcv_snd_enable(ndev);
1741 } else if (mdp->link) {
1746 if (mdp->cd->no_psr || mdp->no_ether_link)
1747 sh_eth_rcv_snd_disable(ndev);
1750 if (new_state && netif_msg_link(mdp))
1751 phy_print_status(phydev);
1754 /* PHY init function */
1755 static int sh_eth_phy_init(struct net_device *ndev)
1757 struct device_node *np = ndev->dev.parent->of_node;
1758 struct sh_eth_private *mdp = netdev_priv(ndev);
1759 struct phy_device *phydev = NULL;
1765 /* Try connect to PHY */
1767 struct device_node *pn;
1769 pn = of_parse_phandle(np, "phy-handle", 0);
1770 phydev = of_phy_connect(ndev, pn,
1771 sh_eth_adjust_link, 0,
1772 mdp->phy_interface);
1775 phydev = ERR_PTR(-ENOENT);
1777 char phy_id[MII_BUS_ID_SIZE + 3];
1779 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1780 mdp->mii_bus->id, mdp->phy_id);
1782 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1783 mdp->phy_interface);
1786 if (IS_ERR(phydev)) {
1787 netdev_err(ndev, "failed to connect PHY\n");
1788 return PTR_ERR(phydev);
1791 netdev_info(ndev, "attached PHY %d (IRQ %d) to driver %s\n",
1792 phydev->addr, phydev->irq, phydev->drv->name);
1794 mdp->phydev = phydev;
1799 /* PHY control start function */
1800 static int sh_eth_phy_start(struct net_device *ndev)
1802 struct sh_eth_private *mdp = netdev_priv(ndev);
1805 ret = sh_eth_phy_init(ndev);
1809 phy_start(mdp->phydev);
1814 static int sh_eth_get_settings(struct net_device *ndev,
1815 struct ethtool_cmd *ecmd)
1817 struct sh_eth_private *mdp = netdev_priv(ndev);
1818 unsigned long flags;
1821 spin_lock_irqsave(&mdp->lock, flags);
1822 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1823 spin_unlock_irqrestore(&mdp->lock, flags);
1828 static int sh_eth_set_settings(struct net_device *ndev,
1829 struct ethtool_cmd *ecmd)
1831 struct sh_eth_private *mdp = netdev_priv(ndev);
1832 unsigned long flags;
1835 spin_lock_irqsave(&mdp->lock, flags);
1837 /* disable tx and rx */
1838 sh_eth_rcv_snd_disable(ndev);
1840 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1844 if (ecmd->duplex == DUPLEX_FULL)
1849 if (mdp->cd->set_duplex)
1850 mdp->cd->set_duplex(ndev);
1855 /* enable tx and rx */
1856 sh_eth_rcv_snd_enable(ndev);
1858 spin_unlock_irqrestore(&mdp->lock, flags);
1863 static int sh_eth_nway_reset(struct net_device *ndev)
1865 struct sh_eth_private *mdp = netdev_priv(ndev);
1866 unsigned long flags;
1869 spin_lock_irqsave(&mdp->lock, flags);
1870 ret = phy_start_aneg(mdp->phydev);
1871 spin_unlock_irqrestore(&mdp->lock, flags);
1876 static u32 sh_eth_get_msglevel(struct net_device *ndev)
1878 struct sh_eth_private *mdp = netdev_priv(ndev);
1879 return mdp->msg_enable;
1882 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1884 struct sh_eth_private *mdp = netdev_priv(ndev);
1885 mdp->msg_enable = value;
1888 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1889 "rx_current", "tx_current",
1890 "rx_dirty", "tx_dirty",
1892 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
1894 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1898 return SH_ETH_STATS_LEN;
1904 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1905 struct ethtool_stats *stats, u64 *data)
1907 struct sh_eth_private *mdp = netdev_priv(ndev);
1910 /* device-specific stats */
1911 data[i++] = mdp->cur_rx;
1912 data[i++] = mdp->cur_tx;
1913 data[i++] = mdp->dirty_rx;
1914 data[i++] = mdp->dirty_tx;
1917 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1919 switch (stringset) {
1921 memcpy(data, *sh_eth_gstrings_stats,
1922 sizeof(sh_eth_gstrings_stats));
1927 static void sh_eth_get_ringparam(struct net_device *ndev,
1928 struct ethtool_ringparam *ring)
1930 struct sh_eth_private *mdp = netdev_priv(ndev);
1932 ring->rx_max_pending = RX_RING_MAX;
1933 ring->tx_max_pending = TX_RING_MAX;
1934 ring->rx_pending = mdp->num_rx_ring;
1935 ring->tx_pending = mdp->num_tx_ring;
1938 static int sh_eth_set_ringparam(struct net_device *ndev,
1939 struct ethtool_ringparam *ring)
1941 struct sh_eth_private *mdp = netdev_priv(ndev);
1944 if (ring->tx_pending > TX_RING_MAX ||
1945 ring->rx_pending > RX_RING_MAX ||
1946 ring->tx_pending < TX_RING_MIN ||
1947 ring->rx_pending < RX_RING_MIN)
1949 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1952 if (netif_running(ndev)) {
1953 netif_tx_disable(ndev);
1954 /* Disable interrupts by clearing the interrupt mask. */
1955 sh_eth_write(ndev, 0x0000, EESIPR);
1956 /* Stop the chip's Tx and Rx processes. */
1957 sh_eth_write(ndev, 0, EDTRR);
1958 sh_eth_write(ndev, 0, EDRRR);
1959 synchronize_irq(ndev->irq);
1962 /* Free all the skbuffs in the Rx queue. */
1963 sh_eth_ring_free(ndev);
1964 /* Free DMA buffer */
1965 sh_eth_free_dma_buffer(mdp);
1967 /* Set new parameters */
1968 mdp->num_rx_ring = ring->rx_pending;
1969 mdp->num_tx_ring = ring->tx_pending;
1971 ret = sh_eth_ring_init(ndev);
1973 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n", __func__);
1976 ret = sh_eth_dev_init(ndev, false);
1978 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n", __func__);
1982 if (netif_running(ndev)) {
1983 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1984 /* Setting the Rx mode will start the Rx process. */
1985 sh_eth_write(ndev, EDRRR_R, EDRRR);
1986 netif_wake_queue(ndev);
1992 static const struct ethtool_ops sh_eth_ethtool_ops = {
1993 .get_settings = sh_eth_get_settings,
1994 .set_settings = sh_eth_set_settings,
1995 .nway_reset = sh_eth_nway_reset,
1996 .get_msglevel = sh_eth_get_msglevel,
1997 .set_msglevel = sh_eth_set_msglevel,
1998 .get_link = ethtool_op_get_link,
1999 .get_strings = sh_eth_get_strings,
2000 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2001 .get_sset_count = sh_eth_get_sset_count,
2002 .get_ringparam = sh_eth_get_ringparam,
2003 .set_ringparam = sh_eth_set_ringparam,
2006 /* network device open function */
2007 static int sh_eth_open(struct net_device *ndev)
2010 struct sh_eth_private *mdp = netdev_priv(ndev);
2012 pm_runtime_get_sync(&mdp->pdev->dev);
2014 napi_enable(&mdp->napi);
2016 ret = request_irq(ndev->irq, sh_eth_interrupt,
2017 mdp->cd->irq_flags, ndev->name, ndev);
2019 netdev_err(ndev, "Can not assign IRQ number\n");
2023 /* Descriptor set */
2024 ret = sh_eth_ring_init(ndev);
2029 ret = sh_eth_dev_init(ndev, true);
2033 /* PHY control start*/
2034 ret = sh_eth_phy_start(ndev);
2041 free_irq(ndev->irq, ndev);
2043 napi_disable(&mdp->napi);
2044 pm_runtime_put_sync(&mdp->pdev->dev);
2048 /* Timeout function */
2049 static void sh_eth_tx_timeout(struct net_device *ndev)
2051 struct sh_eth_private *mdp = netdev_priv(ndev);
2052 struct sh_eth_rxdesc *rxdesc;
2055 netif_stop_queue(ndev);
2057 netif_err(mdp, timer, ndev,
2058 "transmit timed out, status %8.8x, resetting...\n",
2059 (int)sh_eth_read(ndev, EESR));
2061 /* tx_errors count up */
2062 ndev->stats.tx_errors++;
2064 /* Free all the skbuffs in the Rx queue. */
2065 for (i = 0; i < mdp->num_rx_ring; i++) {
2066 rxdesc = &mdp->rx_ring[i];
2068 rxdesc->addr = 0xBADF00D0;
2069 if (mdp->rx_skbuff[i])
2070 dev_kfree_skb(mdp->rx_skbuff[i]);
2071 mdp->rx_skbuff[i] = NULL;
2073 for (i = 0; i < mdp->num_tx_ring; i++) {
2074 if (mdp->tx_skbuff[i])
2075 dev_kfree_skb(mdp->tx_skbuff[i]);
2076 mdp->tx_skbuff[i] = NULL;
2080 sh_eth_dev_init(ndev, true);
2083 /* Packet transmit function */
2084 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2086 struct sh_eth_private *mdp = netdev_priv(ndev);
2087 struct sh_eth_txdesc *txdesc;
2089 unsigned long flags;
2091 spin_lock_irqsave(&mdp->lock, flags);
2092 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2093 if (!sh_eth_txfree(ndev)) {
2094 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2095 netif_stop_queue(ndev);
2096 spin_unlock_irqrestore(&mdp->lock, flags);
2097 return NETDEV_TX_BUSY;
2100 spin_unlock_irqrestore(&mdp->lock, flags);
2102 entry = mdp->cur_tx % mdp->num_tx_ring;
2103 mdp->tx_skbuff[entry] = skb;
2104 txdesc = &mdp->tx_ring[entry];
2106 if (!mdp->cd->hw_swap)
2107 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
2109 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2111 if (skb->len < ETH_ZLEN)
2112 txdesc->buffer_length = ETH_ZLEN;
2114 txdesc->buffer_length = skb->len;
2116 if (entry >= mdp->num_tx_ring - 1)
2117 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
2119 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
2123 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2124 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2126 return NETDEV_TX_OK;
2129 /* device close function */
2130 static int sh_eth_close(struct net_device *ndev)
2132 struct sh_eth_private *mdp = netdev_priv(ndev);
2134 netif_stop_queue(ndev);
2136 /* Disable interrupts by clearing the interrupt mask. */
2137 sh_eth_write(ndev, 0x0000, EESIPR);
2139 /* Stop the chip's Tx and Rx processes. */
2140 sh_eth_write(ndev, 0, EDTRR);
2141 sh_eth_write(ndev, 0, EDRRR);
2143 /* PHY Disconnect */
2145 phy_stop(mdp->phydev);
2146 phy_disconnect(mdp->phydev);
2149 free_irq(ndev->irq, ndev);
2151 napi_disable(&mdp->napi);
2153 /* Free all the skbuffs in the Rx queue. */
2154 sh_eth_ring_free(ndev);
2156 /* free DMA buffer */
2157 sh_eth_free_dma_buffer(mdp);
2159 pm_runtime_put_sync(&mdp->pdev->dev);
2164 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2166 struct sh_eth_private *mdp = netdev_priv(ndev);
2168 if (sh_eth_is_rz_fast_ether(mdp))
2169 return &ndev->stats;
2171 pm_runtime_get_sync(&mdp->pdev->dev);
2173 ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
2174 sh_eth_write(ndev, 0, TROCR); /* (write clear) */
2175 ndev->stats.collisions += sh_eth_read(ndev, CDCR);
2176 sh_eth_write(ndev, 0, CDCR); /* (write clear) */
2177 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
2178 sh_eth_write(ndev, 0, LCCR); /* (write clear) */
2179 if (sh_eth_is_gether(mdp)) {
2180 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
2181 sh_eth_write(ndev, 0, CERCR); /* (write clear) */
2182 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
2183 sh_eth_write(ndev, 0, CEECR); /* (write clear) */
2185 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
2186 sh_eth_write(ndev, 0, CNDCR); /* (write clear) */
2188 pm_runtime_put_sync(&mdp->pdev->dev);
2190 return &ndev->stats;
2193 /* ioctl to device function */
2194 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2196 struct sh_eth_private *mdp = netdev_priv(ndev);
2197 struct phy_device *phydev = mdp->phydev;
2199 if (!netif_running(ndev))
2205 return phy_mii_ioctl(phydev, rq, cmd);
2208 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2209 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2212 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2215 static u32 sh_eth_tsu_get_post_mask(int entry)
2217 return 0x0f << (28 - ((entry % 8) * 4));
2220 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2222 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2225 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2228 struct sh_eth_private *mdp = netdev_priv(ndev);
2232 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2233 tmp = ioread32(reg_offset);
2234 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2237 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2240 struct sh_eth_private *mdp = netdev_priv(ndev);
2241 u32 post_mask, ref_mask, tmp;
2244 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2245 post_mask = sh_eth_tsu_get_post_mask(entry);
2246 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2248 tmp = ioread32(reg_offset);
2249 iowrite32(tmp & ~post_mask, reg_offset);
2251 /* If other port enables, the function returns "true" */
2252 return tmp & ref_mask;
2255 static int sh_eth_tsu_busy(struct net_device *ndev)
2257 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2258 struct sh_eth_private *mdp = netdev_priv(ndev);
2260 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2264 netdev_err(ndev, "%s: timeout\n", __func__);
2272 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2277 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2278 iowrite32(val, reg);
2279 if (sh_eth_tsu_busy(ndev) < 0)
2282 val = addr[4] << 8 | addr[5];
2283 iowrite32(val, reg + 4);
2284 if (sh_eth_tsu_busy(ndev) < 0)
2290 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2294 val = ioread32(reg);
2295 addr[0] = (val >> 24) & 0xff;
2296 addr[1] = (val >> 16) & 0xff;
2297 addr[2] = (val >> 8) & 0xff;
2298 addr[3] = val & 0xff;
2299 val = ioread32(reg + 4);
2300 addr[4] = (val >> 8) & 0xff;
2301 addr[5] = val & 0xff;
2305 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2307 struct sh_eth_private *mdp = netdev_priv(ndev);
2308 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2310 u8 c_addr[ETH_ALEN];
2312 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2313 sh_eth_tsu_read_entry(reg_offset, c_addr);
2314 if (ether_addr_equal(addr, c_addr))
2321 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2326 memset(blank, 0, sizeof(blank));
2327 entry = sh_eth_tsu_find_entry(ndev, blank);
2328 return (entry < 0) ? -ENOMEM : entry;
2331 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2334 struct sh_eth_private *mdp = netdev_priv(ndev);
2335 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2339 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2340 ~(1 << (31 - entry)), TSU_TEN);
2342 memset(blank, 0, sizeof(blank));
2343 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2349 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2351 struct sh_eth_private *mdp = netdev_priv(ndev);
2352 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2358 i = sh_eth_tsu_find_entry(ndev, addr);
2360 /* No entry found, create one */
2361 i = sh_eth_tsu_find_empty(ndev);
2364 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2368 /* Enable the entry */
2369 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2370 (1 << (31 - i)), TSU_TEN);
2373 /* Entry found or created, enable POST */
2374 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2379 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2381 struct sh_eth_private *mdp = netdev_priv(ndev);
2387 i = sh_eth_tsu_find_entry(ndev, addr);
2390 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2393 /* Disable the entry if both ports was disabled */
2394 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2402 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2404 struct sh_eth_private *mdp = netdev_priv(ndev);
2407 if (unlikely(!mdp->cd->tsu))
2410 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2411 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2414 /* Disable the entry if both ports was disabled */
2415 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2423 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2425 struct sh_eth_private *mdp = netdev_priv(ndev);
2427 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2430 if (unlikely(!mdp->cd->tsu))
2433 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2434 sh_eth_tsu_read_entry(reg_offset, addr);
2435 if (is_multicast_ether_addr(addr))
2436 sh_eth_tsu_del_entry(ndev, addr);
2440 /* Multicast reception directions set */
2441 static void sh_eth_set_multicast_list(struct net_device *ndev)
2443 struct sh_eth_private *mdp = netdev_priv(ndev);
2446 unsigned long flags;
2448 spin_lock_irqsave(&mdp->lock, flags);
2449 /* Initial condition is MCT = 1, PRM = 0.
2450 * Depending on ndev->flags, set PRM or clear MCT
2452 ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT;
2454 if (!(ndev->flags & IFF_MULTICAST)) {
2455 sh_eth_tsu_purge_mcast(ndev);
2458 if (ndev->flags & IFF_ALLMULTI) {
2459 sh_eth_tsu_purge_mcast(ndev);
2460 ecmr_bits &= ~ECMR_MCT;
2464 if (ndev->flags & IFF_PROMISC) {
2465 sh_eth_tsu_purge_all(ndev);
2466 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2467 } else if (mdp->cd->tsu) {
2468 struct netdev_hw_addr *ha;
2469 netdev_for_each_mc_addr(ha, ndev) {
2470 if (mcast_all && is_multicast_ether_addr(ha->addr))
2473 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2475 sh_eth_tsu_purge_mcast(ndev);
2476 ecmr_bits &= ~ECMR_MCT;
2482 /* Normal, unicast/broadcast-only mode. */
2483 ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT;
2486 /* update the ethernet mode */
2487 sh_eth_write(ndev, ecmr_bits, ECMR);
2489 spin_unlock_irqrestore(&mdp->lock, flags);
2492 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2500 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2501 __be16 proto, u16 vid)
2503 struct sh_eth_private *mdp = netdev_priv(ndev);
2504 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2506 if (unlikely(!mdp->cd->tsu))
2509 /* No filtering if vid = 0 */
2513 mdp->vlan_num_ids++;
2515 /* The controller has one VLAN tag HW filter. So, if the filter is
2516 * already enabled, the driver disables it and the filte
2518 if (mdp->vlan_num_ids > 1) {
2519 /* disable VLAN filter */
2520 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2524 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2530 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2531 __be16 proto, u16 vid)
2533 struct sh_eth_private *mdp = netdev_priv(ndev);
2534 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2536 if (unlikely(!mdp->cd->tsu))
2539 /* No filtering if vid = 0 */
2543 mdp->vlan_num_ids--;
2544 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2549 /* SuperH's TSU register init function */
2550 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2552 if (sh_eth_is_rz_fast_ether(mdp)) {
2553 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2557 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2558 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2559 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2560 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2561 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2562 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2563 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2564 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2565 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2566 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2567 if (sh_eth_is_gether(mdp)) {
2568 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2569 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2571 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2572 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2574 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2575 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2576 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2577 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2578 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2579 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2580 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
2583 /* MDIO bus release function */
2584 static int sh_mdio_release(struct sh_eth_private *mdp)
2586 /* unregister mdio bus */
2587 mdiobus_unregister(mdp->mii_bus);
2589 /* free bitbang info */
2590 free_mdio_bitbang(mdp->mii_bus);
2595 /* MDIO bus init function */
2596 static int sh_mdio_init(struct sh_eth_private *mdp,
2597 struct sh_eth_plat_data *pd)
2600 struct bb_info *bitbang;
2601 struct platform_device *pdev = mdp->pdev;
2602 struct device *dev = &mdp->pdev->dev;
2604 /* create bit control struct for PHY */
2605 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
2610 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2611 bitbang->set_gate = pd->set_mdio_gate;
2612 bitbang->mdi_msk = PIR_MDI;
2613 bitbang->mdo_msk = PIR_MDO;
2614 bitbang->mmd_msk = PIR_MMD;
2615 bitbang->mdc_msk = PIR_MDC;
2616 bitbang->ctrl.ops = &bb_ops;
2618 /* MII controller setting */
2619 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2623 /* Hook up MII support for ethtool */
2624 mdp->mii_bus->name = "sh_mii";
2625 mdp->mii_bus->parent = dev;
2626 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2627 pdev->name, pdev->id);
2630 mdp->mii_bus->irq = devm_kzalloc(dev, sizeof(int) * PHY_MAX_ADDR,
2632 if (!mdp->mii_bus->irq) {
2637 /* register MDIO bus */
2639 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
2641 for (i = 0; i < PHY_MAX_ADDR; i++)
2642 mdp->mii_bus->irq[i] = PHY_POLL;
2643 if (pd->phy_irq > 0)
2644 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2646 ret = mdiobus_register(mdp->mii_bus);
2655 free_mdio_bitbang(mdp->mii_bus);
2659 static const u16 *sh_eth_get_register_offset(int register_type)
2661 const u16 *reg_offset = NULL;
2663 switch (register_type) {
2664 case SH_ETH_REG_GIGABIT:
2665 reg_offset = sh_eth_offset_gigabit;
2667 case SH_ETH_REG_FAST_RZ:
2668 reg_offset = sh_eth_offset_fast_rz;
2670 case SH_ETH_REG_FAST_RCAR:
2671 reg_offset = sh_eth_offset_fast_rcar;
2673 case SH_ETH_REG_FAST_SH4:
2674 reg_offset = sh_eth_offset_fast_sh4;
2676 case SH_ETH_REG_FAST_SH3_SH2:
2677 reg_offset = sh_eth_offset_fast_sh3_sh2;
2686 static const struct net_device_ops sh_eth_netdev_ops = {
2687 .ndo_open = sh_eth_open,
2688 .ndo_stop = sh_eth_close,
2689 .ndo_start_xmit = sh_eth_start_xmit,
2690 .ndo_get_stats = sh_eth_get_stats,
2691 .ndo_tx_timeout = sh_eth_tx_timeout,
2692 .ndo_do_ioctl = sh_eth_do_ioctl,
2693 .ndo_validate_addr = eth_validate_addr,
2694 .ndo_set_mac_address = eth_mac_addr,
2695 .ndo_change_mtu = eth_change_mtu,
2698 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2699 .ndo_open = sh_eth_open,
2700 .ndo_stop = sh_eth_close,
2701 .ndo_start_xmit = sh_eth_start_xmit,
2702 .ndo_get_stats = sh_eth_get_stats,
2703 .ndo_set_rx_mode = sh_eth_set_multicast_list,
2704 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
2705 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
2706 .ndo_tx_timeout = sh_eth_tx_timeout,
2707 .ndo_do_ioctl = sh_eth_do_ioctl,
2708 .ndo_validate_addr = eth_validate_addr,
2709 .ndo_set_mac_address = eth_mac_addr,
2710 .ndo_change_mtu = eth_change_mtu,
2714 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2716 struct device_node *np = dev->of_node;
2717 struct sh_eth_plat_data *pdata;
2718 const char *mac_addr;
2720 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2724 pdata->phy_interface = of_get_phy_mode(np);
2726 mac_addr = of_get_mac_address(np);
2728 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
2730 pdata->no_ether_link =
2731 of_property_read_bool(np, "renesas,no-ether-link");
2732 pdata->ether_link_active_low =
2733 of_property_read_bool(np, "renesas,ether-link-active-low");
2738 static const struct of_device_id sh_eth_match_table[] = {
2739 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
2740 { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
2741 { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
2742 { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
2743 { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
2744 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
2747 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
2749 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2755 static int sh_eth_drv_probe(struct platform_device *pdev)
2758 struct resource *res;
2759 struct net_device *ndev = NULL;
2760 struct sh_eth_private *mdp = NULL;
2761 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
2762 const struct platform_device_id *id = platform_get_device_id(pdev);
2765 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2766 if (unlikely(res == NULL)) {
2767 dev_err(&pdev->dev, "invalid resource\n");
2771 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
2775 pm_runtime_enable(&pdev->dev);
2776 pm_runtime_get_sync(&pdev->dev);
2778 /* The sh Ether-specific entries in the device structure. */
2779 ndev->base_addr = res->start;
2785 ret = platform_get_irq(pdev, 0);
2792 SET_NETDEV_DEV(ndev, &pdev->dev);
2794 mdp = netdev_priv(ndev);
2795 mdp->num_tx_ring = TX_RING_SIZE;
2796 mdp->num_rx_ring = RX_RING_SIZE;
2797 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
2798 if (IS_ERR(mdp->addr)) {
2799 ret = PTR_ERR(mdp->addr);
2803 spin_lock_init(&mdp->lock);
2806 if (pdev->dev.of_node)
2807 pd = sh_eth_parse_dt(&pdev->dev);
2809 dev_err(&pdev->dev, "no platform data\n");
2815 mdp->phy_id = pd->phy;
2816 mdp->phy_interface = pd->phy_interface;
2818 mdp->edmac_endian = pd->edmac_endian;
2819 mdp->no_ether_link = pd->no_ether_link;
2820 mdp->ether_link_active_low = pd->ether_link_active_low;
2824 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
2826 const struct of_device_id *match;
2828 match = of_match_device(of_match_ptr(sh_eth_match_table),
2830 mdp->cd = (struct sh_eth_cpu_data *)match->data;
2832 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
2833 if (!mdp->reg_offset) {
2834 dev_err(&pdev->dev, "Unknown register type (%d)\n",
2835 mdp->cd->register_type);
2839 sh_eth_set_default_cpu_data(mdp->cd);
2843 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
2845 ndev->netdev_ops = &sh_eth_netdev_ops;
2846 SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
2847 ndev->watchdog_timeo = TX_TIMEOUT;
2849 /* debug message level */
2850 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
2852 /* read and set MAC address */
2853 read_mac_address(ndev, pd->mac_addr);
2854 if (!is_valid_ether_addr(ndev->dev_addr)) {
2855 dev_warn(&pdev->dev,
2856 "no valid MAC address supplied, using a random one.\n");
2857 eth_hw_addr_random(ndev);
2860 /* ioremap the TSU registers */
2862 struct resource *rtsu;
2863 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2864 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
2865 if (IS_ERR(mdp->tsu_addr)) {
2866 ret = PTR_ERR(mdp->tsu_addr);
2869 mdp->port = devno % 2;
2870 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
2873 /* initialize first or needed device */
2874 if (!devno || pd->needs_init) {
2875 if (mdp->cd->chip_reset)
2876 mdp->cd->chip_reset(ndev);
2879 /* TSU init (Init only)*/
2880 sh_eth_tsu_init(mdp);
2885 ret = sh_mdio_init(mdp, pd);
2887 dev_err(&ndev->dev, "failed to initialise MDIO\n");
2891 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
2893 /* network device register */
2894 ret = register_netdev(ndev);
2898 /* print device information */
2899 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
2900 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2902 pm_runtime_put(&pdev->dev);
2903 platform_set_drvdata(pdev, ndev);
2908 netif_napi_del(&mdp->napi);
2909 sh_mdio_release(mdp);
2916 pm_runtime_put(&pdev->dev);
2917 pm_runtime_disable(&pdev->dev);
2921 static int sh_eth_drv_remove(struct platform_device *pdev)
2923 struct net_device *ndev = platform_get_drvdata(pdev);
2924 struct sh_eth_private *mdp = netdev_priv(ndev);
2926 unregister_netdev(ndev);
2927 netif_napi_del(&mdp->napi);
2928 sh_mdio_release(mdp);
2929 pm_runtime_disable(&pdev->dev);
2936 static int sh_eth_runtime_nop(struct device *dev)
2938 /* Runtime PM callback shared between ->runtime_suspend()
2939 * and ->runtime_resume(). Simply returns success.
2941 * This driver re-initializes all registers after
2942 * pm_runtime_get_sync() anyway so there is no need
2943 * to save and restore registers here.
2948 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
2949 .runtime_suspend = sh_eth_runtime_nop,
2950 .runtime_resume = sh_eth_runtime_nop,
2952 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
2954 #define SH_ETH_PM_OPS NULL
2957 static struct platform_device_id sh_eth_id_table[] = {
2958 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
2959 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
2960 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
2961 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
2962 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
2963 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
2964 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
2965 { "r7s72100-ether", (kernel_ulong_t)&r7s72100_data },
2966 { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
2967 { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
2968 { "r8a7790-ether", (kernel_ulong_t)&r8a779x_data },
2969 { "r8a7791-ether", (kernel_ulong_t)&r8a779x_data },
2972 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
2974 static struct platform_driver sh_eth_driver = {
2975 .probe = sh_eth_drv_probe,
2976 .remove = sh_eth_drv_remove,
2977 .id_table = sh_eth_id_table,
2980 .pm = SH_ETH_PM_OPS,
2981 .of_match_table = of_match_ptr(sh_eth_match_table),
2985 module_platform_driver(sh_eth_driver);
2987 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
2988 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
2989 MODULE_LICENSE("GPL v2");