1 /* SuperH Ethernet device driver
3 * Copyright (C) 2014 Renesas Electronics Corporation
4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2014 Renesas Solutions Corp.
6 * Copyright (C) 2013-2014 Cogent Embedded, Inc.
7 * Copyright (C) 2014 Codethink Limited
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/spinlock.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/etherdevice.h>
28 #include <linux/delay.h>
29 #include <linux/platform_device.h>
30 #include <linux/mdio-bitbang.h>
31 #include <linux/netdevice.h>
33 #include <linux/of_device.h>
34 #include <linux/of_irq.h>
35 #include <linux/of_net.h>
36 #include <linux/phy.h>
37 #include <linux/cache.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/slab.h>
41 #include <linux/ethtool.h>
42 #include <linux/if_vlan.h>
43 #include <linux/clk.h>
44 #include <linux/sh_eth.h>
45 #include <linux/of_mdio.h>
49 #define SH_ETH_DEF_MSG_ENABLE \
55 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
109 [TSU_CTRST] = 0x0004,
110 [TSU_FWEN0] = 0x0010,
111 [TSU_FWEN1] = 0x0014,
113 [TSU_BSYSL0] = 0x0020,
114 [TSU_BSYSL1] = 0x0024,
115 [TSU_PRISL0] = 0x0028,
116 [TSU_PRISL1] = 0x002c,
117 [TSU_FWSL0] = 0x0030,
118 [TSU_FWSL1] = 0x0034,
119 [TSU_FWSLC] = 0x0038,
120 [TSU_QTAG0] = 0x0040,
121 [TSU_QTAG1] = 0x0044,
123 [TSU_FWINMK] = 0x0054,
124 [TSU_ADQT0] = 0x0048,
125 [TSU_ADQT1] = 0x004c,
126 [TSU_VTAG0] = 0x0058,
127 [TSU_VTAG1] = 0x005c,
128 [TSU_ADSBSY] = 0x0060,
130 [TSU_POST1] = 0x0070,
131 [TSU_POST2] = 0x0074,
132 [TSU_POST3] = 0x0078,
133 [TSU_POST4] = 0x007c,
134 [TSU_ADRH0] = 0x0100,
135 [TSU_ADRL0] = 0x0104,
136 [TSU_ADRH31] = 0x01f8,
137 [TSU_ADRL31] = 0x01fc,
153 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
197 [TSU_CTRST] = 0x0004,
198 [TSU_VTAG0] = 0x0058,
199 [TSU_ADSBSY] = 0x0060,
201 [TSU_ADRH0] = 0x0100,
202 [TSU_ADRL0] = 0x0104,
203 [TSU_ADRH31] = 0x01f8,
204 [TSU_ADRL31] = 0x01fc,
212 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
258 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
310 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
357 [TSU_CTRST] = 0x0004,
358 [TSU_FWEN0] = 0x0010,
359 [TSU_FWEN1] = 0x0014,
361 [TSU_BSYSL0] = 0x0020,
362 [TSU_BSYSL1] = 0x0024,
363 [TSU_PRISL0] = 0x0028,
364 [TSU_PRISL1] = 0x002c,
365 [TSU_FWSL0] = 0x0030,
366 [TSU_FWSL1] = 0x0034,
367 [TSU_FWSLC] = 0x0038,
368 [TSU_QTAGM0] = 0x0040,
369 [TSU_QTAGM1] = 0x0044,
370 [TSU_ADQT0] = 0x0048,
371 [TSU_ADQT1] = 0x004c,
373 [TSU_FWINMK] = 0x0054,
374 [TSU_ADSBSY] = 0x0060,
376 [TSU_POST1] = 0x0070,
377 [TSU_POST2] = 0x0074,
378 [TSU_POST3] = 0x0078,
379 [TSU_POST4] = 0x007c,
394 [TSU_ADRH0] = 0x0100,
395 [TSU_ADRL0] = 0x0104,
396 [TSU_ADRL31] = 0x01fc,
399 static bool sh_eth_is_gether(struct sh_eth_private *mdp)
401 return mdp->reg_offset == sh_eth_offset_gigabit;
404 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
406 return mdp->reg_offset == sh_eth_offset_fast_rz;
409 static void sh_eth_select_mii(struct net_device *ndev)
412 struct sh_eth_private *mdp = netdev_priv(ndev);
414 switch (mdp->phy_interface) {
415 case PHY_INTERFACE_MODE_GMII:
418 case PHY_INTERFACE_MODE_MII:
421 case PHY_INTERFACE_MODE_RMII:
426 "PHY interface mode was not setup. Set to MII.\n");
431 sh_eth_write(ndev, value, RMII_MII);
434 static void sh_eth_set_duplex(struct net_device *ndev)
436 struct sh_eth_private *mdp = netdev_priv(ndev);
438 if (mdp->duplex) /* Full */
439 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
441 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
444 /* There is CPU dependent code */
445 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
447 struct sh_eth_private *mdp = netdev_priv(ndev);
449 switch (mdp->speed) {
450 case 10: /* 10BASE */
451 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
453 case 100:/* 100BASE */
454 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
462 static struct sh_eth_cpu_data r8a777x_data = {
463 .set_duplex = sh_eth_set_duplex,
464 .set_rate = sh_eth_set_rate_r8a777x,
466 .register_type = SH_ETH_REG_FAST_RCAR,
468 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
469 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
470 .eesipr_value = 0x01ff009f,
472 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
473 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
474 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
484 static struct sh_eth_cpu_data r8a779x_data = {
485 .set_duplex = sh_eth_set_duplex,
486 .set_rate = sh_eth_set_rate_r8a777x,
488 .register_type = SH_ETH_REG_FAST_RCAR,
490 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
491 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
492 .eesipr_value = 0x01ff009f,
494 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
495 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
496 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
507 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
509 struct sh_eth_private *mdp = netdev_priv(ndev);
511 switch (mdp->speed) {
512 case 10: /* 10BASE */
513 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
515 case 100:/* 100BASE */
516 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
524 static struct sh_eth_cpu_data sh7724_data = {
525 .set_duplex = sh_eth_set_duplex,
526 .set_rate = sh_eth_set_rate_sh7724,
528 .register_type = SH_ETH_REG_FAST_SH4,
530 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
531 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
532 .eesipr_value = 0x01ff009f,
534 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
535 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
536 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
544 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
547 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
549 struct sh_eth_private *mdp = netdev_priv(ndev);
551 switch (mdp->speed) {
552 case 10: /* 10BASE */
553 sh_eth_write(ndev, 0, RTRATE);
555 case 100:/* 100BASE */
556 sh_eth_write(ndev, 1, RTRATE);
564 static struct sh_eth_cpu_data sh7757_data = {
565 .set_duplex = sh_eth_set_duplex,
566 .set_rate = sh_eth_set_rate_sh7757,
568 .register_type = SH_ETH_REG_FAST_SH4,
570 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
572 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
573 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
574 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
577 .irq_flags = IRQF_SHARED,
584 .rpadir_value = 2 << 16,
587 #define SH_GIGA_ETH_BASE 0xfee00000UL
588 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
589 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
590 static void sh_eth_chip_reset_giga(struct net_device *ndev)
593 unsigned long mahr[2], malr[2];
595 /* save MAHR and MALR */
596 for (i = 0; i < 2; i++) {
597 malr[i] = ioread32((void *)GIGA_MALR(i));
598 mahr[i] = ioread32((void *)GIGA_MAHR(i));
602 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
605 /* restore MAHR and MALR */
606 for (i = 0; i < 2; i++) {
607 iowrite32(malr[i], (void *)GIGA_MALR(i));
608 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
612 static void sh_eth_set_rate_giga(struct net_device *ndev)
614 struct sh_eth_private *mdp = netdev_priv(ndev);
616 switch (mdp->speed) {
617 case 10: /* 10BASE */
618 sh_eth_write(ndev, 0x00000000, GECMR);
620 case 100:/* 100BASE */
621 sh_eth_write(ndev, 0x00000010, GECMR);
623 case 1000: /* 1000BASE */
624 sh_eth_write(ndev, 0x00000020, GECMR);
631 /* SH7757(GETHERC) */
632 static struct sh_eth_cpu_data sh7757_data_giga = {
633 .chip_reset = sh_eth_chip_reset_giga,
634 .set_duplex = sh_eth_set_duplex,
635 .set_rate = sh_eth_set_rate_giga,
637 .register_type = SH_ETH_REG_GIGABIT,
639 .ecsr_value = ECSR_ICD | ECSR_MPD,
640 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
641 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
643 .tx_check = EESR_TC1 | EESR_FTC,
644 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
645 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
647 .fdr_value = 0x0000072f,
649 .irq_flags = IRQF_SHARED,
656 .rpadir_value = 2 << 16,
662 static void sh_eth_chip_reset(struct net_device *ndev)
664 struct sh_eth_private *mdp = netdev_priv(ndev);
667 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
671 static void sh_eth_set_rate_gether(struct net_device *ndev)
673 struct sh_eth_private *mdp = netdev_priv(ndev);
675 switch (mdp->speed) {
676 case 10: /* 10BASE */
677 sh_eth_write(ndev, GECMR_10, GECMR);
679 case 100:/* 100BASE */
680 sh_eth_write(ndev, GECMR_100, GECMR);
682 case 1000: /* 1000BASE */
683 sh_eth_write(ndev, GECMR_1000, GECMR);
691 static struct sh_eth_cpu_data sh7734_data = {
692 .chip_reset = sh_eth_chip_reset,
693 .set_duplex = sh_eth_set_duplex,
694 .set_rate = sh_eth_set_rate_gether,
696 .register_type = SH_ETH_REG_GIGABIT,
698 .ecsr_value = ECSR_ICD | ECSR_MPD,
699 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
700 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
702 .tx_check = EESR_TC1 | EESR_FTC,
703 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
704 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
720 static struct sh_eth_cpu_data sh7763_data = {
721 .chip_reset = sh_eth_chip_reset,
722 .set_duplex = sh_eth_set_duplex,
723 .set_rate = sh_eth_set_rate_gether,
725 .register_type = SH_ETH_REG_GIGABIT,
727 .ecsr_value = ECSR_ICD | ECSR_MPD,
728 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
729 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
731 .tx_check = EESR_TC1 | EESR_FTC,
732 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
733 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
744 .irq_flags = IRQF_SHARED,
747 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
749 struct sh_eth_private *mdp = netdev_priv(ndev);
752 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
755 sh_eth_select_mii(ndev);
759 static struct sh_eth_cpu_data r8a7740_data = {
760 .chip_reset = sh_eth_chip_reset_r8a7740,
761 .set_duplex = sh_eth_set_duplex,
762 .set_rate = sh_eth_set_rate_gether,
764 .register_type = SH_ETH_REG_GIGABIT,
766 .ecsr_value = ECSR_ICD | ECSR_MPD,
767 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
768 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
770 .tx_check = EESR_TC1 | EESR_FTC,
771 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
772 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
774 .fdr_value = 0x0000070f,
782 .rpadir_value = 2 << 16,
791 static struct sh_eth_cpu_data r7s72100_data = {
792 .chip_reset = sh_eth_chip_reset,
793 .set_duplex = sh_eth_set_duplex,
795 .register_type = SH_ETH_REG_FAST_RZ,
797 .ecsr_value = ECSR_ICD,
798 .ecsipr_value = ECSIPR_ICDIP,
799 .eesipr_value = 0xff7f009f,
801 .tx_check = EESR_TC1 | EESR_FTC,
802 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
803 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
805 .fdr_value = 0x0000070f,
813 .rpadir_value = 2 << 16,
821 static struct sh_eth_cpu_data sh7619_data = {
822 .register_type = SH_ETH_REG_FAST_SH3_SH2,
824 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
832 static struct sh_eth_cpu_data sh771x_data = {
833 .register_type = SH_ETH_REG_FAST_SH3_SH2,
835 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
839 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
842 cd->ecsr_value = DEFAULT_ECSR_INIT;
844 if (!cd->ecsipr_value)
845 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
847 if (!cd->fcftr_value)
848 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
849 DEFAULT_FIFO_F_D_RFD;
852 cd->fdr_value = DEFAULT_FDR_INIT;
855 cd->tx_check = DEFAULT_TX_CHECK;
857 if (!cd->eesr_err_check)
858 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
861 static int sh_eth_check_reset(struct net_device *ndev)
867 if (!(sh_eth_read(ndev, EDMR) & 0x3))
873 netdev_err(ndev, "Device reset failed\n");
879 static int sh_eth_reset(struct net_device *ndev)
881 struct sh_eth_private *mdp = netdev_priv(ndev);
884 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
885 sh_eth_write(ndev, EDSR_ENALL, EDSR);
886 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
889 ret = sh_eth_check_reset(ndev);
894 sh_eth_write(ndev, 0x0, TDLAR);
895 sh_eth_write(ndev, 0x0, TDFAR);
896 sh_eth_write(ndev, 0x0, TDFXR);
897 sh_eth_write(ndev, 0x0, TDFFR);
898 sh_eth_write(ndev, 0x0, RDLAR);
899 sh_eth_write(ndev, 0x0, RDFAR);
900 sh_eth_write(ndev, 0x0, RDFXR);
901 sh_eth_write(ndev, 0x0, RDFFR);
903 /* Reset HW CRC register */
905 sh_eth_write(ndev, 0x0, CSMR);
907 /* Select MII mode */
908 if (mdp->cd->select_mii)
909 sh_eth_select_mii(ndev);
911 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
914 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
921 static void sh_eth_set_receive_align(struct sk_buff *skb)
923 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
926 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
930 /* CPU <-> EDMAC endian convert */
931 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
933 switch (mdp->edmac_endian) {
934 case EDMAC_LITTLE_ENDIAN:
935 return cpu_to_le32(x);
936 case EDMAC_BIG_ENDIAN:
937 return cpu_to_be32(x);
942 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
944 switch (mdp->edmac_endian) {
945 case EDMAC_LITTLE_ENDIAN:
946 return le32_to_cpu(x);
947 case EDMAC_BIG_ENDIAN:
948 return be32_to_cpu(x);
953 /* Program the hardware MAC address from dev->dev_addr. */
954 static void update_mac_address(struct net_device *ndev)
957 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
958 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
960 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
963 /* Get MAC address from SuperH MAC address register
965 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
966 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
967 * When you want use this device, you must set MAC address in bootloader.
970 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
972 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
973 memcpy(ndev->dev_addr, mac, ETH_ALEN);
975 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
976 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
977 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
978 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
979 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
980 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
984 static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
986 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
987 return EDTRR_TRNS_GETHER;
989 return EDTRR_TRNS_ETHER;
993 void (*set_gate)(void *addr);
994 struct mdiobb_ctrl ctrl;
996 u32 mmd_msk;/* MMD */
1003 static void bb_set(void *addr, u32 msk)
1005 iowrite32(ioread32(addr) | msk, addr);
1009 static void bb_clr(void *addr, u32 msk)
1011 iowrite32((ioread32(addr) & ~msk), addr);
1015 static int bb_read(void *addr, u32 msk)
1017 return (ioread32(addr) & msk) != 0;
1020 /* Data I/O pin control */
1021 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1023 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1025 if (bitbang->set_gate)
1026 bitbang->set_gate(bitbang->addr);
1029 bb_set(bitbang->addr, bitbang->mmd_msk);
1031 bb_clr(bitbang->addr, bitbang->mmd_msk);
1035 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1037 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1039 if (bitbang->set_gate)
1040 bitbang->set_gate(bitbang->addr);
1043 bb_set(bitbang->addr, bitbang->mdo_msk);
1045 bb_clr(bitbang->addr, bitbang->mdo_msk);
1049 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1051 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1053 if (bitbang->set_gate)
1054 bitbang->set_gate(bitbang->addr);
1056 return bb_read(bitbang->addr, bitbang->mdi_msk);
1059 /* MDC pin control */
1060 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1062 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1064 if (bitbang->set_gate)
1065 bitbang->set_gate(bitbang->addr);
1068 bb_set(bitbang->addr, bitbang->mdc_msk);
1070 bb_clr(bitbang->addr, bitbang->mdc_msk);
1073 /* mdio bus control struct */
1074 static struct mdiobb_ops bb_ops = {
1075 .owner = THIS_MODULE,
1076 .set_mdc = sh_mdc_ctrl,
1077 .set_mdio_dir = sh_mmd_ctrl,
1078 .set_mdio_data = sh_set_mdio,
1079 .get_mdio_data = sh_get_mdio,
1082 /* free skb and descriptor buffer */
1083 static void sh_eth_ring_free(struct net_device *ndev)
1085 struct sh_eth_private *mdp = netdev_priv(ndev);
1088 /* Free Rx skb ringbuffer */
1089 if (mdp->rx_skbuff) {
1090 for (i = 0; i < mdp->num_rx_ring; i++)
1091 dev_kfree_skb(mdp->rx_skbuff[i]);
1093 kfree(mdp->rx_skbuff);
1094 mdp->rx_skbuff = NULL;
1096 /* Free Tx skb ringbuffer */
1097 if (mdp->tx_skbuff) {
1098 for (i = 0; i < mdp->num_tx_ring; i++)
1099 dev_kfree_skb(mdp->tx_skbuff[i]);
1101 kfree(mdp->tx_skbuff);
1102 mdp->tx_skbuff = NULL;
1105 /* format skb and descriptor buffer */
1106 static void sh_eth_ring_format(struct net_device *ndev)
1108 struct sh_eth_private *mdp = netdev_priv(ndev);
1110 struct sk_buff *skb;
1111 struct sh_eth_rxdesc *rxdesc = NULL;
1112 struct sh_eth_txdesc *txdesc = NULL;
1113 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1114 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1115 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN - 1;
1122 memset(mdp->rx_ring, 0, rx_ringsize);
1124 /* build Rx ring buffer */
1125 for (i = 0; i < mdp->num_rx_ring; i++) {
1127 mdp->rx_skbuff[i] = NULL;
1128 skb = netdev_alloc_skb(ndev, skbuff_size);
1129 mdp->rx_skbuff[i] = skb;
1132 sh_eth_set_receive_align(skb);
1135 rxdesc = &mdp->rx_ring[i];
1136 /* The size of the buffer is a multiple of 16 bytes. */
1137 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1138 dma_map_single(&ndev->dev, skb->data, rxdesc->buffer_length,
1140 rxdesc->addr = virt_to_phys(skb->data);
1141 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1143 /* Rx descriptor address set */
1145 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1146 if (sh_eth_is_gether(mdp) ||
1147 sh_eth_is_rz_fast_ether(mdp))
1148 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1152 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1154 /* Mark the last entry as wrapping the ring. */
1155 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
1157 memset(mdp->tx_ring, 0, tx_ringsize);
1159 /* build Tx ring buffer */
1160 for (i = 0; i < mdp->num_tx_ring; i++) {
1161 mdp->tx_skbuff[i] = NULL;
1162 txdesc = &mdp->tx_ring[i];
1163 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1164 txdesc->buffer_length = 0;
1166 /* Tx descriptor address set */
1167 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1168 if (sh_eth_is_gether(mdp) ||
1169 sh_eth_is_rz_fast_ether(mdp))
1170 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1174 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1177 /* Get skb and descriptor buffer */
1178 static int sh_eth_ring_init(struct net_device *ndev)
1180 struct sh_eth_private *mdp = netdev_priv(ndev);
1181 int rx_ringsize, tx_ringsize, ret = 0;
1183 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1184 * card needs room to do 8 byte alignment, +2 so we can reserve
1185 * the first 2 bytes, and +16 gets room for the status word from the
1188 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1189 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1190 if (mdp->cd->rpadir)
1191 mdp->rx_buf_sz += NET_IP_ALIGN;
1193 /* Allocate RX and TX skb rings */
1194 mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring,
1195 sizeof(*mdp->rx_skbuff), GFP_KERNEL);
1196 if (!mdp->rx_skbuff) {
1201 mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring,
1202 sizeof(*mdp->tx_skbuff), GFP_KERNEL);
1203 if (!mdp->tx_skbuff) {
1208 /* Allocate all Rx descriptors. */
1209 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1210 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1212 if (!mdp->rx_ring) {
1214 goto desc_ring_free;
1219 /* Allocate all Tx descriptors. */
1220 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1221 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1223 if (!mdp->tx_ring) {
1225 goto desc_ring_free;
1230 /* free DMA buffer */
1231 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1234 /* Free Rx and Tx skb ring buffer */
1235 sh_eth_ring_free(ndev);
1236 mdp->tx_ring = NULL;
1237 mdp->rx_ring = NULL;
1242 static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
1247 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1248 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1250 mdp->rx_ring = NULL;
1254 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1255 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1257 mdp->tx_ring = NULL;
1261 static int sh_eth_dev_init(struct net_device *ndev, bool start)
1264 struct sh_eth_private *mdp = netdev_priv(ndev);
1268 ret = sh_eth_reset(ndev);
1272 if (mdp->cd->rmiimode)
1273 sh_eth_write(ndev, 0x1, RMIIMODE);
1275 /* Descriptor format */
1276 sh_eth_ring_format(ndev);
1277 if (mdp->cd->rpadir)
1278 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1280 /* all sh_eth int mask */
1281 sh_eth_write(ndev, 0, EESIPR);
1283 #if defined(__LITTLE_ENDIAN)
1284 if (mdp->cd->hw_swap)
1285 sh_eth_write(ndev, EDMR_EL, EDMR);
1288 sh_eth_write(ndev, 0, EDMR);
1291 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1292 sh_eth_write(ndev, 0, TFTR);
1294 /* Frame recv control (enable multiple-packets per rx irq) */
1295 sh_eth_write(ndev, RMCR_RNC, RMCR);
1297 sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER);
1300 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
1302 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1304 if (!mdp->cd->no_trimd)
1305 sh_eth_write(ndev, 0, TRIMD);
1307 /* Recv frame limit set register */
1308 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1311 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
1313 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1315 /* PAUSE Prohibition */
1316 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
1317 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1319 sh_eth_write(ndev, val, ECMR);
1321 if (mdp->cd->set_rate)
1322 mdp->cd->set_rate(ndev);
1324 /* E-MAC Status Register clear */
1325 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1327 /* E-MAC Interrupt Enable register */
1329 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1331 /* Set MAC address */
1332 update_mac_address(ndev);
1336 sh_eth_write(ndev, APR_AP, APR);
1338 sh_eth_write(ndev, MPR_MP, MPR);
1339 if (mdp->cd->tpauser)
1340 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1343 /* Setting the Rx mode will start the Rx process. */
1344 sh_eth_write(ndev, EDRRR_R, EDRRR);
1346 netif_start_queue(ndev);
1352 /* free Tx skb function */
1353 static int sh_eth_txfree(struct net_device *ndev)
1355 struct sh_eth_private *mdp = netdev_priv(ndev);
1356 struct sh_eth_txdesc *txdesc;
1360 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1361 entry = mdp->dirty_tx % mdp->num_tx_ring;
1362 txdesc = &mdp->tx_ring[entry];
1363 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
1365 /* Free the original skb. */
1366 if (mdp->tx_skbuff[entry]) {
1367 dma_unmap_single(&ndev->dev, txdesc->addr,
1368 txdesc->buffer_length, DMA_TO_DEVICE);
1369 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1370 mdp->tx_skbuff[entry] = NULL;
1373 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1374 if (entry >= mdp->num_tx_ring - 1)
1375 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1377 ndev->stats.tx_packets++;
1378 ndev->stats.tx_bytes += txdesc->buffer_length;
1383 /* Packet receive function */
1384 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1386 struct sh_eth_private *mdp = netdev_priv(ndev);
1387 struct sh_eth_rxdesc *rxdesc;
1389 int entry = mdp->cur_rx % mdp->num_rx_ring;
1390 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1392 struct sk_buff *skb;
1395 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN - 1;
1397 boguscnt = min(boguscnt, *quota);
1399 rxdesc = &mdp->rx_ring[entry];
1400 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1401 desc_status = edmac_to_cpu(mdp, rxdesc->status);
1402 pkt_len = rxdesc->frame_length;
1407 if (!(desc_status & RDFEND))
1408 ndev->stats.rx_length_errors++;
1410 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1411 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1412 * bit 0. However, in case of the R8A7740, R8A779x, and
1413 * R7S72100 the RFS bits are from bit 25 to bit 16. So, the
1414 * driver needs right shifting by 16.
1416 if (mdp->cd->shift_rd0)
1419 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1420 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1421 ndev->stats.rx_errors++;
1422 if (desc_status & RD_RFS1)
1423 ndev->stats.rx_crc_errors++;
1424 if (desc_status & RD_RFS2)
1425 ndev->stats.rx_frame_errors++;
1426 if (desc_status & RD_RFS3)
1427 ndev->stats.rx_length_errors++;
1428 if (desc_status & RD_RFS4)
1429 ndev->stats.rx_length_errors++;
1430 if (desc_status & RD_RFS6)
1431 ndev->stats.rx_missed_errors++;
1432 if (desc_status & RD_RFS10)
1433 ndev->stats.rx_over_errors++;
1435 if (!mdp->cd->hw_swap)
1437 phys_to_virt(ALIGN(rxdesc->addr, 4)),
1439 skb = mdp->rx_skbuff[entry];
1440 mdp->rx_skbuff[entry] = NULL;
1441 if (mdp->cd->rpadir)
1442 skb_reserve(skb, NET_IP_ALIGN);
1443 dma_sync_single_for_cpu(&ndev->dev, rxdesc->addr,
1444 ALIGN(mdp->rx_buf_sz, 16),
1446 skb_put(skb, pkt_len);
1447 skb->protocol = eth_type_trans(skb, ndev);
1448 netif_receive_skb(skb);
1449 ndev->stats.rx_packets++;
1450 ndev->stats.rx_bytes += pkt_len;
1452 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1453 rxdesc = &mdp->rx_ring[entry];
1456 /* Refill the Rx ring buffers. */
1457 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1458 entry = mdp->dirty_rx % mdp->num_rx_ring;
1459 rxdesc = &mdp->rx_ring[entry];
1460 /* The size of the buffer is 16 byte boundary. */
1461 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1463 if (mdp->rx_skbuff[entry] == NULL) {
1464 skb = netdev_alloc_skb(ndev, skbuff_size);
1465 mdp->rx_skbuff[entry] = skb;
1467 break; /* Better luck next round. */
1468 sh_eth_set_receive_align(skb);
1469 dma_map_single(&ndev->dev, skb->data,
1470 rxdesc->buffer_length, DMA_FROM_DEVICE);
1472 skb_checksum_none_assert(skb);
1473 rxdesc->addr = virt_to_phys(skb->data);
1475 if (entry >= mdp->num_rx_ring - 1)
1477 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
1480 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1483 /* Restart Rx engine if stopped. */
1484 /* If we don't need to check status, don't. -KDU */
1485 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1486 /* fix the values for the next receiving if RDE is set */
1487 if (intr_status & EESR_RDE) {
1488 u32 count = (sh_eth_read(ndev, RDFAR) -
1489 sh_eth_read(ndev, RDLAR)) >> 4;
1491 mdp->cur_rx = count;
1492 mdp->dirty_rx = count;
1494 sh_eth_write(ndev, EDRRR_R, EDRRR);
1497 *quota -= limit - boguscnt - 1;
1502 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1504 /* disable tx and rx */
1505 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1506 ~(ECMR_RE | ECMR_TE), ECMR);
1509 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1511 /* enable tx and rx */
1512 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1513 (ECMR_RE | ECMR_TE), ECMR);
1516 /* error control function */
1517 static void sh_eth_error(struct net_device *ndev, int intr_status)
1519 struct sh_eth_private *mdp = netdev_priv(ndev);
1524 if (intr_status & EESR_ECI) {
1525 felic_stat = sh_eth_read(ndev, ECSR);
1526 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1527 if (felic_stat & ECSR_ICD)
1528 ndev->stats.tx_carrier_errors++;
1529 if (felic_stat & ECSR_LCHNG) {
1531 if (mdp->cd->no_psr || mdp->no_ether_link) {
1534 link_stat = (sh_eth_read(ndev, PSR));
1535 if (mdp->ether_link_active_low)
1536 link_stat = ~link_stat;
1538 if (!(link_stat & PHY_ST_LINK)) {
1539 sh_eth_rcv_snd_disable(ndev);
1542 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1543 ~DMAC_M_ECI, EESIPR);
1545 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1547 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1548 DMAC_M_ECI, EESIPR);
1549 /* enable tx and rx */
1550 sh_eth_rcv_snd_enable(ndev);
1556 if (intr_status & EESR_TWB) {
1557 /* Unused write back interrupt */
1558 if (intr_status & EESR_TABT) { /* Transmit Abort int */
1559 ndev->stats.tx_aborted_errors++;
1560 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1564 if (intr_status & EESR_RABT) {
1565 /* Receive Abort int */
1566 if (intr_status & EESR_RFRMER) {
1567 /* Receive Frame Overflow int */
1568 ndev->stats.rx_frame_errors++;
1569 netif_err(mdp, rx_err, ndev, "Receive Abort\n");
1573 if (intr_status & EESR_TDE) {
1574 /* Transmit Descriptor Empty int */
1575 ndev->stats.tx_fifo_errors++;
1576 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1579 if (intr_status & EESR_TFE) {
1580 /* FIFO under flow */
1581 ndev->stats.tx_fifo_errors++;
1582 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1585 if (intr_status & EESR_RDE) {
1586 /* Receive Descriptor Empty int */
1587 ndev->stats.rx_over_errors++;
1588 netif_err(mdp, rx_err, ndev, "Receive Descriptor Empty\n");
1591 if (intr_status & EESR_RFE) {
1592 /* Receive FIFO Overflow int */
1593 ndev->stats.rx_fifo_errors++;
1594 netif_err(mdp, rx_err, ndev, "Receive FIFO Overflow\n");
1597 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1599 ndev->stats.tx_fifo_errors++;
1600 netif_err(mdp, tx_err, ndev, "Address Error\n");
1603 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1604 if (mdp->cd->no_ade)
1606 if (intr_status & mask) {
1608 u32 edtrr = sh_eth_read(ndev, EDTRR);
1611 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1612 intr_status, mdp->cur_tx, mdp->dirty_tx,
1613 (u32)ndev->state, edtrr);
1614 /* dirty buffer free */
1615 sh_eth_txfree(ndev);
1618 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1620 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1623 netif_wake_queue(ndev);
1627 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1629 struct net_device *ndev = netdev;
1630 struct sh_eth_private *mdp = netdev_priv(ndev);
1631 struct sh_eth_cpu_data *cd = mdp->cd;
1632 irqreturn_t ret = IRQ_NONE;
1633 unsigned long intr_status, intr_enable;
1635 spin_lock(&mdp->lock);
1637 /* Get interrupt status */
1638 intr_status = sh_eth_read(ndev, EESR);
1639 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1640 * enabled since it's the one that comes thru regardless of the mask,
1641 * and we need to fully handle it in sh_eth_error() in order to quench
1642 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1644 intr_enable = sh_eth_read(ndev, EESIPR);
1645 intr_status &= intr_enable | DMAC_M_ECI;
1646 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
1651 if (intr_status & EESR_RX_CHECK) {
1652 if (napi_schedule_prep(&mdp->napi)) {
1653 /* Mask Rx interrupts */
1654 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1656 __napi_schedule(&mdp->napi);
1659 "ignoring interrupt, status 0x%08lx, mask 0x%08lx.\n",
1660 intr_status, intr_enable);
1665 if (intr_status & cd->tx_check) {
1666 /* Clear Tx interrupts */
1667 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1669 sh_eth_txfree(ndev);
1670 netif_wake_queue(ndev);
1673 if (intr_status & cd->eesr_err_check) {
1674 /* Clear error interrupts */
1675 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1677 sh_eth_error(ndev, intr_status);
1681 spin_unlock(&mdp->lock);
1686 static int sh_eth_poll(struct napi_struct *napi, int budget)
1688 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1690 struct net_device *ndev = napi->dev;
1692 unsigned long intr_status;
1695 intr_status = sh_eth_read(ndev, EESR);
1696 if (!(intr_status & EESR_RX_CHECK))
1698 /* Clear Rx interrupts */
1699 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1701 if (sh_eth_rx(ndev, intr_status, "a))
1705 napi_complete(napi);
1707 /* Reenable Rx interrupts */
1708 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1710 return budget - quota;
1713 /* PHY state control function */
1714 static void sh_eth_adjust_link(struct net_device *ndev)
1716 struct sh_eth_private *mdp = netdev_priv(ndev);
1717 struct phy_device *phydev = mdp->phydev;
1721 if (phydev->duplex != mdp->duplex) {
1723 mdp->duplex = phydev->duplex;
1724 if (mdp->cd->set_duplex)
1725 mdp->cd->set_duplex(ndev);
1728 if (phydev->speed != mdp->speed) {
1730 mdp->speed = phydev->speed;
1731 if (mdp->cd->set_rate)
1732 mdp->cd->set_rate(ndev);
1736 sh_eth_read(ndev, ECMR) & ~ECMR_TXF,
1739 mdp->link = phydev->link;
1740 if (mdp->cd->no_psr || mdp->no_ether_link)
1741 sh_eth_rcv_snd_enable(ndev);
1743 } else if (mdp->link) {
1748 if (mdp->cd->no_psr || mdp->no_ether_link)
1749 sh_eth_rcv_snd_disable(ndev);
1752 if (new_state && netif_msg_link(mdp))
1753 phy_print_status(phydev);
1756 /* PHY init function */
1757 static int sh_eth_phy_init(struct net_device *ndev)
1759 struct device_node *np = ndev->dev.parent->of_node;
1760 struct sh_eth_private *mdp = netdev_priv(ndev);
1761 struct phy_device *phydev = NULL;
1767 /* Try connect to PHY */
1769 struct device_node *pn;
1771 pn = of_parse_phandle(np, "phy-handle", 0);
1772 phydev = of_phy_connect(ndev, pn,
1773 sh_eth_adjust_link, 0,
1774 mdp->phy_interface);
1777 phydev = ERR_PTR(-ENOENT);
1779 char phy_id[MII_BUS_ID_SIZE + 3];
1781 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1782 mdp->mii_bus->id, mdp->phy_id);
1784 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1785 mdp->phy_interface);
1788 if (IS_ERR(phydev)) {
1789 netdev_err(ndev, "failed to connect PHY\n");
1790 return PTR_ERR(phydev);
1793 netdev_info(ndev, "attached PHY %d (IRQ %d) to driver %s\n",
1794 phydev->addr, phydev->irq, phydev->drv->name);
1796 mdp->phydev = phydev;
1801 /* PHY control start function */
1802 static int sh_eth_phy_start(struct net_device *ndev)
1804 struct sh_eth_private *mdp = netdev_priv(ndev);
1807 ret = sh_eth_phy_init(ndev);
1811 phy_start(mdp->phydev);
1816 static int sh_eth_get_settings(struct net_device *ndev,
1817 struct ethtool_cmd *ecmd)
1819 struct sh_eth_private *mdp = netdev_priv(ndev);
1820 unsigned long flags;
1823 spin_lock_irqsave(&mdp->lock, flags);
1824 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1825 spin_unlock_irqrestore(&mdp->lock, flags);
1830 static int sh_eth_set_settings(struct net_device *ndev,
1831 struct ethtool_cmd *ecmd)
1833 struct sh_eth_private *mdp = netdev_priv(ndev);
1834 unsigned long flags;
1837 spin_lock_irqsave(&mdp->lock, flags);
1839 /* disable tx and rx */
1840 sh_eth_rcv_snd_disable(ndev);
1842 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1846 if (ecmd->duplex == DUPLEX_FULL)
1851 if (mdp->cd->set_duplex)
1852 mdp->cd->set_duplex(ndev);
1857 /* enable tx and rx */
1858 sh_eth_rcv_snd_enable(ndev);
1860 spin_unlock_irqrestore(&mdp->lock, flags);
1865 static int sh_eth_nway_reset(struct net_device *ndev)
1867 struct sh_eth_private *mdp = netdev_priv(ndev);
1868 unsigned long flags;
1871 spin_lock_irqsave(&mdp->lock, flags);
1872 ret = phy_start_aneg(mdp->phydev);
1873 spin_unlock_irqrestore(&mdp->lock, flags);
1878 static u32 sh_eth_get_msglevel(struct net_device *ndev)
1880 struct sh_eth_private *mdp = netdev_priv(ndev);
1881 return mdp->msg_enable;
1884 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1886 struct sh_eth_private *mdp = netdev_priv(ndev);
1887 mdp->msg_enable = value;
1890 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1891 "rx_current", "tx_current",
1892 "rx_dirty", "tx_dirty",
1894 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
1896 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1900 return SH_ETH_STATS_LEN;
1906 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1907 struct ethtool_stats *stats, u64 *data)
1909 struct sh_eth_private *mdp = netdev_priv(ndev);
1912 /* device-specific stats */
1913 data[i++] = mdp->cur_rx;
1914 data[i++] = mdp->cur_tx;
1915 data[i++] = mdp->dirty_rx;
1916 data[i++] = mdp->dirty_tx;
1919 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1921 switch (stringset) {
1923 memcpy(data, *sh_eth_gstrings_stats,
1924 sizeof(sh_eth_gstrings_stats));
1929 static void sh_eth_get_ringparam(struct net_device *ndev,
1930 struct ethtool_ringparam *ring)
1932 struct sh_eth_private *mdp = netdev_priv(ndev);
1934 ring->rx_max_pending = RX_RING_MAX;
1935 ring->tx_max_pending = TX_RING_MAX;
1936 ring->rx_pending = mdp->num_rx_ring;
1937 ring->tx_pending = mdp->num_tx_ring;
1940 static int sh_eth_set_ringparam(struct net_device *ndev,
1941 struct ethtool_ringparam *ring)
1943 struct sh_eth_private *mdp = netdev_priv(ndev);
1946 if (ring->tx_pending > TX_RING_MAX ||
1947 ring->rx_pending > RX_RING_MAX ||
1948 ring->tx_pending < TX_RING_MIN ||
1949 ring->rx_pending < RX_RING_MIN)
1951 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1954 if (netif_running(ndev)) {
1955 netif_tx_disable(ndev);
1956 /* Disable interrupts by clearing the interrupt mask. */
1957 sh_eth_write(ndev, 0x0000, EESIPR);
1958 /* Stop the chip's Tx and Rx processes. */
1959 sh_eth_write(ndev, 0, EDTRR);
1960 sh_eth_write(ndev, 0, EDRRR);
1961 synchronize_irq(ndev->irq);
1964 /* Free all the skbuffs in the Rx queue. */
1965 sh_eth_ring_free(ndev);
1966 /* Free DMA buffer */
1967 sh_eth_free_dma_buffer(mdp);
1969 /* Set new parameters */
1970 mdp->num_rx_ring = ring->rx_pending;
1971 mdp->num_tx_ring = ring->tx_pending;
1973 ret = sh_eth_ring_init(ndev);
1975 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n", __func__);
1978 ret = sh_eth_dev_init(ndev, false);
1980 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n", __func__);
1984 if (netif_running(ndev)) {
1985 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1986 /* Setting the Rx mode will start the Rx process. */
1987 sh_eth_write(ndev, EDRRR_R, EDRRR);
1988 netif_wake_queue(ndev);
1994 static const struct ethtool_ops sh_eth_ethtool_ops = {
1995 .get_settings = sh_eth_get_settings,
1996 .set_settings = sh_eth_set_settings,
1997 .nway_reset = sh_eth_nway_reset,
1998 .get_msglevel = sh_eth_get_msglevel,
1999 .set_msglevel = sh_eth_set_msglevel,
2000 .get_link = ethtool_op_get_link,
2001 .get_strings = sh_eth_get_strings,
2002 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2003 .get_sset_count = sh_eth_get_sset_count,
2004 .get_ringparam = sh_eth_get_ringparam,
2005 .set_ringparam = sh_eth_set_ringparam,
2008 /* network device open function */
2009 static int sh_eth_open(struct net_device *ndev)
2012 struct sh_eth_private *mdp = netdev_priv(ndev);
2014 pm_runtime_get_sync(&mdp->pdev->dev);
2016 napi_enable(&mdp->napi);
2018 ret = request_irq(ndev->irq, sh_eth_interrupt,
2019 mdp->cd->irq_flags, ndev->name, ndev);
2021 netdev_err(ndev, "Can not assign IRQ number\n");
2025 /* Descriptor set */
2026 ret = sh_eth_ring_init(ndev);
2031 ret = sh_eth_dev_init(ndev, true);
2035 /* PHY control start*/
2036 ret = sh_eth_phy_start(ndev);
2045 free_irq(ndev->irq, ndev);
2047 napi_disable(&mdp->napi);
2048 pm_runtime_put_sync(&mdp->pdev->dev);
2052 /* Timeout function */
2053 static void sh_eth_tx_timeout(struct net_device *ndev)
2055 struct sh_eth_private *mdp = netdev_priv(ndev);
2056 struct sh_eth_rxdesc *rxdesc;
2059 netif_stop_queue(ndev);
2061 netif_err(mdp, timer, ndev,
2062 "transmit timed out, status %8.8x, resetting...\n",
2063 (int)sh_eth_read(ndev, EESR));
2065 /* tx_errors count up */
2066 ndev->stats.tx_errors++;
2068 /* Free all the skbuffs in the Rx queue. */
2069 for (i = 0; i < mdp->num_rx_ring; i++) {
2070 rxdesc = &mdp->rx_ring[i];
2072 rxdesc->addr = 0xBADF00D0;
2073 dev_kfree_skb(mdp->rx_skbuff[i]);
2074 mdp->rx_skbuff[i] = NULL;
2076 for (i = 0; i < mdp->num_tx_ring; i++) {
2077 dev_kfree_skb(mdp->tx_skbuff[i]);
2078 mdp->tx_skbuff[i] = NULL;
2082 sh_eth_dev_init(ndev, true);
2085 /* Packet transmit function */
2086 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2088 struct sh_eth_private *mdp = netdev_priv(ndev);
2089 struct sh_eth_txdesc *txdesc;
2091 unsigned long flags;
2093 spin_lock_irqsave(&mdp->lock, flags);
2094 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2095 if (!sh_eth_txfree(ndev)) {
2096 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2097 netif_stop_queue(ndev);
2098 spin_unlock_irqrestore(&mdp->lock, flags);
2099 return NETDEV_TX_BUSY;
2102 spin_unlock_irqrestore(&mdp->lock, flags);
2104 entry = mdp->cur_tx % mdp->num_tx_ring;
2105 mdp->tx_skbuff[entry] = skb;
2106 txdesc = &mdp->tx_ring[entry];
2108 if (!mdp->cd->hw_swap)
2109 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
2111 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2113 if (skb->len < ETH_ZLEN)
2114 txdesc->buffer_length = ETH_ZLEN;
2116 txdesc->buffer_length = skb->len;
2118 if (entry >= mdp->num_tx_ring - 1)
2119 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
2121 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
2125 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2126 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2128 return NETDEV_TX_OK;
2131 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2133 struct sh_eth_private *mdp = netdev_priv(ndev);
2135 if (sh_eth_is_rz_fast_ether(mdp))
2136 return &ndev->stats;
2138 if (!mdp->is_opened)
2139 return &ndev->stats;
2141 ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
2142 sh_eth_write(ndev, 0, TROCR); /* (write clear) */
2143 ndev->stats.collisions += sh_eth_read(ndev, CDCR);
2144 sh_eth_write(ndev, 0, CDCR); /* (write clear) */
2145 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
2146 sh_eth_write(ndev, 0, LCCR); /* (write clear) */
2148 if (sh_eth_is_gether(mdp)) {
2149 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
2150 sh_eth_write(ndev, 0, CERCR); /* (write clear) */
2151 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
2152 sh_eth_write(ndev, 0, CEECR); /* (write clear) */
2154 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
2155 sh_eth_write(ndev, 0, CNDCR); /* (write clear) */
2158 return &ndev->stats;
2161 /* device close function */
2162 static int sh_eth_close(struct net_device *ndev)
2164 struct sh_eth_private *mdp = netdev_priv(ndev);
2166 netif_stop_queue(ndev);
2168 /* Disable interrupts by clearing the interrupt mask. */
2169 sh_eth_write(ndev, 0x0000, EESIPR);
2171 /* Stop the chip's Tx and Rx processes. */
2172 sh_eth_write(ndev, 0, EDTRR);
2173 sh_eth_write(ndev, 0, EDRRR);
2175 sh_eth_get_stats(ndev);
2176 /* PHY Disconnect */
2178 phy_stop(mdp->phydev);
2179 phy_disconnect(mdp->phydev);
2182 free_irq(ndev->irq, ndev);
2184 napi_disable(&mdp->napi);
2186 /* Free all the skbuffs in the Rx queue. */
2187 sh_eth_ring_free(ndev);
2189 /* free DMA buffer */
2190 sh_eth_free_dma_buffer(mdp);
2192 pm_runtime_put_sync(&mdp->pdev->dev);
2199 /* ioctl to device function */
2200 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2202 struct sh_eth_private *mdp = netdev_priv(ndev);
2203 struct phy_device *phydev = mdp->phydev;
2205 if (!netif_running(ndev))
2211 return phy_mii_ioctl(phydev, rq, cmd);
2214 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2215 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2218 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2221 static u32 sh_eth_tsu_get_post_mask(int entry)
2223 return 0x0f << (28 - ((entry % 8) * 4));
2226 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2228 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2231 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2234 struct sh_eth_private *mdp = netdev_priv(ndev);
2238 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2239 tmp = ioread32(reg_offset);
2240 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2243 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2246 struct sh_eth_private *mdp = netdev_priv(ndev);
2247 u32 post_mask, ref_mask, tmp;
2250 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2251 post_mask = sh_eth_tsu_get_post_mask(entry);
2252 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2254 tmp = ioread32(reg_offset);
2255 iowrite32(tmp & ~post_mask, reg_offset);
2257 /* If other port enables, the function returns "true" */
2258 return tmp & ref_mask;
2261 static int sh_eth_tsu_busy(struct net_device *ndev)
2263 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2264 struct sh_eth_private *mdp = netdev_priv(ndev);
2266 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2270 netdev_err(ndev, "%s: timeout\n", __func__);
2278 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2283 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2284 iowrite32(val, reg);
2285 if (sh_eth_tsu_busy(ndev) < 0)
2288 val = addr[4] << 8 | addr[5];
2289 iowrite32(val, reg + 4);
2290 if (sh_eth_tsu_busy(ndev) < 0)
2296 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2300 val = ioread32(reg);
2301 addr[0] = (val >> 24) & 0xff;
2302 addr[1] = (val >> 16) & 0xff;
2303 addr[2] = (val >> 8) & 0xff;
2304 addr[3] = val & 0xff;
2305 val = ioread32(reg + 4);
2306 addr[4] = (val >> 8) & 0xff;
2307 addr[5] = val & 0xff;
2311 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2313 struct sh_eth_private *mdp = netdev_priv(ndev);
2314 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2316 u8 c_addr[ETH_ALEN];
2318 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2319 sh_eth_tsu_read_entry(reg_offset, c_addr);
2320 if (ether_addr_equal(addr, c_addr))
2327 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2332 memset(blank, 0, sizeof(blank));
2333 entry = sh_eth_tsu_find_entry(ndev, blank);
2334 return (entry < 0) ? -ENOMEM : entry;
2337 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2340 struct sh_eth_private *mdp = netdev_priv(ndev);
2341 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2345 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2346 ~(1 << (31 - entry)), TSU_TEN);
2348 memset(blank, 0, sizeof(blank));
2349 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2355 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2357 struct sh_eth_private *mdp = netdev_priv(ndev);
2358 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2364 i = sh_eth_tsu_find_entry(ndev, addr);
2366 /* No entry found, create one */
2367 i = sh_eth_tsu_find_empty(ndev);
2370 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2374 /* Enable the entry */
2375 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2376 (1 << (31 - i)), TSU_TEN);
2379 /* Entry found or created, enable POST */
2380 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2385 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2387 struct sh_eth_private *mdp = netdev_priv(ndev);
2393 i = sh_eth_tsu_find_entry(ndev, addr);
2396 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2399 /* Disable the entry if both ports was disabled */
2400 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2408 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2410 struct sh_eth_private *mdp = netdev_priv(ndev);
2413 if (unlikely(!mdp->cd->tsu))
2416 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2417 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2420 /* Disable the entry if both ports was disabled */
2421 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2429 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2431 struct sh_eth_private *mdp = netdev_priv(ndev);
2433 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2436 if (unlikely(!mdp->cd->tsu))
2439 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2440 sh_eth_tsu_read_entry(reg_offset, addr);
2441 if (is_multicast_ether_addr(addr))
2442 sh_eth_tsu_del_entry(ndev, addr);
2446 /* Multicast reception directions set */
2447 static void sh_eth_set_multicast_list(struct net_device *ndev)
2449 struct sh_eth_private *mdp = netdev_priv(ndev);
2452 unsigned long flags;
2454 spin_lock_irqsave(&mdp->lock, flags);
2455 /* Initial condition is MCT = 1, PRM = 0.
2456 * Depending on ndev->flags, set PRM or clear MCT
2458 ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT;
2460 if (!(ndev->flags & IFF_MULTICAST)) {
2461 sh_eth_tsu_purge_mcast(ndev);
2464 if (ndev->flags & IFF_ALLMULTI) {
2465 sh_eth_tsu_purge_mcast(ndev);
2466 ecmr_bits &= ~ECMR_MCT;
2470 if (ndev->flags & IFF_PROMISC) {
2471 sh_eth_tsu_purge_all(ndev);
2472 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2473 } else if (mdp->cd->tsu) {
2474 struct netdev_hw_addr *ha;
2475 netdev_for_each_mc_addr(ha, ndev) {
2476 if (mcast_all && is_multicast_ether_addr(ha->addr))
2479 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2481 sh_eth_tsu_purge_mcast(ndev);
2482 ecmr_bits &= ~ECMR_MCT;
2488 /* Normal, unicast/broadcast-only mode. */
2489 ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT;
2492 /* update the ethernet mode */
2493 sh_eth_write(ndev, ecmr_bits, ECMR);
2495 spin_unlock_irqrestore(&mdp->lock, flags);
2498 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2506 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2507 __be16 proto, u16 vid)
2509 struct sh_eth_private *mdp = netdev_priv(ndev);
2510 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2512 if (unlikely(!mdp->cd->tsu))
2515 /* No filtering if vid = 0 */
2519 mdp->vlan_num_ids++;
2521 /* The controller has one VLAN tag HW filter. So, if the filter is
2522 * already enabled, the driver disables it and the filte
2524 if (mdp->vlan_num_ids > 1) {
2525 /* disable VLAN filter */
2526 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2530 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2536 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2537 __be16 proto, u16 vid)
2539 struct sh_eth_private *mdp = netdev_priv(ndev);
2540 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2542 if (unlikely(!mdp->cd->tsu))
2545 /* No filtering if vid = 0 */
2549 mdp->vlan_num_ids--;
2550 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2555 /* SuperH's TSU register init function */
2556 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2558 if (sh_eth_is_rz_fast_ether(mdp)) {
2559 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2563 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2564 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2565 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2566 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2567 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2568 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2569 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2570 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2571 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2572 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2573 if (sh_eth_is_gether(mdp)) {
2574 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2575 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2577 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2578 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2580 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2581 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2582 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2583 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2584 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2585 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2586 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
2589 /* MDIO bus release function */
2590 static int sh_mdio_release(struct sh_eth_private *mdp)
2592 /* unregister mdio bus */
2593 mdiobus_unregister(mdp->mii_bus);
2595 /* free bitbang info */
2596 free_mdio_bitbang(mdp->mii_bus);
2601 /* MDIO bus init function */
2602 static int sh_mdio_init(struct sh_eth_private *mdp,
2603 struct sh_eth_plat_data *pd)
2606 struct bb_info *bitbang;
2607 struct platform_device *pdev = mdp->pdev;
2608 struct device *dev = &mdp->pdev->dev;
2610 /* create bit control struct for PHY */
2611 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
2616 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2617 bitbang->set_gate = pd->set_mdio_gate;
2618 bitbang->mdi_msk = PIR_MDI;
2619 bitbang->mdo_msk = PIR_MDO;
2620 bitbang->mmd_msk = PIR_MMD;
2621 bitbang->mdc_msk = PIR_MDC;
2622 bitbang->ctrl.ops = &bb_ops;
2624 /* MII controller setting */
2625 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2629 /* Hook up MII support for ethtool */
2630 mdp->mii_bus->name = "sh_mii";
2631 mdp->mii_bus->parent = dev;
2632 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2633 pdev->name, pdev->id);
2636 mdp->mii_bus->irq = devm_kmalloc_array(dev, PHY_MAX_ADDR, sizeof(int),
2638 if (!mdp->mii_bus->irq) {
2643 /* register MDIO bus */
2645 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
2647 for (i = 0; i < PHY_MAX_ADDR; i++)
2648 mdp->mii_bus->irq[i] = PHY_POLL;
2649 if (pd->phy_irq > 0)
2650 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2652 ret = mdiobus_register(mdp->mii_bus);
2661 free_mdio_bitbang(mdp->mii_bus);
2665 static const u16 *sh_eth_get_register_offset(int register_type)
2667 const u16 *reg_offset = NULL;
2669 switch (register_type) {
2670 case SH_ETH_REG_GIGABIT:
2671 reg_offset = sh_eth_offset_gigabit;
2673 case SH_ETH_REG_FAST_RZ:
2674 reg_offset = sh_eth_offset_fast_rz;
2676 case SH_ETH_REG_FAST_RCAR:
2677 reg_offset = sh_eth_offset_fast_rcar;
2679 case SH_ETH_REG_FAST_SH4:
2680 reg_offset = sh_eth_offset_fast_sh4;
2682 case SH_ETH_REG_FAST_SH3_SH2:
2683 reg_offset = sh_eth_offset_fast_sh3_sh2;
2692 static const struct net_device_ops sh_eth_netdev_ops = {
2693 .ndo_open = sh_eth_open,
2694 .ndo_stop = sh_eth_close,
2695 .ndo_start_xmit = sh_eth_start_xmit,
2696 .ndo_get_stats = sh_eth_get_stats,
2697 .ndo_tx_timeout = sh_eth_tx_timeout,
2698 .ndo_do_ioctl = sh_eth_do_ioctl,
2699 .ndo_validate_addr = eth_validate_addr,
2700 .ndo_set_mac_address = eth_mac_addr,
2701 .ndo_change_mtu = eth_change_mtu,
2704 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2705 .ndo_open = sh_eth_open,
2706 .ndo_stop = sh_eth_close,
2707 .ndo_start_xmit = sh_eth_start_xmit,
2708 .ndo_get_stats = sh_eth_get_stats,
2709 .ndo_set_rx_mode = sh_eth_set_multicast_list,
2710 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
2711 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
2712 .ndo_tx_timeout = sh_eth_tx_timeout,
2713 .ndo_do_ioctl = sh_eth_do_ioctl,
2714 .ndo_validate_addr = eth_validate_addr,
2715 .ndo_set_mac_address = eth_mac_addr,
2716 .ndo_change_mtu = eth_change_mtu,
2720 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2722 struct device_node *np = dev->of_node;
2723 struct sh_eth_plat_data *pdata;
2724 const char *mac_addr;
2726 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2730 pdata->phy_interface = of_get_phy_mode(np);
2732 mac_addr = of_get_mac_address(np);
2734 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
2736 pdata->no_ether_link =
2737 of_property_read_bool(np, "renesas,no-ether-link");
2738 pdata->ether_link_active_low =
2739 of_property_read_bool(np, "renesas,ether-link-active-low");
2744 static const struct of_device_id sh_eth_match_table[] = {
2745 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
2746 { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
2747 { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
2748 { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
2749 { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
2750 { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
2751 { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
2752 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
2755 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
2757 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2763 static int sh_eth_drv_probe(struct platform_device *pdev)
2766 struct resource *res;
2767 struct net_device *ndev = NULL;
2768 struct sh_eth_private *mdp = NULL;
2769 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
2770 const struct platform_device_id *id = platform_get_device_id(pdev);
2773 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2775 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
2779 pm_runtime_enable(&pdev->dev);
2780 pm_runtime_get_sync(&pdev->dev);
2787 ret = platform_get_irq(pdev, 0);
2794 SET_NETDEV_DEV(ndev, &pdev->dev);
2796 mdp = netdev_priv(ndev);
2797 mdp->num_tx_ring = TX_RING_SIZE;
2798 mdp->num_rx_ring = RX_RING_SIZE;
2799 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
2800 if (IS_ERR(mdp->addr)) {
2801 ret = PTR_ERR(mdp->addr);
2805 ndev->base_addr = res->start;
2807 spin_lock_init(&mdp->lock);
2810 if (pdev->dev.of_node)
2811 pd = sh_eth_parse_dt(&pdev->dev);
2813 dev_err(&pdev->dev, "no platform data\n");
2819 mdp->phy_id = pd->phy;
2820 mdp->phy_interface = pd->phy_interface;
2822 mdp->edmac_endian = pd->edmac_endian;
2823 mdp->no_ether_link = pd->no_ether_link;
2824 mdp->ether_link_active_low = pd->ether_link_active_low;
2828 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
2830 const struct of_device_id *match;
2832 match = of_match_device(of_match_ptr(sh_eth_match_table),
2834 mdp->cd = (struct sh_eth_cpu_data *)match->data;
2836 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
2837 if (!mdp->reg_offset) {
2838 dev_err(&pdev->dev, "Unknown register type (%d)\n",
2839 mdp->cd->register_type);
2843 sh_eth_set_default_cpu_data(mdp->cd);
2847 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
2849 ndev->netdev_ops = &sh_eth_netdev_ops;
2850 ndev->ethtool_ops = &sh_eth_ethtool_ops;
2851 ndev->watchdog_timeo = TX_TIMEOUT;
2853 /* debug message level */
2854 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
2856 /* read and set MAC address */
2857 read_mac_address(ndev, pd->mac_addr);
2858 if (!is_valid_ether_addr(ndev->dev_addr)) {
2859 dev_warn(&pdev->dev,
2860 "no valid MAC address supplied, using a random one.\n");
2861 eth_hw_addr_random(ndev);
2864 /* ioremap the TSU registers */
2866 struct resource *rtsu;
2867 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2868 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
2869 if (IS_ERR(mdp->tsu_addr)) {
2870 ret = PTR_ERR(mdp->tsu_addr);
2873 mdp->port = devno % 2;
2874 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
2877 /* initialize first or needed device */
2878 if (!devno || pd->needs_init) {
2879 if (mdp->cd->chip_reset)
2880 mdp->cd->chip_reset(ndev);
2883 /* TSU init (Init only)*/
2884 sh_eth_tsu_init(mdp);
2888 if (mdp->cd->rmiimode)
2889 sh_eth_write(ndev, 0x1, RMIIMODE);
2892 ret = sh_mdio_init(mdp, pd);
2894 dev_err(&ndev->dev, "failed to initialise MDIO\n");
2898 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
2900 /* network device register */
2901 ret = register_netdev(ndev);
2905 /* print device information */
2906 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
2907 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2909 pm_runtime_put(&pdev->dev);
2910 platform_set_drvdata(pdev, ndev);
2915 netif_napi_del(&mdp->napi);
2916 sh_mdio_release(mdp);
2923 pm_runtime_put(&pdev->dev);
2924 pm_runtime_disable(&pdev->dev);
2928 static int sh_eth_drv_remove(struct platform_device *pdev)
2930 struct net_device *ndev = platform_get_drvdata(pdev);
2931 struct sh_eth_private *mdp = netdev_priv(ndev);
2933 unregister_netdev(ndev);
2934 netif_napi_del(&mdp->napi);
2935 sh_mdio_release(mdp);
2936 pm_runtime_disable(&pdev->dev);
2943 static int sh_eth_runtime_nop(struct device *dev)
2945 /* Runtime PM callback shared between ->runtime_suspend()
2946 * and ->runtime_resume(). Simply returns success.
2948 * This driver re-initializes all registers after
2949 * pm_runtime_get_sync() anyway so there is no need
2950 * to save and restore registers here.
2955 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
2956 .runtime_suspend = sh_eth_runtime_nop,
2957 .runtime_resume = sh_eth_runtime_nop,
2959 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
2961 #define SH_ETH_PM_OPS NULL
2964 static struct platform_device_id sh_eth_id_table[] = {
2965 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
2966 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
2967 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
2968 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
2969 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
2970 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
2971 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
2972 { "r7s72100-ether", (kernel_ulong_t)&r7s72100_data },
2973 { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
2974 { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
2975 { "r8a7790-ether", (kernel_ulong_t)&r8a779x_data },
2976 { "r8a7791-ether", (kernel_ulong_t)&r8a779x_data },
2977 { "r8a7793-ether", (kernel_ulong_t)&r8a779x_data },
2978 { "r8a7794-ether", (kernel_ulong_t)&r8a779x_data },
2981 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
2983 static struct platform_driver sh_eth_driver = {
2984 .probe = sh_eth_drv_probe,
2985 .remove = sh_eth_drv_remove,
2986 .id_table = sh_eth_id_table,
2989 .pm = SH_ETH_PM_OPS,
2990 .of_match_table = of_match_ptr(sh_eth_match_table),
2994 module_platform_driver(sh_eth_driver);
2996 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
2997 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
2998 MODULE_LICENSE("GPL v2");