drivers/net/ethernet/renesas/sh_eth.c

   1 /*  SuperH Ethernet device driver
   2  *
   3  *  Copyright (C) 2014  Renesas Electronics Corporation
   4  *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
   5  *  Copyright (C) 2008-2014 Renesas Solutions Corp.
   6  *  Copyright (C) 2013-2016 Cogent Embedded, Inc.
   7  *  Copyright (C) 2014 Codethink Limited
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms and conditions of the GNU General Public License,
  11  *  version 2, as published by the Free Software Foundation.
  12  *
  13  *  This program is distributed in the hope it will be useful, but WITHOUT
  14  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  16  *  more details.
  17  *
  18  *  The full GNU General Public License is included in this distribution in
  19  *  the file called "COPYING".
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/etherdevice.h>
  28 #include <linux/delay.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/mdio-bitbang.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/of.h>
  33 #include <linux/of_device.h>
  34 #include <linux/of_irq.h>
  35 #include <linux/of_net.h>
  36 #include <linux/phy.h>
  37 #include <linux/cache.h>
  38 #include <linux/io.h>
  39 #include <linux/pm_runtime.h>
  40 #include <linux/slab.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/clk.h>
  44 #include <linux/sh_eth.h>
  45 #include <linux/of_mdio.h>
  46
  47 #include "sh_eth.h"
  48
  49 #define SH_ETH_DEF_MSG_ENABLE \
  50                 (NETIF_MSG_LINK | \
  51                 NETIF_MSG_TIMER | \
  52                 NETIF_MSG_RX_ERR| \
  53                 NETIF_MSG_TX_ERR)
  54
  55 #define SH_ETH_OFFSET_INVALID   ((u16)~0)
  56
  57 #define SH_ETH_OFFSET_DEFAULTS                  \
  58         [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
  59
  60 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
  61         SH_ETH_OFFSET_DEFAULTS,
  62
  63         [EDSR]          = 0x0000,
  64         [EDMR]          = 0x0400,
  65         [EDTRR]         = 0x0408,
  66         [EDRRR]         = 0x0410,
  67         [EESR]          = 0x0428,
  68         [EESIPR]        = 0x0430,
  69         [TDLAR]         = 0x0010,
  70         [TDFAR]         = 0x0014,
  71         [TDFXR]         = 0x0018,
  72         [TDFFR]         = 0x001c,
  73         [RDLAR]         = 0x0030,
  74         [RDFAR]         = 0x0034,
  75         [RDFXR]         = 0x0038,
  76         [RDFFR]         = 0x003c,
  77         [TRSCER]        = 0x0438,
  78         [RMFCR]         = 0x0440,
  79         [TFTR]          = 0x0448,
  80         [FDR]           = 0x0450,
  81         [RMCR]          = 0x0458,
  82         [RPADIR]        = 0x0460,
  83         [FCFTR]         = 0x0468,
  84         [CSMR]          = 0x04E4,
  85
  86         [ECMR]          = 0x0500,
  87         [ECSR]          = 0x0510,
  88         [ECSIPR]        = 0x0518,
  89         [PIR]           = 0x0520,
  90         [PSR]           = 0x0528,
  91         [PIPR]          = 0x052c,
  92         [RFLR]          = 0x0508,
  93         [APR]           = 0x0554,
  94         [MPR]           = 0x0558,
  95         [PFTCR]         = 0x055c,
  96         [PFRCR]         = 0x0560,
  97         [TPAUSER]       = 0x0564,
  98         [GECMR]         = 0x05b0,
  99         [BCULR]         = 0x05b4,
 100         [MAHR]          = 0x05c0,
 101         [MALR]          = 0x05c8,
 102         [TROCR]         = 0x0700,
 103         [CDCR]          = 0x0708,
 104         [LCCR]          = 0x0710,
 105         [CEFCR]         = 0x0740,
 106         [FRECR]         = 0x0748,
 107         [TSFRCR]        = 0x0750,
 108         [TLFRCR]        = 0x0758,
 109         [RFCR]          = 0x0760,
 110         [CERCR]         = 0x0768,
 111         [CEECR]         = 0x0770,
 112         [MAFCR]         = 0x0778,
 113         [RMII_MII]      = 0x0790,
 114
 115         [ARSTR]         = 0x0000,
 116         [TSU_CTRST]     = 0x0004,
 117         [TSU_FWEN0]     = 0x0010,
 118         [TSU_FWEN1]     = 0x0014,
 119         [TSU_FCM]       = 0x0018,
 120         [TSU_BSYSL0]    = 0x0020,
 121         [TSU_BSYSL1]    = 0x0024,
 122         [TSU_PRISL0]    = 0x0028,
 123         [TSU_PRISL1]    = 0x002c,
 124         [TSU_FWSL0]     = 0x0030,
 125         [TSU_FWSL1]     = 0x0034,
 126         [TSU_FWSLC]     = 0x0038,
 127         [TSU_QTAG0]     = 0x0040,
 128         [TSU_QTAG1]     = 0x0044,
 129         [TSU_FWSR]      = 0x0050,
 130         [TSU_FWINMK]    = 0x0054,
 131         [TSU_ADQT0]     = 0x0048,
 132         [TSU_ADQT1]     = 0x004c,
 133         [TSU_VTAG0]     = 0x0058,
 134         [TSU_VTAG1]     = 0x005c,
 135         [TSU_ADSBSY]    = 0x0060,
 136         [TSU_TEN]       = 0x0064,
 137         [TSU_POST1]     = 0x0070,
 138         [TSU_POST2]     = 0x0074,
 139         [TSU_POST3]     = 0x0078,
 140         [TSU_POST4]     = 0x007c,
 141         [TSU_ADRH0]     = 0x0100,
 142
 143         [TXNLCR0]       = 0x0080,
 144         [TXALCR0]       = 0x0084,
 145         [RXNLCR0]       = 0x0088,
 146         [RXALCR0]       = 0x008c,
 147         [FWNLCR0]       = 0x0090,
 148         [FWALCR0]       = 0x0094,
 149         [TXNLCR1]       = 0x00a0,
 150         [TXALCR1]       = 0x00a0,
 151         [RXNLCR1]       = 0x00a8,
 152         [RXALCR1]       = 0x00ac,
 153         [FWNLCR1]       = 0x00b0,
 154         [FWALCR1]       = 0x00b4,
 155 };
 156
 157 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
 158         SH_ETH_OFFSET_DEFAULTS,
 159
 160         [EDSR]          = 0x0000,
 161         [EDMR]          = 0x0400,
 162         [EDTRR]         = 0x0408,
 163         [EDRRR]         = 0x0410,
 164         [EESR]          = 0x0428,
 165         [EESIPR]        = 0x0430,
 166         [TDLAR]         = 0x0010,
 167         [TDFAR]         = 0x0014,
 168         [TDFXR]         = 0x0018,
 169         [TDFFR]         = 0x001c,
 170         [RDLAR]         = 0x0030,
 171         [RDFAR]         = 0x0034,
 172         [RDFXR]         = 0x0038,
 173         [RDFFR]         = 0x003c,
 174         [TRSCER]        = 0x0438,
 175         [RMFCR]         = 0x0440,
 176         [TFTR]          = 0x0448,
 177         [FDR]           = 0x0450,
 178         [RMCR]          = 0x0458,
 179         [RPADIR]        = 0x0460,
 180         [FCFTR]         = 0x0468,
 181         [CSMR]          = 0x04E4,
 182
 183         [ECMR]          = 0x0500,
 184         [RFLR]          = 0x0508,
 185         [ECSR]          = 0x0510,
 186         [ECSIPR]        = 0x0518,
 187         [PIR]           = 0x0520,
 188         [APR]           = 0x0554,
 189         [MPR]           = 0x0558,
 190         [PFTCR]         = 0x055c,
 191         [PFRCR]         = 0x0560,
 192         [TPAUSER]       = 0x0564,
 193         [MAHR]          = 0x05c0,
 194         [MALR]          = 0x05c8,
 195         [CEFCR]         = 0x0740,
 196         [FRECR]         = 0x0748,
 197         [TSFRCR]        = 0x0750,
 198         [TLFRCR]        = 0x0758,
 199         [RFCR]          = 0x0760,
 200         [MAFCR]         = 0x0778,
 201
 202         [ARSTR]         = 0x0000,
 203         [TSU_CTRST]     = 0x0004,
 204         [TSU_VTAG0]     = 0x0058,
 205         [TSU_ADSBSY]    = 0x0060,
 206         [TSU_TEN]       = 0x0064,
 207         [TSU_ADRH0]     = 0x0100,
 208
 209         [TXNLCR0]       = 0x0080,
 210         [TXALCR0]       = 0x0084,
 211         [RXNLCR0]       = 0x0088,
 212         [RXALCR0]       = 0x008C,
 213 };
 214
 215 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
 216         SH_ETH_OFFSET_DEFAULTS,
 217
 218         [ECMR]          = 0x0300,
 219         [RFLR]          = 0x0308,
 220         [ECSR]          = 0x0310,
 221         [ECSIPR]        = 0x0318,
 222         [PIR]           = 0x0320,
 223         [PSR]           = 0x0328,
 224         [RDMLR]         = 0x0340,
 225         [IPGR]          = 0x0350,
 226         [APR]           = 0x0354,
 227         [MPR]           = 0x0358,
 228         [RFCF]          = 0x0360,
 229         [TPAUSER]       = 0x0364,
 230         [TPAUSECR]      = 0x0368,
 231         [MAHR]          = 0x03c0,
 232         [MALR]          = 0x03c8,
 233         [TROCR]         = 0x03d0,
 234         [CDCR]          = 0x03d4,
 235         [LCCR]          = 0x03d8,
 236         [CNDCR]         = 0x03dc,
 237         [CEFCR]         = 0x03e4,
 238         [FRECR]         = 0x03e8,
 239         [TSFRCR]        = 0x03ec,
 240         [TLFRCR]        = 0x03f0,
 241         [RFCR]          = 0x03f4,
 242         [MAFCR]         = 0x03f8,
 243
 244         [EDMR]          = 0x0200,
 245         [EDTRR]         = 0x0208,
 246         [EDRRR]         = 0x0210,
 247         [TDLAR]         = 0x0218,
 248         [RDLAR]         = 0x0220,
 249         [EESR]          = 0x0228,
 250         [EESIPR]        = 0x0230,
 251         [TRSCER]        = 0x0238,
 252         [RMFCR]         = 0x0240,
 253         [TFTR]          = 0x0248,
 254         [FDR]           = 0x0250,
 255         [RMCR]          = 0x0258,
 256         [TFUCR]         = 0x0264,
 257         [RFOCR]         = 0x0268,
 258         [RMIIMODE]      = 0x026c,
 259         [FCFTR]         = 0x0270,
 260         [TRIMD]         = 0x027c,
 261 };
 262
 263 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 264         SH_ETH_OFFSET_DEFAULTS,
 265
 266         [ECMR]          = 0x0100,
 267         [RFLR]          = 0x0108,
 268         [ECSR]          = 0x0110,
 269         [ECSIPR]        = 0x0118,
 270         [PIR]           = 0x0120,
 271         [PSR]           = 0x0128,
 272         [RDMLR]         = 0x0140,
 273         [IPGR]          = 0x0150,
 274         [APR]           = 0x0154,
 275         [MPR]           = 0x0158,
 276         [TPAUSER]       = 0x0164,
 277         [RFCF]          = 0x0160,
 278         [TPAUSECR]      = 0x0168,
 279         [BCFRR]         = 0x016c,
 280         [MAHR]          = 0x01c0,
 281         [MALR]          = 0x01c8,
 282         [TROCR]         = 0x01d0,
 283         [CDCR]          = 0x01d4,
 284         [LCCR]          = 0x01d8,
 285         [CNDCR]         = 0x01dc,
 286         [CEFCR]         = 0x01e4,
 287         [FRECR]         = 0x01e8,
 288         [TSFRCR]        = 0x01ec,
 289         [TLFRCR]        = 0x01f0,
 290         [RFCR]          = 0x01f4,
 291         [MAFCR]         = 0x01f8,
 292         [RTRATE]        = 0x01fc,
 293
 294         [EDMR]          = 0x0000,
 295         [EDTRR]         = 0x0008,
 296         [EDRRR]         = 0x0010,
 297         [TDLAR]         = 0x0018,
 298         [RDLAR]         = 0x0020,
 299         [EESR]          = 0x0028,
 300         [EESIPR]        = 0x0030,
 301         [TRSCER]        = 0x0038,
 302         [RMFCR]         = 0x0040,
 303         [TFTR]          = 0x0048,
 304         [FDR]           = 0x0050,
 305         [RMCR]          = 0x0058,
 306         [TFUCR]         = 0x0064,
 307         [RFOCR]         = 0x0068,
 308         [FCFTR]         = 0x0070,
 309         [RPADIR]        = 0x0078,
 310         [TRIMD]         = 0x007c,
 311         [RBWAR]         = 0x00c8,
 312         [RDFAR]         = 0x00cc,
 313         [TBRAR]         = 0x00d4,
 314         [TDFAR]         = 0x00d8,
 315 };
 316
 317 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
 318         SH_ETH_OFFSET_DEFAULTS,
 319
 320         [EDMR]          = 0x0000,
 321         [EDTRR]         = 0x0004,
 322         [EDRRR]         = 0x0008,
 323         [TDLAR]         = 0x000c,
 324         [RDLAR]         = 0x0010,
 325         [EESR]          = 0x0014,
 326         [EESIPR]        = 0x0018,
 327         [TRSCER]        = 0x001c,
 328         [RMFCR]         = 0x0020,
 329         [TFTR]          = 0x0024,
 330         [FDR]           = 0x0028,
 331         [RMCR]          = 0x002c,
 332         [EDOCR]         = 0x0030,
 333         [FCFTR]         = 0x0034,
 334         [RPADIR]        = 0x0038,
 335         [TRIMD]         = 0x003c,
 336         [RBWAR]         = 0x0040,
 337         [RDFAR]         = 0x0044,
 338         [TBRAR]         = 0x004c,
 339         [TDFAR]         = 0x0050,
 340
 341         [ECMR]          = 0x0160,
 342         [ECSR]          = 0x0164,
 343         [ECSIPR]        = 0x0168,
 344         [PIR]           = 0x016c,
 345         [MAHR]          = 0x0170,
 346         [MALR]          = 0x0174,
 347         [RFLR]          = 0x0178,
 348         [PSR]           = 0x017c,
 349         [TROCR]         = 0x0180,
 350         [CDCR]          = 0x0184,
 351         [LCCR]          = 0x0188,
 352         [CNDCR]         = 0x018c,
 353         [CEFCR]         = 0x0194,
 354         [FRECR]         = 0x0198,
 355         [TSFRCR]        = 0x019c,
 356         [TLFRCR]        = 0x01a0,
 357         [RFCR]          = 0x01a4,
 358         [MAFCR]         = 0x01a8,
 359         [IPGR]          = 0x01b4,
 360         [APR]           = 0x01b8,
 361         [MPR]           = 0x01bc,
 362         [TPAUSER]       = 0x01c4,
 363         [BCFR]          = 0x01cc,
 364
 365         [ARSTR]         = 0x0000,
 366         [TSU_CTRST]     = 0x0004,
 367         [TSU_FWEN0]     = 0x0010,
 368         [TSU_FWEN1]     = 0x0014,
 369         [TSU_FCM]       = 0x0018,
 370         [TSU_BSYSL0]    = 0x0020,
 371         [TSU_BSYSL1]    = 0x0024,
 372         [TSU_PRISL0]    = 0x0028,
 373         [TSU_PRISL1]    = 0x002c,
 374         [TSU_FWSL0]     = 0x0030,
 375         [TSU_FWSL1]     = 0x0034,
 376         [TSU_FWSLC]     = 0x0038,
 377         [TSU_QTAGM0]    = 0x0040,
 378         [TSU_QTAGM1]    = 0x0044,
 379         [TSU_ADQT0]     = 0x0048,
 380         [TSU_ADQT1]     = 0x004c,
 381         [TSU_FWSR]      = 0x0050,
 382         [TSU_FWINMK]    = 0x0054,
 383         [TSU_ADSBSY]    = 0x0060,
 384         [TSU_TEN]       = 0x0064,
 385         [TSU_POST1]     = 0x0070,
 386         [TSU_POST2]     = 0x0074,
 387         [TSU_POST3]     = 0x0078,
 388         [TSU_POST4]     = 0x007c,
 389
 390         [TXNLCR0]       = 0x0080,
 391         [TXALCR0]       = 0x0084,
 392         [RXNLCR0]       = 0x0088,
 393         [RXALCR0]       = 0x008c,
 394         [FWNLCR0]       = 0x0090,
 395         [FWALCR0]       = 0x0094,
 396         [TXNLCR1]       = 0x00a0,
 397         [TXALCR1]       = 0x00a0,
 398         [RXNLCR1]       = 0x00a8,
 399         [RXALCR1]       = 0x00ac,
 400         [FWNLCR1]       = 0x00b0,
 401         [FWALCR1]       = 0x00b4,
 402
 403         [TSU_ADRH0]     = 0x0100,
 404 };
 405
 406 static void sh_eth_rcv_snd_disable(struct net_device *ndev);
 407 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
 408
 409 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
 410 {
 411         struct sh_eth_private *mdp = netdev_priv(ndev);
 412         u16 offset = mdp->reg_offset[enum_index];
 413
 414         if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
 415                 return;
 416
 417         iowrite32(data, mdp->addr + offset);
 418 }
 419
 420 static u32 sh_eth_read(struct net_device *ndev, int enum_index)
 421 {
 422         struct sh_eth_private *mdp = netdev_priv(ndev);
 423         u16 offset = mdp->reg_offset[enum_index];
 424
 425         if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
 426                 return ~0U;
 427
 428         return ioread32(mdp->addr + offset);
 429 }
 430
 431 static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
 432                           u32 set)
 433 {
 434         sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set,
 435                      enum_index);
 436 }
 437
 438 static bool sh_eth_is_gether(struct sh_eth_private *mdp)
 439 {
 440         return mdp->reg_offset == sh_eth_offset_gigabit;
 441 }
 442
 443 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
 444 {
 445         return mdp->reg_offset == sh_eth_offset_fast_rz;
 446 }
 447
 448 static void sh_eth_select_mii(struct net_device *ndev)
 449 {
 450         struct sh_eth_private *mdp = netdev_priv(ndev);
 451         u32 value;
 452
 453         switch (mdp->phy_interface) {
 454         case PHY_INTERFACE_MODE_GMII:
 455                 value = 0x2;
 456                 break;
 457         case PHY_INTERFACE_MODE_MII:
 458                 value = 0x1;
 459                 break;
 460         case PHY_INTERFACE_MODE_RMII:
 461                 value = 0x0;
 462                 break;
 463         default:
 464                 netdev_warn(ndev,
 465                             "PHY interface mode was not setup. Set to MII.\n");
 466                 value = 0x1;
 467                 break;
 468         }
 469
 470         sh_eth_write(ndev, value, RMII_MII);
 471 }
 472
 473 static void sh_eth_set_duplex(struct net_device *ndev)
 474 {
 475         struct sh_eth_private *mdp = netdev_priv(ndev);
 476
 477         sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0);
 478 }
 479
 480 static void sh_eth_chip_reset(struct net_device *ndev)
 481 {
 482         struct sh_eth_private *mdp = netdev_priv(ndev);
 483
 484         /* reset device */
 485         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 486         mdelay(1);
 487 }
 488
 489 static void sh_eth_set_rate_gether(struct net_device *ndev)
 490 {
 491         struct sh_eth_private *mdp = netdev_priv(ndev);
 492
 493         switch (mdp->speed) {
 494         case 10: /* 10BASE */
 495                 sh_eth_write(ndev, GECMR_10, GECMR);
 496                 break;
 497         case 100:/* 100BASE */
 498                 sh_eth_write(ndev, GECMR_100, GECMR);
 499                 break;
 500         case 1000: /* 1000BASE */
 501                 sh_eth_write(ndev, GECMR_1000, GECMR);
 502                 break;
 503         }
 504 }
 505
 506 #ifdef CONFIG_OF
 507 /* R7S72100 */
 508 static struct sh_eth_cpu_data r7s72100_data = {
 509         .chip_reset     = sh_eth_chip_reset,
 510         .set_duplex     = sh_eth_set_duplex,
 511
 512         .register_type  = SH_ETH_REG_FAST_RZ,
 513
 514         .ecsr_value     = ECSR_ICD,
 515         .ecsipr_value   = ECSIPR_ICDIP,
 516         .eesipr_value   = 0xff7f009f,
 517
 518         .tx_check       = EESR_TC1 | EESR_FTC,
 519         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 520                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 521                           EESR_TDE | EESR_ECI,
 522         .fdr_value      = 0x0000070f,
 523
 524         .no_psr         = 1,
 525         .apr            = 1,
 526         .mpr            = 1,
 527         .tpauser        = 1,
 528         .hw_swap        = 1,
 529         .rpadir         = 1,
 530         .rpadir_value   = 2 << 16,
 531         .no_trimd       = 1,
 532         .no_ade         = 1,
 533         .hw_crc         = 1,
 534         .tsu            = 1,
 535         .shift_rd0      = 1,
 536 };
 537
 538 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
 539 {
 540         struct sh_eth_private *mdp = netdev_priv(ndev);
 541
 542         /* reset device */
 543         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 544         mdelay(1);
 545
 546         sh_eth_select_mii(ndev);
 547 }
 548
 549 /* R8A7740 */
 550 static struct sh_eth_cpu_data r8a7740_data = {
 551         .chip_reset     = sh_eth_chip_reset_r8a7740,
 552         .set_duplex     = sh_eth_set_duplex,
 553         .set_rate       = sh_eth_set_rate_gether,
 554
 555         .register_type  = SH_ETH_REG_GIGABIT,
 556
 557         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 558         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 559         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 560
 561         .tx_check       = EESR_TC1 | EESR_FTC,
 562         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 563                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 564                           EESR_TDE | EESR_ECI,
 565         .fdr_value      = 0x0000070f,
 566
 567         .apr            = 1,
 568         .mpr            = 1,
 569         .tpauser        = 1,
 570         .bculr          = 1,
 571         .hw_swap        = 1,
 572         .rpadir         = 1,
 573         .rpadir_value   = 2 << 16,
 574         .no_trimd       = 1,
 575         .no_ade         = 1,
 576         .tsu            = 1,
 577         .select_mii     = 1,
 578         .shift_rd0      = 1,
 579 };
 580
 581 /* There is CPU dependent code */
 582 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
 583 {
 584         struct sh_eth_private *mdp = netdev_priv(ndev);
 585
 586         switch (mdp->speed) {
 587         case 10: /* 10BASE */
 588                 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0);
 589                 break;
 590         case 100:/* 100BASE */
 591                 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB);
 592                 break;
 593         }
 594 }
 595
 596 /* R8A7778/9 */
 597 static struct sh_eth_cpu_data r8a777x_data = {
 598         .set_duplex     = sh_eth_set_duplex,
 599         .set_rate       = sh_eth_set_rate_r8a777x,
 600
 601         .register_type  = SH_ETH_REG_FAST_RCAR,
 602
 603         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 604         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 605         .eesipr_value   = 0x01ff009f,
 606
 607         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 608         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 609                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 610                           EESR_ECI,
 611         .fdr_value      = 0x00000f0f,
 612
 613         .apr            = 1,
 614         .mpr            = 1,
 615         .tpauser        = 1,
 616         .hw_swap        = 1,
 617 };
 618
 619 /* R8A7790/1 */
 620 static struct sh_eth_cpu_data r8a779x_data = {
 621         .set_duplex     = sh_eth_set_duplex,
 622         .set_rate       = sh_eth_set_rate_r8a777x,
 623
 624         .register_type  = SH_ETH_REG_FAST_RCAR,
 625
 626         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 627         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 628         .eesipr_value   = 0x01ff009f,
 629
 630         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 631         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 632                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 633                           EESR_ECI,
 634         .fdr_value      = 0x00000f0f,
 635
 636         .trscer_err_mask = DESC_I_RINT8,
 637
 638         .apr            = 1,
 639         .mpr            = 1,
 640         .tpauser        = 1,
 641         .hw_swap        = 1,
 642         .rmiimode       = 1,
 643 };
 644 #endif /* CONFIG_OF */
 645
 646 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
 647 {
 648         struct sh_eth_private *mdp = netdev_priv(ndev);
 649
 650         switch (mdp->speed) {
 651         case 10: /* 10BASE */
 652                 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0);
 653                 break;
 654         case 100:/* 100BASE */
 655                 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM);
 656                 break;
 657         }
 658 }
 659
 660 /* SH7724 */
 661 static struct sh_eth_cpu_data sh7724_data = {
 662         .set_duplex     = sh_eth_set_duplex,
 663         .set_rate       = sh_eth_set_rate_sh7724,
 664
 665         .register_type  = SH_ETH_REG_FAST_SH4,
 666
 667         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 668         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 669         .eesipr_value   = 0x01ff009f,
 670
 671         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 672         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 673                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 674                           EESR_ECI,
 675
 676         .apr            = 1,
 677         .mpr            = 1,
 678         .tpauser        = 1,
 679         .hw_swap        = 1,
 680         .rpadir         = 1,
 681         .rpadir_value   = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
 682 };
 683
 684 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
 685 {
 686         struct sh_eth_private *mdp = netdev_priv(ndev);
 687
 688         switch (mdp->speed) {
 689         case 10: /* 10BASE */
 690                 sh_eth_write(ndev, 0, RTRATE);
 691                 break;
 692         case 100:/* 100BASE */
 693                 sh_eth_write(ndev, 1, RTRATE);
 694                 break;
 695         }
 696 }
 697
 698 /* SH7757 */
 699 static struct sh_eth_cpu_data sh7757_data = {
 700         .set_duplex     = sh_eth_set_duplex,
 701         .set_rate       = sh_eth_set_rate_sh7757,
 702
 703         .register_type  = SH_ETH_REG_FAST_SH4,
 704
 705         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 706
 707         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 708         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 709                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 710                           EESR_ECI,
 711
 712         .irq_flags      = IRQF_SHARED,
 713         .apr            = 1,
 714         .mpr            = 1,
 715         .tpauser        = 1,
 716         .hw_swap        = 1,
 717         .no_ade         = 1,
 718         .rpadir         = 1,
 719         .rpadir_value   = 2 << 16,
 720         .rtrate         = 1,
 721 };
 722
 723 #define SH_GIGA_ETH_BASE        0xfee00000UL
 724 #define GIGA_MALR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
 725 #define GIGA_MAHR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
 726 static void sh_eth_chip_reset_giga(struct net_device *ndev)
 727 {
 728         int i;
 729         u32 mahr[2], malr[2];
 730
 731         /* save MAHR and MALR */
 732         for (i = 0; i < 2; i++) {
 733                 malr[i] = ioread32((void *)GIGA_MALR(i));
 734                 mahr[i] = ioread32((void *)GIGA_MAHR(i));
 735         }
 736
 737         /* reset device */
 738         iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
 739         mdelay(1);
 740
 741         /* restore MAHR and MALR */
 742         for (i = 0; i < 2; i++) {
 743                 iowrite32(malr[i], (void *)GIGA_MALR(i));
 744                 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
 745         }
 746 }
 747
 748 static void sh_eth_set_rate_giga(struct net_device *ndev)
 749 {
 750         struct sh_eth_private *mdp = netdev_priv(ndev);
 751
 752         switch (mdp->speed) {
 753         case 10: /* 10BASE */
 754                 sh_eth_write(ndev, 0x00000000, GECMR);
 755                 break;
 756         case 100:/* 100BASE */
 757                 sh_eth_write(ndev, 0x00000010, GECMR);
 758                 break;
 759         case 1000: /* 1000BASE */
 760                 sh_eth_write(ndev, 0x00000020, GECMR);
 761                 break;
 762         }
 763 }
 764
 765 /* SH7757(GETHERC) */
 766 static struct sh_eth_cpu_data sh7757_data_giga = {
 767         .chip_reset     = sh_eth_chip_reset_giga,
 768         .set_duplex     = sh_eth_set_duplex,
 769         .set_rate       = sh_eth_set_rate_giga,
 770
 771         .register_type  = SH_ETH_REG_GIGABIT,
 772
 773         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 774         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 775         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 776
 777         .tx_check       = EESR_TC1 | EESR_FTC,
 778         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 779                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 780                           EESR_TDE | EESR_ECI,
 781         .fdr_value      = 0x0000072f,
 782
 783         .irq_flags      = IRQF_SHARED,
 784         .apr            = 1,
 785         .mpr            = 1,
 786         .tpauser        = 1,
 787         .bculr          = 1,
 788         .hw_swap        = 1,
 789         .rpadir         = 1,
 790         .rpadir_value   = 2 << 16,
 791         .no_trimd       = 1,
 792         .no_ade         = 1,
 793         .tsu            = 1,
 794 };
 795
 796 /* SH7734 */
 797 static struct sh_eth_cpu_data sh7734_data = {
 798         .chip_reset     = sh_eth_chip_reset,
 799         .set_duplex     = sh_eth_set_duplex,
 800         .set_rate       = sh_eth_set_rate_gether,
 801
 802         .register_type  = SH_ETH_REG_GIGABIT,
 803
 804         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 805         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 806         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 807
 808         .tx_check       = EESR_TC1 | EESR_FTC,
 809         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 810                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 811                           EESR_TDE | EESR_ECI,
 812
 813         .apr            = 1,
 814         .mpr            = 1,
 815         .tpauser        = 1,
 816         .bculr          = 1,
 817         .hw_swap        = 1,
 818         .no_trimd       = 1,
 819         .no_ade         = 1,
 820         .tsu            = 1,
 821         .hw_crc         = 1,
 822         .select_mii     = 1,
 823 };
 824
 825 /* SH7763 */
 826 static struct sh_eth_cpu_data sh7763_data = {
 827         .chip_reset     = sh_eth_chip_reset,
 828         .set_duplex     = sh_eth_set_duplex,
 829         .set_rate       = sh_eth_set_rate_gether,
 830
 831         .register_type  = SH_ETH_REG_GIGABIT,
 832
 833         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 834         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 835         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 836
 837         .tx_check       = EESR_TC1 | EESR_FTC,
 838         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 839                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 840                           EESR_ECI,
 841
 842         .apr            = 1,
 843         .mpr            = 1,
 844         .tpauser        = 1,
 845         .bculr          = 1,
 846         .hw_swap        = 1,
 847         .no_trimd       = 1,
 848         .no_ade         = 1,
 849         .tsu            = 1,
 850         .irq_flags      = IRQF_SHARED,
 851 };
 852
 853 static struct sh_eth_cpu_data sh7619_data = {
 854         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
 855
 856         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 857
 858         .apr            = 1,
 859         .mpr            = 1,
 860         .tpauser        = 1,
 861         .hw_swap        = 1,
 862 };
 863
 864 static struct sh_eth_cpu_data sh771x_data = {
 865         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
 866
 867         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 868         .tsu            = 1,
 869 };
 870
 871 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
 872 {
 873         if (!cd->ecsr_value)
 874                 cd->ecsr_value = DEFAULT_ECSR_INIT;
 875
 876         if (!cd->ecsipr_value)
 877                 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
 878
 879         if (!cd->fcftr_value)
 880                 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
 881                                   DEFAULT_FIFO_F_D_RFD;
 882
 883         if (!cd->fdr_value)
 884                 cd->fdr_value = DEFAULT_FDR_INIT;
 885
 886         if (!cd->tx_check)
 887                 cd->tx_check = DEFAULT_TX_CHECK;
 888
 889         if (!cd->eesr_err_check)
 890                 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
 891
 892         if (!cd->trscer_err_mask)
 893                 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
 894 }
 895
 896 static int sh_eth_check_reset(struct net_device *ndev)
 897 {
 898         int ret = 0;
 899         int cnt = 100;
 900
 901         while (cnt > 0) {
 902                 if (!(sh_eth_read(ndev, EDMR) & 0x3))
 903                         break;
 904                 mdelay(1);
 905                 cnt--;
 906         }
 907         if (cnt <= 0) {
 908                 netdev_err(ndev, "Device reset failed\n");
 909                 ret = -ETIMEDOUT;
 910         }
 911         return ret;
 912 }
 913
 914 static int sh_eth_reset(struct net_device *ndev)
 915 {
 916         struct sh_eth_private *mdp = netdev_priv(ndev);
 917         int ret = 0;
 918
 919         if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
 920                 sh_eth_write(ndev, EDSR_ENALL, EDSR);
 921                 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
 922
 923                 ret = sh_eth_check_reset(ndev);
 924                 if (ret)
 925                         return ret;
 926
 927                 /* Table Init */
 928                 sh_eth_write(ndev, 0x0, TDLAR);
 929                 sh_eth_write(ndev, 0x0, TDFAR);
 930                 sh_eth_write(ndev, 0x0, TDFXR);
 931                 sh_eth_write(ndev, 0x0, TDFFR);
 932                 sh_eth_write(ndev, 0x0, RDLAR);
 933                 sh_eth_write(ndev, 0x0, RDFAR);
 934                 sh_eth_write(ndev, 0x0, RDFXR);
 935                 sh_eth_write(ndev, 0x0, RDFFR);
 936
 937                 /* Reset HW CRC register */
 938                 if (mdp->cd->hw_crc)
 939                         sh_eth_write(ndev, 0x0, CSMR);
 940
 941                 /* Select MII mode */
 942                 if (mdp->cd->select_mii)
 943                         sh_eth_select_mii(ndev);
 944         } else {
 945                 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
 946                 mdelay(3);
 947                 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
 948         }
 949
 950         return ret;
 951 }
 952
 953 static void sh_eth_set_receive_align(struct sk_buff *skb)
 954 {
 955         uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
 956
 957         if (reserve)
 958                 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
 959 }
 960
 961 /* Program the hardware MAC address from dev->dev_addr. */
 962 static void update_mac_address(struct net_device *ndev)
 963 {
 964         sh_eth_write(ndev,
 965                      (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
 966                      (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
 967         sh_eth_write(ndev,
 968                      (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
 969 }
 970
 971 /* Get MAC address from SuperH MAC address register
 972  *
 973  * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
 974  * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
 975  * When you want use this device, you must set MAC address in bootloader.
 976  *
 977  */
 978 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
 979 {
 980         if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
 981                 memcpy(ndev->dev_addr, mac, ETH_ALEN);
 982         } else {
 983                 u32 mahr = sh_eth_read(ndev, MAHR);
 984                 u32 malr = sh_eth_read(ndev, MALR);
 985
 986                 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
 987                 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
 988                 ndev->dev_addr[2] = (mahr >>  8) & 0xFF;
 989                 ndev->dev_addr[3] = (mahr >>  0) & 0xFF;
 990                 ndev->dev_addr[4] = (malr >>  8) & 0xFF;
 991                 ndev->dev_addr[5] = (malr >>  0) & 0xFF;
 992         }
 993 }
 994
 995 static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
 996 {
 997         if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
 998                 return EDTRR_TRNS_GETHER;
 999         else
1000                 return EDTRR_TRNS_ETHER;
1001 }
1002
1003 struct bb_info {
1004         void (*set_gate)(void *addr);
1005         struct mdiobb_ctrl ctrl;
1006         void *addr;
1007 };
1008
1009 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
1010 {
1011         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1012         u32 pir;
1013
1014         if (bitbang->set_gate)
1015                 bitbang->set_gate(bitbang->addr);
1016
1017         pir = ioread32(bitbang->addr);
1018         if (set)
1019                 pir |=  mask;
1020         else
1021                 pir &= ~mask;
1022         iowrite32(pir, bitbang->addr);
1023 }
1024
1025 /* Data I/O pin control */
1026 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1027 {
1028         sh_mdio_ctrl(ctrl, PIR_MMD, bit);
1029 }
1030
1031 /* Set bit data*/
1032 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1033 {
1034         sh_mdio_ctrl(ctrl, PIR_MDO, bit);
1035 }
1036
1037 /* Get bit data*/
1038 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1039 {
1040         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1041
1042         if (bitbang->set_gate)
1043                 bitbang->set_gate(bitbang->addr);
1044
1045         return (ioread32(bitbang->addr) & PIR_MDI) != 0;
1046 }
1047
1048 /* MDC pin control */
1049 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1050 {
1051         sh_mdio_ctrl(ctrl, PIR_MDC, bit);
1052 }
1053
1054 /* mdio bus control struct */
1055 static struct mdiobb_ops bb_ops = {
1056         .owner = THIS_MODULE,
1057         .set_mdc = sh_mdc_ctrl,
1058         .set_mdio_dir = sh_mmd_ctrl,
1059         .set_mdio_data = sh_set_mdio,
1060         .get_mdio_data = sh_get_mdio,
1061 };
1062
1063 /* free skb and descriptor buffer */
1064 static void sh_eth_ring_free(struct net_device *ndev)
1065 {
1066         struct sh_eth_private *mdp = netdev_priv(ndev);
1067         int ringsize, i;
1068
1069         /* Free Rx skb ringbuffer */
1070         if (mdp->rx_skbuff) {
1071                 for (i = 0; i < mdp->num_rx_ring; i++)
1072                         dev_kfree_skb(mdp->rx_skbuff[i]);
1073         }
1074         kfree(mdp->rx_skbuff);
1075         mdp->rx_skbuff = NULL;
1076
1077         /* Free Tx skb ringbuffer */
1078         if (mdp->tx_skbuff) {
1079                 for (i = 0; i < mdp->num_tx_ring; i++)
1080                         dev_kfree_skb(mdp->tx_skbuff[i]);
1081         }
1082         kfree(mdp->tx_skbuff);
1083         mdp->tx_skbuff = NULL;
1084
1085         if (mdp->rx_ring) {
1086                 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1087                 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1088                                   mdp->rx_desc_dma);
1089                 mdp->rx_ring = NULL;
1090         }
1091
1092         if (mdp->tx_ring) {
1093                 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1094                 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1095                                   mdp->tx_desc_dma);
1096                 mdp->tx_ring = NULL;
1097         }
1098 }
1099
1100 /* format skb and descriptor buffer */
1101 static void sh_eth_ring_format(struct net_device *ndev)
1102 {
1103         struct sh_eth_private *mdp = netdev_priv(ndev);
1104         int i;
1105         struct sk_buff *skb;
1106         struct sh_eth_rxdesc *rxdesc = NULL;
1107         struct sh_eth_txdesc *txdesc = NULL;
1108         int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1109         int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1110         int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1111         dma_addr_t dma_addr;
1112         u32 buf_len;
1113
1114         mdp->cur_rx = 0;
1115         mdp->cur_tx = 0;
1116         mdp->dirty_rx = 0;
1117         mdp->dirty_tx = 0;
1118
1119         memset(mdp->rx_ring, 0, rx_ringsize);
1120
1121         /* build Rx ring buffer */
1122         for (i = 0; i < mdp->num_rx_ring; i++) {
1123                 /* skb */
1124                 mdp->rx_skbuff[i] = NULL;
1125                 skb = netdev_alloc_skb(ndev, skbuff_size);
1126                 if (skb == NULL)
1127                         break;
1128                 sh_eth_set_receive_align(skb);
1129
1130                 /* The size of the buffer is a multiple of 32 bytes. */
1131                 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1132                 dma_addr = dma_map_single(&ndev->dev, skb->data, buf_len,
1133                                           DMA_FROM_DEVICE);
1134                 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1135                         kfree_skb(skb);
1136                         break;
1137                 }
1138                 mdp->rx_skbuff[i] = skb;
1139
1140                 /* RX descriptor */
1141                 rxdesc = &mdp->rx_ring[i];
1142                 rxdesc->len = cpu_to_le32(buf_len << 16);
1143                 rxdesc->addr = cpu_to_le32(dma_addr);
1144                 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
1145
1146                 /* Rx descriptor address set */
1147                 if (i == 0) {
1148                         sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1149                         if (sh_eth_is_gether(mdp) ||
1150                             sh_eth_is_rz_fast_ether(mdp))
1151                                 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1152                 }
1153         }
1154
1155         mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1156
1157         /* Mark the last entry as wrapping the ring. */
1158         if (rxdesc)
1159                 rxdesc->status |= cpu_to_le32(RD_RDLE);
1160
1161         memset(mdp->tx_ring, 0, tx_ringsize);
1162
1163         /* build Tx ring buffer */
1164         for (i = 0; i < mdp->num_tx_ring; i++) {
1165                 mdp->tx_skbuff[i] = NULL;
1166                 txdesc = &mdp->tx_ring[i];
1167                 txdesc->status = cpu_to_le32(TD_TFP);
1168                 txdesc->len = cpu_to_le32(0);
1169                 if (i == 0) {
1170                         /* Tx descriptor address set */
1171                         sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1172                         if (sh_eth_is_gether(mdp) ||
1173                             sh_eth_is_rz_fast_ether(mdp))
1174                                 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1175                 }
1176         }
1177
1178         txdesc->status |= cpu_to_le32(TD_TDLE);
1179 }
1180
1181 /* Get skb and descriptor buffer */
1182 static int sh_eth_ring_init(struct net_device *ndev)
1183 {
1184         struct sh_eth_private *mdp = netdev_priv(ndev);
1185         int rx_ringsize, tx_ringsize;
1186
1187         /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1188          * card needs room to do 8 byte alignment, +2 so we can reserve
1189          * the first 2 bytes, and +16 gets room for the status word from the
1190          * card.
1191          */
1192         mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1193                           (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1194         if (mdp->cd->rpadir)
1195                 mdp->rx_buf_sz += NET_IP_ALIGN;
1196
1197         /* Allocate RX and TX skb rings */
1198         mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1199                                  GFP_KERNEL);
1200         if (!mdp->rx_skbuff)
1201                 return -ENOMEM;
1202
1203         mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1204                                  GFP_KERNEL);
1205         if (!mdp->tx_skbuff)
1206                 goto ring_free;
1207
1208         /* Allocate all Rx descriptors. */
1209         rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1210         mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1211                                           GFP_KERNEL);
1212         if (!mdp->rx_ring)
1213                 goto ring_free;
1214
1215         mdp->dirty_rx = 0;
1216
1217         /* Allocate all Tx descriptors. */
1218         tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1219         mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1220                                           GFP_KERNEL);
1221         if (!mdp->tx_ring)
1222                 goto ring_free;
1223         return 0;
1224
1225 ring_free:
1226         /* Free Rx and Tx skb ring buffer and DMA buffer */
1227         sh_eth_ring_free(ndev);
1228
1229         return -ENOMEM;
1230 }
1231
1232 static int sh_eth_dev_init(struct net_device *ndev)
1233 {
1234         struct sh_eth_private *mdp = netdev_priv(ndev);
1235         int ret;
1236
1237         /* Soft Reset */
1238         ret = sh_eth_reset(ndev);
1239         if (ret)
1240                 return ret;
1241
1242         if (mdp->cd->rmiimode)
1243                 sh_eth_write(ndev, 0x1, RMIIMODE);
1244
1245         /* Descriptor format */
1246         sh_eth_ring_format(ndev);
1247         if (mdp->cd->rpadir)
1248                 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1249
1250         /* all sh_eth int mask */
1251         sh_eth_write(ndev, 0, EESIPR);
1252
1253 #if defined(__LITTLE_ENDIAN)
1254         if (mdp->cd->hw_swap)
1255                 sh_eth_write(ndev, EDMR_EL, EDMR);
1256         else
1257 #endif
1258                 sh_eth_write(ndev, 0, EDMR);
1259
1260         /* FIFO size set */
1261         sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1262         sh_eth_write(ndev, 0, TFTR);
1263
1264         /* Frame recv control (enable multiple-packets per rx irq) */
1265         sh_eth_write(ndev, RMCR_RNC, RMCR);
1266
1267         sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1268
1269         if (mdp->cd->bculr)
1270                 sh_eth_write(ndev, 0x800, BCULR);       /* Burst sycle set */
1271
1272         sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1273
1274         if (!mdp->cd->no_trimd)
1275                 sh_eth_write(ndev, 0, TRIMD);
1276
1277         /* Recv frame limit set register */
1278         sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1279                      RFLR);
1280
1281         sh_eth_modify(ndev, EESR, 0, 0);
1282         mdp->irq_enabled = true;
1283         sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1284
1285         /* PAUSE Prohibition */
1286         sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |
1287                      ECMR_TE | ECMR_RE, ECMR);
1288
1289         if (mdp->cd->set_rate)
1290                 mdp->cd->set_rate(ndev);
1291
1292         /* E-MAC Status Register clear */
1293         sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1294
1295         /* E-MAC Interrupt Enable register */
1296         sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1297
1298         /* Set MAC address */
1299         update_mac_address(ndev);
1300
1301         /* mask reset */
1302         if (mdp->cd->apr)
1303                 sh_eth_write(ndev, APR_AP, APR);
1304         if (mdp->cd->mpr)
1305                 sh_eth_write(ndev, MPR_MP, MPR);
1306         if (mdp->cd->tpauser)
1307                 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1308
1309         /* Setting the Rx mode will start the Rx process. */
1310         sh_eth_write(ndev, EDRRR_R, EDRRR);
1311
1312         return ret;
1313 }
1314
1315 static void sh_eth_dev_exit(struct net_device *ndev)
1316 {
1317         struct sh_eth_private *mdp = netdev_priv(ndev);
1318         int i;
1319
1320         /* Deactivate all TX descriptors, so DMA should stop at next
1321          * packet boundary if it's currently running
1322          */
1323         for (i = 0; i < mdp->num_tx_ring; i++)
1324                 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT);
1325
1326         /* Disable TX FIFO egress to MAC */
1327         sh_eth_rcv_snd_disable(ndev);
1328
1329         /* Stop RX DMA at next packet boundary */
1330         sh_eth_write(ndev, 0, EDRRR);
1331
1332         /* Aside from TX DMA, we can't tell when the hardware is
1333          * really stopped, so we need to reset to make sure.
1334          * Before doing that, wait for long enough to *probably*
1335          * finish transmitting the last packet and poll stats.
1336          */
1337         msleep(2); /* max frame time at 10 Mbps < 1250 us */
1338         sh_eth_get_stats(ndev);
1339         sh_eth_reset(ndev);
1340
1341         /* Set MAC address again */
1342         update_mac_address(ndev);
1343 }
1344
1345 /* free Tx skb function */
1346 static int sh_eth_txfree(struct net_device *ndev)
1347 {
1348         struct sh_eth_private *mdp = netdev_priv(ndev);
1349         struct sh_eth_txdesc *txdesc;
1350         int free_num = 0;
1351         int entry;
1352
1353         for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1354                 entry = mdp->dirty_tx % mdp->num_tx_ring;
1355                 txdesc = &mdp->tx_ring[entry];
1356                 if (txdesc->status & cpu_to_le32(TD_TACT))
1357                         break;
1358                 /* TACT bit must be checked before all the following reads */
1359                 dma_rmb();
1360                 netif_info(mdp, tx_done, ndev,
1361                            "tx entry %d status 0x%08x\n",
1362                            entry, le32_to_cpu(txdesc->status));
1363                 /* Free the original skb. */
1364                 if (mdp->tx_skbuff[entry]) {
1365                         dma_unmap_single(&ndev->dev, le32_to_cpu(txdesc->addr),
1366                                          le32_to_cpu(txdesc->len) >> 16,
1367                                          DMA_TO_DEVICE);
1368                         dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1369                         mdp->tx_skbuff[entry] = NULL;
1370                         free_num++;
1371                 }
1372                 txdesc->status = cpu_to_le32(TD_TFP);
1373                 if (entry >= mdp->num_tx_ring - 1)
1374                         txdesc->status |= cpu_to_le32(TD_TDLE);
1375
1376                 ndev->stats.tx_packets++;
1377                 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
1378         }
1379         return free_num;
1380 }
1381
1382 /* Packet receive function */
1383 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1384 {
1385         struct sh_eth_private *mdp = netdev_priv(ndev);
1386         struct sh_eth_rxdesc *rxdesc;
1387
1388         int entry = mdp->cur_rx % mdp->num_rx_ring;
1389         int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1390         int limit;
1391         struct sk_buff *skb;
1392         u32 desc_status;
1393         int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1394         dma_addr_t dma_addr;
1395         u16 pkt_len;
1396         u32 buf_len;
1397
1398         boguscnt = min(boguscnt, *quota);
1399         limit = boguscnt;
1400         rxdesc = &mdp->rx_ring[entry];
1401         while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
1402                 /* RACT bit must be checked before all the following reads */
1403                 dma_rmb();
1404                 desc_status = le32_to_cpu(rxdesc->status);
1405                 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL;
1406
1407                 if (--boguscnt < 0)
1408                         break;
1409
1410                 netif_info(mdp, rx_status, ndev,
1411                            "rx entry %d status 0x%08x len %d\n",
1412                            entry, desc_status, pkt_len);
1413
1414                 if (!(desc_status & RDFEND))
1415                         ndev->stats.rx_length_errors++;
1416
1417                 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1418                  * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1419                  * bit 0. However, in case of the R8A7740 and R7S72100
1420                  * the RFS bits are from bit 25 to bit 16. So, the
1421                  * driver needs right shifting by 16.
1422                  */
1423                 if (mdp->cd->shift_rd0)
1424                         desc_status >>= 16;
1425
1426                 skb = mdp->rx_skbuff[entry];
1427                 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1428                                    RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1429                         ndev->stats.rx_errors++;
1430                         if (desc_status & RD_RFS1)
1431                                 ndev->stats.rx_crc_errors++;
1432                         if (desc_status & RD_RFS2)
1433                                 ndev->stats.rx_frame_errors++;
1434                         if (desc_status & RD_RFS3)
1435                                 ndev->stats.rx_length_errors++;
1436                         if (desc_status & RD_RFS4)
1437                                 ndev->stats.rx_length_errors++;
1438                         if (desc_status & RD_RFS6)
1439                                 ndev->stats.rx_missed_errors++;
1440                         if (desc_status & RD_RFS10)
1441                                 ndev->stats.rx_over_errors++;
1442                 } else  if (skb) {
1443                         dma_addr = le32_to_cpu(rxdesc->addr);
1444                         if (!mdp->cd->hw_swap)
1445                                 sh_eth_soft_swap(
1446                                         phys_to_virt(ALIGN(dma_addr, 4)),
1447                                         pkt_len + 2);
1448                         mdp->rx_skbuff[entry] = NULL;
1449                         if (mdp->cd->rpadir)
1450                                 skb_reserve(skb, NET_IP_ALIGN);
1451                         dma_unmap_single(&ndev->dev, dma_addr,
1452                                          ALIGN(mdp->rx_buf_sz, 32),
1453                                          DMA_FROM_DEVICE);
1454                         skb_put(skb, pkt_len);
1455                         skb->protocol = eth_type_trans(skb, ndev);
1456                         netif_receive_skb(skb);
1457                         ndev->stats.rx_packets++;
1458                         ndev->stats.rx_bytes += pkt_len;
1459                         if (desc_status & RD_RFS8)
1460                                 ndev->stats.multicast++;
1461                 }
1462                 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1463                 rxdesc = &mdp->rx_ring[entry];
1464         }
1465
1466         /* Refill the Rx ring buffers. */
1467         for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1468                 entry = mdp->dirty_rx % mdp->num_rx_ring;
1469                 rxdesc = &mdp->rx_ring[entry];
1470                 /* The size of the buffer is 32 byte boundary. */
1471                 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1472                 rxdesc->len = cpu_to_le32(buf_len << 16);
1473
1474                 if (mdp->rx_skbuff[entry] == NULL) {
1475                         skb = netdev_alloc_skb(ndev, skbuff_size);
1476                         if (skb == NULL)
1477                                 break;  /* Better luck next round. */
1478                         sh_eth_set_receive_align(skb);
1479                         dma_addr = dma_map_single(&ndev->dev, skb->data,
1480                                                   buf_len, DMA_FROM_DEVICE);
1481                         if (dma_mapping_error(&ndev->dev, dma_addr)) {
1482                                 kfree_skb(skb);
1483                                 break;
1484                         }
1485                         mdp->rx_skbuff[entry] = skb;
1486
1487                         skb_checksum_none_assert(skb);
1488                         rxdesc->addr = cpu_to_le32(dma_addr);
1489                 }
1490                 dma_wmb(); /* RACT bit must be set after all the above writes */
1491                 if (entry >= mdp->num_rx_ring - 1)
1492                         rxdesc->status |=
1493                                 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE);
1494                 else
1495                         rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP);
1496         }
1497
1498         /* Restart Rx engine if stopped. */
1499         /* If we don't need to check status, don't. -KDU */
1500         if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1501                 /* fix the values for the next receiving if RDE is set */
1502                 if (intr_status & EESR_RDE &&
1503                     mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) {
1504                         u32 count = (sh_eth_read(ndev, RDFAR) -
1505                                      sh_eth_read(ndev, RDLAR)) >> 4;
1506
1507                         mdp->cur_rx = count;
1508                         mdp->dirty_rx = count;
1509                 }
1510                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1511         }
1512
1513         *quota -= limit - boguscnt - 1;
1514
1515         return *quota <= 0;
1516 }
1517
1518 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1519 {
1520         /* disable tx and rx */
1521         sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
1522 }
1523
1524 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1525 {
1526         /* enable tx and rx */
1527         sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
1528 }
1529
1530 /* error control function */
1531 static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1532 {
1533         struct sh_eth_private *mdp = netdev_priv(ndev);
1534         u32 felic_stat;
1535         u32 link_stat;
1536         u32 mask;
1537
1538         if (intr_status & EESR_ECI) {
1539                 felic_stat = sh_eth_read(ndev, ECSR);
1540                 sh_eth_write(ndev, felic_stat, ECSR);   /* clear int */
1541                 if (felic_stat & ECSR_ICD)
1542                         ndev->stats.tx_carrier_errors++;
1543                 if (felic_stat & ECSR_LCHNG) {
1544                         /* Link Changed */
1545                         if (mdp->cd->no_psr || mdp->no_ether_link) {
1546                                 goto ignore_link;
1547                         } else {
1548                                 link_stat = (sh_eth_read(ndev, PSR));
1549                                 if (mdp->ether_link_active_low)
1550                                         link_stat = ~link_stat;
1551                         }
1552                         if (!(link_stat & PHY_ST_LINK)) {
1553                                 sh_eth_rcv_snd_disable(ndev);
1554                         } else {
1555                                 /* Link Up */
1556                                 sh_eth_modify(ndev, EESIPR, DMAC_M_ECI, 0);
1557                                 /* clear int */
1558                                 sh_eth_modify(ndev, ECSR, 0, 0);
1559                                 sh_eth_modify(ndev, EESIPR, DMAC_M_ECI,
1560                                               DMAC_M_ECI);
1561                                 /* enable tx and rx */
1562                                 sh_eth_rcv_snd_enable(ndev);
1563                         }
1564                 }
1565         }
1566
1567 ignore_link:
1568         if (intr_status & EESR_TWB) {
1569                 /* Unused write back interrupt */
1570                 if (intr_status & EESR_TABT) {  /* Transmit Abort int */
1571                         ndev->stats.tx_aborted_errors++;
1572                         netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1573                 }
1574         }
1575
1576         if (intr_status & EESR_RABT) {
1577                 /* Receive Abort int */
1578                 if (intr_status & EESR_RFRMER) {
1579                         /* Receive Frame Overflow int */
1580                         ndev->stats.rx_frame_errors++;
1581                 }
1582         }
1583
1584         if (intr_status & EESR_TDE) {
1585                 /* Transmit Descriptor Empty int */
1586                 ndev->stats.tx_fifo_errors++;
1587                 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1588         }
1589
1590         if (intr_status & EESR_TFE) {
1591                 /* FIFO under flow */
1592                 ndev->stats.tx_fifo_errors++;
1593                 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1594         }
1595
1596         if (intr_status & EESR_RDE) {
1597                 /* Receive Descriptor Empty int */
1598                 ndev->stats.rx_over_errors++;
1599         }
1600
1601         if (intr_status & EESR_RFE) {
1602                 /* Receive FIFO Overflow int */
1603                 ndev->stats.rx_fifo_errors++;
1604         }
1605
1606         if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1607                 /* Address Error */
1608                 ndev->stats.tx_fifo_errors++;
1609                 netif_err(mdp, tx_err, ndev, "Address Error\n");
1610         }
1611
1612         mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1613         if (mdp->cd->no_ade)
1614                 mask &= ~EESR_ADE;
1615         if (intr_status & mask) {
1616                 /* Tx error */
1617                 u32 edtrr = sh_eth_read(ndev, EDTRR);
1618
1619                 /* dmesg */
1620                 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1621                            intr_status, mdp->cur_tx, mdp->dirty_tx,
1622                            (u32)ndev->state, edtrr);
1623                 /* dirty buffer free */
1624                 sh_eth_txfree(ndev);
1625
1626                 /* SH7712 BUG */
1627                 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1628                         /* tx dma start */
1629                         sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1630                 }
1631                 /* wakeup */
1632                 netif_wake_queue(ndev);
1633         }
1634 }
1635
1636 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1637 {
1638         struct net_device *ndev = netdev;
1639         struct sh_eth_private *mdp = netdev_priv(ndev);
1640         struct sh_eth_cpu_data *cd = mdp->cd;
1641         irqreturn_t ret = IRQ_NONE;
1642         u32 intr_status, intr_enable;
1643
1644         spin_lock(&mdp->lock);
1645
1646         /* Get interrupt status */
1647         intr_status = sh_eth_read(ndev, EESR);
1648         /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1649          * enabled since it's the one that  comes thru regardless of the mask,
1650          * and we need to fully handle it in sh_eth_error() in order to quench
1651          * it as it doesn't get cleared by just writing 1 to the ECI bit...
1652          */
1653         intr_enable = sh_eth_read(ndev, EESIPR);
1654         intr_status &= intr_enable | DMAC_M_ECI;
1655         if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
1656                 ret = IRQ_HANDLED;
1657         else
1658                 goto out;
1659
1660         if (!likely(mdp->irq_enabled)) {
1661                 sh_eth_write(ndev, 0, EESIPR);
1662                 goto out;
1663         }
1664
1665         if (intr_status & EESR_RX_CHECK) {
1666                 if (napi_schedule_prep(&mdp->napi)) {
1667                         /* Mask Rx interrupts */
1668                         sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1669                                      EESIPR);
1670                         __napi_schedule(&mdp->napi);
1671                 } else {
1672                         netdev_warn(ndev,
1673                                     "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1674                                     intr_status, intr_enable);
1675                 }
1676         }
1677
1678         /* Tx Check */
1679         if (intr_status & cd->tx_check) {
1680                 /* Clear Tx interrupts */
1681                 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1682
1683                 sh_eth_txfree(ndev);
1684                 netif_wake_queue(ndev);
1685         }
1686
1687         if (intr_status & cd->eesr_err_check) {
1688                 /* Clear error interrupts */
1689                 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1690
1691                 sh_eth_error(ndev, intr_status);
1692         }
1693
1694 out:
1695         spin_unlock(&mdp->lock);
1696
1697         return ret;
1698 }
1699
1700 static int sh_eth_poll(struct napi_struct *napi, int budget)
1701 {
1702         struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1703                                                   napi);
1704         struct net_device *ndev = napi->dev;
1705         int quota = budget;
1706         u32 intr_status;
1707
1708         for (;;) {
1709                 intr_status = sh_eth_read(ndev, EESR);
1710                 if (!(intr_status & EESR_RX_CHECK))
1711                         break;
1712                 /* Clear Rx interrupts */
1713                 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1714
1715                 if (sh_eth_rx(ndev, intr_status, &quota))
1716                         goto out;
1717         }
1718
1719         napi_complete(napi);
1720
1721         /* Reenable Rx interrupts */
1722         if (mdp->irq_enabled)
1723                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1724 out:
1725         return budget - quota;
1726 }
1727
1728 /* PHY state control function */
1729 static void sh_eth_adjust_link(struct net_device *ndev)
1730 {
1731         struct sh_eth_private *mdp = netdev_priv(ndev);
1732         struct phy_device *phydev = mdp->phydev;
1733         int new_state = 0;
1734
1735         if (phydev->link) {
1736                 if (phydev->duplex != mdp->duplex) {
1737                         new_state = 1;
1738                         mdp->duplex = phydev->duplex;
1739                         if (mdp->cd->set_duplex)
1740                                 mdp->cd->set_duplex(ndev);
1741                 }
1742
1743                 if (phydev->speed != mdp->speed) {
1744                         new_state = 1;
1745                         mdp->speed = phydev->speed;
1746                         if (mdp->cd->set_rate)
1747                                 mdp->cd->set_rate(ndev);
1748                 }
1749                 if (!mdp->link) {
1750                         sh_eth_modify(ndev, ECMR, ECMR_TXF, 0);
1751                         new_state = 1;
1752                         mdp->link = phydev->link;
1753                         if (mdp->cd->no_psr || mdp->no_ether_link)
1754                                 sh_eth_rcv_snd_enable(ndev);
1755                 }
1756         } else if (mdp->link) {
1757                 new_state = 1;
1758                 mdp->link = 0;
1759                 mdp->speed = 0;
1760                 mdp->duplex = -1;
1761                 if (mdp->cd->no_psr || mdp->no_ether_link)
1762                         sh_eth_rcv_snd_disable(ndev);
1763         }
1764
1765         if (new_state && netif_msg_link(mdp))
1766                 phy_print_status(phydev);
1767 }
1768
1769 /* PHY init function */
1770 static int sh_eth_phy_init(struct net_device *ndev)
1771 {
1772         struct device_node *np = ndev->dev.parent->of_node;
1773         struct sh_eth_private *mdp = netdev_priv(ndev);
1774         struct phy_device *phydev;
1775
1776         mdp->link = 0;
1777         mdp->speed = 0;
1778         mdp->duplex = -1;
1779
1780         /* Try connect to PHY */
1781         if (np) {
1782                 struct device_node *pn;
1783
1784                 pn = of_parse_phandle(np, "phy-handle", 0);
1785                 phydev = of_phy_connect(ndev, pn,
1786                                         sh_eth_adjust_link, 0,
1787                                         mdp->phy_interface);
1788
1789                 if (!phydev)
1790                         phydev = ERR_PTR(-ENOENT);
1791         } else {
1792                 char phy_id[MII_BUS_ID_SIZE + 3];
1793
1794                 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1795                          mdp->mii_bus->id, mdp->phy_id);
1796
1797                 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1798                                      mdp->phy_interface);
1799         }
1800
1801         if (IS_ERR(phydev)) {
1802                 netdev_err(ndev, "failed to connect PHY\n");
1803                 return PTR_ERR(phydev);
1804         }
1805
1806         phy_attached_info(phydev);
1807
1808         mdp->phydev = phydev;
1809
1810         return 0;
1811 }
1812
1813 /* PHY control start function */
1814 static int sh_eth_phy_start(struct net_device *ndev)
1815 {
1816         struct sh_eth_private *mdp = netdev_priv(ndev);
1817         int ret;
1818
1819         ret = sh_eth_phy_init(ndev);
1820         if (ret)
1821                 return ret;
1822
1823         phy_start(mdp->phydev);
1824
1825         return 0;
1826 }
1827
1828 static int sh_eth_get_settings(struct net_device *ndev,
1829                                struct ethtool_cmd *ecmd)
1830 {
1831         struct sh_eth_private *mdp = netdev_priv(ndev);
1832         unsigned long flags;
1833         int ret;
1834
1835         if (!mdp->phydev)
1836                 return -ENODEV;
1837
1838         spin_lock_irqsave(&mdp->lock, flags);
1839         ret = phy_ethtool_gset(mdp->phydev, ecmd);
1840         spin_unlock_irqrestore(&mdp->lock, flags);
1841
1842         return ret;
1843 }
1844
1845 static int sh_eth_set_settings(struct net_device *ndev,
1846                                struct ethtool_cmd *ecmd)
1847 {
1848         struct sh_eth_private *mdp = netdev_priv(ndev);
1849         unsigned long flags;
1850         int ret;
1851
1852         if (!mdp->phydev)
1853                 return -ENODEV;
1854
1855         spin_lock_irqsave(&mdp->lock, flags);
1856
1857         /* disable tx and rx */
1858         sh_eth_rcv_snd_disable(ndev);
1859
1860         ret = phy_ethtool_sset(mdp->phydev, ecmd);
1861         if (ret)
1862                 goto error_exit;
1863
1864         if (ecmd->duplex == DUPLEX_FULL)
1865                 mdp->duplex = 1;
1866         else
1867                 mdp->duplex = 0;
1868
1869         if (mdp->cd->set_duplex)
1870                 mdp->cd->set_duplex(ndev);
1871
1872 error_exit:
1873         mdelay(1);
1874
1875         /* enable tx and rx */
1876         sh_eth_rcv_snd_enable(ndev);
1877
1878         spin_unlock_irqrestore(&mdp->lock, flags);
1879
1880         return ret;
1881 }
1882
1883 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
1884  * version must be bumped as well.  Just adding registers up to that
1885  * limit is fine, as long as the existing register indices don't
1886  * change.
1887  */
1888 #define SH_ETH_REG_DUMP_VERSION         1
1889 #define SH_ETH_REG_DUMP_MAX_REGS        256
1890
1891 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
1892 {
1893         struct sh_eth_private *mdp = netdev_priv(ndev);
1894         struct sh_eth_cpu_data *cd = mdp->cd;
1895         u32 *valid_map;
1896         size_t len;
1897
1898         BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
1899
1900         /* Dump starts with a bitmap that tells ethtool which
1901          * registers are defined for this chip.
1902          */
1903         len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
1904         if (buf) {
1905                 valid_map = buf;
1906                 buf += len;
1907         } else {
1908                 valid_map = NULL;
1909         }
1910
1911         /* Add a register to the dump, if it has a defined offset.
1912          * This automatically skips most undefined registers, but for
1913          * some it is also necessary to check a capability flag in
1914          * struct sh_eth_cpu_data.
1915          */
1916 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
1917 #define add_reg_from(reg, read_expr) do {                               \
1918                 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) {    \
1919                         if (buf) {                                      \
1920                                 mark_reg_valid(reg);                    \
1921                                 *buf++ = read_expr;                     \
1922                         }                                               \
1923                         ++len;                                          \
1924                 }                                                       \
1925         } while (0)
1926 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
1927 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
1928
1929         add_reg(EDSR);
1930         add_reg(EDMR);
1931         add_reg(EDTRR);
1932         add_reg(EDRRR);
1933         add_reg(EESR);
1934         add_reg(EESIPR);
1935         add_reg(TDLAR);
1936         add_reg(TDFAR);
1937         add_reg(TDFXR);
1938         add_reg(TDFFR);
1939         add_reg(RDLAR);
1940         add_reg(RDFAR);
1941         add_reg(RDFXR);
1942         add_reg(RDFFR);
1943         add_reg(TRSCER);
1944         add_reg(RMFCR);
1945         add_reg(TFTR);
1946         add_reg(FDR);
1947         add_reg(RMCR);
1948         add_reg(TFUCR);
1949         add_reg(RFOCR);
1950         if (cd->rmiimode)
1951                 add_reg(RMIIMODE);
1952         add_reg(FCFTR);
1953         if (cd->rpadir)
1954                 add_reg(RPADIR);
1955         if (!cd->no_trimd)
1956                 add_reg(TRIMD);
1957         add_reg(ECMR);
1958         add_reg(ECSR);
1959         add_reg(ECSIPR);
1960         add_reg(PIR);
1961         if (!cd->no_psr)
1962                 add_reg(PSR);
1963         add_reg(RDMLR);
1964         add_reg(RFLR);
1965         add_reg(IPGR);
1966         if (cd->apr)
1967                 add_reg(APR);
1968         if (cd->mpr)
1969                 add_reg(MPR);
1970         add_reg(RFCR);
1971         add_reg(RFCF);
1972         if (cd->tpauser)
1973                 add_reg(TPAUSER);
1974         add_reg(TPAUSECR);
1975         add_reg(GECMR);
1976         if (cd->bculr)
1977                 add_reg(BCULR);
1978         add_reg(MAHR);
1979         add_reg(MALR);
1980         add_reg(TROCR);
1981         add_reg(CDCR);
1982         add_reg(LCCR);
1983         add_reg(CNDCR);
1984         add_reg(CEFCR);
1985         add_reg(FRECR);
1986         add_reg(TSFRCR);
1987         add_reg(TLFRCR);
1988         add_reg(CERCR);
1989         add_reg(CEECR);
1990         add_reg(MAFCR);
1991         if (cd->rtrate)
1992                 add_reg(RTRATE);
1993         if (cd->hw_crc)
1994                 add_reg(CSMR);
1995         if (cd->select_mii)
1996                 add_reg(RMII_MII);
1997         add_reg(ARSTR);
1998         if (cd->tsu) {
1999                 add_tsu_reg(TSU_CTRST);
2000                 add_tsu_reg(TSU_FWEN0);
2001                 add_tsu_reg(TSU_FWEN1);
2002                 add_tsu_reg(TSU_FCM);
2003                 add_tsu_reg(TSU_BSYSL0);
2004                 add_tsu_reg(TSU_BSYSL1);
2005                 add_tsu_reg(TSU_PRISL0);
2006                 add_tsu_reg(TSU_PRISL1);
2007                 add_tsu_reg(TSU_FWSL0);
2008                 add_tsu_reg(TSU_FWSL1);
2009                 add_tsu_reg(TSU_FWSLC);
2010                 add_tsu_reg(TSU_QTAG0);
2011                 add_tsu_reg(TSU_QTAG1);
2012                 add_tsu_reg(TSU_QTAGM0);
2013                 add_tsu_reg(TSU_QTAGM1);
2014                 add_tsu_reg(TSU_FWSR);
2015                 add_tsu_reg(TSU_FWINMK);
2016                 add_tsu_reg(TSU_ADQT0);
2017                 add_tsu_reg(TSU_ADQT1);
2018                 add_tsu_reg(TSU_VTAG0);
2019                 add_tsu_reg(TSU_VTAG1);
2020                 add_tsu_reg(TSU_ADSBSY);
2021                 add_tsu_reg(TSU_TEN);
2022                 add_tsu_reg(TSU_POST1);
2023                 add_tsu_reg(TSU_POST2);
2024                 add_tsu_reg(TSU_POST3);
2025                 add_tsu_reg(TSU_POST4);
2026                 if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) {
2027                         /* This is the start of a table, not just a single
2028                          * register.
2029                          */
2030                         if (buf) {
2031                                 unsigned int i;
2032
2033                                 mark_reg_valid(TSU_ADRH0);
2034                                 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2035                                         *buf++ = ioread32(
2036                                                 mdp->tsu_addr +
2037                                                 mdp->reg_offset[TSU_ADRH0] +
2038                                                 i * 4);
2039                         }
2040                         len += SH_ETH_TSU_CAM_ENTRIES * 2;
2041                 }
2042         }
2043
2044 #undef mark_reg_valid
2045 #undef add_reg_from
2046 #undef add_reg
2047 #undef add_tsu_reg
2048
2049         return len * 4;
2050 }
2051
2052 static int sh_eth_get_regs_len(struct net_device *ndev)
2053 {
2054         return __sh_eth_get_regs(ndev, NULL);
2055 }
2056
2057 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2058                             void *buf)
2059 {
2060         struct sh_eth_private *mdp = netdev_priv(ndev);
2061
2062         regs->version = SH_ETH_REG_DUMP_VERSION;
2063
2064         pm_runtime_get_sync(&mdp->pdev->dev);
2065         __sh_eth_get_regs(ndev, buf);
2066         pm_runtime_put_sync(&mdp->pdev->dev);
2067 }
2068
2069 static int sh_eth_nway_reset(struct net_device *ndev)
2070 {
2071         struct sh_eth_private *mdp = netdev_priv(ndev);
2072         unsigned long flags;
2073         int ret;
2074
2075         if (!mdp->phydev)
2076                 return -ENODEV;
2077
2078         spin_lock_irqsave(&mdp->lock, flags);
2079         ret = phy_start_aneg(mdp->phydev);
2080         spin_unlock_irqrestore(&mdp->lock, flags);
2081
2082         return ret;
2083 }
2084
2085 static u32 sh_eth_get_msglevel(struct net_device *ndev)
2086 {
2087         struct sh_eth_private *mdp = netdev_priv(ndev);
2088         return mdp->msg_enable;
2089 }
2090
2091 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2092 {
2093         struct sh_eth_private *mdp = netdev_priv(ndev);
2094         mdp->msg_enable = value;
2095 }
2096
2097 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2098         "rx_current", "tx_current",
2099         "rx_dirty", "tx_dirty",
2100 };
2101 #define SH_ETH_STATS_LEN  ARRAY_SIZE(sh_eth_gstrings_stats)
2102
2103 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2104 {
2105         switch (sset) {
2106         case ETH_SS_STATS:
2107                 return SH_ETH_STATS_LEN;
2108         default:
2109                 return -EOPNOTSUPP;
2110         }
2111 }
2112
2113 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
2114                                      struct ethtool_stats *stats, u64 *data)
2115 {
2116         struct sh_eth_private *mdp = netdev_priv(ndev);
2117         int i = 0;
2118
2119         /* device-specific stats */
2120         data[i++] = mdp->cur_rx;
2121         data[i++] = mdp->cur_tx;
2122         data[i++] = mdp->dirty_rx;
2123         data[i++] = mdp->dirty_tx;
2124 }
2125
2126 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2127 {
2128         switch (stringset) {
2129         case ETH_SS_STATS:
2130                 memcpy(data, *sh_eth_gstrings_stats,
2131                        sizeof(sh_eth_gstrings_stats));
2132                 break;
2133         }
2134 }
2135
2136 static void sh_eth_get_ringparam(struct net_device *ndev,
2137                                  struct ethtool_ringparam *ring)
2138 {
2139         struct sh_eth_private *mdp = netdev_priv(ndev);
2140
2141         ring->rx_max_pending = RX_RING_MAX;
2142         ring->tx_max_pending = TX_RING_MAX;
2143         ring->rx_pending = mdp->num_rx_ring;
2144         ring->tx_pending = mdp->num_tx_ring;
2145 }
2146
2147 static int sh_eth_set_ringparam(struct net_device *ndev,
2148                                 struct ethtool_ringparam *ring)
2149 {
2150         struct sh_eth_private *mdp = netdev_priv(ndev);
2151         int ret;
2152
2153         if (ring->tx_pending > TX_RING_MAX ||
2154             ring->rx_pending > RX_RING_MAX ||
2155             ring->tx_pending < TX_RING_MIN ||
2156             ring->rx_pending < RX_RING_MIN)
2157                 return -EINVAL;
2158         if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2159                 return -EINVAL;
2160
2161         if (netif_running(ndev)) {
2162                 netif_device_detach(ndev);
2163                 netif_tx_disable(ndev);
2164
2165                 /* Serialise with the interrupt handler and NAPI, then
2166                  * disable interrupts.  We have to clear the
2167                  * irq_enabled flag first to ensure that interrupts
2168                  * won't be re-enabled.
2169                  */
2170                 mdp->irq_enabled = false;
2171                 synchronize_irq(ndev->irq);
2172                 napi_synchronize(&mdp->napi);
2173                 sh_eth_write(ndev, 0x0000, EESIPR);
2174
2175                 sh_eth_dev_exit(ndev);
2176
2177                 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
2178                 sh_eth_ring_free(ndev);
2179         }
2180
2181         /* Set new parameters */
2182         mdp->num_rx_ring = ring->rx_pending;
2183         mdp->num_tx_ring = ring->tx_pending;
2184
2185         if (netif_running(ndev)) {
2186                 ret = sh_eth_ring_init(ndev);
2187                 if (ret < 0) {
2188                         netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2189                                    __func__);
2190                         return ret;
2191                 }
2192                 ret = sh_eth_dev_init(ndev);
2193                 if (ret < 0) {
2194                         netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2195                                    __func__);
2196                         return ret;
2197                 }
2198
2199                 netif_device_attach(ndev);
2200         }
2201
2202         return 0;
2203 }
2204
2205 static const struct ethtool_ops sh_eth_ethtool_ops = {
2206         .get_settings   = sh_eth_get_settings,
2207         .set_settings   = sh_eth_set_settings,
2208         .get_regs_len   = sh_eth_get_regs_len,
2209         .get_regs       = sh_eth_get_regs,
2210         .nway_reset     = sh_eth_nway_reset,
2211         .get_msglevel   = sh_eth_get_msglevel,
2212         .set_msglevel   = sh_eth_set_msglevel,
2213         .get_link       = ethtool_op_get_link,
2214         .get_strings    = sh_eth_get_strings,
2215         .get_ethtool_stats  = sh_eth_get_ethtool_stats,
2216         .get_sset_count     = sh_eth_get_sset_count,
2217         .get_ringparam  = sh_eth_get_ringparam,
2218         .set_ringparam  = sh_eth_set_ringparam,
2219 };
2220
2221 /* network device open function */
2222 static int sh_eth_open(struct net_device *ndev)
2223 {
2224         struct sh_eth_private *mdp = netdev_priv(ndev);
2225         int ret;
2226
2227         pm_runtime_get_sync(&mdp->pdev->dev);
2228
2229         napi_enable(&mdp->napi);
2230
2231         ret = request_irq(ndev->irq, sh_eth_interrupt,
2232                           mdp->cd->irq_flags, ndev->name, ndev);
2233         if (ret) {
2234                 netdev_err(ndev, "Can not assign IRQ number\n");
2235                 goto out_napi_off;
2236         }
2237
2238         /* Descriptor set */
2239         ret = sh_eth_ring_init(ndev);
2240         if (ret)
2241                 goto out_free_irq;
2242
2243         /* device init */
2244         ret = sh_eth_dev_init(ndev);
2245         if (ret)
2246                 goto out_free_irq;
2247
2248         /* PHY control start*/
2249         ret = sh_eth_phy_start(ndev);
2250         if (ret)
2251                 goto out_free_irq;
2252
2253         netif_start_queue(ndev);
2254
2255         mdp->is_opened = 1;
2256
2257         return ret;
2258
2259 out_free_irq:
2260         free_irq(ndev->irq, ndev);
2261 out_napi_off:
2262         napi_disable(&mdp->napi);
2263         pm_runtime_put_sync(&mdp->pdev->dev);
2264         return ret;
2265 }
2266
2267 /* Timeout function */
2268 static void sh_eth_tx_timeout(struct net_device *ndev)
2269 {
2270         struct sh_eth_private *mdp = netdev_priv(ndev);
2271         struct sh_eth_rxdesc *rxdesc;
2272         int i;
2273
2274         netif_stop_queue(ndev);
2275
2276         netif_err(mdp, timer, ndev,
2277                   "transmit timed out, status %8.8x, resetting...\n",
2278                   sh_eth_read(ndev, EESR));
2279
2280         /* tx_errors count up */
2281         ndev->stats.tx_errors++;
2282
2283         /* Free all the skbuffs in the Rx queue. */
2284         for (i = 0; i < mdp->num_rx_ring; i++) {
2285                 rxdesc = &mdp->rx_ring[i];
2286                 rxdesc->status = cpu_to_le32(0);
2287                 rxdesc->addr = cpu_to_le32(0xBADF00D0);
2288                 dev_kfree_skb(mdp->rx_skbuff[i]);
2289                 mdp->rx_skbuff[i] = NULL;
2290         }
2291         for (i = 0; i < mdp->num_tx_ring; i++) {
2292                 dev_kfree_skb(mdp->tx_skbuff[i]);
2293                 mdp->tx_skbuff[i] = NULL;
2294         }
2295
2296         /* device init */
2297         sh_eth_dev_init(ndev);
2298
2299         netif_start_queue(ndev);
2300 }
2301
2302 /* Packet transmit function */
2303 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2304 {
2305         struct sh_eth_private *mdp = netdev_priv(ndev);
2306         struct sh_eth_txdesc *txdesc;
2307         dma_addr_t dma_addr;
2308         u32 entry;
2309         unsigned long flags;
2310
2311         spin_lock_irqsave(&mdp->lock, flags);
2312         if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2313                 if (!sh_eth_txfree(ndev)) {
2314                         netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2315                         netif_stop_queue(ndev);
2316                         spin_unlock_irqrestore(&mdp->lock, flags);
2317                         return NETDEV_TX_BUSY;
2318                 }
2319         }
2320         spin_unlock_irqrestore(&mdp->lock, flags);
2321
2322         if (skb_put_padto(skb, ETH_ZLEN))
2323                 return NETDEV_TX_OK;
2324
2325         entry = mdp->cur_tx % mdp->num_tx_ring;
2326         mdp->tx_skbuff[entry] = skb;
2327         txdesc = &mdp->tx_ring[entry];
2328         /* soft swap. */
2329         if (!mdp->cd->hw_swap)
2330                 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
2331         dma_addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2332                                   DMA_TO_DEVICE);
2333         if (dma_mapping_error(&ndev->dev, dma_addr)) {
2334                 kfree_skb(skb);
2335                 return NETDEV_TX_OK;
2336         }
2337         txdesc->addr = cpu_to_le32(dma_addr);
2338         txdesc->len  = cpu_to_le32(skb->len << 16);
2339
2340         dma_wmb(); /* TACT bit must be set after all the above writes */
2341         if (entry >= mdp->num_tx_ring - 1)
2342                 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
2343         else
2344                 txdesc->status |= cpu_to_le32(TD_TACT);
2345
2346         mdp->cur_tx++;
2347
2348         if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2349                 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2350
2351         return NETDEV_TX_OK;
2352 }
2353
2354 /* The statistics registers have write-clear behaviour, which means we
2355  * will lose any increment between the read and write.  We mitigate
2356  * this by only clearing when we read a non-zero value, so we will
2357  * never falsely report a total of zero.
2358  */
2359 static void
2360 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2361 {
2362         u32 delta = sh_eth_read(ndev, reg);
2363
2364         if (delta) {
2365                 *stat += delta;
2366                 sh_eth_write(ndev, 0, reg);
2367         }
2368 }
2369
2370 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2371 {
2372         struct sh_eth_private *mdp = netdev_priv(ndev);
2373
2374         if (sh_eth_is_rz_fast_ether(mdp))
2375                 return &ndev->stats;
2376
2377         if (!mdp->is_opened)
2378                 return &ndev->stats;
2379
2380         sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2381         sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2382         sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
2383
2384         if (sh_eth_is_gether(mdp)) {
2385                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2386                                    CERCR);
2387                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2388                                    CEECR);
2389         } else {
2390                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2391                                    CNDCR);
2392         }
2393
2394         return &ndev->stats;
2395 }
2396
2397 /* device close function */
2398 static int sh_eth_close(struct net_device *ndev)
2399 {
2400         struct sh_eth_private *mdp = netdev_priv(ndev);
2401
2402         netif_stop_queue(ndev);
2403
2404         /* Serialise with the interrupt handler and NAPI, then disable
2405          * interrupts.  We have to clear the irq_enabled flag first to
2406          * ensure that interrupts won't be re-enabled.
2407          */
2408         mdp->irq_enabled = false;
2409         synchronize_irq(ndev->irq);
2410         napi_disable(&mdp->napi);
2411         sh_eth_write(ndev, 0x0000, EESIPR);
2412
2413         sh_eth_dev_exit(ndev);
2414
2415         /* PHY Disconnect */
2416         if (mdp->phydev) {
2417                 phy_stop(mdp->phydev);
2418                 phy_disconnect(mdp->phydev);
2419                 mdp->phydev = NULL;
2420         }
2421
2422         free_irq(ndev->irq, ndev);
2423
2424         /* Free all the skbuffs in the Rx queue and the DMA buffer. */
2425         sh_eth_ring_free(ndev);
2426
2427         pm_runtime_put_sync(&mdp->pdev->dev);
2428
2429         mdp->is_opened = 0;
2430
2431         return 0;
2432 }
2433
2434 /* ioctl to device function */
2435 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2436 {
2437         struct sh_eth_private *mdp = netdev_priv(ndev);
2438         struct phy_device *phydev = mdp->phydev;
2439
2440         if (!netif_running(ndev))
2441                 return -EINVAL;
2442
2443         if (!phydev)
2444                 return -ENODEV;
2445
2446         return phy_mii_ioctl(phydev, rq, cmd);
2447 }
2448
2449 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2450 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2451                                             int entry)
2452 {
2453         return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2454 }
2455
2456 static u32 sh_eth_tsu_get_post_mask(int entry)
2457 {
2458         return 0x0f << (28 - ((entry % 8) * 4));
2459 }
2460
2461 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2462 {
2463         return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2464 }
2465
2466 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2467                                              int entry)
2468 {
2469         struct sh_eth_private *mdp = netdev_priv(ndev);
2470         u32 tmp;
2471         void *reg_offset;
2472
2473         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2474         tmp = ioread32(reg_offset);
2475         iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2476 }
2477
2478 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2479                                               int entry)
2480 {
2481         struct sh_eth_private *mdp = netdev_priv(ndev);
2482         u32 post_mask, ref_mask, tmp;
2483         void *reg_offset;
2484
2485         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2486         post_mask = sh_eth_tsu_get_post_mask(entry);
2487         ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2488
2489         tmp = ioread32(reg_offset);
2490         iowrite32(tmp & ~post_mask, reg_offset);
2491
2492         /* If other port enables, the function returns "true" */
2493         return tmp & ref_mask;
2494 }
2495
2496 static int sh_eth_tsu_busy(struct net_device *ndev)
2497 {
2498         int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2499         struct sh_eth_private *mdp = netdev_priv(ndev);
2500
2501         while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2502                 udelay(10);
2503                 timeout--;
2504                 if (timeout <= 0) {
2505                         netdev_err(ndev, "%s: timeout\n", __func__);
2506                         return -ETIMEDOUT;
2507                 }
2508         }
2509
2510         return 0;
2511 }
2512
2513 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2514                                   const u8 *addr)
2515 {
2516         u32 val;
2517
2518         val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2519         iowrite32(val, reg);
2520         if (sh_eth_tsu_busy(ndev) < 0)
2521                 return -EBUSY;
2522
2523         val = addr[4] << 8 | addr[5];
2524         iowrite32(val, reg + 4);
2525         if (sh_eth_tsu_busy(ndev) < 0)
2526                 return -EBUSY;
2527
2528         return 0;
2529 }
2530
2531 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2532 {
2533         u32 val;
2534
2535         val = ioread32(reg);
2536         addr[0] = (val >> 24) & 0xff;
2537         addr[1] = (val >> 16) & 0xff;
2538         addr[2] = (val >> 8) & 0xff;
2539         addr[3] = val & 0xff;
2540         val = ioread32(reg + 4);
2541         addr[4] = (val >> 8) & 0xff;
2542         addr[5] = val & 0xff;
2543 }
2544
2545
2546 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2547 {
2548         struct sh_eth_private *mdp = netdev_priv(ndev);
2549         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2550         int i;
2551         u8 c_addr[ETH_ALEN];
2552
2553         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2554                 sh_eth_tsu_read_entry(reg_offset, c_addr);
2555                 if (ether_addr_equal(addr, c_addr))
2556                         return i;
2557         }
2558
2559         return -ENOENT;
2560 }
2561
2562 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2563 {
2564         u8 blank[ETH_ALEN];
2565         int entry;
2566
2567         memset(blank, 0, sizeof(blank));
2568         entry = sh_eth_tsu_find_entry(ndev, blank);
2569         return (entry < 0) ? -ENOMEM : entry;
2570 }
2571
2572 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2573                                               int entry)
2574 {
2575         struct sh_eth_private *mdp = netdev_priv(ndev);
2576         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2577         int ret;
2578         u8 blank[ETH_ALEN];
2579
2580         sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2581                          ~(1 << (31 - entry)), TSU_TEN);
2582
2583         memset(blank, 0, sizeof(blank));
2584         ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2585         if (ret < 0)
2586                 return ret;
2587         return 0;
2588 }
2589
2590 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2591 {
2592         struct sh_eth_private *mdp = netdev_priv(ndev);
2593         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2594         int i, ret;
2595
2596         if (!mdp->cd->tsu)
2597                 return 0;
2598
2599         i = sh_eth_tsu_find_entry(ndev, addr);
2600         if (i < 0) {
2601                 /* No entry found, create one */
2602                 i = sh_eth_tsu_find_empty(ndev);
2603                 if (i < 0)
2604                         return -ENOMEM;
2605                 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2606                 if (ret < 0)
2607                         return ret;
2608
2609                 /* Enable the entry */
2610                 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2611                                  (1 << (31 - i)), TSU_TEN);
2612         }
2613
2614         /* Entry found or created, enable POST */
2615         sh_eth_tsu_enable_cam_entry_post(ndev, i);
2616
2617         return 0;
2618 }
2619
2620 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2621 {
2622         struct sh_eth_private *mdp = netdev_priv(ndev);
2623         int i, ret;
2624
2625         if (!mdp->cd->tsu)
2626                 return 0;
2627
2628         i = sh_eth_tsu_find_entry(ndev, addr);
2629         if (i) {
2630                 /* Entry found */
2631                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2632                         goto done;
2633
2634                 /* Disable the entry if both ports was disabled */
2635                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2636                 if (ret < 0)
2637                         return ret;
2638         }
2639 done:
2640         return 0;
2641 }
2642
2643 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2644 {
2645         struct sh_eth_private *mdp = netdev_priv(ndev);
2646         int i, ret;
2647
2648         if (!mdp->cd->tsu)
2649                 return 0;
2650
2651         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2652                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2653                         continue;
2654
2655                 /* Disable the entry if both ports was disabled */
2656                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2657                 if (ret < 0)
2658                         return ret;
2659         }
2660
2661         return 0;
2662 }
2663
2664 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2665 {
2666         struct sh_eth_private *mdp = netdev_priv(ndev);
2667         u8 addr[ETH_ALEN];
2668         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2669         int i;
2670
2671         if (!mdp->cd->tsu)
2672                 return;
2673
2674         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2675                 sh_eth_tsu_read_entry(reg_offset, addr);
2676                 if (is_multicast_ether_addr(addr))
2677                         sh_eth_tsu_del_entry(ndev, addr);
2678         }
2679 }
2680
2681 /* Update promiscuous flag and multicast filter */
2682 static void sh_eth_set_rx_mode(struct net_device *ndev)
2683 {
2684         struct sh_eth_private *mdp = netdev_priv(ndev);
2685         u32 ecmr_bits;
2686         int mcast_all = 0;
2687         unsigned long flags;
2688
2689         spin_lock_irqsave(&mdp->lock, flags);
2690         /* Initial condition is MCT = 1, PRM = 0.
2691          * Depending on ndev->flags, set PRM or clear MCT
2692          */
2693         ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2694         if (mdp->cd->tsu)
2695                 ecmr_bits |= ECMR_MCT;
2696
2697         if (!(ndev->flags & IFF_MULTICAST)) {
2698                 sh_eth_tsu_purge_mcast(ndev);
2699                 mcast_all = 1;
2700         }
2701         if (ndev->flags & IFF_ALLMULTI) {
2702                 sh_eth_tsu_purge_mcast(ndev);
2703                 ecmr_bits &= ~ECMR_MCT;
2704                 mcast_all = 1;
2705         }
2706
2707         if (ndev->flags & IFF_PROMISC) {
2708                 sh_eth_tsu_purge_all(ndev);
2709                 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2710         } else if (mdp->cd->tsu) {
2711                 struct netdev_hw_addr *ha;
2712                 netdev_for_each_mc_addr(ha, ndev) {
2713                         if (mcast_all && is_multicast_ether_addr(ha->addr))
2714                                 continue;
2715
2716                         if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2717                                 if (!mcast_all) {
2718                                         sh_eth_tsu_purge_mcast(ndev);
2719                                         ecmr_bits &= ~ECMR_MCT;
2720                                         mcast_all = 1;
2721                                 }
2722                         }
2723                 }
2724         }
2725
2726         /* update the ethernet mode */
2727         sh_eth_write(ndev, ecmr_bits, ECMR);
2728
2729         spin_unlock_irqrestore(&mdp->lock, flags);
2730 }
2731
2732 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2733 {
2734         if (!mdp->port)
2735                 return TSU_VTAG0;
2736         else
2737                 return TSU_VTAG1;
2738 }
2739
2740 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2741                                   __be16 proto, u16 vid)
2742 {
2743         struct sh_eth_private *mdp = netdev_priv(ndev);
2744         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2745
2746         if (unlikely(!mdp->cd->tsu))
2747                 return -EPERM;
2748
2749         /* No filtering if vid = 0 */
2750         if (!vid)
2751                 return 0;
2752
2753         mdp->vlan_num_ids++;
2754
2755         /* The controller has one VLAN tag HW filter. So, if the filter is
2756          * already enabled, the driver disables it and the filte
2757          */
2758         if (mdp->vlan_num_ids > 1) {
2759                 /* disable VLAN filter */
2760                 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2761                 return 0;
2762         }
2763
2764         sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2765                          vtag_reg_index);
2766
2767         return 0;
2768 }
2769
2770 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2771                                    __be16 proto, u16 vid)
2772 {
2773         struct sh_eth_private *mdp = netdev_priv(ndev);
2774         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2775
2776         if (unlikely(!mdp->cd->tsu))
2777                 return -EPERM;
2778
2779         /* No filtering if vid = 0 */
2780         if (!vid)
2781                 return 0;
2782
2783         mdp->vlan_num_ids--;
2784         sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2785
2786         return 0;
2787 }
2788
2789 /* SuperH's TSU register init function */
2790 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2791 {
2792         if (sh_eth_is_rz_fast_ether(mdp)) {
2793                 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2794                 return;
2795         }
2796
2797         sh_eth_tsu_write(mdp, 0, TSU_FWEN0);    /* Disable forward(0->1) */
2798         sh_eth_tsu_write(mdp, 0, TSU_FWEN1);    /* Disable forward(1->0) */
2799         sh_eth_tsu_write(mdp, 0, TSU_FCM);      /* forward fifo 3k-3k */
2800         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2801         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2802         sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2803         sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2804         sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2805         sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2806         sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2807         if (sh_eth_is_gether(mdp)) {
2808                 sh_eth_tsu_write(mdp, 0, TSU_QTAG0);    /* Disable QTAG(0->1) */
2809                 sh_eth_tsu_write(mdp, 0, TSU_QTAG1);    /* Disable QTAG(1->0) */
2810         } else {
2811                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0);   /* Disable QTAG(0->1) */
2812                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1);   /* Disable QTAG(1->0) */
2813         }
2814         sh_eth_tsu_write(mdp, 0, TSU_FWSR);     /* all interrupt status clear */
2815         sh_eth_tsu_write(mdp, 0, TSU_FWINMK);   /* Disable all interrupt */
2816         sh_eth_tsu_write(mdp, 0, TSU_TEN);      /* Disable all CAM entry */
2817         sh_eth_tsu_write(mdp, 0, TSU_POST1);    /* Disable CAM entry [ 0- 7] */
2818         sh_eth_tsu_write(mdp, 0, TSU_POST2);    /* Disable CAM entry [ 8-15] */
2819         sh_eth_tsu_write(mdp, 0, TSU_POST3);    /* Disable CAM entry [16-23] */
2820         sh_eth_tsu_write(mdp, 0, TSU_POST4);    /* Disable CAM entry [24-31] */
2821 }
2822
2823 /* MDIO bus release function */
2824 static int sh_mdio_release(struct sh_eth_private *mdp)
2825 {
2826         /* unregister mdio bus */
2827         mdiobus_unregister(mdp->mii_bus);
2828
2829         /* free bitbang info */
2830         free_mdio_bitbang(mdp->mii_bus);
2831
2832         return 0;
2833 }
2834
2835 /* MDIO bus init function */
2836 static int sh_mdio_init(struct sh_eth_private *mdp,
2837                         struct sh_eth_plat_data *pd)
2838 {
2839         int ret;
2840         struct bb_info *bitbang;
2841         struct platform_device *pdev = mdp->pdev;
2842         struct device *dev = &mdp->pdev->dev;
2843
2844         /* create bit control struct for PHY */
2845         bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
2846         if (!bitbang)
2847                 return -ENOMEM;
2848
2849         /* bitbang init */
2850         bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2851         bitbang->set_gate = pd->set_mdio_gate;
2852         bitbang->ctrl.ops = &bb_ops;
2853
2854         /* MII controller setting */
2855         mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2856         if (!mdp->mii_bus)
2857                 return -ENOMEM;
2858
2859         /* Hook up MII support for ethtool */
2860         mdp->mii_bus->name = "sh_mii";
2861         mdp->mii_bus->parent = dev;
2862         snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2863                  pdev->name, pdev->id);
2864
2865         /* register MDIO bus */
2866         if (dev->of_node) {
2867                 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
2868         } else {
2869                 if (pd->phy_irq > 0)
2870                         mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2871
2872                 ret = mdiobus_register(mdp->mii_bus);
2873         }
2874
2875         if (ret)
2876                 goto out_free_bus;
2877
2878         return 0;
2879
2880 out_free_bus:
2881         free_mdio_bitbang(mdp->mii_bus);
2882         return ret;
2883 }
2884
2885 static const u16 *sh_eth_get_register_offset(int register_type)
2886 {
2887         const u16 *reg_offset = NULL;
2888
2889         switch (register_type) {
2890         case SH_ETH_REG_GIGABIT:
2891                 reg_offset = sh_eth_offset_gigabit;
2892                 break;
2893         case SH_ETH_REG_FAST_RZ:
2894                 reg_offset = sh_eth_offset_fast_rz;
2895                 break;
2896         case SH_ETH_REG_FAST_RCAR:
2897                 reg_offset = sh_eth_offset_fast_rcar;
2898                 break;
2899         case SH_ETH_REG_FAST_SH4:
2900                 reg_offset = sh_eth_offset_fast_sh4;
2901                 break;
2902         case SH_ETH_REG_FAST_SH3_SH2:
2903                 reg_offset = sh_eth_offset_fast_sh3_sh2;
2904                 break;
2905         }
2906
2907         return reg_offset;
2908 }
2909
2910 static const struct net_device_ops sh_eth_netdev_ops = {
2911         .ndo_open               = sh_eth_open,
2912         .ndo_stop               = sh_eth_close,
2913         .ndo_start_xmit         = sh_eth_start_xmit,
2914         .ndo_get_stats          = sh_eth_get_stats,
2915         .ndo_set_rx_mode        = sh_eth_set_rx_mode,
2916         .ndo_tx_timeout         = sh_eth_tx_timeout,
2917         .ndo_do_ioctl           = sh_eth_do_ioctl,
2918         .ndo_validate_addr      = eth_validate_addr,
2919         .ndo_set_mac_address    = eth_mac_addr,
2920         .ndo_change_mtu         = eth_change_mtu,
2921 };
2922
2923 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2924         .ndo_open               = sh_eth_open,
2925         .ndo_stop               = sh_eth_close,
2926         .ndo_start_xmit         = sh_eth_start_xmit,
2927         .ndo_get_stats          = sh_eth_get_stats,
2928         .ndo_set_rx_mode        = sh_eth_set_rx_mode,
2929         .ndo_vlan_rx_add_vid    = sh_eth_vlan_rx_add_vid,
2930         .ndo_vlan_rx_kill_vid   = sh_eth_vlan_rx_kill_vid,
2931         .ndo_tx_timeout         = sh_eth_tx_timeout,
2932         .ndo_do_ioctl           = sh_eth_do_ioctl,
2933         .ndo_validate_addr      = eth_validate_addr,
2934         .ndo_set_mac_address    = eth_mac_addr,
2935         .ndo_change_mtu         = eth_change_mtu,
2936 };
2937
2938 #ifdef CONFIG_OF
2939 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2940 {
2941         struct device_node *np = dev->of_node;
2942         struct sh_eth_plat_data *pdata;
2943         const char *mac_addr;
2944
2945         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2946         if (!pdata)
2947                 return NULL;
2948
2949         pdata->phy_interface = of_get_phy_mode(np);
2950
2951         mac_addr = of_get_mac_address(np);
2952         if (mac_addr)
2953                 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
2954
2955         pdata->no_ether_link =
2956                 of_property_read_bool(np, "renesas,no-ether-link");
2957         pdata->ether_link_active_low =
2958                 of_property_read_bool(np, "renesas,ether-link-active-low");
2959
2960         return pdata;
2961 }
2962
2963 static const struct of_device_id sh_eth_match_table[] = {
2964         { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
2965         { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
2966         { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
2967         { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
2968         { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
2969         { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
2970         { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
2971         { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
2972         { }
2973 };
2974 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
2975 #else
2976 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2977 {
2978         return NULL;
2979 }
2980 #endif
2981
2982 static int sh_eth_drv_probe(struct platform_device *pdev)
2983 {
2984         struct resource *res;
2985         struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
2986         const struct platform_device_id *id = platform_get_device_id(pdev);
2987         struct sh_eth_private *mdp;
2988         struct net_device *ndev;
2989         int ret, devno;
2990
2991         /* get base addr */
2992         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2993
2994         ndev = alloc_etherdev(sizeof(struct sh_eth_private));
2995         if (!ndev)
2996                 return -ENOMEM;
2997
2998         pm_runtime_enable(&pdev->dev);
2999         pm_runtime_get_sync(&pdev->dev);
3000
3001         devno = pdev->id;
3002         if (devno < 0)
3003                 devno = 0;
3004
3005         ndev->dma = -1;
3006         ret = platform_get_irq(pdev, 0);
3007         if (ret < 0)
3008                 goto out_release;
3009         ndev->irq = ret;
3010
3011         SET_NETDEV_DEV(ndev, &pdev->dev);
3012
3013         mdp = netdev_priv(ndev);
3014         mdp->num_tx_ring = TX_RING_SIZE;
3015         mdp->num_rx_ring = RX_RING_SIZE;
3016         mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3017         if (IS_ERR(mdp->addr)) {
3018                 ret = PTR_ERR(mdp->addr);
3019                 goto out_release;
3020         }
3021
3022         ndev->base_addr = res->start;
3023
3024         spin_lock_init(&mdp->lock);
3025         mdp->pdev = pdev;
3026
3027         if (pdev->dev.of_node)
3028                 pd = sh_eth_parse_dt(&pdev->dev);
3029         if (!pd) {
3030                 dev_err(&pdev->dev, "no platform data\n");
3031                 ret = -EINVAL;
3032                 goto out_release;
3033         }
3034
3035         /* get PHY ID */
3036         mdp->phy_id = pd->phy;
3037         mdp->phy_interface = pd->phy_interface;
3038         mdp->no_ether_link = pd->no_ether_link;
3039         mdp->ether_link_active_low = pd->ether_link_active_low;
3040
3041         /* set cpu data */
3042         if (id)
3043                 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3044         else
3045                 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev);
3046
3047         mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
3048         if (!mdp->reg_offset) {
3049                 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3050                         mdp->cd->register_type);
3051                 ret = -EINVAL;
3052                 goto out_release;
3053         }
3054         sh_eth_set_default_cpu_data(mdp->cd);
3055
3056         /* set function */
3057         if (mdp->cd->tsu)
3058                 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3059         else
3060                 ndev->netdev_ops = &sh_eth_netdev_ops;
3061         ndev->ethtool_ops = &sh_eth_ethtool_ops;
3062         ndev->watchdog_timeo = TX_TIMEOUT;
3063
3064         /* debug message level */
3065         mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
3066
3067         /* read and set MAC address */
3068         read_mac_address(ndev, pd->mac_addr);
3069         if (!is_valid_ether_addr(ndev->dev_addr)) {
3070                 dev_warn(&pdev->dev,
3071                          "no valid MAC address supplied, using a random one.\n");
3072                 eth_hw_addr_random(ndev);
3073         }
3074
3075         /* ioremap the TSU registers */
3076         if (mdp->cd->tsu) {
3077                 struct resource *rtsu;
3078                 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3079                 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
3080                 if (IS_ERR(mdp->tsu_addr)) {
3081                         ret = PTR_ERR(mdp->tsu_addr);
3082                         goto out_release;
3083                 }
3084                 mdp->port = devno % 2;
3085                 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
3086         }
3087
3088         /* initialize first or needed device */
3089         if (!devno || pd->needs_init) {
3090                 if (mdp->cd->chip_reset)
3091                         mdp->cd->chip_reset(ndev);
3092
3093                 if (mdp->cd->tsu) {
3094                         /* TSU init (Init only)*/
3095                         sh_eth_tsu_init(mdp);
3096                 }
3097         }
3098
3099         if (mdp->cd->rmiimode)
3100                 sh_eth_write(ndev, 0x1, RMIIMODE);
3101
3102         /* MDIO bus init */
3103         ret = sh_mdio_init(mdp, pd);
3104         if (ret) {
3105                 dev_err(&ndev->dev, "failed to initialise MDIO\n");
3106                 goto out_release;
3107         }
3108
3109         netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3110
3111         /* network device register */
3112         ret = register_netdev(ndev);
3113         if (ret)
3114                 goto out_napi_del;
3115
3116         /* print device information */
3117         netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3118                     (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
3119
3120         pm_runtime_put(&pdev->dev);
3121         platform_set_drvdata(pdev, ndev);
3122
3123         return ret;
3124
3125 out_napi_del:
3126         netif_napi_del(&mdp->napi);
3127         sh_mdio_release(mdp);
3128
3129 out_release:
3130         /* net_dev free */
3131         if (ndev)
3132                 free_netdev(ndev);
3133
3134         pm_runtime_put(&pdev->dev);
3135         pm_runtime_disable(&pdev->dev);
3136         return ret;
3137 }
3138
3139 static int sh_eth_drv_remove(struct platform_device *pdev)
3140 {
3141         struct net_device *ndev = platform_get_drvdata(pdev);
3142         struct sh_eth_private *mdp = netdev_priv(ndev);
3143
3144         unregister_netdev(ndev);
3145         netif_napi_del(&mdp->napi);
3146         sh_mdio_release(mdp);
3147         pm_runtime_disable(&pdev->dev);
3148         free_netdev(ndev);
3149
3150         return 0;
3151 }
3152
3153 #ifdef CONFIG_PM
3154 #ifdef CONFIG_PM_SLEEP
3155 static int sh_eth_suspend(struct device *dev)
3156 {
3157         struct net_device *ndev = dev_get_drvdata(dev);
3158         int ret = 0;
3159
3160         if (netif_running(ndev)) {
3161                 netif_device_detach(ndev);
3162                 ret = sh_eth_close(ndev);
3163         }
3164
3165         return ret;
3166 }
3167
3168 static int sh_eth_resume(struct device *dev)
3169 {
3170         struct net_device *ndev = dev_get_drvdata(dev);
3171         int ret = 0;
3172
3173         if (netif_running(ndev)) {
3174                 ret = sh_eth_open(ndev);
3175                 if (ret < 0)
3176                         return ret;
3177                 netif_device_attach(ndev);
3178         }
3179
3180         return ret;
3181 }
3182 #endif
3183
3184 static int sh_eth_runtime_nop(struct device *dev)
3185 {
3186         /* Runtime PM callback shared between ->runtime_suspend()
3187          * and ->runtime_resume(). Simply returns success.
3188          *
3189          * This driver re-initializes all registers after
3190          * pm_runtime_get_sync() anyway so there is no need
3191          * to save and restore registers here.
3192          */
3193         return 0;
3194 }
3195
3196 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
3197         SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
3198         SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
3199 };
3200 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3201 #else
3202 #define SH_ETH_PM_OPS NULL
3203 #endif
3204
3205 static struct platform_device_id sh_eth_id_table[] = {
3206         { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3207         { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3208         { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3209         { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3210         { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3211         { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3212         { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3213         { }
3214 };
3215 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3216
3217 static struct platform_driver sh_eth_driver = {
3218         .probe = sh_eth_drv_probe,
3219         .remove = sh_eth_drv_remove,
3220         .id_table = sh_eth_id_table,
3221         .driver = {
3222                    .name = CARDNAME,
3223                    .pm = SH_ETH_PM_OPS,
3224                    .of_match_table = of_match_ptr(sh_eth_match_table),
3225         },
3226 };
3227
3228 module_platform_driver(sh_eth_driver);
3229
3230 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3231 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3232 MODULE_LICENSE("GPL v2");