1 /* SuperH Ethernet device driver
3 * Copyright (C) 2014 Renesas Electronics Corporation
4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2014 Renesas Solutions Corp.
6 * Copyright (C) 2013-2014 Cogent Embedded, Inc.
7 * Copyright (C) 2014 Codethink Limited
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/spinlock.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/etherdevice.h>
28 #include <linux/delay.h>
29 #include <linux/platform_device.h>
30 #include <linux/mdio-bitbang.h>
31 #include <linux/netdevice.h>
33 #include <linux/of_device.h>
34 #include <linux/of_irq.h>
35 #include <linux/of_net.h>
36 #include <linux/phy.h>
37 #include <linux/cache.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/slab.h>
41 #include <linux/ethtool.h>
42 #include <linux/if_vlan.h>
43 #include <linux/clk.h>
44 #include <linux/sh_eth.h>
45 #include <linux/of_mdio.h>
49 #define SH_ETH_DEF_MSG_ENABLE \
55 #define SH_ETH_OFFSET_DEFAULTS \
56 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
58 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
59 SH_ETH_OFFSET_DEFAULTS,
114 [TSU_CTRST] = 0x0004,
115 [TSU_FWEN0] = 0x0010,
116 [TSU_FWEN1] = 0x0014,
118 [TSU_BSYSL0] = 0x0020,
119 [TSU_BSYSL1] = 0x0024,
120 [TSU_PRISL0] = 0x0028,
121 [TSU_PRISL1] = 0x002c,
122 [TSU_FWSL0] = 0x0030,
123 [TSU_FWSL1] = 0x0034,
124 [TSU_FWSLC] = 0x0038,
125 [TSU_QTAG0] = 0x0040,
126 [TSU_QTAG1] = 0x0044,
128 [TSU_FWINMK] = 0x0054,
129 [TSU_ADQT0] = 0x0048,
130 [TSU_ADQT1] = 0x004c,
131 [TSU_VTAG0] = 0x0058,
132 [TSU_VTAG1] = 0x005c,
133 [TSU_ADSBSY] = 0x0060,
135 [TSU_POST1] = 0x0070,
136 [TSU_POST2] = 0x0074,
137 [TSU_POST3] = 0x0078,
138 [TSU_POST4] = 0x007c,
139 [TSU_ADRH0] = 0x0100,
155 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
156 SH_ETH_OFFSET_DEFAULTS,
201 [TSU_CTRST] = 0x0004,
202 [TSU_VTAG0] = 0x0058,
203 [TSU_ADSBSY] = 0x0060,
205 [TSU_ADRH0] = 0x0100,
213 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
214 SH_ETH_OFFSET_DEFAULTS,
261 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
262 SH_ETH_OFFSET_DEFAULTS,
315 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
316 SH_ETH_OFFSET_DEFAULTS,
364 [TSU_CTRST] = 0x0004,
365 [TSU_FWEN0] = 0x0010,
366 [TSU_FWEN1] = 0x0014,
368 [TSU_BSYSL0] = 0x0020,
369 [TSU_BSYSL1] = 0x0024,
370 [TSU_PRISL0] = 0x0028,
371 [TSU_PRISL1] = 0x002c,
372 [TSU_FWSL0] = 0x0030,
373 [TSU_FWSL1] = 0x0034,
374 [TSU_FWSLC] = 0x0038,
375 [TSU_QTAGM0] = 0x0040,
376 [TSU_QTAGM1] = 0x0044,
377 [TSU_ADQT0] = 0x0048,
378 [TSU_ADQT1] = 0x004c,
380 [TSU_FWINMK] = 0x0054,
381 [TSU_ADSBSY] = 0x0060,
383 [TSU_POST1] = 0x0070,
384 [TSU_POST2] = 0x0074,
385 [TSU_POST3] = 0x0078,
386 [TSU_POST4] = 0x007c,
401 [TSU_ADRH0] = 0x0100,
404 static void sh_eth_rcv_snd_disable(struct net_device *ndev);
405 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
407 static bool sh_eth_is_gether(struct sh_eth_private *mdp)
409 return mdp->reg_offset == sh_eth_offset_gigabit;
412 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
414 return mdp->reg_offset == sh_eth_offset_fast_rz;
417 static void sh_eth_select_mii(struct net_device *ndev)
420 struct sh_eth_private *mdp = netdev_priv(ndev);
422 switch (mdp->phy_interface) {
423 case PHY_INTERFACE_MODE_GMII:
426 case PHY_INTERFACE_MODE_MII:
429 case PHY_INTERFACE_MODE_RMII:
434 "PHY interface mode was not setup. Set to MII.\n");
439 sh_eth_write(ndev, value, RMII_MII);
442 static void sh_eth_set_duplex(struct net_device *ndev)
444 struct sh_eth_private *mdp = netdev_priv(ndev);
446 if (mdp->duplex) /* Full */
447 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
449 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
452 static void sh_eth_chip_reset(struct net_device *ndev)
454 struct sh_eth_private *mdp = netdev_priv(ndev);
457 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
461 static void sh_eth_set_rate_gether(struct net_device *ndev)
463 struct sh_eth_private *mdp = netdev_priv(ndev);
465 switch (mdp->speed) {
466 case 10: /* 10BASE */
467 sh_eth_write(ndev, GECMR_10, GECMR);
469 case 100:/* 100BASE */
470 sh_eth_write(ndev, GECMR_100, GECMR);
472 case 1000: /* 1000BASE */
473 sh_eth_write(ndev, GECMR_1000, GECMR);
482 static struct sh_eth_cpu_data r7s72100_data = {
483 .chip_reset = sh_eth_chip_reset,
484 .set_duplex = sh_eth_set_duplex,
486 .register_type = SH_ETH_REG_FAST_RZ,
488 .ecsr_value = ECSR_ICD,
489 .ecsipr_value = ECSIPR_ICDIP,
490 .eesipr_value = 0xff7f009f,
492 .tx_check = EESR_TC1 | EESR_FTC,
493 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
494 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
496 .fdr_value = 0x0000070f,
504 .rpadir_value = 2 << 16,
512 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
514 struct sh_eth_private *mdp = netdev_priv(ndev);
517 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
520 sh_eth_select_mii(ndev);
524 static struct sh_eth_cpu_data r8a7740_data = {
525 .chip_reset = sh_eth_chip_reset_r8a7740,
526 .set_duplex = sh_eth_set_duplex,
527 .set_rate = sh_eth_set_rate_gether,
529 .register_type = SH_ETH_REG_GIGABIT,
531 .ecsr_value = ECSR_ICD | ECSR_MPD,
532 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
533 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
535 .tx_check = EESR_TC1 | EESR_FTC,
536 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
537 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
539 .fdr_value = 0x0000070f,
547 .rpadir_value = 2 << 16,
555 /* There is CPU dependent code */
556 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
558 struct sh_eth_private *mdp = netdev_priv(ndev);
560 switch (mdp->speed) {
561 case 10: /* 10BASE */
562 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
564 case 100:/* 100BASE */
565 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
573 static struct sh_eth_cpu_data r8a777x_data = {
574 .set_duplex = sh_eth_set_duplex,
575 .set_rate = sh_eth_set_rate_r8a777x,
577 .register_type = SH_ETH_REG_FAST_RCAR,
579 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
580 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
581 .eesipr_value = 0x01ff009f,
583 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
584 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
585 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
587 .fdr_value = 0x00000f0f,
596 static struct sh_eth_cpu_data r8a779x_data = {
597 .set_duplex = sh_eth_set_duplex,
598 .set_rate = sh_eth_set_rate_r8a777x,
600 .register_type = SH_ETH_REG_FAST_RCAR,
602 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
603 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
604 .eesipr_value = 0x01ff009f,
606 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
607 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
608 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
610 .fdr_value = 0x00000f0f,
612 .trscer_err_mask = DESC_I_RINT8,
620 #endif /* CONFIG_OF */
622 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
624 struct sh_eth_private *mdp = netdev_priv(ndev);
626 switch (mdp->speed) {
627 case 10: /* 10BASE */
628 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
630 case 100:/* 100BASE */
631 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
639 static struct sh_eth_cpu_data sh7724_data = {
640 .set_duplex = sh_eth_set_duplex,
641 .set_rate = sh_eth_set_rate_sh7724,
643 .register_type = SH_ETH_REG_FAST_SH4,
645 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
646 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
647 .eesipr_value = 0x01ff009f,
649 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
650 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
651 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
659 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
662 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
664 struct sh_eth_private *mdp = netdev_priv(ndev);
666 switch (mdp->speed) {
667 case 10: /* 10BASE */
668 sh_eth_write(ndev, 0, RTRATE);
670 case 100:/* 100BASE */
671 sh_eth_write(ndev, 1, RTRATE);
679 static struct sh_eth_cpu_data sh7757_data = {
680 .set_duplex = sh_eth_set_duplex,
681 .set_rate = sh_eth_set_rate_sh7757,
683 .register_type = SH_ETH_REG_FAST_SH4,
685 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
687 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
688 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
689 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
692 .irq_flags = IRQF_SHARED,
699 .rpadir_value = 2 << 16,
703 #define SH_GIGA_ETH_BASE 0xfee00000UL
704 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
705 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
706 static void sh_eth_chip_reset_giga(struct net_device *ndev)
709 u32 mahr[2], malr[2];
711 /* save MAHR and MALR */
712 for (i = 0; i < 2; i++) {
713 malr[i] = ioread32((void *)GIGA_MALR(i));
714 mahr[i] = ioread32((void *)GIGA_MAHR(i));
718 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
721 /* restore MAHR and MALR */
722 for (i = 0; i < 2; i++) {
723 iowrite32(malr[i], (void *)GIGA_MALR(i));
724 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
728 static void sh_eth_set_rate_giga(struct net_device *ndev)
730 struct sh_eth_private *mdp = netdev_priv(ndev);
732 switch (mdp->speed) {
733 case 10: /* 10BASE */
734 sh_eth_write(ndev, 0x00000000, GECMR);
736 case 100:/* 100BASE */
737 sh_eth_write(ndev, 0x00000010, GECMR);
739 case 1000: /* 1000BASE */
740 sh_eth_write(ndev, 0x00000020, GECMR);
747 /* SH7757(GETHERC) */
748 static struct sh_eth_cpu_data sh7757_data_giga = {
749 .chip_reset = sh_eth_chip_reset_giga,
750 .set_duplex = sh_eth_set_duplex,
751 .set_rate = sh_eth_set_rate_giga,
753 .register_type = SH_ETH_REG_GIGABIT,
755 .ecsr_value = ECSR_ICD | ECSR_MPD,
756 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
757 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
759 .tx_check = EESR_TC1 | EESR_FTC,
760 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
761 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
763 .fdr_value = 0x0000072f,
765 .irq_flags = IRQF_SHARED,
772 .rpadir_value = 2 << 16,
779 static struct sh_eth_cpu_data sh7734_data = {
780 .chip_reset = sh_eth_chip_reset,
781 .set_duplex = sh_eth_set_duplex,
782 .set_rate = sh_eth_set_rate_gether,
784 .register_type = SH_ETH_REG_GIGABIT,
786 .ecsr_value = ECSR_ICD | ECSR_MPD,
787 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
788 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
790 .tx_check = EESR_TC1 | EESR_FTC,
791 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
792 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
808 static struct sh_eth_cpu_data sh7763_data = {
809 .chip_reset = sh_eth_chip_reset,
810 .set_duplex = sh_eth_set_duplex,
811 .set_rate = sh_eth_set_rate_gether,
813 .register_type = SH_ETH_REG_GIGABIT,
815 .ecsr_value = ECSR_ICD | ECSR_MPD,
816 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
817 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
819 .tx_check = EESR_TC1 | EESR_FTC,
820 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
821 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
832 .irq_flags = IRQF_SHARED,
835 static struct sh_eth_cpu_data sh7619_data = {
836 .register_type = SH_ETH_REG_FAST_SH3_SH2,
838 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
846 static struct sh_eth_cpu_data sh771x_data = {
847 .register_type = SH_ETH_REG_FAST_SH3_SH2,
849 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
853 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
856 cd->ecsr_value = DEFAULT_ECSR_INIT;
858 if (!cd->ecsipr_value)
859 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
861 if (!cd->fcftr_value)
862 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
863 DEFAULT_FIFO_F_D_RFD;
866 cd->fdr_value = DEFAULT_FDR_INIT;
869 cd->tx_check = DEFAULT_TX_CHECK;
871 if (!cd->eesr_err_check)
872 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
874 if (!cd->trscer_err_mask)
875 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
878 static int sh_eth_check_reset(struct net_device *ndev)
884 if (!(sh_eth_read(ndev, EDMR) & 0x3))
890 netdev_err(ndev, "Device reset failed\n");
896 static int sh_eth_reset(struct net_device *ndev)
898 struct sh_eth_private *mdp = netdev_priv(ndev);
901 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
902 sh_eth_write(ndev, EDSR_ENALL, EDSR);
903 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
906 ret = sh_eth_check_reset(ndev);
911 sh_eth_write(ndev, 0x0, TDLAR);
912 sh_eth_write(ndev, 0x0, TDFAR);
913 sh_eth_write(ndev, 0x0, TDFXR);
914 sh_eth_write(ndev, 0x0, TDFFR);
915 sh_eth_write(ndev, 0x0, RDLAR);
916 sh_eth_write(ndev, 0x0, RDFAR);
917 sh_eth_write(ndev, 0x0, RDFXR);
918 sh_eth_write(ndev, 0x0, RDFFR);
920 /* Reset HW CRC register */
922 sh_eth_write(ndev, 0x0, CSMR);
924 /* Select MII mode */
925 if (mdp->cd->select_mii)
926 sh_eth_select_mii(ndev);
928 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
931 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
938 static void sh_eth_set_receive_align(struct sk_buff *skb)
940 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
943 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
947 /* CPU <-> EDMAC endian convert */
948 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
950 switch (mdp->edmac_endian) {
951 case EDMAC_LITTLE_ENDIAN:
952 return cpu_to_le32(x);
953 case EDMAC_BIG_ENDIAN:
954 return cpu_to_be32(x);
959 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
961 switch (mdp->edmac_endian) {
962 case EDMAC_LITTLE_ENDIAN:
963 return le32_to_cpu(x);
964 case EDMAC_BIG_ENDIAN:
965 return be32_to_cpu(x);
970 /* Program the hardware MAC address from dev->dev_addr. */
971 static void update_mac_address(struct net_device *ndev)
974 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
975 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
977 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
980 /* Get MAC address from SuperH MAC address register
982 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
983 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
984 * When you want use this device, you must set MAC address in bootloader.
987 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
989 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
990 memcpy(ndev->dev_addr, mac, ETH_ALEN);
992 u32 mahr = sh_eth_read(ndev, MAHR);
993 u32 malr = sh_eth_read(ndev, MALR);
995 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
996 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
997 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
998 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
999 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
1000 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
1004 static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
1006 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
1007 return EDTRR_TRNS_GETHER;
1009 return EDTRR_TRNS_ETHER;
1013 void (*set_gate)(void *addr);
1014 struct mdiobb_ctrl ctrl;
1019 static void bb_set(void *addr, u32 msk)
1021 iowrite32(ioread32(addr) | msk, addr);
1025 static void bb_clr(void *addr, u32 msk)
1027 iowrite32((ioread32(addr) & ~msk), addr);
1031 static int bb_read(void *addr, u32 msk)
1033 return (ioread32(addr) & msk) != 0;
1036 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
1038 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1040 if (bitbang->set_gate)
1041 bitbang->set_gate(bitbang->addr);
1044 bb_set(bitbang->addr, mask);
1046 bb_clr(bitbang->addr, mask);
1049 /* Data I/O pin control */
1050 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1052 sh_mdio_ctrl(ctrl, PIR_MMD, bit);
1056 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1058 sh_mdio_ctrl(ctrl, PIR_MDO, bit);
1062 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1064 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1066 if (bitbang->set_gate)
1067 bitbang->set_gate(bitbang->addr);
1069 return bb_read(bitbang->addr, PIR_MDI);
1072 /* MDC pin control */
1073 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1075 sh_mdio_ctrl(ctrl, PIR_MDC, bit);
1078 /* mdio bus control struct */
1079 static struct mdiobb_ops bb_ops = {
1080 .owner = THIS_MODULE,
1081 .set_mdc = sh_mdc_ctrl,
1082 .set_mdio_dir = sh_mmd_ctrl,
1083 .set_mdio_data = sh_set_mdio,
1084 .get_mdio_data = sh_get_mdio,
1087 /* free skb and descriptor buffer */
1088 static void sh_eth_ring_free(struct net_device *ndev)
1090 struct sh_eth_private *mdp = netdev_priv(ndev);
1093 /* Free Rx skb ringbuffer */
1094 if (mdp->rx_skbuff) {
1095 for (i = 0; i < mdp->num_rx_ring; i++)
1096 dev_kfree_skb(mdp->rx_skbuff[i]);
1098 kfree(mdp->rx_skbuff);
1099 mdp->rx_skbuff = NULL;
1101 /* Free Tx skb ringbuffer */
1102 if (mdp->tx_skbuff) {
1103 for (i = 0; i < mdp->num_tx_ring; i++)
1104 dev_kfree_skb(mdp->tx_skbuff[i]);
1106 kfree(mdp->tx_skbuff);
1107 mdp->tx_skbuff = NULL;
1110 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1111 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1113 mdp->rx_ring = NULL;
1117 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1118 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1120 mdp->tx_ring = NULL;
1124 /* format skb and descriptor buffer */
1125 static void sh_eth_ring_format(struct net_device *ndev)
1127 struct sh_eth_private *mdp = netdev_priv(ndev);
1129 struct sk_buff *skb;
1130 struct sh_eth_rxdesc *rxdesc = NULL;
1131 struct sh_eth_txdesc *txdesc = NULL;
1132 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1133 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1134 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1135 dma_addr_t dma_addr;
1142 memset(mdp->rx_ring, 0, rx_ringsize);
1144 /* build Rx ring buffer */
1145 for (i = 0; i < mdp->num_rx_ring; i++) {
1147 mdp->rx_skbuff[i] = NULL;
1148 skb = netdev_alloc_skb(ndev, skbuff_size);
1151 sh_eth_set_receive_align(skb);
1154 rxdesc = &mdp->rx_ring[i];
1155 /* The size of the buffer is a multiple of 32 bytes. */
1156 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 32);
1157 dma_addr = dma_map_single(&ndev->dev, skb->data,
1158 rxdesc->buffer_length,
1160 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1164 mdp->rx_skbuff[i] = skb;
1165 rxdesc->addr = dma_addr;
1166 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1168 /* Rx descriptor address set */
1170 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1171 if (sh_eth_is_gether(mdp) ||
1172 sh_eth_is_rz_fast_ether(mdp))
1173 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1177 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1179 /* Mark the last entry as wrapping the ring. */
1180 rxdesc->status |= cpu_to_edmac(mdp, RD_RDLE);
1182 memset(mdp->tx_ring, 0, tx_ringsize);
1184 /* build Tx ring buffer */
1185 for (i = 0; i < mdp->num_tx_ring; i++) {
1186 mdp->tx_skbuff[i] = NULL;
1187 txdesc = &mdp->tx_ring[i];
1188 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1189 txdesc->buffer_length = 0;
1191 /* Tx descriptor address set */
1192 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1193 if (sh_eth_is_gether(mdp) ||
1194 sh_eth_is_rz_fast_ether(mdp))
1195 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1199 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1202 /* Get skb and descriptor buffer */
1203 static int sh_eth_ring_init(struct net_device *ndev)
1205 struct sh_eth_private *mdp = netdev_priv(ndev);
1206 int rx_ringsize, tx_ringsize;
1208 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1209 * card needs room to do 8 byte alignment, +2 so we can reserve
1210 * the first 2 bytes, and +16 gets room for the status word from the
1213 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1214 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1215 if (mdp->cd->rpadir)
1216 mdp->rx_buf_sz += NET_IP_ALIGN;
1218 /* Allocate RX and TX skb rings */
1219 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1221 if (!mdp->rx_skbuff)
1224 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1226 if (!mdp->tx_skbuff)
1229 /* Allocate all Rx descriptors. */
1230 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1231 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1238 /* Allocate all Tx descriptors. */
1239 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1240 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1247 /* Free Rx and Tx skb ring buffer and DMA buffer */
1248 sh_eth_ring_free(ndev);
1253 static int sh_eth_dev_init(struct net_device *ndev, bool start)
1256 struct sh_eth_private *mdp = netdev_priv(ndev);
1260 ret = sh_eth_reset(ndev);
1264 if (mdp->cd->rmiimode)
1265 sh_eth_write(ndev, 0x1, RMIIMODE);
1267 /* Descriptor format */
1268 sh_eth_ring_format(ndev);
1269 if (mdp->cd->rpadir)
1270 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1272 /* all sh_eth int mask */
1273 sh_eth_write(ndev, 0, EESIPR);
1275 #if defined(__LITTLE_ENDIAN)
1276 if (mdp->cd->hw_swap)
1277 sh_eth_write(ndev, EDMR_EL, EDMR);
1280 sh_eth_write(ndev, 0, EDMR);
1283 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1284 sh_eth_write(ndev, 0, TFTR);
1286 /* Frame recv control (enable multiple-packets per rx irq) */
1287 sh_eth_write(ndev, RMCR_RNC, RMCR);
1289 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1292 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
1294 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1296 if (!mdp->cd->no_trimd)
1297 sh_eth_write(ndev, 0, TRIMD);
1299 /* Recv frame limit set register */
1300 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1303 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
1305 mdp->irq_enabled = true;
1306 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1309 /* PAUSE Prohibition */
1310 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
1311 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1313 sh_eth_write(ndev, val, ECMR);
1315 if (mdp->cd->set_rate)
1316 mdp->cd->set_rate(ndev);
1318 /* E-MAC Status Register clear */
1319 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1321 /* E-MAC Interrupt Enable register */
1323 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1325 /* Set MAC address */
1326 update_mac_address(ndev);
1330 sh_eth_write(ndev, APR_AP, APR);
1332 sh_eth_write(ndev, MPR_MP, MPR);
1333 if (mdp->cd->tpauser)
1334 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1337 /* Setting the Rx mode will start the Rx process. */
1338 sh_eth_write(ndev, EDRRR_R, EDRRR);
1340 netif_start_queue(ndev);
1346 static void sh_eth_dev_exit(struct net_device *ndev)
1348 struct sh_eth_private *mdp = netdev_priv(ndev);
1351 /* Deactivate all TX descriptors, so DMA should stop at next
1352 * packet boundary if it's currently running
1354 for (i = 0; i < mdp->num_tx_ring; i++)
1355 mdp->tx_ring[i].status &= ~cpu_to_edmac(mdp, TD_TACT);
1357 /* Disable TX FIFO egress to MAC */
1358 sh_eth_rcv_snd_disable(ndev);
1360 /* Stop RX DMA at next packet boundary */
1361 sh_eth_write(ndev, 0, EDRRR);
1363 /* Aside from TX DMA, we can't tell when the hardware is
1364 * really stopped, so we need to reset to make sure.
1365 * Before doing that, wait for long enough to *probably*
1366 * finish transmitting the last packet and poll stats.
1368 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1369 sh_eth_get_stats(ndev);
1372 /* Set MAC address again */
1373 update_mac_address(ndev);
1376 /* free Tx skb function */
1377 static int sh_eth_txfree(struct net_device *ndev)
1379 struct sh_eth_private *mdp = netdev_priv(ndev);
1380 struct sh_eth_txdesc *txdesc;
1384 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1385 entry = mdp->dirty_tx % mdp->num_tx_ring;
1386 txdesc = &mdp->tx_ring[entry];
1387 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
1389 /* TACT bit must be checked before all the following reads */
1391 netif_info(mdp, tx_done, ndev,
1392 "tx entry %d status 0x%08x\n",
1393 entry, edmac_to_cpu(mdp, txdesc->status));
1394 /* Free the original skb. */
1395 if (mdp->tx_skbuff[entry]) {
1396 dma_unmap_single(&ndev->dev, txdesc->addr,
1397 txdesc->buffer_length, DMA_TO_DEVICE);
1398 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1399 mdp->tx_skbuff[entry] = NULL;
1402 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1403 if (entry >= mdp->num_tx_ring - 1)
1404 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1406 ndev->stats.tx_packets++;
1407 ndev->stats.tx_bytes += txdesc->buffer_length;
1412 /* Packet receive function */
1413 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1415 struct sh_eth_private *mdp = netdev_priv(ndev);
1416 struct sh_eth_rxdesc *rxdesc;
1418 int entry = mdp->cur_rx % mdp->num_rx_ring;
1419 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1421 struct sk_buff *skb;
1424 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1425 dma_addr_t dma_addr;
1427 boguscnt = min(boguscnt, *quota);
1429 rxdesc = &mdp->rx_ring[entry];
1430 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1431 /* RACT bit must be checked before all the following reads */
1433 desc_status = edmac_to_cpu(mdp, rxdesc->status);
1434 pkt_len = rxdesc->frame_length;
1439 netif_info(mdp, rx_status, ndev,
1440 "rx entry %d status 0x%08x len %d\n",
1441 entry, desc_status, pkt_len);
1443 if (!(desc_status & RDFEND))
1444 ndev->stats.rx_length_errors++;
1446 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1447 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1448 * bit 0. However, in case of the R8A7740 and R7S72100
1449 * the RFS bits are from bit 25 to bit 16. So, the
1450 * driver needs right shifting by 16.
1452 if (mdp->cd->shift_rd0)
1455 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1456 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1457 ndev->stats.rx_errors++;
1458 if (desc_status & RD_RFS1)
1459 ndev->stats.rx_crc_errors++;
1460 if (desc_status & RD_RFS2)
1461 ndev->stats.rx_frame_errors++;
1462 if (desc_status & RD_RFS3)
1463 ndev->stats.rx_length_errors++;
1464 if (desc_status & RD_RFS4)
1465 ndev->stats.rx_length_errors++;
1466 if (desc_status & RD_RFS6)
1467 ndev->stats.rx_missed_errors++;
1468 if (desc_status & RD_RFS10)
1469 ndev->stats.rx_over_errors++;
1471 if (!mdp->cd->hw_swap)
1473 phys_to_virt(ALIGN(rxdesc->addr, 4)),
1475 skb = mdp->rx_skbuff[entry];
1476 mdp->rx_skbuff[entry] = NULL;
1477 if (mdp->cd->rpadir)
1478 skb_reserve(skb, NET_IP_ALIGN);
1479 dma_unmap_single(&ndev->dev, rxdesc->addr,
1480 ALIGN(mdp->rx_buf_sz, 32),
1482 skb_put(skb, pkt_len);
1483 skb->protocol = eth_type_trans(skb, ndev);
1484 netif_receive_skb(skb);
1485 ndev->stats.rx_packets++;
1486 ndev->stats.rx_bytes += pkt_len;
1487 if (desc_status & RD_RFS8)
1488 ndev->stats.multicast++;
1490 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1491 rxdesc = &mdp->rx_ring[entry];
1494 /* Refill the Rx ring buffers. */
1495 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1496 entry = mdp->dirty_rx % mdp->num_rx_ring;
1497 rxdesc = &mdp->rx_ring[entry];
1498 /* The size of the buffer is 32 byte boundary. */
1499 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 32);
1501 if (mdp->rx_skbuff[entry] == NULL) {
1502 skb = netdev_alloc_skb(ndev, skbuff_size);
1504 break; /* Better luck next round. */
1505 sh_eth_set_receive_align(skb);
1506 dma_addr = dma_map_single(&ndev->dev, skb->data,
1507 rxdesc->buffer_length,
1509 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1513 mdp->rx_skbuff[entry] = skb;
1515 skb_checksum_none_assert(skb);
1516 rxdesc->addr = dma_addr;
1518 dma_wmb(); /* RACT bit must be set after all the above writes */
1519 if (entry >= mdp->num_rx_ring - 1)
1521 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDLE);
1524 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1527 /* Restart Rx engine if stopped. */
1528 /* If we don't need to check status, don't. -KDU */
1529 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1530 /* fix the values for the next receiving if RDE is set */
1531 if (intr_status & EESR_RDE &&
1532 mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) {
1533 u32 count = (sh_eth_read(ndev, RDFAR) -
1534 sh_eth_read(ndev, RDLAR)) >> 4;
1536 mdp->cur_rx = count;
1537 mdp->dirty_rx = count;
1539 sh_eth_write(ndev, EDRRR_R, EDRRR);
1542 *quota -= limit - boguscnt - 1;
1547 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1549 /* disable tx and rx */
1550 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1551 ~(ECMR_RE | ECMR_TE), ECMR);
1554 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1556 /* enable tx and rx */
1557 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1558 (ECMR_RE | ECMR_TE), ECMR);
1561 /* error control function */
1562 static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1564 struct sh_eth_private *mdp = netdev_priv(ndev);
1569 if (intr_status & EESR_ECI) {
1570 felic_stat = sh_eth_read(ndev, ECSR);
1571 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1572 if (felic_stat & ECSR_ICD)
1573 ndev->stats.tx_carrier_errors++;
1574 if (felic_stat & ECSR_LCHNG) {
1576 if (mdp->cd->no_psr || mdp->no_ether_link) {
1579 link_stat = (sh_eth_read(ndev, PSR));
1580 if (mdp->ether_link_active_low)
1581 link_stat = ~link_stat;
1583 if (!(link_stat & PHY_ST_LINK)) {
1584 sh_eth_rcv_snd_disable(ndev);
1587 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1588 ~DMAC_M_ECI, EESIPR);
1590 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1592 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1593 DMAC_M_ECI, EESIPR);
1594 /* enable tx and rx */
1595 sh_eth_rcv_snd_enable(ndev);
1601 if (intr_status & EESR_TWB) {
1602 /* Unused write back interrupt */
1603 if (intr_status & EESR_TABT) { /* Transmit Abort int */
1604 ndev->stats.tx_aborted_errors++;
1605 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1609 if (intr_status & EESR_RABT) {
1610 /* Receive Abort int */
1611 if (intr_status & EESR_RFRMER) {
1612 /* Receive Frame Overflow int */
1613 ndev->stats.rx_frame_errors++;
1617 if (intr_status & EESR_TDE) {
1618 /* Transmit Descriptor Empty int */
1619 ndev->stats.tx_fifo_errors++;
1620 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1623 if (intr_status & EESR_TFE) {
1624 /* FIFO under flow */
1625 ndev->stats.tx_fifo_errors++;
1626 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1629 if (intr_status & EESR_RDE) {
1630 /* Receive Descriptor Empty int */
1631 ndev->stats.rx_over_errors++;
1634 if (intr_status & EESR_RFE) {
1635 /* Receive FIFO Overflow int */
1636 ndev->stats.rx_fifo_errors++;
1639 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1641 ndev->stats.tx_fifo_errors++;
1642 netif_err(mdp, tx_err, ndev, "Address Error\n");
1645 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1646 if (mdp->cd->no_ade)
1648 if (intr_status & mask) {
1650 u32 edtrr = sh_eth_read(ndev, EDTRR);
1653 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1654 intr_status, mdp->cur_tx, mdp->dirty_tx,
1655 (u32)ndev->state, edtrr);
1656 /* dirty buffer free */
1657 sh_eth_txfree(ndev);
1660 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1662 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1665 netif_wake_queue(ndev);
1669 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1671 struct net_device *ndev = netdev;
1672 struct sh_eth_private *mdp = netdev_priv(ndev);
1673 struct sh_eth_cpu_data *cd = mdp->cd;
1674 irqreturn_t ret = IRQ_NONE;
1675 u32 intr_status, intr_enable;
1677 spin_lock(&mdp->lock);
1679 /* Get interrupt status */
1680 intr_status = sh_eth_read(ndev, EESR);
1681 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1682 * enabled since it's the one that comes thru regardless of the mask,
1683 * and we need to fully handle it in sh_eth_error() in order to quench
1684 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1686 intr_enable = sh_eth_read(ndev, EESIPR);
1687 intr_status &= intr_enable | DMAC_M_ECI;
1688 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
1693 if (!likely(mdp->irq_enabled)) {
1694 sh_eth_write(ndev, 0, EESIPR);
1698 if (intr_status & EESR_RX_CHECK) {
1699 if (napi_schedule_prep(&mdp->napi)) {
1700 /* Mask Rx interrupts */
1701 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1703 __napi_schedule(&mdp->napi);
1706 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1707 intr_status, intr_enable);
1712 if (intr_status & cd->tx_check) {
1713 /* Clear Tx interrupts */
1714 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1716 sh_eth_txfree(ndev);
1717 netif_wake_queue(ndev);
1720 if (intr_status & cd->eesr_err_check) {
1721 /* Clear error interrupts */
1722 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1724 sh_eth_error(ndev, intr_status);
1728 spin_unlock(&mdp->lock);
1733 static int sh_eth_poll(struct napi_struct *napi, int budget)
1735 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1737 struct net_device *ndev = napi->dev;
1742 intr_status = sh_eth_read(ndev, EESR);
1743 if (!(intr_status & EESR_RX_CHECK))
1745 /* Clear Rx interrupts */
1746 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1748 if (sh_eth_rx(ndev, intr_status, "a))
1752 napi_complete(napi);
1754 /* Reenable Rx interrupts */
1755 if (mdp->irq_enabled)
1756 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1758 return budget - quota;
1761 /* PHY state control function */
1762 static void sh_eth_adjust_link(struct net_device *ndev)
1764 struct sh_eth_private *mdp = netdev_priv(ndev);
1765 struct phy_device *phydev = mdp->phydev;
1769 if (phydev->duplex != mdp->duplex) {
1771 mdp->duplex = phydev->duplex;
1772 if (mdp->cd->set_duplex)
1773 mdp->cd->set_duplex(ndev);
1776 if (phydev->speed != mdp->speed) {
1778 mdp->speed = phydev->speed;
1779 if (mdp->cd->set_rate)
1780 mdp->cd->set_rate(ndev);
1784 sh_eth_read(ndev, ECMR) & ~ECMR_TXF,
1787 mdp->link = phydev->link;
1788 if (mdp->cd->no_psr || mdp->no_ether_link)
1789 sh_eth_rcv_snd_enable(ndev);
1791 } else if (mdp->link) {
1796 if (mdp->cd->no_psr || mdp->no_ether_link)
1797 sh_eth_rcv_snd_disable(ndev);
1800 if (new_state && netif_msg_link(mdp))
1801 phy_print_status(phydev);
1804 /* PHY init function */
1805 static int sh_eth_phy_init(struct net_device *ndev)
1807 struct device_node *np = ndev->dev.parent->of_node;
1808 struct sh_eth_private *mdp = netdev_priv(ndev);
1809 struct phy_device *phydev = NULL;
1815 /* Try connect to PHY */
1817 struct device_node *pn;
1819 pn = of_parse_phandle(np, "phy-handle", 0);
1820 phydev = of_phy_connect(ndev, pn,
1821 sh_eth_adjust_link, 0,
1822 mdp->phy_interface);
1825 phydev = ERR_PTR(-ENOENT);
1827 char phy_id[MII_BUS_ID_SIZE + 3];
1829 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1830 mdp->mii_bus->id, mdp->phy_id);
1832 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1833 mdp->phy_interface);
1836 if (IS_ERR(phydev)) {
1837 netdev_err(ndev, "failed to connect PHY\n");
1838 return PTR_ERR(phydev);
1841 netdev_info(ndev, "attached PHY %d (IRQ %d) to driver %s\n",
1842 phydev->addr, phydev->irq, phydev->drv->name);
1844 mdp->phydev = phydev;
1849 /* PHY control start function */
1850 static int sh_eth_phy_start(struct net_device *ndev)
1852 struct sh_eth_private *mdp = netdev_priv(ndev);
1855 ret = sh_eth_phy_init(ndev);
1859 phy_start(mdp->phydev);
1864 static int sh_eth_get_settings(struct net_device *ndev,
1865 struct ethtool_cmd *ecmd)
1867 struct sh_eth_private *mdp = netdev_priv(ndev);
1868 unsigned long flags;
1874 spin_lock_irqsave(&mdp->lock, flags);
1875 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1876 spin_unlock_irqrestore(&mdp->lock, flags);
1881 static int sh_eth_set_settings(struct net_device *ndev,
1882 struct ethtool_cmd *ecmd)
1884 struct sh_eth_private *mdp = netdev_priv(ndev);
1885 unsigned long flags;
1891 spin_lock_irqsave(&mdp->lock, flags);
1893 /* disable tx and rx */
1894 sh_eth_rcv_snd_disable(ndev);
1896 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1900 if (ecmd->duplex == DUPLEX_FULL)
1905 if (mdp->cd->set_duplex)
1906 mdp->cd->set_duplex(ndev);
1911 /* enable tx and rx */
1912 sh_eth_rcv_snd_enable(ndev);
1914 spin_unlock_irqrestore(&mdp->lock, flags);
1919 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
1920 * version must be bumped as well. Just adding registers up to that
1921 * limit is fine, as long as the existing register indices don't
1924 #define SH_ETH_REG_DUMP_VERSION 1
1925 #define SH_ETH_REG_DUMP_MAX_REGS 256
1927 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
1929 struct sh_eth_private *mdp = netdev_priv(ndev);
1930 struct sh_eth_cpu_data *cd = mdp->cd;
1934 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
1936 /* Dump starts with a bitmap that tells ethtool which
1937 * registers are defined for this chip.
1939 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
1947 /* Add a register to the dump, if it has a defined offset.
1948 * This automatically skips most undefined registers, but for
1949 * some it is also necessary to check a capability flag in
1950 * struct sh_eth_cpu_data.
1952 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
1953 #define add_reg_from(reg, read_expr) do { \
1954 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \
1956 mark_reg_valid(reg); \
1957 *buf++ = read_expr; \
1962 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
1963 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
2035 add_tsu_reg(TSU_CTRST);
2036 add_tsu_reg(TSU_FWEN0);
2037 add_tsu_reg(TSU_FWEN1);
2038 add_tsu_reg(TSU_FCM);
2039 add_tsu_reg(TSU_BSYSL0);
2040 add_tsu_reg(TSU_BSYSL1);
2041 add_tsu_reg(TSU_PRISL0);
2042 add_tsu_reg(TSU_PRISL1);
2043 add_tsu_reg(TSU_FWSL0);
2044 add_tsu_reg(TSU_FWSL1);
2045 add_tsu_reg(TSU_FWSLC);
2046 add_tsu_reg(TSU_QTAG0);
2047 add_tsu_reg(TSU_QTAG1);
2048 add_tsu_reg(TSU_QTAGM0);
2049 add_tsu_reg(TSU_QTAGM1);
2050 add_tsu_reg(TSU_FWSR);
2051 add_tsu_reg(TSU_FWINMK);
2052 add_tsu_reg(TSU_ADQT0);
2053 add_tsu_reg(TSU_ADQT1);
2054 add_tsu_reg(TSU_VTAG0);
2055 add_tsu_reg(TSU_VTAG1);
2056 add_tsu_reg(TSU_ADSBSY);
2057 add_tsu_reg(TSU_TEN);
2058 add_tsu_reg(TSU_POST1);
2059 add_tsu_reg(TSU_POST2);
2060 add_tsu_reg(TSU_POST3);
2061 add_tsu_reg(TSU_POST4);
2062 if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) {
2063 /* This is the start of a table, not just a single
2069 mark_reg_valid(TSU_ADRH0);
2070 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2073 mdp->reg_offset[TSU_ADRH0] +
2076 len += SH_ETH_TSU_CAM_ENTRIES * 2;
2080 #undef mark_reg_valid
2088 static int sh_eth_get_regs_len(struct net_device *ndev)
2090 return __sh_eth_get_regs(ndev, NULL);
2093 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2096 struct sh_eth_private *mdp = netdev_priv(ndev);
2098 regs->version = SH_ETH_REG_DUMP_VERSION;
2100 pm_runtime_get_sync(&mdp->pdev->dev);
2101 __sh_eth_get_regs(ndev, buf);
2102 pm_runtime_put_sync(&mdp->pdev->dev);
2105 static int sh_eth_nway_reset(struct net_device *ndev)
2107 struct sh_eth_private *mdp = netdev_priv(ndev);
2108 unsigned long flags;
2114 spin_lock_irqsave(&mdp->lock, flags);
2115 ret = phy_start_aneg(mdp->phydev);
2116 spin_unlock_irqrestore(&mdp->lock, flags);
2121 static u32 sh_eth_get_msglevel(struct net_device *ndev)
2123 struct sh_eth_private *mdp = netdev_priv(ndev);
2124 return mdp->msg_enable;
2127 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2129 struct sh_eth_private *mdp = netdev_priv(ndev);
2130 mdp->msg_enable = value;
2133 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2134 "rx_current", "tx_current",
2135 "rx_dirty", "tx_dirty",
2137 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
2139 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2143 return SH_ETH_STATS_LEN;
2149 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
2150 struct ethtool_stats *stats, u64 *data)
2152 struct sh_eth_private *mdp = netdev_priv(ndev);
2155 /* device-specific stats */
2156 data[i++] = mdp->cur_rx;
2157 data[i++] = mdp->cur_tx;
2158 data[i++] = mdp->dirty_rx;
2159 data[i++] = mdp->dirty_tx;
2162 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2164 switch (stringset) {
2166 memcpy(data, *sh_eth_gstrings_stats,
2167 sizeof(sh_eth_gstrings_stats));
2172 static void sh_eth_get_ringparam(struct net_device *ndev,
2173 struct ethtool_ringparam *ring)
2175 struct sh_eth_private *mdp = netdev_priv(ndev);
2177 ring->rx_max_pending = RX_RING_MAX;
2178 ring->tx_max_pending = TX_RING_MAX;
2179 ring->rx_pending = mdp->num_rx_ring;
2180 ring->tx_pending = mdp->num_tx_ring;
2183 static int sh_eth_set_ringparam(struct net_device *ndev,
2184 struct ethtool_ringparam *ring)
2186 struct sh_eth_private *mdp = netdev_priv(ndev);
2189 if (ring->tx_pending > TX_RING_MAX ||
2190 ring->rx_pending > RX_RING_MAX ||
2191 ring->tx_pending < TX_RING_MIN ||
2192 ring->rx_pending < RX_RING_MIN)
2194 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2197 if (netif_running(ndev)) {
2198 netif_device_detach(ndev);
2199 netif_tx_disable(ndev);
2201 /* Serialise with the interrupt handler and NAPI, then
2202 * disable interrupts. We have to clear the
2203 * irq_enabled flag first to ensure that interrupts
2204 * won't be re-enabled.
2206 mdp->irq_enabled = false;
2207 synchronize_irq(ndev->irq);
2208 napi_synchronize(&mdp->napi);
2209 sh_eth_write(ndev, 0x0000, EESIPR);
2211 sh_eth_dev_exit(ndev);
2213 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
2214 sh_eth_ring_free(ndev);
2217 /* Set new parameters */
2218 mdp->num_rx_ring = ring->rx_pending;
2219 mdp->num_tx_ring = ring->tx_pending;
2221 if (netif_running(ndev)) {
2222 ret = sh_eth_ring_init(ndev);
2224 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2228 ret = sh_eth_dev_init(ndev, false);
2230 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2235 mdp->irq_enabled = true;
2236 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
2237 /* Setting the Rx mode will start the Rx process. */
2238 sh_eth_write(ndev, EDRRR_R, EDRRR);
2239 netif_device_attach(ndev);
2245 static const struct ethtool_ops sh_eth_ethtool_ops = {
2246 .get_settings = sh_eth_get_settings,
2247 .set_settings = sh_eth_set_settings,
2248 .get_regs_len = sh_eth_get_regs_len,
2249 .get_regs = sh_eth_get_regs,
2250 .nway_reset = sh_eth_nway_reset,
2251 .get_msglevel = sh_eth_get_msglevel,
2252 .set_msglevel = sh_eth_set_msglevel,
2253 .get_link = ethtool_op_get_link,
2254 .get_strings = sh_eth_get_strings,
2255 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2256 .get_sset_count = sh_eth_get_sset_count,
2257 .get_ringparam = sh_eth_get_ringparam,
2258 .set_ringparam = sh_eth_set_ringparam,
2261 /* network device open function */
2262 static int sh_eth_open(struct net_device *ndev)
2265 struct sh_eth_private *mdp = netdev_priv(ndev);
2267 pm_runtime_get_sync(&mdp->pdev->dev);
2269 napi_enable(&mdp->napi);
2271 ret = request_irq(ndev->irq, sh_eth_interrupt,
2272 mdp->cd->irq_flags, ndev->name, ndev);
2274 netdev_err(ndev, "Can not assign IRQ number\n");
2278 /* Descriptor set */
2279 ret = sh_eth_ring_init(ndev);
2284 ret = sh_eth_dev_init(ndev, true);
2288 /* PHY control start*/
2289 ret = sh_eth_phy_start(ndev);
2298 free_irq(ndev->irq, ndev);
2300 napi_disable(&mdp->napi);
2301 pm_runtime_put_sync(&mdp->pdev->dev);
2305 /* Timeout function */
2306 static void sh_eth_tx_timeout(struct net_device *ndev)
2308 struct sh_eth_private *mdp = netdev_priv(ndev);
2309 struct sh_eth_rxdesc *rxdesc;
2312 netif_stop_queue(ndev);
2314 netif_err(mdp, timer, ndev,
2315 "transmit timed out, status %8.8x, resetting...\n",
2316 sh_eth_read(ndev, EESR));
2318 /* tx_errors count up */
2319 ndev->stats.tx_errors++;
2321 /* Free all the skbuffs in the Rx queue. */
2322 for (i = 0; i < mdp->num_rx_ring; i++) {
2323 rxdesc = &mdp->rx_ring[i];
2325 rxdesc->addr = 0xBADF00D0;
2326 dev_kfree_skb(mdp->rx_skbuff[i]);
2327 mdp->rx_skbuff[i] = NULL;
2329 for (i = 0; i < mdp->num_tx_ring; i++) {
2330 dev_kfree_skb(mdp->tx_skbuff[i]);
2331 mdp->tx_skbuff[i] = NULL;
2335 sh_eth_dev_init(ndev, true);
2338 /* Packet transmit function */
2339 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2341 struct sh_eth_private *mdp = netdev_priv(ndev);
2342 struct sh_eth_txdesc *txdesc;
2344 unsigned long flags;
2346 spin_lock_irqsave(&mdp->lock, flags);
2347 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2348 if (!sh_eth_txfree(ndev)) {
2349 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2350 netif_stop_queue(ndev);
2351 spin_unlock_irqrestore(&mdp->lock, flags);
2352 return NETDEV_TX_BUSY;
2355 spin_unlock_irqrestore(&mdp->lock, flags);
2357 if (skb_put_padto(skb, ETH_ZLEN))
2358 return NETDEV_TX_OK;
2360 entry = mdp->cur_tx % mdp->num_tx_ring;
2361 mdp->tx_skbuff[entry] = skb;
2362 txdesc = &mdp->tx_ring[entry];
2364 if (!mdp->cd->hw_swap)
2365 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
2367 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2369 if (dma_mapping_error(&ndev->dev, txdesc->addr)) {
2371 return NETDEV_TX_OK;
2373 txdesc->buffer_length = skb->len;
2375 dma_wmb(); /* TACT bit must be set after all the above writes */
2376 if (entry >= mdp->num_tx_ring - 1)
2377 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
2379 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
2383 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2384 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2386 return NETDEV_TX_OK;
2389 /* The statistics registers have write-clear behaviour, which means we
2390 * will lose any increment between the read and write. We mitigate
2391 * this by only clearing when we read a non-zero value, so we will
2392 * never falsely report a total of zero.
2395 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2397 u32 delta = sh_eth_read(ndev, reg);
2401 sh_eth_write(ndev, 0, reg);
2405 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2407 struct sh_eth_private *mdp = netdev_priv(ndev);
2409 if (sh_eth_is_rz_fast_ether(mdp))
2410 return &ndev->stats;
2412 if (!mdp->is_opened)
2413 return &ndev->stats;
2415 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2416 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2417 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
2419 if (sh_eth_is_gether(mdp)) {
2420 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2422 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2425 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2429 return &ndev->stats;
2432 /* device close function */
2433 static int sh_eth_close(struct net_device *ndev)
2435 struct sh_eth_private *mdp = netdev_priv(ndev);
2437 netif_stop_queue(ndev);
2439 /* Serialise with the interrupt handler and NAPI, then disable
2440 * interrupts. We have to clear the irq_enabled flag first to
2441 * ensure that interrupts won't be re-enabled.
2443 mdp->irq_enabled = false;
2444 synchronize_irq(ndev->irq);
2445 napi_disable(&mdp->napi);
2446 sh_eth_write(ndev, 0x0000, EESIPR);
2448 sh_eth_dev_exit(ndev);
2450 /* PHY Disconnect */
2452 phy_stop(mdp->phydev);
2453 phy_disconnect(mdp->phydev);
2457 free_irq(ndev->irq, ndev);
2459 /* Free all the skbuffs in the Rx queue and the DMA buffer. */
2460 sh_eth_ring_free(ndev);
2462 pm_runtime_put_sync(&mdp->pdev->dev);
2469 /* ioctl to device function */
2470 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2472 struct sh_eth_private *mdp = netdev_priv(ndev);
2473 struct phy_device *phydev = mdp->phydev;
2475 if (!netif_running(ndev))
2481 return phy_mii_ioctl(phydev, rq, cmd);
2484 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2485 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2488 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2491 static u32 sh_eth_tsu_get_post_mask(int entry)
2493 return 0x0f << (28 - ((entry % 8) * 4));
2496 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2498 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2501 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2504 struct sh_eth_private *mdp = netdev_priv(ndev);
2508 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2509 tmp = ioread32(reg_offset);
2510 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2513 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2516 struct sh_eth_private *mdp = netdev_priv(ndev);
2517 u32 post_mask, ref_mask, tmp;
2520 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2521 post_mask = sh_eth_tsu_get_post_mask(entry);
2522 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2524 tmp = ioread32(reg_offset);
2525 iowrite32(tmp & ~post_mask, reg_offset);
2527 /* If other port enables, the function returns "true" */
2528 return tmp & ref_mask;
2531 static int sh_eth_tsu_busy(struct net_device *ndev)
2533 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2534 struct sh_eth_private *mdp = netdev_priv(ndev);
2536 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2540 netdev_err(ndev, "%s: timeout\n", __func__);
2548 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2553 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2554 iowrite32(val, reg);
2555 if (sh_eth_tsu_busy(ndev) < 0)
2558 val = addr[4] << 8 | addr[5];
2559 iowrite32(val, reg + 4);
2560 if (sh_eth_tsu_busy(ndev) < 0)
2566 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2570 val = ioread32(reg);
2571 addr[0] = (val >> 24) & 0xff;
2572 addr[1] = (val >> 16) & 0xff;
2573 addr[2] = (val >> 8) & 0xff;
2574 addr[3] = val & 0xff;
2575 val = ioread32(reg + 4);
2576 addr[4] = (val >> 8) & 0xff;
2577 addr[5] = val & 0xff;
2581 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2583 struct sh_eth_private *mdp = netdev_priv(ndev);
2584 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2586 u8 c_addr[ETH_ALEN];
2588 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2589 sh_eth_tsu_read_entry(reg_offset, c_addr);
2590 if (ether_addr_equal(addr, c_addr))
2597 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2602 memset(blank, 0, sizeof(blank));
2603 entry = sh_eth_tsu_find_entry(ndev, blank);
2604 return (entry < 0) ? -ENOMEM : entry;
2607 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2610 struct sh_eth_private *mdp = netdev_priv(ndev);
2611 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2615 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2616 ~(1 << (31 - entry)), TSU_TEN);
2618 memset(blank, 0, sizeof(blank));
2619 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2625 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2627 struct sh_eth_private *mdp = netdev_priv(ndev);
2628 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2634 i = sh_eth_tsu_find_entry(ndev, addr);
2636 /* No entry found, create one */
2637 i = sh_eth_tsu_find_empty(ndev);
2640 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2644 /* Enable the entry */
2645 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2646 (1 << (31 - i)), TSU_TEN);
2649 /* Entry found or created, enable POST */
2650 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2655 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2657 struct sh_eth_private *mdp = netdev_priv(ndev);
2663 i = sh_eth_tsu_find_entry(ndev, addr);
2666 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2669 /* Disable the entry if both ports was disabled */
2670 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2678 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2680 struct sh_eth_private *mdp = netdev_priv(ndev);
2686 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2687 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2690 /* Disable the entry if both ports was disabled */
2691 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2699 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2701 struct sh_eth_private *mdp = netdev_priv(ndev);
2703 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2709 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2710 sh_eth_tsu_read_entry(reg_offset, addr);
2711 if (is_multicast_ether_addr(addr))
2712 sh_eth_tsu_del_entry(ndev, addr);
2716 /* Update promiscuous flag and multicast filter */
2717 static void sh_eth_set_rx_mode(struct net_device *ndev)
2719 struct sh_eth_private *mdp = netdev_priv(ndev);
2722 unsigned long flags;
2724 spin_lock_irqsave(&mdp->lock, flags);
2725 /* Initial condition is MCT = 1, PRM = 0.
2726 * Depending on ndev->flags, set PRM or clear MCT
2728 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2730 ecmr_bits |= ECMR_MCT;
2732 if (!(ndev->flags & IFF_MULTICAST)) {
2733 sh_eth_tsu_purge_mcast(ndev);
2736 if (ndev->flags & IFF_ALLMULTI) {
2737 sh_eth_tsu_purge_mcast(ndev);
2738 ecmr_bits &= ~ECMR_MCT;
2742 if (ndev->flags & IFF_PROMISC) {
2743 sh_eth_tsu_purge_all(ndev);
2744 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2745 } else if (mdp->cd->tsu) {
2746 struct netdev_hw_addr *ha;
2747 netdev_for_each_mc_addr(ha, ndev) {
2748 if (mcast_all && is_multicast_ether_addr(ha->addr))
2751 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2753 sh_eth_tsu_purge_mcast(ndev);
2754 ecmr_bits &= ~ECMR_MCT;
2761 /* update the ethernet mode */
2762 sh_eth_write(ndev, ecmr_bits, ECMR);
2764 spin_unlock_irqrestore(&mdp->lock, flags);
2767 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2775 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2776 __be16 proto, u16 vid)
2778 struct sh_eth_private *mdp = netdev_priv(ndev);
2779 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2781 if (unlikely(!mdp->cd->tsu))
2784 /* No filtering if vid = 0 */
2788 mdp->vlan_num_ids++;
2790 /* The controller has one VLAN tag HW filter. So, if the filter is
2791 * already enabled, the driver disables it and the filte
2793 if (mdp->vlan_num_ids > 1) {
2794 /* disable VLAN filter */
2795 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2799 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2805 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2806 __be16 proto, u16 vid)
2808 struct sh_eth_private *mdp = netdev_priv(ndev);
2809 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2811 if (unlikely(!mdp->cd->tsu))
2814 /* No filtering if vid = 0 */
2818 mdp->vlan_num_ids--;
2819 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2824 /* SuperH's TSU register init function */
2825 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2827 if (sh_eth_is_rz_fast_ether(mdp)) {
2828 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2832 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2833 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2834 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2835 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2836 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2837 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2838 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2839 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2840 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2841 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2842 if (sh_eth_is_gether(mdp)) {
2843 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2844 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2846 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2847 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2849 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2850 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2851 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2852 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2853 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2854 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2855 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
2858 /* MDIO bus release function */
2859 static int sh_mdio_release(struct sh_eth_private *mdp)
2861 /* unregister mdio bus */
2862 mdiobus_unregister(mdp->mii_bus);
2864 /* free bitbang info */
2865 free_mdio_bitbang(mdp->mii_bus);
2870 /* MDIO bus init function */
2871 static int sh_mdio_init(struct sh_eth_private *mdp,
2872 struct sh_eth_plat_data *pd)
2875 struct bb_info *bitbang;
2876 struct platform_device *pdev = mdp->pdev;
2877 struct device *dev = &mdp->pdev->dev;
2879 /* create bit control struct for PHY */
2880 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
2885 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2886 bitbang->set_gate = pd->set_mdio_gate;
2887 bitbang->ctrl.ops = &bb_ops;
2889 /* MII controller setting */
2890 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2894 /* Hook up MII support for ethtool */
2895 mdp->mii_bus->name = "sh_mii";
2896 mdp->mii_bus->parent = dev;
2897 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2898 pdev->name, pdev->id);
2901 mdp->mii_bus->irq = devm_kmalloc_array(dev, PHY_MAX_ADDR, sizeof(int),
2903 if (!mdp->mii_bus->irq) {
2908 /* register MDIO bus */
2910 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
2912 for (i = 0; i < PHY_MAX_ADDR; i++)
2913 mdp->mii_bus->irq[i] = PHY_POLL;
2914 if (pd->phy_irq > 0)
2915 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2917 ret = mdiobus_register(mdp->mii_bus);
2926 free_mdio_bitbang(mdp->mii_bus);
2930 static const u16 *sh_eth_get_register_offset(int register_type)
2932 const u16 *reg_offset = NULL;
2934 switch (register_type) {
2935 case SH_ETH_REG_GIGABIT:
2936 reg_offset = sh_eth_offset_gigabit;
2938 case SH_ETH_REG_FAST_RZ:
2939 reg_offset = sh_eth_offset_fast_rz;
2941 case SH_ETH_REG_FAST_RCAR:
2942 reg_offset = sh_eth_offset_fast_rcar;
2944 case SH_ETH_REG_FAST_SH4:
2945 reg_offset = sh_eth_offset_fast_sh4;
2947 case SH_ETH_REG_FAST_SH3_SH2:
2948 reg_offset = sh_eth_offset_fast_sh3_sh2;
2957 static const struct net_device_ops sh_eth_netdev_ops = {
2958 .ndo_open = sh_eth_open,
2959 .ndo_stop = sh_eth_close,
2960 .ndo_start_xmit = sh_eth_start_xmit,
2961 .ndo_get_stats = sh_eth_get_stats,
2962 .ndo_set_rx_mode = sh_eth_set_rx_mode,
2963 .ndo_tx_timeout = sh_eth_tx_timeout,
2964 .ndo_do_ioctl = sh_eth_do_ioctl,
2965 .ndo_validate_addr = eth_validate_addr,
2966 .ndo_set_mac_address = eth_mac_addr,
2967 .ndo_change_mtu = eth_change_mtu,
2970 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2971 .ndo_open = sh_eth_open,
2972 .ndo_stop = sh_eth_close,
2973 .ndo_start_xmit = sh_eth_start_xmit,
2974 .ndo_get_stats = sh_eth_get_stats,
2975 .ndo_set_rx_mode = sh_eth_set_rx_mode,
2976 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
2977 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
2978 .ndo_tx_timeout = sh_eth_tx_timeout,
2979 .ndo_do_ioctl = sh_eth_do_ioctl,
2980 .ndo_validate_addr = eth_validate_addr,
2981 .ndo_set_mac_address = eth_mac_addr,
2982 .ndo_change_mtu = eth_change_mtu,
2986 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2988 struct device_node *np = dev->of_node;
2989 struct sh_eth_plat_data *pdata;
2990 const char *mac_addr;
2992 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2996 pdata->phy_interface = of_get_phy_mode(np);
2998 mac_addr = of_get_mac_address(np);
3000 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
3002 pdata->no_ether_link =
3003 of_property_read_bool(np, "renesas,no-ether-link");
3004 pdata->ether_link_active_low =
3005 of_property_read_bool(np, "renesas,ether-link-active-low");
3010 static const struct of_device_id sh_eth_match_table[] = {
3011 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
3012 { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
3013 { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
3014 { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
3015 { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
3016 { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
3017 { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
3018 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
3021 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
3023 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3029 static int sh_eth_drv_probe(struct platform_device *pdev)
3032 struct resource *res;
3033 struct net_device *ndev = NULL;
3034 struct sh_eth_private *mdp = NULL;
3035 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
3036 const struct platform_device_id *id = platform_get_device_id(pdev);
3039 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3041 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
3045 pm_runtime_enable(&pdev->dev);
3046 pm_runtime_get_sync(&pdev->dev);
3053 ret = platform_get_irq(pdev, 0);
3058 SET_NETDEV_DEV(ndev, &pdev->dev);
3060 mdp = netdev_priv(ndev);
3061 mdp->num_tx_ring = TX_RING_SIZE;
3062 mdp->num_rx_ring = RX_RING_SIZE;
3063 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3064 if (IS_ERR(mdp->addr)) {
3065 ret = PTR_ERR(mdp->addr);
3069 ndev->base_addr = res->start;
3071 spin_lock_init(&mdp->lock);
3074 if (pdev->dev.of_node)
3075 pd = sh_eth_parse_dt(&pdev->dev);
3077 dev_err(&pdev->dev, "no platform data\n");
3083 mdp->phy_id = pd->phy;
3084 mdp->phy_interface = pd->phy_interface;
3086 mdp->edmac_endian = pd->edmac_endian;
3087 mdp->no_ether_link = pd->no_ether_link;
3088 mdp->ether_link_active_low = pd->ether_link_active_low;
3092 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3094 const struct of_device_id *match;
3096 match = of_match_device(of_match_ptr(sh_eth_match_table),
3098 mdp->cd = (struct sh_eth_cpu_data *)match->data;
3100 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
3101 if (!mdp->reg_offset) {
3102 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3103 mdp->cd->register_type);
3107 sh_eth_set_default_cpu_data(mdp->cd);
3111 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3113 ndev->netdev_ops = &sh_eth_netdev_ops;
3114 ndev->ethtool_ops = &sh_eth_ethtool_ops;
3115 ndev->watchdog_timeo = TX_TIMEOUT;
3117 /* debug message level */
3118 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
3120 /* read and set MAC address */
3121 read_mac_address(ndev, pd->mac_addr);
3122 if (!is_valid_ether_addr(ndev->dev_addr)) {
3123 dev_warn(&pdev->dev,
3124 "no valid MAC address supplied, using a random one.\n");
3125 eth_hw_addr_random(ndev);
3128 /* ioremap the TSU registers */
3130 struct resource *rtsu;
3131 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3132 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
3133 if (IS_ERR(mdp->tsu_addr)) {
3134 ret = PTR_ERR(mdp->tsu_addr);
3137 mdp->port = devno % 2;
3138 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
3141 /* initialize first or needed device */
3142 if (!devno || pd->needs_init) {
3143 if (mdp->cd->chip_reset)
3144 mdp->cd->chip_reset(ndev);
3147 /* TSU init (Init only)*/
3148 sh_eth_tsu_init(mdp);
3152 if (mdp->cd->rmiimode)
3153 sh_eth_write(ndev, 0x1, RMIIMODE);
3156 ret = sh_mdio_init(mdp, pd);
3158 dev_err(&ndev->dev, "failed to initialise MDIO\n");
3162 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3164 /* network device register */
3165 ret = register_netdev(ndev);
3169 /* print device information */
3170 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3171 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
3173 pm_runtime_put(&pdev->dev);
3174 platform_set_drvdata(pdev, ndev);
3179 netif_napi_del(&mdp->napi);
3180 sh_mdio_release(mdp);
3187 pm_runtime_put(&pdev->dev);
3188 pm_runtime_disable(&pdev->dev);
3192 static int sh_eth_drv_remove(struct platform_device *pdev)
3194 struct net_device *ndev = platform_get_drvdata(pdev);
3195 struct sh_eth_private *mdp = netdev_priv(ndev);
3197 unregister_netdev(ndev);
3198 netif_napi_del(&mdp->napi);
3199 sh_mdio_release(mdp);
3200 pm_runtime_disable(&pdev->dev);
3207 #ifdef CONFIG_PM_SLEEP
3208 static int sh_eth_suspend(struct device *dev)
3210 struct net_device *ndev = dev_get_drvdata(dev);
3213 if (netif_running(ndev)) {
3214 netif_device_detach(ndev);
3215 ret = sh_eth_close(ndev);
3221 static int sh_eth_resume(struct device *dev)
3223 struct net_device *ndev = dev_get_drvdata(dev);
3226 if (netif_running(ndev)) {
3227 ret = sh_eth_open(ndev);
3230 netif_device_attach(ndev);
3237 static int sh_eth_runtime_nop(struct device *dev)
3239 /* Runtime PM callback shared between ->runtime_suspend()
3240 * and ->runtime_resume(). Simply returns success.
3242 * This driver re-initializes all registers after
3243 * pm_runtime_get_sync() anyway so there is no need
3244 * to save and restore registers here.
3249 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
3250 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
3251 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
3253 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3255 #define SH_ETH_PM_OPS NULL
3258 static struct platform_device_id sh_eth_id_table[] = {
3259 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3260 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3261 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3262 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3263 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3264 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3265 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3268 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3270 static struct platform_driver sh_eth_driver = {
3271 .probe = sh_eth_drv_probe,
3272 .remove = sh_eth_drv_remove,
3273 .id_table = sh_eth_id_table,
3276 .pm = SH_ETH_PM_OPS,
3277 .of_match_table = of_match_ptr(sh_eth_match_table),
3281 module_platform_driver(sh_eth_driver);
3283 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3284 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3285 MODULE_LICENSE("GPL v2");