1 /* 10G controller driver for Samsung SoCs
3 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * Author: Siva Reddy Kallam <siva.kallam@samsung.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15 #include <linux/clk.h>
16 #include <linux/crc32.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/etherdevice.h>
19 #include <linux/ethtool.h>
21 #include <linux/if_ether.h>
22 #include <linux/if_vlan.h>
23 #include <linux/init.h>
24 #include <linux/interrupt.h>
26 #include <linux/kernel.h>
27 #include <linux/mii.h>
28 #include <linux/module.h>
29 #include <linux/net_tstamp.h>
30 #include <linux/netdevice.h>
31 #include <linux/phy.h>
32 #include <linux/platform_device.h>
33 #include <linux/prefetch.h>
34 #include <linux/skbuff.h>
35 #include <linux/slab.h>
36 #include <linux/tcp.h>
37 #include <linux/sxgbe_platform.h>
39 #include "sxgbe_common.h"
40 #include "sxgbe_desc.h"
41 #include "sxgbe_dma.h"
42 #include "sxgbe_mtl.h"
43 #include "sxgbe_reg.h"
45 #define SXGBE_ALIGN(x) L1_CACHE_ALIGN(x)
46 #define JUMBO_LEN 9000
48 /* Module parameters */
50 #define DMA_TX_SIZE 512
51 #define DMA_RX_SIZE 1024
53 #define DMA_BUFFER_SIZE BUF_SIZE_2KiB
54 /* The default timer value as per the sxgbe specification 1 sec(1000 ms) */
55 #define SXGBE_DEFAULT_LPI_TIMER 1000
57 static int debug = -1;
58 static int eee_timer = SXGBE_DEFAULT_LPI_TIMER;
60 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
62 module_param(debug, int, S_IRUGO | S_IWUSR);
63 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
64 NETIF_MSG_LINK | NETIF_MSG_IFUP |
65 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
67 static irqreturn_t sxgbe_common_interrupt(int irq, void *dev_id);
68 static irqreturn_t sxgbe_tx_interrupt(int irq, void *dev_id);
69 static irqreturn_t sxgbe_rx_interrupt(int irq, void *dev_id);
71 #define SXGBE_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
73 #define SXGBE_LPI_TIMER(x) (jiffies + msecs_to_jiffies(x))
76 * sxgbe_verify_args - verify the driver parameters.
77 * Description: it verifies if some wrong parameter is passed to the driver.
78 * Note that wrong parameters are replaced with the default values.
80 static void sxgbe_verify_args(void)
82 if (unlikely(eee_timer < 0))
83 eee_timer = SXGBE_DEFAULT_LPI_TIMER;
86 static void sxgbe_enable_eee_mode(const struct sxgbe_priv_data *priv)
88 /* Check and enter in LPI mode */
89 if (!priv->tx_path_in_lpi_mode)
90 priv->hw->mac->set_eee_mode(priv->ioaddr);
93 void sxgbe_disable_eee_mode(struct sxgbe_priv_data * const priv)
95 /* Exit and disable EEE in case of we are are in LPI state. */
96 priv->hw->mac->reset_eee_mode(priv->ioaddr);
97 del_timer_sync(&priv->eee_ctrl_timer);
98 priv->tx_path_in_lpi_mode = false;
102 * sxgbe_eee_ctrl_timer
105 * If there is no data transfer and if we are not in LPI state,
106 * then MAC Transmitter can be moved to LPI state.
108 static void sxgbe_eee_ctrl_timer(unsigned long arg)
110 struct sxgbe_priv_data *priv = (struct sxgbe_priv_data *)arg;
112 sxgbe_enable_eee_mode(priv);
113 mod_timer(&priv->eee_ctrl_timer, SXGBE_LPI_TIMER(eee_timer));
118 * @priv: private device pointer
120 * If the EEE support has been enabled while configuring the driver,
121 * if the GMAC actually supports the EEE (from the HW cap reg) and the
122 * phy can also manage EEE, so enable the LPI state and start the timer
123 * to verify if the tx path can enter in LPI state.
125 bool sxgbe_eee_init(struct sxgbe_priv_data * const priv)
127 struct net_device *ndev = priv->dev;
130 /* MAC core supports the EEE feature. */
131 if (priv->hw_cap.eee) {
132 /* Check if the PHY supports EEE */
133 if (phy_init_eee(ndev->phydev, 1))
136 priv->eee_active = 1;
137 setup_timer(&priv->eee_ctrl_timer, sxgbe_eee_ctrl_timer,
138 (unsigned long)priv);
139 priv->eee_ctrl_timer.expires = SXGBE_LPI_TIMER(eee_timer);
140 add_timer(&priv->eee_ctrl_timer);
142 priv->hw->mac->set_eee_timer(priv->ioaddr,
143 SXGBE_DEFAULT_LPI_TIMER,
146 pr_info("Energy-Efficient Ethernet initialized\n");
154 static void sxgbe_eee_adjust(const struct sxgbe_priv_data *priv)
156 struct net_device *ndev = priv->dev;
158 /* When the EEE has been already initialised we have to
159 * modify the PLS bit in the LPI ctrl & status reg according
160 * to the PHY link status. For this reason.
162 if (priv->eee_enabled)
163 priv->hw->mac->set_eee_pls(priv->ioaddr, ndev->phydev->link);
167 * sxgbe_clk_csr_set - dynamically set the MDC clock
168 * @priv: driver private structure
169 * Description: this is to dynamically set the MDC clock according to the csr
172 static void sxgbe_clk_csr_set(struct sxgbe_priv_data *priv)
174 u32 clk_rate = clk_get_rate(priv->sxgbe_clk);
176 /* assign the proper divider, this will be used during
179 if (clk_rate < SXGBE_CSR_F_150M)
180 priv->clk_csr = SXGBE_CSR_100_150M;
181 else if (clk_rate <= SXGBE_CSR_F_250M)
182 priv->clk_csr = SXGBE_CSR_150_250M;
183 else if (clk_rate <= SXGBE_CSR_F_300M)
184 priv->clk_csr = SXGBE_CSR_250_300M;
185 else if (clk_rate <= SXGBE_CSR_F_350M)
186 priv->clk_csr = SXGBE_CSR_300_350M;
187 else if (clk_rate <= SXGBE_CSR_F_400M)
188 priv->clk_csr = SXGBE_CSR_350_400M;
189 else if (clk_rate <= SXGBE_CSR_F_500M)
190 priv->clk_csr = SXGBE_CSR_400_500M;
193 /* minimum number of free TX descriptors required to wake up TX process */
194 #define SXGBE_TX_THRESH(x) (x->dma_tx_size/4)
196 static inline u32 sxgbe_tx_avail(struct sxgbe_tx_queue *queue, int tx_qsize)
198 return queue->dirty_tx + tx_qsize - queue->cur_tx - 1;
203 * @dev: net device structure
204 * Description: it adjusts the link parameters.
206 static void sxgbe_adjust_link(struct net_device *dev)
208 struct sxgbe_priv_data *priv = netdev_priv(dev);
209 struct phy_device *phydev = dev->phydev;
216 /* SXGBE is not supporting auto-negotiation and
217 * half duplex mode. so, not handling duplex change
218 * in this function. only handling speed and link status
221 if (phydev->speed != priv->speed) {
223 switch (phydev->speed) {
225 speed = SXGBE_SPEED_10G;
228 speed = SXGBE_SPEED_2_5G;
231 speed = SXGBE_SPEED_1G;
234 netif_err(priv, link, dev,
235 "Speed (%d) not supported\n",
239 priv->speed = phydev->speed;
240 priv->hw->mac->set_speed(priv->ioaddr, speed);
243 if (!priv->oldlink) {
247 } else if (priv->oldlink) {
250 priv->speed = SPEED_UNKNOWN;
253 if (new_state & netif_msg_link(priv))
254 phy_print_status(phydev);
256 /* Alter the MAC settings for EEE */
257 sxgbe_eee_adjust(priv);
261 * sxgbe_init_phy - PHY initialization
262 * @dev: net device structure
263 * Description: it initializes the driver's PHY state, and attaches the PHY
268 static int sxgbe_init_phy(struct net_device *ndev)
270 char phy_id_fmt[MII_BUS_ID_SIZE + 3];
271 char bus_id[MII_BUS_ID_SIZE];
272 struct phy_device *phydev;
273 struct sxgbe_priv_data *priv = netdev_priv(ndev);
274 int phy_iface = priv->plat->interface;
276 /* assign default link status */
278 priv->speed = SPEED_UNKNOWN;
279 priv->oldduplex = DUPLEX_UNKNOWN;
281 if (priv->plat->phy_bus_name)
282 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
283 priv->plat->phy_bus_name, priv->plat->bus_id);
285 snprintf(bus_id, MII_BUS_ID_SIZE, "sxgbe-%x",
288 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
289 priv->plat->phy_addr);
290 netdev_dbg(ndev, "%s: trying to attach to %s\n", __func__, phy_id_fmt);
292 phydev = phy_connect(ndev, phy_id_fmt, &sxgbe_adjust_link, phy_iface);
294 if (IS_ERR(phydev)) {
295 netdev_err(ndev, "Could not attach to PHY\n");
296 return PTR_ERR(phydev);
299 /* Stop Advertising 1000BASE Capability if interface is not GMII */
300 if ((phy_iface == PHY_INTERFACE_MODE_MII) ||
301 (phy_iface == PHY_INTERFACE_MODE_RMII))
302 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
303 SUPPORTED_1000baseT_Full);
304 if (phydev->phy_id == 0) {
305 phy_disconnect(phydev);
309 netdev_dbg(ndev, "%s: attached to PHY (UID 0x%x) Link = %d\n",
310 __func__, phydev->phy_id, phydev->link);
316 * sxgbe_clear_descriptors: clear descriptors
317 * @priv: driver private structure
318 * Description: this function is called to clear the tx and rx descriptors
319 * in case of both basic and extended descriptors are used.
321 static void sxgbe_clear_descriptors(struct sxgbe_priv_data *priv)
324 unsigned int txsize = priv->dma_tx_size;
325 unsigned int rxsize = priv->dma_rx_size;
327 /* Clear the Rx/Tx descriptors */
328 for (j = 0; j < SXGBE_RX_QUEUES; j++) {
329 for (i = 0; i < rxsize; i++)
330 priv->hw->desc->init_rx_desc(&priv->rxq[j]->dma_rx[i],
331 priv->use_riwt, priv->mode,
335 for (j = 0; j < SXGBE_TX_QUEUES; j++) {
336 for (i = 0; i < txsize; i++)
337 priv->hw->desc->init_tx_desc(&priv->txq[j]->dma_tx[i]);
341 static int sxgbe_init_rx_buffers(struct net_device *dev,
342 struct sxgbe_rx_norm_desc *p, int i,
343 unsigned int dma_buf_sz,
344 struct sxgbe_rx_queue *rx_ring)
346 struct sxgbe_priv_data *priv = netdev_priv(dev);
349 skb = __netdev_alloc_skb_ip_align(dev, dma_buf_sz, GFP_KERNEL);
353 rx_ring->rx_skbuff[i] = skb;
354 rx_ring->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
355 dma_buf_sz, DMA_FROM_DEVICE);
357 if (dma_mapping_error(priv->device, rx_ring->rx_skbuff_dma[i])) {
358 netdev_err(dev, "%s: DMA mapping error\n", __func__);
359 dev_kfree_skb_any(skb);
363 p->rdes23.rx_rd_des23.buf2_addr = rx_ring->rx_skbuff_dma[i];
369 * sxgbe_free_rx_buffers - free what sxgbe_init_rx_buffers() allocated
370 * @dev: net device structure
371 * @rx_ring: ring to be freed
372 * @rx_rsize: ring size
373 * Description: this function initializes the DMA RX descriptor
375 static void sxgbe_free_rx_buffers(struct net_device *dev,
376 struct sxgbe_rx_norm_desc *p, int i,
377 unsigned int dma_buf_sz,
378 struct sxgbe_rx_queue *rx_ring)
380 struct sxgbe_priv_data *priv = netdev_priv(dev);
382 kfree_skb(rx_ring->rx_skbuff[i]);
383 dma_unmap_single(priv->device, rx_ring->rx_skbuff_dma[i],
384 dma_buf_sz, DMA_FROM_DEVICE);
388 * init_tx_ring - init the TX descriptor ring
389 * @dev: net device structure
390 * @tx_ring: ring to be initialised
391 * @tx_rsize: ring size
392 * Description: this function initializes the DMA TX descriptor
394 static int init_tx_ring(struct device *dev, u8 queue_no,
395 struct sxgbe_tx_queue *tx_ring, int tx_rsize)
397 /* TX ring is not allcoated */
399 dev_err(dev, "No memory for TX queue of SXGBE\n");
403 /* allocate memory for TX descriptors */
404 tx_ring->dma_tx = dma_zalloc_coherent(dev,
405 tx_rsize * sizeof(struct sxgbe_tx_norm_desc),
406 &tx_ring->dma_tx_phy, GFP_KERNEL);
407 if (!tx_ring->dma_tx)
410 /* allocate memory for TX skbuff array */
411 tx_ring->tx_skbuff_dma = devm_kcalloc(dev, tx_rsize,
412 sizeof(dma_addr_t), GFP_KERNEL);
413 if (!tx_ring->tx_skbuff_dma)
416 tx_ring->tx_skbuff = devm_kcalloc(dev, tx_rsize,
417 sizeof(struct sk_buff *), GFP_KERNEL);
419 if (!tx_ring->tx_skbuff)
422 /* assign queue number */
423 tx_ring->queue_no = queue_no;
425 /* initialise counters */
426 tx_ring->dirty_tx = 0;
432 dma_free_coherent(dev, tx_rsize * sizeof(struct sxgbe_tx_norm_desc),
433 tx_ring->dma_tx, tx_ring->dma_tx_phy);
438 * free_rx_ring - free the RX descriptor ring
439 * @dev: net device structure
440 * @rx_ring: ring to be initialised
441 * @rx_rsize: ring size
442 * Description: this function initializes the DMA RX descriptor
444 static void free_rx_ring(struct device *dev, struct sxgbe_rx_queue *rx_ring,
447 dma_free_coherent(dev, rx_rsize * sizeof(struct sxgbe_rx_norm_desc),
448 rx_ring->dma_rx, rx_ring->dma_rx_phy);
449 kfree(rx_ring->rx_skbuff_dma);
450 kfree(rx_ring->rx_skbuff);
454 * init_rx_ring - init the RX descriptor ring
455 * @dev: net device structure
456 * @rx_ring: ring to be initialised
457 * @rx_rsize: ring size
458 * Description: this function initializes the DMA RX descriptor
460 static int init_rx_ring(struct net_device *dev, u8 queue_no,
461 struct sxgbe_rx_queue *rx_ring, int rx_rsize)
463 struct sxgbe_priv_data *priv = netdev_priv(dev);
465 unsigned int bfsize = 0;
466 unsigned int ret = 0;
468 /* Set the max buffer size according to the MTU. */
469 bfsize = ALIGN(dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN, 8);
471 netif_dbg(priv, probe, dev, "%s: bfsize %d\n", __func__, bfsize);
473 /* RX ring is not allcoated */
474 if (rx_ring == NULL) {
475 netdev_err(dev, "No memory for RX queue\n");
479 /* assign queue number */
480 rx_ring->queue_no = queue_no;
482 /* allocate memory for RX descriptors */
483 rx_ring->dma_rx = dma_zalloc_coherent(priv->device,
484 rx_rsize * sizeof(struct sxgbe_rx_norm_desc),
485 &rx_ring->dma_rx_phy, GFP_KERNEL);
487 if (rx_ring->dma_rx == NULL)
490 /* allocate memory for RX skbuff array */
491 rx_ring->rx_skbuff_dma = kmalloc_array(rx_rsize,
492 sizeof(dma_addr_t), GFP_KERNEL);
493 if (!rx_ring->rx_skbuff_dma) {
495 goto err_free_dma_rx;
498 rx_ring->rx_skbuff = kmalloc_array(rx_rsize,
499 sizeof(struct sk_buff *), GFP_KERNEL);
500 if (!rx_ring->rx_skbuff) {
502 goto err_free_skbuff_dma;
505 /* initialise the buffers */
506 for (desc_index = 0; desc_index < rx_rsize; desc_index++) {
507 struct sxgbe_rx_norm_desc *p;
508 p = rx_ring->dma_rx + desc_index;
509 ret = sxgbe_init_rx_buffers(dev, p, desc_index,
512 goto err_free_rx_buffers;
515 /* initialise counters */
517 rx_ring->dirty_rx = (unsigned int)(desc_index - rx_rsize);
518 priv->dma_buf_sz = bfsize;
523 while (--desc_index >= 0) {
524 struct sxgbe_rx_norm_desc *p;
526 p = rx_ring->dma_rx + desc_index;
527 sxgbe_free_rx_buffers(dev, p, desc_index, bfsize, rx_ring);
529 kfree(rx_ring->rx_skbuff);
531 kfree(rx_ring->rx_skbuff_dma);
533 dma_free_coherent(priv->device,
534 rx_rsize * sizeof(struct sxgbe_rx_norm_desc),
535 rx_ring->dma_rx, rx_ring->dma_rx_phy);
540 * free_tx_ring - free the TX descriptor ring
541 * @dev: net device structure
542 * @tx_ring: ring to be initialised
543 * @tx_rsize: ring size
544 * Description: this function initializes the DMA TX descriptor
546 static void free_tx_ring(struct device *dev, struct sxgbe_tx_queue *tx_ring,
549 dma_free_coherent(dev, tx_rsize * sizeof(struct sxgbe_tx_norm_desc),
550 tx_ring->dma_tx, tx_ring->dma_tx_phy);
554 * init_dma_desc_rings - init the RX/TX descriptor rings
555 * @dev: net device structure
556 * Description: this function initializes the DMA RX/TX descriptors
557 * and allocates the socket buffers. It suppors the chained and ring
560 static int init_dma_desc_rings(struct net_device *netd)
563 struct sxgbe_priv_data *priv = netdev_priv(netd);
564 int tx_rsize = priv->dma_tx_size;
565 int rx_rsize = priv->dma_rx_size;
567 /* Allocate memory for queue structures and TX descs */
568 SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
569 ret = init_tx_ring(priv->device, queue_num,
570 priv->txq[queue_num], tx_rsize);
572 dev_err(&netd->dev, "TX DMA ring allocation failed!\n");
576 /* save private pointer in each ring this
577 * pointer is needed during cleaing TX queue
579 priv->txq[queue_num]->priv_ptr = priv;
582 /* Allocate memory for queue structures and RX descs */
583 SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) {
584 ret = init_rx_ring(netd, queue_num,
585 priv->rxq[queue_num], rx_rsize);
587 netdev_err(netd, "RX DMA ring allocation failed!!\n");
591 /* save private pointer in each ring this
592 * pointer is needed during cleaing TX queue
594 priv->rxq[queue_num]->priv_ptr = priv;
597 sxgbe_clear_descriptors(priv);
603 free_tx_ring(priv->device, priv->txq[queue_num], tx_rsize);
608 free_rx_ring(priv->device, priv->rxq[queue_num], rx_rsize);
612 static void tx_free_ring_skbufs(struct sxgbe_tx_queue *txqueue)
615 struct sxgbe_priv_data *priv = txqueue->priv_ptr;
616 int tx_rsize = priv->dma_tx_size;
618 for (dma_desc = 0; dma_desc < tx_rsize; dma_desc++) {
619 struct sxgbe_tx_norm_desc *tdesc = txqueue->dma_tx + dma_desc;
621 if (txqueue->tx_skbuff_dma[dma_desc])
622 dma_unmap_single(priv->device,
623 txqueue->tx_skbuff_dma[dma_desc],
624 priv->hw->desc->get_tx_len(tdesc),
627 dev_kfree_skb_any(txqueue->tx_skbuff[dma_desc]);
628 txqueue->tx_skbuff[dma_desc] = NULL;
629 txqueue->tx_skbuff_dma[dma_desc] = 0;
634 static void dma_free_tx_skbufs(struct sxgbe_priv_data *priv)
638 SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
639 struct sxgbe_tx_queue *tqueue = priv->txq[queue_num];
640 tx_free_ring_skbufs(tqueue);
644 static void free_dma_desc_resources(struct sxgbe_priv_data *priv)
647 int tx_rsize = priv->dma_tx_size;
648 int rx_rsize = priv->dma_rx_size;
650 /* Release the DMA TX buffers */
651 dma_free_tx_skbufs(priv);
653 /* Release the TX ring memory also */
654 SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
655 free_tx_ring(priv->device, priv->txq[queue_num], tx_rsize);
658 /* Release the RX ring memory also */
659 SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) {
660 free_rx_ring(priv->device, priv->rxq[queue_num], rx_rsize);
664 static int txring_mem_alloc(struct sxgbe_priv_data *priv)
668 SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
669 priv->txq[queue_num] = devm_kmalloc(priv->device,
670 sizeof(struct sxgbe_tx_queue), GFP_KERNEL);
671 if (!priv->txq[queue_num])
678 static int rxring_mem_alloc(struct sxgbe_priv_data *priv)
682 SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) {
683 priv->rxq[queue_num] = devm_kmalloc(priv->device,
684 sizeof(struct sxgbe_rx_queue), GFP_KERNEL);
685 if (!priv->rxq[queue_num])
693 * sxgbe_mtl_operation_mode - HW MTL operation mode
694 * @priv: driver private structure
695 * Description: it sets the MTL operation mode: tx/rx MTL thresholds
696 * or Store-And-Forward capability.
698 static void sxgbe_mtl_operation_mode(struct sxgbe_priv_data *priv)
702 /* TX/RX threshold control */
703 if (likely(priv->plat->force_sf_dma_mode)) {
704 /* set TC mode for TX QUEUES */
705 SXGBE_FOR_EACH_QUEUE(priv->hw_cap.tx_mtl_queues, queue_num)
706 priv->hw->mtl->set_tx_mtl_mode(priv->ioaddr, queue_num,
708 priv->tx_tc = SXGBE_MTL_SFMODE;
710 /* set TC mode for RX QUEUES */
711 SXGBE_FOR_EACH_QUEUE(priv->hw_cap.rx_mtl_queues, queue_num)
712 priv->hw->mtl->set_rx_mtl_mode(priv->ioaddr, queue_num,
714 priv->rx_tc = SXGBE_MTL_SFMODE;
715 } else if (unlikely(priv->plat->force_thresh_dma_mode)) {
716 /* set TC mode for TX QUEUES */
717 SXGBE_FOR_EACH_QUEUE(priv->hw_cap.tx_mtl_queues, queue_num)
718 priv->hw->mtl->set_tx_mtl_mode(priv->ioaddr, queue_num,
720 /* set TC mode for RX QUEUES */
721 SXGBE_FOR_EACH_QUEUE(priv->hw_cap.rx_mtl_queues, queue_num)
722 priv->hw->mtl->set_rx_mtl_mode(priv->ioaddr, queue_num,
725 pr_err("ERROR: %s: Invalid TX threshold mode\n", __func__);
730 * sxgbe_tx_queue_clean:
731 * @priv: driver private structure
732 * Description: it reclaims resources after transmission completes.
734 static void sxgbe_tx_queue_clean(struct sxgbe_tx_queue *tqueue)
736 struct sxgbe_priv_data *priv = tqueue->priv_ptr;
737 unsigned int tx_rsize = priv->dma_tx_size;
738 struct netdev_queue *dev_txq;
739 u8 queue_no = tqueue->queue_no;
741 dev_txq = netdev_get_tx_queue(priv->dev, queue_no);
743 __netif_tx_lock(dev_txq, smp_processor_id());
745 priv->xstats.tx_clean++;
746 while (tqueue->dirty_tx != tqueue->cur_tx) {
747 unsigned int entry = tqueue->dirty_tx % tx_rsize;
748 struct sk_buff *skb = tqueue->tx_skbuff[entry];
749 struct sxgbe_tx_norm_desc *p;
751 p = tqueue->dma_tx + entry;
753 /* Check if the descriptor is owned by the DMA. */
754 if (priv->hw->desc->get_tx_owner(p))
757 if (netif_msg_tx_done(priv))
758 pr_debug("%s: curr %d, dirty %d\n",
759 __func__, tqueue->cur_tx, tqueue->dirty_tx);
761 if (likely(tqueue->tx_skbuff_dma[entry])) {
762 dma_unmap_single(priv->device,
763 tqueue->tx_skbuff_dma[entry],
764 priv->hw->desc->get_tx_len(p),
766 tqueue->tx_skbuff_dma[entry] = 0;
771 tqueue->tx_skbuff[entry] = NULL;
774 priv->hw->desc->release_tx_desc(p);
780 if (unlikely(netif_tx_queue_stopped(dev_txq) &&
781 sxgbe_tx_avail(tqueue, tx_rsize) > SXGBE_TX_THRESH(priv))) {
782 if (netif_msg_tx_done(priv))
783 pr_debug("%s: restart transmit\n", __func__);
784 netif_tx_wake_queue(dev_txq);
787 __netif_tx_unlock(dev_txq);
792 * @priv: driver private structure
793 * Description: it reclaims resources after transmission completes.
795 static void sxgbe_tx_all_clean(struct sxgbe_priv_data * const priv)
799 SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
800 struct sxgbe_tx_queue *tqueue = priv->txq[queue_num];
802 sxgbe_tx_queue_clean(tqueue);
805 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
806 sxgbe_enable_eee_mode(priv);
807 mod_timer(&priv->eee_ctrl_timer, SXGBE_LPI_TIMER(eee_timer));
812 * sxgbe_restart_tx_queue: irq tx error mng function
813 * @priv: driver private structure
814 * Description: it cleans the descriptors and restarts the transmission
817 static void sxgbe_restart_tx_queue(struct sxgbe_priv_data *priv, int queue_num)
819 struct sxgbe_tx_queue *tx_ring = priv->txq[queue_num];
820 struct netdev_queue *dev_txq = netdev_get_tx_queue(priv->dev,
824 netif_tx_stop_queue(dev_txq);
826 /* stop the tx dma */
827 priv->hw->dma->stop_tx_queue(priv->ioaddr, queue_num);
829 /* free the skbuffs of the ring */
830 tx_free_ring_skbufs(tx_ring);
832 /* initialise counters */
834 tx_ring->dirty_tx = 0;
836 /* start the tx dma */
837 priv->hw->dma->start_tx_queue(priv->ioaddr, queue_num);
839 priv->dev->stats.tx_errors++;
841 /* wakeup the queue */
842 netif_tx_wake_queue(dev_txq);
846 * sxgbe_reset_all_tx_queues: irq tx error mng function
847 * @priv: driver private structure
848 * Description: it cleans all the descriptors and
849 * restarts the transmission on all queues in case of errors.
851 static void sxgbe_reset_all_tx_queues(struct sxgbe_priv_data *priv)
855 /* On TX timeout of net device, resetting of all queues
856 * may not be proper way, revisit this later if needed
858 SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num)
859 sxgbe_restart_tx_queue(priv, queue_num);
863 * sxgbe_get_hw_features: get XMAC capabilities from the HW cap. register.
864 * @priv: driver private structure
866 * new GMAC chip generations have a new register to indicate the
867 * presence of the optional feature/functions.
868 * This can be also used to override the value passed through the
869 * platform and necessary for old MAC10/100 and GMAC chips.
871 static int sxgbe_get_hw_features(struct sxgbe_priv_data * const priv)
874 struct sxgbe_hw_features *features = &priv->hw_cap;
876 /* Read First Capability Register CAP[0] */
877 rval = priv->hw->mac->get_hw_feature(priv->ioaddr, 0);
879 features->pmt_remote_wake_up =
880 SXGBE_HW_FEAT_PMT_TEMOTE_WOP(rval);
881 features->pmt_magic_frame = SXGBE_HW_FEAT_PMT_MAGIC_PKT(rval);
882 features->atime_stamp = SXGBE_HW_FEAT_IEEE1500_2008(rval);
883 features->tx_csum_offload =
884 SXGBE_HW_FEAT_TX_CSUM_OFFLOAD(rval);
885 features->rx_csum_offload =
886 SXGBE_HW_FEAT_RX_CSUM_OFFLOAD(rval);
887 features->multi_macaddr = SXGBE_HW_FEAT_MACADDR_COUNT(rval);
888 features->tstamp_srcselect = SXGBE_HW_FEAT_TSTMAP_SRC(rval);
889 features->sa_vlan_insert = SXGBE_HW_FEAT_SRCADDR_VLAN(rval);
890 features->eee = SXGBE_HW_FEAT_EEE(rval);
893 /* Read First Capability Register CAP[1] */
894 rval = priv->hw->mac->get_hw_feature(priv->ioaddr, 1);
896 features->rxfifo_size = SXGBE_HW_FEAT_RX_FIFO_SIZE(rval);
897 features->txfifo_size = SXGBE_HW_FEAT_TX_FIFO_SIZE(rval);
898 features->atstmap_hword = SXGBE_HW_FEAT_TX_FIFO_SIZE(rval);
899 features->dcb_enable = SXGBE_HW_FEAT_DCB(rval);
900 features->splithead_enable = SXGBE_HW_FEAT_SPLIT_HDR(rval);
901 features->tcpseg_offload = SXGBE_HW_FEAT_TSO(rval);
902 features->debug_mem = SXGBE_HW_FEAT_DEBUG_MEM_IFACE(rval);
903 features->rss_enable = SXGBE_HW_FEAT_RSS(rval);
904 features->hash_tsize = SXGBE_HW_FEAT_HASH_TABLE_SIZE(rval);
905 features->l3l4_filer_size = SXGBE_HW_FEAT_L3L4_FILTER_NUM(rval);
908 /* Read First Capability Register CAP[2] */
909 rval = priv->hw->mac->get_hw_feature(priv->ioaddr, 2);
911 features->rx_mtl_queues = SXGBE_HW_FEAT_RX_MTL_QUEUES(rval);
912 features->tx_mtl_queues = SXGBE_HW_FEAT_TX_MTL_QUEUES(rval);
913 features->rx_dma_channels = SXGBE_HW_FEAT_RX_DMA_CHANNELS(rval);
914 features->tx_dma_channels = SXGBE_HW_FEAT_TX_DMA_CHANNELS(rval);
915 features->pps_output_count = SXGBE_HW_FEAT_PPS_OUTPUTS(rval);
916 features->aux_input_count = SXGBE_HW_FEAT_AUX_SNAPSHOTS(rval);
923 * sxgbe_check_ether_addr: check if the MAC addr is valid
924 * @priv: driver private structure
926 * it is to verify if the MAC address is valid, in case of failures it
927 * generates a random MAC address
929 static void sxgbe_check_ether_addr(struct sxgbe_priv_data *priv)
931 if (!is_valid_ether_addr(priv->dev->dev_addr)) {
932 priv->hw->mac->get_umac_addr((void __iomem *)
934 priv->dev->dev_addr, 0);
935 if (!is_valid_ether_addr(priv->dev->dev_addr))
936 eth_hw_addr_random(priv->dev);
938 dev_info(priv->device, "device MAC address %pM\n",
939 priv->dev->dev_addr);
943 * sxgbe_init_dma_engine: DMA init.
944 * @priv: driver private structure
946 * It inits the DMA invoking the specific SXGBE callback.
947 * Some DMA parameters can be passed from the platform;
948 * in case of these are not passed a default is kept for the MAC or GMAC.
950 static int sxgbe_init_dma_engine(struct sxgbe_priv_data *priv)
952 int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_map = 0;
955 if (priv->plat->dma_cfg) {
956 pbl = priv->plat->dma_cfg->pbl;
957 fixed_burst = priv->plat->dma_cfg->fixed_burst;
958 burst_map = priv->plat->dma_cfg->burst_map;
961 SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num)
962 priv->hw->dma->cha_init(priv->ioaddr, queue_num,
964 (priv->txq[queue_num])->dma_tx_phy,
965 (priv->rxq[queue_num])->dma_rx_phy,
966 priv->dma_tx_size, priv->dma_rx_size);
968 return priv->hw->dma->init(priv->ioaddr, fixed_burst, burst_map);
972 * sxgbe_init_mtl_engine: MTL init.
973 * @priv: driver private structure
975 * It inits the MTL invoking the specific SXGBE callback.
977 static void sxgbe_init_mtl_engine(struct sxgbe_priv_data *priv)
981 SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
982 priv->hw->mtl->mtl_set_txfifosize(priv->ioaddr, queue_num,
983 priv->hw_cap.tx_mtl_qsize);
984 priv->hw->mtl->mtl_enable_txqueue(priv->ioaddr, queue_num);
989 * sxgbe_disable_mtl_engine: MTL disable.
990 * @priv: driver private structure
992 * It disables the MTL queues by invoking the specific SXGBE callback.
994 static void sxgbe_disable_mtl_engine(struct sxgbe_priv_data *priv)
998 SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num)
999 priv->hw->mtl->mtl_disable_txqueue(priv->ioaddr, queue_num);
1004 * sxgbe_tx_timer: mitigation sw timer for tx.
1005 * @data: data pointer
1007 * This is the timer handler to directly invoke the sxgbe_tx_clean.
1009 static void sxgbe_tx_timer(unsigned long data)
1011 struct sxgbe_tx_queue *p = (struct sxgbe_tx_queue *)data;
1012 sxgbe_tx_queue_clean(p);
1016 * sxgbe_init_tx_coalesce: init tx mitigation options.
1017 * @priv: driver private structure
1019 * This inits the transmit coalesce parameters: i.e. timer rate,
1020 * timer handler and default threshold used for enabling the
1021 * interrupt on completion bit.
1023 static void sxgbe_tx_init_coalesce(struct sxgbe_priv_data *priv)
1027 SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
1028 struct sxgbe_tx_queue *p = priv->txq[queue_num];
1029 p->tx_coal_frames = SXGBE_TX_FRAMES;
1030 p->tx_coal_timer = SXGBE_COAL_TX_TIMER;
1031 setup_timer(&p->txtimer, sxgbe_tx_timer,
1032 (unsigned long)&priv->txq[queue_num]);
1033 p->txtimer.expires = SXGBE_COAL_TIMER(p->tx_coal_timer);
1034 add_timer(&p->txtimer);
1038 static void sxgbe_tx_del_timer(struct sxgbe_priv_data *priv)
1042 SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
1043 struct sxgbe_tx_queue *p = priv->txq[queue_num];
1044 del_timer_sync(&p->txtimer);
1049 * sxgbe_open - open entry point of the driver
1050 * @dev : pointer to the device structure.
1052 * This function is the open entry point of the driver.
1054 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1057 static int sxgbe_open(struct net_device *dev)
1059 struct sxgbe_priv_data *priv = netdev_priv(dev);
1062 clk_prepare_enable(priv->sxgbe_clk);
1064 sxgbe_check_ether_addr(priv);
1067 ret = sxgbe_init_phy(dev);
1069 netdev_err(dev, "%s: Cannot attach to PHY (error: %d)\n",
1074 /* Create and initialize the TX/RX descriptors chains. */
1075 priv->dma_tx_size = SXGBE_ALIGN(DMA_TX_SIZE);
1076 priv->dma_rx_size = SXGBE_ALIGN(DMA_RX_SIZE);
1077 priv->dma_buf_sz = SXGBE_ALIGN(DMA_BUFFER_SIZE);
1078 priv->tx_tc = TC_DEFAULT;
1079 priv->rx_tc = TC_DEFAULT;
1080 init_dma_desc_rings(dev);
1082 /* DMA initialization and SW reset */
1083 ret = sxgbe_init_dma_engine(priv);
1085 netdev_err(dev, "%s: DMA initialization failed\n", __func__);
1089 /* MTL initialization */
1090 sxgbe_init_mtl_engine(priv);
1092 /* Copy the MAC addr into the HW */
1093 priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
1095 /* Initialize the MAC Core */
1096 priv->hw->mac->core_init(priv->ioaddr);
1097 SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) {
1098 priv->hw->mac->enable_rxqueue(priv->ioaddr, queue_num);
1101 /* Request the IRQ lines */
1102 ret = devm_request_irq(priv->device, priv->irq, sxgbe_common_interrupt,
1103 IRQF_SHARED, dev->name, dev);
1104 if (unlikely(ret < 0)) {
1105 netdev_err(dev, "%s: ERROR: allocating the IRQ %d (error: %d)\n",
1106 __func__, priv->irq, ret);
1110 /* If the LPI irq is different from the mac irq
1111 * register a dedicated handler
1113 if (priv->lpi_irq != dev->irq) {
1114 ret = devm_request_irq(priv->device, priv->lpi_irq,
1115 sxgbe_common_interrupt,
1116 IRQF_SHARED, dev->name, dev);
1117 if (unlikely(ret < 0)) {
1118 netdev_err(dev, "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1119 __func__, priv->lpi_irq, ret);
1124 /* Request TX DMA irq lines */
1125 SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
1126 ret = devm_request_irq(priv->device,
1127 (priv->txq[queue_num])->irq_no,
1128 sxgbe_tx_interrupt, 0,
1129 dev->name, priv->txq[queue_num]);
1130 if (unlikely(ret < 0)) {
1131 netdev_err(dev, "%s: ERROR: allocating TX IRQ %d (error: %d)\n",
1132 __func__, priv->irq, ret);
1137 /* Request RX DMA irq lines */
1138 SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) {
1139 ret = devm_request_irq(priv->device,
1140 (priv->rxq[queue_num])->irq_no,
1141 sxgbe_rx_interrupt, 0,
1142 dev->name, priv->rxq[queue_num]);
1143 if (unlikely(ret < 0)) {
1144 netdev_err(dev, "%s: ERROR: allocating TX IRQ %d (error: %d)\n",
1145 __func__, priv->irq, ret);
1150 /* Enable the MAC Rx/Tx */
1151 priv->hw->mac->enable_tx(priv->ioaddr, true);
1152 priv->hw->mac->enable_rx(priv->ioaddr, true);
1154 /* Set the HW DMA mode and the COE */
1155 sxgbe_mtl_operation_mode(priv);
1157 /* Extra statistics */
1158 memset(&priv->xstats, 0, sizeof(struct sxgbe_extra_stats));
1160 priv->xstats.tx_threshold = priv->tx_tc;
1161 priv->xstats.rx_threshold = priv->rx_tc;
1163 /* Start the ball rolling... */
1164 netdev_dbg(dev, "DMA RX/TX processes started...\n");
1165 priv->hw->dma->start_tx(priv->ioaddr, SXGBE_TX_QUEUES);
1166 priv->hw->dma->start_rx(priv->ioaddr, SXGBE_RX_QUEUES);
1169 phy_start(dev->phydev);
1171 /* initialise TX coalesce parameters */
1172 sxgbe_tx_init_coalesce(priv);
1174 if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1175 priv->rx_riwt = SXGBE_MAX_DMA_RIWT;
1176 priv->hw->dma->rx_watchdog(priv->ioaddr, SXGBE_MAX_DMA_RIWT);
1179 priv->tx_lpi_timer = SXGBE_DEFAULT_LPI_TIMER;
1180 priv->eee_enabled = sxgbe_eee_init(priv);
1182 napi_enable(&priv->napi);
1183 netif_start_queue(dev);
1188 free_dma_desc_resources(priv);
1190 phy_disconnect(dev->phydev);
1192 clk_disable_unprepare(priv->sxgbe_clk);
1198 * sxgbe_release - close entry point of the driver
1199 * @dev : device pointer.
1201 * This is the stop entry point of the driver.
1203 static int sxgbe_release(struct net_device *dev)
1205 struct sxgbe_priv_data *priv = netdev_priv(dev);
1207 if (priv->eee_enabled)
1208 del_timer_sync(&priv->eee_ctrl_timer);
1210 /* Stop and disconnect the PHY */
1212 phy_stop(dev->phydev);
1213 phy_disconnect(dev->phydev);
1216 netif_tx_stop_all_queues(dev);
1218 napi_disable(&priv->napi);
1220 /* delete TX timers */
1221 sxgbe_tx_del_timer(priv);
1223 /* Stop TX/RX DMA and clear the descriptors */
1224 priv->hw->dma->stop_tx(priv->ioaddr, SXGBE_TX_QUEUES);
1225 priv->hw->dma->stop_rx(priv->ioaddr, SXGBE_RX_QUEUES);
1227 /* disable MTL queue */
1228 sxgbe_disable_mtl_engine(priv);
1230 /* Release and free the Rx/Tx resources */
1231 free_dma_desc_resources(priv);
1233 /* Disable the MAC Rx/Tx */
1234 priv->hw->mac->enable_tx(priv->ioaddr, false);
1235 priv->hw->mac->enable_rx(priv->ioaddr, false);
1237 clk_disable_unprepare(priv->sxgbe_clk);
1241 /* Prepare first Tx descriptor for doing TSO operation */
1242 static void sxgbe_tso_prepare(struct sxgbe_priv_data *priv,
1243 struct sxgbe_tx_norm_desc *first_desc,
1244 struct sk_buff *skb)
1246 unsigned int total_hdr_len, tcp_hdr_len;
1248 /* Write first Tx descriptor with appropriate value */
1249 tcp_hdr_len = tcp_hdrlen(skb);
1250 total_hdr_len = skb_transport_offset(skb) + tcp_hdr_len;
1252 first_desc->tdes01 = dma_map_single(priv->device, skb->data,
1253 total_hdr_len, DMA_TO_DEVICE);
1254 if (dma_mapping_error(priv->device, first_desc->tdes01))
1255 pr_err("%s: TX dma mapping failed!!\n", __func__);
1257 first_desc->tdes23.tx_rd_des23.first_desc = 1;
1258 priv->hw->desc->tx_desc_enable_tse(first_desc, 1, total_hdr_len,
1260 skb->len - total_hdr_len);
1264 * sxgbe_xmit: Tx entry point of the driver
1265 * @skb : the socket buffer
1266 * @dev : device pointer
1267 * Description : this is the tx entry point of the driver.
1268 * It programs the chain or the ring and supports oversized frames
1271 static netdev_tx_t sxgbe_xmit(struct sk_buff *skb, struct net_device *dev)
1273 unsigned int entry, frag_num;
1275 struct netdev_queue *dev_txq;
1276 unsigned txq_index = skb_get_queue_mapping(skb);
1277 struct sxgbe_priv_data *priv = netdev_priv(dev);
1278 unsigned int tx_rsize = priv->dma_tx_size;
1279 struct sxgbe_tx_queue *tqueue = priv->txq[txq_index];
1280 struct sxgbe_tx_norm_desc *tx_desc, *first_desc;
1281 struct sxgbe_tx_ctxt_desc *ctxt_desc = NULL;
1282 int nr_frags = skb_shinfo(skb)->nr_frags;
1283 int no_pagedlen = skb_headlen(skb);
1285 u16 cur_mss = skb_shinfo(skb)->gso_size;
1286 u32 ctxt_desc_req = 0;
1288 /* get the TX queue handle */
1289 dev_txq = netdev_get_tx_queue(dev, txq_index);
1291 if (unlikely(skb_is_gso(skb) && tqueue->prev_mss != cur_mss))
1294 if (unlikely(skb_vlan_tag_present(skb) ||
1295 ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1296 tqueue->hwts_tx_en)))
1299 if (priv->tx_path_in_lpi_mode)
1300 sxgbe_disable_eee_mode(priv);
1302 if (unlikely(sxgbe_tx_avail(tqueue, tx_rsize) < nr_frags + 1)) {
1303 if (!netif_tx_queue_stopped(dev_txq)) {
1304 netif_tx_stop_queue(dev_txq);
1305 netdev_err(dev, "%s: Tx Ring is full when %d queue is awake\n",
1306 __func__, txq_index);
1308 return NETDEV_TX_BUSY;
1311 entry = tqueue->cur_tx % tx_rsize;
1312 tx_desc = tqueue->dma_tx + entry;
1314 first_desc = tx_desc;
1316 ctxt_desc = (struct sxgbe_tx_ctxt_desc *)first_desc;
1318 /* save the skb address */
1319 tqueue->tx_skbuff[entry] = skb;
1322 if (likely(skb_is_gso(skb))) {
1324 if (unlikely(tqueue->prev_mss != cur_mss)) {
1325 priv->hw->desc->tx_ctxt_desc_set_mss(
1326 ctxt_desc, cur_mss);
1327 priv->hw->desc->tx_ctxt_desc_set_tcmssv(
1329 priv->hw->desc->tx_ctxt_desc_reset_ostc(
1331 priv->hw->desc->tx_ctxt_desc_set_ctxt(
1333 priv->hw->desc->tx_ctxt_desc_set_owner(
1336 entry = (++tqueue->cur_tx) % tx_rsize;
1337 first_desc = tqueue->dma_tx + entry;
1339 tqueue->prev_mss = cur_mss;
1341 sxgbe_tso_prepare(priv, first_desc, skb);
1343 tx_desc->tdes01 = dma_map_single(priv->device,
1344 skb->data, no_pagedlen, DMA_TO_DEVICE);
1345 if (dma_mapping_error(priv->device, tx_desc->tdes01))
1346 netdev_err(dev, "%s: TX dma mapping failed!!\n",
1349 priv->hw->desc->prepare_tx_desc(tx_desc, 1, no_pagedlen,
1350 no_pagedlen, cksum_flag);
1354 for (frag_num = 0; frag_num < nr_frags; frag_num++) {
1355 const skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_num];
1356 int len = skb_frag_size(frag);
1358 entry = (++tqueue->cur_tx) % tx_rsize;
1359 tx_desc = tqueue->dma_tx + entry;
1360 tx_desc->tdes01 = skb_frag_dma_map(priv->device, frag, 0, len,
1363 tqueue->tx_skbuff_dma[entry] = tx_desc->tdes01;
1364 tqueue->tx_skbuff[entry] = NULL;
1366 /* prepare the descriptor */
1367 priv->hw->desc->prepare_tx_desc(tx_desc, 0, len,
1369 /* memory barrier to flush descriptor */
1373 priv->hw->desc->set_tx_owner(tx_desc);
1376 /* close the descriptors */
1377 priv->hw->desc->close_tx_desc(tx_desc);
1379 /* memory barrier to flush descriptor */
1382 tqueue->tx_count_frames += nr_frags + 1;
1383 if (tqueue->tx_count_frames > tqueue->tx_coal_frames) {
1384 priv->hw->desc->clear_tx_ic(tx_desc);
1385 priv->xstats.tx_reset_ic_bit++;
1386 mod_timer(&tqueue->txtimer,
1387 SXGBE_COAL_TIMER(tqueue->tx_coal_timer));
1389 tqueue->tx_count_frames = 0;
1392 /* set owner for first desc */
1393 priv->hw->desc->set_tx_owner(first_desc);
1395 /* memory barrier to flush descriptor */
1400 /* display current ring */
1401 netif_dbg(priv, pktdata, dev, "%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d\n",
1402 __func__, tqueue->cur_tx % tx_rsize,
1403 tqueue->dirty_tx % tx_rsize, entry,
1404 first_desc, nr_frags);
1406 if (unlikely(sxgbe_tx_avail(tqueue, tx_rsize) <= (MAX_SKB_FRAGS + 1))) {
1407 netif_dbg(priv, hw, dev, "%s: stop transmitted packets\n",
1409 netif_tx_stop_queue(dev_txq);
1412 dev->stats.tx_bytes += skb->len;
1414 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1415 tqueue->hwts_tx_en)) {
1416 /* declare that device is doing timestamping */
1417 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1418 priv->hw->desc->tx_enable_tstamp(first_desc);
1421 skb_tx_timestamp(skb);
1423 priv->hw->dma->enable_dma_transmission(priv->ioaddr, txq_index);
1425 return NETDEV_TX_OK;
1429 * sxgbe_rx_refill: refill used skb preallocated buffers
1430 * @priv: driver private structure
1431 * Description : this is to reallocate the skb for the reception process
1432 * that is based on zero-copy.
1434 static void sxgbe_rx_refill(struct sxgbe_priv_data *priv)
1436 unsigned int rxsize = priv->dma_rx_size;
1437 int bfsize = priv->dma_buf_sz;
1438 u8 qnum = priv->cur_rx_qnum;
1440 for (; priv->rxq[qnum]->cur_rx - priv->rxq[qnum]->dirty_rx > 0;
1441 priv->rxq[qnum]->dirty_rx++) {
1442 unsigned int entry = priv->rxq[qnum]->dirty_rx % rxsize;
1443 struct sxgbe_rx_norm_desc *p;
1445 p = priv->rxq[qnum]->dma_rx + entry;
1447 if (likely(priv->rxq[qnum]->rx_skbuff[entry] == NULL)) {
1448 struct sk_buff *skb;
1450 skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
1452 if (unlikely(skb == NULL))
1455 priv->rxq[qnum]->rx_skbuff[entry] = skb;
1456 priv->rxq[qnum]->rx_skbuff_dma[entry] =
1457 dma_map_single(priv->device, skb->data, bfsize,
1460 p->rdes23.rx_rd_des23.buf2_addr =
1461 priv->rxq[qnum]->rx_skbuff_dma[entry];
1464 /* Added memory barrier for RX descriptor modification */
1466 priv->hw->desc->set_rx_owner(p);
1467 priv->hw->desc->set_rx_int_on_com(p);
1468 /* Added memory barrier for RX descriptor modification */
1474 * sxgbe_rx: receive the frames from the remote host
1475 * @priv: driver private structure
1476 * @limit: napi bugget.
1477 * Description : this the function called by the napi poll method.
1478 * It gets all the frames inside the ring.
1480 static int sxgbe_rx(struct sxgbe_priv_data *priv, int limit)
1482 u8 qnum = priv->cur_rx_qnum;
1483 unsigned int rxsize = priv->dma_rx_size;
1484 unsigned int entry = priv->rxq[qnum]->cur_rx;
1485 unsigned int next_entry = 0;
1486 unsigned int count = 0;
1490 while (count < limit) {
1491 struct sxgbe_rx_norm_desc *p;
1492 struct sk_buff *skb;
1495 p = priv->rxq[qnum]->dma_rx + entry;
1497 if (priv->hw->desc->get_rx_owner(p))
1502 next_entry = (++priv->rxq[qnum]->cur_rx) % rxsize;
1503 prefetch(priv->rxq[qnum]->dma_rx + next_entry);
1505 /* Read the status of the incoming frame and also get checksum
1506 * value based on whether it is enabled in SXGBE hardware or
1509 status = priv->hw->desc->rx_wbstatus(p, &priv->xstats,
1511 if (unlikely(status < 0)) {
1515 if (unlikely(!priv->rxcsum_insertion))
1516 checksum = CHECKSUM_NONE;
1518 skb = priv->rxq[qnum]->rx_skbuff[entry];
1521 netdev_err(priv->dev, "rx descriptor is not consistent\n");
1523 prefetch(skb->data - NET_IP_ALIGN);
1524 priv->rxq[qnum]->rx_skbuff[entry] = NULL;
1526 frame_len = priv->hw->desc->get_rx_frame_len(p);
1528 skb_put(skb, frame_len);
1530 skb->ip_summed = checksum;
1531 if (checksum == CHECKSUM_NONE)
1532 netif_receive_skb(skb);
1534 napi_gro_receive(&priv->napi, skb);
1539 sxgbe_rx_refill(priv);
1545 * sxgbe_poll - sxgbe poll method (NAPI)
1546 * @napi : pointer to the napi structure.
1547 * @budget : maximum number of packets that the current CPU can receive from
1550 * To look at the incoming frames and clear the tx resources.
1552 static int sxgbe_poll(struct napi_struct *napi, int budget)
1554 struct sxgbe_priv_data *priv = container_of(napi,
1555 struct sxgbe_priv_data, napi);
1557 u8 qnum = priv->cur_rx_qnum;
1559 priv->xstats.napi_poll++;
1560 /* first, clean the tx queues */
1561 sxgbe_tx_all_clean(priv);
1563 work_done = sxgbe_rx(priv, budget);
1564 if (work_done < budget) {
1565 napi_complete_done(napi, work_done);
1566 priv->hw->dma->enable_dma_irq(priv->ioaddr, qnum);
1574 * @dev : Pointer to net device structure
1575 * Description: this function is called when a packet transmission fails to
1576 * complete within a reasonable time. The driver will mark the error in the
1577 * netdev structure and arrange for the device to be reset to a sane state
1578 * in order to transmit a new packet.
1580 static void sxgbe_tx_timeout(struct net_device *dev)
1582 struct sxgbe_priv_data *priv = netdev_priv(dev);
1584 sxgbe_reset_all_tx_queues(priv);
1588 * sxgbe_common_interrupt - main ISR
1589 * @irq: interrupt number.
1590 * @dev_id: to pass the net device pointer.
1591 * Description: this is the main driver interrupt service routine.
1592 * It calls the DMA ISR and also the core ISR to manage PMT, MMC, LPI
1595 static irqreturn_t sxgbe_common_interrupt(int irq, void *dev_id)
1597 struct net_device *netdev = (struct net_device *)dev_id;
1598 struct sxgbe_priv_data *priv = netdev_priv(netdev);
1601 status = priv->hw->mac->host_irq_status(priv->ioaddr, &priv->xstats);
1602 /* For LPI we need to save the tx status */
1603 if (status & TX_ENTRY_LPI_MODE) {
1604 priv->xstats.tx_lpi_entry_n++;
1605 priv->tx_path_in_lpi_mode = true;
1607 if (status & TX_EXIT_LPI_MODE) {
1608 priv->xstats.tx_lpi_exit_n++;
1609 priv->tx_path_in_lpi_mode = false;
1611 if (status & RX_ENTRY_LPI_MODE)
1612 priv->xstats.rx_lpi_entry_n++;
1613 if (status & RX_EXIT_LPI_MODE)
1614 priv->xstats.rx_lpi_exit_n++;
1620 * sxgbe_tx_interrupt - TX DMA ISR
1621 * @irq: interrupt number.
1622 * @dev_id: to pass the net device pointer.
1623 * Description: this is the tx dma interrupt service routine.
1625 static irqreturn_t sxgbe_tx_interrupt(int irq, void *dev_id)
1628 struct sxgbe_tx_queue *txq = (struct sxgbe_tx_queue *)dev_id;
1629 struct sxgbe_priv_data *priv = txq->priv_ptr;
1631 /* get the channel status */
1632 status = priv->hw->dma->tx_dma_int_status(priv->ioaddr, txq->queue_no,
1634 /* check for normal path */
1635 if (likely((status & handle_tx)))
1636 napi_schedule(&priv->napi);
1638 /* check for unrecoverable error */
1639 if (unlikely((status & tx_hard_error)))
1640 sxgbe_restart_tx_queue(priv, txq->queue_no);
1642 /* check for TC configuration change */
1643 if (unlikely((status & tx_bump_tc) &&
1644 (priv->tx_tc != SXGBE_MTL_SFMODE) &&
1645 (priv->tx_tc < 512))) {
1646 /* step of TX TC is 32 till 128, otherwise 64 */
1647 priv->tx_tc += (priv->tx_tc < 128) ? 32 : 64;
1648 priv->hw->mtl->set_tx_mtl_mode(priv->ioaddr,
1649 txq->queue_no, priv->tx_tc);
1650 priv->xstats.tx_threshold = priv->tx_tc;
1657 * sxgbe_rx_interrupt - RX DMA ISR
1658 * @irq: interrupt number.
1659 * @dev_id: to pass the net device pointer.
1660 * Description: this is the rx dma interrupt service routine.
1662 static irqreturn_t sxgbe_rx_interrupt(int irq, void *dev_id)
1665 struct sxgbe_rx_queue *rxq = (struct sxgbe_rx_queue *)dev_id;
1666 struct sxgbe_priv_data *priv = rxq->priv_ptr;
1668 /* get the channel status */
1669 status = priv->hw->dma->rx_dma_int_status(priv->ioaddr, rxq->queue_no,
1672 if (likely((status & handle_rx) && (napi_schedule_prep(&priv->napi)))) {
1673 priv->hw->dma->disable_dma_irq(priv->ioaddr, rxq->queue_no);
1674 __napi_schedule(&priv->napi);
1677 /* check for TC configuration change */
1678 if (unlikely((status & rx_bump_tc) &&
1679 (priv->rx_tc != SXGBE_MTL_SFMODE) &&
1680 (priv->rx_tc < 128))) {
1681 /* step of TC is 32 */
1683 priv->hw->mtl->set_rx_mtl_mode(priv->ioaddr,
1684 rxq->queue_no, priv->rx_tc);
1685 priv->xstats.rx_threshold = priv->rx_tc;
1691 static inline u64 sxgbe_get_stat64(void __iomem *ioaddr, int reg_lo, int reg_hi)
1693 u64 val = readl(ioaddr + reg_lo);
1695 val |= ((u64)readl(ioaddr + reg_hi)) << 32;
1701 /* sxgbe_get_stats64 - entry point to see statistical information of device
1702 * @dev : device pointer.
1703 * @stats : pointer to hold all the statistical information of device.
1705 * This function is a driver entry point whenever ifconfig command gets
1706 * executed to see device statistics. Statistics are number of
1707 * bytes sent or received, errors occurred etc.
1709 static void sxgbe_get_stats64(struct net_device *dev,
1710 struct rtnl_link_stats64 *stats)
1712 struct sxgbe_priv_data *priv = netdev_priv(dev);
1713 void __iomem *ioaddr = priv->ioaddr;
1716 spin_lock(&priv->stats_lock);
1717 /* Freeze the counter registers before reading value otherwise it may
1718 * get updated by hardware while we are reading them
1720 writel(SXGBE_MMC_CTRL_CNT_FRZ, ioaddr + SXGBE_MMC_CTL_REG);
1722 stats->rx_bytes = sxgbe_get_stat64(ioaddr,
1723 SXGBE_MMC_RXOCTETLO_GCNT_REG,
1724 SXGBE_MMC_RXOCTETHI_GCNT_REG);
1726 stats->rx_packets = sxgbe_get_stat64(ioaddr,
1727 SXGBE_MMC_RXFRAMELO_GBCNT_REG,
1728 SXGBE_MMC_RXFRAMEHI_GBCNT_REG);
1730 stats->multicast = sxgbe_get_stat64(ioaddr,
1731 SXGBE_MMC_RXMULTILO_GCNT_REG,
1732 SXGBE_MMC_RXMULTIHI_GCNT_REG);
1734 stats->rx_crc_errors = sxgbe_get_stat64(ioaddr,
1735 SXGBE_MMC_RXCRCERRLO_REG,
1736 SXGBE_MMC_RXCRCERRHI_REG);
1738 stats->rx_length_errors = sxgbe_get_stat64(ioaddr,
1739 SXGBE_MMC_RXLENERRLO_REG,
1740 SXGBE_MMC_RXLENERRHI_REG);
1742 stats->rx_missed_errors = sxgbe_get_stat64(ioaddr,
1743 SXGBE_MMC_RXFIFOOVERFLOWLO_GBCNT_REG,
1744 SXGBE_MMC_RXFIFOOVERFLOWHI_GBCNT_REG);
1746 stats->tx_bytes = sxgbe_get_stat64(ioaddr,
1747 SXGBE_MMC_TXOCTETLO_GCNT_REG,
1748 SXGBE_MMC_TXOCTETHI_GCNT_REG);
1750 count = sxgbe_get_stat64(ioaddr, SXGBE_MMC_TXFRAMELO_GBCNT_REG,
1751 SXGBE_MMC_TXFRAMEHI_GBCNT_REG);
1753 stats->tx_errors = sxgbe_get_stat64(ioaddr, SXGBE_MMC_TXFRAMELO_GCNT_REG,
1754 SXGBE_MMC_TXFRAMEHI_GCNT_REG);
1755 stats->tx_errors = count - stats->tx_errors;
1756 stats->tx_packets = count;
1757 stats->tx_fifo_errors = sxgbe_get_stat64(ioaddr, SXGBE_MMC_TXUFLWLO_GBCNT_REG,
1758 SXGBE_MMC_TXUFLWHI_GBCNT_REG);
1759 writel(0, ioaddr + SXGBE_MMC_CTL_REG);
1760 spin_unlock(&priv->stats_lock);
1763 /* sxgbe_set_features - entry point to set offload features of the device.
1764 * @dev : device pointer.
1765 * @features : features which are required to be set.
1767 * This function is a driver entry point and called by Linux kernel whenever
1768 * any device features are set or reset by user.
1770 * This function returns 0 after setting or resetting device features.
1772 static int sxgbe_set_features(struct net_device *dev,
1773 netdev_features_t features)
1775 struct sxgbe_priv_data *priv = netdev_priv(dev);
1776 netdev_features_t changed = dev->features ^ features;
1778 if (changed & NETIF_F_RXCSUM) {
1779 if (features & NETIF_F_RXCSUM) {
1780 priv->hw->mac->enable_rx_csum(priv->ioaddr);
1781 priv->rxcsum_insertion = true;
1783 priv->hw->mac->disable_rx_csum(priv->ioaddr);
1784 priv->rxcsum_insertion = false;
1791 /* sxgbe_change_mtu - entry point to change MTU size for the device.
1792 * @dev : device pointer.
1793 * @new_mtu : the new MTU size for the device.
1794 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
1795 * to drive packet transmission. Ethernet has an MTU of 1500 octets
1796 * (ETH_DATA_LEN). This value can be changed with ifconfig.
1798 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1801 static int sxgbe_change_mtu(struct net_device *dev, int new_mtu)
1805 if (!netif_running(dev))
1808 /* Recevice ring buffer size is needed to be set based on MTU. If MTU is
1809 * changed then reinitilisation of the receive ring buffers need to be
1810 * done. Hence bring interface down and bring interface back up
1813 return sxgbe_open(dev);
1816 static void sxgbe_set_umac_addr(void __iomem *ioaddr, unsigned char *addr,
1821 data = (addr[5] << 8) | addr[4];
1822 /* For MAC Addr registers se have to set the Address Enable (AE)
1823 * bit that has no effect on the High Reg 0 where the bit 31 (MO)
1826 writel(data | SXGBE_HI_REG_AE, ioaddr + SXGBE_ADDR_HIGH(reg_n));
1827 data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
1828 writel(data, ioaddr + SXGBE_ADDR_LOW(reg_n));
1832 * sxgbe_set_rx_mode - entry point for setting different receive mode of
1833 * a device. unicast, multicast addressing
1834 * @dev : pointer to the device structure
1836 * This function is a driver entry point which gets called by the kernel
1837 * whenever different receive mode like unicast, multicast and promiscuous
1838 * must be enabled/disabled.
1842 static void sxgbe_set_rx_mode(struct net_device *dev)
1844 struct sxgbe_priv_data *priv = netdev_priv(dev);
1845 void __iomem *ioaddr = (void __iomem *)priv->ioaddr;
1846 unsigned int value = 0;
1848 struct netdev_hw_addr *ha;
1851 netdev_dbg(dev, "%s: # mcasts %d, # unicast %d\n",
1852 __func__, netdev_mc_count(dev), netdev_uc_count(dev));
1854 if (dev->flags & IFF_PROMISC) {
1855 value = SXGBE_FRAME_FILTER_PR;
1857 } else if ((netdev_mc_count(dev) > SXGBE_HASH_TABLE_SIZE) ||
1858 (dev->flags & IFF_ALLMULTI)) {
1859 value = SXGBE_FRAME_FILTER_PM; /* pass all multi */
1860 writel(0xffffffff, ioaddr + SXGBE_HASH_HIGH);
1861 writel(0xffffffff, ioaddr + SXGBE_HASH_LOW);
1863 } else if (!netdev_mc_empty(dev)) {
1864 /* Hash filter for multicast */
1865 value = SXGBE_FRAME_FILTER_HMC;
1867 memset(mc_filter, 0, sizeof(mc_filter));
1868 netdev_for_each_mc_addr(ha, dev) {
1869 /* The upper 6 bits of the calculated CRC are used to
1870 * index the contens of the hash table
1872 int bit_nr = bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26;
1874 /* The most significant bit determines the register to
1875 * use (H/L) while the other 5 bits determine the bit
1876 * within the register.
1878 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1880 writel(mc_filter[0], ioaddr + SXGBE_HASH_LOW);
1881 writel(mc_filter[1], ioaddr + SXGBE_HASH_HIGH);
1884 /* Handle multiple unicast addresses (perfect filtering) */
1885 if (netdev_uc_count(dev) > SXGBE_MAX_PERFECT_ADDRESSES)
1886 /* Switch to promiscuous mode if more than 16 addrs
1889 value |= SXGBE_FRAME_FILTER_PR;
1891 netdev_for_each_uc_addr(ha, dev) {
1892 sxgbe_set_umac_addr(ioaddr, ha->addr, reg);
1896 #ifdef FRAME_FILTER_DEBUG
1897 /* Enable Receive all mode (to debug filtering_fail errors) */
1898 value |= SXGBE_FRAME_FILTER_RA;
1900 writel(value, ioaddr + SXGBE_FRAME_FILTER);
1902 netdev_dbg(dev, "Filter: 0x%08x\n\tHash: HI 0x%08x, LO 0x%08x\n",
1903 readl(ioaddr + SXGBE_FRAME_FILTER),
1904 readl(ioaddr + SXGBE_HASH_HIGH),
1905 readl(ioaddr + SXGBE_HASH_LOW));
1908 #ifdef CONFIG_NET_POLL_CONTROLLER
1910 * sxgbe_poll_controller - entry point for polling receive by device
1911 * @dev : pointer to the device structure
1913 * This function is used by NETCONSOLE and other diagnostic tools
1914 * to allow network I/O with interrupts disabled.
1918 static void sxgbe_poll_controller(struct net_device *dev)
1920 struct sxgbe_priv_data *priv = netdev_priv(dev);
1922 disable_irq(priv->irq);
1923 sxgbe_rx_interrupt(priv->irq, dev);
1924 enable_irq(priv->irq);
1928 /* sxgbe_ioctl - Entry point for the Ioctl
1929 * @dev: Device pointer.
1930 * @rq: An IOCTL specefic structure, that can contain a pointer to
1931 * a proprietary structure used to pass information to the driver.
1932 * @cmd: IOCTL command
1934 * Currently it supports the phy_mii_ioctl(...) and HW time stamping.
1936 static int sxgbe_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1938 int ret = -EOPNOTSUPP;
1940 if (!netif_running(dev))
1949 ret = phy_mii_ioctl(dev->phydev, rq, cmd);
1958 static const struct net_device_ops sxgbe_netdev_ops = {
1959 .ndo_open = sxgbe_open,
1960 .ndo_start_xmit = sxgbe_xmit,
1961 .ndo_stop = sxgbe_release,
1962 .ndo_get_stats64 = sxgbe_get_stats64,
1963 .ndo_change_mtu = sxgbe_change_mtu,
1964 .ndo_set_features = sxgbe_set_features,
1965 .ndo_set_rx_mode = sxgbe_set_rx_mode,
1966 .ndo_tx_timeout = sxgbe_tx_timeout,
1967 .ndo_do_ioctl = sxgbe_ioctl,
1968 #ifdef CONFIG_NET_POLL_CONTROLLER
1969 .ndo_poll_controller = sxgbe_poll_controller,
1971 .ndo_set_mac_address = eth_mac_addr,
1974 /* Get the hardware ops */
1975 static void sxgbe_get_ops(struct sxgbe_ops * const ops_ptr)
1977 ops_ptr->mac = sxgbe_get_core_ops();
1978 ops_ptr->desc = sxgbe_get_desc_ops();
1979 ops_ptr->dma = sxgbe_get_dma_ops();
1980 ops_ptr->mtl = sxgbe_get_mtl_ops();
1982 /* set the MDIO communication Address/Data regisers */
1983 ops_ptr->mii.addr = SXGBE_MDIO_SCMD_ADD_REG;
1984 ops_ptr->mii.data = SXGBE_MDIO_SCMD_DATA_REG;
1986 /* Assigning the default link settings
1987 * no SXGBE defined default values to be set in registers,
1988 * so assigning as 0 for port and duplex
1990 ops_ptr->link.port = 0;
1991 ops_ptr->link.duplex = 0;
1992 ops_ptr->link.speed = SXGBE_SPEED_10G;
1996 * sxgbe_hw_init - Init the GMAC device
1997 * @priv: driver private structure
1998 * Description: this function checks the HW capability
1999 * (if supported) and sets the driver's features.
2001 static int sxgbe_hw_init(struct sxgbe_priv_data * const priv)
2005 priv->hw = kmalloc(sizeof(*priv->hw), GFP_KERNEL);
2009 /* get the hardware ops */
2010 sxgbe_get_ops(priv->hw);
2012 /* get the controller id */
2013 ctrl_ids = priv->hw->mac->get_controller_version(priv->ioaddr);
2014 priv->hw->ctrl_uid = (ctrl_ids & 0x00ff0000) >> 16;
2015 priv->hw->ctrl_id = (ctrl_ids & 0x000000ff);
2016 pr_info("user ID: 0x%x, Controller ID: 0x%x\n",
2017 priv->hw->ctrl_uid, priv->hw->ctrl_id);
2019 /* get the H/W features */
2020 if (!sxgbe_get_hw_features(priv))
2021 pr_info("Hardware features not found\n");
2023 if (priv->hw_cap.tx_csum_offload)
2024 pr_info("TX Checksum offload supported\n");
2026 if (priv->hw_cap.rx_csum_offload)
2027 pr_info("RX Checksum offload supported\n");
2032 static int sxgbe_sw_reset(void __iomem *addr)
2034 int retry_count = 10;
2036 writel(SXGBE_DMA_SOFT_RESET, addr + SXGBE_DMA_MODE_REG);
2037 while (retry_count--) {
2038 if (!(readl(addr + SXGBE_DMA_MODE_REG) &
2039 SXGBE_DMA_SOFT_RESET))
2044 if (retry_count < 0)
2052 * @device: device pointer
2053 * @plat_dat: platform data pointer
2054 * @addr: iobase memory address
2055 * Description: this is the main probe function used to
2056 * call the alloc_etherdev, allocate the priv structure.
2058 struct sxgbe_priv_data *sxgbe_drv_probe(struct device *device,
2059 struct sxgbe_plat_data *plat_dat,
2062 struct sxgbe_priv_data *priv;
2063 struct net_device *ndev;
2067 ndev = alloc_etherdev_mqs(sizeof(struct sxgbe_priv_data),
2068 SXGBE_TX_QUEUES, SXGBE_RX_QUEUES);
2072 SET_NETDEV_DEV(ndev, device);
2074 priv = netdev_priv(ndev);
2075 priv->device = device;
2078 sxgbe_set_ethtool_ops(ndev);
2079 priv->plat = plat_dat;
2080 priv->ioaddr = addr;
2082 ret = sxgbe_sw_reset(priv->ioaddr);
2084 goto error_free_netdev;
2086 /* Verify driver arguments */
2087 sxgbe_verify_args();
2089 /* Init MAC and get the capabilities */
2090 ret = sxgbe_hw_init(priv);
2092 goto error_free_netdev;
2094 /* allocate memory resources for Descriptor rings */
2095 ret = txring_mem_alloc(priv);
2099 ret = rxring_mem_alloc(priv);
2103 ndev->netdev_ops = &sxgbe_netdev_ops;
2105 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2106 NETIF_F_RXCSUM | NETIF_F_TSO | NETIF_F_TSO6 |
2108 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
2109 ndev->watchdog_timeo = msecs_to_jiffies(TX_TIMEO);
2111 /* assign filtering support */
2112 ndev->priv_flags |= IFF_UNICAST_FLT;
2114 /* MTU range: 68 - 9000 */
2115 ndev->min_mtu = MIN_MTU;
2116 ndev->max_mtu = MAX_MTU;
2118 priv->msg_enable = netif_msg_init(debug, default_msg_level);
2120 /* Enable TCP segmentation offload for all DMA channels */
2121 if (priv->hw_cap.tcpseg_offload) {
2122 SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
2123 priv->hw->dma->enable_tso(priv->ioaddr, queue_num);
2127 /* Enable Rx checksum offload */
2128 if (priv->hw_cap.rx_csum_offload) {
2129 priv->hw->mac->enable_rx_csum(priv->ioaddr);
2130 priv->rxcsum_insertion = true;
2133 /* Initialise pause frame settings */
2137 /* Rx Watchdog is available, enable depend on platform data */
2138 if (!priv->plat->riwt_off) {
2140 pr_info("Enable RX Mitigation via HW Watchdog Timer\n");
2143 netif_napi_add(ndev, &priv->napi, sxgbe_poll, 64);
2145 spin_lock_init(&priv->stats_lock);
2147 priv->sxgbe_clk = clk_get(priv->device, SXGBE_RESOURCE_NAME);
2148 if (IS_ERR(priv->sxgbe_clk)) {
2149 netdev_warn(ndev, "%s: warning: cannot get CSR clock\n",
2151 goto error_napi_del;
2154 /* If a specific clk_csr value is passed from the platform
2155 * this means that the CSR Clock Range selection cannot be
2156 * changed at run-time and it is fixed. Viceversa the driver'll try to
2157 * set the MDC clock dynamically according to the csr actual
2160 if (!priv->plat->clk_csr)
2161 sxgbe_clk_csr_set(priv);
2163 priv->clk_csr = priv->plat->clk_csr;
2165 /* MDIO bus Registration */
2166 ret = sxgbe_mdio_register(ndev);
2168 netdev_dbg(ndev, "%s: MDIO bus (id: %d) registration failed\n",
2169 __func__, priv->plat->bus_id);
2173 ret = register_netdev(ndev);
2175 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
2176 goto error_mdio_unregister;
2179 sxgbe_check_ether_addr(priv);
2183 error_mdio_unregister:
2184 sxgbe_mdio_unregister(ndev);
2186 clk_put(priv->sxgbe_clk);
2188 netif_napi_del(&priv->napi);
2199 * @ndev: net device pointer
2200 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
2201 * changes the link status, releases the DMA descriptor rings.
2203 int sxgbe_drv_remove(struct net_device *ndev)
2205 struct sxgbe_priv_data *priv = netdev_priv(ndev);
2208 netdev_info(ndev, "%s: removing driver\n", __func__);
2210 SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) {
2211 priv->hw->mac->disable_rxqueue(priv->ioaddr, queue_num);
2214 priv->hw->dma->stop_rx(priv->ioaddr, SXGBE_RX_QUEUES);
2215 priv->hw->dma->stop_tx(priv->ioaddr, SXGBE_TX_QUEUES);
2217 priv->hw->mac->enable_tx(priv->ioaddr, false);
2218 priv->hw->mac->enable_rx(priv->ioaddr, false);
2220 unregister_netdev(ndev);
2222 sxgbe_mdio_unregister(ndev);
2224 clk_put(priv->sxgbe_clk);
2226 netif_napi_del(&priv->napi);
2236 int sxgbe_suspend(struct net_device *ndev)
2241 int sxgbe_resume(struct net_device *ndev)
2246 int sxgbe_freeze(struct net_device *ndev)
2251 int sxgbe_restore(struct net_device *ndev)
2255 #endif /* CONFIG_PM */
2257 /* Driver is configured as Platform driver */
2258 static int __init sxgbe_init(void)
2262 ret = sxgbe_register_platform();
2267 pr_err("driver registration failed\n");
2271 static void __exit sxgbe_exit(void)
2273 sxgbe_unregister_platform();
2276 module_init(sxgbe_init);
2277 module_exit(sxgbe_exit);
2280 static int __init sxgbe_cmdline_opt(char *str)
2286 while ((opt = strsep(&str, ",")) != NULL) {
2287 if (!strncmp(opt, "eee_timer:", 6)) {
2288 if (kstrtoint(opt + 10, 0, &eee_timer))
2295 pr_err("%s: ERROR broken module parameter conversion\n", __func__);
2299 __setup("sxgbeeth=", sxgbe_cmdline_opt);
2304 MODULE_DESCRIPTION("SAMSUNG 10G/2.5G/1G Ethernet PLATFORM driver");
2306 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
2307 MODULE_PARM_DESC(eee_timer, "EEE-LPI Default LS timer value");
2309 MODULE_AUTHOR("Siva Reddy Kallam <siva.kallam@samsung.com>");
2310 MODULE_AUTHOR("ByungHo An <bh74.an@samsung.com>");
2311 MODULE_AUTHOR("Girish K S <ks.giri@samsung.com>");
2312 MODULE_AUTHOR("Vipul Pandya <vipul.pandya@samsung.com>");
2314 MODULE_LICENSE("GPL");