1 /* 10G controller driver for Samsung SoCs
3 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * Author: Siva Reddy Kallam <siva.kallam@samsung.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 #ifndef __SXGBE_REGMAP_H__
13 #define __SXGBE_REGMAP_H__
15 /* SXGBE MAC Registers */
16 #define SXGBE_CORE_TX_CONFIG_REG 0x0000
17 #define SXGBE_CORE_RX_CONFIG_REG 0x0004
18 #define SXGBE_CORE_PKT_FILTER_REG 0x0008
19 #define SXGBE_CORE_WATCHDOG_TIMEOUT_REG 0x000C
20 #define SXGBE_CORE_HASH_TABLE_REG0 0x0010
21 #define SXGBE_CORE_HASH_TABLE_REG1 0x0014
22 #define SXGBE_CORE_HASH_TABLE_REG2 0x0018
23 #define SXGBE_CORE_HASH_TABLE_REG3 0x001C
24 #define SXGBE_CORE_HASH_TABLE_REG4 0x0020
25 #define SXGBE_CORE_HASH_TABLE_REG5 0x0024
26 #define SXGBE_CORE_HASH_TABLE_REG6 0x0028
27 #define SXGBE_CORE_HASH_TABLE_REG7 0x002C
29 /* EEE-LPI Registers */
30 #define SXGBE_CORE_LPI_CTRL_STATUS 0x00D0
31 #define SXGBE_CORE_LPI_TIMER_CTRL 0x00D4
33 /* VLAN Specific Registers */
34 #define SXGBE_CORE_VLAN_TAG_REG 0x0050
35 #define SXGBE_CORE_VLAN_HASHTAB_REG 0x0058
36 #define SXGBE_CORE_VLAN_INSCTL_REG 0x0060
37 #define SXGBE_CORE_VLAN_INNERCTL_REG 0x0064
38 #define SXGBE_CORE_RX_ETHTYPE_MATCH_REG 0x006C
40 /* Flow Contol Registers */
41 #define SXGBE_CORE_TX_Q0_FLOWCTL_REG 0x0070
42 #define SXGBE_CORE_TX_Q1_FLOWCTL_REG 0x0074
43 #define SXGBE_CORE_TX_Q2_FLOWCTL_REG 0x0078
44 #define SXGBE_CORE_TX_Q3_FLOWCTL_REG 0x007C
45 #define SXGBE_CORE_TX_Q4_FLOWCTL_REG 0x0080
46 #define SXGBE_CORE_TX_Q5_FLOWCTL_REG 0x0084
47 #define SXGBE_CORE_TX_Q6_FLOWCTL_REG 0x0088
48 #define SXGBE_CORE_TX_Q7_FLOWCTL_REG 0x008C
49 #define SXGBE_CORE_RX_FLOWCTL_REG 0x0090
50 #define SXGBE_CORE_RX_CTL0_REG 0x00A0
51 #define SXGBE_CORE_RX_CTL1_REG 0x00A4
52 #define SXGBE_CORE_RX_CTL2_REG 0x00A8
53 #define SXGBE_CORE_RX_CTL3_REG 0x00AC
55 #define SXGBE_CORE_RXQ_ENABLE_MASK 0x0003
56 #define SXGBE_CORE_RXQ_ENABLE 0x0002
57 #define SXGBE_CORE_RXQ_DISABLE 0x0000
59 /* Interrupt Registers */
60 #define SXGBE_CORE_INT_STATUS_REG 0x00B0
61 #define SXGBE_CORE_INT_ENABLE_REG 0x00B4
62 #define SXGBE_CORE_RXTX_ERR_STATUS_REG 0x00B8
63 #define SXGBE_CORE_PMT_CTL_STATUS_REG 0x00C0
64 #define SXGBE_CORE_RWK_PKT_FILTER_REG 0x00C4
65 #define SXGBE_CORE_VERSION_REG 0x0110
66 #define SXGBE_CORE_DEBUG_REG 0x0114
67 #define SXGBE_CORE_HW_FEA_REG(index) (0x011C + index * 4)
69 /* SMA(MDIO) module registers */
70 #define SXGBE_MDIO_SCMD_ADD_REG 0x0200
71 #define SXGBE_MDIO_SCMD_DATA_REG 0x0204
72 #define SXGBE_MDIO_CCMD_WADD_REG 0x0208
73 #define SXGBE_MDIO_CCMD_WDATA_REG 0x020C
74 #define SXGBE_MDIO_CSCAN_PORT_REG 0x0210
75 #define SXGBE_MDIO_INT_STATUS_REG 0x0214
76 #define SXGBE_MDIO_INT_ENABLE_REG 0x0218
77 #define SXGBE_MDIO_PORT_CONDCON_REG 0x021C
78 #define SXGBE_MDIO_CLAUSE22_PORT_REG 0x0220
80 /* port specific, addr = 0-3 */
81 #define SXGBE_MDIO_DEV_BASE_REG 0x0230
82 #define SXGBE_MDIO_PORT_DEV_REG(addr) \
83 (SXGBE_MDIO_DEV_BASE_REG + (0x10 * addr) + 0x0)
84 #define SXGBE_MDIO_PORT_LSTATUS_REG(addr) \
85 (SXGBE_MDIO_DEV_BASE_REG + (0x10 * addr) + 0x4)
86 #define SXGBE_MDIO_PORT_ALIVE_REG(addr) \
87 (SXGBE_MDIO_DEV_BASE_REG + (0x10 * addr) + 0x8)
89 #define SXGBE_CORE_GPIO_CTL_REG 0x0278
90 #define SXGBE_CORE_GPIO_STATUS_REG 0x027C
92 /* Address registers for filtering */
93 #define SXGBE_CORE_ADD_BASE_REG 0x0300
96 #define SXGBE_CORE_ADD_HIGHOFFSET(addr) \
97 (SXGBE_CORE_ADD_BASE_REG + (0x8 * addr) + 0x0)
98 #define SXGBE_CORE_ADD_LOWOFFSET(addr) \
99 (SXGBE_CORE_ADD_BASE_REG + (0x8 * addr) + 0x4)
101 /* SXGBE MMC registers */
102 #define SXGBE_MMC_CTL_REG 0x0800
103 #define SXGBE_MMC_RXINT_STATUS_REG 0x0804
104 #define SXGBE_MMC_TXINT_STATUS_REG 0x0808
105 #define SXGBE_MMC_RXINT_ENABLE_REG 0x080C
106 #define SXGBE_MMC_TXINT_ENABLE_REG 0x0810
108 /* TX specific counters */
109 #define SXGBE_MMC_TXOCTETHI_GBCNT_REG 0x0814
110 #define SXGBE_MMC_TXOCTETLO_GBCNT_REG 0x0818
111 #define SXGBE_MMC_TXFRAMELO_GBCNT_REG 0x081C
112 #define SXGBE_MMC_TXFRAMEHI_GBCNT_REG 0x0820
113 #define SXGBE_MMC_TXBROADLO_GCNT_REG 0x0824
114 #define SXGBE_MMC_TXBROADHI_GCNT_REG 0x0828
115 #define SXGBE_MMC_TXMULTILO_GCNT_REG 0x082C
116 #define SXGBE_MMC_TXMULTIHI_GCNT_REG 0x0830
117 #define SXGBE_MMC_TX64LO_GBCNT_REG 0x0834
118 #define SXGBE_MMC_TX64HI_GBCNT_REG 0x0838
119 #define SXGBE_MMC_TX65TO127LO_GBCNT_REG 0x083C
120 #define SXGBE_MMC_TX65TO127HI_GBCNT_REG 0x0840
121 #define SXGBE_MMC_TX128TO255LO_GBCNT_REG 0x0844
122 #define SXGBE_MMC_TX128TO255HI_GBCNT_REG 0x0848
123 #define SXGBE_MMC_TX256TO511LO_GBCNT_REG 0x084C
124 #define SXGBE_MMC_TX256TO511HI_GBCNT_REG 0x0850
125 #define SXGBE_MMC_TX512TO1023LO_GBCNT_REG 0x0854
126 #define SXGBE_MMC_TX512TO1023HI_GBCNT_REG 0x0858
127 #define SXGBE_MMC_TX1023TOMAXLO_GBCNT_REG 0x085C
128 #define SXGBE_MMC_TX1023TOMAXHI_GBCNT_REG 0x0860
129 #define SXGBE_MMC_TXUNICASTLO_GBCNT_REG 0x0864
130 #define SXGBE_MMC_TXUNICASTHI_GBCNT_REG 0x0868
131 #define SXGBE_MMC_TXMULTILO_GBCNT_REG 0x086C
132 #define SXGBE_MMC_TXMULTIHI_GBCNT_REG 0x0870
133 #define SXGBE_MMC_TXBROADLO_GBCNT_REG 0x0874
134 #define SXGBE_MMC_TXBROADHI_GBCNT_REG 0x0878
135 #define SXGBE_MMC_TXUFLWLO_GBCNT_REG 0x087C
136 #define SXGBE_MMC_TXUFLWHI_GBCNT_REG 0x0880
137 #define SXGBE_MMC_TXOCTETLO_GCNT_REG 0x0884
138 #define SXGBE_MMC_TXOCTETHI_GCNT_REG 0x0888
139 #define SXGBE_MMC_TXFRAMELO_GCNT_REG 0x088C
140 #define SXGBE_MMC_TXFRAMEHI_GCNT_REG 0x0890
141 #define SXGBE_MMC_TXPAUSELO_CNT_REG 0x0894
142 #define SXGBE_MMC_TXPAUSEHI_CNT_REG 0x0898
143 #define SXGBE_MMC_TXVLANLO_GCNT_REG 0x089C
144 #define SXGBE_MMC_TXVLANHI_GCNT_REG 0x08A0
146 /* RX specific counters */
147 #define SXGBE_MMC_RXFRAMELO_GBCNT_REG 0x0900
148 #define SXGBE_MMC_RXFRAMEHI_GBCNT_REG 0x0904
149 #define SXGBE_MMC_RXOCTETLO_GBCNT_REG 0x0908
150 #define SXGBE_MMC_RXOCTETHI_GBCNT_REG 0x090C
151 #define SXGBE_MMC_RXOCTETLO_GCNT_REG 0x0910
152 #define SXGBE_MMC_RXOCTETHI_GCNT_REG 0x0914
153 #define SXGBE_MMC_RXBROADLO_GCNT_REG 0x0918
154 #define SXGBE_MMC_RXBROADHI_GCNT_REG 0x091C
155 #define SXGBE_MMC_RXMULTILO_GCNT_REG 0x0920
156 #define SXGBE_MMC_RXMULTIHI_GCNT_REG 0x0924
157 #define SXGBE_MMC_RXCRCERRLO_REG 0x0928
158 #define SXGBE_MMC_RXCRCERRHI_REG 0x092C
159 #define SXGBE_MMC_RXSHORT64BFRAME_ERR_REG 0x0930
160 #define SXGBE_MMC_RXJABBERERR_REG 0x0934
161 #define SXGBE_MMC_RXSHORT64BFRAME_COR_REG 0x0938
162 #define SXGBE_MMC_RXOVERMAXFRAME_COR_REG 0x093C
163 #define SXGBE_MMC_RX64LO_GBCNT_REG 0x0940
164 #define SXGBE_MMC_RX64HI_GBCNT_REG 0x0944
165 #define SXGBE_MMC_RX65TO127LO_GBCNT_REG 0x0948
166 #define SXGBE_MMC_RX65TO127HI_GBCNT_REG 0x094C
167 #define SXGBE_MMC_RX128TO255LO_GBCNT_REG 0x0950
168 #define SXGBE_MMC_RX128TO255HI_GBCNT_REG 0x0954
169 #define SXGBE_MMC_RX256TO511LO_GBCNT_REG 0x0958
170 #define SXGBE_MMC_RX256TO511HI_GBCNT_REG 0x095C
171 #define SXGBE_MMC_RX512TO1023LO_GBCNT_REG 0x0960
172 #define SXGBE_MMC_RX512TO1023HI_GBCNT_REG 0x0964
173 #define SXGBE_MMC_RX1023TOMAXLO_GBCNT_REG 0x0968
174 #define SXGBE_MMC_RX1023TOMAXHI_GBCNT_REG 0x096C
175 #define SXGBE_MMC_RXUNICASTLO_GCNT_REG 0x0970
176 #define SXGBE_MMC_RXUNICASTHI_GCNT_REG 0x0974
177 #define SXGBE_MMC_RXLENERRLO_REG 0x0978
178 #define SXGBE_MMC_RXLENERRHI_REG 0x097C
179 #define SXGBE_MMC_RXOUTOFRANGETYPELO_REG 0x0980
180 #define SXGBE_MMC_RXOUTOFRANGETYPEHI_REG 0x0984
181 #define SXGBE_MMC_RXPAUSELO_CNT_REG 0x0988
182 #define SXGBE_MMC_RXPAUSEHI_CNT_REG 0x098C
183 #define SXGBE_MMC_RXFIFOOVERFLOWLO_GBCNT_REG 0x0990
184 #define SXGBE_MMC_RXFIFOOVERFLOWHI_GBCNT_REG 0x0994
185 #define SXGBE_MMC_RXVLANLO_GBCNT_REG 0x0998
186 #define SXGBE_MMC_RXVLANHI_GBCNT_REG 0x099C
187 #define SXGBE_MMC_RXWATCHDOG_ERR_REG 0x09A0
189 /* L3/L4 function registers */
190 #define SXGBE_CORE_L34_ADDCTL_REG 0x0C00
191 #define SXGBE_CORE_L34_ADDCTL_REG 0x0C00
192 #define SXGBE_CORE_L34_DATA_REG 0x0C04
195 #define SXGBE_CORE_ARP_ADD_REG 0x0C10
198 #define SXGBE_CORE_RSS_CTL_REG 0x0C80
199 #define SXGBE_CORE_RSS_ADD_REG 0x0C88
200 #define SXGBE_CORE_RSS_DATA_REG 0x0C8C
202 /* RSS control register bits */
203 #define SXGBE_CORE_RSS_CTL_UDP4TE BIT(3)
204 #define SXGBE_CORE_RSS_CTL_TCP4TE BIT(2)
205 #define SXGBE_CORE_RSS_CTL_IP2TE BIT(1)
206 #define SXGBE_CORE_RSS_CTL_RSSE BIT(0)
208 /* IEEE 1588 registers */
209 #define SXGBE_CORE_TSTAMP_CTL_REG 0x0D00
210 #define SXGBE_CORE_SUBSEC_INC_REG 0x0D04
211 #define SXGBE_CORE_SYSTIME_SEC_REG 0x0D0C
212 #define SXGBE_CORE_SYSTIME_NSEC_REG 0x0D10
213 #define SXGBE_CORE_SYSTIME_SECUP_REG 0x0D14
214 #define SXGBE_CORE_TSTAMP_ADD_REG 0x0D18
215 #define SXGBE_CORE_SYSTIME_HWORD_REG 0x0D1C
216 #define SXGBE_CORE_TSTAMP_STATUS_REG 0x0D20
217 #define SXGBE_CORE_TXTIME_STATUSNSEC_REG 0x0D30
218 #define SXGBE_CORE_TXTIME_STATUSSEC_REG 0x0D34
220 /* Auxiliary registers */
221 #define SXGBE_CORE_AUX_CTL_REG 0x0D40
222 #define SXGBE_CORE_AUX_TSTAMP_NSEC_REG 0x0D48
223 #define SXGBE_CORE_AUX_TSTAMP_SEC_REG 0x0D4C
224 #define SXGBE_CORE_AUX_TSTAMP_INGCOR_REG 0x0D50
225 #define SXGBE_CORE_AUX_TSTAMP_ENGCOR_REG 0x0D54
226 #define SXGBE_CORE_AUX_TSTAMP_INGCOR_NSEC_REG 0x0D58
227 #define SXGBE_CORE_AUX_TSTAMP_INGCOR_SUBNSEC_REG 0x0D5C
228 #define SXGBE_CORE_AUX_TSTAMP_ENGCOR_NSEC_REG 0x0D60
229 #define SXGBE_CORE_AUX_TSTAMP_ENGCOR_SUBNSEC_REG 0x0D64
232 #define SXGBE_CORE_PPS_CTL_REG 0x0D70
233 #define SXGBE_CORE_PPS_BASE 0x0D80
236 #define SXGBE_CORE_PPS_TTIME_SEC_REG(addr) \
237 (SXGBE_CORE_PPS_BASE + (0x10 * addr) + 0x0)
238 #define SXGBE_CORE_PPS_TTIME_NSEC_REG(addr) \
239 (SXGBE_CORE_PPS_BASE + (0x10 * addr) + 0x4)
240 #define SXGBE_CORE_PPS_INTERVAL_REG(addr) \
241 (SXGBE_CORE_PPS_BASE + (0x10 * addr) + 0x8)
242 #define SXGBE_CORE_PPS_WIDTH_REG(addr) \
243 (SXGBE_CORE_PPS_BASE + (0x10 * addr) + 0xC)
244 #define SXGBE_CORE_PTO_CTL_REG 0x0DC0
245 #define SXGBE_CORE_SRCPORT_ITY0_REG 0x0DC4
246 #define SXGBE_CORE_SRCPORT_ITY1_REG 0x0DC8
247 #define SXGBE_CORE_SRCPORT_ITY2_REG 0x0DCC
248 #define SXGBE_CORE_LOGMSG_LEVEL_REG 0x0DD0
250 /* SXGBE MTL Registers */
251 #define SXGBE_MTL_BASE_REG 0x1000
252 #define SXGBE_MTL_OP_MODE_REG (SXGBE_MTL_BASE_REG + 0x0000)
253 #define SXGBE_MTL_DEBUG_CTL_REG (SXGBE_MTL_BASE_REG + 0x0008)
254 #define SXGBE_MTL_DEBUG_STATUS_REG (SXGBE_MTL_BASE_REG + 0x000C)
255 #define SXGBE_MTL_FIFO_DEBUGDATA_REG (SXGBE_MTL_BASE_REG + 0x0010)
256 #define SXGBE_MTL_INT_STATUS_REG (SXGBE_MTL_BASE_REG + 0x0020)
257 #define SXGBE_MTL_RXQ_DMAMAP0_REG (SXGBE_MTL_BASE_REG + 0x0030)
258 #define SXGBE_MTL_RXQ_DMAMAP1_REG (SXGBE_MTL_BASE_REG + 0x0034)
259 #define SXGBE_MTL_RXQ_DMAMAP2_REG (SXGBE_MTL_BASE_REG + 0x0038)
260 #define SXGBE_MTL_TX_PRTYMAP0_REG (SXGBE_MTL_BASE_REG + 0x0040)
261 #define SXGBE_MTL_TX_PRTYMAP1_REG (SXGBE_MTL_BASE_REG + 0x0044)
263 /* TC/Queue registers, qnum=0-15 */
264 #define SXGBE_MTL_TC_TXBASE_REG (SXGBE_MTL_BASE_REG + 0x0100)
265 #define SXGBE_MTL_TXQ_OPMODE_REG(qnum) \
266 (SXGBE_MTL_TC_TXBASE_REG + (qnum * 0x80) + 0x00)
267 #define SXGBE_MTL_SFMODE BIT(1)
268 #define SXGBE_MTL_FIFO_LSHIFT 16
269 #define SXGBE_MTL_ENABLE_QUEUE 0x00000008
270 #define SXGBE_MTL_TXQ_UNDERFLOW_REG(qnum) \
271 (SXGBE_MTL_TC_TXBASE_REG + (qnum * 0x80) + 0x04)
272 #define SXGBE_MTL_TXQ_DEBUG_REG(qnum) \
273 (SXGBE_MTL_TC_TXBASE_REG + (qnum * 0x80) + 0x08)
274 #define SXGBE_MTL_TXQ_ETSCTL_REG(qnum) \
275 (SXGBE_MTL_TC_TXBASE_REG + (qnum * 0x80) + 0x10)
276 #define SXGBE_MTL_TXQ_ETSSTATUS_REG(qnum) \
277 (SXGBE_MTL_TC_TXBASE_REG + (qnum * 0x80) + 0x14)
278 #define SXGBE_MTL_TXQ_QUANTWEIGHT_REG(qnum) \
279 (SXGBE_MTL_TC_TXBASE_REG + (qnum * 0x80) + 0x18)
281 #define SXGBE_MTL_TC_RXBASE_REG 0x1140
282 #define SXGBE_RX_MTL_SFMODE BIT(5)
283 #define SXGBE_MTL_RXQ_OPMODE_REG(qnum) \
284 (SXGBE_MTL_TC_RXBASE_REG + (qnum * 0x80) + 0x00)
285 #define SXGBE_MTL_RXQ_MISPKTOVERFLOW_REG(qnum) \
286 (SXGBE_MTL_TC_RXBASE_REG + (qnum * 0x80) + 0x04)
287 #define SXGBE_MTL_RXQ_DEBUG_REG(qnum) \
288 (SXGBE_MTL_TC_RXBASE_REG + (qnum * 0x80) + 0x08)
289 #define SXGBE_MTL_RXQ_CTL_REG(qnum) \
290 (SXGBE_MTL_TC_RXBASE_REG + (qnum * 0x80) + 0x0C)
291 #define SXGBE_MTL_RXQ_INTENABLE_REG(qnum) \
292 (SXGBE_MTL_TC_RXBASE_REG + (qnum * 0x80) + 0x30)
293 #define SXGBE_MTL_RXQ_INTSTATUS_REG(qnum) \
294 (SXGBE_MTL_TC_RXBASE_REG + (qnum * 0x80) + 0x34)
296 /* SXGBE DMA Registers */
297 #define SXGBE_DMA_BASE_REG 0x3000
298 #define SXGBE_DMA_MODE_REG (SXGBE_DMA_BASE_REG + 0x0000)
299 #define SXGBE_DMA_SOFT_RESET BIT(0)
300 #define SXGBE_DMA_SYSBUS_MODE_REG (SXGBE_DMA_BASE_REG + 0x0004)
301 #define SXGBE_DMA_AXI_UNDEF_BURST BIT(0)
302 #define SXGBE_DMA_ENHACE_ADDR_MODE BIT(11)
303 #define SXGBE_DMA_INT_STATUS_REG (SXGBE_DMA_BASE_REG + 0x0008)
304 #define SXGBE_DMA_AXI_ARCACHECTL_REG (SXGBE_DMA_BASE_REG + 0x0010)
305 #define SXGBE_DMA_AXI_AWCACHECTL_REG (SXGBE_DMA_BASE_REG + 0x0018)
306 #define SXGBE_DMA_DEBUG_STATUS0_REG (SXGBE_DMA_BASE_REG + 0x0020)
307 #define SXGBE_DMA_DEBUG_STATUS1_REG (SXGBE_DMA_BASE_REG + 0x0024)
308 #define SXGBE_DMA_DEBUG_STATUS2_REG (SXGBE_DMA_BASE_REG + 0x0028)
309 #define SXGBE_DMA_DEBUG_STATUS3_REG (SXGBE_DMA_BASE_REG + 0x002C)
310 #define SXGBE_DMA_DEBUG_STATUS4_REG (SXGBE_DMA_BASE_REG + 0x0030)
311 #define SXGBE_DMA_DEBUG_STATUS5_REG (SXGBE_DMA_BASE_REG + 0x0034)
313 /* Channel Registers, cha_num = 0-15 */
314 #define SXGBE_DMA_CHA_BASE_REG \
315 (SXGBE_DMA_BASE_REG + 0x0100)
316 #define SXGBE_DMA_CHA_CTL_REG(cha_num) \
317 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x00)
318 #define SXGBE_DMA_PBL_X8MODE BIT(16)
319 #define SXGBE_DMA_CHA_TXCTL_TSE_ENABLE BIT(12)
320 #define SXGBE_DMA_CHA_TXCTL_REG(cha_num) \
321 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x04)
322 #define SXGBE_DMA_CHA_RXCTL_REG(cha_num) \
323 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x08)
324 #define SXGBE_DMA_CHA_TXDESC_HADD_REG(cha_num) \
325 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x10)
326 #define SXGBE_DMA_CHA_TXDESC_LADD_REG(cha_num) \
327 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x14)
328 #define SXGBE_DMA_CHA_RXDESC_HADD_REG(cha_num) \
329 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x18)
330 #define SXGBE_DMA_CHA_RXDESC_LADD_REG(cha_num) \
331 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x1C)
332 #define SXGBE_DMA_CHA_TXDESC_TAILPTR_REG(cha_num) \
333 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x24)
334 #define SXGBE_DMA_CHA_RXDESC_TAILPTR_REG(cha_num) \
335 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x2C)
336 #define SXGBE_DMA_CHA_TXDESC_RINGLEN_REG(cha_num) \
337 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x30)
338 #define SXGBE_DMA_CHA_RXDESC_RINGLEN_REG(cha_num) \
339 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x34)
340 #define SXGBE_DMA_CHA_INT_ENABLE_REG(cha_num) \
341 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x38)
342 #define SXGBE_DMA_CHA_INT_RXWATCHTMR_REG(cha_num) \
343 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x3C)
344 #define SXGBE_DMA_CHA_TXDESC_CURADDLO_REG(cha_num) \
345 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x44)
346 #define SXGBE_DMA_CHA_RXDESC_CURADDLO_REG(cha_num) \
347 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x4C)
348 #define SXGBE_DMA_CHA_CURTXBUF_ADDHI_REG(cha_num) \
349 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x50)
350 #define SXGBE_DMA_CHA_CURTXBUF_ADDLO_REG(cha_num) \
351 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x54)
352 #define SXGBE_DMA_CHA_CURRXBUF_ADDHI_REG(cha_num) \
353 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x58)
354 #define SXGBE_DMA_CHA_CURRXBUF_ADDLO_REG(cha_num) \
355 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x5C)
356 #define SXGBE_DMA_CHA_STATUS_REG(cha_num) \
357 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x60)
359 /* TX DMA control register specific */
360 #define SXGBE_TX_START_DMA BIT(0)
362 /* sxgbe tx configuration register bitfields */
363 #define SXGBE_SPEED_10G 0x0
364 #define SXGBE_SPEED_2_5G 0x1
365 #define SXGBE_SPEED_1G 0x2
366 #define SXGBE_SPEED_LSHIFT 29
368 #define SXGBE_TX_ENABLE BIT(0)
369 #define SXGBE_TX_DISDIC_ALGO BIT(1)
370 #define SXGBE_TX_JABBER_DISABLE BIT(16)
372 /* sxgbe rx configuration register bitfields */
373 #define SXGBE_RX_ENABLE BIT(0)
374 #define SXGBE_RX_ACS_ENABLE BIT(1)
375 #define SXGBE_RX_WATCHDOG_DISABLE BIT(7)
376 #define SXGBE_RX_JUMBPKT_ENABLE BIT(8)
377 #define SXGBE_RX_CSUMOFFLOAD_ENABLE BIT(9)
378 #define SXGBE_RX_LOOPBACK_ENABLE BIT(10)
379 #define SXGBE_RX_ARPOFFLOAD_ENABLE BIT(31)
381 /* sxgbe vlan Tag Register bitfields */
382 #define SXGBE_VLAN_SVLAN_ENABLE BIT(18)
383 #define SXGBE_VLAN_DOUBLEVLAN_ENABLE BIT(26)
384 #define SXGBE_VLAN_INNERVLAN_ENABLE BIT(27)
386 /* XMAC VLAN Tag Inclusion Register(0x0060) bitfields
387 * Below fields same for Inner VLAN Tag Inclusion
388 * Register(0x0064) register
390 enum vlan_tag_ctl_tx {
396 #define SXGBE_VLAN_PRTY_CTL BIT(18)
397 #define SXGBE_VLAN_CSVL_CTL BIT(19)
399 /* SXGBE TX Q Flow Control Register bitfields */
400 #define SXGBE_TX_FLOW_CTL_FCB BIT(0)
401 #define SXGBE_TX_FLOW_CTL_TFB BIT(1)
403 /* SXGBE RX Q Flow Control Register bitfields */
404 #define SXGBE_RX_FLOW_CTL_ENABLE BIT(0)
405 #define SXGBE_RX_UNICAST_DETECT BIT(1)
406 #define SXGBE_RX_PRTYFLOW_CTL_ENABLE BIT(8)
408 /* sxgbe rx Q control0 register bitfields */
409 #define SXGBE_RX_Q_ENABLE 0x2
411 /* SXGBE hardware features bitfield specific */
412 /* Capability Register 0 */
413 #define SXGBE_HW_FEAT_GMII(cap) ((cap & 0x00000002) >> 1)
414 #define SXGBE_HW_FEAT_VLAN_HASH_FILTER(cap) ((cap & 0x00000010) >> 4)
415 #define SXGBE_HW_FEAT_SMA(cap) ((cap & 0x00000020) >> 5)
416 #define SXGBE_HW_FEAT_PMT_TEMOTE_WOP(cap) ((cap & 0x00000040) >> 6)
417 #define SXGBE_HW_FEAT_PMT_MAGIC_PKT(cap) ((cap & 0x00000080) >> 7)
418 #define SXGBE_HW_FEAT_RMON(cap) ((cap & 0x00000100) >> 8)
419 #define SXGBE_HW_FEAT_ARP_OFFLOAD(cap) ((cap & 0x00000200) >> 9)
420 #define SXGBE_HW_FEAT_IEEE1500_2008(cap) ((cap & 0x00001000) >> 12)
421 #define SXGBE_HW_FEAT_EEE(cap) ((cap & 0x00002000) >> 13)
422 #define SXGBE_HW_FEAT_TX_CSUM_OFFLOAD(cap) ((cap & 0x00004000) >> 14)
423 #define SXGBE_HW_FEAT_RX_CSUM_OFFLOAD(cap) ((cap & 0x00010000) >> 16)
424 #define SXGBE_HW_FEAT_MACADDR_COUNT(cap) ((cap & 0x007C0000) >> 18)
425 #define SXGBE_HW_FEAT_TSTMAP_SRC(cap) ((cap & 0x06000000) >> 25)
426 #define SXGBE_HW_FEAT_SRCADDR_VLAN(cap) ((cap & 0x08000000) >> 27)
428 /* Capability Register 1 */
429 #define SXGBE_HW_FEAT_RX_FIFO_SIZE(cap) ((cap & 0x0000001F))
430 #define SXGBE_HW_FEAT_TX_FIFO_SIZE(cap) ((cap & 0x000007C0) >> 6)
431 #define SXGBE_HW_FEAT_IEEE1588_HWORD(cap) ((cap & 0x00002000) >> 13)
432 #define SXGBE_HW_FEAT_DCB(cap) ((cap & 0x00010000) >> 16)
433 #define SXGBE_HW_FEAT_SPLIT_HDR(cap) ((cap & 0x00020000) >> 17)
434 #define SXGBE_HW_FEAT_TSO(cap) ((cap & 0x00040000) >> 18)
435 #define SXGBE_HW_FEAT_DEBUG_MEM_IFACE(cap) ((cap & 0x00080000) >> 19)
436 #define SXGBE_HW_FEAT_RSS(cap) ((cap & 0x00100000) >> 20)
437 #define SXGBE_HW_FEAT_HASH_TABLE_SIZE(cap) ((cap & 0x03000000) >> 24)
438 #define SXGBE_HW_FEAT_L3L4_FILTER_NUM(cap) ((cap & 0x78000000) >> 27)
440 /* Capability Register 2 */
441 #define SXGBE_HW_FEAT_RX_MTL_QUEUES(cap) ((cap & 0x0000000F))
442 #define SXGBE_HW_FEAT_TX_MTL_QUEUES(cap) ((cap & 0x000003C0) >> 6)
443 #define SXGBE_HW_FEAT_RX_DMA_CHANNELS(cap) ((cap & 0x0000F000) >> 12)
444 #define SXGBE_HW_FEAT_TX_DMA_CHANNELS(cap) ((cap & 0x003C0000) >> 18)
445 #define SXGBE_HW_FEAT_PPS_OUTPUTS(cap) ((cap & 0x07000000) >> 24)
446 #define SXGBE_HW_FEAT_AUX_SNAPSHOTS(cap) ((cap & 0x70000000) >> 28)
448 /* DMAchannel interrupt enable specific */
449 /* DMA Normal interrupt */
450 #define SXGBE_DMA_INT_ENA_NIE BIT(16) /* Normal Summary */
451 #define SXGBE_DMA_INT_ENA_TIE BIT(0) /* Transmit Interrupt */
452 #define SXGBE_DMA_INT_ENA_TUE BIT(2) /* Transmit Buffer Unavailable */
453 #define SXGBE_DMA_INT_ENA_RIE BIT(6) /* Receive Interrupt */
455 #define SXGBE_DMA_INT_NORMAL \
456 (SXGBE_DMA_INT_ENA_NIE | SXGBE_DMA_INT_ENA_RIE | \
457 SXGBE_DMA_INT_ENA_TIE | SXGBE_DMA_INT_ENA_TUE)
459 /* DMA Abnormal interrupt */
460 #define SXGBE_DMA_INT_ENA_AIE BIT(15) /* Abnormal Summary */
461 #define SXGBE_DMA_INT_ENA_TSE BIT(1) /* Transmit Stopped */
462 #define SXGBE_DMA_INT_ENA_RUE BIT(7) /* Receive Buffer Unavailable */
463 #define SXGBE_DMA_INT_ENA_RSE BIT(8) /* Receive Stopped */
464 #define SXGBE_DMA_INT_ENA_FBE BIT(12) /* Fatal Bus Error */
465 #define SXGBE_DMA_INT_ENA_CDEE BIT(13) /* Context Descriptor Error */
467 #define SXGBE_DMA_INT_ABNORMAL \
468 (SXGBE_DMA_INT_ENA_AIE | SXGBE_DMA_INT_ENA_TSE | \
469 SXGBE_DMA_INT_ENA_RUE | SXGBE_DMA_INT_ENA_RSE | \
470 SXGBE_DMA_INT_ENA_FBE | SXGBE_DMA_INT_ENA_CDEE)
472 #define SXGBE_DMA_ENA_INT (SXGBE_DMA_INT_NORMAL | SXGBE_DMA_INT_ABNORMAL)
474 /* DMA channel interrupt status specific */
475 #define SXGBE_DMA_INT_STATUS_REB2 BIT(21)
476 #define SXGBE_DMA_INT_STATUS_REB1 BIT(20)
477 #define SXGBE_DMA_INT_STATUS_REB0 BIT(19)
478 #define SXGBE_DMA_INT_STATUS_TEB2 BIT(18)
479 #define SXGBE_DMA_INT_STATUS_TEB1 BIT(17)
480 #define SXGBE_DMA_INT_STATUS_TEB0 BIT(16)
481 #define SXGBE_DMA_INT_STATUS_NIS BIT(15)
482 #define SXGBE_DMA_INT_STATUS_AIS BIT(14)
483 #define SXGBE_DMA_INT_STATUS_CTXTERR BIT(13)
484 #define SXGBE_DMA_INT_STATUS_FBE BIT(12)
485 #define SXGBE_DMA_INT_STATUS_RPS BIT(8)
486 #define SXGBE_DMA_INT_STATUS_RBU BIT(7)
487 #define SXGBE_DMA_INT_STATUS_RI BIT(6)
488 #define SXGBE_DMA_INT_STATUS_TBU BIT(2)
489 #define SXGBE_DMA_INT_STATUS_TPS BIT(1)
490 #define SXGBE_DMA_INT_STATUS_TI BIT(0)
492 #endif /* __SXGBE_REGMAP_H__ */