drivers/net/ethernet/sfc/ef10.c

   1 /****************************************************************************
   2  * Driver for Solarflare network controllers and boards
   3  * Copyright 2012-2013 Solarflare Communications Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published
   7  * by the Free Software Foundation, incorporated herein by reference.
   8  */
   9
  10 #include "net_driver.h"
  11 #include "ef10_regs.h"
  12 #include "io.h"
  13 #include "mcdi.h"
  14 #include "mcdi_pcol.h"
  15 #include "nic.h"
  16 #include "workarounds.h"
  17 #include <linux/in.h>
  18 #include <linux/jhash.h>
  19 #include <linux/wait.h>
  20 #include <linux/workqueue.h>
  21
  22 /* Hardware control for EF10 architecture including 'Huntington'. */
  23
  24 #define EFX_EF10_DRVGEN_EV              7
  25 enum {
  26         EFX_EF10_TEST = 1,
  27         EFX_EF10_REFILL,
  28 };
  29
  30 /* The reserved RSS context value */
  31 #define EFX_EF10_RSS_CONTEXT_INVALID    0xffffffff
  32
  33 /* The filter table(s) are managed by firmware and we have write-only
  34  * access.  When removing filters we must identify them to the
  35  * firmware by a 64-bit handle, but this is too wide for Linux kernel
  36  * interfaces (32-bit for RX NFC, 16-bit for RFS).  Also, we need to
  37  * be able to tell in advance whether a requested insertion will
  38  * replace an existing filter.  Therefore we maintain a software hash
  39  * table, which should be at least as large as the hardware hash
  40  * table.
  41  *
  42  * Huntington has a single 8K filter table shared between all filter
  43  * types and both ports.
  44  */
  45 #define HUNT_FILTER_TBL_ROWS 8192
  46
  47 struct efx_ef10_filter_table {
  48 /* The RX match field masks supported by this fw & hw, in order of priority */
  49         enum efx_filter_match_flags rx_match_flags[
  50                 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM];
  51         unsigned int rx_match_count;
  52
  53         struct {
  54                 unsigned long spec;     /* pointer to spec plus flag bits */
  55 /* BUSY flag indicates that an update is in progress.  STACK_OLD is
  56  * used to mark and sweep stack-owned MAC filters.
  57  */
  58 #define EFX_EF10_FILTER_FLAG_BUSY       1UL
  59 #define EFX_EF10_FILTER_FLAG_STACK_OLD  2UL
  60 #define EFX_EF10_FILTER_FLAGS           3UL
  61                 u64 handle;             /* firmware handle */
  62         } *entry;
  63         wait_queue_head_t waitq;
  64 /* Shadow of net_device address lists, guarded by mac_lock */
  65 #define EFX_EF10_FILTER_STACK_UC_MAX    32
  66 #define EFX_EF10_FILTER_STACK_MC_MAX    256
  67         struct {
  68                 u8 addr[ETH_ALEN];
  69                 u16 id;
  70         } stack_uc_list[EFX_EF10_FILTER_STACK_UC_MAX],
  71           stack_mc_list[EFX_EF10_FILTER_STACK_MC_MAX];
  72         int stack_uc_count;             /* negative for PROMISC */
  73         int stack_mc_count;             /* negative for PROMISC/ALLMULTI */
  74 };
  75
  76 /* An arbitrary search limit for the software hash table */
  77 #define EFX_EF10_FILTER_SEARCH_LIMIT 200
  78
  79 static void efx_ef10_rx_push_indir_table(struct efx_nic *efx);
  80 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
  81 static void efx_ef10_filter_table_remove(struct efx_nic *efx);
  82
  83 static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
  84 {
  85         efx_dword_t reg;
  86
  87         efx_readd(efx, &reg, ER_DZ_BIU_MC_SFT_STATUS);
  88         return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
  89                 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
  90 }
  91
  92 static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
  93 {
  94         return resource_size(&efx->pci_dev->resource[EFX_MEM_BAR]);
  95 }
  96
  97 static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
  98 {
  99         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_OUT_LEN);
 100         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 101         size_t outlen;
 102         int rc;
 103
 104         BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
 105
 106         rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
 107                           outbuf, sizeof(outbuf), &outlen);
 108         if (rc)
 109                 return rc;
 110         if (outlen < sizeof(outbuf)) {
 111                 netif_err(efx, drv, efx->net_dev,
 112                           "unable to read datapath firmware capabilities\n");
 113                 return -EIO;
 114         }
 115
 116         nic_data->datapath_caps =
 117                 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
 118
 119         if (!(nic_data->datapath_caps &
 120               (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))) {
 121                 netif_err(efx, drv, efx->net_dev,
 122                           "current firmware does not support TSO\n");
 123                 return -ENODEV;
 124         }
 125
 126         if (!(nic_data->datapath_caps &
 127               (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
 128                 netif_err(efx, probe, efx->net_dev,
 129                           "current firmware does not support an RX prefix\n");
 130                 return -ENODEV;
 131         }
 132
 133         return 0;
 134 }
 135
 136 static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
 137 {
 138         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
 139         int rc;
 140
 141         rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
 142                           outbuf, sizeof(outbuf), NULL);
 143         if (rc)
 144                 return rc;
 145         rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
 146         return rc > 0 ? rc : -ERANGE;
 147 }
 148
 149 static int efx_ef10_get_mac_address(struct efx_nic *efx, u8 *mac_address)
 150 {
 151         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
 152         size_t outlen;
 153         int rc;
 154
 155         BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
 156
 157         rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
 158                           outbuf, sizeof(outbuf), &outlen);
 159         if (rc)
 160                 return rc;
 161         if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
 162                 return -EIO;
 163
 164         memcpy(mac_address,
 165                MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE), ETH_ALEN);
 166         return 0;
 167 }
 168
 169 static int efx_ef10_probe(struct efx_nic *efx)
 170 {
 171         struct efx_ef10_nic_data *nic_data;
 172         int i, rc;
 173
 174         /* We can have one VI for each 8K region.  However we need
 175          * multiple TX queues per channel.
 176          */
 177         efx->max_channels =
 178                 min_t(unsigned int,
 179                       EFX_MAX_CHANNELS,
 180                       resource_size(&efx->pci_dev->resource[EFX_MEM_BAR]) /
 181                       (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES));
 182         BUG_ON(efx->max_channels == 0);
 183
 184         nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
 185         if (!nic_data)
 186                 return -ENOMEM;
 187         efx->nic_data = nic_data;
 188
 189         rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
 190                                   8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
 191         if (rc)
 192                 goto fail1;
 193
 194         /* Get the MC's warm boot count.  In case it's rebooting right
 195          * now, be prepared to retry.
 196          */
 197         i = 0;
 198         for (;;) {
 199                 rc = efx_ef10_get_warm_boot_count(efx);
 200                 if (rc >= 0)
 201                         break;
 202                 if (++i == 5)
 203                         goto fail2;
 204                 ssleep(1);
 205         }
 206         nic_data->warm_boot_count = rc;
 207
 208         nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
 209
 210         /* In case we're recovering from a crash (kexec), we want to
 211          * cancel any outstanding request by the previous user of this
 212          * function.  We send a special message using the least
 213          * significant bits of the 'high' (doorbell) register.
 214          */
 215         _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
 216
 217         rc = efx_mcdi_init(efx);
 218         if (rc)
 219                 goto fail2;
 220
 221         /* Reset (most) configuration for this function */
 222         rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
 223         if (rc)
 224                 goto fail3;
 225
 226         /* Enable event logging */
 227         rc = efx_mcdi_log_ctrl(efx, true, false, 0);
 228         if (rc)
 229                 goto fail3;
 230
 231         rc = efx_ef10_init_datapath_caps(efx);
 232         if (rc < 0)
 233                 goto fail3;
 234
 235         efx->rx_packet_len_offset =
 236                 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
 237
 238         rc = efx_mcdi_port_get_number(efx);
 239         if (rc < 0)
 240                 goto fail3;
 241         efx->port_num = rc;
 242
 243         rc = efx_ef10_get_mac_address(efx, efx->net_dev->perm_addr);
 244         if (rc)
 245                 goto fail3;
 246
 247         rc = efx_ef10_get_sysclk_freq(efx);
 248         if (rc < 0)
 249                 goto fail3;
 250         efx->timer_quantum_ns = 1536000 / rc; /* 1536 cycles */
 251
 252         /* Check whether firmware supports bug 35388 workaround */
 253         rc = efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG35388, true);
 254         if (rc == 0)
 255                 nic_data->workaround_35388 = true;
 256         else if (rc != -ENOSYS && rc != -ENOENT)
 257                 goto fail3;
 258         netif_dbg(efx, probe, efx->net_dev,
 259                   "workaround for bug 35388 is %sabled\n",
 260                   nic_data->workaround_35388 ? "en" : "dis");
 261
 262         rc = efx_mcdi_mon_probe(efx);
 263         if (rc)
 264                 goto fail3;
 265
 266         return 0;
 267
 268 fail3:
 269         efx_mcdi_fini(efx);
 270 fail2:
 271         efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
 272 fail1:
 273         kfree(nic_data);
 274         efx->nic_data = NULL;
 275         return rc;
 276 }
 277
 278 static int efx_ef10_free_vis(struct efx_nic *efx)
 279 {
 280         int rc = efx_mcdi_rpc(efx, MC_CMD_FREE_VIS, NULL, 0, NULL, 0, NULL);
 281
 282         /* -EALREADY means nothing to free, so ignore */
 283         if (rc == -EALREADY)
 284                 rc = 0;
 285         return rc;
 286 }
 287
 288 static void efx_ef10_remove(struct efx_nic *efx)
 289 {
 290         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 291         int rc;
 292
 293         efx_mcdi_mon_remove(efx);
 294
 295         /* This needs to be after efx_ptp_remove_channel() with no filters */
 296         efx_ef10_rx_free_indir_table(efx);
 297
 298         rc = efx_ef10_free_vis(efx);
 299         WARN_ON(rc != 0);
 300
 301         efx_mcdi_fini(efx);
 302         efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
 303         kfree(nic_data);
 304 }
 305
 306 static int efx_ef10_alloc_vis(struct efx_nic *efx,
 307                               unsigned int min_vis, unsigned int max_vis)
 308 {
 309         MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
 310         MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
 311         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 312         size_t outlen;
 313         int rc;
 314
 315         MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
 316         MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
 317         rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
 318                           outbuf, sizeof(outbuf), &outlen);
 319         if (rc != 0)
 320                 return rc;
 321
 322         if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
 323                 return -EIO;
 324
 325         netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
 326                   MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
 327
 328         nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
 329         nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
 330         return 0;
 331 }
 332
 333 static int efx_ef10_dimension_resources(struct efx_nic *efx)
 334 {
 335         unsigned int n_vis =
 336                 max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
 337
 338         return efx_ef10_alloc_vis(efx, n_vis, n_vis);
 339 }
 340
 341 static int efx_ef10_init_nic(struct efx_nic *efx)
 342 {
 343         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 344         int rc;
 345
 346         if (nic_data->must_check_datapath_caps) {
 347                 rc = efx_ef10_init_datapath_caps(efx);
 348                 if (rc)
 349                         return rc;
 350                 nic_data->must_check_datapath_caps = false;
 351         }
 352
 353         if (nic_data->must_realloc_vis) {
 354                 /* We cannot let the number of VIs change now */
 355                 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
 356                                         nic_data->n_allocated_vis);
 357                 if (rc)
 358                         return rc;
 359                 nic_data->must_realloc_vis = false;
 360         }
 361
 362         efx_ef10_rx_push_indir_table(efx);
 363         return 0;
 364 }
 365
 366 static int efx_ef10_map_reset_flags(u32 *flags)
 367 {
 368         enum {
 369                 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
 370                                    ETH_RESET_SHARED_SHIFT),
 371                 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
 372                                   ETH_RESET_OFFLOAD | ETH_RESET_MAC |
 373                                   ETH_RESET_PHY | ETH_RESET_MGMT) <<
 374                                  ETH_RESET_SHARED_SHIFT)
 375         };
 376
 377         /* We assume for now that our PCI function is permitted to
 378          * reset everything.
 379          */
 380
 381         if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
 382                 *flags &= ~EF10_RESET_MC;
 383                 return RESET_TYPE_WORLD;
 384         }
 385
 386         if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
 387                 *flags &= ~EF10_RESET_PORT;
 388                 return RESET_TYPE_ALL;
 389         }
 390
 391         /* no invisible reset implemented */
 392
 393         return -EINVAL;
 394 }
 395
 396 #define EF10_DMA_STAT(ext_name, mcdi_name)                      \
 397         [EF10_STAT_ ## ext_name] =                              \
 398         { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
 399 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name)                \
 400         [EF10_STAT_ ## int_name] =                              \
 401         { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
 402 #define EF10_OTHER_STAT(ext_name)                               \
 403         [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
 404
 405 static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
 406         EF10_DMA_STAT(tx_bytes, TX_BYTES),
 407         EF10_DMA_STAT(tx_packets, TX_PKTS),
 408         EF10_DMA_STAT(tx_pause, TX_PAUSE_PKTS),
 409         EF10_DMA_STAT(tx_control, TX_CONTROL_PKTS),
 410         EF10_DMA_STAT(tx_unicast, TX_UNICAST_PKTS),
 411         EF10_DMA_STAT(tx_multicast, TX_MULTICAST_PKTS),
 412         EF10_DMA_STAT(tx_broadcast, TX_BROADCAST_PKTS),
 413         EF10_DMA_STAT(tx_lt64, TX_LT64_PKTS),
 414         EF10_DMA_STAT(tx_64, TX_64_PKTS),
 415         EF10_DMA_STAT(tx_65_to_127, TX_65_TO_127_PKTS),
 416         EF10_DMA_STAT(tx_128_to_255, TX_128_TO_255_PKTS),
 417         EF10_DMA_STAT(tx_256_to_511, TX_256_TO_511_PKTS),
 418         EF10_DMA_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS),
 419         EF10_DMA_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
 420         EF10_DMA_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
 421         EF10_DMA_STAT(rx_bytes, RX_BYTES),
 422         EF10_DMA_INVIS_STAT(rx_bytes_minus_good_bytes, RX_BAD_BYTES),
 423         EF10_OTHER_STAT(rx_good_bytes),
 424         EF10_OTHER_STAT(rx_bad_bytes),
 425         EF10_DMA_STAT(rx_packets, RX_PKTS),
 426         EF10_DMA_STAT(rx_good, RX_GOOD_PKTS),
 427         EF10_DMA_STAT(rx_bad, RX_BAD_FCS_PKTS),
 428         EF10_DMA_STAT(rx_pause, RX_PAUSE_PKTS),
 429         EF10_DMA_STAT(rx_control, RX_CONTROL_PKTS),
 430         EF10_DMA_STAT(rx_unicast, RX_UNICAST_PKTS),
 431         EF10_DMA_STAT(rx_multicast, RX_MULTICAST_PKTS),
 432         EF10_DMA_STAT(rx_broadcast, RX_BROADCAST_PKTS),
 433         EF10_DMA_STAT(rx_lt64, RX_UNDERSIZE_PKTS),
 434         EF10_DMA_STAT(rx_64, RX_64_PKTS),
 435         EF10_DMA_STAT(rx_65_to_127, RX_65_TO_127_PKTS),
 436         EF10_DMA_STAT(rx_128_to_255, RX_128_TO_255_PKTS),
 437         EF10_DMA_STAT(rx_256_to_511, RX_256_TO_511_PKTS),
 438         EF10_DMA_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS),
 439         EF10_DMA_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
 440         EF10_DMA_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
 441         EF10_DMA_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS),
 442         EF10_DMA_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS),
 443         EF10_DMA_STAT(rx_overflow, RX_OVERFLOW_PKTS),
 444         EF10_DMA_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS),
 445         EF10_DMA_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS),
 446         EF10_DMA_STAT(rx_nodesc_drops, RX_NODESC_DROPS),
 447 };
 448
 449 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_tx_bytes) |           \
 450                                (1ULL << EF10_STAT_tx_packets) |         \
 451                                (1ULL << EF10_STAT_tx_pause) |           \
 452                                (1ULL << EF10_STAT_tx_unicast) |         \
 453                                (1ULL << EF10_STAT_tx_multicast) |       \
 454                                (1ULL << EF10_STAT_tx_broadcast) |       \
 455                                (1ULL << EF10_STAT_rx_bytes) |           \
 456                                (1ULL << EF10_STAT_rx_bytes_minus_good_bytes) | \
 457                                (1ULL << EF10_STAT_rx_good_bytes) |      \
 458                                (1ULL << EF10_STAT_rx_bad_bytes) |       \
 459                                (1ULL << EF10_STAT_rx_packets) |         \
 460                                (1ULL << EF10_STAT_rx_good) |            \
 461                                (1ULL << EF10_STAT_rx_bad) |             \
 462                                (1ULL << EF10_STAT_rx_pause) |           \
 463                                (1ULL << EF10_STAT_rx_control) |         \
 464                                (1ULL << EF10_STAT_rx_unicast) |         \
 465                                (1ULL << EF10_STAT_rx_multicast) |       \
 466                                (1ULL << EF10_STAT_rx_broadcast) |       \
 467                                (1ULL << EF10_STAT_rx_lt64) |            \
 468                                (1ULL << EF10_STAT_rx_64) |              \
 469                                (1ULL << EF10_STAT_rx_65_to_127) |       \
 470                                (1ULL << EF10_STAT_rx_128_to_255) |      \
 471                                (1ULL << EF10_STAT_rx_256_to_511) |      \
 472                                (1ULL << EF10_STAT_rx_512_to_1023) |     \
 473                                (1ULL << EF10_STAT_rx_1024_to_15xx) |    \
 474                                (1ULL << EF10_STAT_rx_15xx_to_jumbo) |   \
 475                                (1ULL << EF10_STAT_rx_gtjumbo) |         \
 476                                (1ULL << EF10_STAT_rx_bad_gtjumbo) |     \
 477                                (1ULL << EF10_STAT_rx_overflow) |        \
 478                                (1ULL << EF10_STAT_rx_nodesc_drops))
 479
 480 /* These statistics are only provided by the 10G MAC.  For a 10G/40G
 481  * switchable port we do not expose these because they might not
 482  * include all the packets they should.
 483  */
 484 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_tx_control) |       \
 485                                  (1ULL << EF10_STAT_tx_lt64) |          \
 486                                  (1ULL << EF10_STAT_tx_64) |            \
 487                                  (1ULL << EF10_STAT_tx_65_to_127) |     \
 488                                  (1ULL << EF10_STAT_tx_128_to_255) |    \
 489                                  (1ULL << EF10_STAT_tx_256_to_511) |    \
 490                                  (1ULL << EF10_STAT_tx_512_to_1023) |   \
 491                                  (1ULL << EF10_STAT_tx_1024_to_15xx) |  \
 492                                  (1ULL << EF10_STAT_tx_15xx_to_jumbo))
 493
 494 /* These statistics are only provided by the 40G MAC.  For a 10G/40G
 495  * switchable port we do expose these because the errors will otherwise
 496  * be silent.
 497  */
 498 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_rx_align_error) |  \
 499                                   (1ULL << EF10_STAT_rx_length_error))
 500
 501 static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
 502 {
 503         u64 raw_mask = HUNT_COMMON_STAT_MASK;
 504         u32 port_caps = efx_mcdi_phy_get_caps(efx);
 505
 506         if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN))
 507                 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
 508         else
 509                 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
 510         return raw_mask;
 511 }
 512
 513 static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
 514 {
 515         u64 raw_mask = efx_ef10_raw_stat_mask(efx);
 516
 517 #if BITS_PER_LONG == 64
 518         mask[0] = raw_mask;
 519 #else
 520         mask[0] = raw_mask & 0xffffffff;
 521         mask[1] = raw_mask >> 32;
 522 #endif
 523 }
 524
 525 static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
 526 {
 527         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
 528
 529         efx_ef10_get_stat_mask(efx, mask);
 530         return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
 531                                       mask, names);
 532 }
 533
 534 static int efx_ef10_try_update_nic_stats(struct efx_nic *efx)
 535 {
 536         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 537         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
 538         __le64 generation_start, generation_end;
 539         u64 *stats = nic_data->stats;
 540         __le64 *dma_stats;
 541
 542         efx_ef10_get_stat_mask(efx, mask);
 543
 544         dma_stats = efx->stats_buffer.addr;
 545         nic_data = efx->nic_data;
 546
 547         generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
 548         if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
 549                 return 0;
 550         rmb();
 551         efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
 552                              stats, efx->stats_buffer.addr, false);
 553         rmb();
 554         generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
 555         if (generation_end != generation_start)
 556                 return -EAGAIN;
 557
 558         /* Update derived statistics */
 559         stats[EF10_STAT_rx_good_bytes] =
 560                 stats[EF10_STAT_rx_bytes] -
 561                 stats[EF10_STAT_rx_bytes_minus_good_bytes];
 562         efx_update_diff_stat(&stats[EF10_STAT_rx_bad_bytes],
 563                              stats[EF10_STAT_rx_bytes_minus_good_bytes]);
 564
 565         return 0;
 566 }
 567
 568
 569 static size_t efx_ef10_update_stats(struct efx_nic *efx, u64 *full_stats,
 570                                     struct rtnl_link_stats64 *core_stats)
 571 {
 572         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
 573         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 574         u64 *stats = nic_data->stats;
 575         size_t stats_count = 0, index;
 576         int retry;
 577
 578         efx_ef10_get_stat_mask(efx, mask);
 579
 580         /* If we're unlucky enough to read statistics during the DMA, wait
 581          * up to 10ms for it to finish (typically takes <500us)
 582          */
 583         for (retry = 0; retry < 100; ++retry) {
 584                 if (efx_ef10_try_update_nic_stats(efx) == 0)
 585                         break;
 586                 udelay(100);
 587         }
 588
 589         if (full_stats) {
 590                 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
 591                         if (efx_ef10_stat_desc[index].name) {
 592                                 *full_stats++ = stats[index];
 593                                 ++stats_count;
 594                         }
 595                 }
 596         }
 597
 598         if (core_stats) {
 599                 core_stats->rx_packets = stats[EF10_STAT_rx_packets];
 600                 core_stats->tx_packets = stats[EF10_STAT_tx_packets];
 601                 core_stats->rx_bytes = stats[EF10_STAT_rx_bytes];
 602                 core_stats->tx_bytes = stats[EF10_STAT_tx_bytes];
 603                 core_stats->rx_dropped = stats[EF10_STAT_rx_nodesc_drops];
 604                 core_stats->multicast = stats[EF10_STAT_rx_multicast];
 605                 core_stats->rx_length_errors =
 606                         stats[EF10_STAT_rx_gtjumbo] +
 607                         stats[EF10_STAT_rx_length_error];
 608                 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
 609                 core_stats->rx_frame_errors = stats[EF10_STAT_rx_align_error];
 610                 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
 611                 core_stats->rx_errors = (core_stats->rx_length_errors +
 612                                          core_stats->rx_crc_errors +
 613                                          core_stats->rx_frame_errors);
 614         }
 615
 616         return stats_count;
 617 }
 618
 619 static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
 620 {
 621         struct efx_nic *efx = channel->efx;
 622         unsigned int mode, value;
 623         efx_dword_t timer_cmd;
 624
 625         if (channel->irq_moderation) {
 626                 mode = 3;
 627                 value = channel->irq_moderation - 1;
 628         } else {
 629                 mode = 0;
 630                 value = 0;
 631         }
 632
 633         if (EFX_EF10_WORKAROUND_35388(efx)) {
 634                 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
 635                                      EFE_DD_EVQ_IND_TIMER_FLAGS,
 636                                      ERF_DD_EVQ_IND_TIMER_MODE, mode,
 637                                      ERF_DD_EVQ_IND_TIMER_VAL, value);
 638                 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
 639                                 channel->channel);
 640         } else {
 641                 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
 642                                      ERF_DZ_TC_TIMER_VAL, value);
 643                 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
 644                                 channel->channel);
 645         }
 646 }
 647
 648 static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
 649 {
 650         wol->supported = 0;
 651         wol->wolopts = 0;
 652         memset(&wol->sopass, 0, sizeof(wol->sopass));
 653 }
 654
 655 static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
 656 {
 657         if (type != 0)
 658                 return -EINVAL;
 659         return 0;
 660 }
 661
 662 static void efx_ef10_mcdi_request(struct efx_nic *efx,
 663                                   const efx_dword_t *hdr, size_t hdr_len,
 664                                   const efx_dword_t *sdu, size_t sdu_len)
 665 {
 666         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 667         u8 *pdu = nic_data->mcdi_buf.addr;
 668
 669         memcpy(pdu, hdr, hdr_len);
 670         memcpy(pdu + hdr_len, sdu, sdu_len);
 671         wmb();
 672
 673         /* The hardware provides 'low' and 'high' (doorbell) registers
 674          * for passing the 64-bit address of an MCDI request to
 675          * firmware.  However the dwords are swapped by firmware.  The
 676          * least significant bits of the doorbell are then 0 for all
 677          * MCDI requests due to alignment.
 678          */
 679         _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
 680                     ER_DZ_MC_DB_LWRD);
 681         _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
 682                     ER_DZ_MC_DB_HWRD);
 683 }
 684
 685 static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
 686 {
 687         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 688         const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
 689
 690         rmb();
 691         return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
 692 }
 693
 694 static void
 695 efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
 696                             size_t offset, size_t outlen)
 697 {
 698         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 699         const u8 *pdu = nic_data->mcdi_buf.addr;
 700
 701         memcpy(outbuf, pdu + offset, outlen);
 702 }
 703
 704 static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
 705 {
 706         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 707         int rc;
 708
 709         rc = efx_ef10_get_warm_boot_count(efx);
 710         if (rc < 0) {
 711                 /* The firmware is presumably in the process of
 712                  * rebooting.  However, we are supposed to report each
 713                  * reboot just once, so we must only do that once we
 714                  * can read and store the updated warm boot count.
 715                  */
 716                 return 0;
 717         }
 718
 719         if (rc == nic_data->warm_boot_count)
 720                 return 0;
 721
 722         nic_data->warm_boot_count = rc;
 723
 724         /* All our allocations have been reset */
 725         nic_data->must_realloc_vis = true;
 726         nic_data->must_restore_filters = true;
 727         nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
 728
 729         /* The datapath firmware might have been changed */
 730         nic_data->must_check_datapath_caps = true;
 731
 732         /* MAC statistics have been cleared on the NIC; clear the local
 733          * statistic that we update with efx_update_diff_stat().
 734          */
 735         nic_data->stats[EF10_STAT_rx_bad_bytes] = 0;
 736
 737         return -EIO;
 738 }
 739
 740 /* Handle an MSI interrupt
 741  *
 742  * Handle an MSI hardware interrupt.  This routine schedules event
 743  * queue processing.  No interrupt acknowledgement cycle is necessary.
 744  * Also, we never need to check that the interrupt is for us, since
 745  * MSI interrupts cannot be shared.
 746  */
 747 static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
 748 {
 749         struct efx_msi_context *context = dev_id;
 750         struct efx_nic *efx = context->efx;
 751
 752         netif_vdbg(efx, intr, efx->net_dev,
 753                    "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
 754
 755         if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) {
 756                 /* Note test interrupts */
 757                 if (context->index == efx->irq_level)
 758                         efx->last_irq_cpu = raw_smp_processor_id();
 759
 760                 /* Schedule processing of the channel */
 761                 efx_schedule_channel_irq(efx->channel[context->index]);
 762         }
 763
 764         return IRQ_HANDLED;
 765 }
 766
 767 static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
 768 {
 769         struct efx_nic *efx = dev_id;
 770         bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
 771         struct efx_channel *channel;
 772         efx_dword_t reg;
 773         u32 queues;
 774
 775         /* Read the ISR which also ACKs the interrupts */
 776         efx_readd(efx, &reg, ER_DZ_BIU_INT_ISR);
 777         queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
 778
 779         if (queues == 0)
 780                 return IRQ_NONE;
 781
 782         if (likely(soft_enabled)) {
 783                 /* Note test interrupts */
 784                 if (queues & (1U << efx->irq_level))
 785                         efx->last_irq_cpu = raw_smp_processor_id();
 786
 787                 efx_for_each_channel(channel, efx) {
 788                         if (queues & 1)
 789                                 efx_schedule_channel_irq(channel);
 790                         queues >>= 1;
 791                 }
 792         }
 793
 794         netif_vdbg(efx, intr, efx->net_dev,
 795                    "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
 796                    irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
 797
 798         return IRQ_HANDLED;
 799 }
 800
 801 static void efx_ef10_irq_test_generate(struct efx_nic *efx)
 802 {
 803         MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
 804
 805         BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
 806
 807         MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
 808         (void) efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
 809                             inbuf, sizeof(inbuf), NULL, 0, NULL);
 810 }
 811
 812 static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
 813 {
 814         return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
 815                                     (tx_queue->ptr_mask + 1) *
 816                                     sizeof(efx_qword_t),
 817                                     GFP_KERNEL);
 818 }
 819
 820 /* This writes to the TX_DESC_WPTR and also pushes data */
 821 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
 822                                          const efx_qword_t *txd)
 823 {
 824         unsigned int write_ptr;
 825         efx_oword_t reg;
 826
 827         write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
 828         EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
 829         reg.qword[0] = *txd;
 830         efx_writeo_page(tx_queue->efx, &reg,
 831                         ER_DZ_TX_DESC_UPD, tx_queue->queue);
 832 }
 833
 834 static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
 835 {
 836         MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
 837                                                        EFX_BUF_SIZE));
 838         MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_TXQ_OUT_LEN);
 839         bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
 840         size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
 841         struct efx_channel *channel = tx_queue->channel;
 842         struct efx_nic *efx = tx_queue->efx;
 843         size_t inlen, outlen;
 844         dma_addr_t dma_addr;
 845         efx_qword_t *txd;
 846         int rc;
 847         int i;
 848
 849         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
 850         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
 851         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
 852         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
 853         MCDI_POPULATE_DWORD_2(inbuf, INIT_TXQ_IN_FLAGS,
 854                               INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
 855                               INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
 856         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
 857         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
 858
 859         dma_addr = tx_queue->txd.buf.dma_addr;
 860
 861         netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
 862                   tx_queue->queue, entries, (u64)dma_addr);
 863
 864         for (i = 0; i < entries; ++i) {
 865                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
 866                 dma_addr += EFX_BUF_SIZE;
 867         }
 868
 869         inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
 870
 871         rc = efx_mcdi_rpc(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
 872                           outbuf, sizeof(outbuf), &outlen);
 873         if (rc)
 874                 goto fail;
 875
 876         /* A previous user of this TX queue might have set us up the
 877          * bomb by writing a descriptor to the TX push collector but
 878          * not the doorbell.  (Each collector belongs to a port, not a
 879          * queue or function, so cannot easily be reset.)  We must
 880          * attempt to push a no-op descriptor in its place.
 881          */
 882         tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
 883         tx_queue->insert_count = 1;
 884         txd = efx_tx_desc(tx_queue, 0);
 885         EFX_POPULATE_QWORD_4(*txd,
 886                              ESF_DZ_TX_DESC_IS_OPT, true,
 887                              ESF_DZ_TX_OPTION_TYPE,
 888                              ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
 889                              ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
 890                              ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
 891         tx_queue->write_count = 1;
 892         wmb();
 893         efx_ef10_push_tx_desc(tx_queue, txd);
 894
 895         return;
 896
 897 fail:
 898         WARN_ON(true);
 899         netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
 900 }
 901
 902 static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
 903 {
 904         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
 905         MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_TXQ_OUT_LEN);
 906         struct efx_nic *efx = tx_queue->efx;
 907         size_t outlen;
 908         int rc;
 909
 910         MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
 911                        tx_queue->queue);
 912
 913         rc = efx_mcdi_rpc(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
 914                           outbuf, sizeof(outbuf), &outlen);
 915
 916         if (rc && rc != -EALREADY)
 917                 goto fail;
 918
 919         return;
 920
 921 fail:
 922         netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
 923 }
 924
 925 static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
 926 {
 927         efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
 928 }
 929
 930 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
 931 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
 932 {
 933         unsigned int write_ptr;
 934         efx_dword_t reg;
 935
 936         write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
 937         EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
 938         efx_writed_page(tx_queue->efx, &reg,
 939                         ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
 940 }
 941
 942 static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
 943 {
 944         unsigned int old_write_count = tx_queue->write_count;
 945         struct efx_tx_buffer *buffer;
 946         unsigned int write_ptr;
 947         efx_qword_t *txd;
 948
 949         BUG_ON(tx_queue->write_count == tx_queue->insert_count);
 950
 951         do {
 952                 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
 953                 buffer = &tx_queue->buffer[write_ptr];
 954                 txd = efx_tx_desc(tx_queue, write_ptr);
 955                 ++tx_queue->write_count;
 956
 957                 /* Create TX descriptor ring entry */
 958                 if (buffer->flags & EFX_TX_BUF_OPTION) {
 959                         *txd = buffer->option;
 960                 } else {
 961                         BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
 962                         EFX_POPULATE_QWORD_3(
 963                                 *txd,
 964                                 ESF_DZ_TX_KER_CONT,
 965                                 buffer->flags & EFX_TX_BUF_CONT,
 966                                 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
 967                                 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
 968                 }
 969         } while (tx_queue->write_count != tx_queue->insert_count);
 970
 971         wmb(); /* Ensure descriptors are written before they are fetched */
 972
 973         if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
 974                 txd = efx_tx_desc(tx_queue,
 975                                   old_write_count & tx_queue->ptr_mask);
 976                 efx_ef10_push_tx_desc(tx_queue, txd);
 977                 ++tx_queue->pushes;
 978         } else {
 979                 efx_ef10_notify_tx_desc(tx_queue);
 980         }
 981 }
 982
 983 static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context)
 984 {
 985         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
 986         MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
 987         size_t outlen;
 988         int rc;
 989
 990         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
 991                        EVB_PORT_ID_ASSIGNED);
 992         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE,
 993                        MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE);
 994         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES,
 995                        EFX_MAX_CHANNELS);
 996
 997         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
 998                 outbuf, sizeof(outbuf), &outlen);
 999         if (rc != 0)
1000                 return rc;
1001
1002         if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
1003                 return -EIO;
1004
1005         *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
1006
1007         return 0;
1008 }
1009
1010 static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
1011 {
1012         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
1013         int rc;
1014
1015         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
1016                        context);
1017
1018         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
1019                             NULL, 0, NULL);
1020         WARN_ON(rc != 0);
1021 }
1022
1023 static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context)
1024 {
1025         MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
1026         MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
1027         int i, rc;
1028
1029         MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
1030                        context);
1031         BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
1032                      MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
1033
1034         for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
1035                 MCDI_PTR(tablebuf,
1036                          RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
1037                                 (u8) efx->rx_indir_table[i];
1038
1039         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
1040                           sizeof(tablebuf), NULL, 0, NULL);
1041         if (rc != 0)
1042                 return rc;
1043
1044         MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
1045                        context);
1046         BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
1047                      MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
1048         for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
1049                 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] =
1050                         efx->rx_hash_key[i];
1051
1052         return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
1053                             sizeof(keybuf), NULL, 0, NULL);
1054 }
1055
1056 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
1057 {
1058         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1059
1060         if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
1061                 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
1062         nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
1063 }
1064
1065 static void efx_ef10_rx_push_indir_table(struct efx_nic *efx)
1066 {
1067         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1068         int rc;
1069
1070         netif_dbg(efx, drv, efx->net_dev, "pushing RX indirection table\n");
1071
1072         if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID) {
1073                 rc = efx_ef10_alloc_rss_context(efx, &nic_data->rx_rss_context);
1074                 if (rc != 0)
1075                         goto fail;
1076         }
1077
1078         rc = efx_ef10_populate_rss_table(efx, nic_data->rx_rss_context);
1079         if (rc != 0)
1080                 goto fail;
1081
1082         return;
1083
1084 fail:
1085         netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
1086 }
1087
1088 static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
1089 {
1090         return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
1091                                     (rx_queue->ptr_mask + 1) *
1092                                     sizeof(efx_qword_t),
1093                                     GFP_KERNEL);
1094 }
1095
1096 static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
1097 {
1098         MCDI_DECLARE_BUF(inbuf,
1099                          MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
1100                                                 EFX_BUF_SIZE));
1101         MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_RXQ_OUT_LEN);
1102         struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
1103         size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
1104         struct efx_nic *efx = rx_queue->efx;
1105         size_t inlen, outlen;
1106         dma_addr_t dma_addr;
1107         int rc;
1108         int i;
1109
1110         rx_queue->scatter_n = 0;
1111         rx_queue->scatter_len = 0;
1112
1113         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
1114         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
1115         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
1116         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
1117                        efx_rx_queue_index(rx_queue));
1118         MCDI_POPULATE_DWORD_1(inbuf, INIT_RXQ_IN_FLAGS,
1119                               INIT_RXQ_IN_FLAG_PREFIX, 1);
1120         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
1121         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1122
1123         dma_addr = rx_queue->rxd.buf.dma_addr;
1124
1125         netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
1126                   efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
1127
1128         for (i = 0; i < entries; ++i) {
1129                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
1130                 dma_addr += EFX_BUF_SIZE;
1131         }
1132
1133         inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
1134
1135         rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
1136                           outbuf, sizeof(outbuf), &outlen);
1137         if (rc)
1138                 goto fail;
1139
1140         return;
1141
1142 fail:
1143         WARN_ON(true);
1144         netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
1145 }
1146
1147 static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
1148 {
1149         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
1150         MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_RXQ_OUT_LEN);
1151         struct efx_nic *efx = rx_queue->efx;
1152         size_t outlen;
1153         int rc;
1154
1155         MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
1156                        efx_rx_queue_index(rx_queue));
1157
1158         rc = efx_mcdi_rpc(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
1159                           outbuf, sizeof(outbuf), &outlen);
1160
1161         if (rc && rc != -EALREADY)
1162                 goto fail;
1163
1164         return;
1165
1166 fail:
1167         netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
1168 }
1169
1170 static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
1171 {
1172         efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
1173 }
1174
1175 /* This creates an entry in the RX descriptor queue */
1176 static inline void
1177 efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
1178 {
1179         struct efx_rx_buffer *rx_buf;
1180         efx_qword_t *rxd;
1181
1182         rxd = efx_rx_desc(rx_queue, index);
1183         rx_buf = efx_rx_buffer(rx_queue, index);
1184         EFX_POPULATE_QWORD_2(*rxd,
1185                              ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
1186                              ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
1187 }
1188
1189 static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
1190 {
1191         struct efx_nic *efx = rx_queue->efx;
1192         unsigned int write_count;
1193         efx_dword_t reg;
1194
1195         /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
1196         write_count = rx_queue->added_count & ~7;
1197         if (rx_queue->notified_count == write_count)
1198                 return;
1199
1200         do
1201                 efx_ef10_build_rx_desc(
1202                         rx_queue,
1203                         rx_queue->notified_count & rx_queue->ptr_mask);
1204         while (++rx_queue->notified_count != write_count);
1205
1206         wmb();
1207         EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
1208                              write_count & rx_queue->ptr_mask);
1209         efx_writed_page(efx, &reg, ER_DZ_RX_DESC_UPD,
1210                         efx_rx_queue_index(rx_queue));
1211 }
1212
1213 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
1214
1215 static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
1216 {
1217         struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
1218         MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
1219         efx_qword_t event;
1220
1221         EFX_POPULATE_QWORD_2(event,
1222                              ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
1223                              ESF_DZ_EV_DATA, EFX_EF10_REFILL);
1224
1225         MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
1226
1227         /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
1228          * already swapped the data to little-endian order.
1229          */
1230         memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
1231                sizeof(efx_qword_t));
1232
1233         efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
1234                            inbuf, sizeof(inbuf), 0,
1235                            efx_ef10_rx_defer_refill_complete, 0);
1236 }
1237
1238 static void
1239 efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
1240                                   int rc, efx_dword_t *outbuf,
1241                                   size_t outlen_actual)
1242 {
1243         /* nothing to do */
1244 }
1245
1246 static int efx_ef10_ev_probe(struct efx_channel *channel)
1247 {
1248         return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
1249                                     (channel->eventq_mask + 1) *
1250                                     sizeof(efx_qword_t),
1251                                     GFP_KERNEL);
1252 }
1253
1254 static int efx_ef10_ev_init(struct efx_channel *channel)
1255 {
1256         MCDI_DECLARE_BUF(inbuf,
1257                          MC_CMD_INIT_EVQ_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
1258                                                 EFX_BUF_SIZE));
1259         MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_OUT_LEN);
1260         size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
1261         struct efx_nic *efx = channel->efx;
1262         struct efx_ef10_nic_data *nic_data;
1263         bool supports_rx_merge;
1264         size_t inlen, outlen;
1265         dma_addr_t dma_addr;
1266         int rc;
1267         int i;
1268
1269         nic_data = efx->nic_data;
1270         supports_rx_merge =
1271                 !!(nic_data->datapath_caps &
1272                    1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
1273
1274         /* Fill event queue with all ones (i.e. empty events) */
1275         memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
1276
1277         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
1278         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
1279         /* INIT_EVQ expects index in vector table, not absolute */
1280         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
1281         MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
1282                               INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
1283                               INIT_EVQ_IN_FLAG_RX_MERGE, 1,
1284                               INIT_EVQ_IN_FLAG_TX_MERGE, 1,
1285                               INIT_EVQ_IN_FLAG_CUT_THRU, !supports_rx_merge);
1286         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
1287                        MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
1288         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
1289         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
1290         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
1291                        MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
1292         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
1293
1294         dma_addr = channel->eventq.buf.dma_addr;
1295         for (i = 0; i < entries; ++i) {
1296                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
1297                 dma_addr += EFX_BUF_SIZE;
1298         }
1299
1300         inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
1301
1302         rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
1303                           outbuf, sizeof(outbuf), &outlen);
1304         if (rc)
1305                 goto fail;
1306
1307         /* IRQ return is ignored */
1308
1309         return 0;
1310
1311 fail:
1312         netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
1313         return rc;
1314 }
1315
1316 static void efx_ef10_ev_fini(struct efx_channel *channel)
1317 {
1318         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
1319         MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_EVQ_OUT_LEN);
1320         struct efx_nic *efx = channel->efx;
1321         size_t outlen;
1322         int rc;
1323
1324         MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
1325
1326         rc = efx_mcdi_rpc(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
1327                           outbuf, sizeof(outbuf), &outlen);
1328
1329         if (rc && rc != -EALREADY)
1330                 goto fail;
1331
1332         return;
1333
1334 fail:
1335         netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
1336 }
1337
1338 static void efx_ef10_ev_remove(struct efx_channel *channel)
1339 {
1340         efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
1341 }
1342
1343 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
1344                                            unsigned int rx_queue_label)
1345 {
1346         struct efx_nic *efx = rx_queue->efx;
1347
1348         netif_info(efx, hw, efx->net_dev,
1349                    "rx event arrived on queue %d labeled as queue %u\n",
1350                    efx_rx_queue_index(rx_queue), rx_queue_label);
1351
1352         efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1353 }
1354
1355 static void
1356 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
1357                              unsigned int actual, unsigned int expected)
1358 {
1359         unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
1360         struct efx_nic *efx = rx_queue->efx;
1361
1362         netif_info(efx, hw, efx->net_dev,
1363                    "dropped %d events (index=%d expected=%d)\n",
1364                    dropped, actual, expected);
1365
1366         efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1367 }
1368
1369 /* partially received RX was aborted. clean up. */
1370 static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
1371 {
1372         unsigned int rx_desc_ptr;
1373
1374         WARN_ON(rx_queue->scatter_n == 0);
1375
1376         netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
1377                   "scattered RX aborted (dropping %u buffers)\n",
1378                   rx_queue->scatter_n);
1379
1380         rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
1381
1382         efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
1383                       0, EFX_RX_PKT_DISCARD);
1384
1385         rx_queue->removed_count += rx_queue->scatter_n;
1386         rx_queue->scatter_n = 0;
1387         rx_queue->scatter_len = 0;
1388         ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
1389 }
1390
1391 static int efx_ef10_handle_rx_event(struct efx_channel *channel,
1392                                     const efx_qword_t *event)
1393 {
1394         unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class;
1395         unsigned int n_descs, n_packets, i;
1396         struct efx_nic *efx = channel->efx;
1397         struct efx_rx_queue *rx_queue;
1398         bool rx_cont;
1399         u16 flags = 0;
1400
1401         if (unlikely(ACCESS_ONCE(efx->reset_pending)))
1402                 return 0;
1403
1404         /* Basic packet information */
1405         rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
1406         next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
1407         rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
1408         rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS);
1409         rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
1410
1411         WARN_ON(EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT));
1412
1413         rx_queue = efx_channel_get_rx_queue(channel);
1414
1415         if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
1416                 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
1417
1418         n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
1419                    ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
1420
1421         if (n_descs != rx_queue->scatter_n + 1) {
1422                 /* detect rx abort */
1423                 if (unlikely(n_descs == rx_queue->scatter_n)) {
1424                         WARN_ON(rx_bytes != 0);
1425                         efx_ef10_handle_rx_abort(rx_queue);
1426                         return 0;
1427                 }
1428
1429                 if (unlikely(rx_queue->scatter_n != 0)) {
1430                         /* Scattered packet completions cannot be
1431                          * merged, so something has gone wrong.
1432                          */
1433                         efx_ef10_handle_rx_bad_lbits(
1434                                 rx_queue, next_ptr_lbits,
1435                                 (rx_queue->removed_count +
1436                                  rx_queue->scatter_n + 1) &
1437                                 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
1438                         return 0;
1439                 }
1440
1441                 /* Merged completion for multiple non-scattered packets */
1442                 rx_queue->scatter_n = 1;
1443                 rx_queue->scatter_len = 0;
1444                 n_packets = n_descs;
1445                 ++channel->n_rx_merge_events;
1446                 channel->n_rx_merge_packets += n_packets;
1447                 flags |= EFX_RX_PKT_PREFIX_LEN;
1448         } else {
1449                 ++rx_queue->scatter_n;
1450                 rx_queue->scatter_len += rx_bytes;
1451                 if (rx_cont)
1452                         return 0;
1453                 n_packets = 1;
1454         }
1455
1456         if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)))
1457                 flags |= EFX_RX_PKT_DISCARD;
1458
1459         if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) {
1460                 channel->n_rx_ip_hdr_chksum_err += n_packets;
1461         } else if (unlikely(EFX_QWORD_FIELD(*event,
1462                                             ESF_DZ_RX_TCPUDP_CKSUM_ERR))) {
1463                 channel->n_rx_tcp_udp_chksum_err += n_packets;
1464         } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
1465                    rx_l4_class == ESE_DZ_L4_CLASS_UDP) {
1466                 flags |= EFX_RX_PKT_CSUMMED;
1467         }
1468
1469         if (rx_l4_class == ESE_DZ_L4_CLASS_TCP)
1470                 flags |= EFX_RX_PKT_TCP;
1471
1472         channel->irq_mod_score += 2 * n_packets;
1473
1474         /* Handle received packet(s) */
1475         for (i = 0; i < n_packets; i++) {
1476                 efx_rx_packet(rx_queue,
1477                               rx_queue->removed_count & rx_queue->ptr_mask,
1478                               rx_queue->scatter_n, rx_queue->scatter_len,
1479                               flags);
1480                 rx_queue->removed_count += rx_queue->scatter_n;
1481         }
1482
1483         rx_queue->scatter_n = 0;
1484         rx_queue->scatter_len = 0;
1485
1486         return n_packets;
1487 }
1488
1489 static int
1490 efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
1491 {
1492         struct efx_nic *efx = channel->efx;
1493         struct efx_tx_queue *tx_queue;
1494         unsigned int tx_ev_desc_ptr;
1495         unsigned int tx_ev_q_label;
1496         int tx_descs = 0;
1497
1498         if (unlikely(ACCESS_ONCE(efx->reset_pending)))
1499                 return 0;
1500
1501         if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
1502                 return 0;
1503
1504         /* Transmit completion */
1505         tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
1506         tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
1507         tx_queue = efx_channel_get_tx_queue(channel,
1508                                             tx_ev_q_label % EFX_TXQ_TYPES);
1509         tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
1510                     tx_queue->ptr_mask);
1511         efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
1512
1513         return tx_descs;
1514 }
1515
1516 static void
1517 efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
1518 {
1519         struct efx_nic *efx = channel->efx;
1520         int subcode;
1521
1522         subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
1523
1524         switch (subcode) {
1525         case ESE_DZ_DRV_TIMER_EV:
1526         case ESE_DZ_DRV_WAKE_UP_EV:
1527                 break;
1528         case ESE_DZ_DRV_START_UP_EV:
1529                 /* event queue init complete. ok. */
1530                 break;
1531         default:
1532                 netif_err(efx, hw, efx->net_dev,
1533                           "channel %d unknown driver event type %d"
1534                           " (data " EFX_QWORD_FMT ")\n",
1535                           channel->channel, subcode,
1536                           EFX_QWORD_VAL(*event));
1537
1538         }
1539 }
1540
1541 static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
1542                                                    efx_qword_t *event)
1543 {
1544         struct efx_nic *efx = channel->efx;
1545         u32 subcode;
1546
1547         subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
1548
1549         switch (subcode) {
1550         case EFX_EF10_TEST:
1551                 channel->event_test_cpu = raw_smp_processor_id();
1552                 break;
1553         case EFX_EF10_REFILL:
1554                 /* The queue must be empty, so we won't receive any rx
1555                  * events, so efx_process_channel() won't refill the
1556                  * queue. Refill it here
1557                  */
1558                 efx_fast_push_rx_descriptors(&channel->rx_queue);
1559                 break;
1560         default:
1561                 netif_err(efx, hw, efx->net_dev,
1562                           "channel %d unknown driver event type %u"
1563                           " (data " EFX_QWORD_FMT ")\n",
1564                           channel->channel, (unsigned) subcode,
1565                           EFX_QWORD_VAL(*event));
1566         }
1567 }
1568
1569 static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
1570 {
1571         struct efx_nic *efx = channel->efx;
1572         efx_qword_t event, *p_event;
1573         unsigned int read_ptr;
1574         int ev_code;
1575         int tx_descs = 0;
1576         int spent = 0;
1577
1578         read_ptr = channel->eventq_read_ptr;
1579
1580         for (;;) {
1581                 p_event = efx_event(channel, read_ptr);
1582                 event = *p_event;
1583
1584                 if (!efx_event_present(&event))
1585                         break;
1586
1587                 EFX_SET_QWORD(*p_event);
1588
1589                 ++read_ptr;
1590
1591                 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
1592
1593                 netif_vdbg(efx, drv, efx->net_dev,
1594                            "processing event on %d " EFX_QWORD_FMT "\n",
1595                            channel->channel, EFX_QWORD_VAL(event));
1596
1597                 switch (ev_code) {
1598                 case ESE_DZ_EV_CODE_MCDI_EV:
1599                         efx_mcdi_process_event(channel, &event);
1600                         break;
1601                 case ESE_DZ_EV_CODE_RX_EV:
1602                         spent += efx_ef10_handle_rx_event(channel, &event);
1603                         if (spent >= quota) {
1604                                 /* XXX can we split a merged event to
1605                                  * avoid going over-quota?
1606                                  */
1607                                 spent = quota;
1608                                 goto out;
1609                         }
1610                         break;
1611                 case ESE_DZ_EV_CODE_TX_EV:
1612                         tx_descs += efx_ef10_handle_tx_event(channel, &event);
1613                         if (tx_descs > efx->txq_entries) {
1614                                 spent = quota;
1615                                 goto out;
1616                         } else if (++spent == quota) {
1617                                 goto out;
1618                         }
1619                         break;
1620                 case ESE_DZ_EV_CODE_DRIVER_EV:
1621                         efx_ef10_handle_driver_event(channel, &event);
1622                         if (++spent == quota)
1623                                 goto out;
1624                         break;
1625                 case EFX_EF10_DRVGEN_EV:
1626                         efx_ef10_handle_driver_generated_event(channel, &event);
1627                         break;
1628                 default:
1629                         netif_err(efx, hw, efx->net_dev,
1630                                   "channel %d unknown event type %d"
1631                                   " (data " EFX_QWORD_FMT ")\n",
1632                                   channel->channel, ev_code,
1633                                   EFX_QWORD_VAL(event));
1634                 }
1635         }
1636
1637 out:
1638         channel->eventq_read_ptr = read_ptr;
1639         return spent;
1640 }
1641
1642 static void efx_ef10_ev_read_ack(struct efx_channel *channel)
1643 {
1644         struct efx_nic *efx = channel->efx;
1645         efx_dword_t rptr;
1646
1647         if (EFX_EF10_WORKAROUND_35388(efx)) {
1648                 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
1649                              (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
1650                 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
1651                              (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
1652
1653                 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
1654                                      EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
1655                                      ERF_DD_EVQ_IND_RPTR,
1656                                      (channel->eventq_read_ptr &
1657                                       channel->eventq_mask) >>
1658                                      ERF_DD_EVQ_IND_RPTR_WIDTH);
1659                 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
1660                                 channel->channel);
1661                 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
1662                                      EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
1663                                      ERF_DD_EVQ_IND_RPTR,
1664                                      channel->eventq_read_ptr &
1665                                      ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
1666                 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
1667                                 channel->channel);
1668         } else {
1669                 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
1670                                      channel->eventq_read_ptr &
1671                                      channel->eventq_mask);
1672                 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
1673         }
1674 }
1675
1676 static void efx_ef10_ev_test_generate(struct efx_channel *channel)
1677 {
1678         MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
1679         struct efx_nic *efx = channel->efx;
1680         efx_qword_t event;
1681         int rc;
1682
1683         EFX_POPULATE_QWORD_2(event,
1684                              ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
1685                              ESF_DZ_EV_DATA, EFX_EF10_TEST);
1686
1687         MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
1688
1689         /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
1690          * already swapped the data to little-endian order.
1691          */
1692         memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
1693                sizeof(efx_qword_t));
1694
1695         rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
1696                           NULL, 0, NULL);
1697         if (rc != 0)
1698                 goto fail;
1699
1700         return;
1701
1702 fail:
1703         WARN_ON(true);
1704         netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
1705 }
1706
1707 void efx_ef10_handle_drain_event(struct efx_nic *efx)
1708 {
1709         if (atomic_dec_and_test(&efx->active_queues))
1710                 wake_up(&efx->flush_wq);
1711
1712         WARN_ON(atomic_read(&efx->active_queues) < 0);
1713 }
1714
1715 static int efx_ef10_fini_dmaq(struct efx_nic *efx)
1716 {
1717         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1718         struct efx_channel *channel;
1719         struct efx_tx_queue *tx_queue;
1720         struct efx_rx_queue *rx_queue;
1721         int pending;
1722
1723         /* If the MC has just rebooted, the TX/RX queues will have already been
1724          * torn down, but efx->active_queues needs to be set to zero.
1725          */
1726         if (nic_data->must_realloc_vis) {
1727                 atomic_set(&efx->active_queues, 0);
1728                 return 0;
1729         }
1730
1731         /* Do not attempt to write to the NIC during EEH recovery */
1732         if (efx->state != STATE_RECOVERY) {
1733                 efx_for_each_channel(channel, efx) {
1734                         efx_for_each_channel_rx_queue(rx_queue, channel)
1735                                 efx_ef10_rx_fini(rx_queue);
1736                         efx_for_each_channel_tx_queue(tx_queue, channel)
1737                                 efx_ef10_tx_fini(tx_queue);
1738                 }
1739
1740                 wait_event_timeout(efx->flush_wq,
1741                                    atomic_read(&efx->active_queues) == 0,
1742                                    msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
1743                 pending = atomic_read(&efx->active_queues);
1744                 if (pending) {
1745                         netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
1746                                   pending);
1747                         return -ETIMEDOUT;
1748                 }
1749         }
1750
1751         return 0;
1752 }
1753
1754 static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
1755                                   const struct efx_filter_spec *right)
1756 {
1757         if ((left->match_flags ^ right->match_flags) |
1758             ((left->flags ^ right->flags) &
1759              (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
1760                 return false;
1761
1762         return memcmp(&left->outer_vid, &right->outer_vid,
1763                       sizeof(struct efx_filter_spec) -
1764                       offsetof(struct efx_filter_spec, outer_vid)) == 0;
1765 }
1766
1767 static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
1768 {
1769         BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
1770         return jhash2((const u32 *)&spec->outer_vid,
1771                       (sizeof(struct efx_filter_spec) -
1772                        offsetof(struct efx_filter_spec, outer_vid)) / 4,
1773                       0);
1774         /* XXX should we randomise the initval? */
1775 }
1776
1777 /* Decide whether a filter should be exclusive or else should allow
1778  * delivery to additional recipients.  Currently we decide that
1779  * filters for specific local unicast MAC and IP addresses are
1780  * exclusive.
1781  */
1782 static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
1783 {
1784         if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
1785             !is_multicast_ether_addr(spec->loc_mac))
1786                 return true;
1787
1788         if ((spec->match_flags &
1789              (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
1790             (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
1791                 if (spec->ether_type == htons(ETH_P_IP) &&
1792                     !ipv4_is_multicast(spec->loc_host[0]))
1793                         return true;
1794                 if (spec->ether_type == htons(ETH_P_IPV6) &&
1795                     ((const u8 *)spec->loc_host)[0] != 0xff)
1796                         return true;
1797         }
1798
1799         return false;
1800 }
1801
1802 static struct efx_filter_spec *
1803 efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
1804                            unsigned int filter_idx)
1805 {
1806         return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
1807                                           ~EFX_EF10_FILTER_FLAGS);
1808 }
1809
1810 static unsigned int
1811 efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
1812                            unsigned int filter_idx)
1813 {
1814         return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
1815 }
1816
1817 static void
1818 efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
1819                           unsigned int filter_idx,
1820                           const struct efx_filter_spec *spec,
1821                           unsigned int flags)
1822 {
1823         table->entry[filter_idx].spec = (unsigned long)spec | flags;
1824 }
1825
1826 static void efx_ef10_filter_push_prep(struct efx_nic *efx,
1827                                       const struct efx_filter_spec *spec,
1828                                       efx_dword_t *inbuf, u64 handle,
1829                                       bool replacing)
1830 {
1831         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1832
1833         memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN);
1834
1835         if (replacing) {
1836                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
1837                                MC_CMD_FILTER_OP_IN_OP_REPLACE);
1838                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
1839         } else {
1840                 u32 match_fields = 0;
1841
1842                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
1843                                efx_ef10_filter_is_exclusive(spec) ?
1844                                MC_CMD_FILTER_OP_IN_OP_INSERT :
1845                                MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
1846
1847                 /* Convert match flags and values.  Unlike almost
1848                  * everything else in MCDI, these fields are in
1849                  * network byte order.
1850                  */
1851                 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
1852                         match_fields |=
1853                                 is_multicast_ether_addr(spec->loc_mac) ?
1854                                 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN :
1855                                 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
1856 #define COPY_FIELD(gen_flag, gen_field, mcdi_field)                          \
1857                 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) {     \
1858                         match_fields |=                                      \
1859                                 1 << MC_CMD_FILTER_OP_IN_MATCH_ ##           \
1860                                 mcdi_field ## _LBN;                          \
1861                         BUILD_BUG_ON(                                        \
1862                                 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
1863                                 sizeof(spec->gen_field));                    \
1864                         memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
1865                                &spec->gen_field, sizeof(spec->gen_field));   \
1866                 }
1867                 COPY_FIELD(REM_HOST, rem_host, SRC_IP);
1868                 COPY_FIELD(LOC_HOST, loc_host, DST_IP);
1869                 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
1870                 COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
1871                 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
1872                 COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
1873                 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
1874                 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
1875                 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
1876                 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
1877 #undef COPY_FIELD
1878                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
1879                                match_fields);
1880         }
1881
1882         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1883         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
1884                        spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
1885                        MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
1886                        MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
1887         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
1888                        MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
1889         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE, spec->dmaq_id);
1890         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
1891                        (spec->flags & EFX_FILTER_FLAG_RX_RSS) ?
1892                        MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
1893                        MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
1894         if (spec->flags & EFX_FILTER_FLAG_RX_RSS)
1895                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
1896                                spec->rss_context !=
1897                                EFX_FILTER_RSS_CONTEXT_DEFAULT ?
1898                                spec->rss_context : nic_data->rx_rss_context);
1899 }
1900
1901 static int efx_ef10_filter_push(struct efx_nic *efx,
1902                                 const struct efx_filter_spec *spec,
1903                                 u64 *handle, bool replacing)
1904 {
1905         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
1906         MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN);
1907         int rc;
1908
1909         efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
1910         rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
1911                           outbuf, sizeof(outbuf), NULL);
1912         if (rc == 0)
1913                 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
1914         return rc;
1915 }
1916
1917 static int efx_ef10_filter_rx_match_pri(struct efx_ef10_filter_table *table,
1918                                         enum efx_filter_match_flags match_flags)
1919 {
1920         unsigned int match_pri;
1921
1922         for (match_pri = 0;
1923              match_pri < table->rx_match_count;
1924              match_pri++)
1925                 if (table->rx_match_flags[match_pri] == match_flags)
1926                         return match_pri;
1927
1928         return -EPROTONOSUPPORT;
1929 }
1930
1931 static s32 efx_ef10_filter_insert(struct efx_nic *efx,
1932                                   struct efx_filter_spec *spec,
1933                                   bool replace_equal)
1934 {
1935         struct efx_ef10_filter_table *table = efx->filter_state;
1936         DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
1937         struct efx_filter_spec *saved_spec;
1938         unsigned int match_pri, hash;
1939         unsigned int priv_flags;
1940         bool replacing = false;
1941         int ins_index = -1;
1942         DEFINE_WAIT(wait);
1943         bool is_mc_recip;
1944         s32 rc;
1945
1946         /* For now, only support RX filters */
1947         if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
1948             EFX_FILTER_FLAG_RX)
1949                 return -EINVAL;
1950
1951         rc = efx_ef10_filter_rx_match_pri(table, spec->match_flags);
1952         if (rc < 0)
1953                 return rc;
1954         match_pri = rc;
1955
1956         hash = efx_ef10_filter_hash(spec);
1957         is_mc_recip = efx_filter_is_mc_recipient(spec);
1958         if (is_mc_recip)
1959                 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
1960
1961         /* Find any existing filters with the same match tuple or
1962          * else a free slot to insert at.  If any of them are busy,
1963          * we have to wait and retry.
1964          */
1965         for (;;) {
1966                 unsigned int depth = 1;
1967                 unsigned int i;
1968
1969                 spin_lock_bh(&efx->filter_lock);
1970
1971                 for (;;) {
1972                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
1973                         saved_spec = efx_ef10_filter_entry_spec(table, i);
1974
1975                         if (!saved_spec) {
1976                                 if (ins_index < 0)
1977                                         ins_index = i;
1978                         } else if (efx_ef10_filter_equal(spec, saved_spec)) {
1979                                 if (table->entry[i].spec &
1980                                     EFX_EF10_FILTER_FLAG_BUSY)
1981                                         break;
1982                                 if (spec->priority < saved_spec->priority &&
1983                                     !(saved_spec->priority ==
1984                                       EFX_FILTER_PRI_REQUIRED &&
1985                                       saved_spec->flags &
1986                                       EFX_FILTER_FLAG_RX_STACK)) {
1987                                         rc = -EPERM;
1988                                         goto out_unlock;
1989                                 }
1990                                 if (!is_mc_recip) {
1991                                         /* This is the only one */
1992                                         if (spec->priority ==
1993                                             saved_spec->priority &&
1994                                             !replace_equal) {
1995                                                 rc = -EEXIST;
1996                                                 goto out_unlock;
1997                                         }
1998                                         ins_index = i;
1999                                         goto found;
2000                                 } else if (spec->priority >
2001                                            saved_spec->priority ||
2002                                            (spec->priority ==
2003                                             saved_spec->priority &&
2004                                             replace_equal)) {
2005                                         if (ins_index < 0)
2006                                                 ins_index = i;
2007                                         else
2008                                                 __set_bit(depth, mc_rem_map);
2009                                 }
2010                         }
2011
2012                         /* Once we reach the maximum search depth, use
2013                          * the first suitable slot or return -EBUSY if
2014                          * there was none
2015                          */
2016                         if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
2017                                 if (ins_index < 0) {
2018                                         rc = -EBUSY;
2019                                         goto out_unlock;
2020                                 }
2021                                 goto found;
2022                         }
2023
2024                         ++depth;
2025                 }
2026
2027                 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
2028                 spin_unlock_bh(&efx->filter_lock);
2029                 schedule();
2030         }
2031
2032 found:
2033         /* Create a software table entry if necessary, and mark it
2034          * busy.  We might yet fail to insert, but any attempt to
2035          * insert a conflicting filter while we're waiting for the
2036          * firmware must find the busy entry.
2037          */
2038         saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
2039         if (saved_spec) {
2040                 if (spec->flags & EFX_FILTER_FLAG_RX_STACK) {
2041                         /* Just make sure it won't be removed */
2042                         saved_spec->flags |= EFX_FILTER_FLAG_RX_STACK;
2043                         table->entry[ins_index].spec &=
2044                                 ~EFX_EF10_FILTER_FLAG_STACK_OLD;
2045                         rc = ins_index;
2046                         goto out_unlock;
2047                 }
2048                 replacing = true;
2049                 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
2050         } else {
2051                 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
2052                 if (!saved_spec) {
2053                         rc = -ENOMEM;
2054                         goto out_unlock;
2055                 }
2056                 *saved_spec = *spec;
2057                 priv_flags = 0;
2058         }
2059         efx_ef10_filter_set_entry(table, ins_index, saved_spec,
2060                                   priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
2061
2062         /* Mark lower-priority multicast recipients busy prior to removal */
2063         if (is_mc_recip) {
2064                 unsigned int depth, i;
2065
2066                 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
2067                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2068                         if (test_bit(depth, mc_rem_map))
2069                                 table->entry[i].spec |=
2070                                         EFX_EF10_FILTER_FLAG_BUSY;
2071                 }
2072         }
2073
2074         spin_unlock_bh(&efx->filter_lock);
2075
2076         rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
2077                                   replacing);
2078
2079         /* Finalise the software table entry */
2080         spin_lock_bh(&efx->filter_lock);
2081         if (rc == 0) {
2082                 if (replacing) {
2083                         /* Update the fields that may differ */
2084                         saved_spec->priority = spec->priority;
2085                         saved_spec->flags &= EFX_FILTER_FLAG_RX_STACK;
2086                         saved_spec->flags |= spec->flags;
2087                         saved_spec->rss_context = spec->rss_context;
2088                         saved_spec->dmaq_id = spec->dmaq_id;
2089                 }
2090         } else if (!replacing) {
2091                 kfree(saved_spec);
2092                 saved_spec = NULL;
2093         }
2094         efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
2095
2096         /* Remove and finalise entries for lower-priority multicast
2097          * recipients
2098          */
2099         if (is_mc_recip) {
2100                 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2101                 unsigned int depth, i;
2102
2103                 memset(inbuf, 0, sizeof(inbuf));
2104
2105                 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
2106                         if (!test_bit(depth, mc_rem_map))
2107                                 continue;
2108
2109                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2110                         saved_spec = efx_ef10_filter_entry_spec(table, i);
2111                         priv_flags = efx_ef10_filter_entry_flags(table, i);
2112
2113                         if (rc == 0) {
2114                                 spin_unlock_bh(&efx->filter_lock);
2115                                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2116                                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
2117                                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
2118                                                table->entry[i].handle);
2119                                 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
2120                                                   inbuf, sizeof(inbuf),
2121                                                   NULL, 0, NULL);
2122                                 spin_lock_bh(&efx->filter_lock);
2123                         }
2124
2125                         if (rc == 0) {
2126                                 kfree(saved_spec);
2127                                 saved_spec = NULL;
2128                                 priv_flags = 0;
2129                         } else {
2130                                 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
2131                         }
2132                         efx_ef10_filter_set_entry(table, i, saved_spec,
2133                                                   priv_flags);
2134                 }
2135         }
2136
2137         /* If successful, return the inserted filter ID */
2138         if (rc == 0)
2139                 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index;
2140
2141         wake_up_all(&table->waitq);
2142 out_unlock:
2143         spin_unlock_bh(&efx->filter_lock);
2144         finish_wait(&table->waitq, &wait);
2145         return rc;
2146 }
2147
2148 void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
2149 {
2150         /* no need to do anything here on EF10 */
2151 }
2152
2153 /* Remove a filter.
2154  * If !stack_requested, remove by ID
2155  * If stack_requested, remove by index
2156  * Filter ID may come from userland and must be range-checked.
2157  */
2158 static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
2159                                            enum efx_filter_priority priority,
2160                                            u32 filter_id, bool stack_requested)
2161 {
2162         unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
2163         struct efx_ef10_filter_table *table = efx->filter_state;
2164         MCDI_DECLARE_BUF(inbuf,
2165                          MC_CMD_FILTER_OP_IN_HANDLE_OFST +
2166                          MC_CMD_FILTER_OP_IN_HANDLE_LEN);
2167         struct efx_filter_spec *spec;
2168         DEFINE_WAIT(wait);
2169         int rc;
2170
2171         /* Find the software table entry and mark it busy.  Don't
2172          * remove it yet; any attempt to update while we're waiting
2173          * for the firmware must find the busy entry.
2174          */
2175         for (;;) {
2176                 spin_lock_bh(&efx->filter_lock);
2177                 if (!(table->entry[filter_idx].spec &
2178                       EFX_EF10_FILTER_FLAG_BUSY))
2179                         break;
2180                 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
2181                 spin_unlock_bh(&efx->filter_lock);
2182                 schedule();
2183         }
2184         spec = efx_ef10_filter_entry_spec(table, filter_idx);
2185         if (!spec || spec->priority > priority ||
2186             (!stack_requested &&
2187              efx_ef10_filter_rx_match_pri(table, spec->match_flags) !=
2188              filter_id / HUNT_FILTER_TBL_ROWS)) {
2189                 rc = -ENOENT;
2190                 goto out_unlock;
2191         }
2192         table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
2193         spin_unlock_bh(&efx->filter_lock);
2194
2195         if (spec->flags & EFX_FILTER_FLAG_RX_STACK && !stack_requested) {
2196                 /* Reset steering of a stack-owned filter */
2197
2198                 struct efx_filter_spec new_spec = *spec;
2199
2200                 new_spec.priority = EFX_FILTER_PRI_REQUIRED;
2201                 new_spec.flags = (EFX_FILTER_FLAG_RX |
2202                                   EFX_FILTER_FLAG_RX_RSS |
2203                                   EFX_FILTER_FLAG_RX_STACK);
2204                 new_spec.dmaq_id = 0;
2205                 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
2206                 rc = efx_ef10_filter_push(efx, &new_spec,
2207                                           &table->entry[filter_idx].handle,
2208                                           true);
2209
2210                 spin_lock_bh(&efx->filter_lock);
2211                 if (rc == 0)
2212                         *spec = new_spec;
2213         } else {
2214                 /* Really remove the filter */
2215
2216                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2217                                efx_ef10_filter_is_exclusive(spec) ?
2218                                MC_CMD_FILTER_OP_IN_OP_REMOVE :
2219                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
2220                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
2221                                table->entry[filter_idx].handle);
2222                 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
2223                                   inbuf, sizeof(inbuf), NULL, 0, NULL);
2224
2225                 spin_lock_bh(&efx->filter_lock);
2226                 if (rc == 0) {
2227                         kfree(spec);
2228                         efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
2229                 }
2230         }
2231         table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
2232         wake_up_all(&table->waitq);
2233 out_unlock:
2234         spin_unlock_bh(&efx->filter_lock);
2235         finish_wait(&table->waitq, &wait);
2236         return rc;
2237 }
2238
2239 static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
2240                                        enum efx_filter_priority priority,
2241                                        u32 filter_id)
2242 {
2243         return efx_ef10_filter_remove_internal(efx, priority, filter_id, false);
2244 }
2245
2246 static int efx_ef10_filter_get_safe(struct efx_nic *efx,
2247                                     enum efx_filter_priority priority,
2248                                     u32 filter_id, struct efx_filter_spec *spec)
2249 {
2250         unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
2251         struct efx_ef10_filter_table *table = efx->filter_state;
2252         const struct efx_filter_spec *saved_spec;
2253         int rc;
2254
2255         spin_lock_bh(&efx->filter_lock);
2256         saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
2257         if (saved_spec && saved_spec->priority == priority &&
2258             efx_ef10_filter_rx_match_pri(table, saved_spec->match_flags) ==
2259             filter_id / HUNT_FILTER_TBL_ROWS) {
2260                 *spec = *saved_spec;
2261                 rc = 0;
2262         } else {
2263                 rc = -ENOENT;
2264         }
2265         spin_unlock_bh(&efx->filter_lock);
2266         return rc;
2267 }
2268
2269 static void efx_ef10_filter_clear_rx(struct efx_nic *efx,
2270                                      enum efx_filter_priority priority)
2271 {
2272         /* TODO */
2273 }
2274
2275 static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
2276                                          enum efx_filter_priority priority)
2277 {
2278         struct efx_ef10_filter_table *table = efx->filter_state;
2279         unsigned int filter_idx;
2280         s32 count = 0;
2281
2282         spin_lock_bh(&efx->filter_lock);
2283         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
2284                 if (table->entry[filter_idx].spec &&
2285                     efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
2286                     priority)
2287                         ++count;
2288         }
2289         spin_unlock_bh(&efx->filter_lock);
2290         return count;
2291 }
2292
2293 static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
2294 {
2295         struct efx_ef10_filter_table *table = efx->filter_state;
2296
2297         return table->rx_match_count * HUNT_FILTER_TBL_ROWS;
2298 }
2299
2300 static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
2301                                       enum efx_filter_priority priority,
2302                                       u32 *buf, u32 size)
2303 {
2304         struct efx_ef10_filter_table *table = efx->filter_state;
2305         struct efx_filter_spec *spec;
2306         unsigned int filter_idx;
2307         s32 count = 0;
2308
2309         spin_lock_bh(&efx->filter_lock);
2310         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
2311                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
2312                 if (spec && spec->priority == priority) {
2313                         if (count == size) {
2314                                 count = -EMSGSIZE;
2315                                 break;
2316                         }
2317                         buf[count++] = (efx_ef10_filter_rx_match_pri(
2318                                                 table, spec->match_flags) *
2319                                         HUNT_FILTER_TBL_ROWS +
2320                                         filter_idx);
2321                 }
2322         }
2323         spin_unlock_bh(&efx->filter_lock);
2324         return count;
2325 }
2326
2327 #ifdef CONFIG_RFS_ACCEL
2328
2329 static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
2330
2331 static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
2332                                       struct efx_filter_spec *spec)
2333 {
2334         struct efx_ef10_filter_table *table = efx->filter_state;
2335         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2336         struct efx_filter_spec *saved_spec;
2337         unsigned int hash, i, depth = 1;
2338         bool replacing = false;
2339         int ins_index = -1;
2340         u64 cookie;
2341         s32 rc;
2342
2343         /* Must be an RX filter without RSS and not for a multicast
2344          * destination address (RFS only works for connected sockets).
2345          * These restrictions allow us to pass only a tiny amount of
2346          * data through to the completion function.
2347          */
2348         EFX_WARN_ON_PARANOID(spec->flags !=
2349                              (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
2350         EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
2351         EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
2352
2353         hash = efx_ef10_filter_hash(spec);
2354
2355         spin_lock_bh(&efx->filter_lock);
2356
2357         /* Find any existing filter with the same match tuple or else
2358          * a free slot to insert at.  If an existing filter is busy,
2359          * we have to give up.
2360          */
2361         for (;;) {
2362                 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2363                 saved_spec = efx_ef10_filter_entry_spec(table, i);
2364
2365                 if (!saved_spec) {
2366                         if (ins_index < 0)
2367                                 ins_index = i;
2368                 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
2369                         if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
2370                                 rc = -EBUSY;
2371                                 goto fail_unlock;
2372                         }
2373                         EFX_WARN_ON_PARANOID(saved_spec->flags &
2374                                              EFX_FILTER_FLAG_RX_STACK);
2375                         if (spec->priority < saved_spec->priority) {
2376                                 rc = -EPERM;
2377                                 goto fail_unlock;
2378                         }
2379                         ins_index = i;
2380                         break;
2381                 }
2382
2383                 /* Once we reach the maximum search depth, use the
2384                  * first suitable slot or return -EBUSY if there was
2385                  * none
2386                  */
2387                 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
2388                         if (ins_index < 0) {
2389                                 rc = -EBUSY;
2390                                 goto fail_unlock;
2391                         }
2392                         break;
2393                 }
2394
2395                 ++depth;
2396         }
2397
2398         /* Create a software table entry if necessary, and mark it
2399          * busy.  We might yet fail to insert, but any attempt to
2400          * insert a conflicting filter while we're waiting for the
2401          * firmware must find the busy entry.
2402          */
2403         saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
2404         if (saved_spec) {
2405                 replacing = true;
2406         } else {
2407                 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
2408                 if (!saved_spec) {
2409                         rc = -ENOMEM;
2410                         goto fail_unlock;
2411                 }
2412                 *saved_spec = *spec;
2413         }
2414         efx_ef10_filter_set_entry(table, ins_index, saved_spec,
2415                                   EFX_EF10_FILTER_FLAG_BUSY);
2416
2417         spin_unlock_bh(&efx->filter_lock);
2418
2419         /* Pack up the variables needed on completion */
2420         cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
2421
2422         efx_ef10_filter_push_prep(efx, spec, inbuf,
2423                                   table->entry[ins_index].handle, replacing);
2424         efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
2425                            MC_CMD_FILTER_OP_OUT_LEN,
2426                            efx_ef10_filter_rfs_insert_complete, cookie);
2427
2428         return ins_index;
2429
2430 fail_unlock:
2431         spin_unlock_bh(&efx->filter_lock);
2432         return rc;
2433 }
2434
2435 static void
2436 efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
2437                                     int rc, efx_dword_t *outbuf,
2438                                     size_t outlen_actual)
2439 {
2440         struct efx_ef10_filter_table *table = efx->filter_state;
2441         unsigned int ins_index, dmaq_id;
2442         struct efx_filter_spec *spec;
2443         bool replacing;
2444
2445         /* Unpack the cookie */
2446         replacing = cookie >> 31;
2447         ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
2448         dmaq_id = cookie & 0xffff;
2449
2450         spin_lock_bh(&efx->filter_lock);
2451         spec = efx_ef10_filter_entry_spec(table, ins_index);
2452         if (rc == 0) {
2453                 table->entry[ins_index].handle =
2454                         MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
2455                 if (replacing)
2456                         spec->dmaq_id = dmaq_id;
2457         } else if (!replacing) {
2458                 kfree(spec);
2459                 spec = NULL;
2460         }
2461         efx_ef10_filter_set_entry(table, ins_index, spec, 0);
2462         spin_unlock_bh(&efx->filter_lock);
2463
2464         wake_up_all(&table->waitq);
2465 }
2466
2467 static void
2468 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
2469                                     unsigned long filter_idx,
2470                                     int rc, efx_dword_t *outbuf,
2471                                     size_t outlen_actual);
2472
2473 static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
2474                                            unsigned int filter_idx)
2475 {
2476         struct efx_ef10_filter_table *table = efx->filter_state;
2477         struct efx_filter_spec *spec =
2478                 efx_ef10_filter_entry_spec(table, filter_idx);
2479         MCDI_DECLARE_BUF(inbuf,
2480                          MC_CMD_FILTER_OP_IN_HANDLE_OFST +
2481                          MC_CMD_FILTER_OP_IN_HANDLE_LEN);
2482
2483         if (!spec ||
2484             (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
2485             spec->priority != EFX_FILTER_PRI_HINT ||
2486             !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
2487                                  flow_id, filter_idx))
2488                 return false;
2489
2490         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2491                        MC_CMD_FILTER_OP_IN_OP_REMOVE);
2492         MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
2493                        table->entry[filter_idx].handle);
2494         if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
2495                                efx_ef10_filter_rfs_expire_complete, filter_idx))
2496                 return false;
2497
2498         table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
2499         return true;
2500 }
2501
2502 static void
2503 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
2504                                     unsigned long filter_idx,
2505                                     int rc, efx_dword_t *outbuf,
2506                                     size_t outlen_actual)
2507 {
2508         struct efx_ef10_filter_table *table = efx->filter_state;
2509         struct efx_filter_spec *spec =
2510                 efx_ef10_filter_entry_spec(table, filter_idx);
2511
2512         spin_lock_bh(&efx->filter_lock);
2513         if (rc == 0) {
2514                 kfree(spec);
2515                 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
2516         }
2517         table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
2518         wake_up_all(&table->waitq);
2519         spin_unlock_bh(&efx->filter_lock);
2520 }
2521
2522 #endif /* CONFIG_RFS_ACCEL */
2523
2524 static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags)
2525 {
2526         int match_flags = 0;
2527
2528 #define MAP_FLAG(gen_flag, mcdi_field) {                                \
2529                 u32 old_mcdi_flags = mcdi_flags;                        \
2530                 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ##      \
2531                                 mcdi_field ## _LBN);                    \
2532                 if (mcdi_flags != old_mcdi_flags)                       \
2533                         match_flags |= EFX_FILTER_MATCH_ ## gen_flag;   \
2534         }
2535         MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
2536         MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
2537         MAP_FLAG(REM_HOST, SRC_IP);
2538         MAP_FLAG(LOC_HOST, DST_IP);
2539         MAP_FLAG(REM_MAC, SRC_MAC);
2540         MAP_FLAG(REM_PORT, SRC_PORT);
2541         MAP_FLAG(LOC_MAC, DST_MAC);
2542         MAP_FLAG(LOC_PORT, DST_PORT);
2543         MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
2544         MAP_FLAG(INNER_VID, INNER_VLAN);
2545         MAP_FLAG(OUTER_VID, OUTER_VLAN);
2546         MAP_FLAG(IP_PROTO, IP_PROTO);
2547 #undef MAP_FLAG
2548
2549         /* Did we map them all? */
2550         if (mcdi_flags)
2551                 return -EINVAL;
2552
2553         return match_flags;
2554 }
2555
2556 static int efx_ef10_filter_table_probe(struct efx_nic *efx)
2557 {
2558         MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
2559         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
2560         unsigned int pd_match_pri, pd_match_count;
2561         struct efx_ef10_filter_table *table;
2562         size_t outlen;
2563         int rc;
2564
2565         table = kzalloc(sizeof(*table), GFP_KERNEL);
2566         if (!table)
2567                 return -ENOMEM;
2568
2569         /* Find out which RX filter types are supported, and their priorities */
2570         MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
2571                        MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
2572         rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
2573                           inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
2574                           &outlen);
2575         if (rc)
2576                 goto fail;
2577         pd_match_count = MCDI_VAR_ARRAY_LEN(
2578                 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
2579         table->rx_match_count = 0;
2580
2581         for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
2582                 u32 mcdi_flags =
2583                         MCDI_ARRAY_DWORD(
2584                                 outbuf,
2585                                 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
2586                                 pd_match_pri);
2587                 rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags);
2588                 if (rc < 0) {
2589                         netif_dbg(efx, probe, efx->net_dev,
2590                                   "%s: fw flags %#x pri %u not supported in driver\n",
2591                                   __func__, mcdi_flags, pd_match_pri);
2592                 } else {
2593                         netif_dbg(efx, probe, efx->net_dev,
2594                                   "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
2595                                   __func__, mcdi_flags, pd_match_pri,
2596                                   rc, table->rx_match_count);
2597                         table->rx_match_flags[table->rx_match_count++] = rc;
2598                 }
2599         }
2600
2601         table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
2602         if (!table->entry) {
2603                 rc = -ENOMEM;
2604                 goto fail;
2605         }
2606
2607         efx->filter_state = table;
2608         init_waitqueue_head(&table->waitq);
2609         return 0;
2610
2611 fail:
2612         kfree(table);
2613         return rc;
2614 }
2615
2616 static void efx_ef10_filter_table_restore(struct efx_nic *efx)
2617 {
2618         struct efx_ef10_filter_table *table = efx->filter_state;
2619         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2620         struct efx_filter_spec *spec;
2621         unsigned int filter_idx;
2622         bool failed = false;
2623         int rc;
2624
2625         if (!nic_data->must_restore_filters)
2626                 return;
2627
2628         spin_lock_bh(&efx->filter_lock);
2629
2630         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
2631                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
2632                 if (!spec)
2633                         continue;
2634
2635                 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
2636                 spin_unlock_bh(&efx->filter_lock);
2637
2638                 rc = efx_ef10_filter_push(efx, spec,
2639                                           &table->entry[filter_idx].handle,
2640                                           false);
2641                 if (rc)
2642                         failed = true;
2643
2644                 spin_lock_bh(&efx->filter_lock);
2645                 if (rc) {
2646                         kfree(spec);
2647                         efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
2648                 } else {
2649                         table->entry[filter_idx].spec &=
2650                                 ~EFX_EF10_FILTER_FLAG_BUSY;
2651                 }
2652         }
2653
2654         spin_unlock_bh(&efx->filter_lock);
2655
2656         if (failed)
2657                 netif_err(efx, hw, efx->net_dev,
2658                           "unable to restore all filters\n");
2659         else
2660                 nic_data->must_restore_filters = false;
2661 }
2662
2663 static void efx_ef10_filter_table_remove(struct efx_nic *efx)
2664 {
2665         struct efx_ef10_filter_table *table = efx->filter_state;
2666         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2667         struct efx_filter_spec *spec;
2668         unsigned int filter_idx;
2669         int rc;
2670
2671         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
2672                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
2673                 if (!spec)
2674                         continue;
2675
2676                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2677                                efx_ef10_filter_is_exclusive(spec) ?
2678                                MC_CMD_FILTER_OP_IN_OP_REMOVE :
2679                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
2680                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
2681                                table->entry[filter_idx].handle);
2682                 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
2683                                   NULL, 0, NULL);
2684
2685                 WARN_ON(rc != 0);
2686                 kfree(spec);
2687         }
2688
2689         vfree(table->entry);
2690         kfree(table);
2691 }
2692
2693 static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
2694 {
2695         struct efx_ef10_filter_table *table = efx->filter_state;
2696         struct net_device *net_dev = efx->net_dev;
2697         struct efx_filter_spec spec;
2698         bool remove_failed = false;
2699         struct netdev_hw_addr *uc;
2700         struct netdev_hw_addr *mc;
2701         unsigned int filter_idx;
2702         int i, n, rc;
2703
2704         if (!efx_dev_registered(efx))
2705                 return;
2706
2707         /* Mark old filters that may need to be removed */
2708         spin_lock_bh(&efx->filter_lock);
2709         n = table->stack_uc_count < 0 ? 1 : table->stack_uc_count;
2710         for (i = 0; i < n; i++) {
2711                 filter_idx = table->stack_uc_list[i].id % HUNT_FILTER_TBL_ROWS;
2712                 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_STACK_OLD;
2713         }
2714         n = table->stack_mc_count < 0 ? 1 : table->stack_mc_count;
2715         for (i = 0; i < n; i++) {
2716                 filter_idx = table->stack_mc_list[i].id % HUNT_FILTER_TBL_ROWS;
2717                 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_STACK_OLD;
2718         }
2719         spin_unlock_bh(&efx->filter_lock);
2720
2721         /* Copy/convert the address lists; add the primary station
2722          * address and broadcast address
2723          */
2724         netif_addr_lock_bh(net_dev);
2725         if (net_dev->flags & IFF_PROMISC ||
2726             netdev_uc_count(net_dev) >= EFX_EF10_FILTER_STACK_UC_MAX) {
2727                 table->stack_uc_count = -1;
2728         } else {
2729                 table->stack_uc_count = 1 + netdev_uc_count(net_dev);
2730                 memcpy(table->stack_uc_list[0].addr, net_dev->dev_addr,
2731                        ETH_ALEN);
2732                 i = 1;
2733                 netdev_for_each_uc_addr(uc, net_dev) {
2734                         memcpy(table->stack_uc_list[i].addr,
2735                                uc->addr, ETH_ALEN);
2736                         i++;
2737                 }
2738         }
2739         if (net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI) ||
2740             netdev_mc_count(net_dev) >= EFX_EF10_FILTER_STACK_MC_MAX) {
2741                 table->stack_mc_count = -1;
2742         } else {
2743                 table->stack_mc_count = 1 + netdev_mc_count(net_dev);
2744                 eth_broadcast_addr(table->stack_mc_list[0].addr);
2745                 i = 1;
2746                 netdev_for_each_mc_addr(mc, net_dev) {
2747                         memcpy(table->stack_mc_list[i].addr,
2748                                mc->addr, ETH_ALEN);
2749                         i++;
2750                 }
2751         }
2752         netif_addr_unlock_bh(net_dev);
2753
2754         /* Insert/renew unicast filters */
2755         if (table->stack_uc_count >= 0) {
2756                 for (i = 0; i < table->stack_uc_count; i++) {
2757                         efx_filter_init_rx(&spec, EFX_FILTER_PRI_REQUIRED,
2758                                            EFX_FILTER_FLAG_RX_RSS |
2759                                            EFX_FILTER_FLAG_RX_STACK,
2760                                            0);
2761                         efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
2762                                                  table->stack_uc_list[i].addr);
2763                         rc = efx_ef10_filter_insert(efx, &spec, true);
2764                         if (rc < 0) {
2765                                 /* Fall back to unicast-promisc */
2766                                 while (i--)
2767                                         efx_ef10_filter_remove_safe(
2768                                                 efx, EFX_FILTER_PRI_REQUIRED,
2769                                                 table->stack_uc_list[i].id);
2770                                 table->stack_uc_count = -1;
2771                                 break;
2772                         }
2773                         table->stack_uc_list[i].id = rc;
2774                 }
2775         }
2776         if (table->stack_uc_count < 0) {
2777                 efx_filter_init_rx(&spec, EFX_FILTER_PRI_REQUIRED,
2778                                    EFX_FILTER_FLAG_RX_RSS |
2779                                    EFX_FILTER_FLAG_RX_STACK,
2780                                    0);
2781                 efx_filter_set_uc_def(&spec);
2782                 rc = efx_ef10_filter_insert(efx, &spec, true);
2783                 if (rc < 0) {
2784                         WARN_ON(1);
2785                         table->stack_uc_count = 0;
2786                 } else {
2787                         table->stack_uc_list[0].id = rc;
2788                 }
2789         }
2790
2791         /* Insert/renew multicast filters */
2792         if (table->stack_mc_count >= 0) {
2793                 for (i = 0; i < table->stack_mc_count; i++) {
2794                         efx_filter_init_rx(&spec, EFX_FILTER_PRI_REQUIRED,
2795                                            EFX_FILTER_FLAG_RX_RSS |
2796                                            EFX_FILTER_FLAG_RX_STACK,
2797                                            0);
2798                         efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
2799                                                  table->stack_mc_list[i].addr);
2800                         rc = efx_ef10_filter_insert(efx, &spec, true);
2801                         if (rc < 0) {
2802                                 /* Fall back to multicast-promisc */
2803                                 while (i--)
2804                                         efx_ef10_filter_remove_safe(
2805                                                 efx, EFX_FILTER_PRI_REQUIRED,
2806                                                 table->stack_mc_list[i].id);
2807                                 table->stack_mc_count = -1;
2808                                 break;
2809                         }
2810                         table->stack_mc_list[i].id = rc;
2811                 }
2812         }
2813         if (table->stack_mc_count < 0) {
2814                 efx_filter_init_rx(&spec, EFX_FILTER_PRI_REQUIRED,
2815                                    EFX_FILTER_FLAG_RX_RSS |
2816                                    EFX_FILTER_FLAG_RX_STACK,
2817                                    0);
2818                 efx_filter_set_mc_def(&spec);
2819                 rc = efx_ef10_filter_insert(efx, &spec, true);
2820                 if (rc < 0) {
2821                         WARN_ON(1);
2822                         table->stack_mc_count = 0;
2823                 } else {
2824                         table->stack_mc_list[0].id = rc;
2825                 }
2826         }
2827
2828         /* Remove filters that weren't renewed.  Since nothing else
2829          * changes the STACK_OLD flag or removes these filters, we
2830          * don't need to hold the filter_lock while scanning for
2831          * these filters.
2832          */
2833         for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
2834                 if (ACCESS_ONCE(table->entry[i].spec) &
2835                     EFX_EF10_FILTER_FLAG_STACK_OLD) {
2836                         if (efx_ef10_filter_remove_internal(efx,
2837                                         EFX_FILTER_PRI_REQUIRED,
2838                                         i, true) < 0)
2839                                 remove_failed = true;
2840                 }
2841         }
2842         WARN_ON(remove_failed);
2843 }
2844
2845 static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
2846 {
2847         efx_ef10_filter_sync_rx_mode(efx);
2848
2849         return efx_mcdi_set_mac(efx);
2850 }
2851
2852 #ifdef CONFIG_SFC_MTD
2853
2854 struct efx_ef10_nvram_type_info {
2855         u16 type, type_mask;
2856         u8 port;
2857         const char *name;
2858 };
2859
2860 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
2861         { NVRAM_PARTITION_TYPE_MC_FIRMWARE,        0,    0, "sfc_mcfw" },
2862         { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0,    0, "sfc_mcfw_backup" },
2863         { NVRAM_PARTITION_TYPE_EXPANSION_ROM,      0,    0, "sfc_exp_rom" },
2864         { NVRAM_PARTITION_TYPE_STATIC_CONFIG,      0,    0, "sfc_static_cfg" },
2865         { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG,     0,    0, "sfc_dynamic_cfg" },
2866         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0,   0, "sfc_exp_rom_cfg" },
2867         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0,   1, "sfc_exp_rom_cfg" },
2868         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0,   2, "sfc_exp_rom_cfg" },
2869         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0,   3, "sfc_exp_rom_cfg" },
2870         { NVRAM_PARTITION_TYPE_PHY_MIN,            0xff, 0, "sfc_phy_fw" },
2871 };
2872
2873 static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
2874                                         struct efx_mcdi_mtd_partition *part,
2875                                         unsigned int type)
2876 {
2877         MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
2878         MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
2879         const struct efx_ef10_nvram_type_info *info;
2880         size_t size, erase_size, outlen;
2881         bool protected;
2882         int rc;
2883
2884         for (info = efx_ef10_nvram_types; ; info++) {
2885                 if (info ==
2886                     efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
2887                         return -ENODEV;
2888                 if ((type & ~info->type_mask) == info->type)
2889                         break;
2890         }
2891         if (info->port != efx_port_num(efx))
2892                 return -ENODEV;
2893
2894         rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
2895         if (rc)
2896                 return rc;
2897         if (protected)
2898                 return -ENODEV; /* hide it */
2899
2900         part->nvram_type = type;
2901
2902         MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
2903         rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
2904                           outbuf, sizeof(outbuf), &outlen);
2905         if (rc)
2906                 return rc;
2907         if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
2908                 return -EIO;
2909         if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
2910             (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
2911                 part->fw_subtype = MCDI_DWORD(outbuf,
2912                                               NVRAM_METADATA_OUT_SUBTYPE);
2913
2914         part->common.dev_type_name = "EF10 NVRAM manager";
2915         part->common.type_name = info->name;
2916
2917         part->common.mtd.type = MTD_NORFLASH;
2918         part->common.mtd.flags = MTD_CAP_NORFLASH;
2919         part->common.mtd.size = size;
2920         part->common.mtd.erasesize = erase_size;
2921
2922         return 0;
2923 }
2924
2925 static int efx_ef10_mtd_probe(struct efx_nic *efx)
2926 {
2927         MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
2928         struct efx_mcdi_mtd_partition *parts;
2929         size_t outlen, n_parts_total, i, n_parts;
2930         unsigned int type;
2931         int rc;
2932
2933         ASSERT_RTNL();
2934
2935         BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
2936         rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
2937                           outbuf, sizeof(outbuf), &outlen);
2938         if (rc)
2939                 return rc;
2940         if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
2941                 return -EIO;
2942
2943         n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
2944         if (n_parts_total >
2945             MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
2946                 return -EIO;
2947
2948         parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
2949         if (!parts)
2950                 return -ENOMEM;
2951
2952         n_parts = 0;
2953         for (i = 0; i < n_parts_total; i++) {
2954                 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
2955                                         i);
2956                 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
2957                 if (rc == 0)
2958                         n_parts++;
2959                 else if (rc != -ENODEV)
2960                         goto fail;
2961         }
2962
2963         rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
2964 fail:
2965         if (rc)
2966                 kfree(parts);
2967         return rc;
2968 }
2969
2970 #endif /* CONFIG_SFC_MTD */
2971
2972 static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
2973 {
2974         _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
2975 }
2976
2977 const struct efx_nic_type efx_hunt_a0_nic_type = {
2978         .mem_map_size = efx_ef10_mem_map_size,
2979         .probe = efx_ef10_probe,
2980         .remove = efx_ef10_remove,
2981         .dimension_resources = efx_ef10_dimension_resources,
2982         .init = efx_ef10_init_nic,
2983         .fini = efx_port_dummy_op_void,
2984         .map_reset_reason = efx_mcdi_map_reset_reason,
2985         .map_reset_flags = efx_ef10_map_reset_flags,
2986         .reset = efx_mcdi_reset,
2987         .probe_port = efx_mcdi_port_probe,
2988         .remove_port = efx_mcdi_port_remove,
2989         .fini_dmaq = efx_ef10_fini_dmaq,
2990         .describe_stats = efx_ef10_describe_stats,
2991         .update_stats = efx_ef10_update_stats,
2992         .start_stats = efx_mcdi_mac_start_stats,
2993         .stop_stats = efx_mcdi_mac_stop_stats,
2994         .set_id_led = efx_mcdi_set_id_led,
2995         .push_irq_moderation = efx_ef10_push_irq_moderation,
2996         .reconfigure_mac = efx_ef10_mac_reconfigure,
2997         .check_mac_fault = efx_mcdi_mac_check_fault,
2998         .reconfigure_port = efx_mcdi_port_reconfigure,
2999         .get_wol = efx_ef10_get_wol,
3000         .set_wol = efx_ef10_set_wol,
3001         .resume_wol = efx_port_dummy_op_void,
3002         /* TODO: test_chip */
3003         .test_nvram = efx_mcdi_nvram_test_all,
3004         .mcdi_request = efx_ef10_mcdi_request,
3005         .mcdi_poll_response = efx_ef10_mcdi_poll_response,
3006         .mcdi_read_response = efx_ef10_mcdi_read_response,
3007         .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
3008         .irq_enable_master = efx_port_dummy_op_void,
3009         .irq_test_generate = efx_ef10_irq_test_generate,
3010         .irq_disable_non_ev = efx_port_dummy_op_void,
3011         .irq_handle_msi = efx_ef10_msi_interrupt,
3012         .irq_handle_legacy = efx_ef10_legacy_interrupt,
3013         .tx_probe = efx_ef10_tx_probe,
3014         .tx_init = efx_ef10_tx_init,
3015         .tx_remove = efx_ef10_tx_remove,
3016         .tx_write = efx_ef10_tx_write,
3017         .rx_push_indir_table = efx_ef10_rx_push_indir_table,
3018         .rx_probe = efx_ef10_rx_probe,
3019         .rx_init = efx_ef10_rx_init,
3020         .rx_remove = efx_ef10_rx_remove,
3021         .rx_write = efx_ef10_rx_write,
3022         .rx_defer_refill = efx_ef10_rx_defer_refill,
3023         .ev_probe = efx_ef10_ev_probe,
3024         .ev_init = efx_ef10_ev_init,
3025         .ev_fini = efx_ef10_ev_fini,
3026         .ev_remove = efx_ef10_ev_remove,
3027         .ev_process = efx_ef10_ev_process,
3028         .ev_read_ack = efx_ef10_ev_read_ack,
3029         .ev_test_generate = efx_ef10_ev_test_generate,
3030         .filter_table_probe = efx_ef10_filter_table_probe,
3031         .filter_table_restore = efx_ef10_filter_table_restore,
3032         .filter_table_remove = efx_ef10_filter_table_remove,
3033         .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
3034         .filter_insert = efx_ef10_filter_insert,
3035         .filter_remove_safe = efx_ef10_filter_remove_safe,
3036         .filter_get_safe = efx_ef10_filter_get_safe,
3037         .filter_clear_rx = efx_ef10_filter_clear_rx,
3038         .filter_count_rx_used = efx_ef10_filter_count_rx_used,
3039         .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
3040         .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
3041 #ifdef CONFIG_RFS_ACCEL
3042         .filter_rfs_insert = efx_ef10_filter_rfs_insert,
3043         .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
3044 #endif
3045 #ifdef CONFIG_SFC_MTD
3046         .mtd_probe = efx_ef10_mtd_probe,
3047         .mtd_rename = efx_mcdi_mtd_rename,
3048         .mtd_read = efx_mcdi_mtd_read,
3049         .mtd_erase = efx_mcdi_mtd_erase,
3050         .mtd_write = efx_mcdi_mtd_write,
3051         .mtd_sync = efx_mcdi_mtd_sync,
3052 #endif
3053         .ptp_write_host_time = efx_ef10_ptp_write_host_time,
3054
3055         .revision = EFX_REV_HUNT_A0,
3056         .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
3057         .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
3058         .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
3059         .can_rx_scatter = true,
3060         .always_rx_scatter = true,
3061         .max_interrupt_mode = EFX_INT_MODE_MSIX,
3062         .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
3063         .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3064                              NETIF_F_RXHASH | NETIF_F_NTUPLE),
3065         .mcdi_max_ver = 2,
3066         .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
3067 };