1 /****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2012-2013 Solarflare Communications Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
10 #include "net_driver.h"
11 #include "ef10_regs.h"
14 #include "mcdi_pcol.h"
16 #include "workarounds.h"
18 #include <linux/jhash.h>
19 #include <linux/wait.h>
20 #include <linux/workqueue.h>
22 /* Hardware control for EF10 architecture including 'Huntington'. */
24 #define EFX_EF10_DRVGEN_EV 7
30 /* The reserved RSS context value */
31 #define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff
33 /* The filter table(s) are managed by firmware and we have write-only
34 * access. When removing filters we must identify them to the
35 * firmware by a 64-bit handle, but this is too wide for Linux kernel
36 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to
37 * be able to tell in advance whether a requested insertion will
38 * replace an existing filter. Therefore we maintain a software hash
39 * table, which should be at least as large as the hardware hash
42 * Huntington has a single 8K filter table shared between all filter
43 * types and both ports.
45 #define HUNT_FILTER_TBL_ROWS 8192
47 struct efx_ef10_filter_table {
48 /* The RX match field masks supported by this fw & hw, in order of priority */
49 enum efx_filter_match_flags rx_match_flags[
50 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM];
51 unsigned int rx_match_count;
54 unsigned long spec; /* pointer to spec plus flag bits */
55 /* BUSY flag indicates that an update is in progress. STACK_OLD is
56 * used to mark and sweep stack-owned MAC filters.
58 #define EFX_EF10_FILTER_FLAG_BUSY 1UL
59 #define EFX_EF10_FILTER_FLAG_STACK_OLD 2UL
60 #define EFX_EF10_FILTER_FLAGS 3UL
61 u64 handle; /* firmware handle */
63 wait_queue_head_t waitq;
64 /* Shadow of net_device address lists, guarded by mac_lock */
65 #define EFX_EF10_FILTER_STACK_UC_MAX 32
66 #define EFX_EF10_FILTER_STACK_MC_MAX 256
70 } stack_uc_list[EFX_EF10_FILTER_STACK_UC_MAX],
71 stack_mc_list[EFX_EF10_FILTER_STACK_MC_MAX];
72 int stack_uc_count; /* negative for PROMISC */
73 int stack_mc_count; /* negative for PROMISC/ALLMULTI */
76 /* An arbitrary search limit for the software hash table */
77 #define EFX_EF10_FILTER_SEARCH_LIMIT 200
79 static void efx_ef10_rx_push_indir_table(struct efx_nic *efx);
80 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
81 static void efx_ef10_filter_table_remove(struct efx_nic *efx);
83 static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
87 efx_readd(efx, ®, ER_DZ_BIU_MC_SFT_STATUS);
88 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
89 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
92 static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
94 return resource_size(&efx->pci_dev->resource[EFX_MEM_BAR]);
97 static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
99 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_OUT_LEN);
100 struct efx_ef10_nic_data *nic_data = efx->nic_data;
104 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
106 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
107 outbuf, sizeof(outbuf), &outlen);
110 if (outlen < sizeof(outbuf)) {
111 netif_err(efx, drv, efx->net_dev,
112 "unable to read datapath firmware capabilities\n");
116 nic_data->datapath_caps =
117 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
119 if (!(nic_data->datapath_caps &
120 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))) {
121 netif_err(efx, drv, efx->net_dev,
122 "current firmware does not support TSO\n");
126 if (!(nic_data->datapath_caps &
127 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
128 netif_err(efx, probe, efx->net_dev,
129 "current firmware does not support an RX prefix\n");
136 static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
138 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
141 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
142 outbuf, sizeof(outbuf), NULL);
145 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
146 return rc > 0 ? rc : -ERANGE;
149 static int efx_ef10_get_mac_address(struct efx_nic *efx, u8 *mac_address)
151 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
155 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
157 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
158 outbuf, sizeof(outbuf), &outlen);
161 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
165 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE), ETH_ALEN);
169 static int efx_ef10_probe(struct efx_nic *efx)
171 struct efx_ef10_nic_data *nic_data;
174 /* We can have one VI for each 8K region. However we need
175 * multiple TX queues per channel.
180 resource_size(&efx->pci_dev->resource[EFX_MEM_BAR]) /
181 (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES));
182 BUG_ON(efx->max_channels == 0);
184 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
187 efx->nic_data = nic_data;
189 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
190 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
194 /* Get the MC's warm boot count. In case it's rebooting right
195 * now, be prepared to retry.
199 rc = efx_ef10_get_warm_boot_count(efx);
206 nic_data->warm_boot_count = rc;
208 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
210 /* In case we're recovering from a crash (kexec), we want to
211 * cancel any outstanding request by the previous user of this
212 * function. We send a special message using the least
213 * significant bits of the 'high' (doorbell) register.
215 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
217 rc = efx_mcdi_init(efx);
221 /* Reset (most) configuration for this function */
222 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
226 /* Enable event logging */
227 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
231 rc = efx_ef10_init_datapath_caps(efx);
235 efx->rx_packet_len_offset =
236 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
238 rc = efx_mcdi_port_get_number(efx);
243 rc = efx_ef10_get_mac_address(efx, efx->net_dev->perm_addr);
247 rc = efx_ef10_get_sysclk_freq(efx);
250 efx->timer_quantum_ns = 1536000 / rc; /* 1536 cycles */
252 /* Check whether firmware supports bug 35388 workaround */
253 rc = efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG35388, true);
255 nic_data->workaround_35388 = true;
256 else if (rc != -ENOSYS && rc != -ENOENT)
258 netif_dbg(efx, probe, efx->net_dev,
259 "workaround for bug 35388 is %sabled\n",
260 nic_data->workaround_35388 ? "en" : "dis");
262 rc = efx_mcdi_mon_probe(efx);
271 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
274 efx->nic_data = NULL;
278 static int efx_ef10_free_vis(struct efx_nic *efx)
280 int rc = efx_mcdi_rpc(efx, MC_CMD_FREE_VIS, NULL, 0, NULL, 0, NULL);
282 /* -EALREADY means nothing to free, so ignore */
288 static void efx_ef10_remove(struct efx_nic *efx)
290 struct efx_ef10_nic_data *nic_data = efx->nic_data;
293 efx_mcdi_mon_remove(efx);
295 /* This needs to be after efx_ptp_remove_channel() with no filters */
296 efx_ef10_rx_free_indir_table(efx);
298 rc = efx_ef10_free_vis(efx);
302 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
306 static int efx_ef10_alloc_vis(struct efx_nic *efx,
307 unsigned int min_vis, unsigned int max_vis)
309 MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
310 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
311 struct efx_ef10_nic_data *nic_data = efx->nic_data;
315 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
316 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
317 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
318 outbuf, sizeof(outbuf), &outlen);
322 if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
325 netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
326 MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
328 nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
329 nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
333 static int efx_ef10_dimension_resources(struct efx_nic *efx)
336 max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
338 return efx_ef10_alloc_vis(efx, n_vis, n_vis);
341 static int efx_ef10_init_nic(struct efx_nic *efx)
343 struct efx_ef10_nic_data *nic_data = efx->nic_data;
346 if (nic_data->must_check_datapath_caps) {
347 rc = efx_ef10_init_datapath_caps(efx);
350 nic_data->must_check_datapath_caps = false;
353 if (nic_data->must_realloc_vis) {
354 /* We cannot let the number of VIs change now */
355 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
356 nic_data->n_allocated_vis);
359 nic_data->must_realloc_vis = false;
362 efx_ef10_rx_push_indir_table(efx);
366 static int efx_ef10_map_reset_flags(u32 *flags)
369 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
370 ETH_RESET_SHARED_SHIFT),
371 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
372 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
373 ETH_RESET_PHY | ETH_RESET_MGMT) <<
374 ETH_RESET_SHARED_SHIFT)
377 /* We assume for now that our PCI function is permitted to
381 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
382 *flags &= ~EF10_RESET_MC;
383 return RESET_TYPE_WORLD;
386 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
387 *flags &= ~EF10_RESET_PORT;
388 return RESET_TYPE_ALL;
391 /* no invisible reset implemented */
396 #define EF10_DMA_STAT(ext_name, mcdi_name) \
397 [EF10_STAT_ ## ext_name] = \
398 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
399 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \
400 [EF10_STAT_ ## int_name] = \
401 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
402 #define EF10_OTHER_STAT(ext_name) \
403 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
405 static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
406 EF10_DMA_STAT(tx_bytes, TX_BYTES),
407 EF10_DMA_STAT(tx_packets, TX_PKTS),
408 EF10_DMA_STAT(tx_pause, TX_PAUSE_PKTS),
409 EF10_DMA_STAT(tx_control, TX_CONTROL_PKTS),
410 EF10_DMA_STAT(tx_unicast, TX_UNICAST_PKTS),
411 EF10_DMA_STAT(tx_multicast, TX_MULTICAST_PKTS),
412 EF10_DMA_STAT(tx_broadcast, TX_BROADCAST_PKTS),
413 EF10_DMA_STAT(tx_lt64, TX_LT64_PKTS),
414 EF10_DMA_STAT(tx_64, TX_64_PKTS),
415 EF10_DMA_STAT(tx_65_to_127, TX_65_TO_127_PKTS),
416 EF10_DMA_STAT(tx_128_to_255, TX_128_TO_255_PKTS),
417 EF10_DMA_STAT(tx_256_to_511, TX_256_TO_511_PKTS),
418 EF10_DMA_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS),
419 EF10_DMA_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
420 EF10_DMA_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
421 EF10_DMA_STAT(rx_bytes, RX_BYTES),
422 EF10_DMA_INVIS_STAT(rx_bytes_minus_good_bytes, RX_BAD_BYTES),
423 EF10_OTHER_STAT(rx_good_bytes),
424 EF10_OTHER_STAT(rx_bad_bytes),
425 EF10_DMA_STAT(rx_packets, RX_PKTS),
426 EF10_DMA_STAT(rx_good, RX_GOOD_PKTS),
427 EF10_DMA_STAT(rx_bad, RX_BAD_FCS_PKTS),
428 EF10_DMA_STAT(rx_pause, RX_PAUSE_PKTS),
429 EF10_DMA_STAT(rx_control, RX_CONTROL_PKTS),
430 EF10_DMA_STAT(rx_unicast, RX_UNICAST_PKTS),
431 EF10_DMA_STAT(rx_multicast, RX_MULTICAST_PKTS),
432 EF10_DMA_STAT(rx_broadcast, RX_BROADCAST_PKTS),
433 EF10_DMA_STAT(rx_lt64, RX_UNDERSIZE_PKTS),
434 EF10_DMA_STAT(rx_64, RX_64_PKTS),
435 EF10_DMA_STAT(rx_65_to_127, RX_65_TO_127_PKTS),
436 EF10_DMA_STAT(rx_128_to_255, RX_128_TO_255_PKTS),
437 EF10_DMA_STAT(rx_256_to_511, RX_256_TO_511_PKTS),
438 EF10_DMA_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS),
439 EF10_DMA_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
440 EF10_DMA_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
441 EF10_DMA_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS),
442 EF10_DMA_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS),
443 EF10_DMA_STAT(rx_overflow, RX_OVERFLOW_PKTS),
444 EF10_DMA_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS),
445 EF10_DMA_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS),
446 EF10_DMA_STAT(rx_nodesc_drops, RX_NODESC_DROPS),
447 EF10_DMA_STAT(rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
448 EF10_DMA_STAT(rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
449 EF10_DMA_STAT(rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
450 EF10_DMA_STAT(rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
451 EF10_DMA_STAT(rx_pm_trunc_qbb, PM_TRUNC_QBB),
452 EF10_DMA_STAT(rx_pm_discard_qbb, PM_DISCARD_QBB),
453 EF10_DMA_STAT(rx_pm_discard_mapping, PM_DISCARD_MAPPING),
454 EF10_DMA_STAT(rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
455 EF10_DMA_STAT(rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
456 EF10_DMA_STAT(rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
457 EF10_DMA_STAT(rx_dp_emerg_fetch, RXDP_EMERGENCY_FETCH_CONDITIONS),
458 EF10_DMA_STAT(rx_dp_emerg_wait, RXDP_EMERGENCY_WAIT_CONDITIONS),
461 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_tx_bytes) | \
462 (1ULL << EF10_STAT_tx_packets) | \
463 (1ULL << EF10_STAT_tx_pause) | \
464 (1ULL << EF10_STAT_tx_unicast) | \
465 (1ULL << EF10_STAT_tx_multicast) | \
466 (1ULL << EF10_STAT_tx_broadcast) | \
467 (1ULL << EF10_STAT_rx_bytes) | \
468 (1ULL << EF10_STAT_rx_bytes_minus_good_bytes) | \
469 (1ULL << EF10_STAT_rx_good_bytes) | \
470 (1ULL << EF10_STAT_rx_bad_bytes) | \
471 (1ULL << EF10_STAT_rx_packets) | \
472 (1ULL << EF10_STAT_rx_good) | \
473 (1ULL << EF10_STAT_rx_bad) | \
474 (1ULL << EF10_STAT_rx_pause) | \
475 (1ULL << EF10_STAT_rx_control) | \
476 (1ULL << EF10_STAT_rx_unicast) | \
477 (1ULL << EF10_STAT_rx_multicast) | \
478 (1ULL << EF10_STAT_rx_broadcast) | \
479 (1ULL << EF10_STAT_rx_lt64) | \
480 (1ULL << EF10_STAT_rx_64) | \
481 (1ULL << EF10_STAT_rx_65_to_127) | \
482 (1ULL << EF10_STAT_rx_128_to_255) | \
483 (1ULL << EF10_STAT_rx_256_to_511) | \
484 (1ULL << EF10_STAT_rx_512_to_1023) | \
485 (1ULL << EF10_STAT_rx_1024_to_15xx) | \
486 (1ULL << EF10_STAT_rx_15xx_to_jumbo) | \
487 (1ULL << EF10_STAT_rx_gtjumbo) | \
488 (1ULL << EF10_STAT_rx_bad_gtjumbo) | \
489 (1ULL << EF10_STAT_rx_overflow) | \
490 (1ULL << EF10_STAT_rx_nodesc_drops))
492 /* These statistics are only provided by the 10G MAC. For a 10G/40G
493 * switchable port we do not expose these because they might not
494 * include all the packets they should.
496 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_tx_control) | \
497 (1ULL << EF10_STAT_tx_lt64) | \
498 (1ULL << EF10_STAT_tx_64) | \
499 (1ULL << EF10_STAT_tx_65_to_127) | \
500 (1ULL << EF10_STAT_tx_128_to_255) | \
501 (1ULL << EF10_STAT_tx_256_to_511) | \
502 (1ULL << EF10_STAT_tx_512_to_1023) | \
503 (1ULL << EF10_STAT_tx_1024_to_15xx) | \
504 (1ULL << EF10_STAT_tx_15xx_to_jumbo))
506 /* These statistics are only provided by the 40G MAC. For a 10G/40G
507 * switchable port we do expose these because the errors will otherwise
510 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_rx_align_error) | \
511 (1ULL << EF10_STAT_rx_length_error))
513 /* These statistics are only provided if the firmware supports the
514 * capability PM_AND_RXDP_COUNTERS.
516 #define HUNT_PM_AND_RXDP_STAT_MASK ( \
517 (1ULL << EF10_STAT_rx_pm_trunc_bb_overflow) | \
518 (1ULL << EF10_STAT_rx_pm_discard_bb_overflow) | \
519 (1ULL << EF10_STAT_rx_pm_trunc_vfifo_full) | \
520 (1ULL << EF10_STAT_rx_pm_discard_vfifo_full) | \
521 (1ULL << EF10_STAT_rx_pm_trunc_qbb) | \
522 (1ULL << EF10_STAT_rx_pm_discard_qbb) | \
523 (1ULL << EF10_STAT_rx_pm_discard_mapping) | \
524 (1ULL << EF10_STAT_rx_dp_q_disabled_packets) | \
525 (1ULL << EF10_STAT_rx_dp_di_dropped_packets) | \
526 (1ULL << EF10_STAT_rx_dp_streaming_packets) | \
527 (1ULL << EF10_STAT_rx_dp_emerg_fetch) | \
528 (1ULL << EF10_STAT_rx_dp_emerg_wait))
530 static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
532 u64 raw_mask = HUNT_COMMON_STAT_MASK;
533 u32 port_caps = efx_mcdi_phy_get_caps(efx);
534 struct efx_ef10_nic_data *nic_data = efx->nic_data;
536 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN))
537 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
539 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
541 if (nic_data->datapath_caps &
542 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
543 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
548 static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
550 u64 raw_mask = efx_ef10_raw_stat_mask(efx);
552 #if BITS_PER_LONG == 64
555 mask[0] = raw_mask & 0xffffffff;
556 mask[1] = raw_mask >> 32;
560 static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
562 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
564 efx_ef10_get_stat_mask(efx, mask);
565 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
569 static int efx_ef10_try_update_nic_stats(struct efx_nic *efx)
571 struct efx_ef10_nic_data *nic_data = efx->nic_data;
572 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
573 __le64 generation_start, generation_end;
574 u64 *stats = nic_data->stats;
577 efx_ef10_get_stat_mask(efx, mask);
579 dma_stats = efx->stats_buffer.addr;
580 nic_data = efx->nic_data;
582 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
583 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
586 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
587 stats, efx->stats_buffer.addr, false);
589 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
590 if (generation_end != generation_start)
593 /* Update derived statistics */
594 stats[EF10_STAT_rx_good_bytes] =
595 stats[EF10_STAT_rx_bytes] -
596 stats[EF10_STAT_rx_bytes_minus_good_bytes];
597 efx_update_diff_stat(&stats[EF10_STAT_rx_bad_bytes],
598 stats[EF10_STAT_rx_bytes_minus_good_bytes]);
604 static size_t efx_ef10_update_stats(struct efx_nic *efx, u64 *full_stats,
605 struct rtnl_link_stats64 *core_stats)
607 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
608 struct efx_ef10_nic_data *nic_data = efx->nic_data;
609 u64 *stats = nic_data->stats;
610 size_t stats_count = 0, index;
613 efx_ef10_get_stat_mask(efx, mask);
615 /* If we're unlucky enough to read statistics during the DMA, wait
616 * up to 10ms for it to finish (typically takes <500us)
618 for (retry = 0; retry < 100; ++retry) {
619 if (efx_ef10_try_update_nic_stats(efx) == 0)
625 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
626 if (efx_ef10_stat_desc[index].name) {
627 *full_stats++ = stats[index];
634 core_stats->rx_packets = stats[EF10_STAT_rx_packets];
635 core_stats->tx_packets = stats[EF10_STAT_tx_packets];
636 core_stats->rx_bytes = stats[EF10_STAT_rx_bytes];
637 core_stats->tx_bytes = stats[EF10_STAT_tx_bytes];
638 core_stats->rx_dropped = stats[EF10_STAT_rx_nodesc_drops];
639 core_stats->multicast = stats[EF10_STAT_rx_multicast];
640 core_stats->rx_length_errors =
641 stats[EF10_STAT_rx_gtjumbo] +
642 stats[EF10_STAT_rx_length_error];
643 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
644 core_stats->rx_frame_errors = stats[EF10_STAT_rx_align_error];
645 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
646 core_stats->rx_errors = (core_stats->rx_length_errors +
647 core_stats->rx_crc_errors +
648 core_stats->rx_frame_errors);
654 static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
656 struct efx_nic *efx = channel->efx;
657 unsigned int mode, value;
658 efx_dword_t timer_cmd;
660 if (channel->irq_moderation) {
662 value = channel->irq_moderation - 1;
668 if (EFX_EF10_WORKAROUND_35388(efx)) {
669 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
670 EFE_DD_EVQ_IND_TIMER_FLAGS,
671 ERF_DD_EVQ_IND_TIMER_MODE, mode,
672 ERF_DD_EVQ_IND_TIMER_VAL, value);
673 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
676 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
677 ERF_DZ_TC_TIMER_VAL, value);
678 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
683 static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
687 memset(&wol->sopass, 0, sizeof(wol->sopass));
690 static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
697 static void efx_ef10_mcdi_request(struct efx_nic *efx,
698 const efx_dword_t *hdr, size_t hdr_len,
699 const efx_dword_t *sdu, size_t sdu_len)
701 struct efx_ef10_nic_data *nic_data = efx->nic_data;
702 u8 *pdu = nic_data->mcdi_buf.addr;
704 memcpy(pdu, hdr, hdr_len);
705 memcpy(pdu + hdr_len, sdu, sdu_len);
708 /* The hardware provides 'low' and 'high' (doorbell) registers
709 * for passing the 64-bit address of an MCDI request to
710 * firmware. However the dwords are swapped by firmware. The
711 * least significant bits of the doorbell are then 0 for all
712 * MCDI requests due to alignment.
714 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
716 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
720 static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
722 struct efx_ef10_nic_data *nic_data = efx->nic_data;
723 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
726 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
730 efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
731 size_t offset, size_t outlen)
733 struct efx_ef10_nic_data *nic_data = efx->nic_data;
734 const u8 *pdu = nic_data->mcdi_buf.addr;
736 memcpy(outbuf, pdu + offset, outlen);
739 static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
741 struct efx_ef10_nic_data *nic_data = efx->nic_data;
744 rc = efx_ef10_get_warm_boot_count(efx);
746 /* The firmware is presumably in the process of
747 * rebooting. However, we are supposed to report each
748 * reboot just once, so we must only do that once we
749 * can read and store the updated warm boot count.
754 if (rc == nic_data->warm_boot_count)
757 nic_data->warm_boot_count = rc;
759 /* All our allocations have been reset */
760 nic_data->must_realloc_vis = true;
761 nic_data->must_restore_filters = true;
762 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
764 /* The datapath firmware might have been changed */
765 nic_data->must_check_datapath_caps = true;
767 /* MAC statistics have been cleared on the NIC; clear the local
768 * statistic that we update with efx_update_diff_stat().
770 nic_data->stats[EF10_STAT_rx_bad_bytes] = 0;
775 /* Handle an MSI interrupt
777 * Handle an MSI hardware interrupt. This routine schedules event
778 * queue processing. No interrupt acknowledgement cycle is necessary.
779 * Also, we never need to check that the interrupt is for us, since
780 * MSI interrupts cannot be shared.
782 static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
784 struct efx_msi_context *context = dev_id;
785 struct efx_nic *efx = context->efx;
787 netif_vdbg(efx, intr, efx->net_dev,
788 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
790 if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) {
791 /* Note test interrupts */
792 if (context->index == efx->irq_level)
793 efx->last_irq_cpu = raw_smp_processor_id();
795 /* Schedule processing of the channel */
796 efx_schedule_channel_irq(efx->channel[context->index]);
802 static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
804 struct efx_nic *efx = dev_id;
805 bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
806 struct efx_channel *channel;
810 /* Read the ISR which also ACKs the interrupts */
811 efx_readd(efx, ®, ER_DZ_BIU_INT_ISR);
812 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
817 if (likely(soft_enabled)) {
818 /* Note test interrupts */
819 if (queues & (1U << efx->irq_level))
820 efx->last_irq_cpu = raw_smp_processor_id();
822 efx_for_each_channel(channel, efx) {
824 efx_schedule_channel_irq(channel);
829 netif_vdbg(efx, intr, efx->net_dev,
830 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
831 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
836 static void efx_ef10_irq_test_generate(struct efx_nic *efx)
838 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
840 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
842 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
843 (void) efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
844 inbuf, sizeof(inbuf), NULL, 0, NULL);
847 static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
849 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
850 (tx_queue->ptr_mask + 1) *
855 /* This writes to the TX_DESC_WPTR and also pushes data */
856 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
857 const efx_qword_t *txd)
859 unsigned int write_ptr;
862 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
863 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
865 efx_writeo_page(tx_queue->efx, ®,
866 ER_DZ_TX_DESC_UPD, tx_queue->queue);
869 static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
871 MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
873 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_TXQ_OUT_LEN);
874 bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
875 size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
876 struct efx_channel *channel = tx_queue->channel;
877 struct efx_nic *efx = tx_queue->efx;
878 size_t inlen, outlen;
884 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
885 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
886 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
887 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
888 MCDI_POPULATE_DWORD_2(inbuf, INIT_TXQ_IN_FLAGS,
889 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
890 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
891 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
892 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
894 dma_addr = tx_queue->txd.buf.dma_addr;
896 netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
897 tx_queue->queue, entries, (u64)dma_addr);
899 for (i = 0; i < entries; ++i) {
900 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
901 dma_addr += EFX_BUF_SIZE;
904 inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
906 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
907 outbuf, sizeof(outbuf), &outlen);
911 /* A previous user of this TX queue might have set us up the
912 * bomb by writing a descriptor to the TX push collector but
913 * not the doorbell. (Each collector belongs to a port, not a
914 * queue or function, so cannot easily be reset.) We must
915 * attempt to push a no-op descriptor in its place.
917 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
918 tx_queue->insert_count = 1;
919 txd = efx_tx_desc(tx_queue, 0);
920 EFX_POPULATE_QWORD_4(*txd,
921 ESF_DZ_TX_DESC_IS_OPT, true,
922 ESF_DZ_TX_OPTION_TYPE,
923 ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
924 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
925 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
926 tx_queue->write_count = 1;
928 efx_ef10_push_tx_desc(tx_queue, txd);
934 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
937 static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
939 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
940 MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_TXQ_OUT_LEN);
941 struct efx_nic *efx = tx_queue->efx;
945 MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
948 rc = efx_mcdi_rpc(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
949 outbuf, sizeof(outbuf), &outlen);
951 if (rc && rc != -EALREADY)
957 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
960 static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
962 efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
965 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
966 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
968 unsigned int write_ptr;
971 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
972 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
973 efx_writed_page(tx_queue->efx, ®,
974 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
977 static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
979 unsigned int old_write_count = tx_queue->write_count;
980 struct efx_tx_buffer *buffer;
981 unsigned int write_ptr;
984 BUG_ON(tx_queue->write_count == tx_queue->insert_count);
987 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
988 buffer = &tx_queue->buffer[write_ptr];
989 txd = efx_tx_desc(tx_queue, write_ptr);
990 ++tx_queue->write_count;
992 /* Create TX descriptor ring entry */
993 if (buffer->flags & EFX_TX_BUF_OPTION) {
994 *txd = buffer->option;
996 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
997 EFX_POPULATE_QWORD_3(
1000 buffer->flags & EFX_TX_BUF_CONT,
1001 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
1002 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
1004 } while (tx_queue->write_count != tx_queue->insert_count);
1006 wmb(); /* Ensure descriptors are written before they are fetched */
1008 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
1009 txd = efx_tx_desc(tx_queue,
1010 old_write_count & tx_queue->ptr_mask);
1011 efx_ef10_push_tx_desc(tx_queue, txd);
1014 efx_ef10_notify_tx_desc(tx_queue);
1018 static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context)
1020 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
1021 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
1025 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
1026 EVB_PORT_ID_ASSIGNED);
1027 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE,
1028 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE);
1029 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES,
1032 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
1033 outbuf, sizeof(outbuf), &outlen);
1037 if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
1040 *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
1045 static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
1047 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
1050 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
1053 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
1058 static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context)
1060 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
1061 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
1064 MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
1066 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
1067 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
1069 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
1071 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
1072 (u8) efx->rx_indir_table[i];
1074 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
1075 sizeof(tablebuf), NULL, 0, NULL);
1079 MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
1081 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
1082 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
1083 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
1084 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] =
1085 efx->rx_hash_key[i];
1087 return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
1088 sizeof(keybuf), NULL, 0, NULL);
1091 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
1093 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1095 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
1096 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
1097 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
1100 static void efx_ef10_rx_push_indir_table(struct efx_nic *efx)
1102 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1105 netif_dbg(efx, drv, efx->net_dev, "pushing RX indirection table\n");
1107 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID) {
1108 rc = efx_ef10_alloc_rss_context(efx, &nic_data->rx_rss_context);
1113 rc = efx_ef10_populate_rss_table(efx, nic_data->rx_rss_context);
1120 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
1123 static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
1125 return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
1126 (rx_queue->ptr_mask + 1) *
1127 sizeof(efx_qword_t),
1131 static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
1133 MCDI_DECLARE_BUF(inbuf,
1134 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
1136 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_RXQ_OUT_LEN);
1137 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
1138 size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
1139 struct efx_nic *efx = rx_queue->efx;
1140 size_t inlen, outlen;
1141 dma_addr_t dma_addr;
1145 rx_queue->scatter_n = 0;
1146 rx_queue->scatter_len = 0;
1148 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
1149 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
1150 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
1151 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
1152 efx_rx_queue_index(rx_queue));
1153 MCDI_POPULATE_DWORD_1(inbuf, INIT_RXQ_IN_FLAGS,
1154 INIT_RXQ_IN_FLAG_PREFIX, 1);
1155 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
1156 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1158 dma_addr = rx_queue->rxd.buf.dma_addr;
1160 netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
1161 efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
1163 for (i = 0; i < entries; ++i) {
1164 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
1165 dma_addr += EFX_BUF_SIZE;
1168 inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
1170 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
1171 outbuf, sizeof(outbuf), &outlen);
1179 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
1182 static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
1184 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
1185 MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_RXQ_OUT_LEN);
1186 struct efx_nic *efx = rx_queue->efx;
1190 MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
1191 efx_rx_queue_index(rx_queue));
1193 rc = efx_mcdi_rpc(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
1194 outbuf, sizeof(outbuf), &outlen);
1196 if (rc && rc != -EALREADY)
1202 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
1205 static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
1207 efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
1210 /* This creates an entry in the RX descriptor queue */
1212 efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
1214 struct efx_rx_buffer *rx_buf;
1217 rxd = efx_rx_desc(rx_queue, index);
1218 rx_buf = efx_rx_buffer(rx_queue, index);
1219 EFX_POPULATE_QWORD_2(*rxd,
1220 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
1221 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
1224 static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
1226 struct efx_nic *efx = rx_queue->efx;
1227 unsigned int write_count;
1230 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
1231 write_count = rx_queue->added_count & ~7;
1232 if (rx_queue->notified_count == write_count)
1236 efx_ef10_build_rx_desc(
1238 rx_queue->notified_count & rx_queue->ptr_mask);
1239 while (++rx_queue->notified_count != write_count);
1242 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
1243 write_count & rx_queue->ptr_mask);
1244 efx_writed_page(efx, ®, ER_DZ_RX_DESC_UPD,
1245 efx_rx_queue_index(rx_queue));
1248 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
1250 static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
1252 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
1253 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
1256 EFX_POPULATE_QWORD_2(event,
1257 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
1258 ESF_DZ_EV_DATA, EFX_EF10_REFILL);
1260 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
1262 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
1263 * already swapped the data to little-endian order.
1265 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
1266 sizeof(efx_qword_t));
1268 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
1269 inbuf, sizeof(inbuf), 0,
1270 efx_ef10_rx_defer_refill_complete, 0);
1274 efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
1275 int rc, efx_dword_t *outbuf,
1276 size_t outlen_actual)
1281 static int efx_ef10_ev_probe(struct efx_channel *channel)
1283 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
1284 (channel->eventq_mask + 1) *
1285 sizeof(efx_qword_t),
1289 static int efx_ef10_ev_init(struct efx_channel *channel)
1291 MCDI_DECLARE_BUF(inbuf,
1292 MC_CMD_INIT_EVQ_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
1294 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_OUT_LEN);
1295 size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
1296 struct efx_nic *efx = channel->efx;
1297 struct efx_ef10_nic_data *nic_data;
1298 bool supports_rx_merge;
1299 size_t inlen, outlen;
1300 dma_addr_t dma_addr;
1304 nic_data = efx->nic_data;
1306 !!(nic_data->datapath_caps &
1307 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
1309 /* Fill event queue with all ones (i.e. empty events) */
1310 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
1312 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
1313 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
1314 /* INIT_EVQ expects index in vector table, not absolute */
1315 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
1316 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
1317 INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
1318 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
1319 INIT_EVQ_IN_FLAG_TX_MERGE, 1,
1320 INIT_EVQ_IN_FLAG_CUT_THRU, !supports_rx_merge);
1321 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
1322 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
1323 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
1324 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
1325 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
1326 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
1327 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
1329 dma_addr = channel->eventq.buf.dma_addr;
1330 for (i = 0; i < entries; ++i) {
1331 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
1332 dma_addr += EFX_BUF_SIZE;
1335 inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
1337 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
1338 outbuf, sizeof(outbuf), &outlen);
1342 /* IRQ return is ignored */
1347 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
1351 static void efx_ef10_ev_fini(struct efx_channel *channel)
1353 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
1354 MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_EVQ_OUT_LEN);
1355 struct efx_nic *efx = channel->efx;
1359 MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
1361 rc = efx_mcdi_rpc(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
1362 outbuf, sizeof(outbuf), &outlen);
1364 if (rc && rc != -EALREADY)
1370 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
1373 static void efx_ef10_ev_remove(struct efx_channel *channel)
1375 efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
1378 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
1379 unsigned int rx_queue_label)
1381 struct efx_nic *efx = rx_queue->efx;
1383 netif_info(efx, hw, efx->net_dev,
1384 "rx event arrived on queue %d labeled as queue %u\n",
1385 efx_rx_queue_index(rx_queue), rx_queue_label);
1387 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1391 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
1392 unsigned int actual, unsigned int expected)
1394 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
1395 struct efx_nic *efx = rx_queue->efx;
1397 netif_info(efx, hw, efx->net_dev,
1398 "dropped %d events (index=%d expected=%d)\n",
1399 dropped, actual, expected);
1401 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1404 /* partially received RX was aborted. clean up. */
1405 static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
1407 unsigned int rx_desc_ptr;
1409 WARN_ON(rx_queue->scatter_n == 0);
1411 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
1412 "scattered RX aborted (dropping %u buffers)\n",
1413 rx_queue->scatter_n);
1415 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
1417 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
1418 0, EFX_RX_PKT_DISCARD);
1420 rx_queue->removed_count += rx_queue->scatter_n;
1421 rx_queue->scatter_n = 0;
1422 rx_queue->scatter_len = 0;
1423 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
1426 static int efx_ef10_handle_rx_event(struct efx_channel *channel,
1427 const efx_qword_t *event)
1429 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class;
1430 unsigned int n_descs, n_packets, i;
1431 struct efx_nic *efx = channel->efx;
1432 struct efx_rx_queue *rx_queue;
1436 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
1439 /* Basic packet information */
1440 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
1441 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
1442 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
1443 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS);
1444 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
1446 WARN_ON(EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT));
1448 rx_queue = efx_channel_get_rx_queue(channel);
1450 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
1451 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
1453 n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
1454 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
1456 if (n_descs != rx_queue->scatter_n + 1) {
1457 /* detect rx abort */
1458 if (unlikely(n_descs == rx_queue->scatter_n)) {
1459 WARN_ON(rx_bytes != 0);
1460 efx_ef10_handle_rx_abort(rx_queue);
1464 if (unlikely(rx_queue->scatter_n != 0)) {
1465 /* Scattered packet completions cannot be
1466 * merged, so something has gone wrong.
1468 efx_ef10_handle_rx_bad_lbits(
1469 rx_queue, next_ptr_lbits,
1470 (rx_queue->removed_count +
1471 rx_queue->scatter_n + 1) &
1472 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
1476 /* Merged completion for multiple non-scattered packets */
1477 rx_queue->scatter_n = 1;
1478 rx_queue->scatter_len = 0;
1479 n_packets = n_descs;
1480 ++channel->n_rx_merge_events;
1481 channel->n_rx_merge_packets += n_packets;
1482 flags |= EFX_RX_PKT_PREFIX_LEN;
1484 ++rx_queue->scatter_n;
1485 rx_queue->scatter_len += rx_bytes;
1491 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)))
1492 flags |= EFX_RX_PKT_DISCARD;
1494 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) {
1495 channel->n_rx_ip_hdr_chksum_err += n_packets;
1496 } else if (unlikely(EFX_QWORD_FIELD(*event,
1497 ESF_DZ_RX_TCPUDP_CKSUM_ERR))) {
1498 channel->n_rx_tcp_udp_chksum_err += n_packets;
1499 } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
1500 rx_l4_class == ESE_DZ_L4_CLASS_UDP) {
1501 flags |= EFX_RX_PKT_CSUMMED;
1504 if (rx_l4_class == ESE_DZ_L4_CLASS_TCP)
1505 flags |= EFX_RX_PKT_TCP;
1507 channel->irq_mod_score += 2 * n_packets;
1509 /* Handle received packet(s) */
1510 for (i = 0; i < n_packets; i++) {
1511 efx_rx_packet(rx_queue,
1512 rx_queue->removed_count & rx_queue->ptr_mask,
1513 rx_queue->scatter_n, rx_queue->scatter_len,
1515 rx_queue->removed_count += rx_queue->scatter_n;
1518 rx_queue->scatter_n = 0;
1519 rx_queue->scatter_len = 0;
1525 efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
1527 struct efx_nic *efx = channel->efx;
1528 struct efx_tx_queue *tx_queue;
1529 unsigned int tx_ev_desc_ptr;
1530 unsigned int tx_ev_q_label;
1533 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
1536 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
1539 /* Transmit completion */
1540 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
1541 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
1542 tx_queue = efx_channel_get_tx_queue(channel,
1543 tx_ev_q_label % EFX_TXQ_TYPES);
1544 tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
1545 tx_queue->ptr_mask);
1546 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
1552 efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
1554 struct efx_nic *efx = channel->efx;
1557 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
1560 case ESE_DZ_DRV_TIMER_EV:
1561 case ESE_DZ_DRV_WAKE_UP_EV:
1563 case ESE_DZ_DRV_START_UP_EV:
1564 /* event queue init complete. ok. */
1567 netif_err(efx, hw, efx->net_dev,
1568 "channel %d unknown driver event type %d"
1569 " (data " EFX_QWORD_FMT ")\n",
1570 channel->channel, subcode,
1571 EFX_QWORD_VAL(*event));
1576 static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
1579 struct efx_nic *efx = channel->efx;
1582 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
1586 channel->event_test_cpu = raw_smp_processor_id();
1588 case EFX_EF10_REFILL:
1589 /* The queue must be empty, so we won't receive any rx
1590 * events, so efx_process_channel() won't refill the
1591 * queue. Refill it here
1593 efx_fast_push_rx_descriptors(&channel->rx_queue);
1596 netif_err(efx, hw, efx->net_dev,
1597 "channel %d unknown driver event type %u"
1598 " (data " EFX_QWORD_FMT ")\n",
1599 channel->channel, (unsigned) subcode,
1600 EFX_QWORD_VAL(*event));
1604 static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
1606 struct efx_nic *efx = channel->efx;
1607 efx_qword_t event, *p_event;
1608 unsigned int read_ptr;
1613 read_ptr = channel->eventq_read_ptr;
1616 p_event = efx_event(channel, read_ptr);
1619 if (!efx_event_present(&event))
1622 EFX_SET_QWORD(*p_event);
1626 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
1628 netif_vdbg(efx, drv, efx->net_dev,
1629 "processing event on %d " EFX_QWORD_FMT "\n",
1630 channel->channel, EFX_QWORD_VAL(event));
1633 case ESE_DZ_EV_CODE_MCDI_EV:
1634 efx_mcdi_process_event(channel, &event);
1636 case ESE_DZ_EV_CODE_RX_EV:
1637 spent += efx_ef10_handle_rx_event(channel, &event);
1638 if (spent >= quota) {
1639 /* XXX can we split a merged event to
1640 * avoid going over-quota?
1646 case ESE_DZ_EV_CODE_TX_EV:
1647 tx_descs += efx_ef10_handle_tx_event(channel, &event);
1648 if (tx_descs > efx->txq_entries) {
1651 } else if (++spent == quota) {
1655 case ESE_DZ_EV_CODE_DRIVER_EV:
1656 efx_ef10_handle_driver_event(channel, &event);
1657 if (++spent == quota)
1660 case EFX_EF10_DRVGEN_EV:
1661 efx_ef10_handle_driver_generated_event(channel, &event);
1664 netif_err(efx, hw, efx->net_dev,
1665 "channel %d unknown event type %d"
1666 " (data " EFX_QWORD_FMT ")\n",
1667 channel->channel, ev_code,
1668 EFX_QWORD_VAL(event));
1673 channel->eventq_read_ptr = read_ptr;
1677 static void efx_ef10_ev_read_ack(struct efx_channel *channel)
1679 struct efx_nic *efx = channel->efx;
1682 if (EFX_EF10_WORKAROUND_35388(efx)) {
1683 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
1684 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
1685 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
1686 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
1688 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
1689 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
1690 ERF_DD_EVQ_IND_RPTR,
1691 (channel->eventq_read_ptr &
1692 channel->eventq_mask) >>
1693 ERF_DD_EVQ_IND_RPTR_WIDTH);
1694 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
1696 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
1697 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
1698 ERF_DD_EVQ_IND_RPTR,
1699 channel->eventq_read_ptr &
1700 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
1701 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
1704 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
1705 channel->eventq_read_ptr &
1706 channel->eventq_mask);
1707 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
1711 static void efx_ef10_ev_test_generate(struct efx_channel *channel)
1713 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
1714 struct efx_nic *efx = channel->efx;
1718 EFX_POPULATE_QWORD_2(event,
1719 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
1720 ESF_DZ_EV_DATA, EFX_EF10_TEST);
1722 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
1724 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
1725 * already swapped the data to little-endian order.
1727 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
1728 sizeof(efx_qword_t));
1730 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
1739 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
1742 void efx_ef10_handle_drain_event(struct efx_nic *efx)
1744 if (atomic_dec_and_test(&efx->active_queues))
1745 wake_up(&efx->flush_wq);
1747 WARN_ON(atomic_read(&efx->active_queues) < 0);
1750 static int efx_ef10_fini_dmaq(struct efx_nic *efx)
1752 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1753 struct efx_channel *channel;
1754 struct efx_tx_queue *tx_queue;
1755 struct efx_rx_queue *rx_queue;
1758 /* If the MC has just rebooted, the TX/RX queues will have already been
1759 * torn down, but efx->active_queues needs to be set to zero.
1761 if (nic_data->must_realloc_vis) {
1762 atomic_set(&efx->active_queues, 0);
1766 /* Do not attempt to write to the NIC during EEH recovery */
1767 if (efx->state != STATE_RECOVERY) {
1768 efx_for_each_channel(channel, efx) {
1769 efx_for_each_channel_rx_queue(rx_queue, channel)
1770 efx_ef10_rx_fini(rx_queue);
1771 efx_for_each_channel_tx_queue(tx_queue, channel)
1772 efx_ef10_tx_fini(tx_queue);
1775 wait_event_timeout(efx->flush_wq,
1776 atomic_read(&efx->active_queues) == 0,
1777 msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
1778 pending = atomic_read(&efx->active_queues);
1780 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
1789 static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
1790 const struct efx_filter_spec *right)
1792 if ((left->match_flags ^ right->match_flags) |
1793 ((left->flags ^ right->flags) &
1794 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
1797 return memcmp(&left->outer_vid, &right->outer_vid,
1798 sizeof(struct efx_filter_spec) -
1799 offsetof(struct efx_filter_spec, outer_vid)) == 0;
1802 static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
1804 BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
1805 return jhash2((const u32 *)&spec->outer_vid,
1806 (sizeof(struct efx_filter_spec) -
1807 offsetof(struct efx_filter_spec, outer_vid)) / 4,
1809 /* XXX should we randomise the initval? */
1812 /* Decide whether a filter should be exclusive or else should allow
1813 * delivery to additional recipients. Currently we decide that
1814 * filters for specific local unicast MAC and IP addresses are
1817 static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
1819 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
1820 !is_multicast_ether_addr(spec->loc_mac))
1823 if ((spec->match_flags &
1824 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
1825 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
1826 if (spec->ether_type == htons(ETH_P_IP) &&
1827 !ipv4_is_multicast(spec->loc_host[0]))
1829 if (spec->ether_type == htons(ETH_P_IPV6) &&
1830 ((const u8 *)spec->loc_host)[0] != 0xff)
1837 static struct efx_filter_spec *
1838 efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
1839 unsigned int filter_idx)
1841 return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
1842 ~EFX_EF10_FILTER_FLAGS);
1846 efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
1847 unsigned int filter_idx)
1849 return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
1853 efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
1854 unsigned int filter_idx,
1855 const struct efx_filter_spec *spec,
1858 table->entry[filter_idx].spec = (unsigned long)spec | flags;
1861 static void efx_ef10_filter_push_prep(struct efx_nic *efx,
1862 const struct efx_filter_spec *spec,
1863 efx_dword_t *inbuf, u64 handle,
1866 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1868 memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN);
1871 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
1872 MC_CMD_FILTER_OP_IN_OP_REPLACE);
1873 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
1875 u32 match_fields = 0;
1877 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
1878 efx_ef10_filter_is_exclusive(spec) ?
1879 MC_CMD_FILTER_OP_IN_OP_INSERT :
1880 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
1882 /* Convert match flags and values. Unlike almost
1883 * everything else in MCDI, these fields are in
1884 * network byte order.
1886 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
1888 is_multicast_ether_addr(spec->loc_mac) ?
1889 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN :
1890 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
1891 #define COPY_FIELD(gen_flag, gen_field, mcdi_field) \
1892 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \
1894 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
1895 mcdi_field ## _LBN; \
1897 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
1898 sizeof(spec->gen_field)); \
1899 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
1900 &spec->gen_field, sizeof(spec->gen_field)); \
1902 COPY_FIELD(REM_HOST, rem_host, SRC_IP);
1903 COPY_FIELD(LOC_HOST, loc_host, DST_IP);
1904 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
1905 COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
1906 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
1907 COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
1908 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
1909 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
1910 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
1911 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
1913 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
1917 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1918 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
1919 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
1920 MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
1921 MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
1922 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
1923 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
1924 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE, spec->dmaq_id);
1925 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
1926 (spec->flags & EFX_FILTER_FLAG_RX_RSS) ?
1927 MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
1928 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
1929 if (spec->flags & EFX_FILTER_FLAG_RX_RSS)
1930 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
1931 spec->rss_context !=
1932 EFX_FILTER_RSS_CONTEXT_DEFAULT ?
1933 spec->rss_context : nic_data->rx_rss_context);
1936 static int efx_ef10_filter_push(struct efx_nic *efx,
1937 const struct efx_filter_spec *spec,
1938 u64 *handle, bool replacing)
1940 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
1941 MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN);
1944 efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
1945 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
1946 outbuf, sizeof(outbuf), NULL);
1948 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
1952 static int efx_ef10_filter_rx_match_pri(struct efx_ef10_filter_table *table,
1953 enum efx_filter_match_flags match_flags)
1955 unsigned int match_pri;
1958 match_pri < table->rx_match_count;
1960 if (table->rx_match_flags[match_pri] == match_flags)
1963 return -EPROTONOSUPPORT;
1966 static s32 efx_ef10_filter_insert(struct efx_nic *efx,
1967 struct efx_filter_spec *spec,
1970 struct efx_ef10_filter_table *table = efx->filter_state;
1971 DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
1972 struct efx_filter_spec *saved_spec;
1973 unsigned int match_pri, hash;
1974 unsigned int priv_flags;
1975 bool replacing = false;
1981 /* For now, only support RX filters */
1982 if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
1986 rc = efx_ef10_filter_rx_match_pri(table, spec->match_flags);
1991 hash = efx_ef10_filter_hash(spec);
1992 is_mc_recip = efx_filter_is_mc_recipient(spec);
1994 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
1996 /* Find any existing filters with the same match tuple or
1997 * else a free slot to insert at. If any of them are busy,
1998 * we have to wait and retry.
2001 unsigned int depth = 1;
2004 spin_lock_bh(&efx->filter_lock);
2007 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2008 saved_spec = efx_ef10_filter_entry_spec(table, i);
2013 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
2014 if (table->entry[i].spec &
2015 EFX_EF10_FILTER_FLAG_BUSY)
2017 if (spec->priority < saved_spec->priority &&
2018 !(saved_spec->priority ==
2019 EFX_FILTER_PRI_REQUIRED &&
2021 EFX_FILTER_FLAG_RX_STACK)) {
2026 /* This is the only one */
2027 if (spec->priority ==
2028 saved_spec->priority &&
2035 } else if (spec->priority >
2036 saved_spec->priority ||
2038 saved_spec->priority &&
2043 __set_bit(depth, mc_rem_map);
2047 /* Once we reach the maximum search depth, use
2048 * the first suitable slot or return -EBUSY if
2051 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
2052 if (ins_index < 0) {
2062 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
2063 spin_unlock_bh(&efx->filter_lock);
2068 /* Create a software table entry if necessary, and mark it
2069 * busy. We might yet fail to insert, but any attempt to
2070 * insert a conflicting filter while we're waiting for the
2071 * firmware must find the busy entry.
2073 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
2075 if (spec->flags & EFX_FILTER_FLAG_RX_STACK) {
2076 /* Just make sure it won't be removed */
2077 saved_spec->flags |= EFX_FILTER_FLAG_RX_STACK;
2078 table->entry[ins_index].spec &=
2079 ~EFX_EF10_FILTER_FLAG_STACK_OLD;
2084 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
2086 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
2091 *saved_spec = *spec;
2094 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
2095 priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
2097 /* Mark lower-priority multicast recipients busy prior to removal */
2099 unsigned int depth, i;
2101 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
2102 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2103 if (test_bit(depth, mc_rem_map))
2104 table->entry[i].spec |=
2105 EFX_EF10_FILTER_FLAG_BUSY;
2109 spin_unlock_bh(&efx->filter_lock);
2111 rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
2114 /* Finalise the software table entry */
2115 spin_lock_bh(&efx->filter_lock);
2118 /* Update the fields that may differ */
2119 saved_spec->priority = spec->priority;
2120 saved_spec->flags &= EFX_FILTER_FLAG_RX_STACK;
2121 saved_spec->flags |= spec->flags;
2122 saved_spec->rss_context = spec->rss_context;
2123 saved_spec->dmaq_id = spec->dmaq_id;
2125 } else if (!replacing) {
2129 efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
2131 /* Remove and finalise entries for lower-priority multicast
2135 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2136 unsigned int depth, i;
2138 memset(inbuf, 0, sizeof(inbuf));
2140 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
2141 if (!test_bit(depth, mc_rem_map))
2144 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2145 saved_spec = efx_ef10_filter_entry_spec(table, i);
2146 priv_flags = efx_ef10_filter_entry_flags(table, i);
2149 spin_unlock_bh(&efx->filter_lock);
2150 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2151 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
2152 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
2153 table->entry[i].handle);
2154 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
2155 inbuf, sizeof(inbuf),
2157 spin_lock_bh(&efx->filter_lock);
2165 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
2167 efx_ef10_filter_set_entry(table, i, saved_spec,
2172 /* If successful, return the inserted filter ID */
2174 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index;
2176 wake_up_all(&table->waitq);
2178 spin_unlock_bh(&efx->filter_lock);
2179 finish_wait(&table->waitq, &wait);
2183 void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
2185 /* no need to do anything here on EF10 */
2189 * If !stack_requested, remove by ID
2190 * If stack_requested, remove by index
2191 * Filter ID may come from userland and must be range-checked.
2193 static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
2194 enum efx_filter_priority priority,
2195 u32 filter_id, bool stack_requested)
2197 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
2198 struct efx_ef10_filter_table *table = efx->filter_state;
2199 MCDI_DECLARE_BUF(inbuf,
2200 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
2201 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
2202 struct efx_filter_spec *spec;
2206 /* Find the software table entry and mark it busy. Don't
2207 * remove it yet; any attempt to update while we're waiting
2208 * for the firmware must find the busy entry.
2211 spin_lock_bh(&efx->filter_lock);
2212 if (!(table->entry[filter_idx].spec &
2213 EFX_EF10_FILTER_FLAG_BUSY))
2215 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
2216 spin_unlock_bh(&efx->filter_lock);
2219 spec = efx_ef10_filter_entry_spec(table, filter_idx);
2220 if (!spec || spec->priority > priority ||
2221 (!stack_requested &&
2222 efx_ef10_filter_rx_match_pri(table, spec->match_flags) !=
2223 filter_id / HUNT_FILTER_TBL_ROWS)) {
2227 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
2228 spin_unlock_bh(&efx->filter_lock);
2230 if (spec->flags & EFX_FILTER_FLAG_RX_STACK && !stack_requested) {
2231 /* Reset steering of a stack-owned filter */
2233 struct efx_filter_spec new_spec = *spec;
2235 new_spec.priority = EFX_FILTER_PRI_REQUIRED;
2236 new_spec.flags = (EFX_FILTER_FLAG_RX |
2237 EFX_FILTER_FLAG_RX_RSS |
2238 EFX_FILTER_FLAG_RX_STACK);
2239 new_spec.dmaq_id = 0;
2240 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
2241 rc = efx_ef10_filter_push(efx, &new_spec,
2242 &table->entry[filter_idx].handle,
2245 spin_lock_bh(&efx->filter_lock);
2249 /* Really remove the filter */
2251 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2252 efx_ef10_filter_is_exclusive(spec) ?
2253 MC_CMD_FILTER_OP_IN_OP_REMOVE :
2254 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
2255 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
2256 table->entry[filter_idx].handle);
2257 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
2258 inbuf, sizeof(inbuf), NULL, 0, NULL);
2260 spin_lock_bh(&efx->filter_lock);
2263 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
2266 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
2267 wake_up_all(&table->waitq);
2269 spin_unlock_bh(&efx->filter_lock);
2270 finish_wait(&table->waitq, &wait);
2274 static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
2275 enum efx_filter_priority priority,
2278 return efx_ef10_filter_remove_internal(efx, priority, filter_id, false);
2281 static int efx_ef10_filter_get_safe(struct efx_nic *efx,
2282 enum efx_filter_priority priority,
2283 u32 filter_id, struct efx_filter_spec *spec)
2285 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
2286 struct efx_ef10_filter_table *table = efx->filter_state;
2287 const struct efx_filter_spec *saved_spec;
2290 spin_lock_bh(&efx->filter_lock);
2291 saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
2292 if (saved_spec && saved_spec->priority == priority &&
2293 efx_ef10_filter_rx_match_pri(table, saved_spec->match_flags) ==
2294 filter_id / HUNT_FILTER_TBL_ROWS) {
2295 *spec = *saved_spec;
2300 spin_unlock_bh(&efx->filter_lock);
2304 static void efx_ef10_filter_clear_rx(struct efx_nic *efx,
2305 enum efx_filter_priority priority)
2310 static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
2311 enum efx_filter_priority priority)
2313 struct efx_ef10_filter_table *table = efx->filter_state;
2314 unsigned int filter_idx;
2317 spin_lock_bh(&efx->filter_lock);
2318 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
2319 if (table->entry[filter_idx].spec &&
2320 efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
2324 spin_unlock_bh(&efx->filter_lock);
2328 static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
2330 struct efx_ef10_filter_table *table = efx->filter_state;
2332 return table->rx_match_count * HUNT_FILTER_TBL_ROWS;
2335 static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
2336 enum efx_filter_priority priority,
2339 struct efx_ef10_filter_table *table = efx->filter_state;
2340 struct efx_filter_spec *spec;
2341 unsigned int filter_idx;
2344 spin_lock_bh(&efx->filter_lock);
2345 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
2346 spec = efx_ef10_filter_entry_spec(table, filter_idx);
2347 if (spec && spec->priority == priority) {
2348 if (count == size) {
2352 buf[count++] = (efx_ef10_filter_rx_match_pri(
2353 table, spec->match_flags) *
2354 HUNT_FILTER_TBL_ROWS +
2358 spin_unlock_bh(&efx->filter_lock);
2362 #ifdef CONFIG_RFS_ACCEL
2364 static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
2366 static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
2367 struct efx_filter_spec *spec)
2369 struct efx_ef10_filter_table *table = efx->filter_state;
2370 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2371 struct efx_filter_spec *saved_spec;
2372 unsigned int hash, i, depth = 1;
2373 bool replacing = false;
2378 /* Must be an RX filter without RSS and not for a multicast
2379 * destination address (RFS only works for connected sockets).
2380 * These restrictions allow us to pass only a tiny amount of
2381 * data through to the completion function.
2383 EFX_WARN_ON_PARANOID(spec->flags !=
2384 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
2385 EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
2386 EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
2388 hash = efx_ef10_filter_hash(spec);
2390 spin_lock_bh(&efx->filter_lock);
2392 /* Find any existing filter with the same match tuple or else
2393 * a free slot to insert at. If an existing filter is busy,
2394 * we have to give up.
2397 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2398 saved_spec = efx_ef10_filter_entry_spec(table, i);
2403 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
2404 if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
2408 EFX_WARN_ON_PARANOID(saved_spec->flags &
2409 EFX_FILTER_FLAG_RX_STACK);
2410 if (spec->priority < saved_spec->priority) {
2418 /* Once we reach the maximum search depth, use the
2419 * first suitable slot or return -EBUSY if there was
2422 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
2423 if (ins_index < 0) {
2433 /* Create a software table entry if necessary, and mark it
2434 * busy. We might yet fail to insert, but any attempt to
2435 * insert a conflicting filter while we're waiting for the
2436 * firmware must find the busy entry.
2438 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
2442 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
2447 *saved_spec = *spec;
2449 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
2450 EFX_EF10_FILTER_FLAG_BUSY);
2452 spin_unlock_bh(&efx->filter_lock);
2454 /* Pack up the variables needed on completion */
2455 cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
2457 efx_ef10_filter_push_prep(efx, spec, inbuf,
2458 table->entry[ins_index].handle, replacing);
2459 efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
2460 MC_CMD_FILTER_OP_OUT_LEN,
2461 efx_ef10_filter_rfs_insert_complete, cookie);
2466 spin_unlock_bh(&efx->filter_lock);
2471 efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
2472 int rc, efx_dword_t *outbuf,
2473 size_t outlen_actual)
2475 struct efx_ef10_filter_table *table = efx->filter_state;
2476 unsigned int ins_index, dmaq_id;
2477 struct efx_filter_spec *spec;
2480 /* Unpack the cookie */
2481 replacing = cookie >> 31;
2482 ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
2483 dmaq_id = cookie & 0xffff;
2485 spin_lock_bh(&efx->filter_lock);
2486 spec = efx_ef10_filter_entry_spec(table, ins_index);
2488 table->entry[ins_index].handle =
2489 MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
2491 spec->dmaq_id = dmaq_id;
2492 } else if (!replacing) {
2496 efx_ef10_filter_set_entry(table, ins_index, spec, 0);
2497 spin_unlock_bh(&efx->filter_lock);
2499 wake_up_all(&table->waitq);
2503 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
2504 unsigned long filter_idx,
2505 int rc, efx_dword_t *outbuf,
2506 size_t outlen_actual);
2508 static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
2509 unsigned int filter_idx)
2511 struct efx_ef10_filter_table *table = efx->filter_state;
2512 struct efx_filter_spec *spec =
2513 efx_ef10_filter_entry_spec(table, filter_idx);
2514 MCDI_DECLARE_BUF(inbuf,
2515 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
2516 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
2519 (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
2520 spec->priority != EFX_FILTER_PRI_HINT ||
2521 !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
2522 flow_id, filter_idx))
2525 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2526 MC_CMD_FILTER_OP_IN_OP_REMOVE);
2527 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
2528 table->entry[filter_idx].handle);
2529 if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
2530 efx_ef10_filter_rfs_expire_complete, filter_idx))
2533 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
2538 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
2539 unsigned long filter_idx,
2540 int rc, efx_dword_t *outbuf,
2541 size_t outlen_actual)
2543 struct efx_ef10_filter_table *table = efx->filter_state;
2544 struct efx_filter_spec *spec =
2545 efx_ef10_filter_entry_spec(table, filter_idx);
2547 spin_lock_bh(&efx->filter_lock);
2550 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
2552 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
2553 wake_up_all(&table->waitq);
2554 spin_unlock_bh(&efx->filter_lock);
2557 #endif /* CONFIG_RFS_ACCEL */
2559 static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags)
2561 int match_flags = 0;
2563 #define MAP_FLAG(gen_flag, mcdi_field) { \
2564 u32 old_mcdi_flags = mcdi_flags; \
2565 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
2566 mcdi_field ## _LBN); \
2567 if (mcdi_flags != old_mcdi_flags) \
2568 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \
2570 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
2571 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
2572 MAP_FLAG(REM_HOST, SRC_IP);
2573 MAP_FLAG(LOC_HOST, DST_IP);
2574 MAP_FLAG(REM_MAC, SRC_MAC);
2575 MAP_FLAG(REM_PORT, SRC_PORT);
2576 MAP_FLAG(LOC_MAC, DST_MAC);
2577 MAP_FLAG(LOC_PORT, DST_PORT);
2578 MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
2579 MAP_FLAG(INNER_VID, INNER_VLAN);
2580 MAP_FLAG(OUTER_VID, OUTER_VLAN);
2581 MAP_FLAG(IP_PROTO, IP_PROTO);
2584 /* Did we map them all? */
2591 static int efx_ef10_filter_table_probe(struct efx_nic *efx)
2593 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
2594 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
2595 unsigned int pd_match_pri, pd_match_count;
2596 struct efx_ef10_filter_table *table;
2600 table = kzalloc(sizeof(*table), GFP_KERNEL);
2604 /* Find out which RX filter types are supported, and their priorities */
2605 MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
2606 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
2607 rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
2608 inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
2612 pd_match_count = MCDI_VAR_ARRAY_LEN(
2613 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
2614 table->rx_match_count = 0;
2616 for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
2620 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
2622 rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags);
2624 netif_dbg(efx, probe, efx->net_dev,
2625 "%s: fw flags %#x pri %u not supported in driver\n",
2626 __func__, mcdi_flags, pd_match_pri);
2628 netif_dbg(efx, probe, efx->net_dev,
2629 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
2630 __func__, mcdi_flags, pd_match_pri,
2631 rc, table->rx_match_count);
2632 table->rx_match_flags[table->rx_match_count++] = rc;
2636 table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
2637 if (!table->entry) {
2642 efx->filter_state = table;
2643 init_waitqueue_head(&table->waitq);
2651 static void efx_ef10_filter_table_restore(struct efx_nic *efx)
2653 struct efx_ef10_filter_table *table = efx->filter_state;
2654 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2655 struct efx_filter_spec *spec;
2656 unsigned int filter_idx;
2657 bool failed = false;
2660 if (!nic_data->must_restore_filters)
2663 spin_lock_bh(&efx->filter_lock);
2665 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
2666 spec = efx_ef10_filter_entry_spec(table, filter_idx);
2670 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
2671 spin_unlock_bh(&efx->filter_lock);
2673 rc = efx_ef10_filter_push(efx, spec,
2674 &table->entry[filter_idx].handle,
2679 spin_lock_bh(&efx->filter_lock);
2682 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
2684 table->entry[filter_idx].spec &=
2685 ~EFX_EF10_FILTER_FLAG_BUSY;
2689 spin_unlock_bh(&efx->filter_lock);
2692 netif_err(efx, hw, efx->net_dev,
2693 "unable to restore all filters\n");
2695 nic_data->must_restore_filters = false;
2698 static void efx_ef10_filter_table_remove(struct efx_nic *efx)
2700 struct efx_ef10_filter_table *table = efx->filter_state;
2701 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2702 struct efx_filter_spec *spec;
2703 unsigned int filter_idx;
2706 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
2707 spec = efx_ef10_filter_entry_spec(table, filter_idx);
2711 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2712 efx_ef10_filter_is_exclusive(spec) ?
2713 MC_CMD_FILTER_OP_IN_OP_REMOVE :
2714 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
2715 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
2716 table->entry[filter_idx].handle);
2717 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
2724 vfree(table->entry);
2728 static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
2730 struct efx_ef10_filter_table *table = efx->filter_state;
2731 struct net_device *net_dev = efx->net_dev;
2732 struct efx_filter_spec spec;
2733 bool remove_failed = false;
2734 struct netdev_hw_addr *uc;
2735 struct netdev_hw_addr *mc;
2736 unsigned int filter_idx;
2739 if (!efx_dev_registered(efx))
2742 /* Mark old filters that may need to be removed */
2743 spin_lock_bh(&efx->filter_lock);
2744 n = table->stack_uc_count < 0 ? 1 : table->stack_uc_count;
2745 for (i = 0; i < n; i++) {
2746 filter_idx = table->stack_uc_list[i].id % HUNT_FILTER_TBL_ROWS;
2747 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_STACK_OLD;
2749 n = table->stack_mc_count < 0 ? 1 : table->stack_mc_count;
2750 for (i = 0; i < n; i++) {
2751 filter_idx = table->stack_mc_list[i].id % HUNT_FILTER_TBL_ROWS;
2752 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_STACK_OLD;
2754 spin_unlock_bh(&efx->filter_lock);
2756 /* Copy/convert the address lists; add the primary station
2757 * address and broadcast address
2759 netif_addr_lock_bh(net_dev);
2760 if (net_dev->flags & IFF_PROMISC ||
2761 netdev_uc_count(net_dev) >= EFX_EF10_FILTER_STACK_UC_MAX) {
2762 table->stack_uc_count = -1;
2764 table->stack_uc_count = 1 + netdev_uc_count(net_dev);
2765 memcpy(table->stack_uc_list[0].addr, net_dev->dev_addr,
2768 netdev_for_each_uc_addr(uc, net_dev) {
2769 memcpy(table->stack_uc_list[i].addr,
2770 uc->addr, ETH_ALEN);
2774 if (net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI) ||
2775 netdev_mc_count(net_dev) >= EFX_EF10_FILTER_STACK_MC_MAX) {
2776 table->stack_mc_count = -1;
2778 table->stack_mc_count = 1 + netdev_mc_count(net_dev);
2779 eth_broadcast_addr(table->stack_mc_list[0].addr);
2781 netdev_for_each_mc_addr(mc, net_dev) {
2782 memcpy(table->stack_mc_list[i].addr,
2783 mc->addr, ETH_ALEN);
2787 netif_addr_unlock_bh(net_dev);
2789 /* Insert/renew unicast filters */
2790 if (table->stack_uc_count >= 0) {
2791 for (i = 0; i < table->stack_uc_count; i++) {
2792 efx_filter_init_rx(&spec, EFX_FILTER_PRI_REQUIRED,
2793 EFX_FILTER_FLAG_RX_RSS |
2794 EFX_FILTER_FLAG_RX_STACK,
2796 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
2797 table->stack_uc_list[i].addr);
2798 rc = efx_ef10_filter_insert(efx, &spec, true);
2800 /* Fall back to unicast-promisc */
2802 efx_ef10_filter_remove_safe(
2803 efx, EFX_FILTER_PRI_REQUIRED,
2804 table->stack_uc_list[i].id);
2805 table->stack_uc_count = -1;
2808 table->stack_uc_list[i].id = rc;
2811 if (table->stack_uc_count < 0) {
2812 efx_filter_init_rx(&spec, EFX_FILTER_PRI_REQUIRED,
2813 EFX_FILTER_FLAG_RX_RSS |
2814 EFX_FILTER_FLAG_RX_STACK,
2816 efx_filter_set_uc_def(&spec);
2817 rc = efx_ef10_filter_insert(efx, &spec, true);
2820 table->stack_uc_count = 0;
2822 table->stack_uc_list[0].id = rc;
2826 /* Insert/renew multicast filters */
2827 if (table->stack_mc_count >= 0) {
2828 for (i = 0; i < table->stack_mc_count; i++) {
2829 efx_filter_init_rx(&spec, EFX_FILTER_PRI_REQUIRED,
2830 EFX_FILTER_FLAG_RX_RSS |
2831 EFX_FILTER_FLAG_RX_STACK,
2833 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
2834 table->stack_mc_list[i].addr);
2835 rc = efx_ef10_filter_insert(efx, &spec, true);
2837 /* Fall back to multicast-promisc */
2839 efx_ef10_filter_remove_safe(
2840 efx, EFX_FILTER_PRI_REQUIRED,
2841 table->stack_mc_list[i].id);
2842 table->stack_mc_count = -1;
2845 table->stack_mc_list[i].id = rc;
2848 if (table->stack_mc_count < 0) {
2849 efx_filter_init_rx(&spec, EFX_FILTER_PRI_REQUIRED,
2850 EFX_FILTER_FLAG_RX_RSS |
2851 EFX_FILTER_FLAG_RX_STACK,
2853 efx_filter_set_mc_def(&spec);
2854 rc = efx_ef10_filter_insert(efx, &spec, true);
2857 table->stack_mc_count = 0;
2859 table->stack_mc_list[0].id = rc;
2863 /* Remove filters that weren't renewed. Since nothing else
2864 * changes the STACK_OLD flag or removes these filters, we
2865 * don't need to hold the filter_lock while scanning for
2868 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
2869 if (ACCESS_ONCE(table->entry[i].spec) &
2870 EFX_EF10_FILTER_FLAG_STACK_OLD) {
2871 if (efx_ef10_filter_remove_internal(efx,
2872 EFX_FILTER_PRI_REQUIRED,
2874 remove_failed = true;
2877 WARN_ON(remove_failed);
2880 static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
2882 efx_ef10_filter_sync_rx_mode(efx);
2884 return efx_mcdi_set_mac(efx);
2887 #ifdef CONFIG_SFC_MTD
2889 struct efx_ef10_nvram_type_info {
2890 u16 type, type_mask;
2895 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
2896 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" },
2897 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" },
2898 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" },
2899 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" },
2900 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" },
2901 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" },
2902 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" },
2903 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" },
2904 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" },
2905 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" },
2908 static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
2909 struct efx_mcdi_mtd_partition *part,
2912 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
2913 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
2914 const struct efx_ef10_nvram_type_info *info;
2915 size_t size, erase_size, outlen;
2919 for (info = efx_ef10_nvram_types; ; info++) {
2921 efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
2923 if ((type & ~info->type_mask) == info->type)
2926 if (info->port != efx_port_num(efx))
2929 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
2933 return -ENODEV; /* hide it */
2935 part->nvram_type = type;
2937 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
2938 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
2939 outbuf, sizeof(outbuf), &outlen);
2942 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
2944 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
2945 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
2946 part->fw_subtype = MCDI_DWORD(outbuf,
2947 NVRAM_METADATA_OUT_SUBTYPE);
2949 part->common.dev_type_name = "EF10 NVRAM manager";
2950 part->common.type_name = info->name;
2952 part->common.mtd.type = MTD_NORFLASH;
2953 part->common.mtd.flags = MTD_CAP_NORFLASH;
2954 part->common.mtd.size = size;
2955 part->common.mtd.erasesize = erase_size;
2960 static int efx_ef10_mtd_probe(struct efx_nic *efx)
2962 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
2963 struct efx_mcdi_mtd_partition *parts;
2964 size_t outlen, n_parts_total, i, n_parts;
2970 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
2971 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
2972 outbuf, sizeof(outbuf), &outlen);
2975 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
2978 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
2980 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
2983 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
2988 for (i = 0; i < n_parts_total; i++) {
2989 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
2991 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
2994 else if (rc != -ENODEV)
2998 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
3005 #endif /* CONFIG_SFC_MTD */
3007 static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
3009 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
3012 const struct efx_nic_type efx_hunt_a0_nic_type = {
3013 .mem_map_size = efx_ef10_mem_map_size,
3014 .probe = efx_ef10_probe,
3015 .remove = efx_ef10_remove,
3016 .dimension_resources = efx_ef10_dimension_resources,
3017 .init = efx_ef10_init_nic,
3018 .fini = efx_port_dummy_op_void,
3019 .map_reset_reason = efx_mcdi_map_reset_reason,
3020 .map_reset_flags = efx_ef10_map_reset_flags,
3021 .reset = efx_mcdi_reset,
3022 .probe_port = efx_mcdi_port_probe,
3023 .remove_port = efx_mcdi_port_remove,
3024 .fini_dmaq = efx_ef10_fini_dmaq,
3025 .describe_stats = efx_ef10_describe_stats,
3026 .update_stats = efx_ef10_update_stats,
3027 .start_stats = efx_mcdi_mac_start_stats,
3028 .stop_stats = efx_mcdi_mac_stop_stats,
3029 .set_id_led = efx_mcdi_set_id_led,
3030 .push_irq_moderation = efx_ef10_push_irq_moderation,
3031 .reconfigure_mac = efx_ef10_mac_reconfigure,
3032 .check_mac_fault = efx_mcdi_mac_check_fault,
3033 .reconfigure_port = efx_mcdi_port_reconfigure,
3034 .get_wol = efx_ef10_get_wol,
3035 .set_wol = efx_ef10_set_wol,
3036 .resume_wol = efx_port_dummy_op_void,
3037 /* TODO: test_chip */
3038 .test_nvram = efx_mcdi_nvram_test_all,
3039 .mcdi_request = efx_ef10_mcdi_request,
3040 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
3041 .mcdi_read_response = efx_ef10_mcdi_read_response,
3042 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
3043 .irq_enable_master = efx_port_dummy_op_void,
3044 .irq_test_generate = efx_ef10_irq_test_generate,
3045 .irq_disable_non_ev = efx_port_dummy_op_void,
3046 .irq_handle_msi = efx_ef10_msi_interrupt,
3047 .irq_handle_legacy = efx_ef10_legacy_interrupt,
3048 .tx_probe = efx_ef10_tx_probe,
3049 .tx_init = efx_ef10_tx_init,
3050 .tx_remove = efx_ef10_tx_remove,
3051 .tx_write = efx_ef10_tx_write,
3052 .rx_push_indir_table = efx_ef10_rx_push_indir_table,
3053 .rx_probe = efx_ef10_rx_probe,
3054 .rx_init = efx_ef10_rx_init,
3055 .rx_remove = efx_ef10_rx_remove,
3056 .rx_write = efx_ef10_rx_write,
3057 .rx_defer_refill = efx_ef10_rx_defer_refill,
3058 .ev_probe = efx_ef10_ev_probe,
3059 .ev_init = efx_ef10_ev_init,
3060 .ev_fini = efx_ef10_ev_fini,
3061 .ev_remove = efx_ef10_ev_remove,
3062 .ev_process = efx_ef10_ev_process,
3063 .ev_read_ack = efx_ef10_ev_read_ack,
3064 .ev_test_generate = efx_ef10_ev_test_generate,
3065 .filter_table_probe = efx_ef10_filter_table_probe,
3066 .filter_table_restore = efx_ef10_filter_table_restore,
3067 .filter_table_remove = efx_ef10_filter_table_remove,
3068 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
3069 .filter_insert = efx_ef10_filter_insert,
3070 .filter_remove_safe = efx_ef10_filter_remove_safe,
3071 .filter_get_safe = efx_ef10_filter_get_safe,
3072 .filter_clear_rx = efx_ef10_filter_clear_rx,
3073 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
3074 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
3075 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
3076 #ifdef CONFIG_RFS_ACCEL
3077 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
3078 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
3080 #ifdef CONFIG_SFC_MTD
3081 .mtd_probe = efx_ef10_mtd_probe,
3082 .mtd_rename = efx_mcdi_mtd_rename,
3083 .mtd_read = efx_mcdi_mtd_read,
3084 .mtd_erase = efx_mcdi_mtd_erase,
3085 .mtd_write = efx_mcdi_mtd_write,
3086 .mtd_sync = efx_mcdi_mtd_sync,
3088 .ptp_write_host_time = efx_ef10_ptp_write_host_time,
3090 .revision = EFX_REV_HUNT_A0,
3091 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
3092 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
3093 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
3094 .can_rx_scatter = true,
3095 .always_rx_scatter = true,
3096 .max_interrupt_mode = EFX_INT_MODE_MSIX,
3097 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
3098 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3099 NETIF_F_RXHASH | NETIF_F_NTUPLE),
3101 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,