drivers/net/ethernet/sfc/falcon.c

   1 /****************************************************************************
   2  * Driver for Solarflare network controllers and boards
   3  * Copyright 2005-2006 Fen Systems Ltd.
   4  * Copyright 2006-2013 Solarflare Communications Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation, incorporated herein by reference.
   9  */
  10
  11 #include <linux/bitops.h>
  12 #include <linux/delay.h>
  13 #include <linux/pci.h>
  14 #include <linux/module.h>
  15 #include <linux/seq_file.h>
  16 #include <linux/i2c.h>
  17 #include <linux/mii.h>
  18 #include <linux/slab.h>
  19 #include "net_driver.h"
  20 #include "bitfield.h"
  21 #include "efx.h"
  22 #include "nic.h"
  23 #include "farch_regs.h"
  24 #include "io.h"
  25 #include "phy.h"
  26 #include "workarounds.h"
  27 #include "selftest.h"
  28 #include "mdio_10g.h"
  29
  30 /* Hardware control for SFC4000 (aka Falcon). */
  31
  32 /**************************************************************************
  33  *
  34  * NIC stats
  35  *
  36  **************************************************************************
  37  */
  38
  39 #define FALCON_MAC_STATS_SIZE 0x100
  40
  41 #define XgRxOctets_offset 0x0
  42 #define XgRxOctets_WIDTH 48
  43 #define XgRxOctetsOK_offset 0x8
  44 #define XgRxOctetsOK_WIDTH 48
  45 #define XgRxPkts_offset 0x10
  46 #define XgRxPkts_WIDTH 32
  47 #define XgRxPktsOK_offset 0x14
  48 #define XgRxPktsOK_WIDTH 32
  49 #define XgRxBroadcastPkts_offset 0x18
  50 #define XgRxBroadcastPkts_WIDTH 32
  51 #define XgRxMulticastPkts_offset 0x1C
  52 #define XgRxMulticastPkts_WIDTH 32
  53 #define XgRxUnicastPkts_offset 0x20
  54 #define XgRxUnicastPkts_WIDTH 32
  55 #define XgRxUndersizePkts_offset 0x24
  56 #define XgRxUndersizePkts_WIDTH 32
  57 #define XgRxOversizePkts_offset 0x28
  58 #define XgRxOversizePkts_WIDTH 32
  59 #define XgRxJabberPkts_offset 0x2C
  60 #define XgRxJabberPkts_WIDTH 32
  61 #define XgRxUndersizeFCSerrorPkts_offset 0x30
  62 #define XgRxUndersizeFCSerrorPkts_WIDTH 32
  63 #define XgRxDropEvents_offset 0x34
  64 #define XgRxDropEvents_WIDTH 32
  65 #define XgRxFCSerrorPkts_offset 0x38
  66 #define XgRxFCSerrorPkts_WIDTH 32
  67 #define XgRxAlignError_offset 0x3C
  68 #define XgRxAlignError_WIDTH 32
  69 #define XgRxSymbolError_offset 0x40
  70 #define XgRxSymbolError_WIDTH 32
  71 #define XgRxInternalMACError_offset 0x44
  72 #define XgRxInternalMACError_WIDTH 32
  73 #define XgRxControlPkts_offset 0x48
  74 #define XgRxControlPkts_WIDTH 32
  75 #define XgRxPausePkts_offset 0x4C
  76 #define XgRxPausePkts_WIDTH 32
  77 #define XgRxPkts64Octets_offset 0x50
  78 #define XgRxPkts64Octets_WIDTH 32
  79 #define XgRxPkts65to127Octets_offset 0x54
  80 #define XgRxPkts65to127Octets_WIDTH 32
  81 #define XgRxPkts128to255Octets_offset 0x58
  82 #define XgRxPkts128to255Octets_WIDTH 32
  83 #define XgRxPkts256to511Octets_offset 0x5C
  84 #define XgRxPkts256to511Octets_WIDTH 32
  85 #define XgRxPkts512to1023Octets_offset 0x60
  86 #define XgRxPkts512to1023Octets_WIDTH 32
  87 #define XgRxPkts1024to15xxOctets_offset 0x64
  88 #define XgRxPkts1024to15xxOctets_WIDTH 32
  89 #define XgRxPkts15xxtoMaxOctets_offset 0x68
  90 #define XgRxPkts15xxtoMaxOctets_WIDTH 32
  91 #define XgRxLengthError_offset 0x6C
  92 #define XgRxLengthError_WIDTH 32
  93 #define XgTxPkts_offset 0x80
  94 #define XgTxPkts_WIDTH 32
  95 #define XgTxOctets_offset 0x88
  96 #define XgTxOctets_WIDTH 48
  97 #define XgTxMulticastPkts_offset 0x90
  98 #define XgTxMulticastPkts_WIDTH 32
  99 #define XgTxBroadcastPkts_offset 0x94
 100 #define XgTxBroadcastPkts_WIDTH 32
 101 #define XgTxUnicastPkts_offset 0x98
 102 #define XgTxUnicastPkts_WIDTH 32
 103 #define XgTxControlPkts_offset 0x9C
 104 #define XgTxControlPkts_WIDTH 32
 105 #define XgTxPausePkts_offset 0xA0
 106 #define XgTxPausePkts_WIDTH 32
 107 #define XgTxPkts64Octets_offset 0xA4
 108 #define XgTxPkts64Octets_WIDTH 32
 109 #define XgTxPkts65to127Octets_offset 0xA8
 110 #define XgTxPkts65to127Octets_WIDTH 32
 111 #define XgTxPkts128to255Octets_offset 0xAC
 112 #define XgTxPkts128to255Octets_WIDTH 32
 113 #define XgTxPkts256to511Octets_offset 0xB0
 114 #define XgTxPkts256to511Octets_WIDTH 32
 115 #define XgTxPkts512to1023Octets_offset 0xB4
 116 #define XgTxPkts512to1023Octets_WIDTH 32
 117 #define XgTxPkts1024to15xxOctets_offset 0xB8
 118 #define XgTxPkts1024to15xxOctets_WIDTH 32
 119 #define XgTxPkts1519toMaxOctets_offset 0xBC
 120 #define XgTxPkts1519toMaxOctets_WIDTH 32
 121 #define XgTxUndersizePkts_offset 0xC0
 122 #define XgTxUndersizePkts_WIDTH 32
 123 #define XgTxOversizePkts_offset 0xC4
 124 #define XgTxOversizePkts_WIDTH 32
 125 #define XgTxNonTcpUdpPkt_offset 0xC8
 126 #define XgTxNonTcpUdpPkt_WIDTH 16
 127 #define XgTxMacSrcErrPkt_offset 0xCC
 128 #define XgTxMacSrcErrPkt_WIDTH 16
 129 #define XgTxIpSrcErrPkt_offset 0xD0
 130 #define XgTxIpSrcErrPkt_WIDTH 16
 131 #define XgDmaDone_offset 0xD4
 132 #define XgDmaDone_WIDTH 32
 133
 134 #define FALCON_XMAC_STATS_DMA_FLAG(efx)                         \
 135         (*(u32 *)((efx)->stats_buffer.addr + XgDmaDone_offset))
 136
 137 #define FALCON_DMA_STAT(ext_name, hw_name)                              \
 138         [FALCON_STAT_ ## ext_name] =                                    \
 139         { #ext_name,                                                    \
 140           /* 48-bit stats are zero-padded to 64 on DMA */               \
 141           hw_name ## _ ## WIDTH == 48 ? 64 : hw_name ## _ ## WIDTH,     \
 142           hw_name ## _ ## offset }
 143 #define FALCON_OTHER_STAT(ext_name)                                     \
 144         [FALCON_STAT_ ## ext_name] = { #ext_name, 0, 0 }
 145
 146 static const struct efx_hw_stat_desc falcon_stat_desc[FALCON_STAT_COUNT] = {
 147         FALCON_DMA_STAT(tx_bytes, XgTxOctets),
 148         FALCON_DMA_STAT(tx_packets, XgTxPkts),
 149         FALCON_DMA_STAT(tx_pause, XgTxPausePkts),
 150         FALCON_DMA_STAT(tx_control, XgTxControlPkts),
 151         FALCON_DMA_STAT(tx_unicast, XgTxUnicastPkts),
 152         FALCON_DMA_STAT(tx_multicast, XgTxMulticastPkts),
 153         FALCON_DMA_STAT(tx_broadcast, XgTxBroadcastPkts),
 154         FALCON_DMA_STAT(tx_lt64, XgTxUndersizePkts),
 155         FALCON_DMA_STAT(tx_64, XgTxPkts64Octets),
 156         FALCON_DMA_STAT(tx_65_to_127, XgTxPkts65to127Octets),
 157         FALCON_DMA_STAT(tx_128_to_255, XgTxPkts128to255Octets),
 158         FALCON_DMA_STAT(tx_256_to_511, XgTxPkts256to511Octets),
 159         FALCON_DMA_STAT(tx_512_to_1023, XgTxPkts512to1023Octets),
 160         FALCON_DMA_STAT(tx_1024_to_15xx, XgTxPkts1024to15xxOctets),
 161         FALCON_DMA_STAT(tx_15xx_to_jumbo, XgTxPkts1519toMaxOctets),
 162         FALCON_DMA_STAT(tx_gtjumbo, XgTxOversizePkts),
 163         FALCON_DMA_STAT(tx_non_tcpudp, XgTxNonTcpUdpPkt),
 164         FALCON_DMA_STAT(tx_mac_src_error, XgTxMacSrcErrPkt),
 165         FALCON_DMA_STAT(tx_ip_src_error, XgTxIpSrcErrPkt),
 166         FALCON_DMA_STAT(rx_bytes, XgRxOctets),
 167         FALCON_DMA_STAT(rx_good_bytes, XgRxOctetsOK),
 168         FALCON_OTHER_STAT(rx_bad_bytes),
 169         FALCON_DMA_STAT(rx_packets, XgRxPkts),
 170         FALCON_DMA_STAT(rx_good, XgRxPktsOK),
 171         FALCON_DMA_STAT(rx_bad, XgRxFCSerrorPkts),
 172         FALCON_DMA_STAT(rx_pause, XgRxPausePkts),
 173         FALCON_DMA_STAT(rx_control, XgRxControlPkts),
 174         FALCON_DMA_STAT(rx_unicast, XgRxUnicastPkts),
 175         FALCON_DMA_STAT(rx_multicast, XgRxMulticastPkts),
 176         FALCON_DMA_STAT(rx_broadcast, XgRxBroadcastPkts),
 177         FALCON_DMA_STAT(rx_lt64, XgRxUndersizePkts),
 178         FALCON_DMA_STAT(rx_64, XgRxPkts64Octets),
 179         FALCON_DMA_STAT(rx_65_to_127, XgRxPkts65to127Octets),
 180         FALCON_DMA_STAT(rx_128_to_255, XgRxPkts128to255Octets),
 181         FALCON_DMA_STAT(rx_256_to_511, XgRxPkts256to511Octets),
 182         FALCON_DMA_STAT(rx_512_to_1023, XgRxPkts512to1023Octets),
 183         FALCON_DMA_STAT(rx_1024_to_15xx, XgRxPkts1024to15xxOctets),
 184         FALCON_DMA_STAT(rx_15xx_to_jumbo, XgRxPkts15xxtoMaxOctets),
 185         FALCON_DMA_STAT(rx_gtjumbo, XgRxOversizePkts),
 186         FALCON_DMA_STAT(rx_bad_lt64, XgRxUndersizeFCSerrorPkts),
 187         FALCON_DMA_STAT(rx_bad_gtjumbo, XgRxJabberPkts),
 188         FALCON_DMA_STAT(rx_overflow, XgRxDropEvents),
 189         FALCON_DMA_STAT(rx_symbol_error, XgRxSymbolError),
 190         FALCON_DMA_STAT(rx_align_error, XgRxAlignError),
 191         FALCON_DMA_STAT(rx_length_error, XgRxLengthError),
 192         FALCON_DMA_STAT(rx_internal_error, XgRxInternalMACError),
 193         FALCON_OTHER_STAT(rx_nodesc_drop_cnt),
 194 };
 195 static const unsigned long falcon_stat_mask[] = {
 196         [0 ... BITS_TO_LONGS(FALCON_STAT_COUNT) - 1] = ~0UL,
 197 };
 198
 199 /**************************************************************************
 200  *
 201  * Basic SPI command set and bit definitions
 202  *
 203  *************************************************************************/
 204
 205 #define SPI_WRSR 0x01           /* Write status register */
 206 #define SPI_WRITE 0x02          /* Write data to memory array */
 207 #define SPI_READ 0x03           /* Read data from memory array */
 208 #define SPI_WRDI 0x04           /* Reset write enable latch */
 209 #define SPI_RDSR 0x05           /* Read status register */
 210 #define SPI_WREN 0x06           /* Set write enable latch */
 211 #define SPI_SST_EWSR 0x50       /* SST: Enable write to status register */
 212
 213 #define SPI_STATUS_WPEN 0x80    /* Write-protect pin enabled */
 214 #define SPI_STATUS_BP2 0x10     /* Block protection bit 2 */
 215 #define SPI_STATUS_BP1 0x08     /* Block protection bit 1 */
 216 #define SPI_STATUS_BP0 0x04     /* Block protection bit 0 */
 217 #define SPI_STATUS_WEN 0x02     /* State of the write enable latch */
 218 #define SPI_STATUS_NRDY 0x01    /* Device busy flag */
 219
 220 /**************************************************************************
 221  *
 222  * Non-volatile memory layout
 223  *
 224  **************************************************************************
 225  */
 226
 227 /* SFC4000 flash is partitioned into:
 228  *     0-0x400       chip and board config (see struct falcon_nvconfig)
 229  *     0x400-0x8000  unused (or may contain VPD if EEPROM not present)
 230  *     0x8000-end    boot code (mapped to PCI expansion ROM)
 231  * SFC4000 small EEPROM (size < 0x400) is used for VPD only.
 232  * SFC4000 large EEPROM (size >= 0x400) is partitioned into:
 233  *     0-0x400       chip and board config
 234  *     configurable  VPD
 235  *     0x800-0x1800  boot config
 236  * Aside from the chip and board config, all of these are optional and may
 237  * be absent or truncated depending on the devices used.
 238  */
 239 #define FALCON_NVCONFIG_END 0x400U
 240 #define FALCON_FLASH_BOOTCODE_START 0x8000U
 241 #define FALCON_EEPROM_BOOTCONFIG_START 0x800U
 242 #define FALCON_EEPROM_BOOTCONFIG_END 0x1800U
 243
 244 /* Board configuration v2 (v1 is obsolete; later versions are compatible) */
 245 struct falcon_nvconfig_board_v2 {
 246         __le16 nports;
 247         u8 port0_phy_addr;
 248         u8 port0_phy_type;
 249         u8 port1_phy_addr;
 250         u8 port1_phy_type;
 251         __le16 asic_sub_revision;
 252         __le16 board_revision;
 253 } __packed;
 254
 255 /* Board configuration v3 extra information */
 256 struct falcon_nvconfig_board_v3 {
 257         __le32 spi_device_type[2];
 258 } __packed;
 259
 260 /* Bit numbers for spi_device_type */
 261 #define SPI_DEV_TYPE_SIZE_LBN 0
 262 #define SPI_DEV_TYPE_SIZE_WIDTH 5
 263 #define SPI_DEV_TYPE_ADDR_LEN_LBN 6
 264 #define SPI_DEV_TYPE_ADDR_LEN_WIDTH 2
 265 #define SPI_DEV_TYPE_ERASE_CMD_LBN 8
 266 #define SPI_DEV_TYPE_ERASE_CMD_WIDTH 8
 267 #define SPI_DEV_TYPE_ERASE_SIZE_LBN 16
 268 #define SPI_DEV_TYPE_ERASE_SIZE_WIDTH 5
 269 #define SPI_DEV_TYPE_BLOCK_SIZE_LBN 24
 270 #define SPI_DEV_TYPE_BLOCK_SIZE_WIDTH 5
 271 #define SPI_DEV_TYPE_FIELD(type, field)                                 \
 272         (((type) >> EFX_LOW_BIT(field)) & EFX_MASK32(EFX_WIDTH(field)))
 273
 274 #define FALCON_NVCONFIG_OFFSET 0x300
 275
 276 #define FALCON_NVCONFIG_BOARD_MAGIC_NUM 0xFA1C
 277 struct falcon_nvconfig {
 278         efx_oword_t ee_vpd_cfg_reg;                     /* 0x300 */
 279         u8 mac_address[2][8];                   /* 0x310 */
 280         efx_oword_t pcie_sd_ctl0123_reg;                /* 0x320 */
 281         efx_oword_t pcie_sd_ctl45_reg;                  /* 0x330 */
 282         efx_oword_t pcie_pcs_ctl_stat_reg;              /* 0x340 */
 283         efx_oword_t hw_init_reg;                        /* 0x350 */
 284         efx_oword_t nic_stat_reg;                       /* 0x360 */
 285         efx_oword_t glb_ctl_reg;                        /* 0x370 */
 286         efx_oword_t srm_cfg_reg;                        /* 0x380 */
 287         efx_oword_t spare_reg;                          /* 0x390 */
 288         __le16 board_magic_num;                 /* 0x3A0 */
 289         __le16 board_struct_ver;
 290         __le16 board_checksum;
 291         struct falcon_nvconfig_board_v2 board_v2;
 292         efx_oword_t ee_base_page_reg;                   /* 0x3B0 */
 293         struct falcon_nvconfig_board_v3 board_v3;       /* 0x3C0 */
 294 } __packed;
 295
 296 /*************************************************************************/
 297
 298 static int falcon_reset_hw(struct efx_nic *efx, enum reset_type method);
 299 static void falcon_reconfigure_mac_wrapper(struct efx_nic *efx);
 300
 301 static const unsigned int
 302 /* "Large" EEPROM device: Atmel AT25640 or similar
 303  * 8 KB, 16-bit address, 32 B write block */
 304 large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN)
 305                      | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
 306                      | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)),
 307 /* Default flash device: Atmel AT25F1024
 308  * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */
 309 default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN)
 310                       | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
 311                       | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
 312                       | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
 313                       | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN));
 314
 315 /**************************************************************************
 316  *
 317  * I2C bus - this is a bit-bashing interface using GPIO pins
 318  * Note that it uses the output enables to tristate the outputs
 319  * SDA is the data pin and SCL is the clock
 320  *
 321  **************************************************************************
 322  */
 323 static void falcon_setsda(void *data, int state)
 324 {
 325         struct efx_nic *efx = (struct efx_nic *)data;
 326         efx_oword_t reg;
 327
 328         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
 329         EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state);
 330         efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
 331 }
 332
 333 static void falcon_setscl(void *data, int state)
 334 {
 335         struct efx_nic *efx = (struct efx_nic *)data;
 336         efx_oword_t reg;
 337
 338         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
 339         EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state);
 340         efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
 341 }
 342
 343 static int falcon_getsda(void *data)
 344 {
 345         struct efx_nic *efx = (struct efx_nic *)data;
 346         efx_oword_t reg;
 347
 348         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
 349         return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN);
 350 }
 351
 352 static int falcon_getscl(void *data)
 353 {
 354         struct efx_nic *efx = (struct efx_nic *)data;
 355         efx_oword_t reg;
 356
 357         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
 358         return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN);
 359 }
 360
 361 static const struct i2c_algo_bit_data falcon_i2c_bit_operations = {
 362         .setsda         = falcon_setsda,
 363         .setscl         = falcon_setscl,
 364         .getsda         = falcon_getsda,
 365         .getscl         = falcon_getscl,
 366         .udelay         = 5,
 367         /* Wait up to 50 ms for slave to let us pull SCL high */
 368         .timeout        = DIV_ROUND_UP(HZ, 20),
 369 };
 370
 371 static void falcon_push_irq_moderation(struct efx_channel *channel)
 372 {
 373         efx_dword_t timer_cmd;
 374         struct efx_nic *efx = channel->efx;
 375
 376         /* Set timer register */
 377         if (channel->irq_moderation) {
 378                 EFX_POPULATE_DWORD_2(timer_cmd,
 379                                      FRF_AB_TC_TIMER_MODE,
 380                                      FFE_BB_TIMER_MODE_INT_HLDOFF,
 381                                      FRF_AB_TC_TIMER_VAL,
 382                                      channel->irq_moderation - 1);
 383         } else {
 384                 EFX_POPULATE_DWORD_2(timer_cmd,
 385                                      FRF_AB_TC_TIMER_MODE,
 386                                      FFE_BB_TIMER_MODE_DIS,
 387                                      FRF_AB_TC_TIMER_VAL, 0);
 388         }
 389         BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0);
 390         efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
 391                                channel->channel);
 392 }
 393
 394 static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx);
 395
 396 static void falcon_prepare_flush(struct efx_nic *efx)
 397 {
 398         falcon_deconfigure_mac_wrapper(efx);
 399
 400         /* Wait for the tx and rx fifo's to get to the next packet boundary
 401          * (~1ms without back-pressure), then to drain the remainder of the
 402          * fifo's at data path speeds (negligible), with a healthy margin. */
 403         msleep(10);
 404 }
 405
 406 /* Acknowledge a legacy interrupt from Falcon
 407  *
 408  * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
 409  *
 410  * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
 411  * BIU. Interrupt acknowledge is read sensitive so must write instead
 412  * (then read to ensure the BIU collector is flushed)
 413  *
 414  * NB most hardware supports MSI interrupts
 415  */
 416 static inline void falcon_irq_ack_a1(struct efx_nic *efx)
 417 {
 418         efx_dword_t reg;
 419
 420         EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e);
 421         efx_writed(efx, &reg, FR_AA_INT_ACK_KER);
 422         efx_readd(efx, &reg, FR_AA_WORK_AROUND_BROKEN_PCI_READS);
 423 }
 424
 425 static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
 426 {
 427         struct efx_nic *efx = dev_id;
 428         efx_oword_t *int_ker = efx->irq_status.addr;
 429         int syserr;
 430         int queues;
 431
 432         /* Check to see if this is our interrupt.  If it isn't, we
 433          * exit without having touched the hardware.
 434          */
 435         if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
 436                 netif_vdbg(efx, intr, efx->net_dev,
 437                            "IRQ %d on CPU %d not for me\n", irq,
 438                            raw_smp_processor_id());
 439                 return IRQ_NONE;
 440         }
 441         efx->last_irq_cpu = raw_smp_processor_id();
 442         netif_vdbg(efx, intr, efx->net_dev,
 443                    "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
 444                    irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
 445
 446         if (!likely(ACCESS_ONCE(efx->irq_soft_enabled)))
 447                 return IRQ_HANDLED;
 448
 449         /* Check to see if we have a serious error condition */
 450         syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
 451         if (unlikely(syserr))
 452                 return efx_farch_fatal_interrupt(efx);
 453
 454         /* Determine interrupting queues, clear interrupt status
 455          * register and acknowledge the device interrupt.
 456          */
 457         BUILD_BUG_ON(FSF_AZ_NET_IVEC_INT_Q_WIDTH > EFX_MAX_CHANNELS);
 458         queues = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_INT_Q);
 459         EFX_ZERO_OWORD(*int_ker);
 460         wmb(); /* Ensure the vector is cleared before interrupt ack */
 461         falcon_irq_ack_a1(efx);
 462
 463         if (queues & 1)
 464                 efx_schedule_channel_irq(efx_get_channel(efx, 0));
 465         if (queues & 2)
 466                 efx_schedule_channel_irq(efx_get_channel(efx, 1));
 467         return IRQ_HANDLED;
 468 }
 469
 470 /**************************************************************************
 471  *
 472  * RSS
 473  *
 474  **************************************************************************
 475  */
 476
 477 static void falcon_b0_rx_push_rss_config(struct efx_nic *efx)
 478 {
 479         efx_oword_t temp;
 480
 481         /* Set hash key for IPv4 */
 482         memcpy(&temp, efx->rx_hash_key, sizeof(temp));
 483         efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
 484
 485         efx_farch_rx_push_indir_table(efx);
 486 }
 487
 488 /**************************************************************************
 489  *
 490  * EEPROM/flash
 491  *
 492  **************************************************************************
 493  */
 494
 495 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
 496
 497 static int falcon_spi_poll(struct efx_nic *efx)
 498 {
 499         efx_oword_t reg;
 500         efx_reado(efx, &reg, FR_AB_EE_SPI_HCMD);
 501         return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0;
 502 }
 503
 504 /* Wait for SPI command completion */
 505 static int falcon_spi_wait(struct efx_nic *efx)
 506 {
 507         /* Most commands will finish quickly, so we start polling at
 508          * very short intervals.  Sometimes the command may have to
 509          * wait for VPD or expansion ROM access outside of our
 510          * control, so we allow up to 100 ms. */
 511         unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10);
 512         int i;
 513
 514         for (i = 0; i < 10; i++) {
 515                 if (!falcon_spi_poll(efx))
 516                         return 0;
 517                 udelay(10);
 518         }
 519
 520         for (;;) {
 521                 if (!falcon_spi_poll(efx))
 522                         return 0;
 523                 if (time_after_eq(jiffies, timeout)) {
 524                         netif_err(efx, hw, efx->net_dev,
 525                                   "timed out waiting for SPI\n");
 526                         return -ETIMEDOUT;
 527                 }
 528                 schedule_timeout_uninterruptible(1);
 529         }
 530 }
 531
 532 static int
 533 falcon_spi_cmd(struct efx_nic *efx, const struct falcon_spi_device *spi,
 534                unsigned int command, int address,
 535                const void *in, void *out, size_t len)
 536 {
 537         bool addressed = (address >= 0);
 538         bool reading = (out != NULL);
 539         efx_oword_t reg;
 540         int rc;
 541
 542         /* Input validation */
 543         if (len > FALCON_SPI_MAX_LEN)
 544                 return -EINVAL;
 545
 546         /* Check that previous command is not still running */
 547         rc = falcon_spi_poll(efx);
 548         if (rc)
 549                 return rc;
 550
 551         /* Program address register, if we have an address */
 552         if (addressed) {
 553                 EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address);
 554                 efx_writeo(efx, &reg, FR_AB_EE_SPI_HADR);
 555         }
 556
 557         /* Program data register, if we have data */
 558         if (in != NULL) {
 559                 memcpy(&reg, in, len);
 560                 efx_writeo(efx, &reg, FR_AB_EE_SPI_HDATA);
 561         }
 562
 563         /* Issue read/write command */
 564         EFX_POPULATE_OWORD_7(reg,
 565                              FRF_AB_EE_SPI_HCMD_CMD_EN, 1,
 566                              FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id,
 567                              FRF_AB_EE_SPI_HCMD_DABCNT, len,
 568                              FRF_AB_EE_SPI_HCMD_READ, reading,
 569                              FRF_AB_EE_SPI_HCMD_DUBCNT, 0,
 570                              FRF_AB_EE_SPI_HCMD_ADBCNT,
 571                              (addressed ? spi->addr_len : 0),
 572                              FRF_AB_EE_SPI_HCMD_ENC, command);
 573         efx_writeo(efx, &reg, FR_AB_EE_SPI_HCMD);
 574
 575         /* Wait for read/write to complete */
 576         rc = falcon_spi_wait(efx);
 577         if (rc)
 578                 return rc;
 579
 580         /* Read data */
 581         if (out != NULL) {
 582                 efx_reado(efx, &reg, FR_AB_EE_SPI_HDATA);
 583                 memcpy(out, &reg, len);
 584         }
 585
 586         return 0;
 587 }
 588
 589 static inline u8
 590 falcon_spi_munge_command(const struct falcon_spi_device *spi,
 591                          const u8 command, const unsigned int address)
 592 {
 593         return command | (((address >> 8) & spi->munge_address) << 3);
 594 }
 595
 596 static int
 597 falcon_spi_read(struct efx_nic *efx, const struct falcon_spi_device *spi,
 598                 loff_t start, size_t len, size_t *retlen, u8 *buffer)
 599 {
 600         size_t block_len, pos = 0;
 601         unsigned int command;
 602         int rc = 0;
 603
 604         while (pos < len) {
 605                 block_len = min(len - pos, FALCON_SPI_MAX_LEN);
 606
 607                 command = falcon_spi_munge_command(spi, SPI_READ, start + pos);
 608                 rc = falcon_spi_cmd(efx, spi, command, start + pos, NULL,
 609                                     buffer + pos, block_len);
 610                 if (rc)
 611                         break;
 612                 pos += block_len;
 613
 614                 /* Avoid locking up the system */
 615                 cond_resched();
 616                 if (signal_pending(current)) {
 617                         rc = -EINTR;
 618                         break;
 619                 }
 620         }
 621
 622         if (retlen)
 623                 *retlen = pos;
 624         return rc;
 625 }
 626
 627 #ifdef CONFIG_SFC_MTD
 628
 629 struct falcon_mtd_partition {
 630         struct efx_mtd_partition common;
 631         const struct falcon_spi_device *spi;
 632         size_t offset;
 633 };
 634
 635 #define to_falcon_mtd_partition(mtd)                            \
 636         container_of(mtd, struct falcon_mtd_partition, common.mtd)
 637
 638 static size_t
 639 falcon_spi_write_limit(const struct falcon_spi_device *spi, size_t start)
 640 {
 641         return min(FALCON_SPI_MAX_LEN,
 642                    (spi->block_size - (start & (spi->block_size - 1))));
 643 }
 644
 645 /* Wait up to 10 ms for buffered write completion */
 646 static int
 647 falcon_spi_wait_write(struct efx_nic *efx, const struct falcon_spi_device *spi)
 648 {
 649         unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100);
 650         u8 status;
 651         int rc;
 652
 653         for (;;) {
 654                 rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL,
 655                                     &status, sizeof(status));
 656                 if (rc)
 657                         return rc;
 658                 if (!(status & SPI_STATUS_NRDY))
 659                         return 0;
 660                 if (time_after_eq(jiffies, timeout)) {
 661                         netif_err(efx, hw, efx->net_dev,
 662                                   "SPI write timeout on device %d"
 663                                   " last status=0x%02x\n",
 664                                   spi->device_id, status);
 665                         return -ETIMEDOUT;
 666                 }
 667                 schedule_timeout_uninterruptible(1);
 668         }
 669 }
 670
 671 static int
 672 falcon_spi_write(struct efx_nic *efx, const struct falcon_spi_device *spi,
 673                  loff_t start, size_t len, size_t *retlen, const u8 *buffer)
 674 {
 675         u8 verify_buffer[FALCON_SPI_MAX_LEN];
 676         size_t block_len, pos = 0;
 677         unsigned int command;
 678         int rc = 0;
 679
 680         while (pos < len) {
 681                 rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0);
 682                 if (rc)
 683                         break;
 684
 685                 block_len = min(len - pos,
 686                                 falcon_spi_write_limit(spi, start + pos));
 687                 command = falcon_spi_munge_command(spi, SPI_WRITE, start + pos);
 688                 rc = falcon_spi_cmd(efx, spi, command, start + pos,
 689                                     buffer + pos, NULL, block_len);
 690                 if (rc)
 691                         break;
 692
 693                 rc = falcon_spi_wait_write(efx, spi);
 694                 if (rc)
 695                         break;
 696
 697                 command = falcon_spi_munge_command(spi, SPI_READ, start + pos);
 698                 rc = falcon_spi_cmd(efx, spi, command, start + pos,
 699                                     NULL, verify_buffer, block_len);
 700                 if (memcmp(verify_buffer, buffer + pos, block_len)) {
 701                         rc = -EIO;
 702                         break;
 703                 }
 704
 705                 pos += block_len;
 706
 707                 /* Avoid locking up the system */
 708                 cond_resched();
 709                 if (signal_pending(current)) {
 710                         rc = -EINTR;
 711                         break;
 712                 }
 713         }
 714
 715         if (retlen)
 716                 *retlen = pos;
 717         return rc;
 718 }
 719
 720 static int
 721 falcon_spi_slow_wait(struct falcon_mtd_partition *part, bool uninterruptible)
 722 {
 723         const struct falcon_spi_device *spi = part->spi;
 724         struct efx_nic *efx = part->common.mtd.priv;
 725         u8 status;
 726         int rc, i;
 727
 728         /* Wait up to 4s for flash/EEPROM to finish a slow operation. */
 729         for (i = 0; i < 40; i++) {
 730                 __set_current_state(uninterruptible ?
 731                                     TASK_UNINTERRUPTIBLE : TASK_INTERRUPTIBLE);
 732                 schedule_timeout(HZ / 10);
 733                 rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL,
 734                                     &status, sizeof(status));
 735                 if (rc)
 736                         return rc;
 737                 if (!(status & SPI_STATUS_NRDY))
 738                         return 0;
 739                 if (signal_pending(current))
 740                         return -EINTR;
 741         }
 742         pr_err("%s: timed out waiting for %s\n",
 743                part->common.name, part->common.dev_type_name);
 744         return -ETIMEDOUT;
 745 }
 746
 747 static int
 748 falcon_spi_unlock(struct efx_nic *efx, const struct falcon_spi_device *spi)
 749 {
 750         const u8 unlock_mask = (SPI_STATUS_BP2 | SPI_STATUS_BP1 |
 751                                 SPI_STATUS_BP0);
 752         u8 status;
 753         int rc;
 754
 755         rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL,
 756                             &status, sizeof(status));
 757         if (rc)
 758                 return rc;
 759
 760         if (!(status & unlock_mask))
 761                 return 0; /* already unlocked */
 762
 763         rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0);
 764         if (rc)
 765                 return rc;
 766         rc = falcon_spi_cmd(efx, spi, SPI_SST_EWSR, -1, NULL, NULL, 0);
 767         if (rc)
 768                 return rc;
 769
 770         status &= ~unlock_mask;
 771         rc = falcon_spi_cmd(efx, spi, SPI_WRSR, -1, &status,
 772                             NULL, sizeof(status));
 773         if (rc)
 774                 return rc;
 775         rc = falcon_spi_wait_write(efx, spi);
 776         if (rc)
 777                 return rc;
 778
 779         return 0;
 780 }
 781
 782 #define FALCON_SPI_VERIFY_BUF_LEN 16
 783
 784 static int
 785 falcon_spi_erase(struct falcon_mtd_partition *part, loff_t start, size_t len)
 786 {
 787         const struct falcon_spi_device *spi = part->spi;
 788         struct efx_nic *efx = part->common.mtd.priv;
 789         unsigned pos, block_len;
 790         u8 empty[FALCON_SPI_VERIFY_BUF_LEN];
 791         u8 buffer[FALCON_SPI_VERIFY_BUF_LEN];
 792         int rc;
 793
 794         if (len != spi->erase_size)
 795                 return -EINVAL;
 796
 797         if (spi->erase_command == 0)
 798                 return -EOPNOTSUPP;
 799
 800         rc = falcon_spi_unlock(efx, spi);
 801         if (rc)
 802                 return rc;
 803         rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0);
 804         if (rc)
 805                 return rc;
 806         rc = falcon_spi_cmd(efx, spi, spi->erase_command, start, NULL,
 807                             NULL, 0);
 808         if (rc)
 809                 return rc;
 810         rc = falcon_spi_slow_wait(part, false);
 811
 812         /* Verify the entire region has been wiped */
 813         memset(empty, 0xff, sizeof(empty));
 814         for (pos = 0; pos < len; pos += block_len) {
 815                 block_len = min(len - pos, sizeof(buffer));
 816                 rc = falcon_spi_read(efx, spi, start + pos, block_len,
 817                                      NULL, buffer);
 818                 if (rc)
 819                         return rc;
 820                 if (memcmp(empty, buffer, block_len))
 821                         return -EIO;
 822
 823                 /* Avoid locking up the system */
 824                 cond_resched();
 825                 if (signal_pending(current))
 826                         return -EINTR;
 827         }
 828
 829         return rc;
 830 }
 831
 832 static void falcon_mtd_rename(struct efx_mtd_partition *part)
 833 {
 834         struct efx_nic *efx = part->mtd.priv;
 835
 836         snprintf(part->name, sizeof(part->name), "%s %s",
 837                  efx->name, part->type_name);
 838 }
 839
 840 static int falcon_mtd_read(struct mtd_info *mtd, loff_t start,
 841                            size_t len, size_t *retlen, u8 *buffer)
 842 {
 843         struct falcon_mtd_partition *part = to_falcon_mtd_partition(mtd);
 844         struct efx_nic *efx = mtd->priv;
 845         struct falcon_nic_data *nic_data = efx->nic_data;
 846         int rc;
 847
 848         rc = mutex_lock_interruptible(&nic_data->spi_lock);
 849         if (rc)
 850                 return rc;
 851         rc = falcon_spi_read(efx, part->spi, part->offset + start,
 852                              len, retlen, buffer);
 853         mutex_unlock(&nic_data->spi_lock);
 854         return rc;
 855 }
 856
 857 static int falcon_mtd_erase(struct mtd_info *mtd, loff_t start, size_t len)
 858 {
 859         struct falcon_mtd_partition *part = to_falcon_mtd_partition(mtd);
 860         struct efx_nic *efx = mtd->priv;
 861         struct falcon_nic_data *nic_data = efx->nic_data;
 862         int rc;
 863
 864         rc = mutex_lock_interruptible(&nic_data->spi_lock);
 865         if (rc)
 866                 return rc;
 867         rc = falcon_spi_erase(part, part->offset + start, len);
 868         mutex_unlock(&nic_data->spi_lock);
 869         return rc;
 870 }
 871
 872 static int falcon_mtd_write(struct mtd_info *mtd, loff_t start,
 873                             size_t len, size_t *retlen, const u8 *buffer)
 874 {
 875         struct falcon_mtd_partition *part = to_falcon_mtd_partition(mtd);
 876         struct efx_nic *efx = mtd->priv;
 877         struct falcon_nic_data *nic_data = efx->nic_data;
 878         int rc;
 879
 880         rc = mutex_lock_interruptible(&nic_data->spi_lock);
 881         if (rc)
 882                 return rc;
 883         rc = falcon_spi_write(efx, part->spi, part->offset + start,
 884                               len, retlen, buffer);
 885         mutex_unlock(&nic_data->spi_lock);
 886         return rc;
 887 }
 888
 889 static int falcon_mtd_sync(struct mtd_info *mtd)
 890 {
 891         struct falcon_mtd_partition *part = to_falcon_mtd_partition(mtd);
 892         struct efx_nic *efx = mtd->priv;
 893         struct falcon_nic_data *nic_data = efx->nic_data;
 894         int rc;
 895
 896         mutex_lock(&nic_data->spi_lock);
 897         rc = falcon_spi_slow_wait(part, true);
 898         mutex_unlock(&nic_data->spi_lock);
 899         return rc;
 900 }
 901
 902 static int falcon_mtd_probe(struct efx_nic *efx)
 903 {
 904         struct falcon_nic_data *nic_data = efx->nic_data;
 905         struct falcon_mtd_partition *parts;
 906         struct falcon_spi_device *spi;
 907         size_t n_parts;
 908         int rc = -ENODEV;
 909
 910         ASSERT_RTNL();
 911
 912         /* Allocate space for maximum number of partitions */
 913         parts = kcalloc(2, sizeof(*parts), GFP_KERNEL);
 914         if (!parts)
 915                 return -ENOMEM;
 916         n_parts = 0;
 917
 918         spi = &nic_data->spi_flash;
 919         if (falcon_spi_present(spi) && spi->size > FALCON_FLASH_BOOTCODE_START) {
 920                 parts[n_parts].spi = spi;
 921                 parts[n_parts].offset = FALCON_FLASH_BOOTCODE_START;
 922                 parts[n_parts].common.dev_type_name = "flash";
 923                 parts[n_parts].common.type_name = "sfc_flash_bootrom";
 924                 parts[n_parts].common.mtd.type = MTD_NORFLASH;
 925                 parts[n_parts].common.mtd.flags = MTD_CAP_NORFLASH;
 926                 parts[n_parts].common.mtd.size = spi->size - FALCON_FLASH_BOOTCODE_START;
 927                 parts[n_parts].common.mtd.erasesize = spi->erase_size;
 928                 n_parts++;
 929         }
 930
 931         spi = &nic_data->spi_eeprom;
 932         if (falcon_spi_present(spi) && spi->size > FALCON_EEPROM_BOOTCONFIG_START) {
 933                 parts[n_parts].spi = spi;
 934                 parts[n_parts].offset = FALCON_EEPROM_BOOTCONFIG_START;
 935                 parts[n_parts].common.dev_type_name = "EEPROM";
 936                 parts[n_parts].common.type_name = "sfc_bootconfig";
 937                 parts[n_parts].common.mtd.type = MTD_RAM;
 938                 parts[n_parts].common.mtd.flags = MTD_CAP_RAM;
 939                 parts[n_parts].common.mtd.size =
 940                         min(spi->size, FALCON_EEPROM_BOOTCONFIG_END) -
 941                         FALCON_EEPROM_BOOTCONFIG_START;
 942                 parts[n_parts].common.mtd.erasesize = spi->erase_size;
 943                 n_parts++;
 944         }
 945
 946         rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
 947         if (rc)
 948                 kfree(parts);
 949         return rc;
 950 }
 951
 952 #endif /* CONFIG_SFC_MTD */
 953
 954 /**************************************************************************
 955  *
 956  * XMAC operations
 957  *
 958  **************************************************************************
 959  */
 960
 961 /* Configure the XAUI driver that is an output from Falcon */
 962 static void falcon_setup_xaui(struct efx_nic *efx)
 963 {
 964         efx_oword_t sdctl, txdrv;
 965
 966         /* Move the XAUI into low power, unless there is no PHY, in
 967          * which case the XAUI will have to drive a cable. */
 968         if (efx->phy_type == PHY_TYPE_NONE)
 969                 return;
 970
 971         efx_reado(efx, &sdctl, FR_AB_XX_SD_CTL);
 972         EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVD, FFE_AB_XX_SD_CTL_DRV_DEF);
 973         EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVD, FFE_AB_XX_SD_CTL_DRV_DEF);
 974         EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVC, FFE_AB_XX_SD_CTL_DRV_DEF);
 975         EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVC, FFE_AB_XX_SD_CTL_DRV_DEF);
 976         EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVB, FFE_AB_XX_SD_CTL_DRV_DEF);
 977         EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVB, FFE_AB_XX_SD_CTL_DRV_DEF);
 978         EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVA, FFE_AB_XX_SD_CTL_DRV_DEF);
 979         EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVA, FFE_AB_XX_SD_CTL_DRV_DEF);
 980         efx_writeo(efx, &sdctl, FR_AB_XX_SD_CTL);
 981
 982         EFX_POPULATE_OWORD_8(txdrv,
 983                              FRF_AB_XX_DEQD, FFE_AB_XX_TXDRV_DEQ_DEF,
 984                              FRF_AB_XX_DEQC, FFE_AB_XX_TXDRV_DEQ_DEF,
 985                              FRF_AB_XX_DEQB, FFE_AB_XX_TXDRV_DEQ_DEF,
 986                              FRF_AB_XX_DEQA, FFE_AB_XX_TXDRV_DEQ_DEF,
 987                              FRF_AB_XX_DTXD, FFE_AB_XX_TXDRV_DTX_DEF,
 988                              FRF_AB_XX_DTXC, FFE_AB_XX_TXDRV_DTX_DEF,
 989                              FRF_AB_XX_DTXB, FFE_AB_XX_TXDRV_DTX_DEF,
 990                              FRF_AB_XX_DTXA, FFE_AB_XX_TXDRV_DTX_DEF);
 991         efx_writeo(efx, &txdrv, FR_AB_XX_TXDRV_CTL);
 992 }
 993
 994 int falcon_reset_xaui(struct efx_nic *efx)
 995 {
 996         struct falcon_nic_data *nic_data = efx->nic_data;
 997         efx_oword_t reg;
 998         int count;
 999
1000         /* Don't fetch MAC statistics over an XMAC reset */
1001         WARN_ON(nic_data->stats_disable_count == 0);
1002
1003         /* Start reset sequence */
1004         EFX_POPULATE_OWORD_1(reg, FRF_AB_XX_RST_XX_EN, 1);
1005         efx_writeo(efx, &reg, FR_AB_XX_PWR_RST);
1006
1007         /* Wait up to 10 ms for completion, then reinitialise */
1008         for (count = 0; count < 1000; count++) {
1009                 efx_reado(efx, &reg, FR_AB_XX_PWR_RST);
1010                 if (EFX_OWORD_FIELD(reg, FRF_AB_XX_RST_XX_EN) == 0 &&
1011                     EFX_OWORD_FIELD(reg, FRF_AB_XX_SD_RST_ACT) == 0) {
1012                         falcon_setup_xaui(efx);
1013                         return 0;
1014                 }
1015                 udelay(10);
1016         }
1017         netif_err(efx, hw, efx->net_dev,
1018                   "timed out waiting for XAUI/XGXS reset\n");
1019         return -ETIMEDOUT;
1020 }
1021
1022 static void falcon_ack_status_intr(struct efx_nic *efx)
1023 {
1024         struct falcon_nic_data *nic_data = efx->nic_data;
1025         efx_oword_t reg;
1026
1027         if ((efx_nic_rev(efx) != EFX_REV_FALCON_B0) || LOOPBACK_INTERNAL(efx))
1028                 return;
1029
1030         /* We expect xgmii faults if the wireside link is down */
1031         if (!efx->link_state.up)
1032                 return;
1033
1034         /* We can only use this interrupt to signal the negative edge of
1035          * xaui_align [we have to poll the positive edge]. */
1036         if (nic_data->xmac_poll_required)
1037                 return;
1038
1039         efx_reado(efx, &reg, FR_AB_XM_MGT_INT_MSK);
1040 }
1041
1042 static bool falcon_xgxs_link_ok(struct efx_nic *efx)
1043 {
1044         efx_oword_t reg;
1045         bool align_done, link_ok = false;
1046         int sync_status;
1047
1048         /* Read link status */
1049         efx_reado(efx, &reg, FR_AB_XX_CORE_STAT);
1050
1051         align_done = EFX_OWORD_FIELD(reg, FRF_AB_XX_ALIGN_DONE);
1052         sync_status = EFX_OWORD_FIELD(reg, FRF_AB_XX_SYNC_STAT);
1053         if (align_done && (sync_status == FFE_AB_XX_STAT_ALL_LANES))
1054                 link_ok = true;
1055
1056         /* Clear link status ready for next read */
1057         EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_COMMA_DET, FFE_AB_XX_STAT_ALL_LANES);
1058         EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_CHAR_ERR, FFE_AB_XX_STAT_ALL_LANES);
1059         EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_DISPERR, FFE_AB_XX_STAT_ALL_LANES);
1060         efx_writeo(efx, &reg, FR_AB_XX_CORE_STAT);
1061
1062         return link_ok;
1063 }
1064
1065 static bool falcon_xmac_link_ok(struct efx_nic *efx)
1066 {
1067         /*
1068          * Check MAC's XGXS link status except when using XGMII loopback
1069          * which bypasses the XGXS block.
1070          * If possible, check PHY's XGXS link status except when using
1071          * MAC loopback.
1072          */
1073         return (efx->loopback_mode == LOOPBACK_XGMII ||
1074                 falcon_xgxs_link_ok(efx)) &&
1075                 (!(efx->mdio.mmds & (1 << MDIO_MMD_PHYXS)) ||
1076                  LOOPBACK_INTERNAL(efx) ||
1077                  efx_mdio_phyxgxs_lane_sync(efx));
1078 }
1079
1080 static void falcon_reconfigure_xmac_core(struct efx_nic *efx)
1081 {
1082         unsigned int max_frame_len;
1083         efx_oword_t reg;
1084         bool rx_fc = !!(efx->link_state.fc & EFX_FC_RX);
1085         bool tx_fc = !!(efx->link_state.fc & EFX_FC_TX);
1086
1087         /* Configure MAC  - cut-thru mode is hard wired on */
1088         EFX_POPULATE_OWORD_3(reg,
1089                              FRF_AB_XM_RX_JUMBO_MODE, 1,
1090                              FRF_AB_XM_TX_STAT_EN, 1,
1091                              FRF_AB_XM_RX_STAT_EN, 1);
1092         efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);
1093
1094         /* Configure TX */
1095         EFX_POPULATE_OWORD_6(reg,
1096                              FRF_AB_XM_TXEN, 1,
1097                              FRF_AB_XM_TX_PRMBL, 1,
1098                              FRF_AB_XM_AUTO_PAD, 1,
1099                              FRF_AB_XM_TXCRC, 1,
1100                              FRF_AB_XM_FCNTL, tx_fc,
1101                              FRF_AB_XM_IPG, 0x3);
1102         efx_writeo(efx, &reg, FR_AB_XM_TX_CFG);
1103
1104         /* Configure RX */
1105         EFX_POPULATE_OWORD_5(reg,
1106                              FRF_AB_XM_RXEN, 1,
1107                              FRF_AB_XM_AUTO_DEPAD, 0,
1108                              FRF_AB_XM_ACPT_ALL_MCAST, 1,
1109                              FRF_AB_XM_ACPT_ALL_UCAST, !efx->unicast_filter,
1110                              FRF_AB_XM_PASS_CRC_ERR, 1);
1111         efx_writeo(efx, &reg, FR_AB_XM_RX_CFG);
1112
1113         /* Set frame length */
1114         max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu);
1115         EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_MAX_RX_FRM_SIZE, max_frame_len);
1116         efx_writeo(efx, &reg, FR_AB_XM_RX_PARAM);
1117         EFX_POPULATE_OWORD_2(reg,
1118                              FRF_AB_XM_MAX_TX_FRM_SIZE, max_frame_len,
1119                              FRF_AB_XM_TX_JUMBO_MODE, 1);
1120         efx_writeo(efx, &reg, FR_AB_XM_TX_PARAM);
1121
1122         EFX_POPULATE_OWORD_2(reg,
1123                              FRF_AB_XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */
1124                              FRF_AB_XM_DIS_FCNTL, !rx_fc);
1125         efx_writeo(efx, &reg, FR_AB_XM_FC);
1126
1127         /* Set MAC address */
1128         memcpy(&reg, &efx->net_dev->dev_addr[0], 4);
1129         efx_writeo(efx, &reg, FR_AB_XM_ADR_LO);
1130         memcpy(&reg, &efx->net_dev->dev_addr[4], 2);
1131         efx_writeo(efx, &reg, FR_AB_XM_ADR_HI);
1132 }
1133
1134 static void falcon_reconfigure_xgxs_core(struct efx_nic *efx)
1135 {
1136         efx_oword_t reg;
1137         bool xgxs_loopback = (efx->loopback_mode == LOOPBACK_XGXS);
1138         bool xaui_loopback = (efx->loopback_mode == LOOPBACK_XAUI);
1139         bool xgmii_loopback = (efx->loopback_mode == LOOPBACK_XGMII);
1140         bool old_xgmii_loopback, old_xgxs_loopback, old_xaui_loopback;
1141
1142         /* XGXS block is flaky and will need to be reset if moving
1143          * into our out of XGMII, XGXS or XAUI loopbacks. */
1144         efx_reado(efx, &reg, FR_AB_XX_CORE_STAT);
1145         old_xgxs_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN);
1146         old_xgmii_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN);
1147
1148         efx_reado(efx, &reg, FR_AB_XX_SD_CTL);
1149         old_xaui_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_LPBKA);
1150
1151         /* The PHY driver may have turned XAUI off */
1152         if ((xgxs_loopback != old_xgxs_loopback) ||
1153             (xaui_loopback != old_xaui_loopback) ||
1154             (xgmii_loopback != old_xgmii_loopback))
1155                 falcon_reset_xaui(efx);
1156
1157         efx_reado(efx, &reg, FR_AB_XX_CORE_STAT);
1158         EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_FORCE_SIG,
1159                             (xgxs_loopback || xaui_loopback) ?
1160                             FFE_AB_XX_FORCE_SIG_ALL_LANES : 0);
1161         EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN, xgxs_loopback);
1162         EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN, xgmii_loopback);
1163         efx_writeo(efx, &reg, FR_AB_XX_CORE_STAT);
1164
1165         efx_reado(efx, &reg, FR_AB_XX_SD_CTL);
1166         EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKD, xaui_loopback);
1167         EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKC, xaui_loopback);
1168         EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKB, xaui_loopback);
1169         EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKA, xaui_loopback);
1170         efx_writeo(efx, &reg, FR_AB_XX_SD_CTL);
1171 }
1172
1173
1174 /* Try to bring up the Falcon side of the Falcon-Phy XAUI link */
1175 static bool falcon_xmac_link_ok_retry(struct efx_nic *efx, int tries)
1176 {
1177         bool mac_up = falcon_xmac_link_ok(efx);
1178
1179         if (LOOPBACK_MASK(efx) & LOOPBACKS_EXTERNAL(efx) & LOOPBACKS_WS ||
1180             efx_phy_mode_disabled(efx->phy_mode))
1181                 /* XAUI link is expected to be down */
1182                 return mac_up;
1183
1184         falcon_stop_nic_stats(efx);
1185
1186         while (!mac_up && tries) {
1187                 netif_dbg(efx, hw, efx->net_dev, "bashing xaui\n");
1188                 falcon_reset_xaui(efx);
1189                 udelay(200);
1190
1191                 mac_up = falcon_xmac_link_ok(efx);
1192                 --tries;
1193         }
1194
1195         falcon_start_nic_stats(efx);
1196
1197         return mac_up;
1198 }
1199
1200 static bool falcon_xmac_check_fault(struct efx_nic *efx)
1201 {
1202         return !falcon_xmac_link_ok_retry(efx, 5);
1203 }
1204
1205 static int falcon_reconfigure_xmac(struct efx_nic *efx)
1206 {
1207         struct falcon_nic_data *nic_data = efx->nic_data;
1208
1209         efx_farch_filter_sync_rx_mode(efx);
1210
1211         falcon_reconfigure_xgxs_core(efx);
1212         falcon_reconfigure_xmac_core(efx);
1213
1214         falcon_reconfigure_mac_wrapper(efx);
1215
1216         nic_data->xmac_poll_required = !falcon_xmac_link_ok_retry(efx, 5);
1217         falcon_ack_status_intr(efx);
1218
1219         return 0;
1220 }
1221
1222 static void falcon_poll_xmac(struct efx_nic *efx)
1223 {
1224         struct falcon_nic_data *nic_data = efx->nic_data;
1225
1226         /* We expect xgmii faults if the wireside link is down */
1227         if (!efx->link_state.up || !nic_data->xmac_poll_required)
1228                 return;
1229
1230         nic_data->xmac_poll_required = !falcon_xmac_link_ok_retry(efx, 1);
1231         falcon_ack_status_intr(efx);
1232 }
1233
1234 /**************************************************************************
1235  *
1236  * MAC wrapper
1237  *
1238  **************************************************************************
1239  */
1240
1241 static void falcon_push_multicast_hash(struct efx_nic *efx)
1242 {
1243         union efx_multicast_hash *mc_hash = &efx->multicast_hash;
1244
1245         WARN_ON(!mutex_is_locked(&efx->mac_lock));
1246
1247         efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0);
1248         efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1);
1249 }
1250
1251 static void falcon_reset_macs(struct efx_nic *efx)
1252 {
1253         struct falcon_nic_data *nic_data = efx->nic_data;
1254         efx_oword_t reg, mac_ctrl;
1255         int count;
1256
1257         if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) {
1258                 /* It's not safe to use GLB_CTL_REG to reset the
1259                  * macs, so instead use the internal MAC resets
1260                  */
1261                 EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1);
1262                 efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);
1263
1264                 for (count = 0; count < 10000; count++) {
1265                         efx_reado(efx, &reg, FR_AB_XM_GLB_CFG);
1266                         if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) ==
1267                             0)
1268                                 return;
1269                         udelay(10);
1270                 }
1271
1272                 netif_err(efx, hw, efx->net_dev,
1273                           "timed out waiting for XMAC core reset\n");
1274         }
1275
1276         /* Mac stats will fail whist the TX fifo is draining */
1277         WARN_ON(nic_data->stats_disable_count == 0);
1278
1279         efx_reado(efx, &mac_ctrl, FR_AB_MAC_CTRL);
1280         EFX_SET_OWORD_FIELD(mac_ctrl, FRF_BB_TXFIFO_DRAIN_EN, 1);
1281         efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
1282
1283         efx_reado(efx, &reg, FR_AB_GLB_CTL);
1284         EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1);
1285         EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1);
1286         EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1);
1287         efx_writeo(efx, &reg, FR_AB_GLB_CTL);
1288
1289         count = 0;
1290         while (1) {
1291                 efx_reado(efx, &reg, FR_AB_GLB_CTL);
1292                 if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) &&
1293                     !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) &&
1294                     !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) {
1295                         netif_dbg(efx, hw, efx->net_dev,
1296                                   "Completed MAC reset after %d loops\n",
1297                                   count);
1298                         break;
1299                 }
1300                 if (count > 20) {
1301                         netif_err(efx, hw, efx->net_dev, "MAC reset failed\n");
1302                         break;
1303                 }
1304                 count++;
1305                 udelay(10);
1306         }
1307
1308         /* Ensure the correct MAC is selected before statistics
1309          * are re-enabled by the caller */
1310         efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
1311
1312         falcon_setup_xaui(efx);
1313 }
1314
1315 static void falcon_drain_tx_fifo(struct efx_nic *efx)
1316 {
1317         efx_oword_t reg;
1318
1319         if ((efx_nic_rev(efx) < EFX_REV_FALCON_B0) ||
1320             (efx->loopback_mode != LOOPBACK_NONE))
1321                 return;
1322
1323         efx_reado(efx, &reg, FR_AB_MAC_CTRL);
1324         /* There is no point in draining more than once */
1325         if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN))
1326                 return;
1327
1328         falcon_reset_macs(efx);
1329 }
1330
1331 static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
1332 {
1333         efx_oword_t reg;
1334
1335         if (efx_nic_rev(efx) < EFX_REV_FALCON_B0)
1336                 return;
1337
1338         /* Isolate the MAC -> RX */
1339         efx_reado(efx, &reg, FR_AZ_RX_CFG);
1340         EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0);
1341         efx_writeo(efx, &reg, FR_AZ_RX_CFG);
1342
1343         /* Isolate TX -> MAC */
1344         falcon_drain_tx_fifo(efx);
1345 }
1346
1347 static void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
1348 {
1349         struct efx_link_state *link_state = &efx->link_state;
1350         efx_oword_t reg;
1351         int link_speed, isolate;
1352
1353         isolate = !!ACCESS_ONCE(efx->reset_pending);
1354
1355         switch (link_state->speed) {
1356         case 10000: link_speed = 3; break;
1357         case 1000:  link_speed = 2; break;
1358         case 100:   link_speed = 1; break;
1359         default:    link_speed = 0; break;
1360         }
1361
1362         /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
1363          * as advertised.  Disable to ensure packets are not
1364          * indefinitely held and TX queue can be flushed at any point
1365          * while the link is down. */
1366         EFX_POPULATE_OWORD_5(reg,
1367                              FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */,
1368                              FRF_AB_MAC_BCAD_ACPT, 1,
1369                              FRF_AB_MAC_UC_PROM, !efx->unicast_filter,
1370                              FRF_AB_MAC_LINK_STATUS, 1, /* always set */
1371                              FRF_AB_MAC_SPEED, link_speed);
1372         /* On B0, MAC backpressure can be disabled and packets get
1373          * discarded. */
1374         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
1375                 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN,
1376                                     !link_state->up || isolate);
1377         }
1378
1379         efx_writeo(efx, &reg, FR_AB_MAC_CTRL);
1380
1381         /* Restore the multicast hash registers. */
1382         falcon_push_multicast_hash(efx);
1383
1384         efx_reado(efx, &reg, FR_AZ_RX_CFG);
1385         /* Enable XOFF signal from RX FIFO (we enabled it during NIC
1386          * initialisation but it may read back as 0) */
1387         EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
1388         /* Unisolate the MAC -> RX */
1389         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1390                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, !isolate);
1391         efx_writeo(efx, &reg, FR_AZ_RX_CFG);
1392 }
1393
1394 static void falcon_stats_request(struct efx_nic *efx)
1395 {
1396         struct falcon_nic_data *nic_data = efx->nic_data;
1397         efx_oword_t reg;
1398
1399         WARN_ON(nic_data->stats_pending);
1400         WARN_ON(nic_data->stats_disable_count);
1401
1402         FALCON_XMAC_STATS_DMA_FLAG(efx) = 0;
1403         nic_data->stats_pending = true;
1404         wmb(); /* ensure done flag is clear */
1405
1406         /* Initiate DMA transfer of stats */
1407         EFX_POPULATE_OWORD_2(reg,
1408                              FRF_AB_MAC_STAT_DMA_CMD, 1,
1409                              FRF_AB_MAC_STAT_DMA_ADR,
1410                              efx->stats_buffer.dma_addr);
1411         efx_writeo(efx, &reg, FR_AB_MAC_STAT_DMA);
1412
1413         mod_timer(&nic_data->stats_timer, round_jiffies_up(jiffies + HZ / 2));
1414 }
1415
1416 static void falcon_stats_complete(struct efx_nic *efx)
1417 {
1418         struct falcon_nic_data *nic_data = efx->nic_data;
1419
1420         if (!nic_data->stats_pending)
1421                 return;
1422
1423         nic_data->stats_pending = false;
1424         if (FALCON_XMAC_STATS_DMA_FLAG(efx)) {
1425                 rmb(); /* read the done flag before the stats */
1426                 efx_nic_update_stats(falcon_stat_desc, FALCON_STAT_COUNT,
1427                                      falcon_stat_mask, nic_data->stats,
1428                                      efx->stats_buffer.addr, true);
1429         } else {
1430                 netif_err(efx, hw, efx->net_dev,
1431                           "timed out waiting for statistics\n");
1432         }
1433 }
1434
1435 static void falcon_stats_timer_func(unsigned long context)
1436 {
1437         struct efx_nic *efx = (struct efx_nic *)context;
1438         struct falcon_nic_data *nic_data = efx->nic_data;
1439
1440         spin_lock(&efx->stats_lock);
1441
1442         falcon_stats_complete(efx);
1443         if (nic_data->stats_disable_count == 0)
1444                 falcon_stats_request(efx);
1445
1446         spin_unlock(&efx->stats_lock);
1447 }
1448
1449 static bool falcon_loopback_link_poll(struct efx_nic *efx)
1450 {
1451         struct efx_link_state old_state = efx->link_state;
1452
1453         WARN_ON(!mutex_is_locked(&efx->mac_lock));
1454         WARN_ON(!LOOPBACK_INTERNAL(efx));
1455
1456         efx->link_state.fd = true;
1457         efx->link_state.fc = efx->wanted_fc;
1458         efx->link_state.up = true;
1459         efx->link_state.speed = 10000;
1460
1461         return !efx_link_state_equal(&efx->link_state, &old_state);
1462 }
1463
1464 static int falcon_reconfigure_port(struct efx_nic *efx)
1465 {
1466         int rc;
1467
1468         WARN_ON(efx_nic_rev(efx) > EFX_REV_FALCON_B0);
1469
1470         /* Poll the PHY link state *before* reconfiguring it. This means we
1471          * will pick up the correct speed (in loopback) to select the correct
1472          * MAC.
1473          */
1474         if (LOOPBACK_INTERNAL(efx))
1475                 falcon_loopback_link_poll(efx);
1476         else
1477                 efx->phy_op->poll(efx);
1478
1479         falcon_stop_nic_stats(efx);
1480         falcon_deconfigure_mac_wrapper(efx);
1481
1482         falcon_reset_macs(efx);
1483
1484         efx->phy_op->reconfigure(efx);
1485         rc = falcon_reconfigure_xmac(efx);
1486         BUG_ON(rc);
1487
1488         falcon_start_nic_stats(efx);
1489
1490         /* Synchronise efx->link_state with the kernel */
1491         efx_link_status_changed(efx);
1492
1493         return 0;
1494 }
1495
1496 /* TX flow control may automatically turn itself off if the link
1497  * partner (intermittently) stops responding to pause frames. There
1498  * isn't any indication that this has happened, so the best we do is
1499  * leave it up to the user to spot this and fix it by cycling transmit
1500  * flow control on this end.
1501  */
1502
1503 static void falcon_a1_prepare_enable_fc_tx(struct efx_nic *efx)
1504 {
1505         /* Schedule a reset to recover */
1506         efx_schedule_reset(efx, RESET_TYPE_INVISIBLE);
1507 }
1508
1509 static void falcon_b0_prepare_enable_fc_tx(struct efx_nic *efx)
1510 {
1511         /* Recover by resetting the EM block */
1512         falcon_stop_nic_stats(efx);
1513         falcon_drain_tx_fifo(efx);
1514         falcon_reconfigure_xmac(efx);
1515         falcon_start_nic_stats(efx);
1516 }
1517
1518 /**************************************************************************
1519  *
1520  * PHY access via GMII
1521  *
1522  **************************************************************************
1523  */
1524
1525 /* Wait for GMII access to complete */
1526 static int falcon_gmii_wait(struct efx_nic *efx)
1527 {
1528         efx_oword_t md_stat;
1529         int count;
1530
1531         /* wait up to 50ms - taken max from datasheet */
1532         for (count = 0; count < 5000; count++) {
1533                 efx_reado(efx, &md_stat, FR_AB_MD_STAT);
1534                 if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) {
1535                         if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 ||
1536                             EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) {
1537                                 netif_err(efx, hw, efx->net_dev,
1538                                           "error from GMII access "
1539                                           EFX_OWORD_FMT"\n",
1540                                           EFX_OWORD_VAL(md_stat));
1541                                 return -EIO;
1542                         }
1543                         return 0;
1544                 }
1545                 udelay(10);
1546         }
1547         netif_err(efx, hw, efx->net_dev, "timed out waiting for GMII\n");
1548         return -ETIMEDOUT;
1549 }
1550
1551 /* Write an MDIO register of a PHY connected to Falcon. */
1552 static int falcon_mdio_write(struct net_device *net_dev,
1553                              int prtad, int devad, u16 addr, u16 value)
1554 {
1555         struct efx_nic *efx = netdev_priv(net_dev);
1556         struct falcon_nic_data *nic_data = efx->nic_data;
1557         efx_oword_t reg;
1558         int rc;
1559
1560         netif_vdbg(efx, hw, efx->net_dev,
1561                    "writing MDIO %d register %d.%d with 0x%04x\n",
1562                     prtad, devad, addr, value);
1563
1564         mutex_lock(&nic_data->mdio_lock);
1565
1566         /* Check MDIO not currently being accessed */
1567         rc = falcon_gmii_wait(efx);
1568         if (rc)
1569                 goto out;
1570
1571         /* Write the address/ID register */
1572         EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
1573         efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
1574
1575         EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
1576                              FRF_AB_MD_DEV_ADR, devad);
1577         efx_writeo(efx, &reg, FR_AB_MD_ID);
1578
1579         /* Write data */
1580         EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value);
1581         efx_writeo(efx, &reg, FR_AB_MD_TXD);
1582
1583         EFX_POPULATE_OWORD_2(reg,
1584                              FRF_AB_MD_WRC, 1,
1585                              FRF_AB_MD_GC, 0);
1586         efx_writeo(efx, &reg, FR_AB_MD_CS);
1587
1588         /* Wait for data to be written */
1589         rc = falcon_gmii_wait(efx);
1590         if (rc) {
1591                 /* Abort the write operation */
1592                 EFX_POPULATE_OWORD_2(reg,
1593                                      FRF_AB_MD_WRC, 0,
1594                                      FRF_AB_MD_GC, 1);
1595                 efx_writeo(efx, &reg, FR_AB_MD_CS);
1596                 udelay(10);
1597         }
1598
1599 out:
1600         mutex_unlock(&nic_data->mdio_lock);
1601         return rc;
1602 }
1603
1604 /* Read an MDIO register of a PHY connected to Falcon. */
1605 static int falcon_mdio_read(struct net_device *net_dev,
1606                             int prtad, int devad, u16 addr)
1607 {
1608         struct efx_nic *efx = netdev_priv(net_dev);
1609         struct falcon_nic_data *nic_data = efx->nic_data;
1610         efx_oword_t reg;
1611         int rc;
1612
1613         mutex_lock(&nic_data->mdio_lock);
1614
1615         /* Check MDIO not currently being accessed */
1616         rc = falcon_gmii_wait(efx);
1617         if (rc)
1618                 goto out;
1619
1620         EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
1621         efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
1622
1623         EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
1624                              FRF_AB_MD_DEV_ADR, devad);
1625         efx_writeo(efx, &reg, FR_AB_MD_ID);
1626
1627         /* Request data to be read */
1628         EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0);
1629         efx_writeo(efx, &reg, FR_AB_MD_CS);
1630
1631         /* Wait for data to become available */
1632         rc = falcon_gmii_wait(efx);
1633         if (rc == 0) {
1634                 efx_reado(efx, &reg, FR_AB_MD_RXD);
1635                 rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD);
1636                 netif_vdbg(efx, hw, efx->net_dev,
1637                            "read from MDIO %d register %d.%d, got %04x\n",
1638                            prtad, devad, addr, rc);
1639         } else {
1640                 /* Abort the read operation */
1641                 EFX_POPULATE_OWORD_2(reg,
1642                                      FRF_AB_MD_RIC, 0,
1643                                      FRF_AB_MD_GC, 1);
1644                 efx_writeo(efx, &reg, FR_AB_MD_CS);
1645
1646                 netif_dbg(efx, hw, efx->net_dev,
1647                           "read from MDIO %d register %d.%d, got error %d\n",
1648                           prtad, devad, addr, rc);
1649         }
1650
1651 out:
1652         mutex_unlock(&nic_data->mdio_lock);
1653         return rc;
1654 }
1655
1656 /* This call is responsible for hooking in the MAC and PHY operations */
1657 static int falcon_probe_port(struct efx_nic *efx)
1658 {
1659         struct falcon_nic_data *nic_data = efx->nic_data;
1660         int rc;
1661
1662         switch (efx->phy_type) {
1663         case PHY_TYPE_SFX7101:
1664                 efx->phy_op = &falcon_sfx7101_phy_ops;
1665                 break;
1666         case PHY_TYPE_QT2022C2:
1667         case PHY_TYPE_QT2025C:
1668                 efx->phy_op = &falcon_qt202x_phy_ops;
1669                 break;
1670         case PHY_TYPE_TXC43128:
1671                 efx->phy_op = &falcon_txc_phy_ops;
1672                 break;
1673         default:
1674                 netif_err(efx, probe, efx->net_dev, "Unknown PHY type %d\n",
1675                           efx->phy_type);
1676                 return -ENODEV;
1677         }
1678
1679         /* Fill out MDIO structure and loopback modes */
1680         mutex_init(&nic_data->mdio_lock);
1681         efx->mdio.mdio_read = falcon_mdio_read;
1682         efx->mdio.mdio_write = falcon_mdio_write;
1683         rc = efx->phy_op->probe(efx);
1684         if (rc != 0)
1685                 return rc;
1686
1687         /* Initial assumption */
1688         efx->link_state.speed = 10000;
1689         efx->link_state.fd = true;
1690
1691         /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
1692         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1693                 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
1694         else
1695                 efx->wanted_fc = EFX_FC_RX;
1696         if (efx->mdio.mmds & MDIO_DEVS_AN)
1697                 efx->wanted_fc |= EFX_FC_AUTO;
1698
1699         /* Allocate buffer for stats */
1700         rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer,
1701                                   FALCON_MAC_STATS_SIZE, GFP_KERNEL);
1702         if (rc)
1703                 return rc;
1704         netif_dbg(efx, probe, efx->net_dev,
1705                   "stats buffer at %llx (virt %p phys %llx)\n",
1706                   (u64)efx->stats_buffer.dma_addr,
1707                   efx->stats_buffer.addr,
1708                   (u64)virt_to_phys(efx->stats_buffer.addr));
1709
1710         return 0;
1711 }
1712
1713 static void falcon_remove_port(struct efx_nic *efx)
1714 {
1715         efx->phy_op->remove(efx);
1716         efx_nic_free_buffer(efx, &efx->stats_buffer);
1717 }
1718
1719 /* Global events are basically PHY events */
1720 static bool
1721 falcon_handle_global_event(struct efx_channel *channel, efx_qword_t *event)
1722 {
1723         struct efx_nic *efx = channel->efx;
1724         struct falcon_nic_data *nic_data = efx->nic_data;
1725
1726         if (EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_G_PHY0_INTR) ||
1727             EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XG_PHY0_INTR) ||
1728             EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XFP_PHY0_INTR))
1729                 /* Ignored */
1730                 return true;
1731
1732         if ((efx_nic_rev(efx) == EFX_REV_FALCON_B0) &&
1733             EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_XG_MGT_INTR)) {
1734                 nic_data->xmac_poll_required = true;
1735                 return true;
1736         }
1737
1738         if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1 ?
1739             EFX_QWORD_FIELD(*event, FSF_AA_GLB_EV_RX_RECOVERY) :
1740             EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_RX_RECOVERY)) {
1741                 netif_err(efx, rx_err, efx->net_dev,
1742                           "channel %d seen global RX_RESET event. Resetting.\n",
1743                           channel->channel);
1744
1745                 atomic_inc(&efx->rx_reset);
1746                 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
1747                                    RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
1748                 return true;
1749         }
1750
1751         return false;
1752 }
1753
1754 /**************************************************************************
1755  *
1756  * Falcon test code
1757  *
1758  **************************************************************************/
1759
1760 static int
1761 falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
1762 {
1763         struct falcon_nic_data *nic_data = efx->nic_data;
1764         struct falcon_nvconfig *nvconfig;
1765         struct falcon_spi_device *spi;
1766         void *region;
1767         int rc, magic_num, struct_ver;
1768         __le16 *word, *limit;
1769         u32 csum;
1770
1771         if (falcon_spi_present(&nic_data->spi_flash))
1772                 spi = &nic_data->spi_flash;
1773         else if (falcon_spi_present(&nic_data->spi_eeprom))
1774                 spi = &nic_data->spi_eeprom;
1775         else
1776                 return -EINVAL;
1777
1778         region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL);
1779         if (!region)
1780                 return -ENOMEM;
1781         nvconfig = region + FALCON_NVCONFIG_OFFSET;
1782
1783         mutex_lock(&nic_data->spi_lock);
1784         rc = falcon_spi_read(efx, spi, 0, FALCON_NVCONFIG_END, NULL, region);
1785         mutex_unlock(&nic_data->spi_lock);
1786         if (rc) {
1787                 netif_err(efx, hw, efx->net_dev, "Failed to read %s\n",
1788                           falcon_spi_present(&nic_data->spi_flash) ?
1789                           "flash" : "EEPROM");
1790                 rc = -EIO;
1791                 goto out;
1792         }
1793
1794         magic_num = le16_to_cpu(nvconfig->board_magic_num);
1795         struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
1796
1797         rc = -EINVAL;
1798         if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) {
1799                 netif_err(efx, hw, efx->net_dev,
1800                           "NVRAM bad magic 0x%x\n", magic_num);
1801                 goto out;
1802         }
1803         if (struct_ver < 2) {
1804                 netif_err(efx, hw, efx->net_dev,
1805                           "NVRAM has ancient version 0x%x\n", struct_ver);
1806                 goto out;
1807         } else if (struct_ver < 4) {
1808                 word = &nvconfig->board_magic_num;
1809                 limit = (__le16 *) (nvconfig + 1);
1810         } else {
1811                 word = region;
1812                 limit = region + FALCON_NVCONFIG_END;
1813         }
1814         for (csum = 0; word < limit; ++word)
1815                 csum += le16_to_cpu(*word);
1816
1817         if (~csum & 0xffff) {
1818                 netif_err(efx, hw, efx->net_dev,
1819                           "NVRAM has incorrect checksum\n");
1820                 goto out;
1821         }
1822
1823         rc = 0;
1824         if (nvconfig_out)
1825                 memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig));
1826
1827  out:
1828         kfree(region);
1829         return rc;
1830 }
1831
1832 static int falcon_test_nvram(struct efx_nic *efx)
1833 {
1834         return falcon_read_nvram(efx, NULL);
1835 }
1836
1837 static const struct efx_farch_register_test falcon_b0_register_tests[] = {
1838         { FR_AZ_ADR_REGION,
1839           EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
1840         { FR_AZ_RX_CFG,
1841           EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
1842         { FR_AZ_TX_CFG,
1843           EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
1844         { FR_AZ_TX_RESERVED,
1845           EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
1846         { FR_AB_MAC_CTRL,
1847           EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
1848         { FR_AZ_SRM_TX_DC_CFG,
1849           EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
1850         { FR_AZ_RX_DC_CFG,
1851           EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
1852         { FR_AZ_RX_DC_PF_WM,
1853           EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
1854         { FR_BZ_DP_CTRL,
1855           EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
1856         { FR_AB_GM_CFG2,
1857           EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) },
1858         { FR_AB_GMF_CFG0,
1859           EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) },
1860         { FR_AB_XM_GLB_CFG,
1861           EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
1862         { FR_AB_XM_TX_CFG,
1863           EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
1864         { FR_AB_XM_RX_CFG,
1865           EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
1866         { FR_AB_XM_RX_PARAM,
1867           EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
1868         { FR_AB_XM_FC,
1869           EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
1870         { FR_AB_XM_ADR_LO,
1871           EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
1872         { FR_AB_XX_SD_CTL,
1873           EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
1874 };
1875
1876 static int
1877 falcon_b0_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
1878 {
1879         enum reset_type reset_method = RESET_TYPE_INVISIBLE;
1880         int rc, rc2;
1881
1882         mutex_lock(&efx->mac_lock);
1883         if (efx->loopback_modes) {
1884                 /* We need the 312 clock from the PHY to test the XMAC
1885                  * registers, so move into XGMII loopback if available */
1886                 if (efx->loopback_modes & (1 << LOOPBACK_XGMII))
1887                         efx->loopback_mode = LOOPBACK_XGMII;
1888                 else
1889                         efx->loopback_mode = __ffs(efx->loopback_modes);
1890         }
1891         __efx_reconfigure_port(efx);
1892         mutex_unlock(&efx->mac_lock);
1893
1894         efx_reset_down(efx, reset_method);
1895
1896         tests->registers =
1897                 efx_farch_test_registers(efx, falcon_b0_register_tests,
1898                                          ARRAY_SIZE(falcon_b0_register_tests))
1899                 ? -1 : 1;
1900
1901         rc = falcon_reset_hw(efx, reset_method);
1902         rc2 = efx_reset_up(efx, reset_method, rc == 0);
1903         return rc ? rc : rc2;
1904 }
1905
1906 /**************************************************************************
1907  *
1908  * Device reset
1909  *
1910  **************************************************************************
1911  */
1912
1913 static enum reset_type falcon_map_reset_reason(enum reset_type reason)
1914 {
1915         switch (reason) {
1916         case RESET_TYPE_RX_RECOVERY:
1917         case RESET_TYPE_DMA_ERROR:
1918         case RESET_TYPE_TX_SKIP:
1919                 /* These can occasionally occur due to hardware bugs.
1920                  * We try to reset without disrupting the link.
1921                  */
1922                 return RESET_TYPE_INVISIBLE;
1923         default:
1924                 return RESET_TYPE_ALL;
1925         }
1926 }
1927
1928 static int falcon_map_reset_flags(u32 *flags)
1929 {
1930         enum {
1931                 FALCON_RESET_INVISIBLE = (ETH_RESET_DMA | ETH_RESET_FILTER |
1932                                           ETH_RESET_OFFLOAD | ETH_RESET_MAC),
1933                 FALCON_RESET_ALL = FALCON_RESET_INVISIBLE | ETH_RESET_PHY,
1934                 FALCON_RESET_WORLD = FALCON_RESET_ALL | ETH_RESET_IRQ,
1935         };
1936
1937         if ((*flags & FALCON_RESET_WORLD) == FALCON_RESET_WORLD) {
1938                 *flags &= ~FALCON_RESET_WORLD;
1939                 return RESET_TYPE_WORLD;
1940         }
1941
1942         if ((*flags & FALCON_RESET_ALL) == FALCON_RESET_ALL) {
1943                 *flags &= ~FALCON_RESET_ALL;
1944                 return RESET_TYPE_ALL;
1945         }
1946
1947         if ((*flags & FALCON_RESET_INVISIBLE) == FALCON_RESET_INVISIBLE) {
1948                 *flags &= ~FALCON_RESET_INVISIBLE;
1949                 return RESET_TYPE_INVISIBLE;
1950         }
1951
1952         return -EINVAL;
1953 }
1954
1955 /* Resets NIC to known state.  This routine must be called in process
1956  * context and is allowed to sleep. */
1957 static int __falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
1958 {
1959         struct falcon_nic_data *nic_data = efx->nic_data;
1960         efx_oword_t glb_ctl_reg_ker;
1961         int rc;
1962
1963         netif_dbg(efx, hw, efx->net_dev, "performing %s hardware reset\n",
1964                   RESET_TYPE(method));
1965
1966         /* Initiate device reset */
1967         if (method == RESET_TYPE_WORLD) {
1968                 rc = pci_save_state(efx->pci_dev);
1969                 if (rc) {
1970                         netif_err(efx, drv, efx->net_dev,
1971                                   "failed to backup PCI state of primary "
1972                                   "function prior to hardware reset\n");
1973                         goto fail1;
1974                 }
1975                 if (efx_nic_is_dual_func(efx)) {
1976                         rc = pci_save_state(nic_data->pci_dev2);
1977                         if (rc) {
1978                                 netif_err(efx, drv, efx->net_dev,
1979                                           "failed to backup PCI state of "
1980                                           "secondary function prior to "
1981                                           "hardware reset\n");
1982                                 goto fail2;
1983                         }
1984                 }
1985
1986                 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
1987                                      FRF_AB_EXT_PHY_RST_DUR,
1988                                      FFE_AB_EXT_PHY_RST_DUR_10240US,
1989                                      FRF_AB_SWRST, 1);
1990         } else {
1991                 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
1992                                      /* exclude PHY from "invisible" reset */
1993                                      FRF_AB_EXT_PHY_RST_CTL,
1994                                      method == RESET_TYPE_INVISIBLE,
1995                                      /* exclude EEPROM/flash and PCIe */
1996                                      FRF_AB_PCIE_CORE_RST_CTL, 1,
1997                                      FRF_AB_PCIE_NSTKY_RST_CTL, 1,
1998                                      FRF_AB_PCIE_SD_RST_CTL, 1,
1999                                      FRF_AB_EE_RST_CTL, 1,
2000                                      FRF_AB_EXT_PHY_RST_DUR,
2001                                      FFE_AB_EXT_PHY_RST_DUR_10240US,
2002                                      FRF_AB_SWRST, 1);
2003         }
2004         efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
2005
2006         netif_dbg(efx, hw, efx->net_dev, "waiting for hardware reset\n");
2007         schedule_timeout_uninterruptible(HZ / 20);
2008
2009         /* Restore PCI configuration if needed */
2010         if (method == RESET_TYPE_WORLD) {
2011                 if (efx_nic_is_dual_func(efx))
2012                         pci_restore_state(nic_data->pci_dev2);
2013                 pci_restore_state(efx->pci_dev);
2014                 netif_dbg(efx, drv, efx->net_dev,
2015                           "successfully restored PCI config\n");
2016         }
2017
2018         /* Assert that reset complete */
2019         efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
2020         if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) {
2021                 rc = -ETIMEDOUT;
2022                 netif_err(efx, hw, efx->net_dev,
2023                           "timed out waiting for hardware reset\n");
2024                 goto fail3;
2025         }
2026         netif_dbg(efx, hw, efx->net_dev, "hardware reset complete\n");
2027
2028         return 0;
2029
2030         /* pci_save_state() and pci_restore_state() MUST be called in pairs */
2031 fail2:
2032         pci_restore_state(efx->pci_dev);
2033 fail1:
2034 fail3:
2035         return rc;
2036 }
2037
2038 static int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2039 {
2040         struct falcon_nic_data *nic_data = efx->nic_data;
2041         int rc;
2042
2043         mutex_lock(&nic_data->spi_lock);
2044         rc = __falcon_reset_hw(efx, method);
2045         mutex_unlock(&nic_data->spi_lock);
2046
2047         return rc;
2048 }
2049
2050 static void falcon_monitor(struct efx_nic *efx)
2051 {
2052         bool link_changed;
2053         int rc;
2054
2055         BUG_ON(!mutex_is_locked(&efx->mac_lock));
2056
2057         rc = falcon_board(efx)->type->monitor(efx);
2058         if (rc) {
2059                 netif_err(efx, hw, efx->net_dev,
2060                           "Board sensor %s; shutting down PHY\n",
2061                           (rc == -ERANGE) ? "reported fault" : "failed");
2062                 efx->phy_mode |= PHY_MODE_LOW_POWER;
2063                 rc = __efx_reconfigure_port(efx);
2064                 WARN_ON(rc);
2065         }
2066
2067         if (LOOPBACK_INTERNAL(efx))
2068                 link_changed = falcon_loopback_link_poll(efx);
2069         else
2070                 link_changed = efx->phy_op->poll(efx);
2071
2072         if (link_changed) {
2073                 falcon_stop_nic_stats(efx);
2074                 falcon_deconfigure_mac_wrapper(efx);
2075
2076                 falcon_reset_macs(efx);
2077                 rc = falcon_reconfigure_xmac(efx);
2078                 BUG_ON(rc);
2079
2080                 falcon_start_nic_stats(efx);
2081
2082                 efx_link_status_changed(efx);
2083         }
2084
2085         falcon_poll_xmac(efx);
2086 }
2087
2088 /* Zeroes out the SRAM contents.  This routine must be called in
2089  * process context and is allowed to sleep.
2090  */
2091 static int falcon_reset_sram(struct efx_nic *efx)
2092 {
2093         efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
2094         int count;
2095
2096         /* Set the SRAM wake/sleep GPIO appropriately. */
2097         efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
2098         EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1);
2099         EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1);
2100         efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
2101
2102         /* Initiate SRAM reset */
2103         EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
2104                              FRF_AZ_SRM_INIT_EN, 1,
2105                              FRF_AZ_SRM_NB_SZ, 0);
2106         efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
2107
2108         /* Wait for SRAM reset to complete */
2109         count = 0;
2110         do {
2111                 netif_dbg(efx, hw, efx->net_dev,
2112                           "waiting for SRAM reset (attempt %d)...\n", count);
2113
2114                 /* SRAM reset is slow; expect around 16ms */
2115                 schedule_timeout_uninterruptible(HZ / 50);
2116
2117                 /* Check for reset complete */
2118                 efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
2119                 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) {
2120                         netif_dbg(efx, hw, efx->net_dev,
2121                                   "SRAM reset complete\n");
2122
2123                         return 0;
2124                 }
2125         } while (++count < 20); /* wait up to 0.4 sec */
2126
2127         netif_err(efx, hw, efx->net_dev, "timed out waiting for SRAM reset\n");
2128         return -ETIMEDOUT;
2129 }
2130
2131 static void falcon_spi_device_init(struct efx_nic *efx,
2132                                   struct falcon_spi_device *spi_device,
2133                                   unsigned int device_id, u32 device_type)
2134 {
2135         if (device_type != 0) {
2136                 spi_device->device_id = device_id;
2137                 spi_device->size =
2138                         1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
2139                 spi_device->addr_len =
2140                         SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
2141                 spi_device->munge_address = (spi_device->size == 1 << 9 &&
2142                                              spi_device->addr_len == 1);
2143                 spi_device->erase_command =
2144                         SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD);
2145                 spi_device->erase_size =
2146                         1 << SPI_DEV_TYPE_FIELD(device_type,
2147                                                 SPI_DEV_TYPE_ERASE_SIZE);
2148                 spi_device->block_size =
2149                         1 << SPI_DEV_TYPE_FIELD(device_type,
2150                                                 SPI_DEV_TYPE_BLOCK_SIZE);
2151         } else {
2152                 spi_device->size = 0;
2153         }
2154 }
2155
2156 /* Extract non-volatile configuration */
2157 static int falcon_probe_nvconfig(struct efx_nic *efx)
2158 {
2159         struct falcon_nic_data *nic_data = efx->nic_data;
2160         struct falcon_nvconfig *nvconfig;
2161         int rc;
2162
2163         nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
2164         if (!nvconfig)
2165                 return -ENOMEM;
2166
2167         rc = falcon_read_nvram(efx, nvconfig);
2168         if (rc)
2169                 goto out;
2170
2171         efx->phy_type = nvconfig->board_v2.port0_phy_type;
2172         efx->mdio.prtad = nvconfig->board_v2.port0_phy_addr;
2173
2174         if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
2175                 falcon_spi_device_init(
2176                         efx, &nic_data->spi_flash, FFE_AB_SPI_DEVICE_FLASH,
2177                         le32_to_cpu(nvconfig->board_v3
2178                                     .spi_device_type[FFE_AB_SPI_DEVICE_FLASH]));
2179                 falcon_spi_device_init(
2180                         efx, &nic_data->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM,
2181                         le32_to_cpu(nvconfig->board_v3
2182                                     .spi_device_type[FFE_AB_SPI_DEVICE_EEPROM]));
2183         }
2184
2185         /* Read the MAC addresses */
2186         ether_addr_copy(efx->net_dev->perm_addr, nvconfig->mac_address[0]);
2187
2188         netif_dbg(efx, probe, efx->net_dev, "PHY is %d phy_id %d\n",
2189                   efx->phy_type, efx->mdio.prtad);
2190
2191         rc = falcon_probe_board(efx,
2192                                 le16_to_cpu(nvconfig->board_v2.board_revision));
2193 out:
2194         kfree(nvconfig);
2195         return rc;
2196 }
2197
2198 static int falcon_dimension_resources(struct efx_nic *efx)
2199 {
2200         efx->rx_dc_base = 0x20000;
2201         efx->tx_dc_base = 0x26000;
2202         return 0;
2203 }
2204
2205 /* Probe all SPI devices on the NIC */
2206 static void falcon_probe_spi_devices(struct efx_nic *efx)
2207 {
2208         struct falcon_nic_data *nic_data = efx->nic_data;
2209         efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
2210         int boot_dev;
2211
2212         efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL);
2213         efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2214         efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
2215
2216         if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) {
2217                 boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ?
2218                             FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM);
2219                 netif_dbg(efx, probe, efx->net_dev, "Booted from %s\n",
2220                           boot_dev == FFE_AB_SPI_DEVICE_FLASH ?
2221                           "flash" : "EEPROM");
2222         } else {
2223                 /* Disable VPD and set clock dividers to safe
2224                  * values for initial programming. */
2225                 boot_dev = -1;
2226                 netif_dbg(efx, probe, efx->net_dev,
2227                           "Booted from internal ASIC settings;"
2228                           " setting SPI config\n");
2229                 EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0,
2230                                      /* 125 MHz / 7 ~= 20 MHz */
2231                                      FRF_AB_EE_SF_CLOCK_DIV, 7,
2232                                      /* 125 MHz / 63 ~= 2 MHz */
2233                                      FRF_AB_EE_EE_CLOCK_DIV, 63);
2234                 efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
2235         }
2236
2237         mutex_init(&nic_data->spi_lock);
2238
2239         if (boot_dev == FFE_AB_SPI_DEVICE_FLASH)
2240                 falcon_spi_device_init(efx, &nic_data->spi_flash,
2241                                        FFE_AB_SPI_DEVICE_FLASH,
2242                                        default_flash_type);
2243         if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM)
2244                 falcon_spi_device_init(efx, &nic_data->spi_eeprom,
2245                                        FFE_AB_SPI_DEVICE_EEPROM,
2246                                        large_eeprom_type);
2247 }
2248
2249 static unsigned int falcon_a1_mem_map_size(struct efx_nic *efx)
2250 {
2251         return 0x20000;
2252 }
2253
2254 static unsigned int falcon_b0_mem_map_size(struct efx_nic *efx)
2255 {
2256         /* Map everything up to and including the RSS indirection table.
2257          * The PCI core takes care of mapping the MSI-X tables.
2258          */
2259         return FR_BZ_RX_INDIRECTION_TBL +
2260                 FR_BZ_RX_INDIRECTION_TBL_STEP * FR_BZ_RX_INDIRECTION_TBL_ROWS;
2261 }
2262
2263 static int falcon_probe_nic(struct efx_nic *efx)
2264 {
2265         struct falcon_nic_data *nic_data;
2266         struct falcon_board *board;
2267         int rc;
2268
2269         efx->primary = efx; /* only one usable function per controller */
2270
2271         /* Allocate storage for hardware specific data */
2272         nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
2273         if (!nic_data)
2274                 return -ENOMEM;
2275         efx->nic_data = nic_data;
2276
2277         rc = -ENODEV;
2278
2279         if (efx_farch_fpga_ver(efx) != 0) {
2280                 netif_err(efx, probe, efx->net_dev,
2281                           "Falcon FPGA not supported\n");
2282                 goto fail1;
2283         }
2284
2285         if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
2286                 efx_oword_t nic_stat;
2287                 struct pci_dev *dev;
2288                 u8 pci_rev = efx->pci_dev->revision;
2289
2290                 if ((pci_rev == 0xff) || (pci_rev == 0)) {
2291                         netif_err(efx, probe, efx->net_dev,
2292                                   "Falcon rev A0 not supported\n");
2293                         goto fail1;
2294                 }
2295                 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2296                 if (EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) == 0) {
2297                         netif_err(efx, probe, efx->net_dev,
2298                                   "Falcon rev A1 1G not supported\n");
2299                         goto fail1;
2300                 }
2301                 if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) {
2302                         netif_err(efx, probe, efx->net_dev,
2303                                   "Falcon rev A1 PCI-X not supported\n");
2304                         goto fail1;
2305                 }
2306
2307                 dev = pci_dev_get(efx->pci_dev);
2308                 while ((dev = pci_get_device(PCI_VENDOR_ID_SOLARFLARE,
2309                                              PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1,
2310                                              dev))) {
2311                         if (dev->bus == efx->pci_dev->bus &&
2312                             dev->devfn == efx->pci_dev->devfn + 1) {
2313                                 nic_data->pci_dev2 = dev;
2314                                 break;
2315                         }
2316                 }
2317                 if (!nic_data->pci_dev2) {
2318                         netif_err(efx, probe, efx->net_dev,
2319                                   "failed to find secondary function\n");
2320                         rc = -ENODEV;
2321                         goto fail2;
2322                 }
2323         }
2324
2325         /* Now we can reset the NIC */
2326         rc = __falcon_reset_hw(efx, RESET_TYPE_ALL);
2327         if (rc) {
2328                 netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
2329                 goto fail3;
2330         }
2331
2332         /* Allocate memory for INT_KER */
2333         rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t),
2334                                   GFP_KERNEL);
2335         if (rc)
2336                 goto fail4;
2337         BUG_ON(efx->irq_status.dma_addr & 0x0f);
2338
2339         netif_dbg(efx, probe, efx->net_dev,
2340                   "INT_KER at %llx (virt %p phys %llx)\n",
2341                   (u64)efx->irq_status.dma_addr,
2342                   efx->irq_status.addr,
2343                   (u64)virt_to_phys(efx->irq_status.addr));
2344
2345         falcon_probe_spi_devices(efx);
2346
2347         /* Read in the non-volatile configuration */
2348         rc = falcon_probe_nvconfig(efx);
2349         if (rc) {
2350                 if (rc == -EINVAL)
2351                         netif_err(efx, probe, efx->net_dev, "NVRAM is invalid\n");
2352                 goto fail5;
2353         }
2354
2355         efx->max_channels = (efx_nic_rev(efx) <= EFX_REV_FALCON_A1 ? 4 :
2356                              EFX_MAX_CHANNELS);
2357         efx->timer_quantum_ns = 4968; /* 621 cycles */
2358
2359         /* Initialise I2C adapter */
2360         board = falcon_board(efx);
2361         board->i2c_adap.owner = THIS_MODULE;
2362         board->i2c_data = falcon_i2c_bit_operations;
2363         board->i2c_data.data = efx;
2364         board->i2c_adap.algo_data = &board->i2c_data;
2365         board->i2c_adap.dev.parent = &efx->pci_dev->dev;
2366         strlcpy(board->i2c_adap.name, "SFC4000 GPIO",
2367                 sizeof(board->i2c_adap.name));
2368         rc = i2c_bit_add_bus(&board->i2c_adap);
2369         if (rc)
2370                 goto fail5;
2371
2372         rc = falcon_board(efx)->type->init(efx);
2373         if (rc) {
2374                 netif_err(efx, probe, efx->net_dev,
2375                           "failed to initialise board\n");
2376                 goto fail6;
2377         }
2378
2379         nic_data->stats_disable_count = 1;
2380         setup_timer(&nic_data->stats_timer, &falcon_stats_timer_func,
2381                     (unsigned long)efx);
2382
2383         return 0;
2384
2385  fail6:
2386         i2c_del_adapter(&board->i2c_adap);
2387         memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
2388  fail5:
2389         efx_nic_free_buffer(efx, &efx->irq_status);
2390  fail4:
2391  fail3:
2392         if (nic_data->pci_dev2) {
2393                 pci_dev_put(nic_data->pci_dev2);
2394                 nic_data->pci_dev2 = NULL;
2395         }
2396  fail2:
2397  fail1:
2398         kfree(efx->nic_data);
2399         return rc;
2400 }
2401
2402 static void falcon_init_rx_cfg(struct efx_nic *efx)
2403 {
2404         /* RX control FIFO thresholds (32 entries) */
2405         const unsigned ctrl_xon_thr = 20;
2406         const unsigned ctrl_xoff_thr = 25;
2407         efx_oword_t reg;
2408
2409         efx_reado(efx, &reg, FR_AZ_RX_CFG);
2410         if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
2411                 /* Data FIFO size is 5.5K.  The RX DMA engine only
2412                  * supports scattering for user-mode queues, but will
2413                  * split DMA writes at intervals of RX_USR_BUF_SIZE
2414                  * (32-byte units) even for kernel-mode queues.  We
2415                  * set it to be so large that that never happens.
2416                  */
2417                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0);
2418                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE,
2419                                     (3 * 4096) >> 5);
2420                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, 512 >> 8);
2421                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, 2048 >> 8);
2422                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr);
2423                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr);
2424         } else {
2425                 /* Data FIFO size is 80K; register fields moved */
2426                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0);
2427                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE,
2428                                     EFX_RX_USR_BUF_SIZE >> 5);
2429                 /* Send XON and XOFF at ~3 * max MTU away from empty/full */
2430                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, 27648 >> 8);
2431                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, 54272 >> 8);
2432                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr);
2433                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr);
2434                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
2435
2436                 /* Enable hash insertion. This is broken for the
2437                  * 'Falcon' hash so also select Toeplitz TCP/IPv4 and
2438                  * IPv4 hashes. */
2439                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_INSRT_HDR, 1);
2440                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_ALG, 1);
2441                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_IP_HASH, 1);
2442         }
2443         /* Always enable XOFF signal from RX FIFO.  We enable
2444          * or disable transmission of pause frames at the MAC. */
2445         EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
2446         efx_writeo(efx, &reg, FR_AZ_RX_CFG);
2447 }
2448
2449 /* This call performs hardware-specific global initialisation, such as
2450  * defining the descriptor cache sizes and number of RSS channels.
2451  * It does not set up any buffers, descriptor rings or event queues.
2452  */
2453 static int falcon_init_nic(struct efx_nic *efx)
2454 {
2455         efx_oword_t temp;
2456         int rc;
2457
2458         /* Use on-chip SRAM */
2459         efx_reado(efx, &temp, FR_AB_NIC_STAT);
2460         EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1);
2461         efx_writeo(efx, &temp, FR_AB_NIC_STAT);
2462
2463         rc = falcon_reset_sram(efx);
2464         if (rc)
2465                 return rc;
2466
2467         /* Clear the parity enables on the TX data fifos as
2468          * they produce false parity errors because of timing issues
2469          */
2470         if (EFX_WORKAROUND_5129(efx)) {
2471                 efx_reado(efx, &temp, FR_AZ_CSR_SPARE);
2472                 EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0);
2473                 efx_writeo(efx, &temp, FR_AZ_CSR_SPARE);
2474         }
2475
2476         if (EFX_WORKAROUND_7244(efx)) {
2477                 efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL);
2478                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8);
2479                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8);
2480                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8);
2481                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8);
2482                 efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL);
2483         }
2484
2485         /* XXX This is documented only for Falcon A0/A1 */
2486         /* Setup RX.  Wait for descriptor is broken and must
2487          * be disabled.  RXDP recovery shouldn't be needed, but is.
2488          */
2489         efx_reado(efx, &temp, FR_AA_RX_SELF_RST);
2490         EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1);
2491         EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1);
2492         if (EFX_WORKAROUND_5583(efx))
2493                 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1);
2494         efx_writeo(efx, &temp, FR_AA_RX_SELF_RST);
2495
2496         /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
2497          * descriptors (which is bad).
2498          */
2499         efx_reado(efx, &temp, FR_AZ_TX_CFG);
2500         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
2501         efx_writeo(efx, &temp, FR_AZ_TX_CFG);
2502
2503         falcon_init_rx_cfg(efx);
2504
2505         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
2506                 falcon_b0_rx_push_rss_config(efx);
2507
2508                 /* Set destination of both TX and RX Flush events */
2509                 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
2510                 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
2511         }
2512
2513         efx_farch_init_common(efx);
2514
2515         return 0;
2516 }
2517
2518 static void falcon_remove_nic(struct efx_nic *efx)
2519 {
2520         struct falcon_nic_data *nic_data = efx->nic_data;
2521         struct falcon_board *board = falcon_board(efx);
2522
2523         board->type->fini(efx);
2524
2525         /* Remove I2C adapter and clear it in preparation for a retry */
2526         i2c_del_adapter(&board->i2c_adap);
2527         memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
2528
2529         efx_nic_free_buffer(efx, &efx->irq_status);
2530
2531         __falcon_reset_hw(efx, RESET_TYPE_ALL);
2532
2533         /* Release the second function after the reset */
2534         if (nic_data->pci_dev2) {
2535                 pci_dev_put(nic_data->pci_dev2);
2536                 nic_data->pci_dev2 = NULL;
2537         }
2538
2539         /* Tear down the private nic state */
2540         kfree(efx->nic_data);
2541         efx->nic_data = NULL;
2542 }
2543
2544 static size_t falcon_describe_nic_stats(struct efx_nic *efx, u8 *names)
2545 {
2546         return efx_nic_describe_stats(falcon_stat_desc, FALCON_STAT_COUNT,
2547                                       falcon_stat_mask, names);
2548 }
2549
2550 static size_t falcon_update_nic_stats(struct efx_nic *efx, u64 *full_stats,
2551                                       struct rtnl_link_stats64 *core_stats)
2552 {
2553         struct falcon_nic_data *nic_data = efx->nic_data;
2554         u64 *stats = nic_data->stats;
2555         efx_oword_t cnt;
2556
2557         if (!nic_data->stats_disable_count) {
2558                 efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP);
2559                 stats[FALCON_STAT_rx_nodesc_drop_cnt] +=
2560                         EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT);
2561
2562                 if (nic_data->stats_pending &&
2563                     FALCON_XMAC_STATS_DMA_FLAG(efx)) {
2564                         nic_data->stats_pending = false;
2565                         rmb(); /* read the done flag before the stats */
2566                         efx_nic_update_stats(
2567                                 falcon_stat_desc, FALCON_STAT_COUNT,
2568                                 falcon_stat_mask,
2569                                 stats, efx->stats_buffer.addr, true);
2570                 }
2571
2572                 /* Update derived statistic */
2573                 efx_update_diff_stat(&stats[FALCON_STAT_rx_bad_bytes],
2574                                      stats[FALCON_STAT_rx_bytes] -
2575                                      stats[FALCON_STAT_rx_good_bytes] -
2576                                      stats[FALCON_STAT_rx_control] * 64);
2577         }
2578
2579         if (full_stats)
2580                 memcpy(full_stats, stats, sizeof(u64) * FALCON_STAT_COUNT);
2581
2582         if (core_stats) {
2583                 core_stats->rx_packets = stats[FALCON_STAT_rx_packets];
2584                 core_stats->tx_packets = stats[FALCON_STAT_tx_packets];
2585                 core_stats->rx_bytes = stats[FALCON_STAT_rx_bytes];
2586                 core_stats->tx_bytes = stats[FALCON_STAT_tx_bytes];
2587                 core_stats->rx_dropped = stats[FALCON_STAT_rx_nodesc_drop_cnt];
2588                 core_stats->multicast = stats[FALCON_STAT_rx_multicast];
2589                 core_stats->rx_length_errors =
2590                         stats[FALCON_STAT_rx_gtjumbo] +
2591                         stats[FALCON_STAT_rx_length_error];
2592                 core_stats->rx_crc_errors = stats[FALCON_STAT_rx_bad];
2593                 core_stats->rx_frame_errors = stats[FALCON_STAT_rx_align_error];
2594                 core_stats->rx_fifo_errors = stats[FALCON_STAT_rx_overflow];
2595
2596                 core_stats->rx_errors = (core_stats->rx_length_errors +
2597                                          core_stats->rx_crc_errors +
2598                                          core_stats->rx_frame_errors +
2599                                          stats[FALCON_STAT_rx_symbol_error]);
2600         }
2601
2602         return FALCON_STAT_COUNT;
2603 }
2604
2605 void falcon_start_nic_stats(struct efx_nic *efx)
2606 {
2607         struct falcon_nic_data *nic_data = efx->nic_data;
2608
2609         spin_lock_bh(&efx->stats_lock);
2610         if (--nic_data->stats_disable_count == 0)
2611                 falcon_stats_request(efx);
2612         spin_unlock_bh(&efx->stats_lock);
2613 }
2614
2615 /* We don't acutally pull stats on falcon. Wait 10ms so that
2616  * they arrive when we call this just after start_stats
2617  */
2618 static void falcon_pull_nic_stats(struct efx_nic *efx)
2619 {
2620         msleep(10);
2621 }
2622
2623 void falcon_stop_nic_stats(struct efx_nic *efx)
2624 {
2625         struct falcon_nic_data *nic_data = efx->nic_data;
2626         int i;
2627
2628         might_sleep();
2629
2630         spin_lock_bh(&efx->stats_lock);
2631         ++nic_data->stats_disable_count;
2632         spin_unlock_bh(&efx->stats_lock);
2633
2634         del_timer_sync(&nic_data->stats_timer);
2635
2636         /* Wait enough time for the most recent transfer to
2637          * complete. */
2638         for (i = 0; i < 4 && nic_data->stats_pending; i++) {
2639                 if (FALCON_XMAC_STATS_DMA_FLAG(efx))
2640                         break;
2641                 msleep(1);
2642         }
2643
2644         spin_lock_bh(&efx->stats_lock);
2645         falcon_stats_complete(efx);
2646         spin_unlock_bh(&efx->stats_lock);
2647 }
2648
2649 static void falcon_set_id_led(struct efx_nic *efx, enum efx_led_mode mode)
2650 {
2651         falcon_board(efx)->type->set_id_led(efx, mode);
2652 }
2653
2654 /**************************************************************************
2655  *
2656  * Wake on LAN
2657  *
2658  **************************************************************************
2659  */
2660
2661 static void falcon_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
2662 {
2663         wol->supported = 0;
2664         wol->wolopts = 0;
2665         memset(&wol->sopass, 0, sizeof(wol->sopass));
2666 }
2667
2668 static int falcon_set_wol(struct efx_nic *efx, u32 type)
2669 {
2670         if (type != 0)
2671                 return -EINVAL;
2672         return 0;
2673 }
2674
2675 /**************************************************************************
2676  *
2677  * Revision-dependent attributes used by efx.c and nic.c
2678  *
2679  **************************************************************************
2680  */
2681
2682 const struct efx_nic_type falcon_a1_nic_type = {
2683         .mem_map_size = falcon_a1_mem_map_size,
2684         .probe = falcon_probe_nic,
2685         .remove = falcon_remove_nic,
2686         .init = falcon_init_nic,
2687         .dimension_resources = falcon_dimension_resources,
2688         .fini = falcon_irq_ack_a1,
2689         .monitor = falcon_monitor,
2690         .map_reset_reason = falcon_map_reset_reason,
2691         .map_reset_flags = falcon_map_reset_flags,
2692         .reset = falcon_reset_hw,
2693         .probe_port = falcon_probe_port,
2694         .remove_port = falcon_remove_port,
2695         .handle_global_event = falcon_handle_global_event,
2696         .fini_dmaq = efx_farch_fini_dmaq,
2697         .prepare_flush = falcon_prepare_flush,
2698         .finish_flush = efx_port_dummy_op_void,
2699         .describe_stats = falcon_describe_nic_stats,
2700         .update_stats = falcon_update_nic_stats,
2701         .start_stats = falcon_start_nic_stats,
2702         .pull_stats = falcon_pull_nic_stats,
2703         .stop_stats = falcon_stop_nic_stats,
2704         .set_id_led = falcon_set_id_led,
2705         .push_irq_moderation = falcon_push_irq_moderation,
2706         .reconfigure_port = falcon_reconfigure_port,
2707         .prepare_enable_fc_tx = falcon_a1_prepare_enable_fc_tx,
2708         .reconfigure_mac = falcon_reconfigure_xmac,
2709         .check_mac_fault = falcon_xmac_check_fault,
2710         .get_wol = falcon_get_wol,
2711         .set_wol = falcon_set_wol,
2712         .resume_wol = efx_port_dummy_op_void,
2713         .test_nvram = falcon_test_nvram,
2714         .irq_enable_master = efx_farch_irq_enable_master,
2715         .irq_test_generate = efx_farch_irq_test_generate,
2716         .irq_disable_non_ev = efx_farch_irq_disable_master,
2717         .irq_handle_msi = efx_farch_msi_interrupt,
2718         .irq_handle_legacy = falcon_legacy_interrupt_a1,
2719         .tx_probe = efx_farch_tx_probe,
2720         .tx_init = efx_farch_tx_init,
2721         .tx_remove = efx_farch_tx_remove,
2722         .tx_write = efx_farch_tx_write,
2723         .rx_push_rss_config = efx_port_dummy_op_void,
2724         .rx_probe = efx_farch_rx_probe,
2725         .rx_init = efx_farch_rx_init,
2726         .rx_remove = efx_farch_rx_remove,
2727         .rx_write = efx_farch_rx_write,
2728         .rx_defer_refill = efx_farch_rx_defer_refill,
2729         .ev_probe = efx_farch_ev_probe,
2730         .ev_init = efx_farch_ev_init,
2731         .ev_fini = efx_farch_ev_fini,
2732         .ev_remove = efx_farch_ev_remove,
2733         .ev_process = efx_farch_ev_process,
2734         .ev_read_ack = efx_farch_ev_read_ack,
2735         .ev_test_generate = efx_farch_ev_test_generate,
2736
2737         /* We don't expose the filter table on Falcon A1 as it is not
2738          * mapped into function 0, but these implementations still
2739          * work with a degenerate case of all tables set to size 0.
2740          */
2741         .filter_table_probe = efx_farch_filter_table_probe,
2742         .filter_table_restore = efx_farch_filter_table_restore,
2743         .filter_table_remove = efx_farch_filter_table_remove,
2744         .filter_insert = efx_farch_filter_insert,
2745         .filter_remove_safe = efx_farch_filter_remove_safe,
2746         .filter_get_safe = efx_farch_filter_get_safe,
2747         .filter_clear_rx = efx_farch_filter_clear_rx,
2748         .filter_count_rx_used = efx_farch_filter_count_rx_used,
2749         .filter_get_rx_id_limit = efx_farch_filter_get_rx_id_limit,
2750         .filter_get_rx_ids = efx_farch_filter_get_rx_ids,
2751
2752 #ifdef CONFIG_SFC_MTD
2753         .mtd_probe = falcon_mtd_probe,
2754         .mtd_rename = falcon_mtd_rename,
2755         .mtd_read = falcon_mtd_read,
2756         .mtd_erase = falcon_mtd_erase,
2757         .mtd_write = falcon_mtd_write,
2758         .mtd_sync = falcon_mtd_sync,
2759 #endif
2760
2761         .revision = EFX_REV_FALCON_A1,
2762         .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER,
2763         .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER,
2764         .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER,
2765         .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER,
2766         .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER,
2767         .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
2768         .rx_buffer_padding = 0x24,
2769         .can_rx_scatter = false,
2770         .max_interrupt_mode = EFX_INT_MODE_MSI,
2771         .timer_period_max =  1 << FRF_AB_TC_TIMER_VAL_WIDTH,
2772         .offload_features = NETIF_F_IP_CSUM,
2773         .mcdi_max_ver = -1,
2774 };
2775
2776 const struct efx_nic_type falcon_b0_nic_type = {
2777         .mem_map_size = falcon_b0_mem_map_size,
2778         .probe = falcon_probe_nic,
2779         .remove = falcon_remove_nic,
2780         .init = falcon_init_nic,
2781         .dimension_resources = falcon_dimension_resources,
2782         .fini = efx_port_dummy_op_void,
2783         .monitor = falcon_monitor,
2784         .map_reset_reason = falcon_map_reset_reason,
2785         .map_reset_flags = falcon_map_reset_flags,
2786         .reset = falcon_reset_hw,
2787         .probe_port = falcon_probe_port,
2788         .remove_port = falcon_remove_port,
2789         .handle_global_event = falcon_handle_global_event,
2790         .fini_dmaq = efx_farch_fini_dmaq,
2791         .prepare_flush = falcon_prepare_flush,
2792         .finish_flush = efx_port_dummy_op_void,
2793         .describe_stats = falcon_describe_nic_stats,
2794         .update_stats = falcon_update_nic_stats,
2795         .start_stats = falcon_start_nic_stats,
2796         .pull_stats = falcon_pull_nic_stats,
2797         .stop_stats = falcon_stop_nic_stats,
2798         .set_id_led = falcon_set_id_led,
2799         .push_irq_moderation = falcon_push_irq_moderation,
2800         .reconfigure_port = falcon_reconfigure_port,
2801         .prepare_enable_fc_tx = falcon_b0_prepare_enable_fc_tx,
2802         .reconfigure_mac = falcon_reconfigure_xmac,
2803         .check_mac_fault = falcon_xmac_check_fault,
2804         .get_wol = falcon_get_wol,
2805         .set_wol = falcon_set_wol,
2806         .resume_wol = efx_port_dummy_op_void,
2807         .test_chip = falcon_b0_test_chip,
2808         .test_nvram = falcon_test_nvram,
2809         .irq_enable_master = efx_farch_irq_enable_master,
2810         .irq_test_generate = efx_farch_irq_test_generate,
2811         .irq_disable_non_ev = efx_farch_irq_disable_master,
2812         .irq_handle_msi = efx_farch_msi_interrupt,
2813         .irq_handle_legacy = efx_farch_legacy_interrupt,
2814         .tx_probe = efx_farch_tx_probe,
2815         .tx_init = efx_farch_tx_init,
2816         .tx_remove = efx_farch_tx_remove,
2817         .tx_write = efx_farch_tx_write,
2818         .rx_push_rss_config = falcon_b0_rx_push_rss_config,
2819         .rx_probe = efx_farch_rx_probe,
2820         .rx_init = efx_farch_rx_init,
2821         .rx_remove = efx_farch_rx_remove,
2822         .rx_write = efx_farch_rx_write,
2823         .rx_defer_refill = efx_farch_rx_defer_refill,
2824         .ev_probe = efx_farch_ev_probe,
2825         .ev_init = efx_farch_ev_init,
2826         .ev_fini = efx_farch_ev_fini,
2827         .ev_remove = efx_farch_ev_remove,
2828         .ev_process = efx_farch_ev_process,
2829         .ev_read_ack = efx_farch_ev_read_ack,
2830         .ev_test_generate = efx_farch_ev_test_generate,
2831         .filter_table_probe = efx_farch_filter_table_probe,
2832         .filter_table_restore = efx_farch_filter_table_restore,
2833         .filter_table_remove = efx_farch_filter_table_remove,
2834         .filter_update_rx_scatter = efx_farch_filter_update_rx_scatter,
2835         .filter_insert = efx_farch_filter_insert,
2836         .filter_remove_safe = efx_farch_filter_remove_safe,
2837         .filter_get_safe = efx_farch_filter_get_safe,
2838         .filter_clear_rx = efx_farch_filter_clear_rx,
2839         .filter_count_rx_used = efx_farch_filter_count_rx_used,
2840         .filter_get_rx_id_limit = efx_farch_filter_get_rx_id_limit,
2841         .filter_get_rx_ids = efx_farch_filter_get_rx_ids,
2842 #ifdef CONFIG_RFS_ACCEL
2843         .filter_rfs_insert = efx_farch_filter_rfs_insert,
2844         .filter_rfs_expire_one = efx_farch_filter_rfs_expire_one,
2845 #endif
2846 #ifdef CONFIG_SFC_MTD
2847         .mtd_probe = falcon_mtd_probe,
2848         .mtd_rename = falcon_mtd_rename,
2849         .mtd_read = falcon_mtd_read,
2850         .mtd_erase = falcon_mtd_erase,
2851         .mtd_write = falcon_mtd_write,
2852         .mtd_sync = falcon_mtd_sync,
2853 #endif
2854
2855         .revision = EFX_REV_FALCON_B0,
2856         .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
2857         .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
2858         .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
2859         .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
2860         .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
2861         .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
2862         .rx_prefix_size = FS_BZ_RX_PREFIX_SIZE,
2863         .rx_hash_offset = FS_BZ_RX_PREFIX_HASH_OFST,
2864         .rx_buffer_padding = 0,
2865         .can_rx_scatter = true,
2866         .max_interrupt_mode = EFX_INT_MODE_MSIX,
2867         .timer_period_max =  1 << FRF_AB_TC_TIMER_VAL_WIDTH,
2868         .offload_features = NETIF_F_IP_CSUM | NETIF_F_RXHASH | NETIF_F_NTUPLE,
2869         .mcdi_max_ver = -1,
2870         .max_rx_ip_filters = FR_BZ_RX_FILTER_TBL0_ROWS,
2871 };