1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2005-2011 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 /* Common definitions for all Efx net driver code */
13 #ifndef EFX_NET_DRIVER_H
14 #define EFX_NET_DRIVER_H
16 #if defined(EFX_ENABLE_DEBUG) && !defined(DEBUG)
20 #include <linux/netdevice.h>
21 #include <linux/etherdevice.h>
22 #include <linux/ethtool.h>
23 #include <linux/if_vlan.h>
24 #include <linux/timer.h>
25 #include <linux/mdio.h>
26 #include <linux/list.h>
27 #include <linux/pci.h>
28 #include <linux/device.h>
29 #include <linux/highmem.h>
30 #include <linux/workqueue.h>
31 #include <linux/vmalloc.h>
32 #include <linux/i2c.h>
37 /**************************************************************************
41 **************************************************************************/
43 #define EFX_DRIVER_VERSION "3.1"
45 #ifdef EFX_ENABLE_DEBUG
46 #define EFX_BUG_ON_PARANOID(x) BUG_ON(x)
47 #define EFX_WARN_ON_PARANOID(x) WARN_ON(x)
49 #define EFX_BUG_ON_PARANOID(x) do {} while (0)
50 #define EFX_WARN_ON_PARANOID(x) do {} while (0)
53 /**************************************************************************
57 **************************************************************************/
59 #define EFX_MAX_CHANNELS 32
60 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS
62 /* Checksum generation is a per-queue option in hardware, so each
63 * queue visible to the networking core is backed by two hardware TX
65 #define EFX_MAX_TX_TC 2
66 #define EFX_MAX_CORE_TX_QUEUES (EFX_MAX_TX_TC * EFX_MAX_CHANNELS)
67 #define EFX_TXQ_TYPE_OFFLOAD 1 /* flag */
68 #define EFX_TXQ_TYPE_HIGHPRI 2 /* flag */
69 #define EFX_TXQ_TYPES 4
70 #define EFX_MAX_TX_QUEUES (EFX_TXQ_TYPES * EFX_MAX_CHANNELS)
73 * struct efx_special_buffer - An Efx special buffer
74 * @addr: CPU base address of the buffer
75 * @dma_addr: DMA base address of the buffer
76 * @len: Buffer length, in bytes
77 * @index: Buffer index within controller;s buffer table
78 * @entries: Number of buffer table entries
80 * Special buffers are used for the event queues and the TX and RX
81 * descriptor queues for each channel. They are *not* used for the
82 * actual transmit and receive buffers.
84 struct efx_special_buffer {
92 enum efx_flush_state {
100 * struct efx_tx_buffer - An Efx TX buffer
101 * @skb: The associated socket buffer.
102 * Set only on the final fragment of a packet; %NULL for all other
103 * fragments. When this fragment completes, then we can free this
105 * @tsoh: The associated TSO header structure, or %NULL if this
106 * buffer is not a TSO header.
107 * @dma_addr: DMA address of the fragment.
108 * @len: Length of this fragment.
109 * This field is zero when the queue slot is empty.
110 * @continuation: True if this fragment is not the end of a packet.
111 * @unmap_single: True if pci_unmap_single should be used.
112 * @unmap_len: Length of this fragment to unmap
114 struct efx_tx_buffer {
115 const struct sk_buff *skb;
116 struct efx_tso_header *tsoh;
121 unsigned short unmap_len;
125 * struct efx_tx_queue - An Efx TX queue
127 * This is a ring buffer of TX fragments.
128 * Since the TX completion path always executes on the same
129 * CPU and the xmit path can operate on different CPUs,
130 * performance is increased by ensuring that the completion
131 * path and the xmit path operate on different cache lines.
132 * This is particularly important if the xmit path is always
133 * executing on one CPU which is different from the completion
134 * path. There is also a cache line for members which are
135 * read but not written on the fast path.
137 * @efx: The associated Efx NIC
138 * @queue: DMA queue number
139 * @channel: The associated channel
140 * @core_txq: The networking core TX queue structure
141 * @buffer: The software buffer ring
142 * @txd: The hardware descriptor ring
143 * @ptr_mask: The size of the ring minus 1.
144 * @initialised: Has hardware queue been initialised?
145 * @flushed: Used when handling queue flushing
146 * @read_count: Current read pointer.
147 * This is the number of buffers that have been removed from both rings.
148 * @old_write_count: The value of @write_count when last checked.
149 * This is here for performance reasons. The xmit path will
150 * only get the up-to-date value of @write_count if this
151 * variable indicates that the queue is empty. This is to
152 * avoid cache-line ping-pong between the xmit path and the
154 * @insert_count: Current insert pointer
155 * This is the number of buffers that have been added to the
157 * @write_count: Current write pointer
158 * This is the number of buffers that have been added to the
160 * @old_read_count: The value of read_count when last checked.
161 * This is here for performance reasons. The xmit path will
162 * only get the up-to-date value of read_count if this
163 * variable indicates that the queue is full. This is to
164 * avoid cache-line ping-pong between the xmit path and the
166 * @tso_headers_free: A list of TSO headers allocated for this TX queue
167 * that are not in use, and so available for new TSO sends. The list
168 * is protected by the TX queue lock.
169 * @tso_bursts: Number of times TSO xmit invoked by kernel
170 * @tso_long_headers: Number of packets with headers too long for standard
172 * @tso_packets: Number of packets via the TSO xmit path
173 * @pushes: Number of times the TX push feature has been used
174 * @empty_read_count: If the completion path has seen the queue as empty
175 * and the transmission path has not yet checked this, the value of
176 * @read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0.
178 struct efx_tx_queue {
179 /* Members which don't change on the fast path */
180 struct efx_nic *efx ____cacheline_aligned_in_smp;
182 struct efx_channel *channel;
183 struct netdev_queue *core_txq;
184 struct efx_tx_buffer *buffer;
185 struct efx_special_buffer txd;
186 unsigned int ptr_mask;
188 enum efx_flush_state flushed;
190 /* Members used mainly on the completion path */
191 unsigned int read_count ____cacheline_aligned_in_smp;
192 unsigned int old_write_count;
194 /* Members used only on the xmit path */
195 unsigned int insert_count ____cacheline_aligned_in_smp;
196 unsigned int write_count;
197 unsigned int old_read_count;
198 struct efx_tso_header *tso_headers_free;
199 unsigned int tso_bursts;
200 unsigned int tso_long_headers;
201 unsigned int tso_packets;
204 /* Members shared between paths and sometimes updated */
205 unsigned int empty_read_count ____cacheline_aligned_in_smp;
206 #define EFX_EMPTY_COUNT_VALID 0x80000000
210 * struct efx_rx_buffer - An Efx RX data buffer
211 * @dma_addr: DMA base address of the buffer
212 * @skb: The associated socket buffer, if any.
213 * If both this and page are %NULL, the buffer slot is currently free.
214 * @page: The associated page buffer, if any.
215 * If both this and skb are %NULL, the buffer slot is currently free.
216 * @len: Buffer length, in bytes.
217 * @is_page: Indicates if @page is valid. If false, @skb is valid.
219 struct efx_rx_buffer {
230 * struct efx_rx_page_state - Page-based rx buffer state
232 * Inserted at the start of every page allocated for receive buffers.
233 * Used to facilitate sharing dma mappings between recycled rx buffers
234 * and those passed up to the kernel.
236 * @refcnt: Number of struct efx_rx_buffer's referencing this page.
237 * When refcnt falls to zero, the page is unmapped for dma
238 * @dma_addr: The dma address of this page.
240 struct efx_rx_page_state {
244 unsigned int __pad[0] ____cacheline_aligned;
248 * struct efx_rx_queue - An Efx RX queue
249 * @efx: The associated Efx NIC
250 * @buffer: The software buffer ring
251 * @rxd: The hardware descriptor ring
252 * @ptr_mask: The size of the ring minus 1.
253 * @added_count: Number of buffers added to the receive queue.
254 * @notified_count: Number of buffers given to NIC (<= @added_count).
255 * @removed_count: Number of buffers removed from the receive queue.
256 * @max_fill: RX descriptor maximum fill level (<= ring size)
257 * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill
259 * @fast_fill_limit: The level to which a fast fill will fill
260 * (@fast_fill_trigger <= @fast_fill_limit <= @max_fill)
261 * @min_fill: RX descriptor minimum non-zero fill level.
262 * This records the minimum fill level observed when a ring
263 * refill was triggered.
264 * @alloc_page_count: RX allocation strategy counter.
265 * @alloc_skb_count: RX allocation strategy counter.
266 * @slow_fill: Timer used to defer efx_nic_generate_fill_event().
267 * @flushed: Use when handling queue flushing
269 struct efx_rx_queue {
271 struct efx_rx_buffer *buffer;
272 struct efx_special_buffer rxd;
273 unsigned int ptr_mask;
278 unsigned int max_fill;
279 unsigned int fast_fill_trigger;
280 unsigned int fast_fill_limit;
281 unsigned int min_fill;
282 unsigned int min_overfill;
283 unsigned int alloc_page_count;
284 unsigned int alloc_skb_count;
285 struct timer_list slow_fill;
286 unsigned int slow_fill_count;
288 enum efx_flush_state flushed;
292 * struct efx_buffer - An Efx general-purpose buffer
293 * @addr: host base address of the buffer
294 * @dma_addr: DMA base address of the buffer
295 * @len: Buffer length, in bytes
297 * The NIC uses these buffers for its interrupt status registers and
307 enum efx_rx_alloc_method {
308 RX_ALLOC_METHOD_AUTO = 0,
309 RX_ALLOC_METHOD_SKB = 1,
310 RX_ALLOC_METHOD_PAGE = 2,
314 * struct efx_channel - An Efx channel
316 * A channel comprises an event queue, at least one TX queue, at least
317 * one RX queue, and an associated tasklet for processing the event
320 * @efx: Associated Efx NIC
321 * @channel: Channel instance number
322 * @enabled: Channel enabled indicator
323 * @irq: IRQ number (MSI and MSI-X only)
324 * @irq_moderation: IRQ moderation value (in hardware ticks)
325 * @napi_dev: Net device used with NAPI
326 * @napi_str: NAPI control structure
327 * @work_pending: Is work pending via NAPI?
328 * @eventq: Event queue buffer
329 * @eventq_mask: Event queue pointer mask
330 * @eventq_read_ptr: Event queue read pointer
331 * @last_eventq_read_ptr: Last event queue read pointer value.
332 * @irq_count: Number of IRQs since last adaptive moderation decision
333 * @irq_mod_score: IRQ moderation score
334 * @rx_alloc_level: Watermark based heuristic counter for pushing descriptors
335 * and diagnostic counters
336 * @rx_alloc_push_pages: RX allocation method currently in use for pushing
338 * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors
339 * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors
340 * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors
341 * @n_rx_mcast_mismatch: Count of unmatched multicast frames
342 * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors
343 * @n_rx_overlength: Count of RX_OVERLENGTH errors
344 * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun
345 * @rx_queue: RX queue for this channel
346 * @tx_queue: TX queues for this channel
353 unsigned int irq_moderation;
354 struct net_device *napi_dev;
355 struct napi_struct napi_str;
357 struct efx_special_buffer eventq;
358 unsigned int eventq_mask;
359 unsigned int eventq_read_ptr;
360 unsigned int last_eventq_read_ptr;
362 unsigned int irq_count;
363 unsigned int irq_mod_score;
364 #ifdef CONFIG_RFS_ACCEL
365 unsigned int rfs_filters_added;
369 int rx_alloc_push_pages;
371 unsigned n_rx_tobe_disc;
372 unsigned n_rx_ip_hdr_chksum_err;
373 unsigned n_rx_tcp_udp_chksum_err;
374 unsigned n_rx_mcast_mismatch;
375 unsigned n_rx_frm_trunc;
376 unsigned n_rx_overlength;
377 unsigned n_skbuff_leaks;
379 /* Used to pipeline received packets in order to optimise memory
380 * access with prefetches.
382 struct efx_rx_buffer *rx_pkt;
385 struct efx_rx_queue rx_queue;
386 struct efx_tx_queue tx_queue[EFX_TXQ_TYPES];
395 #define STRING_TABLE_LOOKUP(val, member) \
396 ((val) < member ## _max) ? member ## _names[val] : "(invalid)"
398 extern const char *const efx_loopback_mode_names[];
399 extern const unsigned int efx_loopback_mode_max;
400 #define LOOPBACK_MODE(efx) \
401 STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode)
403 extern const char *const efx_reset_type_names[];
404 extern const unsigned int efx_reset_type_max;
405 #define RESET_TYPE(type) \
406 STRING_TABLE_LOOKUP(type, efx_reset_type)
409 /* Be careful if altering to correct macro below */
410 EFX_INT_MODE_MSIX = 0,
411 EFX_INT_MODE_MSI = 1,
412 EFX_INT_MODE_LEGACY = 2,
413 EFX_INT_MODE_MAX /* Insert any new items before this */
415 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
426 * Alignment of page-allocated RX buffers
428 * Controls the number of bytes inserted at the start of an RX buffer.
429 * This is the equivalent of NET_IP_ALIGN [which controls the alignment
430 * of the skb->head for hardware DMA].
432 #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
433 #define EFX_PAGE_IP_ALIGN 0
435 #define EFX_PAGE_IP_ALIGN NET_IP_ALIGN
439 * Alignment of the skb->head which wraps a page-allocated RX buffer
441 * The skb allocated to wrap an rx_buffer can have this alignment. Since
442 * the data is memcpy'd from the rx_buf, it does not need to be equal to
445 #define EFX_PAGE_SKB_ALIGN 2
447 /* Forward declaration */
450 /* Pseudo bit-mask flow control field */
451 #define EFX_FC_RX FLOW_CTRL_RX
452 #define EFX_FC_TX FLOW_CTRL_TX
453 #define EFX_FC_AUTO 4
456 * struct efx_link_state - Current state of the link
458 * @fd: Link is full-duplex
459 * @fc: Actual flow control flags
460 * @speed: Link speed (Mbps)
462 struct efx_link_state {
469 static inline bool efx_link_state_equal(const struct efx_link_state *left,
470 const struct efx_link_state *right)
472 return left->up == right->up && left->fd == right->fd &&
473 left->fc == right->fc && left->speed == right->speed;
477 * struct efx_phy_operations - Efx PHY operations table
478 * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds,
479 * efx->loopback_modes.
480 * @init: Initialise PHY
481 * @fini: Shut down PHY
482 * @reconfigure: Reconfigure PHY (e.g. for new link parameters)
483 * @poll: Update @link_state and report whether it changed.
484 * Serialised by the mac_lock.
485 * @get_settings: Get ethtool settings. Serialised by the mac_lock.
486 * @set_settings: Set ethtool settings. Serialised by the mac_lock.
487 * @set_npage_adv: Set abilities advertised in (Extended) Next Page
488 * (only needed where AN bit is set in mmds)
489 * @test_alive: Test that PHY is 'alive' (online)
490 * @test_name: Get the name of a PHY-specific test/result
491 * @run_tests: Run tests and record results as appropriate (offline).
492 * Flags are the ethtool tests flags.
494 struct efx_phy_operations {
495 int (*probe) (struct efx_nic *efx);
496 int (*init) (struct efx_nic *efx);
497 void (*fini) (struct efx_nic *efx);
498 void (*remove) (struct efx_nic *efx);
499 int (*reconfigure) (struct efx_nic *efx);
500 bool (*poll) (struct efx_nic *efx);
501 void (*get_settings) (struct efx_nic *efx,
502 struct ethtool_cmd *ecmd);
503 int (*set_settings) (struct efx_nic *efx,
504 struct ethtool_cmd *ecmd);
505 void (*set_npage_adv) (struct efx_nic *efx, u32);
506 int (*test_alive) (struct efx_nic *efx);
507 const char *(*test_name) (struct efx_nic *efx, unsigned int index);
508 int (*run_tests) (struct efx_nic *efx, int *results, unsigned flags);
512 * @enum efx_phy_mode - PHY operating mode flags
513 * @PHY_MODE_NORMAL: on and should pass traffic
514 * @PHY_MODE_TX_DISABLED: on with TX disabled
515 * @PHY_MODE_LOW_POWER: set to low power through MDIO
516 * @PHY_MODE_OFF: switched off through external control
517 * @PHY_MODE_SPECIAL: on but will not pass traffic
521 PHY_MODE_TX_DISABLED = 1,
522 PHY_MODE_LOW_POWER = 2,
524 PHY_MODE_SPECIAL = 8,
527 static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode)
529 return !!(mode & ~PHY_MODE_TX_DISABLED);
533 * Efx extended statistics
535 * Not all statistics are provided by all supported MACs. The purpose
536 * is this structure is to contain the raw statistics provided by each
539 struct efx_mac_stats {
543 unsigned long tx_packets;
544 unsigned long tx_bad;
545 unsigned long tx_pause;
546 unsigned long tx_control;
547 unsigned long tx_unicast;
548 unsigned long tx_multicast;
549 unsigned long tx_broadcast;
550 unsigned long tx_lt64;
552 unsigned long tx_65_to_127;
553 unsigned long tx_128_to_255;
554 unsigned long tx_256_to_511;
555 unsigned long tx_512_to_1023;
556 unsigned long tx_1024_to_15xx;
557 unsigned long tx_15xx_to_jumbo;
558 unsigned long tx_gtjumbo;
559 unsigned long tx_collision;
560 unsigned long tx_single_collision;
561 unsigned long tx_multiple_collision;
562 unsigned long tx_excessive_collision;
563 unsigned long tx_deferred;
564 unsigned long tx_late_collision;
565 unsigned long tx_excessive_deferred;
566 unsigned long tx_non_tcpudp;
567 unsigned long tx_mac_src_error;
568 unsigned long tx_ip_src_error;
572 unsigned long rx_packets;
573 unsigned long rx_good;
574 unsigned long rx_bad;
575 unsigned long rx_pause;
576 unsigned long rx_control;
577 unsigned long rx_unicast;
578 unsigned long rx_multicast;
579 unsigned long rx_broadcast;
580 unsigned long rx_lt64;
582 unsigned long rx_65_to_127;
583 unsigned long rx_128_to_255;
584 unsigned long rx_256_to_511;
585 unsigned long rx_512_to_1023;
586 unsigned long rx_1024_to_15xx;
587 unsigned long rx_15xx_to_jumbo;
588 unsigned long rx_gtjumbo;
589 unsigned long rx_bad_lt64;
590 unsigned long rx_bad_64_to_15xx;
591 unsigned long rx_bad_15xx_to_jumbo;
592 unsigned long rx_bad_gtjumbo;
593 unsigned long rx_overflow;
594 unsigned long rx_missed;
595 unsigned long rx_false_carrier;
596 unsigned long rx_symbol_error;
597 unsigned long rx_align_error;
598 unsigned long rx_length_error;
599 unsigned long rx_internal_error;
600 unsigned long rx_good_lt64;
603 /* Number of bits used in a multicast filter hash address */
604 #define EFX_MCAST_HASH_BITS 8
606 /* Number of (single-bit) entries in a multicast filter hash */
607 #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS)
609 /* An Efx multicast filter hash */
610 union efx_multicast_hash {
611 u8 byte[EFX_MCAST_HASH_ENTRIES / 8];
612 efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8];
615 struct efx_filter_state;
618 * struct efx_nic - an Efx NIC
619 * @name: Device name (net device name or bus id before net device registered)
620 * @pci_dev: The PCI device
621 * @type: Controller type attributes
622 * @legacy_irq: IRQ number
623 * @legacy_irq_enabled: Are IRQs enabled on NIC (INT_EN_KER register)?
624 * @workqueue: Workqueue for port reconfigures and the HW monitor.
625 * Work items do not hold and must not acquire RTNL.
626 * @workqueue_name: Name of workqueue
627 * @reset_work: Scheduled reset workitem
628 * @membase_phys: Memory BAR value as physical address
629 * @membase: Memory BAR value
630 * @interrupt_mode: Interrupt mode
631 * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues
632 * @irq_rx_moderation: IRQ moderation time for RX event queues
633 * @msg_enable: Log message enable flags
634 * @state: Device state flag. Serialised by the rtnl_lock.
635 * @reset_pending: Bitmask for pending resets
636 * @tx_queue: TX DMA queues
637 * @rx_queue: RX DMA queues
639 * @channel_name: Names for channels and their IRQs
640 * @rxq_entries: Size of receive queues requested by user.
641 * @txq_entries: Size of transmit queues requested by user.
642 * @next_buffer_table: First available buffer table id
643 * @n_channels: Number of channels in use
644 * @n_rx_channels: Number of channels used for RX (= number of RX queues)
645 * @n_tx_channels: Number of channels used for TX
646 * @rx_buffer_len: RX buffer length
647 * @rx_buffer_order: Order (log2) of number of pages for each RX buffer
648 * @rx_hash_key: Toeplitz hash key for RSS
649 * @rx_indir_table: Indirection table for RSS
650 * @int_error_count: Number of internal errors seen recently
651 * @int_error_expire: Time at which error count will be expired
652 * @irq_status: Interrupt status buffer
653 * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0
654 * @fatal_irq_level: IRQ level (bit number) used for serious errors
655 * @mtd_list: List of MTDs attached to the NIC
656 * @nic_data: Hardware dependent state
657 * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode,
658 * efx_monitor() and efx_reconfigure_port()
659 * @port_enabled: Port enabled indicator.
660 * Serialises efx_stop_all(), efx_start_all(), efx_monitor() and
661 * efx_mac_work() with kernel interfaces. Safe to read under any
662 * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must
663 * be held to modify it.
664 * @port_initialized: Port initialized?
665 * @net_dev: Operating system network device. Consider holding the rtnl lock
666 * @stats_buffer: DMA buffer for statistics
667 * @phy_type: PHY type
668 * @phy_op: PHY interface
669 * @phy_data: PHY private data (including PHY-specific stats)
670 * @mdio: PHY MDIO interface
671 * @mdio_bus: PHY MDIO bus ID (only used by Siena)
672 * @phy_mode: PHY operating mode. Serialised by @mac_lock.
673 * @link_advertising: Autonegotiation advertising flags
674 * @link_state: Current state of the link
675 * @n_link_state_changes: Number of times the link has changed state
676 * @promiscuous: Promiscuous flag. Protected by netif_tx_lock.
677 * @multicast_hash: Multicast hash table
678 * @wanted_fc: Wanted flow control flags
679 * @mac_work: Work item for changing MAC promiscuity and multicast hash
680 * @loopback_mode: Loopback status
681 * @loopback_modes: Supported loopback mode bitmask
682 * @loopback_selftest: Offline self-test private state
683 * @monitor_work: Hardware monitor workitem
684 * @biu_lock: BIU (bus interface unit) lock
685 * @last_irq_cpu: Last CPU to handle interrupt.
686 * This register is written with the SMP processor ID whenever an
687 * interrupt is handled. It is used by efx_nic_test_interrupt()
688 * to verify that an interrupt has occurred.
689 * @n_rx_nodesc_drop_cnt: RX no descriptor drop count
690 * @mac_stats: MAC statistics. These include all statistics the MACs
691 * can provide. Generic code converts these into a standard
692 * &struct net_device_stats.
693 * @stats_lock: Statistics update lock. Serialises statistics fetches
694 * and access to @mac_stats.
696 * This is stored in the private area of the &struct net_device.
699 /* The following fields should be written very rarely */
702 struct pci_dev *pci_dev;
703 const struct efx_nic_type *type;
705 bool legacy_irq_enabled;
706 struct workqueue_struct *workqueue;
707 char workqueue_name[16];
708 struct work_struct reset_work;
709 resource_size_t membase_phys;
710 void __iomem *membase;
712 enum efx_int_mode interrupt_mode;
713 bool irq_rx_adaptive;
714 unsigned int irq_rx_moderation;
717 enum nic_state state;
718 unsigned long reset_pending;
720 struct efx_channel *channel[EFX_MAX_CHANNELS];
721 char channel_name[EFX_MAX_CHANNELS][IFNAMSIZ + 6];
723 unsigned rxq_entries;
724 unsigned txq_entries;
725 unsigned next_buffer_table;
727 unsigned n_rx_channels;
728 unsigned tx_channel_offset;
729 unsigned n_tx_channels;
730 unsigned int rx_buffer_len;
731 unsigned int rx_buffer_order;
733 u32 rx_indir_table[128];
735 unsigned int_error_count;
736 unsigned long int_error_expire;
738 struct efx_buffer irq_status;
739 unsigned irq_zero_count;
740 unsigned fatal_irq_level;
742 #ifdef CONFIG_SFC_MTD
743 struct list_head mtd_list;
748 struct mutex mac_lock;
749 struct work_struct mac_work;
752 bool port_initialized;
753 struct net_device *net_dev;
755 struct efx_buffer stats_buffer;
757 unsigned int phy_type;
758 const struct efx_phy_operations *phy_op;
760 struct mdio_if_info mdio;
761 unsigned int mdio_bus;
762 enum efx_phy_mode phy_mode;
764 u32 link_advertising;
765 struct efx_link_state link_state;
766 unsigned int n_link_state_changes;
769 union efx_multicast_hash multicast_hash;
773 enum efx_loopback_mode loopback_mode;
776 void *loopback_selftest;
778 struct efx_filter_state *filter_state;
780 /* The following fields may be written more often */
782 struct delayed_work monitor_work ____cacheline_aligned_in_smp;
784 volatile signed int last_irq_cpu;
785 unsigned n_rx_nodesc_drop_cnt;
786 struct efx_mac_stats mac_stats;
787 spinlock_t stats_lock;
790 static inline int efx_dev_registered(struct efx_nic *efx)
792 return efx->net_dev->reg_state == NETREG_REGISTERED;
795 /* Net device name, for inclusion in log messages if it has been registered.
796 * Use efx->name not efx->net_dev->name so that races with (un)registration
799 static inline const char *efx_dev_name(struct efx_nic *efx)
801 return efx_dev_registered(efx) ? efx->name : "";
804 static inline unsigned int efx_port_num(struct efx_nic *efx)
806 return efx->net_dev->dev_id;
810 * struct efx_nic_type - Efx device type definition
811 * @probe: Probe the controller
812 * @remove: Free resources allocated by probe()
813 * @init: Initialise the controller
814 * @fini: Shut down the controller
815 * @monitor: Periodic function for polling link state and hardware monitor
816 * @map_reset_reason: Map ethtool reset reason to a reset method
817 * @map_reset_flags: Map ethtool reset flags to a reset method, if possible
818 * @reset: Reset the controller hardware and possibly the PHY. This will
819 * be called while the controller is uninitialised.
820 * @probe_port: Probe the MAC and PHY
821 * @remove_port: Free resources allocated by probe_port()
822 * @handle_global_event: Handle a "global" event (may be %NULL)
823 * @prepare_flush: Prepare the hardware for flushing the DMA queues
824 * @update_stats: Update statistics not provided by event handling
825 * @start_stats: Start the regular fetching of statistics
826 * @stop_stats: Stop the regular fetching of statistics
827 * @set_id_led: Set state of identifying LED or revert to automatic function
828 * @push_irq_moderation: Apply interrupt moderation value
829 * @push_multicast_hash: Apply multicast hash table
830 * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY
831 * @reconfigure_mac: Reconfigure MAC only. Serialised by the mac_lock
832 * @check_mac_fault: Check MAC fault state. True if fault present.
833 * @get_wol: Get WoL configuration from driver state
834 * @set_wol: Push WoL configuration to the NIC
835 * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume)
836 * @test_registers: Test read/write functionality of control registers
837 * @test_nvram: Test validity of NVRAM contents
838 * @revision: Hardware architecture revision
839 * @mem_map_size: Memory BAR mapped size
840 * @txd_ptr_tbl_base: TX descriptor ring base address
841 * @rxd_ptr_tbl_base: RX descriptor ring base address
842 * @buf_tbl_base: Buffer table base address
843 * @evq_ptr_tbl_base: Event queue pointer table base address
844 * @evq_rptr_tbl_base: Event queue read-pointer table base address
845 * @max_dma_mask: Maximum possible DMA mask
846 * @rx_buffer_hash_size: Size of hash at start of RX buffer
847 * @rx_buffer_padding: Size of padding at end of RX buffer
848 * @max_interrupt_mode: Highest capability interrupt mode supported
849 * from &enum efx_init_mode.
850 * @phys_addr_channels: Number of channels with physically addressed
852 * @tx_dc_base: Base address in SRAM of TX queue descriptor caches
853 * @rx_dc_base: Base address in SRAM of RX queue descriptor caches
854 * @offload_features: net_device feature flags for protocol offload
855 * features implemented in hardware
857 struct efx_nic_type {
858 int (*probe)(struct efx_nic *efx);
859 void (*remove)(struct efx_nic *efx);
860 int (*init)(struct efx_nic *efx);
861 void (*fini)(struct efx_nic *efx);
862 void (*monitor)(struct efx_nic *efx);
863 enum reset_type (*map_reset_reason)(enum reset_type reason);
864 int (*map_reset_flags)(u32 *flags);
865 int (*reset)(struct efx_nic *efx, enum reset_type method);
866 int (*probe_port)(struct efx_nic *efx);
867 void (*remove_port)(struct efx_nic *efx);
868 bool (*handle_global_event)(struct efx_channel *channel, efx_qword_t *);
869 void (*prepare_flush)(struct efx_nic *efx);
870 void (*update_stats)(struct efx_nic *efx);
871 void (*start_stats)(struct efx_nic *efx);
872 void (*stop_stats)(struct efx_nic *efx);
873 void (*set_id_led)(struct efx_nic *efx, enum efx_led_mode mode);
874 void (*push_irq_moderation)(struct efx_channel *channel);
875 void (*push_multicast_hash)(struct efx_nic *efx);
876 int (*reconfigure_port)(struct efx_nic *efx);
877 int (*reconfigure_mac)(struct efx_nic *efx);
878 bool (*check_mac_fault)(struct efx_nic *efx);
879 void (*get_wol)(struct efx_nic *efx, struct ethtool_wolinfo *wol);
880 int (*set_wol)(struct efx_nic *efx, u32 type);
881 void (*resume_wol)(struct efx_nic *efx);
882 int (*test_registers)(struct efx_nic *efx);
883 int (*test_nvram)(struct efx_nic *efx);
886 unsigned int mem_map_size;
887 unsigned int txd_ptr_tbl_base;
888 unsigned int rxd_ptr_tbl_base;
889 unsigned int buf_tbl_base;
890 unsigned int evq_ptr_tbl_base;
891 unsigned int evq_rptr_tbl_base;
893 unsigned int rx_buffer_hash_size;
894 unsigned int rx_buffer_padding;
895 unsigned int max_interrupt_mode;
896 unsigned int phys_addr_channels;
897 unsigned int tx_dc_base;
898 unsigned int rx_dc_base;
899 netdev_features_t offload_features;
902 /**************************************************************************
904 * Prototypes and inline functions
906 *************************************************************************/
908 static inline struct efx_channel *
909 efx_get_channel(struct efx_nic *efx, unsigned index)
911 EFX_BUG_ON_PARANOID(index >= efx->n_channels);
912 return efx->channel[index];
915 /* Iterate over all used channels */
916 #define efx_for_each_channel(_channel, _efx) \
917 for (_channel = (_efx)->channel[0]; \
919 _channel = (_channel->channel + 1 < (_efx)->n_channels) ? \
920 (_efx)->channel[_channel->channel + 1] : NULL)
922 static inline struct efx_tx_queue *
923 efx_get_tx_queue(struct efx_nic *efx, unsigned index, unsigned type)
925 EFX_BUG_ON_PARANOID(index >= efx->n_tx_channels ||
926 type >= EFX_TXQ_TYPES);
927 return &efx->channel[efx->tx_channel_offset + index]->tx_queue[type];
930 static inline bool efx_channel_has_tx_queues(struct efx_channel *channel)
932 return channel->channel - channel->efx->tx_channel_offset <
933 channel->efx->n_tx_channels;
936 static inline struct efx_tx_queue *
937 efx_channel_get_tx_queue(struct efx_channel *channel, unsigned type)
939 EFX_BUG_ON_PARANOID(!efx_channel_has_tx_queues(channel) ||
940 type >= EFX_TXQ_TYPES);
941 return &channel->tx_queue[type];
944 static inline bool efx_tx_queue_used(struct efx_tx_queue *tx_queue)
946 return !(tx_queue->efx->net_dev->num_tc < 2 &&
947 tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI);
950 /* Iterate over all TX queues belonging to a channel */
951 #define efx_for_each_channel_tx_queue(_tx_queue, _channel) \
952 if (!efx_channel_has_tx_queues(_channel)) \
955 for (_tx_queue = (_channel)->tx_queue; \
956 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES && \
957 efx_tx_queue_used(_tx_queue); \
960 /* Iterate over all possible TX queues belonging to a channel */
961 #define efx_for_each_possible_channel_tx_queue(_tx_queue, _channel) \
962 for (_tx_queue = (_channel)->tx_queue; \
963 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES; \
966 static inline struct efx_rx_queue *
967 efx_get_rx_queue(struct efx_nic *efx, unsigned index)
969 EFX_BUG_ON_PARANOID(index >= efx->n_rx_channels);
970 return &efx->channel[index]->rx_queue;
973 static inline bool efx_channel_has_rx_queue(struct efx_channel *channel)
975 return channel->channel < channel->efx->n_rx_channels;
978 static inline struct efx_rx_queue *
979 efx_channel_get_rx_queue(struct efx_channel *channel)
981 EFX_BUG_ON_PARANOID(!efx_channel_has_rx_queue(channel));
982 return &channel->rx_queue;
985 /* Iterate over all RX queues belonging to a channel */
986 #define efx_for_each_channel_rx_queue(_rx_queue, _channel) \
987 if (!efx_channel_has_rx_queue(_channel)) \
990 for (_rx_queue = &(_channel)->rx_queue; \
994 static inline struct efx_channel *
995 efx_rx_queue_channel(struct efx_rx_queue *rx_queue)
997 return container_of(rx_queue, struct efx_channel, rx_queue);
1000 static inline int efx_rx_queue_index(struct efx_rx_queue *rx_queue)
1002 return efx_rx_queue_channel(rx_queue)->channel;
1005 /* Returns a pointer to the specified receive buffer in the RX
1008 static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue,
1011 return &rx_queue->buffer[index];
1014 /* Set bit in a little-endian bitfield */
1015 static inline void set_bit_le(unsigned nr, unsigned char *addr)
1017 addr[nr / 8] |= (1 << (nr % 8));
1020 /* Clear bit in a little-endian bitfield */
1021 static inline void clear_bit_le(unsigned nr, unsigned char *addr)
1023 addr[nr / 8] &= ~(1 << (nr % 8));
1028 * EFX_MAX_FRAME_LEN - calculate maximum frame length
1030 * This calculates the maximum frame length that will be used for a
1031 * given MTU. The frame length will be equal to the MTU plus a
1032 * constant amount of header space and padding. This is the quantity
1033 * that the net driver will program into the MAC as the maximum frame
1036 * The 10G MAC requires 8-byte alignment on the frame
1037 * length, so we round up to the nearest 8.
1039 * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an
1040 * XGMII cycle). If the frame length reaches the maximum value in the
1041 * same cycle, the XMAC can miss the IPG altogether. We work around
1042 * this by adding a further 16 bytes.
1044 #define EFX_MAX_FRAME_LEN(mtu) \
1045 ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */ + 7) & ~7) + 16)
1048 #endif /* EFX_NET_DRIVER_H */