1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2010 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/slab.h>
16 #include <linux/random.h>
17 #include "net_driver.h"
21 #include "farch_regs.h"
24 #include "workarounds.h"
26 #include "mcdi_pcol.h"
29 /* Hardware control for SFC9000 family including SFL9021 (aka Siena). */
31 static void siena_init_wol(struct efx_nic *efx);
34 static void siena_push_irq_moderation(struct efx_channel *channel)
36 efx_dword_t timer_cmd;
38 if (channel->irq_moderation)
39 EFX_POPULATE_DWORD_2(timer_cmd,
41 FFE_CZ_TIMER_MODE_INT_HLDOFF,
43 channel->irq_moderation - 1);
45 EFX_POPULATE_DWORD_2(timer_cmd,
47 FFE_CZ_TIMER_MODE_DIS,
48 FRF_CZ_TC_TIMER_VAL, 0);
49 efx_writed_page_locked(channel->efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
53 void siena_prepare_flush(struct efx_nic *efx)
55 if (efx->fc_disable++ == 0)
56 efx_mcdi_set_mac(efx);
59 void siena_finish_flush(struct efx_nic *efx)
61 if (--efx->fc_disable == 0)
62 efx_mcdi_set_mac(efx);
65 static const struct efx_farch_register_test siena_register_tests[] = {
67 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
69 EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) },
71 EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) },
73 EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) },
75 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
76 { FR_AZ_SRM_TX_DC_CFG,
77 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
79 EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) },
81 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
83 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
85 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
86 { FR_CZ_RX_RSS_IPV6_REG1,
87 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
88 { FR_CZ_RX_RSS_IPV6_REG2,
89 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
90 { FR_CZ_RX_RSS_IPV6_REG3,
91 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) },
94 static int siena_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
96 enum reset_type reset_method = RESET_TYPE_ALL;
99 efx_reset_down(efx, reset_method);
101 /* Reset the chip immediately so that it is completely
102 * quiescent regardless of what any VF driver does.
104 rc = efx_mcdi_reset(efx, reset_method);
109 efx_farch_test_registers(efx, siena_register_tests,
110 ARRAY_SIZE(siena_register_tests))
113 rc = efx_mcdi_reset(efx, reset_method);
115 rc2 = efx_reset_up(efx, reset_method, rc == 0);
116 return rc ? rc : rc2;
119 /**************************************************************************
123 **************************************************************************
126 static int siena_map_reset_flags(u32 *flags)
129 SIENA_RESET_PORT = (ETH_RESET_DMA | ETH_RESET_FILTER |
130 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
132 SIENA_RESET_MC = (SIENA_RESET_PORT |
133 ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT),
136 if ((*flags & SIENA_RESET_MC) == SIENA_RESET_MC) {
137 *flags &= ~SIENA_RESET_MC;
138 return RESET_TYPE_WORLD;
141 if ((*flags & SIENA_RESET_PORT) == SIENA_RESET_PORT) {
142 *flags &= ~SIENA_RESET_PORT;
143 return RESET_TYPE_ALL;
146 /* no invisible reset implemented */
152 /* When a PCI device is isolated from the bus, a subsequent MMIO read is
153 * required for the kernel EEH mechanisms to notice. As the Solarflare driver
154 * was written to minimise MMIO read (for latency) then a periodic call to check
155 * the EEH status of the device is required so that device recovery can happen
156 * in a timely fashion.
158 static void siena_monitor(struct efx_nic *efx)
160 struct eeh_dev *eehdev =
161 of_node_to_eeh_dev(pci_device_to_OF_node(efx->pci_dev));
163 eeh_dev_check_failure(eehdev);
167 static int siena_probe_nvconfig(struct efx_nic *efx)
172 rc = efx_mcdi_get_board_cfg(efx, efx->net_dev->perm_addr, NULL, &caps);
174 efx->timer_quantum_ns =
175 (caps & (1 << MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN)) ?
176 3072 : 6144; /* 768 cycles */
180 static int siena_dimension_resources(struct efx_nic *efx)
182 /* Each port has a small block of internal SRAM dedicated to
183 * the buffer table and descriptor caches. In theory we can
184 * map both blocks to one port, but we don't.
186 efx_farch_dimension_resources(efx, FR_CZ_BUF_FULL_TBL_ROWS / 2);
190 static unsigned int siena_mem_map_size(struct efx_nic *efx)
192 return FR_CZ_MC_TREG_SMEM +
193 FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS;
196 static int siena_probe_nic(struct efx_nic *efx)
198 struct siena_nic_data *nic_data;
199 bool already_attached = false;
203 /* Allocate storage for hardware specific data */
204 nic_data = kzalloc(sizeof(struct siena_nic_data), GFP_KERNEL);
207 efx->nic_data = nic_data;
209 if (efx_farch_fpga_ver(efx) != 0) {
210 netif_err(efx, probe, efx->net_dev,
211 "Siena FPGA not supported\n");
216 efx->max_channels = EFX_MAX_CHANNELS;
218 efx_reado(efx, ®, FR_AZ_CS_DEBUG);
219 efx->port_num = EFX_OWORD_FIELD(reg, FRF_CZ_CS_PORT_NUM) - 1;
221 rc = efx_mcdi_init(efx);
225 /* Let the BMC know that the driver is now in charge of link and
226 * filter settings. We must do this before we reset the NIC */
227 rc = efx_mcdi_drv_attach(efx, true, &already_attached);
229 netif_err(efx, probe, efx->net_dev,
230 "Unable to register driver with MCPU\n");
233 if (already_attached)
234 /* Not a fatal error */
235 netif_err(efx, probe, efx->net_dev,
236 "Host already registered with MCPU\n");
238 /* Now we can reset the NIC */
239 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
241 netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
247 /* Allocate memory for INT_KER */
248 rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t),
252 BUG_ON(efx->irq_status.dma_addr & 0x0f);
254 netif_dbg(efx, probe, efx->net_dev,
255 "INT_KER at %llx (virt %p phys %llx)\n",
256 (unsigned long long)efx->irq_status.dma_addr,
257 efx->irq_status.addr,
258 (unsigned long long)virt_to_phys(efx->irq_status.addr));
260 /* Read in the non-volatile configuration */
261 rc = siena_probe_nvconfig(efx);
263 netif_err(efx, probe, efx->net_dev,
264 "NVRAM is invalid therefore using defaults\n");
265 efx->phy_type = PHY_TYPE_NONE;
266 efx->mdio.prtad = MDIO_PRTAD_NONE;
271 rc = efx_mcdi_mon_probe(efx);
275 efx_sriov_probe(efx);
281 efx_nic_free_buffer(efx, &efx->irq_status);
284 efx_mcdi_drv_attach(efx, false, NULL);
288 kfree(efx->nic_data);
292 /* This call performs hardware-specific global initialisation, such as
293 * defining the descriptor cache sizes and number of RSS channels.
294 * It does not set up any buffers, descriptor rings or event queues.
296 static int siena_init_nic(struct efx_nic *efx)
301 /* Recover from a failed assertion post-reset */
302 rc = efx_mcdi_handle_assertion(efx);
306 /* Squash TX of packets of 16 bytes or less */
307 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
308 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
309 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
311 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
312 * descriptors (which is bad).
314 efx_reado(efx, &temp, FR_AZ_TX_CFG);
315 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
316 EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1);
317 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
319 efx_reado(efx, &temp, FR_AZ_RX_CFG);
320 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0);
321 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1);
322 /* Enable hash insertion. This is broken for the 'Falcon' hash
323 * if IPv6 hashing is also enabled, so also select Toeplitz
324 * TCP/IPv4 and IPv4 hashes. */
325 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_INSRT_HDR, 1);
326 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_ALG, 1);
327 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_IP_HASH, 1);
328 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_USR_BUF_SIZE,
329 EFX_RX_USR_BUF_SIZE >> 5);
330 efx_writeo(efx, &temp, FR_AZ_RX_CFG);
332 /* Set hash key for IPv4 */
333 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
334 efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
336 /* Enable IPv6 RSS */
337 BUILD_BUG_ON(sizeof(efx->rx_hash_key) <
338 2 * sizeof(temp) + FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8 ||
339 FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN != 0);
340 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
341 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1);
342 memcpy(&temp, efx->rx_hash_key + sizeof(temp), sizeof(temp));
343 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2);
344 EFX_POPULATE_OWORD_2(temp, FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1,
345 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, 1);
346 memcpy(&temp, efx->rx_hash_key + 2 * sizeof(temp),
347 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8);
348 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3);
350 /* Enable event logging */
351 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
355 /* Set destination of both TX and RX Flush events */
356 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
357 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
359 EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1);
360 efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG);
362 efx_farch_init_common(efx);
366 static void siena_remove_nic(struct efx_nic *efx)
368 efx_mcdi_mon_remove(efx);
370 efx_nic_free_buffer(efx, &efx->irq_status);
372 efx_mcdi_reset(efx, RESET_TYPE_ALL);
374 /* Relinquish the device back to the BMC */
375 efx_mcdi_drv_attach(efx, false, NULL);
377 /* Tear down the private nic state */
378 kfree(efx->nic_data);
379 efx->nic_data = NULL;
384 #define SIENA_DMA_STAT(ext_name, mcdi_name) \
385 [SIENA_STAT_ ## ext_name] = \
386 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
387 #define SIENA_OTHER_STAT(ext_name) \
388 [SIENA_STAT_ ## ext_name] = { #ext_name, 0, 0 }
390 static const struct efx_hw_stat_desc siena_stat_desc[SIENA_STAT_COUNT] = {
391 SIENA_DMA_STAT(tx_bytes, TX_BYTES),
392 SIENA_OTHER_STAT(tx_good_bytes),
393 SIENA_DMA_STAT(tx_bad_bytes, TX_BAD_BYTES),
394 SIENA_DMA_STAT(tx_packets, TX_PKTS),
395 SIENA_DMA_STAT(tx_bad, TX_BAD_FCS_PKTS),
396 SIENA_DMA_STAT(tx_pause, TX_PAUSE_PKTS),
397 SIENA_DMA_STAT(tx_control, TX_CONTROL_PKTS),
398 SIENA_DMA_STAT(tx_unicast, TX_UNICAST_PKTS),
399 SIENA_DMA_STAT(tx_multicast, TX_MULTICAST_PKTS),
400 SIENA_DMA_STAT(tx_broadcast, TX_BROADCAST_PKTS),
401 SIENA_DMA_STAT(tx_lt64, TX_LT64_PKTS),
402 SIENA_DMA_STAT(tx_64, TX_64_PKTS),
403 SIENA_DMA_STAT(tx_65_to_127, TX_65_TO_127_PKTS),
404 SIENA_DMA_STAT(tx_128_to_255, TX_128_TO_255_PKTS),
405 SIENA_DMA_STAT(tx_256_to_511, TX_256_TO_511_PKTS),
406 SIENA_DMA_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS),
407 SIENA_DMA_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
408 SIENA_DMA_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
409 SIENA_DMA_STAT(tx_gtjumbo, TX_GTJUMBO_PKTS),
410 SIENA_OTHER_STAT(tx_collision),
411 SIENA_DMA_STAT(tx_single_collision, TX_SINGLE_COLLISION_PKTS),
412 SIENA_DMA_STAT(tx_multiple_collision, TX_MULTIPLE_COLLISION_PKTS),
413 SIENA_DMA_STAT(tx_excessive_collision, TX_EXCESSIVE_COLLISION_PKTS),
414 SIENA_DMA_STAT(tx_deferred, TX_DEFERRED_PKTS),
415 SIENA_DMA_STAT(tx_late_collision, TX_LATE_COLLISION_PKTS),
416 SIENA_DMA_STAT(tx_excessive_deferred, TX_EXCESSIVE_DEFERRED_PKTS),
417 SIENA_DMA_STAT(tx_non_tcpudp, TX_NON_TCPUDP_PKTS),
418 SIENA_DMA_STAT(tx_mac_src_error, TX_MAC_SRC_ERR_PKTS),
419 SIENA_DMA_STAT(tx_ip_src_error, TX_IP_SRC_ERR_PKTS),
420 SIENA_DMA_STAT(rx_bytes, RX_BYTES),
421 SIENA_OTHER_STAT(rx_good_bytes),
422 SIENA_DMA_STAT(rx_bad_bytes, RX_BAD_BYTES),
423 SIENA_DMA_STAT(rx_packets, RX_PKTS),
424 SIENA_DMA_STAT(rx_good, RX_GOOD_PKTS),
425 SIENA_DMA_STAT(rx_bad, RX_BAD_FCS_PKTS),
426 SIENA_DMA_STAT(rx_pause, RX_PAUSE_PKTS),
427 SIENA_DMA_STAT(rx_control, RX_CONTROL_PKTS),
428 SIENA_DMA_STAT(rx_unicast, RX_UNICAST_PKTS),
429 SIENA_DMA_STAT(rx_multicast, RX_MULTICAST_PKTS),
430 SIENA_DMA_STAT(rx_broadcast, RX_BROADCAST_PKTS),
431 SIENA_DMA_STAT(rx_lt64, RX_UNDERSIZE_PKTS),
432 SIENA_DMA_STAT(rx_64, RX_64_PKTS),
433 SIENA_DMA_STAT(rx_65_to_127, RX_65_TO_127_PKTS),
434 SIENA_DMA_STAT(rx_128_to_255, RX_128_TO_255_PKTS),
435 SIENA_DMA_STAT(rx_256_to_511, RX_256_TO_511_PKTS),
436 SIENA_DMA_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS),
437 SIENA_DMA_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
438 SIENA_DMA_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
439 SIENA_DMA_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS),
440 SIENA_DMA_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS),
441 SIENA_DMA_STAT(rx_overflow, RX_OVERFLOW_PKTS),
442 SIENA_DMA_STAT(rx_false_carrier, RX_FALSE_CARRIER_PKTS),
443 SIENA_DMA_STAT(rx_symbol_error, RX_SYMBOL_ERROR_PKTS),
444 SIENA_DMA_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS),
445 SIENA_DMA_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS),
446 SIENA_DMA_STAT(rx_internal_error, RX_INTERNAL_ERROR_PKTS),
447 SIENA_DMA_STAT(rx_nodesc_drop_cnt, RX_NODESC_DROPS),
449 static const unsigned long siena_stat_mask[] = {
450 [0 ... BITS_TO_LONGS(SIENA_STAT_COUNT) - 1] = ~0UL,
453 static size_t siena_describe_nic_stats(struct efx_nic *efx, u8 *names)
455 return efx_nic_describe_stats(siena_stat_desc, SIENA_STAT_COUNT,
456 siena_stat_mask, names);
459 static int siena_try_update_nic_stats(struct efx_nic *efx)
461 struct siena_nic_data *nic_data = efx->nic_data;
462 u64 *stats = nic_data->stats;
464 __le64 generation_start, generation_end;
466 dma_stats = efx->stats_buffer.addr;
468 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
469 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
472 efx_nic_update_stats(siena_stat_desc, SIENA_STAT_COUNT, siena_stat_mask,
473 stats, efx->stats_buffer.addr, false);
475 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
476 if (generation_end != generation_start)
479 /* Update derived statistics */
480 efx_update_diff_stat(&stats[SIENA_STAT_tx_good_bytes],
481 stats[SIENA_STAT_tx_bytes] -
482 stats[SIENA_STAT_tx_bad_bytes]);
483 stats[SIENA_STAT_tx_collision] =
484 stats[SIENA_STAT_tx_single_collision] +
485 stats[SIENA_STAT_tx_multiple_collision] +
486 stats[SIENA_STAT_tx_excessive_collision] +
487 stats[SIENA_STAT_tx_late_collision];
488 efx_update_diff_stat(&stats[SIENA_STAT_rx_good_bytes],
489 stats[SIENA_STAT_rx_bytes] -
490 stats[SIENA_STAT_rx_bad_bytes]);
494 static size_t siena_update_nic_stats(struct efx_nic *efx, u64 *full_stats,
495 struct rtnl_link_stats64 *core_stats)
497 struct siena_nic_data *nic_data = efx->nic_data;
498 u64 *stats = nic_data->stats;
501 /* If we're unlucky enough to read statistics wduring the DMA, wait
502 * up to 10ms for it to finish (typically takes <500us) */
503 for (retry = 0; retry < 100; ++retry) {
504 if (siena_try_update_nic_stats(efx) == 0)
510 memcpy(full_stats, stats, sizeof(u64) * SIENA_STAT_COUNT);
513 core_stats->rx_packets = stats[SIENA_STAT_rx_packets];
514 core_stats->tx_packets = stats[SIENA_STAT_tx_packets];
515 core_stats->rx_bytes = stats[SIENA_STAT_rx_bytes];
516 core_stats->tx_bytes = stats[SIENA_STAT_tx_bytes];
517 core_stats->rx_dropped = stats[SIENA_STAT_rx_nodesc_drop_cnt];
518 core_stats->multicast = stats[SIENA_STAT_rx_multicast];
519 core_stats->collisions = stats[SIENA_STAT_tx_collision];
520 core_stats->rx_length_errors =
521 stats[SIENA_STAT_rx_gtjumbo] +
522 stats[SIENA_STAT_rx_length_error];
523 core_stats->rx_crc_errors = stats[SIENA_STAT_rx_bad];
524 core_stats->rx_frame_errors = stats[SIENA_STAT_rx_align_error];
525 core_stats->rx_fifo_errors = stats[SIENA_STAT_rx_overflow];
526 core_stats->tx_window_errors =
527 stats[SIENA_STAT_tx_late_collision];
529 core_stats->rx_errors = (core_stats->rx_length_errors +
530 core_stats->rx_crc_errors +
531 core_stats->rx_frame_errors +
532 stats[SIENA_STAT_rx_symbol_error]);
533 core_stats->tx_errors = (core_stats->tx_window_errors +
534 stats[SIENA_STAT_tx_bad]);
537 return SIENA_STAT_COUNT;
540 static int siena_mac_reconfigure(struct efx_nic *efx)
542 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_MCAST_HASH_IN_LEN);
545 BUILD_BUG_ON(MC_CMD_SET_MCAST_HASH_IN_LEN !=
546 MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST +
547 sizeof(efx->multicast_hash));
549 efx_farch_filter_sync_rx_mode(efx);
551 WARN_ON(!mutex_is_locked(&efx->mac_lock));
553 rc = efx_mcdi_set_mac(efx);
557 memcpy(MCDI_PTR(inbuf, SET_MCAST_HASH_IN_HASH0),
558 efx->multicast_hash.byte, sizeof(efx->multicast_hash));
559 return efx_mcdi_rpc(efx, MC_CMD_SET_MCAST_HASH,
560 inbuf, sizeof(inbuf), NULL, 0, NULL);
563 /**************************************************************************
567 **************************************************************************
570 static void siena_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
572 struct siena_nic_data *nic_data = efx->nic_data;
574 wol->supported = WAKE_MAGIC;
575 if (nic_data->wol_filter_id != -1)
576 wol->wolopts = WAKE_MAGIC;
579 memset(&wol->sopass, 0, sizeof(wol->sopass));
583 static int siena_set_wol(struct efx_nic *efx, u32 type)
585 struct siena_nic_data *nic_data = efx->nic_data;
588 if (type & ~WAKE_MAGIC)
591 if (type & WAKE_MAGIC) {
592 if (nic_data->wol_filter_id != -1)
593 efx_mcdi_wol_filter_remove(efx,
594 nic_data->wol_filter_id);
595 rc = efx_mcdi_wol_filter_set_magic(efx, efx->net_dev->dev_addr,
596 &nic_data->wol_filter_id);
600 pci_wake_from_d3(efx->pci_dev, true);
602 rc = efx_mcdi_wol_filter_reset(efx);
603 nic_data->wol_filter_id = -1;
604 pci_wake_from_d3(efx->pci_dev, false);
611 netif_err(efx, hw, efx->net_dev, "%s failed: type=%d rc=%d\n",
617 static void siena_init_wol(struct efx_nic *efx)
619 struct siena_nic_data *nic_data = efx->nic_data;
622 rc = efx_mcdi_wol_filter_get_magic(efx, &nic_data->wol_filter_id);
625 /* If it failed, attempt to get into a synchronised
626 * state with MC by resetting any set WoL filters */
627 efx_mcdi_wol_filter_reset(efx);
628 nic_data->wol_filter_id = -1;
629 } else if (nic_data->wol_filter_id != -1) {
630 pci_wake_from_d3(efx->pci_dev, true);
634 /**************************************************************************
638 **************************************************************************
641 #define MCDI_PDU(efx) \
642 (efx_port_num(efx) ? MC_SMEM_P1_PDU_OFST : MC_SMEM_P0_PDU_OFST)
643 #define MCDI_DOORBELL(efx) \
644 (efx_port_num(efx) ? MC_SMEM_P1_DOORBELL_OFST : MC_SMEM_P0_DOORBELL_OFST)
645 #define MCDI_STATUS(efx) \
646 (efx_port_num(efx) ? MC_SMEM_P1_STATUS_OFST : MC_SMEM_P0_STATUS_OFST)
648 static void siena_mcdi_request(struct efx_nic *efx,
649 const efx_dword_t *hdr, size_t hdr_len,
650 const efx_dword_t *sdu, size_t sdu_len)
652 unsigned pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
653 unsigned doorbell = FR_CZ_MC_TREG_SMEM + MCDI_DOORBELL(efx);
655 unsigned int inlen_dw = DIV_ROUND_UP(sdu_len, 4);
657 EFX_BUG_ON_PARANOID(hdr_len != 4);
659 efx_writed(efx, hdr, pdu);
661 for (i = 0; i < inlen_dw; i++)
662 efx_writed(efx, &sdu[i], pdu + hdr_len + 4 * i);
664 /* Ensure the request is written out before the doorbell */
667 /* ring the doorbell with a distinctive value */
668 _efx_writed(efx, (__force __le32) 0x45789abc, doorbell);
671 static bool siena_mcdi_poll_response(struct efx_nic *efx)
673 unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
676 efx_readd(efx, &hdr, pdu);
678 /* All 1's indicates that shared memory is in reset (and is
679 * not a valid hdr). Wait for it to come out reset before
680 * completing the command
682 return EFX_DWORD_FIELD(hdr, EFX_DWORD_0) != 0xffffffff &&
683 EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
686 static void siena_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
687 size_t offset, size_t outlen)
689 unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
690 unsigned int outlen_dw = DIV_ROUND_UP(outlen, 4);
693 for (i = 0; i < outlen_dw; i++)
694 efx_readd(efx, &outbuf[i], pdu + offset + 4 * i);
697 static int siena_mcdi_poll_reboot(struct efx_nic *efx)
699 struct siena_nic_data *nic_data = efx->nic_data;
700 unsigned int addr = FR_CZ_MC_TREG_SMEM + MCDI_STATUS(efx);
704 efx_readd(efx, ®, addr);
705 value = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
711 efx_writed(efx, ®, addr);
713 /* MAC statistics have been cleared on the NIC; clear the local
714 * copies that we update with efx_update_diff_stat().
716 nic_data->stats[SIENA_STAT_tx_good_bytes] = 0;
717 nic_data->stats[SIENA_STAT_rx_good_bytes] = 0;
719 if (value == MC_STATUS_DWORD_ASSERT)
725 /**************************************************************************
729 **************************************************************************
732 #ifdef CONFIG_SFC_MTD
734 struct siena_nvram_type_info {
739 static const struct siena_nvram_type_info siena_nvram_types[] = {
740 [MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO] = { 0, "sfc_dummy_phy" },
741 [MC_CMD_NVRAM_TYPE_MC_FW] = { 0, "sfc_mcfw" },
742 [MC_CMD_NVRAM_TYPE_MC_FW_BACKUP] = { 0, "sfc_mcfw_backup" },
743 [MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0] = { 0, "sfc_static_cfg" },
744 [MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1] = { 1, "sfc_static_cfg" },
745 [MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0] = { 0, "sfc_dynamic_cfg" },
746 [MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1] = { 1, "sfc_dynamic_cfg" },
747 [MC_CMD_NVRAM_TYPE_EXP_ROM] = { 0, "sfc_exp_rom" },
748 [MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0] = { 0, "sfc_exp_rom_cfg" },
749 [MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1] = { 1, "sfc_exp_rom_cfg" },
750 [MC_CMD_NVRAM_TYPE_PHY_PORT0] = { 0, "sfc_phy_fw" },
751 [MC_CMD_NVRAM_TYPE_PHY_PORT1] = { 1, "sfc_phy_fw" },
752 [MC_CMD_NVRAM_TYPE_FPGA] = { 0, "sfc_fpga" },
755 static int siena_mtd_probe_partition(struct efx_nic *efx,
756 struct efx_mcdi_mtd_partition *part,
759 const struct siena_nvram_type_info *info;
760 size_t size, erase_size;
764 if (type >= ARRAY_SIZE(siena_nvram_types) ||
765 siena_nvram_types[type].name == NULL)
768 info = &siena_nvram_types[type];
770 if (info->port != efx_port_num(efx))
773 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
777 return -ENODEV; /* hide it */
779 part->nvram_type = type;
780 part->common.dev_type_name = "Siena NVRAM manager";
781 part->common.type_name = info->name;
783 part->common.mtd.type = MTD_NORFLASH;
784 part->common.mtd.flags = MTD_CAP_NORFLASH;
785 part->common.mtd.size = size;
786 part->common.mtd.erasesize = erase_size;
791 static int siena_mtd_get_fw_subtypes(struct efx_nic *efx,
792 struct efx_mcdi_mtd_partition *parts,
795 uint16_t fw_subtype_list[
796 MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM];
800 rc = efx_mcdi_get_board_cfg(efx, NULL, fw_subtype_list, NULL);
804 for (i = 0; i < n_parts; i++)
805 parts[i].fw_subtype = fw_subtype_list[parts[i].nvram_type];
810 static int siena_mtd_probe(struct efx_nic *efx)
812 struct efx_mcdi_mtd_partition *parts;
820 rc = efx_mcdi_nvram_types(efx, &nvram_types);
824 parts = kcalloc(hweight32(nvram_types), sizeof(*parts), GFP_KERNEL);
831 while (nvram_types != 0) {
832 if (nvram_types & 1) {
833 rc = siena_mtd_probe_partition(efx, &parts[n_parts],
837 else if (rc != -ENODEV)
844 rc = siena_mtd_get_fw_subtypes(efx, parts, n_parts);
848 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
855 #endif /* CONFIG_SFC_MTD */
857 /**************************************************************************
861 **************************************************************************
864 static void siena_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
866 _efx_writed(efx, cpu_to_le32(host_time),
867 FR_CZ_MC_TREG_SMEM + MC_SMEM_P0_PTP_TIME_OFST);
870 /**************************************************************************
872 * Revision-dependent attributes used by efx.c and nic.c
874 **************************************************************************
877 const struct efx_nic_type siena_a0_nic_type = {
878 .mem_map_size = siena_mem_map_size,
879 .probe = siena_probe_nic,
880 .remove = siena_remove_nic,
881 .init = siena_init_nic,
882 .dimension_resources = siena_dimension_resources,
883 .fini = efx_port_dummy_op_void,
885 .monitor = siena_monitor,
889 .map_reset_reason = efx_mcdi_map_reset_reason,
890 .map_reset_flags = siena_map_reset_flags,
891 .reset = efx_mcdi_reset,
892 .probe_port = efx_mcdi_port_probe,
893 .remove_port = efx_mcdi_port_remove,
894 .fini_dmaq = efx_farch_fini_dmaq,
895 .prepare_flush = siena_prepare_flush,
896 .finish_flush = siena_finish_flush,
897 .describe_stats = siena_describe_nic_stats,
898 .update_stats = siena_update_nic_stats,
899 .start_stats = efx_mcdi_mac_start_stats,
900 .stop_stats = efx_mcdi_mac_stop_stats,
901 .set_id_led = efx_mcdi_set_id_led,
902 .push_irq_moderation = siena_push_irq_moderation,
903 .reconfigure_mac = siena_mac_reconfigure,
904 .check_mac_fault = efx_mcdi_mac_check_fault,
905 .reconfigure_port = efx_mcdi_port_reconfigure,
906 .get_wol = siena_get_wol,
907 .set_wol = siena_set_wol,
908 .resume_wol = siena_init_wol,
909 .test_chip = siena_test_chip,
910 .test_nvram = efx_mcdi_nvram_test_all,
911 .mcdi_request = siena_mcdi_request,
912 .mcdi_poll_response = siena_mcdi_poll_response,
913 .mcdi_read_response = siena_mcdi_read_response,
914 .mcdi_poll_reboot = siena_mcdi_poll_reboot,
915 .irq_enable_master = efx_farch_irq_enable_master,
916 .irq_test_generate = efx_farch_irq_test_generate,
917 .irq_disable_non_ev = efx_farch_irq_disable_master,
918 .irq_handle_msi = efx_farch_msi_interrupt,
919 .irq_handle_legacy = efx_farch_legacy_interrupt,
920 .tx_probe = efx_farch_tx_probe,
921 .tx_init = efx_farch_tx_init,
922 .tx_remove = efx_farch_tx_remove,
923 .tx_write = efx_farch_tx_write,
924 .rx_push_indir_table = efx_farch_rx_push_indir_table,
925 .rx_probe = efx_farch_rx_probe,
926 .rx_init = efx_farch_rx_init,
927 .rx_remove = efx_farch_rx_remove,
928 .rx_write = efx_farch_rx_write,
929 .rx_defer_refill = efx_farch_rx_defer_refill,
930 .ev_probe = efx_farch_ev_probe,
931 .ev_init = efx_farch_ev_init,
932 .ev_fini = efx_farch_ev_fini,
933 .ev_remove = efx_farch_ev_remove,
934 .ev_process = efx_farch_ev_process,
935 .ev_read_ack = efx_farch_ev_read_ack,
936 .ev_test_generate = efx_farch_ev_test_generate,
937 .filter_table_probe = efx_farch_filter_table_probe,
938 .filter_table_restore = efx_farch_filter_table_restore,
939 .filter_table_remove = efx_farch_filter_table_remove,
940 .filter_update_rx_scatter = efx_farch_filter_update_rx_scatter,
941 .filter_insert = efx_farch_filter_insert,
942 .filter_remove_safe = efx_farch_filter_remove_safe,
943 .filter_get_safe = efx_farch_filter_get_safe,
944 .filter_clear_rx = efx_farch_filter_clear_rx,
945 .filter_count_rx_used = efx_farch_filter_count_rx_used,
946 .filter_get_rx_id_limit = efx_farch_filter_get_rx_id_limit,
947 .filter_get_rx_ids = efx_farch_filter_get_rx_ids,
948 #ifdef CONFIG_RFS_ACCEL
949 .filter_rfs_insert = efx_farch_filter_rfs_insert,
950 .filter_rfs_expire_one = efx_farch_filter_rfs_expire_one,
952 #ifdef CONFIG_SFC_MTD
953 .mtd_probe = siena_mtd_probe,
954 .mtd_rename = efx_mcdi_mtd_rename,
955 .mtd_read = efx_mcdi_mtd_read,
956 .mtd_erase = efx_mcdi_mtd_erase,
957 .mtd_write = efx_mcdi_mtd_write,
958 .mtd_sync = efx_mcdi_mtd_sync,
960 .ptp_write_host_time = siena_ptp_write_host_time,
962 .revision = EFX_REV_SIENA_A0,
963 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
964 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
965 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
966 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
967 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
968 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
969 .rx_prefix_size = FS_BZ_RX_PREFIX_SIZE,
970 .rx_hash_offset = FS_BZ_RX_PREFIX_HASH_OFST,
971 .rx_buffer_padding = 0,
972 .can_rx_scatter = true,
973 .max_interrupt_mode = EFX_INT_MODE_MSIX,
974 .timer_period_max = 1 << FRF_CZ_TC_TIMER_VAL_WIDTH,
975 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
976 NETIF_F_RXHASH | NETIF_F_NTUPLE),
978 .max_rx_ip_filters = FR_BZ_RX_FILTER_TBL0_ROWS,