1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2010 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/slab.h>
16 #include <linux/random.h>
17 #include "net_driver.h"
22 #include "farch_regs.h"
25 #include "workarounds.h"
27 #include "mcdi_pcol.h"
30 /* Hardware control for SFC9000 family including SFL9021 (aka Siena). */
32 static void siena_init_wol(struct efx_nic *efx);
35 static void siena_push_irq_moderation(struct efx_channel *channel)
37 efx_dword_t timer_cmd;
39 if (channel->irq_moderation)
40 EFX_POPULATE_DWORD_2(timer_cmd,
42 FFE_CZ_TIMER_MODE_INT_HLDOFF,
44 channel->irq_moderation - 1);
46 EFX_POPULATE_DWORD_2(timer_cmd,
48 FFE_CZ_TIMER_MODE_DIS,
49 FRF_CZ_TC_TIMER_VAL, 0);
50 efx_writed_page_locked(channel->efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
54 void siena_prepare_flush(struct efx_nic *efx)
56 if (efx->fc_disable++ == 0)
57 efx_mcdi_set_mac(efx);
60 void siena_finish_flush(struct efx_nic *efx)
62 if (--efx->fc_disable == 0)
63 efx_mcdi_set_mac(efx);
66 static const struct efx_farch_register_test siena_register_tests[] = {
68 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
70 EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) },
72 EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) },
74 EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) },
76 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
77 { FR_AZ_SRM_TX_DC_CFG,
78 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
80 EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) },
82 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
84 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
86 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
87 { FR_CZ_RX_RSS_IPV6_REG1,
88 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
89 { FR_CZ_RX_RSS_IPV6_REG2,
90 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
91 { FR_CZ_RX_RSS_IPV6_REG3,
92 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) },
95 static int siena_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
97 enum reset_type reset_method = RESET_TYPE_ALL;
100 efx_reset_down(efx, reset_method);
102 /* Reset the chip immediately so that it is completely
103 * quiescent regardless of what any VF driver does.
105 rc = efx_mcdi_reset(efx, reset_method);
110 efx_farch_test_registers(efx, siena_register_tests,
111 ARRAY_SIZE(siena_register_tests))
114 rc = efx_mcdi_reset(efx, reset_method);
116 rc2 = efx_reset_up(efx, reset_method, rc == 0);
117 return rc ? rc : rc2;
120 /**************************************************************************
124 **************************************************************************
127 static int siena_map_reset_flags(u32 *flags)
130 SIENA_RESET_PORT = (ETH_RESET_DMA | ETH_RESET_FILTER |
131 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
133 SIENA_RESET_MC = (SIENA_RESET_PORT |
134 ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT),
137 if ((*flags & SIENA_RESET_MC) == SIENA_RESET_MC) {
138 *flags &= ~SIENA_RESET_MC;
139 return RESET_TYPE_WORLD;
142 if ((*flags & SIENA_RESET_PORT) == SIENA_RESET_PORT) {
143 *flags &= ~SIENA_RESET_PORT;
144 return RESET_TYPE_ALL;
147 /* no invisible reset implemented */
153 /* When a PCI device is isolated from the bus, a subsequent MMIO read is
154 * required for the kernel EEH mechanisms to notice. As the Solarflare driver
155 * was written to minimise MMIO read (for latency) then a periodic call to check
156 * the EEH status of the device is required so that device recovery can happen
157 * in a timely fashion.
159 static void siena_monitor(struct efx_nic *efx)
161 struct eeh_dev *eehdev =
162 of_node_to_eeh_dev(pci_device_to_OF_node(efx->pci_dev));
164 eeh_dev_check_failure(eehdev);
168 static int siena_probe_nvconfig(struct efx_nic *efx)
173 rc = efx_mcdi_get_board_cfg(efx, efx->net_dev->perm_addr, NULL, &caps);
175 efx->timer_quantum_ns =
176 (caps & (1 << MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN)) ?
177 3072 : 6144; /* 768 cycles */
181 static void siena_dimension_resources(struct efx_nic *efx)
183 /* Each port has a small block of internal SRAM dedicated to
184 * the buffer table and descriptor caches. In theory we can
185 * map both blocks to one port, but we don't.
187 efx_farch_dimension_resources(efx, FR_CZ_BUF_FULL_TBL_ROWS / 2);
190 static int siena_probe_nic(struct efx_nic *efx)
192 struct siena_nic_data *nic_data;
193 bool already_attached = false;
197 /* Allocate storage for hardware specific data */
198 nic_data = kzalloc(sizeof(struct siena_nic_data), GFP_KERNEL);
201 efx->nic_data = nic_data;
203 if (efx_farch_fpga_ver(efx) != 0) {
204 netif_err(efx, probe, efx->net_dev,
205 "Siena FPGA not supported\n");
210 efx_reado(efx, ®, FR_AZ_CS_DEBUG);
211 efx->port_num = EFX_OWORD_FIELD(reg, FRF_CZ_CS_PORT_NUM) - 1;
213 rc = efx_mcdi_init(efx);
217 /* Let the BMC know that the driver is now in charge of link and
218 * filter settings. We must do this before we reset the NIC */
219 rc = efx_mcdi_drv_attach(efx, true, &already_attached);
221 netif_err(efx, probe, efx->net_dev,
222 "Unable to register driver with MCPU\n");
225 if (already_attached)
226 /* Not a fatal error */
227 netif_err(efx, probe, efx->net_dev,
228 "Host already registered with MCPU\n");
230 /* Now we can reset the NIC */
231 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
233 netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
239 /* Allocate memory for INT_KER */
240 rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t),
244 BUG_ON(efx->irq_status.dma_addr & 0x0f);
246 netif_dbg(efx, probe, efx->net_dev,
247 "INT_KER at %llx (virt %p phys %llx)\n",
248 (unsigned long long)efx->irq_status.dma_addr,
249 efx->irq_status.addr,
250 (unsigned long long)virt_to_phys(efx->irq_status.addr));
252 /* Read in the non-volatile configuration */
253 rc = siena_probe_nvconfig(efx);
255 netif_err(efx, probe, efx->net_dev,
256 "NVRAM is invalid therefore using defaults\n");
257 efx->phy_type = PHY_TYPE_NONE;
258 efx->mdio.prtad = MDIO_PRTAD_NONE;
263 rc = efx_mcdi_mon_probe(efx);
267 efx_sriov_probe(efx);
273 efx_nic_free_buffer(efx, &efx->irq_status);
276 efx_mcdi_drv_attach(efx, false, NULL);
280 kfree(efx->nic_data);
284 /* This call performs hardware-specific global initialisation, such as
285 * defining the descriptor cache sizes and number of RSS channels.
286 * It does not set up any buffers, descriptor rings or event queues.
288 static int siena_init_nic(struct efx_nic *efx)
293 /* Recover from a failed assertion post-reset */
294 rc = efx_mcdi_handle_assertion(efx);
298 /* Squash TX of packets of 16 bytes or less */
299 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
300 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
301 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
303 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
304 * descriptors (which is bad).
306 efx_reado(efx, &temp, FR_AZ_TX_CFG);
307 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
308 EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1);
309 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
311 efx_reado(efx, &temp, FR_AZ_RX_CFG);
312 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0);
313 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1);
314 /* Enable hash insertion. This is broken for the 'Falcon' hash
315 * if IPv6 hashing is also enabled, so also select Toeplitz
316 * TCP/IPv4 and IPv4 hashes. */
317 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_INSRT_HDR, 1);
318 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_ALG, 1);
319 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_IP_HASH, 1);
320 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_USR_BUF_SIZE,
321 EFX_RX_USR_BUF_SIZE >> 5);
322 efx_writeo(efx, &temp, FR_AZ_RX_CFG);
324 /* Set hash key for IPv4 */
325 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
326 efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
328 /* Enable IPv6 RSS */
329 BUILD_BUG_ON(sizeof(efx->rx_hash_key) <
330 2 * sizeof(temp) + FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8 ||
331 FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN != 0);
332 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
333 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1);
334 memcpy(&temp, efx->rx_hash_key + sizeof(temp), sizeof(temp));
335 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2);
336 EFX_POPULATE_OWORD_2(temp, FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1,
337 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, 1);
338 memcpy(&temp, efx->rx_hash_key + 2 * sizeof(temp),
339 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8);
340 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3);
342 /* Enable event logging */
343 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
347 /* Set destination of both TX and RX Flush events */
348 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
349 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
351 EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1);
352 efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG);
354 efx_farch_init_common(efx);
358 static void siena_remove_nic(struct efx_nic *efx)
360 efx_mcdi_mon_remove(efx);
362 efx_nic_free_buffer(efx, &efx->irq_status);
364 efx_mcdi_reset(efx, RESET_TYPE_ALL);
366 /* Relinquish the device back to the BMC */
367 efx_mcdi_drv_attach(efx, false, NULL);
369 /* Tear down the private nic state */
370 kfree(efx->nic_data);
371 efx->nic_data = NULL;
376 static int siena_try_update_nic_stats(struct efx_nic *efx)
379 struct efx_mac_stats *mac_stats;
380 __le64 generation_start, generation_end;
382 mac_stats = &efx->mac_stats;
383 dma_stats = efx->stats_buffer.addr;
385 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
386 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
390 #define MAC_STAT(M, D) \
391 mac_stats->M = le64_to_cpu(dma_stats[MC_CMD_MAC_ ## D])
393 MAC_STAT(tx_bytes, TX_BYTES);
394 MAC_STAT(tx_bad_bytes, TX_BAD_BYTES);
395 efx_update_diff_stat(&mac_stats->tx_good_bytes,
396 mac_stats->tx_bytes - mac_stats->tx_bad_bytes);
397 MAC_STAT(tx_packets, TX_PKTS);
398 MAC_STAT(tx_bad, TX_BAD_FCS_PKTS);
399 MAC_STAT(tx_pause, TX_PAUSE_PKTS);
400 MAC_STAT(tx_control, TX_CONTROL_PKTS);
401 MAC_STAT(tx_unicast, TX_UNICAST_PKTS);
402 MAC_STAT(tx_multicast, TX_MULTICAST_PKTS);
403 MAC_STAT(tx_broadcast, TX_BROADCAST_PKTS);
404 MAC_STAT(tx_lt64, TX_LT64_PKTS);
405 MAC_STAT(tx_64, TX_64_PKTS);
406 MAC_STAT(tx_65_to_127, TX_65_TO_127_PKTS);
407 MAC_STAT(tx_128_to_255, TX_128_TO_255_PKTS);
408 MAC_STAT(tx_256_to_511, TX_256_TO_511_PKTS);
409 MAC_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS);
410 MAC_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS);
411 MAC_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS);
412 MAC_STAT(tx_gtjumbo, TX_GTJUMBO_PKTS);
413 mac_stats->tx_collision = 0;
414 MAC_STAT(tx_single_collision, TX_SINGLE_COLLISION_PKTS);
415 MAC_STAT(tx_multiple_collision, TX_MULTIPLE_COLLISION_PKTS);
416 MAC_STAT(tx_excessive_collision, TX_EXCESSIVE_COLLISION_PKTS);
417 MAC_STAT(tx_deferred, TX_DEFERRED_PKTS);
418 MAC_STAT(tx_late_collision, TX_LATE_COLLISION_PKTS);
419 mac_stats->tx_collision = (mac_stats->tx_single_collision +
420 mac_stats->tx_multiple_collision +
421 mac_stats->tx_excessive_collision +
422 mac_stats->tx_late_collision);
423 MAC_STAT(tx_excessive_deferred, TX_EXCESSIVE_DEFERRED_PKTS);
424 MAC_STAT(tx_non_tcpudp, TX_NON_TCPUDP_PKTS);
425 MAC_STAT(tx_mac_src_error, TX_MAC_SRC_ERR_PKTS);
426 MAC_STAT(tx_ip_src_error, TX_IP_SRC_ERR_PKTS);
427 MAC_STAT(rx_bytes, RX_BYTES);
428 MAC_STAT(rx_bad_bytes, RX_BAD_BYTES);
429 efx_update_diff_stat(&mac_stats->rx_good_bytes,
430 mac_stats->rx_bytes - mac_stats->rx_bad_bytes);
431 MAC_STAT(rx_packets, RX_PKTS);
432 MAC_STAT(rx_good, RX_GOOD_PKTS);
433 MAC_STAT(rx_bad, RX_BAD_FCS_PKTS);
434 MAC_STAT(rx_pause, RX_PAUSE_PKTS);
435 MAC_STAT(rx_control, RX_CONTROL_PKTS);
436 MAC_STAT(rx_unicast, RX_UNICAST_PKTS);
437 MAC_STAT(rx_multicast, RX_MULTICAST_PKTS);
438 MAC_STAT(rx_broadcast, RX_BROADCAST_PKTS);
439 MAC_STAT(rx_lt64, RX_UNDERSIZE_PKTS);
440 MAC_STAT(rx_64, RX_64_PKTS);
441 MAC_STAT(rx_65_to_127, RX_65_TO_127_PKTS);
442 MAC_STAT(rx_128_to_255, RX_128_TO_255_PKTS);
443 MAC_STAT(rx_256_to_511, RX_256_TO_511_PKTS);
444 MAC_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS);
445 MAC_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS);
446 MAC_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS);
447 MAC_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS);
448 mac_stats->rx_bad_lt64 = 0;
449 mac_stats->rx_bad_64_to_15xx = 0;
450 mac_stats->rx_bad_15xx_to_jumbo = 0;
451 MAC_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS);
452 MAC_STAT(rx_overflow, RX_OVERFLOW_PKTS);
453 mac_stats->rx_missed = 0;
454 MAC_STAT(rx_false_carrier, RX_FALSE_CARRIER_PKTS);
455 MAC_STAT(rx_symbol_error, RX_SYMBOL_ERROR_PKTS);
456 MAC_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS);
457 MAC_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS);
458 MAC_STAT(rx_internal_error, RX_INTERNAL_ERROR_PKTS);
459 mac_stats->rx_good_lt64 = 0;
461 efx->n_rx_nodesc_drop_cnt =
462 le64_to_cpu(dma_stats[MC_CMD_MAC_RX_NODESC_DROPS]);
467 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
468 if (generation_end != generation_start)
474 static void siena_update_nic_stats(struct efx_nic *efx)
478 /* If we're unlucky enough to read statistics wduring the DMA, wait
479 * up to 10ms for it to finish (typically takes <500us) */
480 for (retry = 0; retry < 100; ++retry) {
481 if (siena_try_update_nic_stats(efx) == 0)
486 /* Use the old values instead */
489 static int siena_mac_reconfigure(struct efx_nic *efx)
491 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_MCAST_HASH_IN_LEN);
494 BUILD_BUG_ON(MC_CMD_SET_MCAST_HASH_IN_LEN !=
495 MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST +
496 sizeof(efx->multicast_hash));
498 WARN_ON(!mutex_is_locked(&efx->mac_lock));
500 rc = efx_mcdi_set_mac(efx);
504 memcpy(MCDI_PTR(inbuf, SET_MCAST_HASH_IN_HASH0),
505 efx->multicast_hash.byte, sizeof(efx->multicast_hash));
506 return efx_mcdi_rpc(efx, MC_CMD_SET_MCAST_HASH,
507 inbuf, sizeof(inbuf), NULL, 0, NULL);
510 /**************************************************************************
514 **************************************************************************
517 static void siena_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
519 struct siena_nic_data *nic_data = efx->nic_data;
521 wol->supported = WAKE_MAGIC;
522 if (nic_data->wol_filter_id != -1)
523 wol->wolopts = WAKE_MAGIC;
526 memset(&wol->sopass, 0, sizeof(wol->sopass));
530 static int siena_set_wol(struct efx_nic *efx, u32 type)
532 struct siena_nic_data *nic_data = efx->nic_data;
535 if (type & ~WAKE_MAGIC)
538 if (type & WAKE_MAGIC) {
539 if (nic_data->wol_filter_id != -1)
540 efx_mcdi_wol_filter_remove(efx,
541 nic_data->wol_filter_id);
542 rc = efx_mcdi_wol_filter_set_magic(efx, efx->net_dev->dev_addr,
543 &nic_data->wol_filter_id);
547 pci_wake_from_d3(efx->pci_dev, true);
549 rc = efx_mcdi_wol_filter_reset(efx);
550 nic_data->wol_filter_id = -1;
551 pci_wake_from_d3(efx->pci_dev, false);
558 netif_err(efx, hw, efx->net_dev, "%s failed: type=%d rc=%d\n",
564 static void siena_init_wol(struct efx_nic *efx)
566 struct siena_nic_data *nic_data = efx->nic_data;
569 rc = efx_mcdi_wol_filter_get_magic(efx, &nic_data->wol_filter_id);
572 /* If it failed, attempt to get into a synchronised
573 * state with MC by resetting any set WoL filters */
574 efx_mcdi_wol_filter_reset(efx);
575 nic_data->wol_filter_id = -1;
576 } else if (nic_data->wol_filter_id != -1) {
577 pci_wake_from_d3(efx->pci_dev, true);
581 /**************************************************************************
585 **************************************************************************
588 #define MCDI_PDU(efx) \
589 (efx_port_num(efx) ? MC_SMEM_P1_PDU_OFST : MC_SMEM_P0_PDU_OFST)
590 #define MCDI_DOORBELL(efx) \
591 (efx_port_num(efx) ? MC_SMEM_P1_DOORBELL_OFST : MC_SMEM_P0_DOORBELL_OFST)
592 #define MCDI_STATUS(efx) \
593 (efx_port_num(efx) ? MC_SMEM_P1_STATUS_OFST : MC_SMEM_P0_STATUS_OFST)
595 static void siena_mcdi_request(struct efx_nic *efx,
596 const efx_dword_t *hdr, size_t hdr_len,
597 const efx_dword_t *sdu, size_t sdu_len)
599 unsigned pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
600 unsigned doorbell = FR_CZ_MC_TREG_SMEM + MCDI_DOORBELL(efx);
602 unsigned int inlen_dw = DIV_ROUND_UP(sdu_len, 4);
604 EFX_BUG_ON_PARANOID(hdr_len != 4);
606 efx_writed(efx, hdr, pdu);
608 for (i = 0; i < inlen_dw; i++)
609 efx_writed(efx, &sdu[i], pdu + hdr_len + 4 * i);
611 /* Ensure the request is written out before the doorbell */
614 /* ring the doorbell with a distinctive value */
615 _efx_writed(efx, (__force __le32) 0x45789abc, doorbell);
618 static bool siena_mcdi_poll_response(struct efx_nic *efx)
620 unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
623 efx_readd(efx, &hdr, pdu);
625 /* All 1's indicates that shared memory is in reset (and is
626 * not a valid hdr). Wait for it to come out reset before
627 * completing the command
629 return EFX_DWORD_FIELD(hdr, EFX_DWORD_0) != 0xffffffff &&
630 EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
633 static void siena_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
634 size_t offset, size_t outlen)
636 unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
637 unsigned int outlen_dw = DIV_ROUND_UP(outlen, 4);
640 for (i = 0; i < outlen_dw; i++)
641 efx_readd(efx, &outbuf[i], pdu + offset + 4 * i);
644 static int siena_mcdi_poll_reboot(struct efx_nic *efx)
646 unsigned int addr = FR_CZ_MC_TREG_SMEM + MCDI_STATUS(efx);
650 efx_readd(efx, ®, addr);
651 value = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
657 efx_writed(efx, ®, addr);
659 if (value == MC_STATUS_DWORD_ASSERT)
665 /**************************************************************************
667 * Revision-dependent attributes used by efx.c and nic.c
669 **************************************************************************
672 const struct efx_nic_type siena_a0_nic_type = {
673 .probe = siena_probe_nic,
674 .remove = siena_remove_nic,
675 .init = siena_init_nic,
676 .dimension_resources = siena_dimension_resources,
677 .fini = efx_port_dummy_op_void,
679 .monitor = siena_monitor,
683 .map_reset_reason = efx_mcdi_map_reset_reason,
684 .map_reset_flags = siena_map_reset_flags,
685 .reset = efx_mcdi_reset,
686 .probe_port = efx_mcdi_port_probe,
687 .remove_port = efx_mcdi_port_remove,
688 .fini_dmaq = efx_farch_fini_dmaq,
689 .prepare_flush = siena_prepare_flush,
690 .finish_flush = siena_finish_flush,
691 .update_stats = siena_update_nic_stats,
692 .start_stats = efx_mcdi_mac_start_stats,
693 .stop_stats = efx_mcdi_mac_stop_stats,
694 .set_id_led = efx_mcdi_set_id_led,
695 .push_irq_moderation = siena_push_irq_moderation,
696 .reconfigure_mac = siena_mac_reconfigure,
697 .check_mac_fault = efx_mcdi_mac_check_fault,
698 .reconfigure_port = efx_mcdi_port_reconfigure,
699 .get_wol = siena_get_wol,
700 .set_wol = siena_set_wol,
701 .resume_wol = siena_init_wol,
702 .test_chip = siena_test_chip,
703 .test_nvram = efx_mcdi_nvram_test_all,
704 .mcdi_request = siena_mcdi_request,
705 .mcdi_poll_response = siena_mcdi_poll_response,
706 .mcdi_read_response = siena_mcdi_read_response,
707 .mcdi_poll_reboot = siena_mcdi_poll_reboot,
708 .irq_enable_master = efx_farch_irq_enable_master,
709 .irq_test_generate = efx_farch_irq_test_generate,
710 .irq_disable_non_ev = efx_farch_irq_disable_master,
711 .irq_handle_msi = efx_farch_msi_interrupt,
712 .irq_handle_legacy = efx_farch_legacy_interrupt,
713 .tx_probe = efx_farch_tx_probe,
714 .tx_init = efx_farch_tx_init,
715 .tx_remove = efx_farch_tx_remove,
716 .tx_write = efx_farch_tx_write,
717 .rx_push_indir_table = efx_farch_rx_push_indir_table,
718 .rx_probe = efx_farch_rx_probe,
719 .rx_init = efx_farch_rx_init,
720 .rx_remove = efx_farch_rx_remove,
721 .rx_write = efx_farch_rx_write,
722 .rx_defer_refill = efx_farch_rx_defer_refill,
723 .ev_probe = efx_farch_ev_probe,
724 .ev_init = efx_farch_ev_init,
725 .ev_fini = efx_farch_ev_fini,
726 .ev_remove = efx_farch_ev_remove,
727 .ev_process = efx_farch_ev_process,
728 .ev_read_ack = efx_farch_ev_read_ack,
729 .ev_test_generate = efx_farch_ev_test_generate,
731 .revision = EFX_REV_SIENA_A0,
732 .mem_map_size = (FR_CZ_MC_TREG_SMEM +
733 FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS),
734 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
735 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
736 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
737 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
738 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
739 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
740 .rx_buffer_hash_size = 0x10,
741 .rx_buffer_padding = 0,
742 .can_rx_scatter = true,
743 .max_interrupt_mode = EFX_INT_MODE_MSIX,
744 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
745 * interrupt handler only supports 32
747 .timer_period_max = 1 << FRF_CZ_TC_TIMER_VAL_WIDTH,
748 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
749 NETIF_F_RXHASH | NETIF_F_NTUPLE),