1 /*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
5 Copyright(C) 2007-2011 STMicroelectronics Ltd
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
25 Documentation available at:
26 http://www.stlinux.com
28 https://bugzilla.stlinux.com/
29 *******************************************************************************/
31 #include <linux/kernel.h>
32 #include <linux/interrupt.h>
34 #include <linux/tcp.h>
35 #include <linux/skbuff.h>
36 #include <linux/ethtool.h>
37 #include <linux/if_ether.h>
38 #include <linux/crc32.h>
39 #include <linux/mii.h>
41 #include <linux/if_vlan.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/slab.h>
44 #include <linux/prefetch.h>
45 #ifdef CONFIG_STMMAC_DEBUG_FS
46 #include <linux/debugfs.h>
47 #include <linux/seq_file.h>
52 /*#define STMMAC_DEBUG*/
54 #define DBG(nlevel, klevel, fmt, args...) \
55 ((void)(netif_msg_##nlevel(priv) && \
56 printk(KERN_##klevel fmt, ## args)))
58 #define DBG(nlevel, klevel, fmt, args...) do { } while (0)
61 #undef STMMAC_RX_DEBUG
62 /*#define STMMAC_RX_DEBUG*/
63 #ifdef STMMAC_RX_DEBUG
64 #define RX_DBG(fmt, args...) printk(fmt, ## args)
66 #define RX_DBG(fmt, args...) do { } while (0)
69 #undef STMMAC_XMIT_DEBUG
70 /*#define STMMAC_XMIT_DEBUG*/
71 #ifdef STMMAC_TX_DEBUG
72 #define TX_DBG(fmt, args...) printk(fmt, ## args)
74 #define TX_DBG(fmt, args...) do { } while (0)
77 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
78 #define JUMBO_LEN 9000
80 /* Module parameters */
81 #define TX_TIMEO 5000 /* default 5 seconds */
82 static int watchdog = TX_TIMEO;
83 module_param(watchdog, int, S_IRUGO | S_IWUSR);
84 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds");
86 static int debug = -1; /* -1: default, 0: no output, 16: all */
87 module_param(debug, int, S_IRUGO | S_IWUSR);
88 MODULE_PARM_DESC(debug, "Message Level (0: no output, 16: all)");
91 module_param(phyaddr, int, S_IRUGO);
92 MODULE_PARM_DESC(phyaddr, "Physical device address");
94 #define DMA_TX_SIZE 256
95 static int dma_txsize = DMA_TX_SIZE;
96 module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
97 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
99 #define DMA_RX_SIZE 256
100 static int dma_rxsize = DMA_RX_SIZE;
101 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
102 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
104 static int flow_ctrl = FLOW_OFF;
105 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
106 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
108 static int pause = PAUSE_TIME;
109 module_param(pause, int, S_IRUGO | S_IWUSR);
110 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
112 #define TC_DEFAULT 64
113 static int tc = TC_DEFAULT;
114 module_param(tc, int, S_IRUGO | S_IWUSR);
115 MODULE_PARM_DESC(tc, "DMA threshold control value");
117 /* Pay attention to tune this parameter; take care of both
118 * hardware capability and network stabitily/performance impact.
119 * Many tests showed that ~4ms latency seems to be good enough. */
120 #ifdef CONFIG_STMMAC_TIMER
121 #define DEFAULT_PERIODIC_RATE 256
122 static int tmrate = DEFAULT_PERIODIC_RATE;
123 module_param(tmrate, int, S_IRUGO | S_IWUSR);
124 MODULE_PARM_DESC(tmrate, "External timer freq. (default: 256Hz)");
127 #define DMA_BUFFER_SIZE BUF_SIZE_2KiB
128 static int buf_sz = DMA_BUFFER_SIZE;
129 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
130 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
132 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
133 NETIF_MSG_LINK | NETIF_MSG_IFUP |
134 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
136 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
138 #ifdef CONFIG_STMMAC_DEBUG_FS
139 static int stmmac_init_fs(struct net_device *dev);
140 static void stmmac_exit_fs(void);
144 * stmmac_verify_args - verify the driver parameters.
145 * Description: it verifies if some wrong parameter is passed to the driver.
146 * Note that wrong parameters are replaced with the default values.
148 static void stmmac_verify_args(void)
150 if (unlikely(watchdog < 0))
152 if (unlikely(dma_rxsize < 0))
153 dma_rxsize = DMA_RX_SIZE;
154 if (unlikely(dma_txsize < 0))
155 dma_txsize = DMA_TX_SIZE;
156 if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB)))
157 buf_sz = DMA_BUFFER_SIZE;
158 if (unlikely(flow_ctrl > 1))
159 flow_ctrl = FLOW_AUTO;
160 else if (likely(flow_ctrl < 0))
161 flow_ctrl = FLOW_OFF;
162 if (unlikely((pause < 0) || (pause > 0xffff)))
166 #if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG)
167 static void print_pkt(unsigned char *buf, int len)
170 pr_info("len = %d byte, buf addr: 0x%p", len, buf);
171 for (j = 0; j < len; j++) {
173 pr_info("\n %03x:", j);
174 pr_info(" %02x", buf[j]);
180 /* minimum number of free TX descriptors required to wake up TX process */
181 #define STMMAC_TX_THRESH(x) (x->dma_tx_size/4)
183 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
185 return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
188 /* On some ST platforms, some HW system configuraton registers have to be
189 * set according to the link speed negotiated.
191 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
193 struct phy_device *phydev = priv->phydev;
195 if (likely(priv->plat->fix_mac_speed))
196 priv->plat->fix_mac_speed(priv->plat->bsp_priv,
202 * @dev: net device structure
203 * Description: it adjusts the link parameters.
205 static void stmmac_adjust_link(struct net_device *dev)
207 struct stmmac_priv *priv = netdev_priv(dev);
208 struct phy_device *phydev = priv->phydev;
211 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
216 DBG(probe, DEBUG, "stmmac_adjust_link: called. address %d link %d\n",
217 phydev->addr, phydev->link);
219 spin_lock_irqsave(&priv->lock, flags);
221 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
223 /* Now we make sure that we can be in full duplex mode.
224 * If not, we operate in half-duplex mode. */
225 if (phydev->duplex != priv->oldduplex) {
227 if (!(phydev->duplex))
228 ctrl &= ~priv->hw->link.duplex;
230 ctrl |= priv->hw->link.duplex;
231 priv->oldduplex = phydev->duplex;
233 /* Flow Control operation */
235 priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex,
238 if (phydev->speed != priv->speed) {
240 switch (phydev->speed) {
242 if (likely(priv->plat->has_gmac))
243 ctrl &= ~priv->hw->link.port;
244 stmmac_hw_fix_mac_speed(priv);
248 if (priv->plat->has_gmac) {
249 ctrl |= priv->hw->link.port;
250 if (phydev->speed == SPEED_100) {
251 ctrl |= priv->hw->link.speed;
253 ctrl &= ~(priv->hw->link.speed);
256 ctrl &= ~priv->hw->link.port;
258 stmmac_hw_fix_mac_speed(priv);
261 if (netif_msg_link(priv))
262 pr_warning("%s: Speed (%d) is not 10"
263 " or 100!\n", dev->name, phydev->speed);
267 priv->speed = phydev->speed;
270 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
272 if (!priv->oldlink) {
276 } else if (priv->oldlink) {
280 priv->oldduplex = -1;
283 if (new_state && netif_msg_link(priv))
284 phy_print_status(phydev);
286 spin_unlock_irqrestore(&priv->lock, flags);
288 DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n");
292 * stmmac_init_phy - PHY initialization
293 * @dev: net device structure
294 * Description: it initializes the driver's PHY state, and attaches the PHY
299 static int stmmac_init_phy(struct net_device *dev)
301 struct stmmac_priv *priv = netdev_priv(dev);
302 struct phy_device *phydev;
303 char phy_id[MII_BUS_ID_SIZE + 3];
304 char bus_id[MII_BUS_ID_SIZE];
305 int interface = priv->plat->interface;
308 priv->oldduplex = -1;
310 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x", priv->plat->bus_id);
311 snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
312 priv->plat->phy_addr);
313 pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id);
315 phydev = phy_connect(dev, phy_id, &stmmac_adjust_link, 0, interface);
317 if (IS_ERR(phydev)) {
318 pr_err("%s: Could not attach to PHY\n", dev->name);
319 return PTR_ERR(phydev);
322 /* Stop Advertising 1000BASE Capability if interface is not GMII */
323 if ((interface == PHY_INTERFACE_MODE_MII) ||
324 (interface == PHY_INTERFACE_MODE_RMII))
325 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
326 SUPPORTED_1000baseT_Full);
329 * Broken HW is sometimes missing the pull-up resistor on the
330 * MDIO line, which results in reads to non-existent devices returning
331 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
333 * Note: phydev->phy_id is the result of reading the UID PHY registers.
335 if (phydev->phy_id == 0) {
336 phy_disconnect(phydev);
339 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)"
340 " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
342 priv->phydev = phydev;
349 * @p: pointer to the ring.
350 * @size: size of the ring.
351 * Description: display all the descriptors within the ring.
353 static void display_ring(struct dma_desc *p, int size)
361 for (i = 0; i < size; i++) {
362 struct tmp_s *x = (struct tmp_s *)(p + i);
363 pr_info("\t%d [0x%x]: DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
364 i, (unsigned int)virt_to_phys(&p[i]),
365 (unsigned int)(x->a), (unsigned int)((x->a) >> 32),
371 static int stmmac_set_bfsize(int mtu, int bufsize)
375 if (mtu >= BUF_SIZE_4KiB)
377 else if (mtu >= BUF_SIZE_2KiB)
379 else if (mtu >= DMA_BUFFER_SIZE)
382 ret = DMA_BUFFER_SIZE;
388 * init_dma_desc_rings - init the RX/TX descriptor rings
389 * @dev: net device structure
390 * Description: this function initializes the DMA RX/TX descriptors
391 * and allocates the socket buffers. It suppors the chained and ring
394 static void init_dma_desc_rings(struct net_device *dev)
397 struct stmmac_priv *priv = netdev_priv(dev);
399 unsigned int txsize = priv->dma_tx_size;
400 unsigned int rxsize = priv->dma_rx_size;
403 int des3_as_data_buf = 0;
405 /* Set the max buffer size according to the DESC mode
406 * and the MTU. Note that RING mode allows 16KiB bsize. */
407 bfsize = priv->hw->ring->set_16kib_bfsize(dev->mtu);
409 if (bfsize == BUF_SIZE_16KiB)
410 des3_as_data_buf = 1;
412 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
414 #ifdef CONFIG_STMMAC_TIMER
415 /* Disable interrupts on completion for the reception if timer is on */
416 if (likely(priv->tm->enable))
420 DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n",
421 txsize, rxsize, bfsize);
423 priv->rx_skbuff_dma = kmalloc(rxsize * sizeof(dma_addr_t), GFP_KERNEL);
425 kmalloc(sizeof(struct sk_buff *) * rxsize, GFP_KERNEL);
427 (struct dma_desc *)dma_alloc_coherent(priv->device,
429 sizeof(struct dma_desc),
432 priv->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * txsize,
435 (struct dma_desc *)dma_alloc_coherent(priv->device,
437 sizeof(struct dma_desc),
441 if ((priv->dma_rx == NULL) || (priv->dma_tx == NULL)) {
442 pr_err("%s:ERROR allocating the DMA Tx/Rx desc\n", __func__);
446 DBG(probe, INFO, "stmmac (%s) DMA desc: virt addr (Rx %p, "
447 "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n",
448 dev->name, priv->dma_rx, priv->dma_tx,
449 (unsigned int)priv->dma_rx_phy, (unsigned int)priv->dma_tx_phy);
451 /* RX INITIALIZATION */
452 DBG(probe, INFO, "stmmac: SKB addresses:\n"
453 "skb\t\tskb data\tdma data\n");
455 for (i = 0; i < rxsize; i++) {
456 struct dma_desc *p = priv->dma_rx + i;
458 skb = __netdev_alloc_skb(dev, bfsize + NET_IP_ALIGN,
460 if (unlikely(skb == NULL)) {
461 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
464 skb_reserve(skb, NET_IP_ALIGN);
465 priv->rx_skbuff[i] = skb;
466 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
467 bfsize, DMA_FROM_DEVICE);
469 p->des2 = priv->rx_skbuff_dma[i];
471 priv->hw->ring->init_desc3(des3_as_data_buf, p);
473 DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
474 priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]);
477 priv->dirty_rx = (unsigned int)(i - rxsize);
478 priv->dma_buf_sz = bfsize;
481 /* TX INITIALIZATION */
482 for (i = 0; i < txsize; i++) {
483 priv->tx_skbuff[i] = NULL;
484 priv->dma_tx[i].des2 = 0;
487 /* In case of Chained mode this sets the des3 to the next
488 * element in the chain */
489 priv->hw->ring->init_dma_chain(priv->dma_rx, priv->dma_rx_phy, rxsize);
490 priv->hw->ring->init_dma_chain(priv->dma_tx, priv->dma_tx_phy, txsize);
495 /* Clear the Rx/Tx descriptors */
496 priv->hw->desc->init_rx_desc(priv->dma_rx, rxsize, dis_ic);
497 priv->hw->desc->init_tx_desc(priv->dma_tx, txsize);
499 if (netif_msg_hw(priv)) {
500 pr_info("RX descriptor ring:\n");
501 display_ring(priv->dma_rx, rxsize);
502 pr_info("TX descriptor ring:\n");
503 display_ring(priv->dma_tx, txsize);
507 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
511 for (i = 0; i < priv->dma_rx_size; i++) {
512 if (priv->rx_skbuff[i]) {
513 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
514 priv->dma_buf_sz, DMA_FROM_DEVICE);
515 dev_kfree_skb_any(priv->rx_skbuff[i]);
517 priv->rx_skbuff[i] = NULL;
521 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
525 for (i = 0; i < priv->dma_tx_size; i++) {
526 if (priv->tx_skbuff[i] != NULL) {
527 struct dma_desc *p = priv->dma_tx + i;
529 dma_unmap_single(priv->device, p->des2,
530 priv->hw->desc->get_tx_len(p),
532 dev_kfree_skb_any(priv->tx_skbuff[i]);
533 priv->tx_skbuff[i] = NULL;
538 static void free_dma_desc_resources(struct stmmac_priv *priv)
540 /* Release the DMA TX/RX socket buffers */
541 dma_free_rx_skbufs(priv);
542 dma_free_tx_skbufs(priv);
544 /* Free the region of consistent memory previously allocated for
546 dma_free_coherent(priv->device,
547 priv->dma_tx_size * sizeof(struct dma_desc),
548 priv->dma_tx, priv->dma_tx_phy);
549 dma_free_coherent(priv->device,
550 priv->dma_rx_size * sizeof(struct dma_desc),
551 priv->dma_rx, priv->dma_rx_phy);
552 kfree(priv->rx_skbuff_dma);
553 kfree(priv->rx_skbuff);
554 kfree(priv->tx_skbuff);
558 * stmmac_dma_operation_mode - HW DMA operation mode
559 * @priv : pointer to the private device structure.
560 * Description: it sets the DMA operation mode: tx/rx DMA thresholds
561 * or Store-And-Forward capability.
563 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
565 if (likely(priv->plat->force_sf_dma_mode ||
566 ((priv->plat->tx_coe) && (!priv->no_csum_insertion)))) {
568 * In case of GMAC, SF mode can be enabled
569 * to perform the TX COE in HW. This depends on:
570 * 1) TX COE if actually supported
571 * 2) There is no bugged Jumbo frame support
572 * that needs to not insert csum in the TDES.
574 priv->hw->dma->dma_mode(priv->ioaddr,
575 SF_DMA_MODE, SF_DMA_MODE);
578 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
583 * @priv: private driver structure
584 * Description: it reclaims resources after transmission completes.
586 static void stmmac_tx(struct stmmac_priv *priv)
588 unsigned int txsize = priv->dma_tx_size;
590 spin_lock(&priv->tx_lock);
592 while (priv->dirty_tx != priv->cur_tx) {
594 unsigned int entry = priv->dirty_tx % txsize;
595 struct sk_buff *skb = priv->tx_skbuff[entry];
596 struct dma_desc *p = priv->dma_tx + entry;
598 /* Check if the descriptor is owned by the DMA. */
599 if (priv->hw->desc->get_tx_owner(p))
602 /* Verify tx error by looking at the last segment */
603 last = priv->hw->desc->get_tx_ls(p);
606 priv->hw->desc->tx_status(&priv->dev->stats,
609 if (likely(tx_error == 0)) {
610 priv->dev->stats.tx_packets++;
611 priv->xstats.tx_pkt_n++;
613 priv->dev->stats.tx_errors++;
615 TX_DBG("%s: curr %d, dirty %d\n", __func__,
616 priv->cur_tx, priv->dirty_tx);
619 dma_unmap_single(priv->device, p->des2,
620 priv->hw->desc->get_tx_len(p),
622 priv->hw->ring->clean_desc3(p);
624 if (likely(skb != NULL)) {
626 * If there's room in the queue (limit it to size)
627 * we add this skb back into the pool,
628 * if it's the right size.
630 if ((skb_queue_len(&priv->rx_recycle) <
631 priv->dma_rx_size) &&
632 skb_recycle_check(skb, priv->dma_buf_sz))
633 __skb_queue_head(&priv->rx_recycle, skb);
637 priv->tx_skbuff[entry] = NULL;
640 priv->hw->desc->release_tx_desc(p);
642 entry = (++priv->dirty_tx) % txsize;
644 if (unlikely(netif_queue_stopped(priv->dev) &&
645 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
646 netif_tx_lock(priv->dev);
647 if (netif_queue_stopped(priv->dev) &&
648 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
649 TX_DBG("%s: restart transmit\n", __func__);
650 netif_wake_queue(priv->dev);
652 netif_tx_unlock(priv->dev);
654 spin_unlock(&priv->tx_lock);
657 static inline void stmmac_enable_irq(struct stmmac_priv *priv)
659 #ifdef CONFIG_STMMAC_TIMER
660 if (likely(priv->tm->enable))
661 priv->tm->timer_start(tmrate);
664 priv->hw->dma->enable_dma_irq(priv->ioaddr);
667 static inline void stmmac_disable_irq(struct stmmac_priv *priv)
669 #ifdef CONFIG_STMMAC_TIMER
670 if (likely(priv->tm->enable))
671 priv->tm->timer_stop();
674 priv->hw->dma->disable_dma_irq(priv->ioaddr);
677 static int stmmac_has_work(struct stmmac_priv *priv)
679 unsigned int has_work = 0;
680 int rxret, tx_work = 0;
682 rxret = priv->hw->desc->get_rx_owner(priv->dma_rx +
683 (priv->cur_rx % priv->dma_rx_size));
685 if (priv->dirty_tx != priv->cur_tx)
688 if (likely(!rxret || tx_work))
694 static inline void _stmmac_schedule(struct stmmac_priv *priv)
696 if (likely(stmmac_has_work(priv))) {
697 stmmac_disable_irq(priv);
698 napi_schedule(&priv->napi);
702 #ifdef CONFIG_STMMAC_TIMER
703 void stmmac_schedule(struct net_device *dev)
705 struct stmmac_priv *priv = netdev_priv(dev);
707 priv->xstats.sched_timer_n++;
709 _stmmac_schedule(priv);
712 static void stmmac_no_timer_started(unsigned int x)
716 static void stmmac_no_timer_stopped(void)
723 * @priv: pointer to the private device structure
724 * Description: it cleans the descriptors and restarts the transmission
727 static void stmmac_tx_err(struct stmmac_priv *priv)
729 netif_stop_queue(priv->dev);
731 priv->hw->dma->stop_tx(priv->ioaddr);
732 dma_free_tx_skbufs(priv);
733 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
736 priv->hw->dma->start_tx(priv->ioaddr);
738 priv->dev->stats.tx_errors++;
739 netif_wake_queue(priv->dev);
743 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
747 status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
748 if (likely(status == handle_tx_rx))
749 _stmmac_schedule(priv);
751 else if (unlikely(status == tx_hard_error_bump_tc)) {
752 /* Try to bump up the dma threshold on this failure */
753 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
755 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
756 priv->xstats.threshold = tc;
758 } else if (unlikely(status == tx_hard_error))
762 static void stmmac_mmc_setup(struct stmmac_priv *priv)
764 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
765 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
767 /* Mask MMC irq, counters are managed in SW and registers
768 * are cleared on each READ eventually. */
769 dwmac_mmc_intr_all_mask(priv->ioaddr);
771 if (priv->dma_cap.rmon) {
772 dwmac_mmc_ctrl(priv->ioaddr, mode);
773 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
775 pr_info(" No MAC Management Counters available\n");
778 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
780 u32 hwid = priv->hw->synopsys_uid;
782 /* Only check valid Synopsys Id because old MAC chips
783 * have no HW registers where get the ID */
785 u32 uid = ((hwid & 0x0000ff00) >> 8);
786 u32 synid = (hwid & 0x000000ff);
788 pr_info("STMMAC - user ID: 0x%x, Synopsys ID: 0x%x\n",
797 * stmmac_selec_desc_mode
798 * @dev : device pointer
799 * Description: select the Enhanced/Alternate or Normal descriptors */
800 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
802 if (priv->plat->enh_desc) {
803 pr_info(" Enhanced/Alternate descriptors\n");
804 priv->hw->desc = &enh_desc_ops;
806 pr_info(" Normal descriptors\n");
807 priv->hw->desc = &ndesc_ops;
812 * stmmac_get_hw_features
813 * @priv : private device pointer
815 * new GMAC chip generations have a new register to indicate the
816 * presence of the optional feature/functions.
817 * This can be also used to override the value passed through the
818 * platform and necessary for old MAC10/100 and GMAC chips.
820 static int stmmac_get_hw_features(struct stmmac_priv *priv)
824 if (priv->hw->dma->get_hw_feature) {
825 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
827 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
828 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
829 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
830 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
831 priv->dma_cap.multi_addr =
832 (hw_cap & DMA_HW_FEAT_ADDMACADRSEL) >> 5;
833 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
834 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
835 priv->dma_cap.pmt_remote_wake_up =
836 (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
837 priv->dma_cap.pmt_magic_frame =
838 (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
840 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
842 priv->dma_cap.time_stamp =
843 (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
845 priv->dma_cap.atime_stamp =
846 (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
847 /* 802.3az - Energy-Efficient Ethernet (EEE) */
848 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
849 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
851 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
852 priv->dma_cap.rx_coe_type1 =
853 (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
854 priv->dma_cap.rx_coe_type2 =
855 (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
856 priv->dma_cap.rxfifo_over_2048 =
857 (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
858 /* TX and RX number of channels */
859 priv->dma_cap.number_rx_channel =
860 (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
861 priv->dma_cap.number_tx_channel =
862 (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
863 /* Alternate (enhanced) DESC mode*/
864 priv->dma_cap.enh_desc =
865 (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
873 * stmmac_mac_device_setup
874 * @dev : device pointer
875 * Description: this is to attach the GMAC or MAC 10/100
876 * main core structures that will be completed during the
879 static int stmmac_mac_device_setup(struct net_device *dev)
881 struct stmmac_priv *priv = netdev_priv(dev);
883 struct mac_device_info *device;
885 if (priv->plat->has_gmac)
886 device = dwmac1000_setup(priv->ioaddr);
888 device = dwmac100_setup(priv->ioaddr);
894 priv->hw->ring = &ring_mode_ops;
896 if (device_can_wakeup(priv->device)) {
897 priv->wolopts = WAKE_MAGIC; /* Magic Frame as default */
898 enable_irq_wake(priv->wol_irq);
904 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
906 /* verify if the MAC address is valid, in case of failures it
907 * generates a random MAC address */
908 if (!is_valid_ether_addr(priv->dev->dev_addr)) {
909 priv->hw->mac->get_umac_addr((void __iomem *)
910 priv->dev->base_addr,
911 priv->dev->dev_addr, 0);
912 if (!is_valid_ether_addr(priv->dev->dev_addr))
913 random_ether_addr(priv->dev->dev_addr);
915 pr_warning("%s: device MAC address %pM\n", priv->dev->name,
916 priv->dev->dev_addr);
920 * stmmac_open - open entry point of the driver
921 * @dev : pointer to the device structure.
923 * This function is the open entry point of the driver.
925 * 0 on success and an appropriate (-)ve integer as defined in errno.h
928 static int stmmac_open(struct net_device *dev)
930 struct stmmac_priv *priv = netdev_priv(dev);
933 /* MAC HW device setup */
934 ret = stmmac_mac_device_setup(dev);
938 stmmac_check_ether_addr(priv);
940 stmmac_verify_args();
942 /* Override with kernel parameters if supplied XXX CRS XXX
943 * this needs to have multiple instances */
944 if ((phyaddr >= 0) && (phyaddr <= 31))
945 priv->plat->phy_addr = phyaddr;
947 /* MDIO bus Registration */
948 ret = stmmac_mdio_register(dev);
950 pr_debug("%s: MDIO bus (id: %d) registration failed",
951 __func__, priv->plat->bus_id);
955 #ifdef CONFIG_STMMAC_TIMER
956 priv->tm = kzalloc(sizeof(struct stmmac_timer *), GFP_KERNEL);
957 if (unlikely(priv->tm == NULL)) {
958 pr_err("%s: ERROR: timer memory alloc failed\n", __func__);
961 priv->tm->freq = tmrate;
963 /* Test if the external timer can be actually used.
964 * In case of failure continue without timer. */
965 if (unlikely((stmmac_open_ext_timer(dev, priv->tm)) < 0)) {
966 pr_warning("stmmaceth: cannot attach the external timer.\n");
968 priv->tm->timer_start = stmmac_no_timer_started;
969 priv->tm->timer_stop = stmmac_no_timer_stopped;
971 priv->tm->enable = 1;
973 ret = stmmac_init_phy(dev);
975 pr_err("%s: Cannot attach to PHY (error: %d)\n", __func__, ret);
979 stmmac_get_synopsys_id(priv);
981 priv->hw_cap_support = stmmac_get_hw_features(priv);
983 if (priv->hw_cap_support) {
984 pr_info(" Support DMA HW capability register");
986 /* We can override some gmac/dma configuration fields: e.g.
987 * enh_desc, tx_coe (e.g. that are passed through the
988 * platform) with the values from the HW capability
989 * register (if supported).
991 priv->plat->enh_desc = priv->dma_cap.enh_desc;
992 priv->plat->tx_coe = priv->dma_cap.tx_coe;
993 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
995 /* By default disable wol on magic frame if not supported */
996 if (!priv->dma_cap.pmt_magic_frame)
997 priv->wolopts &= ~WAKE_MAGIC;
1000 pr_info(" No HW DMA feature register supported");
1002 /* Select the enhnaced/normal descriptor structures */
1003 stmmac_selec_desc_mode(priv);
1005 /* PMT module is not integrated in all the MAC devices. */
1006 if (priv->plat->pmt) {
1007 pr_info(" Remote wake-up capable\n");
1008 device_set_wakeup_capable(priv->device, 1);
1011 priv->rx_coe = priv->hw->mac->rx_coe(priv->ioaddr);
1013 pr_info(" Checksum Offload Engine supported\n");
1014 if (priv->plat->tx_coe)
1015 pr_info(" Checksum insertion supported\n");
1017 /* Create and initialize the TX/RX descriptors chains. */
1018 priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
1019 priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
1020 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1021 init_dma_desc_rings(dev);
1023 /* DMA initialization and SW reset */
1024 ret = priv->hw->dma->init(priv->ioaddr, priv->plat->pbl,
1025 priv->dma_tx_phy, priv->dma_rx_phy);
1027 pr_err("%s: DMA initialization failed\n", __func__);
1031 /* Copy the MAC addr into the HW */
1032 priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
1033 /* If required, perform hw setup of the bus. */
1034 if (priv->plat->bus_setup)
1035 priv->plat->bus_setup(priv->ioaddr);
1036 /* Initialize the MAC Core */
1037 priv->hw->mac->core_init(priv->ioaddr);
1039 netdev_update_features(dev);
1041 /* Request the IRQ lines */
1042 ret = request_irq(dev->irq, stmmac_interrupt,
1043 IRQF_SHARED, dev->name, dev);
1044 if (unlikely(ret < 0)) {
1045 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1046 __func__, dev->irq, ret);
1050 /* Enable the MAC Rx/Tx */
1051 stmmac_set_mac(priv->ioaddr, true);
1053 /* Set the HW DMA mode and the COE */
1054 stmmac_dma_operation_mode(priv);
1056 /* Extra statistics */
1057 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1058 priv->xstats.threshold = tc;
1060 stmmac_mmc_setup(priv);
1062 #ifdef CONFIG_STMMAC_DEBUG_FS
1063 ret = stmmac_init_fs(dev);
1065 pr_warning("\tFailed debugFS registration");
1067 /* Start the ball rolling... */
1068 DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name);
1069 priv->hw->dma->start_tx(priv->ioaddr);
1070 priv->hw->dma->start_rx(priv->ioaddr);
1072 #ifdef CONFIG_STMMAC_TIMER
1073 priv->tm->timer_start(tmrate);
1075 /* Dump DMA/MAC registers */
1076 if (netif_msg_hw(priv)) {
1077 priv->hw->mac->dump_regs(priv->ioaddr);
1078 priv->hw->dma->dump_regs(priv->ioaddr);
1082 phy_start(priv->phydev);
1084 napi_enable(&priv->napi);
1085 skb_queue_head_init(&priv->rx_recycle);
1086 netif_start_queue(dev);
1091 #ifdef CONFIG_STMMAC_TIMER
1095 phy_disconnect(priv->phydev);
1101 * stmmac_release - close entry point of the driver
1102 * @dev : device pointer.
1104 * This is the stop entry point of the driver.
1106 static int stmmac_release(struct net_device *dev)
1108 struct stmmac_priv *priv = netdev_priv(dev);
1110 /* Stop and disconnect the PHY */
1112 phy_stop(priv->phydev);
1113 phy_disconnect(priv->phydev);
1114 priv->phydev = NULL;
1117 netif_stop_queue(dev);
1119 #ifdef CONFIG_STMMAC_TIMER
1120 /* Stop and release the timer */
1121 stmmac_close_ext_timer();
1122 if (priv->tm != NULL)
1125 napi_disable(&priv->napi);
1126 skb_queue_purge(&priv->rx_recycle);
1128 /* Free the IRQ lines */
1129 free_irq(dev->irq, dev);
1131 /* Stop TX/RX DMA and clear the descriptors */
1132 priv->hw->dma->stop_tx(priv->ioaddr);
1133 priv->hw->dma->stop_rx(priv->ioaddr);
1135 /* Release and free the Rx/Tx resources */
1136 free_dma_desc_resources(priv);
1138 /* Disable the MAC Rx/Tx */
1139 stmmac_set_mac(priv->ioaddr, false);
1141 netif_carrier_off(dev);
1143 #ifdef CONFIG_STMMAC_DEBUG_FS
1146 stmmac_mdio_unregister(dev);
1153 * @skb : the socket buffer
1154 * @dev : device pointer
1155 * Description : Tx entry point of the driver.
1157 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1159 struct stmmac_priv *priv = netdev_priv(dev);
1160 unsigned int txsize = priv->dma_tx_size;
1162 int i, csum_insertion = 0;
1163 int nfrags = skb_shinfo(skb)->nr_frags;
1164 struct dma_desc *desc, *first;
1165 unsigned int nopaged_len = skb_headlen(skb);
1167 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1168 if (!netif_queue_stopped(dev)) {
1169 netif_stop_queue(dev);
1170 /* This is a hard error, log it. */
1171 pr_err("%s: BUG! Tx Ring full when queue awake\n",
1174 return NETDEV_TX_BUSY;
1177 spin_lock(&priv->tx_lock);
1179 entry = priv->cur_tx % txsize;
1181 #ifdef STMMAC_XMIT_DEBUG
1182 if ((skb->len > ETH_FRAME_LEN) || nfrags)
1183 pr_info("stmmac xmit:\n"
1184 "\tskb addr %p - len: %d - nopaged_len: %d\n"
1185 "\tn_frags: %d - ip_summed: %d - %s gso\n",
1186 skb, skb->len, nopaged_len, nfrags, skb->ip_summed,
1187 !skb_is_gso(skb) ? "isn't" : "is");
1190 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
1192 desc = priv->dma_tx + entry;
1195 #ifdef STMMAC_XMIT_DEBUG
1196 if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN))
1197 pr_debug("stmmac xmit: skb len: %d, nopaged_len: %d,\n"
1198 "\t\tn_frags: %d, ip_summed: %d\n",
1199 skb->len, nopaged_len, nfrags, skb->ip_summed);
1201 priv->tx_skbuff[entry] = skb;
1203 if (priv->hw->ring->is_jumbo_frm(skb->len, priv->plat->enh_desc)) {
1204 entry = priv->hw->ring->jumbo_frm(priv, skb, csum_insertion);
1205 desc = priv->dma_tx + entry;
1207 desc->des2 = dma_map_single(priv->device, skb->data,
1208 nopaged_len, DMA_TO_DEVICE);
1209 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1213 for (i = 0; i < nfrags; i++) {
1214 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1215 int len = skb_frag_size(frag);
1217 entry = (++priv->cur_tx) % txsize;
1218 desc = priv->dma_tx + entry;
1220 TX_DBG("\t[entry %d] segment len: %d\n", entry, len);
1221 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
1223 priv->tx_skbuff[entry] = NULL;
1224 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion);
1226 priv->hw->desc->set_tx_owner(desc);
1229 /* Interrupt on completition only for the latest segment */
1230 priv->hw->desc->close_tx_desc(desc);
1232 #ifdef CONFIG_STMMAC_TIMER
1233 /* Clean IC while using timer */
1234 if (likely(priv->tm->enable))
1235 priv->hw->desc->clear_tx_ic(desc);
1240 /* To avoid raise condition */
1241 priv->hw->desc->set_tx_owner(first);
1245 #ifdef STMMAC_XMIT_DEBUG
1246 if (netif_msg_pktdata(priv)) {
1247 pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, "
1248 "first=%p, nfrags=%d\n",
1249 (priv->cur_tx % txsize), (priv->dirty_tx % txsize),
1250 entry, first, nfrags);
1251 display_ring(priv->dma_tx, txsize);
1252 pr_info(">>> frame to be transmitted: ");
1253 print_pkt(skb->data, skb->len);
1256 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
1257 TX_DBG("%s: stop transmitted packets\n", __func__);
1258 netif_stop_queue(dev);
1261 dev->stats.tx_bytes += skb->len;
1263 skb_tx_timestamp(skb);
1265 priv->hw->dma->enable_dma_transmission(priv->ioaddr);
1267 spin_unlock(&priv->tx_lock);
1269 return NETDEV_TX_OK;
1272 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
1274 unsigned int rxsize = priv->dma_rx_size;
1275 int bfsize = priv->dma_buf_sz;
1276 struct dma_desc *p = priv->dma_rx;
1278 for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
1279 unsigned int entry = priv->dirty_rx % rxsize;
1280 if (likely(priv->rx_skbuff[entry] == NULL)) {
1281 struct sk_buff *skb;
1283 skb = __skb_dequeue(&priv->rx_recycle);
1285 skb = netdev_alloc_skb_ip_align(priv->dev,
1288 if (unlikely(skb == NULL))
1291 priv->rx_skbuff[entry] = skb;
1292 priv->rx_skbuff_dma[entry] =
1293 dma_map_single(priv->device, skb->data, bfsize,
1296 (p + entry)->des2 = priv->rx_skbuff_dma[entry];
1298 if (unlikely(priv->plat->has_gmac))
1299 priv->hw->ring->refill_desc3(bfsize, p + entry);
1301 RX_DBG(KERN_INFO "\trefill entry #%d\n", entry);
1304 priv->hw->desc->set_rx_owner(p + entry);
1308 static int stmmac_rx(struct stmmac_priv *priv, int limit)
1310 unsigned int rxsize = priv->dma_rx_size;
1311 unsigned int entry = priv->cur_rx % rxsize;
1312 unsigned int next_entry;
1313 unsigned int count = 0;
1314 struct dma_desc *p = priv->dma_rx + entry;
1315 struct dma_desc *p_next;
1317 #ifdef STMMAC_RX_DEBUG
1318 if (netif_msg_hw(priv)) {
1319 pr_debug(">>> stmmac_rx: descriptor ring:\n");
1320 display_ring(priv->dma_rx, rxsize);
1324 while (!priv->hw->desc->get_rx_owner(p)) {
1332 next_entry = (++priv->cur_rx) % rxsize;
1333 p_next = priv->dma_rx + next_entry;
1336 /* read the status of the incoming frame */
1337 status = (priv->hw->desc->rx_status(&priv->dev->stats,
1339 if (unlikely(status == discard_frame))
1340 priv->dev->stats.rx_errors++;
1342 struct sk_buff *skb;
1345 frame_len = priv->hw->desc->get_rx_frame_len(p);
1346 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
1347 * Type frames (LLC/LLC-SNAP) */
1348 if (unlikely(status != llc_snap))
1349 frame_len -= ETH_FCS_LEN;
1350 #ifdef STMMAC_RX_DEBUG
1351 if (frame_len > ETH_FRAME_LEN)
1352 pr_debug("\tRX frame size %d, COE status: %d\n",
1355 if (netif_msg_hw(priv))
1356 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
1359 skb = priv->rx_skbuff[entry];
1360 if (unlikely(!skb)) {
1361 pr_err("%s: Inconsistent Rx descriptor chain\n",
1363 priv->dev->stats.rx_dropped++;
1366 prefetch(skb->data - NET_IP_ALIGN);
1367 priv->rx_skbuff[entry] = NULL;
1369 skb_put(skb, frame_len);
1370 dma_unmap_single(priv->device,
1371 priv->rx_skbuff_dma[entry],
1372 priv->dma_buf_sz, DMA_FROM_DEVICE);
1373 #ifdef STMMAC_RX_DEBUG
1374 if (netif_msg_pktdata(priv)) {
1375 pr_info(" frame received (%dbytes)", frame_len);
1376 print_pkt(skb->data, frame_len);
1379 skb->protocol = eth_type_trans(skb, priv->dev);
1381 if (unlikely(!priv->rx_coe)) {
1382 /* No RX COE for old mac10/100 devices */
1383 skb_checksum_none_assert(skb);
1384 netif_receive_skb(skb);
1386 skb->ip_summed = CHECKSUM_UNNECESSARY;
1387 napi_gro_receive(&priv->napi, skb);
1390 priv->dev->stats.rx_packets++;
1391 priv->dev->stats.rx_bytes += frame_len;
1394 p = p_next; /* use prefetched values */
1397 stmmac_rx_refill(priv);
1399 priv->xstats.rx_pkt_n += count;
1405 * stmmac_poll - stmmac poll method (NAPI)
1406 * @napi : pointer to the napi structure.
1407 * @budget : maximum number of packets that the current CPU can receive from
1410 * This function implements the the reception process.
1411 * Also it runs the TX completion thread
1413 static int stmmac_poll(struct napi_struct *napi, int budget)
1415 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
1418 priv->xstats.poll_n++;
1420 work_done = stmmac_rx(priv, budget);
1422 if (work_done < budget) {
1423 napi_complete(napi);
1424 stmmac_enable_irq(priv);
1431 * @dev : Pointer to net device structure
1432 * Description: this function is called when a packet transmission fails to
1433 * complete within a reasonable tmrate. The driver will mark the error in the
1434 * netdev structure and arrange for the device to be reset to a sane state
1435 * in order to transmit a new packet.
1437 static void stmmac_tx_timeout(struct net_device *dev)
1439 struct stmmac_priv *priv = netdev_priv(dev);
1441 /* Clear Tx resources and restart transmitting again */
1442 stmmac_tx_err(priv);
1445 /* Configuration changes (passed on by ifconfig) */
1446 static int stmmac_config(struct net_device *dev, struct ifmap *map)
1448 if (dev->flags & IFF_UP) /* can't act on a running interface */
1451 /* Don't allow changing the I/O address */
1452 if (map->base_addr != dev->base_addr) {
1453 pr_warning("%s: can't change I/O address\n", dev->name);
1457 /* Don't allow changing the IRQ */
1458 if (map->irq != dev->irq) {
1459 pr_warning("%s: can't change IRQ number %d\n",
1460 dev->name, dev->irq);
1464 /* ignore other fields */
1469 * stmmac_set_rx_mode - entry point for multicast addressing
1470 * @dev : pointer to the device structure
1472 * This function is a driver entry point which gets called by the kernel
1473 * whenever multicast addresses must be enabled/disabled.
1477 static void stmmac_set_rx_mode(struct net_device *dev)
1479 struct stmmac_priv *priv = netdev_priv(dev);
1481 spin_lock(&priv->lock);
1482 priv->hw->mac->set_filter(dev);
1483 spin_unlock(&priv->lock);
1487 * stmmac_change_mtu - entry point to change MTU size for the device.
1488 * @dev : device pointer.
1489 * @new_mtu : the new MTU size for the device.
1490 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
1491 * to drive packet transmission. Ethernet has an MTU of 1500 octets
1492 * (ETH_DATA_LEN). This value can be changed with ifconfig.
1494 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1497 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
1499 struct stmmac_priv *priv = netdev_priv(dev);
1502 if (netif_running(dev)) {
1503 pr_err("%s: must be stopped to change its MTU\n", dev->name);
1507 if (priv->plat->enh_desc)
1508 max_mtu = JUMBO_LEN;
1510 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
1512 if ((new_mtu < 46) || (new_mtu > max_mtu)) {
1513 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
1518 netdev_update_features(dev);
1523 static netdev_features_t stmmac_fix_features(struct net_device *dev,
1524 netdev_features_t features)
1526 struct stmmac_priv *priv = netdev_priv(dev);
1529 features &= ~NETIF_F_RXCSUM;
1530 if (!priv->plat->tx_coe)
1531 features &= ~NETIF_F_ALL_CSUM;
1533 /* Some GMAC devices have a bugged Jumbo frame support that
1534 * needs to have the Tx COE disabled for oversized frames
1535 * (due to limited buffer sizes). In this case we disable
1536 * the TX csum insertionin the TDES and not use SF. */
1537 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
1538 features &= ~NETIF_F_ALL_CSUM;
1543 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
1545 struct net_device *dev = (struct net_device *)dev_id;
1546 struct stmmac_priv *priv = netdev_priv(dev);
1548 if (unlikely(!dev)) {
1549 pr_err("%s: invalid dev pointer\n", __func__);
1553 if (priv->plat->has_gmac)
1554 /* To handle GMAC own interrupts */
1555 priv->hw->mac->host_irq_status((void __iomem *) dev->base_addr);
1557 stmmac_dma_interrupt(priv);
1562 #ifdef CONFIG_NET_POLL_CONTROLLER
1563 /* Polling receive - used by NETCONSOLE and other diagnostic tools
1564 * to allow network I/O with interrupts disabled. */
1565 static void stmmac_poll_controller(struct net_device *dev)
1567 disable_irq(dev->irq);
1568 stmmac_interrupt(dev->irq, dev);
1569 enable_irq(dev->irq);
1574 * stmmac_ioctl - Entry point for the Ioctl
1575 * @dev: Device pointer.
1576 * @rq: An IOCTL specefic structure, that can contain a pointer to
1577 * a proprietary structure used to pass information to the driver.
1578 * @cmd: IOCTL command
1580 * Currently there are no special functionality supported in IOCTL, just the
1581 * phy_mii_ioctl(...) can be invoked.
1583 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1585 struct stmmac_priv *priv = netdev_priv(dev);
1588 if (!netif_running(dev))
1594 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
1599 #ifdef CONFIG_STMMAC_DEBUG_FS
1600 static struct dentry *stmmac_fs_dir;
1601 static struct dentry *stmmac_rings_status;
1602 static struct dentry *stmmac_dma_cap;
1604 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
1612 struct net_device *dev = seq->private;
1613 struct stmmac_priv *priv = netdev_priv(dev);
1615 seq_printf(seq, "=======================\n");
1616 seq_printf(seq, " RX descriptor ring\n");
1617 seq_printf(seq, "=======================\n");
1619 for (i = 0; i < priv->dma_rx_size; i++) {
1620 struct tmp_s *x = (struct tmp_s *)(priv->dma_rx + i);
1621 seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
1622 i, (unsigned int)(x->a),
1623 (unsigned int)((x->a) >> 32), x->b, x->c);
1624 seq_printf(seq, "\n");
1627 seq_printf(seq, "\n");
1628 seq_printf(seq, "=======================\n");
1629 seq_printf(seq, " TX descriptor ring\n");
1630 seq_printf(seq, "=======================\n");
1632 for (i = 0; i < priv->dma_tx_size; i++) {
1633 struct tmp_s *x = (struct tmp_s *)(priv->dma_tx + i);
1634 seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
1635 i, (unsigned int)(x->a),
1636 (unsigned int)((x->a) >> 32), x->b, x->c);
1637 seq_printf(seq, "\n");
1643 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
1645 return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
1648 static const struct file_operations stmmac_rings_status_fops = {
1649 .owner = THIS_MODULE,
1650 .open = stmmac_sysfs_ring_open,
1652 .llseek = seq_lseek,
1653 .release = seq_release,
1656 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
1658 struct net_device *dev = seq->private;
1659 struct stmmac_priv *priv = netdev_priv(dev);
1661 if (!priv->hw_cap_support) {
1662 seq_printf(seq, "DMA HW features not supported\n");
1666 seq_printf(seq, "==============================\n");
1667 seq_printf(seq, "\tDMA HW features\n");
1668 seq_printf(seq, "==============================\n");
1670 seq_printf(seq, "\t10/100 Mbps %s\n",
1671 (priv->dma_cap.mbps_10_100) ? "Y" : "N");
1672 seq_printf(seq, "\t1000 Mbps %s\n",
1673 (priv->dma_cap.mbps_1000) ? "Y" : "N");
1674 seq_printf(seq, "\tHalf duple %s\n",
1675 (priv->dma_cap.half_duplex) ? "Y" : "N");
1676 seq_printf(seq, "\tHash Filter: %s\n",
1677 (priv->dma_cap.hash_filter) ? "Y" : "N");
1678 seq_printf(seq, "\tMultiple MAC address registers: %s\n",
1679 (priv->dma_cap.multi_addr) ? "Y" : "N");
1680 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
1681 (priv->dma_cap.pcs) ? "Y" : "N");
1682 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
1683 (priv->dma_cap.sma_mdio) ? "Y" : "N");
1684 seq_printf(seq, "\tPMT Remote wake up: %s\n",
1685 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
1686 seq_printf(seq, "\tPMT Magic Frame: %s\n",
1687 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
1688 seq_printf(seq, "\tRMON module: %s\n",
1689 (priv->dma_cap.rmon) ? "Y" : "N");
1690 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
1691 (priv->dma_cap.time_stamp) ? "Y" : "N");
1692 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
1693 (priv->dma_cap.atime_stamp) ? "Y" : "N");
1694 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
1695 (priv->dma_cap.eee) ? "Y" : "N");
1696 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
1697 seq_printf(seq, "\tChecksum Offload in TX: %s\n",
1698 (priv->dma_cap.tx_coe) ? "Y" : "N");
1699 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
1700 (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
1701 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
1702 (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
1703 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
1704 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
1705 seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
1706 priv->dma_cap.number_rx_channel);
1707 seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
1708 priv->dma_cap.number_tx_channel);
1709 seq_printf(seq, "\tEnhanced descriptors: %s\n",
1710 (priv->dma_cap.enh_desc) ? "Y" : "N");
1715 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
1717 return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
1720 static const struct file_operations stmmac_dma_cap_fops = {
1721 .owner = THIS_MODULE,
1722 .open = stmmac_sysfs_dma_cap_open,
1724 .llseek = seq_lseek,
1725 .release = seq_release,
1728 static int stmmac_init_fs(struct net_device *dev)
1730 /* Create debugfs entries */
1731 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
1733 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
1734 pr_err("ERROR %s, debugfs create directory failed\n",
1735 STMMAC_RESOURCE_NAME);
1740 /* Entry to report DMA RX/TX rings */
1741 stmmac_rings_status = debugfs_create_file("descriptors_status",
1742 S_IRUGO, stmmac_fs_dir, dev,
1743 &stmmac_rings_status_fops);
1745 if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) {
1746 pr_info("ERROR creating stmmac ring debugfs file\n");
1747 debugfs_remove(stmmac_fs_dir);
1752 /* Entry to report the DMA HW features */
1753 stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir,
1754 dev, &stmmac_dma_cap_fops);
1756 if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) {
1757 pr_info("ERROR creating stmmac MMC debugfs file\n");
1758 debugfs_remove(stmmac_rings_status);
1759 debugfs_remove(stmmac_fs_dir);
1767 static void stmmac_exit_fs(void)
1769 debugfs_remove(stmmac_rings_status);
1770 debugfs_remove(stmmac_dma_cap);
1771 debugfs_remove(stmmac_fs_dir);
1773 #endif /* CONFIG_STMMAC_DEBUG_FS */
1775 static const struct net_device_ops stmmac_netdev_ops = {
1776 .ndo_open = stmmac_open,
1777 .ndo_start_xmit = stmmac_xmit,
1778 .ndo_stop = stmmac_release,
1779 .ndo_change_mtu = stmmac_change_mtu,
1780 .ndo_fix_features = stmmac_fix_features,
1781 .ndo_set_rx_mode = stmmac_set_rx_mode,
1782 .ndo_tx_timeout = stmmac_tx_timeout,
1783 .ndo_do_ioctl = stmmac_ioctl,
1784 .ndo_set_config = stmmac_config,
1785 #ifdef CONFIG_NET_POLL_CONTROLLER
1786 .ndo_poll_controller = stmmac_poll_controller,
1788 .ndo_set_mac_address = eth_mac_addr,
1793 * @device: device pointer
1794 * Description: this is the main probe function used to
1795 * call the alloc_etherdev, allocate the priv structure.
1797 struct stmmac_priv *stmmac_dvr_probe(struct device *device,
1798 struct plat_stmmacenet_data *plat_dat)
1801 struct net_device *ndev = NULL;
1802 struct stmmac_priv *priv;
1804 ndev = alloc_etherdev(sizeof(struct stmmac_priv));
1806 pr_err("%s: ERROR: allocating the device\n", __func__);
1810 SET_NETDEV_DEV(ndev, device);
1812 priv = netdev_priv(ndev);
1813 priv->device = device;
1818 ndev->netdev_ops = &stmmac_netdev_ops;
1819 stmmac_set_ethtool_ops(ndev);
1821 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1822 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
1823 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
1824 #ifdef STMMAC_VLAN_TAG_USED
1825 /* Both mac100 and gmac support receive VLAN tag detection */
1826 ndev->features |= NETIF_F_HW_VLAN_RX;
1828 priv->msg_enable = netif_msg_init(debug, default_msg_level);
1831 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
1833 priv->pause = pause;
1834 priv->plat = plat_dat;
1835 netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
1837 spin_lock_init(&priv->lock);
1838 spin_lock_init(&priv->tx_lock);
1840 ret = register_netdev(ndev);
1842 pr_err("%s: ERROR %i registering the device\n",
1847 DBG(probe, DEBUG, "%s: Scatter/Gather: %s - HW checksums: %s\n",
1848 ndev->name, (ndev->features & NETIF_F_SG) ? "on" : "off",
1849 (ndev->features & NETIF_F_IP_CSUM) ? "on" : "off");
1854 netif_napi_del(&priv->napi);
1856 unregister_netdev(ndev);
1864 * @ndev: net device pointer
1865 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
1866 * changes the link status, releases the DMA descriptor rings.
1868 int stmmac_dvr_remove(struct net_device *ndev)
1870 struct stmmac_priv *priv = netdev_priv(ndev);
1872 pr_info("%s:\n\tremoving driver", __func__);
1874 priv->hw->dma->stop_rx(priv->ioaddr);
1875 priv->hw->dma->stop_tx(priv->ioaddr);
1877 stmmac_set_mac(priv->ioaddr, false);
1878 netif_carrier_off(ndev);
1879 unregister_netdev(ndev);
1886 int stmmac_suspend(struct net_device *ndev)
1888 struct stmmac_priv *priv = netdev_priv(ndev);
1891 if (!ndev || !netif_running(ndev))
1895 phy_stop(priv->phydev);
1897 spin_lock(&priv->lock);
1899 netif_device_detach(ndev);
1900 netif_stop_queue(ndev);
1902 #ifdef CONFIG_STMMAC_TIMER
1903 priv->tm->timer_stop();
1904 if (likely(priv->tm->enable))
1907 napi_disable(&priv->napi);
1909 /* Stop TX/RX DMA */
1910 priv->hw->dma->stop_tx(priv->ioaddr);
1911 priv->hw->dma->stop_rx(priv->ioaddr);
1912 /* Clear the Rx/Tx descriptors */
1913 priv->hw->desc->init_rx_desc(priv->dma_rx, priv->dma_rx_size,
1915 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
1917 /* Enable Power down mode by programming the PMT regs */
1918 if (device_may_wakeup(priv->device))
1919 priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
1921 stmmac_set_mac(priv->ioaddr, false);
1923 spin_unlock(&priv->lock);
1927 int stmmac_resume(struct net_device *ndev)
1929 struct stmmac_priv *priv = netdev_priv(ndev);
1931 if (!netif_running(ndev))
1934 spin_lock(&priv->lock);
1936 /* Power Down bit, into the PM register, is cleared
1937 * automatically as soon as a magic packet or a Wake-up frame
1938 * is received. Anyway, it's better to manually clear
1939 * this bit because it can generate problems while resuming
1940 * from another devices (e.g. serial console). */
1941 if (device_may_wakeup(priv->device))
1942 priv->hw->mac->pmt(priv->ioaddr, 0);
1944 netif_device_attach(ndev);
1946 /* Enable the MAC and DMA */
1947 stmmac_set_mac(priv->ioaddr, true);
1948 priv->hw->dma->start_tx(priv->ioaddr);
1949 priv->hw->dma->start_rx(priv->ioaddr);
1951 #ifdef CONFIG_STMMAC_TIMER
1952 if (likely(priv->tm->enable))
1953 priv->tm->timer_start(tmrate);
1955 napi_enable(&priv->napi);
1957 netif_start_queue(ndev);
1959 spin_unlock(&priv->lock);
1962 phy_start(priv->phydev);
1967 int stmmac_freeze(struct net_device *ndev)
1969 if (!ndev || !netif_running(ndev))
1972 return stmmac_release(ndev);
1975 int stmmac_restore(struct net_device *ndev)
1977 if (!ndev || !netif_running(ndev))
1980 return stmmac_open(ndev);
1982 #endif /* CONFIG_PM */
1985 static int __init stmmac_cmdline_opt(char *str)
1991 while ((opt = strsep(&str, ",")) != NULL) {
1992 if (!strncmp(opt, "debug:", 6)) {
1993 if (strict_strtoul(opt + 6, 0, (unsigned long *)&debug))
1995 } else if (!strncmp(opt, "phyaddr:", 8)) {
1996 if (strict_strtoul(opt + 8, 0,
1997 (unsigned long *)&phyaddr))
1999 } else if (!strncmp(opt, "dma_txsize:", 11)) {
2000 if (strict_strtoul(opt + 11, 0,
2001 (unsigned long *)&dma_txsize))
2003 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
2004 if (strict_strtoul(opt + 11, 0,
2005 (unsigned long *)&dma_rxsize))
2007 } else if (!strncmp(opt, "buf_sz:", 7)) {
2008 if (strict_strtoul(opt + 7, 0,
2009 (unsigned long *)&buf_sz))
2011 } else if (!strncmp(opt, "tc:", 3)) {
2012 if (strict_strtoul(opt + 3, 0, (unsigned long *)&tc))
2014 } else if (!strncmp(opt, "watchdog:", 9)) {
2015 if (strict_strtoul(opt + 9, 0,
2016 (unsigned long *)&watchdog))
2018 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
2019 if (strict_strtoul(opt + 10, 0,
2020 (unsigned long *)&flow_ctrl))
2022 } else if (!strncmp(opt, "pause:", 6)) {
2023 if (strict_strtoul(opt + 6, 0, (unsigned long *)&pause))
2025 #ifdef CONFIG_STMMAC_TIMER
2026 } else if (!strncmp(opt, "tmrate:", 7)) {
2027 if (strict_strtoul(opt + 7, 0,
2028 (unsigned long *)&tmrate))
2036 pr_err("%s: ERROR broken module parameter conversion", __func__);
2040 __setup("stmmaceth=", stmmac_cmdline_opt);
2043 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
2044 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
2045 MODULE_LICENSE("GPL");