1 /*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
5 Copyright(C) 2007-2011 STMicroelectronics Ltd
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
25 Documentation available at:
26 http://www.stlinux.com
28 https://bugzilla.stlinux.com/
29 *******************************************************************************/
31 #include <linux/clk.h>
32 #include <linux/kernel.h>
33 #include <linux/interrupt.h>
35 #include <linux/tcp.h>
36 #include <linux/skbuff.h>
37 #include <linux/ethtool.h>
38 #include <linux/if_ether.h>
39 #include <linux/crc32.h>
40 #include <linux/mii.h>
42 #include <linux/if_vlan.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/slab.h>
45 #include <linux/prefetch.h>
46 #include <linux/pinctrl/consumer.h>
47 #ifdef CONFIG_DEBUG_FS
48 #include <linux/debugfs.h>
49 #include <linux/seq_file.h>
50 #endif /* CONFIG_DEBUG_FS */
51 #include <linux/net_tstamp.h>
52 #include "stmmac_ptp.h"
54 #include <linux/reset.h>
55 #include <linux/of_mdio.h>
56 #include "dwmac1000.h"
58 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
59 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1)
61 /* Module parameters */
63 static int watchdog = TX_TIMEO;
64 module_param(watchdog, int, S_IRUGO | S_IWUSR);
65 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
67 static int debug = -1;
68 module_param(debug, int, S_IRUGO | S_IWUSR);
69 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
71 static int phyaddr = -1;
72 module_param(phyaddr, int, S_IRUGO);
73 MODULE_PARM_DESC(phyaddr, "Physical device address");
75 #define STMMAC_TX_THRESH (DMA_TX_SIZE / 4)
76 #define STMMAC_RX_THRESH (DMA_RX_SIZE / 4)
78 static int flow_ctrl = FLOW_OFF;
79 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
80 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
82 static int pause = PAUSE_TIME;
83 module_param(pause, int, S_IRUGO | S_IWUSR);
84 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
87 static int tc = TC_DEFAULT;
88 module_param(tc, int, S_IRUGO | S_IWUSR);
89 MODULE_PARM_DESC(tc, "DMA threshold control value");
91 #define DEFAULT_BUFSIZE 1536
92 static int buf_sz = DEFAULT_BUFSIZE;
93 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
94 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
96 #define STMMAC_RX_COPYBREAK 256
98 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
99 NETIF_MSG_LINK | NETIF_MSG_IFUP |
100 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
102 #define STMMAC_DEFAULT_LPI_TIMER 1000
103 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
104 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
105 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
106 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
108 /* By default the driver will use the ring mode to manage tx and rx descriptors,
109 * but allow user to force to use the chain instead of the ring
111 static unsigned int chain_mode;
112 module_param(chain_mode, int, S_IRUGO);
113 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
115 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
117 #ifdef CONFIG_DEBUG_FS
118 static int stmmac_init_fs(struct net_device *dev);
119 static void stmmac_exit_fs(struct net_device *dev);
122 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
125 * stmmac_verify_args - verify the driver parameters.
126 * Description: it checks the driver parameters and set a default in case of
129 static void stmmac_verify_args(void)
131 if (unlikely(watchdog < 0))
133 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
134 buf_sz = DEFAULT_BUFSIZE;
135 if (unlikely(flow_ctrl > 1))
136 flow_ctrl = FLOW_AUTO;
137 else if (likely(flow_ctrl < 0))
138 flow_ctrl = FLOW_OFF;
139 if (unlikely((pause < 0) || (pause > 0xffff)))
142 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
146 * stmmac_clk_csr_set - dynamically set the MDC clock
147 * @priv: driver private structure
148 * Description: this is to dynamically set the MDC clock according to the csr
151 * If a specific clk_csr value is passed from the platform
152 * this means that the CSR Clock Range selection cannot be
153 * changed at run-time and it is fixed (as reported in the driver
154 * documentation). Viceversa the driver will try to set the MDC
155 * clock dynamically according to the actual clock input.
157 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
161 clk_rate = clk_get_rate(priv->stmmac_clk);
163 /* Platform provided default clk_csr would be assumed valid
164 * for all other cases except for the below mentioned ones.
165 * For values higher than the IEEE 802.3 specified frequency
166 * we can not estimate the proper divider as it is not known
167 * the frequency of clk_csr_i. So we do not change the default
170 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
171 if (clk_rate < CSR_F_35M)
172 priv->clk_csr = STMMAC_CSR_20_35M;
173 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
174 priv->clk_csr = STMMAC_CSR_35_60M;
175 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
176 priv->clk_csr = STMMAC_CSR_60_100M;
177 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
178 priv->clk_csr = STMMAC_CSR_100_150M;
179 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
180 priv->clk_csr = STMMAC_CSR_150_250M;
181 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
182 priv->clk_csr = STMMAC_CSR_250_300M;
186 static void print_pkt(unsigned char *buf, int len)
188 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
189 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
192 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
196 if (priv->dirty_tx > priv->cur_tx)
197 avail = priv->dirty_tx - priv->cur_tx - 1;
199 avail = DMA_TX_SIZE - priv->cur_tx + priv->dirty_tx - 1;
204 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv)
208 if (priv->dirty_rx <= priv->cur_rx)
209 dirty = priv->cur_rx - priv->dirty_rx;
211 dirty = DMA_RX_SIZE - priv->dirty_rx + priv->cur_rx;
217 * stmmac_hw_fix_mac_speed - callback for speed selection
218 * @priv: driver private structure
219 * Description: on some platforms (e.g. ST), some HW system configuraton
220 * registers have to be set according to the link speed negotiated.
222 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
224 struct net_device *ndev = priv->dev;
225 struct phy_device *phydev = ndev->phydev;
227 if (likely(priv->plat->fix_mac_speed))
228 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
232 * stmmac_enable_eee_mode - check and enter in LPI mode
233 * @priv: driver private structure
234 * Description: this function is to verify and enter in LPI mode in case of
237 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
239 /* Check and enter in LPI mode */
240 if ((priv->dirty_tx == priv->cur_tx) &&
241 (priv->tx_path_in_lpi_mode == false))
242 priv->hw->mac->set_eee_mode(priv->hw);
246 * stmmac_disable_eee_mode - disable and exit from LPI mode
247 * @priv: driver private structure
248 * Description: this function is to exit and disable EEE in case of
249 * LPI state is true. This is called by the xmit.
251 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
253 priv->hw->mac->reset_eee_mode(priv->hw);
254 del_timer_sync(&priv->eee_ctrl_timer);
255 priv->tx_path_in_lpi_mode = false;
259 * stmmac_eee_ctrl_timer - EEE TX SW timer.
262 * if there is no data transfer and if we are not in LPI state,
263 * then MAC Transmitter can be moved to LPI state.
265 static void stmmac_eee_ctrl_timer(unsigned long arg)
267 struct stmmac_priv *priv = (struct stmmac_priv *)arg;
269 stmmac_enable_eee_mode(priv);
270 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
274 * stmmac_eee_init - init EEE
275 * @priv: driver private structure
277 * if the GMAC supports the EEE (from the HW cap reg) and the phy device
278 * can also manage EEE, this function enable the LPI state and start related
281 bool stmmac_eee_init(struct stmmac_priv *priv)
283 struct net_device *ndev = priv->dev;
287 /* Using PCS we cannot dial with the phy registers at this stage
288 * so we do not support extra feature like EEE.
290 if ((priv->hw->pcs == STMMAC_PCS_RGMII) ||
291 (priv->hw->pcs == STMMAC_PCS_TBI) ||
292 (priv->hw->pcs == STMMAC_PCS_RTBI))
295 /* MAC core supports the EEE feature. */
296 if (priv->dma_cap.eee) {
297 int tx_lpi_timer = priv->tx_lpi_timer;
299 /* Check if the PHY supports EEE */
300 if (phy_init_eee(ndev->phydev, 1)) {
301 /* To manage at run-time if the EEE cannot be supported
302 * anymore (for example because the lp caps have been
304 * In that case the driver disable own timers.
306 spin_lock_irqsave(&priv->lock, flags);
307 if (priv->eee_active) {
308 netdev_dbg(priv->dev, "disable EEE\n");
309 del_timer_sync(&priv->eee_ctrl_timer);
310 priv->hw->mac->set_eee_timer(priv->hw, 0,
313 priv->eee_active = 0;
314 spin_unlock_irqrestore(&priv->lock, flags);
317 /* Activate the EEE and start timers */
318 spin_lock_irqsave(&priv->lock, flags);
319 if (!priv->eee_active) {
320 priv->eee_active = 1;
321 setup_timer(&priv->eee_ctrl_timer,
322 stmmac_eee_ctrl_timer,
323 (unsigned long)priv);
324 mod_timer(&priv->eee_ctrl_timer,
325 STMMAC_LPI_T(eee_timer));
327 priv->hw->mac->set_eee_timer(priv->hw,
328 STMMAC_DEFAULT_LIT_LS,
331 /* Set HW EEE according to the speed */
332 priv->hw->mac->set_eee_pls(priv->hw, ndev->phydev->link);
335 spin_unlock_irqrestore(&priv->lock, flags);
337 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n");
343 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
344 * @priv: driver private structure
345 * @p : descriptor pointer
346 * @skb : the socket buffer
348 * This function will read timestamp from the descriptor & pass it to stack.
349 * and also perform some sanity checks.
351 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
352 struct dma_desc *p, struct sk_buff *skb)
354 struct skb_shared_hwtstamps shhwtstamp;
357 if (!priv->hwts_tx_en)
360 /* exit if skb doesn't support hw tstamp */
361 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
364 /* check tx tstamp status */
365 if (!priv->hw->desc->get_tx_timestamp_status(p)) {
366 /* get the valid tstamp */
367 ns = priv->hw->desc->get_timestamp(p, priv->adv_ts);
369 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
370 shhwtstamp.hwtstamp = ns_to_ktime(ns);
372 netdev_info(priv->dev, "get valid TX hw timestamp %llu\n", ns);
373 /* pass tstamp to stack */
374 skb_tstamp_tx(skb, &shhwtstamp);
380 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
381 * @priv: driver private structure
382 * @p : descriptor pointer
383 * @np : next descriptor pointer
384 * @skb : the socket buffer
386 * This function will read received packet's timestamp from the descriptor
387 * and pass it to stack. It also perform some sanity checks.
389 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p,
390 struct dma_desc *np, struct sk_buff *skb)
392 struct skb_shared_hwtstamps *shhwtstamp = NULL;
395 if (!priv->hwts_rx_en)
398 /* Check if timestamp is available */
399 if (!priv->hw->desc->get_rx_timestamp_status(p, priv->adv_ts)) {
400 /* For GMAC4, the valid timestamp is from CTX next desc. */
401 if (priv->plat->has_gmac4)
402 ns = priv->hw->desc->get_timestamp(np, priv->adv_ts);
404 ns = priv->hw->desc->get_timestamp(p, priv->adv_ts);
406 netdev_info(priv->dev, "get valid RX hw timestamp %llu\n", ns);
407 shhwtstamp = skb_hwtstamps(skb);
408 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
409 shhwtstamp->hwtstamp = ns_to_ktime(ns);
411 netdev_err(priv->dev, "cannot get RX hw timestamp\n");
416 * stmmac_hwtstamp_ioctl - control hardware timestamping.
417 * @dev: device pointer.
418 * @ifr: An IOCTL specefic structure, that can contain a pointer to
419 * a proprietary structure used to pass information to the driver.
421 * This function configures the MAC to enable/disable both outgoing(TX)
422 * and incoming(RX) packets time stamping based on user input.
424 * 0 on success and an appropriate -ve integer on failure.
426 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
428 struct stmmac_priv *priv = netdev_priv(dev);
429 struct hwtstamp_config config;
430 struct timespec64 now;
434 u32 ptp_over_ipv4_udp = 0;
435 u32 ptp_over_ipv6_udp = 0;
436 u32 ptp_over_ethernet = 0;
437 u32 snap_type_sel = 0;
438 u32 ts_master_en = 0;
443 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
444 netdev_alert(priv->dev, "No support for HW time stamping\n");
445 priv->hwts_tx_en = 0;
446 priv->hwts_rx_en = 0;
451 if (copy_from_user(&config, ifr->ifr_data,
452 sizeof(struct hwtstamp_config)))
455 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
456 __func__, config.flags, config.tx_type, config.rx_filter);
458 /* reserved for future extensions */
462 if (config.tx_type != HWTSTAMP_TX_OFF &&
463 config.tx_type != HWTSTAMP_TX_ON)
467 switch (config.rx_filter) {
468 case HWTSTAMP_FILTER_NONE:
469 /* time stamp no incoming packet at all */
470 config.rx_filter = HWTSTAMP_FILTER_NONE;
473 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
474 /* PTP v1, UDP, any kind of event packet */
475 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
476 /* take time stamp for all event messages */
477 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
479 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
480 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
483 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
484 /* PTP v1, UDP, Sync packet */
485 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
486 /* take time stamp for SYNC messages only */
487 ts_event_en = PTP_TCR_TSEVNTENA;
489 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
490 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
493 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
494 /* PTP v1, UDP, Delay_req packet */
495 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
496 /* take time stamp for Delay_Req messages only */
497 ts_master_en = PTP_TCR_TSMSTRENA;
498 ts_event_en = PTP_TCR_TSEVNTENA;
500 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
501 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
504 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
505 /* PTP v2, UDP, any kind of event packet */
506 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
507 ptp_v2 = PTP_TCR_TSVER2ENA;
508 /* take time stamp for all event messages */
509 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
511 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
512 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
515 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
516 /* PTP v2, UDP, Sync packet */
517 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
518 ptp_v2 = PTP_TCR_TSVER2ENA;
519 /* take time stamp for SYNC messages only */
520 ts_event_en = PTP_TCR_TSEVNTENA;
522 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
523 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
526 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
527 /* PTP v2, UDP, Delay_req packet */
528 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
529 ptp_v2 = PTP_TCR_TSVER2ENA;
530 /* take time stamp for Delay_Req messages only */
531 ts_master_en = PTP_TCR_TSMSTRENA;
532 ts_event_en = PTP_TCR_TSEVNTENA;
534 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
535 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
538 case HWTSTAMP_FILTER_PTP_V2_EVENT:
539 /* PTP v2/802.AS1 any layer, any kind of event packet */
540 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
541 ptp_v2 = PTP_TCR_TSVER2ENA;
542 /* take time stamp for all event messages */
543 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
545 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
546 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
547 ptp_over_ethernet = PTP_TCR_TSIPENA;
550 case HWTSTAMP_FILTER_PTP_V2_SYNC:
551 /* PTP v2/802.AS1, any layer, Sync packet */
552 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
553 ptp_v2 = PTP_TCR_TSVER2ENA;
554 /* take time stamp for SYNC messages only */
555 ts_event_en = PTP_TCR_TSEVNTENA;
557 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
558 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
559 ptp_over_ethernet = PTP_TCR_TSIPENA;
562 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
563 /* PTP v2/802.AS1, any layer, Delay_req packet */
564 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
565 ptp_v2 = PTP_TCR_TSVER2ENA;
566 /* take time stamp for Delay_Req messages only */
567 ts_master_en = PTP_TCR_TSMSTRENA;
568 ts_event_en = PTP_TCR_TSEVNTENA;
570 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
571 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
572 ptp_over_ethernet = PTP_TCR_TSIPENA;
575 case HWTSTAMP_FILTER_ALL:
576 /* time stamp any incoming packet */
577 config.rx_filter = HWTSTAMP_FILTER_ALL;
578 tstamp_all = PTP_TCR_TSENALL;
585 switch (config.rx_filter) {
586 case HWTSTAMP_FILTER_NONE:
587 config.rx_filter = HWTSTAMP_FILTER_NONE;
590 /* PTP v1, UDP, any kind of event packet */
591 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
595 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
596 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
598 if (!priv->hwts_tx_en && !priv->hwts_rx_en)
599 priv->hw->ptp->config_hw_tstamping(priv->ptpaddr, 0);
601 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
602 tstamp_all | ptp_v2 | ptp_over_ethernet |
603 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
604 ts_master_en | snap_type_sel);
605 priv->hw->ptp->config_hw_tstamping(priv->ptpaddr, value);
607 /* program Sub Second Increment reg */
608 sec_inc = priv->hw->ptp->config_sub_second_increment(
609 priv->ptpaddr, priv->clk_ptp_rate,
610 priv->plat->has_gmac4);
611 temp = div_u64(1000000000ULL, sec_inc);
613 /* calculate default added value:
615 * addend = (2^32)/freq_div_ratio;
616 * where, freq_div_ratio = 1e9ns/sec_inc
618 temp = (u64)(temp << 32);
619 priv->default_addend = div_u64(temp, priv->clk_ptp_rate);
620 priv->hw->ptp->config_addend(priv->ptpaddr,
621 priv->default_addend);
623 /* initialize system time */
624 ktime_get_real_ts64(&now);
626 /* lower 32 bits of tv_sec are safe until y2106 */
627 priv->hw->ptp->init_systime(priv->ptpaddr, (u32)now.tv_sec,
631 return copy_to_user(ifr->ifr_data, &config,
632 sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
636 * stmmac_init_ptp - init PTP
637 * @priv: driver private structure
638 * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
639 * This is done by looking at the HW cap. register.
640 * This function also registers the ptp driver.
642 static int stmmac_init_ptp(struct stmmac_priv *priv)
644 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
647 /* Fall-back to main clock in case of no PTP ref is passed */
648 priv->clk_ptp_ref = devm_clk_get(priv->device, "clk_ptp_ref");
649 if (IS_ERR(priv->clk_ptp_ref)) {
650 priv->clk_ptp_rate = clk_get_rate(priv->stmmac_clk);
651 priv->clk_ptp_ref = NULL;
652 netdev_dbg(priv->dev, "PTP uses main clock\n");
654 clk_prepare_enable(priv->clk_ptp_ref);
655 priv->clk_ptp_rate = clk_get_rate(priv->clk_ptp_ref);
656 netdev_dbg(priv->dev, "PTP rate %d\n", priv->clk_ptp_rate);
660 /* Check if adv_ts can be enabled for dwmac 4.x core */
661 if (priv->plat->has_gmac4 && priv->dma_cap.atime_stamp)
663 /* Dwmac 3.x core with extend_desc can support adv_ts */
664 else if (priv->extend_desc && priv->dma_cap.atime_stamp)
667 if (priv->dma_cap.time_stamp)
668 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n");
671 netdev_info(priv->dev,
672 "IEEE 1588-2008 Advanced Timestamp supported\n");
674 priv->hw->ptp = &stmmac_ptp;
675 priv->hwts_tx_en = 0;
676 priv->hwts_rx_en = 0;
678 stmmac_ptp_register(priv);
683 static void stmmac_release_ptp(struct stmmac_priv *priv)
685 if (priv->clk_ptp_ref)
686 clk_disable_unprepare(priv->clk_ptp_ref);
687 stmmac_ptp_unregister(priv);
691 * stmmac_adjust_link - adjusts the link parameters
692 * @dev: net device structure
693 * Description: this is the helper called by the physical abstraction layer
694 * drivers to communicate the phy link status. According the speed and duplex
695 * this driver can invoke registered glue-logic as well.
696 * It also invoke the eee initialization because it could happen when switch
697 * on different networks (that are eee capable).
699 static void stmmac_adjust_link(struct net_device *dev)
701 struct stmmac_priv *priv = netdev_priv(dev);
702 struct phy_device *phydev = dev->phydev;
705 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
710 spin_lock_irqsave(&priv->lock, flags);
713 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
715 /* Now we make sure that we can be in full duplex mode.
716 * If not, we operate in half-duplex mode. */
717 if (phydev->duplex != priv->oldduplex) {
719 if (!(phydev->duplex))
720 ctrl &= ~priv->hw->link.duplex;
722 ctrl |= priv->hw->link.duplex;
723 priv->oldduplex = phydev->duplex;
725 /* Flow Control operation */
727 priv->hw->mac->flow_ctrl(priv->hw, phydev->duplex,
730 if (phydev->speed != priv->speed) {
732 switch (phydev->speed) {
734 if (likely((priv->plat->has_gmac) ||
735 (priv->plat->has_gmac4)))
736 ctrl &= ~priv->hw->link.port;
737 stmmac_hw_fix_mac_speed(priv);
741 if (likely((priv->plat->has_gmac) ||
742 (priv->plat->has_gmac4))) {
743 ctrl |= priv->hw->link.port;
744 if (phydev->speed == SPEED_100) {
745 ctrl |= priv->hw->link.speed;
747 ctrl &= ~(priv->hw->link.speed);
750 ctrl &= ~priv->hw->link.port;
752 stmmac_hw_fix_mac_speed(priv);
755 netif_warn(priv, link, priv->dev,
756 "Speed (%d) not 10/100\n",
761 priv->speed = phydev->speed;
764 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
766 if (!priv->oldlink) {
770 } else if (priv->oldlink) {
774 priv->oldduplex = -1;
777 if (new_state && netif_msg_link(priv))
778 phy_print_status(phydev);
780 spin_unlock_irqrestore(&priv->lock, flags);
782 if (phydev->is_pseudo_fixed_link)
783 /* Stop PHY layer to call the hook to adjust the link in case
784 * of a switch is attached to the stmmac driver.
786 phydev->irq = PHY_IGNORE_INTERRUPT;
788 /* At this stage, init the EEE if supported.
789 * Never called in case of fixed_link.
791 priv->eee_enabled = stmmac_eee_init(priv);
795 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
796 * @priv: driver private structure
797 * Description: this is to verify if the HW supports the PCS.
798 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
799 * configured for the TBI, RTBI, or SGMII PHY interface.
801 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
803 int interface = priv->plat->interface;
805 if (priv->dma_cap.pcs) {
806 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
807 (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
808 (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
809 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
810 netdev_dbg(priv->dev, "PCS RGMII support enabled\n");
811 priv->hw->pcs = STMMAC_PCS_RGMII;
812 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
813 netdev_dbg(priv->dev, "PCS SGMII support enabled\n");
814 priv->hw->pcs = STMMAC_PCS_SGMII;
820 * stmmac_init_phy - PHY initialization
821 * @dev: net device structure
822 * Description: it initializes the driver's PHY state, and attaches the PHY
827 static int stmmac_init_phy(struct net_device *dev)
829 struct stmmac_priv *priv = netdev_priv(dev);
830 struct phy_device *phydev;
831 char phy_id_fmt[MII_BUS_ID_SIZE + 3];
832 char bus_id[MII_BUS_ID_SIZE];
833 int interface = priv->plat->interface;
834 int max_speed = priv->plat->max_speed;
837 priv->oldduplex = -1;
839 if (priv->plat->phy_node) {
840 phydev = of_phy_connect(dev, priv->plat->phy_node,
841 &stmmac_adjust_link, 0, interface);
843 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
846 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
847 priv->plat->phy_addr);
848 netdev_dbg(priv->dev, "%s: trying to attach to %s\n", __func__,
851 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link,
855 if (IS_ERR_OR_NULL(phydev)) {
856 netdev_err(priv->dev, "Could not attach to PHY\n");
860 return PTR_ERR(phydev);
863 /* Stop Advertising 1000BASE Capability if interface is not GMII */
864 if ((interface == PHY_INTERFACE_MODE_MII) ||
865 (interface == PHY_INTERFACE_MODE_RMII) ||
866 (max_speed < 1000 && max_speed > 0))
867 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
868 SUPPORTED_1000baseT_Full);
871 * Broken HW is sometimes missing the pull-up resistor on the
872 * MDIO line, which results in reads to non-existent devices returning
873 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
875 * Note: phydev->phy_id is the result of reading the UID PHY registers.
877 if (!priv->plat->phy_node && phydev->phy_id == 0) {
878 phy_disconnect(phydev);
882 /* stmmac_adjust_link will change this to PHY_IGNORE_INTERRUPT to avoid
883 * subsequent PHY polling, make sure we force a link transition if
884 * we have a UP/DOWN/UP transition
886 if (phydev->is_pseudo_fixed_link)
887 phydev->irq = PHY_POLL;
889 netdev_dbg(priv->dev, "%s: attached to PHY (UID 0x%x) Link = %d\n",
890 __func__, phydev->phy_id, phydev->link);
895 static void stmmac_display_rings(struct stmmac_priv *priv)
897 void *head_rx, *head_tx;
899 if (priv->extend_desc) {
900 head_rx = (void *)priv->dma_erx;
901 head_tx = (void *)priv->dma_etx;
903 head_rx = (void *)priv->dma_rx;
904 head_tx = (void *)priv->dma_tx;
907 /* Display Rx ring */
908 priv->hw->desc->display_ring(head_rx, DMA_RX_SIZE, true);
909 /* Display Tx ring */
910 priv->hw->desc->display_ring(head_tx, DMA_TX_SIZE, false);
913 static int stmmac_set_bfsize(int mtu, int bufsize)
917 if (mtu >= BUF_SIZE_4KiB)
919 else if (mtu >= BUF_SIZE_2KiB)
921 else if (mtu > DEFAULT_BUFSIZE)
924 ret = DEFAULT_BUFSIZE;
930 * stmmac_clear_descriptors - clear descriptors
931 * @priv: driver private structure
932 * Description: this function is called to clear the tx and rx descriptors
933 * in case of both basic and extended descriptors are used.
935 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
939 /* Clear the Rx/Tx descriptors */
940 for (i = 0; i < DMA_RX_SIZE; i++)
941 if (priv->extend_desc)
942 priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
943 priv->use_riwt, priv->mode,
944 (i == DMA_RX_SIZE - 1));
946 priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
947 priv->use_riwt, priv->mode,
948 (i == DMA_RX_SIZE - 1));
949 for (i = 0; i < DMA_TX_SIZE; i++)
950 if (priv->extend_desc)
951 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
953 (i == DMA_TX_SIZE - 1));
955 priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
957 (i == DMA_TX_SIZE - 1));
961 * stmmac_init_rx_buffers - init the RX descriptor buffer.
962 * @priv: driver private structure
963 * @p: descriptor pointer
964 * @i: descriptor index
966 * Description: this function is called to allocate a receive buffer, perform
967 * the DMA mapping and init the descriptor.
969 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
974 skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags);
976 netdev_err(priv->dev,
977 "%s: Rx init fails; skb is NULL\n", __func__);
980 priv->rx_skbuff[i] = skb;
981 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
984 if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) {
985 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__);
986 dev_kfree_skb_any(skb);
990 if (priv->synopsys_id >= DWMAC_CORE_4_00)
991 p->des0 = cpu_to_le32(priv->rx_skbuff_dma[i]);
993 p->des2 = cpu_to_le32(priv->rx_skbuff_dma[i]);
995 if ((priv->hw->mode->init_desc3) &&
996 (priv->dma_buf_sz == BUF_SIZE_16KiB))
997 priv->hw->mode->init_desc3(p);
1002 static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i)
1004 if (priv->rx_skbuff[i]) {
1005 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
1006 priv->dma_buf_sz, DMA_FROM_DEVICE);
1007 dev_kfree_skb_any(priv->rx_skbuff[i]);
1009 priv->rx_skbuff[i] = NULL;
1013 * init_dma_desc_rings - init the RX/TX descriptor rings
1014 * @dev: net device structure
1016 * Description: this function initializes the DMA RX/TX descriptors
1017 * and allocates the socket buffers. It suppors the chained and ring
1020 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1023 struct stmmac_priv *priv = netdev_priv(dev);
1024 unsigned int bfsize = 0;
1027 if (priv->hw->mode->set_16kib_bfsize)
1028 bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu);
1030 if (bfsize < BUF_SIZE_16KiB)
1031 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1033 priv->dma_buf_sz = bfsize;
1035 netif_dbg(priv, probe, priv->dev,
1036 "(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n",
1037 __func__, (u32)priv->dma_rx_phy, (u32)priv->dma_tx_phy);
1039 /* RX INITIALIZATION */
1040 netif_dbg(priv, probe, priv->dev,
1041 "SKB addresses:\nskb\t\tskb data\tdma data\n");
1043 for (i = 0; i < DMA_RX_SIZE; i++) {
1045 if (priv->extend_desc)
1046 p = &((priv->dma_erx + i)->basic);
1048 p = priv->dma_rx + i;
1050 ret = stmmac_init_rx_buffers(priv, p, i, flags);
1052 goto err_init_rx_buffers;
1054 netif_dbg(priv, probe, priv->dev, "[%p]\t[%p]\t[%x]\n",
1055 priv->rx_skbuff[i], priv->rx_skbuff[i]->data,
1056 (unsigned int)priv->rx_skbuff_dma[i]);
1059 priv->dirty_rx = (unsigned int)(i - DMA_RX_SIZE);
1062 /* Setup the chained descriptor addresses */
1063 if (priv->mode == STMMAC_CHAIN_MODE) {
1064 if (priv->extend_desc) {
1065 priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy,
1067 priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy,
1070 priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy,
1072 priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy,
1077 /* TX INITIALIZATION */
1078 for (i = 0; i < DMA_TX_SIZE; i++) {
1080 if (priv->extend_desc)
1081 p = &((priv->dma_etx + i)->basic);
1083 p = priv->dma_tx + i;
1085 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
1094 priv->tx_skbuff_dma[i].buf = 0;
1095 priv->tx_skbuff_dma[i].map_as_page = false;
1096 priv->tx_skbuff_dma[i].len = 0;
1097 priv->tx_skbuff_dma[i].last_segment = false;
1098 priv->tx_skbuff[i] = NULL;
1103 netdev_reset_queue(priv->dev);
1105 stmmac_clear_descriptors(priv);
1107 if (netif_msg_hw(priv))
1108 stmmac_display_rings(priv);
1111 err_init_rx_buffers:
1113 stmmac_free_rx_buffers(priv, i);
1117 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
1121 for (i = 0; i < DMA_RX_SIZE; i++)
1122 stmmac_free_rx_buffers(priv, i);
1125 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
1129 for (i = 0; i < DMA_TX_SIZE; i++) {
1132 if (priv->extend_desc)
1133 p = &((priv->dma_etx + i)->basic);
1135 p = priv->dma_tx + i;
1137 if (priv->tx_skbuff_dma[i].buf) {
1138 if (priv->tx_skbuff_dma[i].map_as_page)
1139 dma_unmap_page(priv->device,
1140 priv->tx_skbuff_dma[i].buf,
1141 priv->tx_skbuff_dma[i].len,
1144 dma_unmap_single(priv->device,
1145 priv->tx_skbuff_dma[i].buf,
1146 priv->tx_skbuff_dma[i].len,
1150 if (priv->tx_skbuff[i] != NULL) {
1151 dev_kfree_skb_any(priv->tx_skbuff[i]);
1152 priv->tx_skbuff[i] = NULL;
1153 priv->tx_skbuff_dma[i].buf = 0;
1154 priv->tx_skbuff_dma[i].map_as_page = false;
1160 * alloc_dma_desc_resources - alloc TX/RX resources.
1161 * @priv: private structure
1162 * Description: according to which descriptor can be used (extend or basic)
1163 * this function allocates the resources for TX and RX paths. In case of
1164 * reception, for example, it pre-allocated the RX socket buffer in order to
1165 * allow zero-copy mechanism.
1167 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1171 priv->rx_skbuff_dma = kmalloc_array(DMA_RX_SIZE, sizeof(dma_addr_t),
1173 if (!priv->rx_skbuff_dma)
1176 priv->rx_skbuff = kmalloc_array(DMA_RX_SIZE, sizeof(struct sk_buff *),
1178 if (!priv->rx_skbuff)
1181 priv->tx_skbuff_dma = kmalloc_array(DMA_TX_SIZE,
1182 sizeof(*priv->tx_skbuff_dma),
1184 if (!priv->tx_skbuff_dma)
1185 goto err_tx_skbuff_dma;
1187 priv->tx_skbuff = kmalloc_array(DMA_TX_SIZE, sizeof(struct sk_buff *),
1189 if (!priv->tx_skbuff)
1192 if (priv->extend_desc) {
1193 priv->dma_erx = dma_zalloc_coherent(priv->device, DMA_RX_SIZE *
1201 priv->dma_etx = dma_zalloc_coherent(priv->device, DMA_TX_SIZE *
1206 if (!priv->dma_etx) {
1207 dma_free_coherent(priv->device, DMA_RX_SIZE *
1208 sizeof(struct dma_extended_desc),
1209 priv->dma_erx, priv->dma_rx_phy);
1213 priv->dma_rx = dma_zalloc_coherent(priv->device, DMA_RX_SIZE *
1214 sizeof(struct dma_desc),
1220 priv->dma_tx = dma_zalloc_coherent(priv->device, DMA_TX_SIZE *
1221 sizeof(struct dma_desc),
1224 if (!priv->dma_tx) {
1225 dma_free_coherent(priv->device, DMA_RX_SIZE *
1226 sizeof(struct dma_desc),
1227 priv->dma_rx, priv->dma_rx_phy);
1235 kfree(priv->tx_skbuff);
1237 kfree(priv->tx_skbuff_dma);
1239 kfree(priv->rx_skbuff);
1241 kfree(priv->rx_skbuff_dma);
1245 static void free_dma_desc_resources(struct stmmac_priv *priv)
1247 /* Release the DMA TX/RX socket buffers */
1248 dma_free_rx_skbufs(priv);
1249 dma_free_tx_skbufs(priv);
1251 /* Free DMA regions of consistent memory previously allocated */
1252 if (!priv->extend_desc) {
1253 dma_free_coherent(priv->device,
1254 DMA_TX_SIZE * sizeof(struct dma_desc),
1255 priv->dma_tx, priv->dma_tx_phy);
1256 dma_free_coherent(priv->device,
1257 DMA_RX_SIZE * sizeof(struct dma_desc),
1258 priv->dma_rx, priv->dma_rx_phy);
1260 dma_free_coherent(priv->device, DMA_TX_SIZE *
1261 sizeof(struct dma_extended_desc),
1262 priv->dma_etx, priv->dma_tx_phy);
1263 dma_free_coherent(priv->device, DMA_RX_SIZE *
1264 sizeof(struct dma_extended_desc),
1265 priv->dma_erx, priv->dma_rx_phy);
1267 kfree(priv->rx_skbuff_dma);
1268 kfree(priv->rx_skbuff);
1269 kfree(priv->tx_skbuff_dma);
1270 kfree(priv->tx_skbuff);
1274 * stmmac_dma_operation_mode - HW DMA operation mode
1275 * @priv: driver private structure
1276 * Description: it is used for configuring the DMA operation mode register in
1277 * order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1279 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1281 int rxfifosz = priv->plat->rx_fifo_size;
1283 if (priv->plat->force_thresh_dma_mode)
1284 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, rxfifosz);
1285 else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1287 * In case of GMAC, SF mode can be enabled
1288 * to perform the TX COE in HW. This depends on:
1289 * 1) TX COE if actually supported
1290 * 2) There is no bugged Jumbo frame support
1291 * that needs to not insert csum in the TDES.
1293 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE,
1295 priv->xstats.threshold = SF_DMA_MODE;
1297 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE,
1302 * stmmac_tx_clean - to manage the transmission completion
1303 * @priv: driver private structure
1304 * Description: it reclaims the transmit resources after transmission completes.
1306 static void stmmac_tx_clean(struct stmmac_priv *priv)
1308 unsigned int bytes_compl = 0, pkts_compl = 0;
1309 unsigned int entry = priv->dirty_tx;
1311 netif_tx_lock(priv->dev);
1313 priv->xstats.tx_clean++;
1315 while (entry != priv->cur_tx) {
1316 struct sk_buff *skb = priv->tx_skbuff[entry];
1320 if (priv->extend_desc)
1321 p = (struct dma_desc *)(priv->dma_etx + entry);
1323 p = priv->dma_tx + entry;
1325 status = priv->hw->desc->tx_status(&priv->dev->stats,
1328 /* Check if the descriptor is owned by the DMA */
1329 if (unlikely(status & tx_dma_own))
1332 /* Just consider the last segment and ...*/
1333 if (likely(!(status & tx_not_ls))) {
1334 /* ... verify the status error condition */
1335 if (unlikely(status & tx_err)) {
1336 priv->dev->stats.tx_errors++;
1338 priv->dev->stats.tx_packets++;
1339 priv->xstats.tx_pkt_n++;
1341 stmmac_get_tx_hwtstamp(priv, p, skb);
1344 if (likely(priv->tx_skbuff_dma[entry].buf)) {
1345 if (priv->tx_skbuff_dma[entry].map_as_page)
1346 dma_unmap_page(priv->device,
1347 priv->tx_skbuff_dma[entry].buf,
1348 priv->tx_skbuff_dma[entry].len,
1351 dma_unmap_single(priv->device,
1352 priv->tx_skbuff_dma[entry].buf,
1353 priv->tx_skbuff_dma[entry].len,
1355 priv->tx_skbuff_dma[entry].buf = 0;
1356 priv->tx_skbuff_dma[entry].len = 0;
1357 priv->tx_skbuff_dma[entry].map_as_page = false;
1360 if (priv->hw->mode->clean_desc3)
1361 priv->hw->mode->clean_desc3(priv, p);
1363 priv->tx_skbuff_dma[entry].last_segment = false;
1364 priv->tx_skbuff_dma[entry].is_jumbo = false;
1366 if (likely(skb != NULL)) {
1368 bytes_compl += skb->len;
1369 dev_consume_skb_any(skb);
1370 priv->tx_skbuff[entry] = NULL;
1373 priv->hw->desc->release_tx_desc(p, priv->mode);
1375 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
1377 priv->dirty_tx = entry;
1379 netdev_completed_queue(priv->dev, pkts_compl, bytes_compl);
1381 if (unlikely(netif_queue_stopped(priv->dev) &&
1382 stmmac_tx_avail(priv) > STMMAC_TX_THRESH)) {
1383 netif_dbg(priv, tx_done, priv->dev,
1384 "%s: restart transmit\n", __func__);
1385 netif_wake_queue(priv->dev);
1388 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1389 stmmac_enable_eee_mode(priv);
1390 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1392 netif_tx_unlock(priv->dev);
1395 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
1397 priv->hw->dma->enable_dma_irq(priv->ioaddr);
1400 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
1402 priv->hw->dma->disable_dma_irq(priv->ioaddr);
1406 * stmmac_tx_err - to manage the tx error
1407 * @priv: driver private structure
1408 * Description: it cleans the descriptors and restarts the transmission
1409 * in case of transmission errors.
1411 static void stmmac_tx_err(struct stmmac_priv *priv)
1414 netif_stop_queue(priv->dev);
1416 priv->hw->dma->stop_tx(priv->ioaddr);
1417 dma_free_tx_skbufs(priv);
1418 for (i = 0; i < DMA_TX_SIZE; i++)
1419 if (priv->extend_desc)
1420 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
1422 (i == DMA_TX_SIZE - 1));
1424 priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
1426 (i == DMA_TX_SIZE - 1));
1429 netdev_reset_queue(priv->dev);
1430 priv->hw->dma->start_tx(priv->ioaddr);
1432 priv->dev->stats.tx_errors++;
1433 netif_wake_queue(priv->dev);
1437 * stmmac_dma_interrupt - DMA ISR
1438 * @priv: driver private structure
1439 * Description: this is the DMA ISR. It is called by the main ISR.
1440 * It calls the dwmac dma routine and schedule poll method in case of some
1443 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
1446 int rxfifosz = priv->plat->rx_fifo_size;
1448 status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
1449 if (likely((status & handle_rx)) || (status & handle_tx)) {
1450 if (likely(napi_schedule_prep(&priv->napi))) {
1451 stmmac_disable_dma_irq(priv);
1452 __napi_schedule(&priv->napi);
1455 if (unlikely(status & tx_hard_error_bump_tc)) {
1456 /* Try to bump up the dma threshold on this failure */
1457 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
1460 if (priv->plat->force_thresh_dma_mode)
1461 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc,
1464 priv->hw->dma->dma_mode(priv->ioaddr, tc,
1465 SF_DMA_MODE, rxfifosz);
1466 priv->xstats.threshold = tc;
1468 } else if (unlikely(status == tx_hard_error))
1469 stmmac_tx_err(priv);
1473 * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1474 * @priv: driver private structure
1475 * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1477 static void stmmac_mmc_setup(struct stmmac_priv *priv)
1479 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
1480 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1482 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
1483 priv->ptpaddr = priv->ioaddr + PTP_GMAC4_OFFSET;
1484 priv->mmcaddr = priv->ioaddr + MMC_GMAC4_OFFSET;
1486 priv->ptpaddr = priv->ioaddr + PTP_GMAC3_X_OFFSET;
1487 priv->mmcaddr = priv->ioaddr + MMC_GMAC3_X_OFFSET;
1490 dwmac_mmc_intr_all_mask(priv->mmcaddr);
1492 if (priv->dma_cap.rmon) {
1493 dwmac_mmc_ctrl(priv->mmcaddr, mode);
1494 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
1496 netdev_info(priv->dev, "No MAC Management Counters available\n");
1500 * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors
1501 * @priv: driver private structure
1502 * Description: select the Enhanced/Alternate or Normal descriptors.
1503 * In case of Enhanced/Alternate, it checks if the extended descriptors are
1504 * supported by the HW capability register.
1506 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
1508 if (priv->plat->enh_desc) {
1509 dev_info(priv->device, "Enhanced/Alternate descriptors\n");
1511 /* GMAC older than 3.50 has no extended descriptors */
1512 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
1513 dev_info(priv->device, "Enabled extended descriptors\n");
1514 priv->extend_desc = 1;
1516 dev_warn(priv->device, "Extended descriptors not supported\n");
1518 priv->hw->desc = &enh_desc_ops;
1520 dev_info(priv->device, "Normal descriptors\n");
1521 priv->hw->desc = &ndesc_ops;
1526 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
1527 * @priv: driver private structure
1529 * new GMAC chip generations have a new register to indicate the
1530 * presence of the optional feature/functions.
1531 * This can be also used to override the value passed through the
1532 * platform and necessary for old MAC10/100 and GMAC chips.
1534 static int stmmac_get_hw_features(struct stmmac_priv *priv)
1538 if (priv->hw->dma->get_hw_feature) {
1539 priv->hw->dma->get_hw_feature(priv->ioaddr,
1548 * stmmac_check_ether_addr - check if the MAC addr is valid
1549 * @priv: driver private structure
1551 * it is to verify if the MAC address is valid, in case of failures it
1552 * generates a random MAC address
1554 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
1556 if (!is_valid_ether_addr(priv->dev->dev_addr)) {
1557 priv->hw->mac->get_umac_addr(priv->hw,
1558 priv->dev->dev_addr, 0);
1559 if (!is_valid_ether_addr(priv->dev->dev_addr))
1560 eth_hw_addr_random(priv->dev);
1561 netdev_info(priv->dev, "device MAC address %pM\n",
1562 priv->dev->dev_addr);
1567 * stmmac_init_dma_engine - DMA init.
1568 * @priv: driver private structure
1570 * It inits the DMA invoking the specific MAC/GMAC callback.
1571 * Some DMA parameters can be passed from the platform;
1572 * in case of these are not passed a default is kept for the MAC or GMAC.
1574 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
1579 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) {
1580 dev_err(priv->device, "Invalid DMA configuration\n");
1584 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
1587 ret = priv->hw->dma->reset(priv->ioaddr);
1589 dev_err(priv->device, "Failed to reset the dma\n");
1593 priv->hw->dma->init(priv->ioaddr, priv->plat->dma_cfg,
1594 priv->dma_tx_phy, priv->dma_rx_phy, atds);
1596 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
1597 priv->rx_tail_addr = priv->dma_rx_phy +
1598 (DMA_RX_SIZE * sizeof(struct dma_desc));
1599 priv->hw->dma->set_rx_tail_ptr(priv->ioaddr, priv->rx_tail_addr,
1602 priv->tx_tail_addr = priv->dma_tx_phy +
1603 (DMA_TX_SIZE * sizeof(struct dma_desc));
1604 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr,
1608 if (priv->plat->axi && priv->hw->dma->axi)
1609 priv->hw->dma->axi(priv->ioaddr, priv->plat->axi);
1615 * stmmac_tx_timer - mitigation sw timer for tx.
1616 * @data: data pointer
1618 * This is the timer handler to directly invoke the stmmac_tx_clean.
1620 static void stmmac_tx_timer(unsigned long data)
1622 struct stmmac_priv *priv = (struct stmmac_priv *)data;
1624 stmmac_tx_clean(priv);
1628 * stmmac_init_tx_coalesce - init tx mitigation options.
1629 * @priv: driver private structure
1631 * This inits the transmit coalesce parameters: i.e. timer rate,
1632 * timer handler and default threshold used for enabling the
1633 * interrupt on completion bit.
1635 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
1637 priv->tx_coal_frames = STMMAC_TX_FRAMES;
1638 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
1639 init_timer(&priv->txtimer);
1640 priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
1641 priv->txtimer.data = (unsigned long)priv;
1642 priv->txtimer.function = stmmac_tx_timer;
1643 add_timer(&priv->txtimer);
1647 * stmmac_hw_setup - setup mac in a usable state.
1648 * @dev : pointer to the device structure.
1650 * this is the main function to setup the HW in a usable state because the
1651 * dma engine is reset, the core registers are configured (e.g. AXI,
1652 * Checksum features, timers). The DMA is ready to start receiving and
1655 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1658 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
1660 struct stmmac_priv *priv = netdev_priv(dev);
1663 /* DMA initialization and SW reset */
1664 ret = stmmac_init_dma_engine(priv);
1666 netdev_err(priv->dev, "%s: DMA engine initialization failed\n",
1671 /* Copy the MAC addr into the HW */
1672 priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0);
1674 /* If required, perform hw setup of the bus. */
1675 if (priv->plat->bus_setup)
1676 priv->plat->bus_setup(priv->ioaddr);
1678 /* PS and related bits will be programmed according to the speed */
1679 if (priv->hw->pcs) {
1680 int speed = priv->plat->mac_port_sel_speed;
1682 if ((speed == SPEED_10) || (speed == SPEED_100) ||
1683 (speed == SPEED_1000)) {
1684 priv->hw->ps = speed;
1686 dev_warn(priv->device, "invalid port speed\n");
1691 /* Initialize the MAC Core */
1692 priv->hw->mac->core_init(priv->hw, dev->mtu);
1694 ret = priv->hw->mac->rx_ipc(priv->hw);
1696 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n");
1697 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
1698 priv->hw->rx_csum = 0;
1701 /* Enable the MAC Rx/Tx */
1702 if (priv->synopsys_id >= DWMAC_CORE_4_00)
1703 stmmac_dwmac4_set_mac(priv->ioaddr, true);
1705 stmmac_set_mac(priv->ioaddr, true);
1707 /* Set the HW DMA mode and the COE */
1708 stmmac_dma_operation_mode(priv);
1710 stmmac_mmc_setup(priv);
1713 ret = stmmac_init_ptp(priv);
1715 netdev_warn(priv->dev, "fail to init PTP.\n");
1718 #ifdef CONFIG_DEBUG_FS
1719 ret = stmmac_init_fs(dev);
1721 netdev_warn(priv->dev, "%s: failed debugFS registration\n",
1724 /* Start the ball rolling... */
1725 netdev_dbg(priv->dev, "DMA RX/TX processes started...\n");
1726 priv->hw->dma->start_tx(priv->ioaddr);
1727 priv->hw->dma->start_rx(priv->ioaddr);
1729 /* Dump DMA/MAC registers */
1730 if (netif_msg_hw(priv)) {
1731 priv->hw->mac->dump_regs(priv->hw);
1732 priv->hw->dma->dump_regs(priv->ioaddr);
1734 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
1736 if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1737 priv->rx_riwt = MAX_DMA_RIWT;
1738 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
1741 if (priv->hw->pcs && priv->hw->mac->pcs_ctrl_ane)
1742 priv->hw->mac->pcs_ctrl_ane(priv->hw, 1, priv->hw->ps, 0);
1744 /* set TX ring length */
1745 if (priv->hw->dma->set_tx_ring_len)
1746 priv->hw->dma->set_tx_ring_len(priv->ioaddr,
1748 /* set RX ring length */
1749 if (priv->hw->dma->set_rx_ring_len)
1750 priv->hw->dma->set_rx_ring_len(priv->ioaddr,
1754 priv->hw->dma->enable_tso(priv->ioaddr, 1, STMMAC_CHAN0);
1760 * stmmac_open - open entry point of the driver
1761 * @dev : pointer to the device structure.
1763 * This function is the open entry point of the driver.
1765 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1768 static int stmmac_open(struct net_device *dev)
1770 struct stmmac_priv *priv = netdev_priv(dev);
1773 stmmac_check_ether_addr(priv);
1775 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
1776 priv->hw->pcs != STMMAC_PCS_TBI &&
1777 priv->hw->pcs != STMMAC_PCS_RTBI) {
1778 ret = stmmac_init_phy(dev);
1780 netdev_err(priv->dev,
1781 "%s: Cannot attach to PHY (error: %d)\n",
1787 /* Extra statistics */
1788 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1789 priv->xstats.threshold = tc;
1791 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1792 priv->rx_copybreak = STMMAC_RX_COPYBREAK;
1794 ret = alloc_dma_desc_resources(priv);
1796 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n",
1798 goto dma_desc_error;
1801 ret = init_dma_desc_rings(dev, GFP_KERNEL);
1803 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n",
1808 ret = stmmac_hw_setup(dev, true);
1810 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__);
1814 stmmac_init_tx_coalesce(priv);
1817 phy_start(dev->phydev);
1819 /* Request the IRQ lines */
1820 ret = request_irq(dev->irq, stmmac_interrupt,
1821 IRQF_SHARED, dev->name, dev);
1822 if (unlikely(ret < 0)) {
1823 netdev_err(priv->dev,
1824 "%s: ERROR: allocating the IRQ %d (error: %d)\n",
1825 __func__, dev->irq, ret);
1829 /* Request the Wake IRQ in case of another line is used for WoL */
1830 if (priv->wol_irq != dev->irq) {
1831 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1832 IRQF_SHARED, dev->name, dev);
1833 if (unlikely(ret < 0)) {
1834 netdev_err(priv->dev,
1835 "%s: ERROR: allocating the WoL IRQ %d (%d)\n",
1836 __func__, priv->wol_irq, ret);
1841 /* Request the IRQ lines */
1842 if (priv->lpi_irq > 0) {
1843 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1845 if (unlikely(ret < 0)) {
1846 netdev_err(priv->dev,
1847 "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1848 __func__, priv->lpi_irq, ret);
1853 napi_enable(&priv->napi);
1854 netif_start_queue(dev);
1859 if (priv->wol_irq != dev->irq)
1860 free_irq(priv->wol_irq, dev);
1862 free_irq(dev->irq, dev);
1865 free_dma_desc_resources(priv);
1868 phy_disconnect(dev->phydev);
1874 * stmmac_release - close entry point of the driver
1875 * @dev : device pointer.
1877 * This is the stop entry point of the driver.
1879 static int stmmac_release(struct net_device *dev)
1881 struct stmmac_priv *priv = netdev_priv(dev);
1883 if (priv->eee_enabled)
1884 del_timer_sync(&priv->eee_ctrl_timer);
1886 /* Stop and disconnect the PHY */
1888 phy_stop(dev->phydev);
1889 phy_disconnect(dev->phydev);
1892 netif_stop_queue(dev);
1894 napi_disable(&priv->napi);
1896 del_timer_sync(&priv->txtimer);
1898 /* Free the IRQ lines */
1899 free_irq(dev->irq, dev);
1900 if (priv->wol_irq != dev->irq)
1901 free_irq(priv->wol_irq, dev);
1902 if (priv->lpi_irq > 0)
1903 free_irq(priv->lpi_irq, dev);
1905 /* Stop TX/RX DMA and clear the descriptors */
1906 priv->hw->dma->stop_tx(priv->ioaddr);
1907 priv->hw->dma->stop_rx(priv->ioaddr);
1909 /* Release and free the Rx/Tx resources */
1910 free_dma_desc_resources(priv);
1912 /* Disable the MAC Rx/Tx */
1913 stmmac_set_mac(priv->ioaddr, false);
1915 netif_carrier_off(dev);
1917 #ifdef CONFIG_DEBUG_FS
1918 stmmac_exit_fs(dev);
1921 stmmac_release_ptp(priv);
1927 * stmmac_tso_allocator - close entry point of the driver
1928 * @priv: driver private structure
1929 * @des: buffer start address
1930 * @total_len: total length to fill in descriptors
1931 * @last_segmant: condition for the last descriptor
1933 * This function fills descriptor and request new descriptors according to
1934 * buffer length to fill
1936 static void stmmac_tso_allocator(struct stmmac_priv *priv, unsigned int des,
1937 int total_len, bool last_segment)
1939 struct dma_desc *desc;
1943 tmp_len = total_len;
1945 while (tmp_len > 0) {
1946 priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE);
1947 desc = priv->dma_tx + priv->cur_tx;
1949 desc->des0 = cpu_to_le32(des + (total_len - tmp_len));
1950 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?
1951 TSO_MAX_BUFF_SIZE : tmp_len;
1953 priv->hw->desc->prepare_tso_tx_desc(desc, 0, buff_size,
1955 (last_segment) && (buff_size < TSO_MAX_BUFF_SIZE),
1958 tmp_len -= TSO_MAX_BUFF_SIZE;
1963 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
1964 * @skb : the socket buffer
1965 * @dev : device pointer
1966 * Description: this is the transmit function that is called on TSO frames
1967 * (support available on GMAC4 and newer chips).
1968 * Diagram below show the ring programming in case of TSO frames:
1972 * | DES0 |---> buffer1 = L2/L3/L4 header
1973 * | DES1 |---> TCP Payload (can continue on next descr...)
1974 * | DES2 |---> buffer 1 and 2 len
1975 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
1981 * | DES0 | --| Split TCP Payload on Buffers 1 and 2
1983 * | DES2 | --> buffer 1 and 2 len
1987 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
1989 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
1992 int tmp_pay_len = 0;
1993 struct stmmac_priv *priv = netdev_priv(dev);
1994 int nfrags = skb_shinfo(skb)->nr_frags;
1995 unsigned int first_entry, des;
1996 struct dma_desc *desc, *first, *mss_desc = NULL;
2000 /* Compute header lengths */
2001 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2003 /* Desc availability based on threshold should be enough safe */
2004 if (unlikely(stmmac_tx_avail(priv) <
2005 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) {
2006 if (!netif_queue_stopped(dev)) {
2007 netif_stop_queue(dev);
2008 /* This is a hard error, log it. */
2009 netdev_err(priv->dev,
2010 "%s: Tx Ring full when queue awake\n",
2013 return NETDEV_TX_BUSY;
2016 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */
2018 mss = skb_shinfo(skb)->gso_size;
2020 /* set new MSS value if needed */
2021 if (mss != priv->mss) {
2022 mss_desc = priv->dma_tx + priv->cur_tx;
2023 priv->hw->desc->set_mss(mss_desc, mss);
2025 priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE);
2028 if (netif_msg_tx_queued(priv)) {
2029 pr_info("%s: tcphdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
2030 __func__, tcp_hdrlen(skb), proto_hdr_len, pay_len, mss);
2031 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len,
2035 first_entry = priv->cur_tx;
2037 desc = priv->dma_tx + first_entry;
2040 /* first descriptor: fill Headers on Buf1 */
2041 des = dma_map_single(priv->device, skb->data, skb_headlen(skb),
2043 if (dma_mapping_error(priv->device, des))
2046 priv->tx_skbuff_dma[first_entry].buf = des;
2047 priv->tx_skbuff_dma[first_entry].len = skb_headlen(skb);
2048 priv->tx_skbuff[first_entry] = skb;
2050 first->des0 = cpu_to_le32(des);
2052 /* Fill start of payload in buff2 of first descriptor */
2054 first->des1 = cpu_to_le32(des + proto_hdr_len);
2056 /* If needed take extra descriptors to fill the remaining payload */
2057 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE;
2059 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0));
2061 /* Prepare fragments */
2062 for (i = 0; i < nfrags; i++) {
2063 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2065 des = skb_frag_dma_map(priv->device, frag, 0,
2066 skb_frag_size(frag),
2069 stmmac_tso_allocator(priv, des, skb_frag_size(frag),
2072 priv->tx_skbuff_dma[priv->cur_tx].buf = des;
2073 priv->tx_skbuff_dma[priv->cur_tx].len = skb_frag_size(frag);
2074 priv->tx_skbuff[priv->cur_tx] = NULL;
2075 priv->tx_skbuff_dma[priv->cur_tx].map_as_page = true;
2078 priv->tx_skbuff_dma[priv->cur_tx].last_segment = true;
2080 priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE);
2082 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
2083 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
2085 netif_stop_queue(dev);
2088 dev->stats.tx_bytes += skb->len;
2089 priv->xstats.tx_tso_frames++;
2090 priv->xstats.tx_tso_nfrags += nfrags;
2092 /* Manage tx mitigation */
2093 priv->tx_count_frames += nfrags + 1;
2094 if (likely(priv->tx_coal_frames > priv->tx_count_frames)) {
2095 mod_timer(&priv->txtimer,
2096 STMMAC_COAL_TIMER(priv->tx_coal_timer));
2098 priv->tx_count_frames = 0;
2099 priv->hw->desc->set_tx_ic(desc);
2100 priv->xstats.tx_set_ic_bit++;
2103 if (!priv->hwts_tx_en)
2104 skb_tx_timestamp(skb);
2106 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2107 priv->hwts_tx_en)) {
2108 /* declare that device is doing timestamping */
2109 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2110 priv->hw->desc->enable_tx_timestamp(first);
2113 /* Complete the first descriptor before granting the DMA */
2114 priv->hw->desc->prepare_tso_tx_desc(first, 1,
2117 1, priv->tx_skbuff_dma[first_entry].last_segment,
2118 tcp_hdrlen(skb) / 4, (skb->len - proto_hdr_len));
2120 /* If context desc is used to change MSS */
2122 priv->hw->desc->set_tx_owner(mss_desc);
2124 /* The own bit must be the latest setting done when prepare the
2125 * descriptor and then barrier is needed to make sure that
2126 * all is coherent before granting the DMA engine.
2130 if (netif_msg_pktdata(priv)) {
2131 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
2132 __func__, priv->cur_tx, priv->dirty_tx, first_entry,
2133 priv->cur_tx, first, nfrags);
2135 priv->hw->desc->display_ring((void *)priv->dma_tx, DMA_TX_SIZE,
2138 pr_info(">>> frame to be transmitted: ");
2139 print_pkt(skb->data, skb_headlen(skb));
2142 netdev_sent_queue(dev, skb->len);
2144 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr,
2147 return NETDEV_TX_OK;
2150 dev_err(priv->device, "Tx dma map failed\n");
2152 priv->dev->stats.tx_dropped++;
2153 return NETDEV_TX_OK;
2157 * stmmac_xmit - Tx entry point of the driver
2158 * @skb : the socket buffer
2159 * @dev : device pointer
2160 * Description : this is the tx entry point of the driver.
2161 * It programs the chain or the ring and supports oversized frames
2164 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
2166 struct stmmac_priv *priv = netdev_priv(dev);
2167 unsigned int nopaged_len = skb_headlen(skb);
2168 int i, csum_insertion = 0, is_jumbo = 0;
2169 int nfrags = skb_shinfo(skb)->nr_frags;
2170 unsigned int entry, first_entry;
2171 struct dma_desc *desc, *first;
2172 unsigned int enh_desc;
2175 /* Manage oversized TCP frames for GMAC4 device */
2176 if (skb_is_gso(skb) && priv->tso) {
2177 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2178 return stmmac_tso_xmit(skb, dev);
2181 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
2182 if (!netif_queue_stopped(dev)) {
2183 netif_stop_queue(dev);
2184 /* This is a hard error, log it. */
2185 netdev_err(priv->dev,
2186 "%s: Tx Ring full when queue awake\n",
2189 return NETDEV_TX_BUSY;
2192 if (priv->tx_path_in_lpi_mode)
2193 stmmac_disable_eee_mode(priv);
2195 entry = priv->cur_tx;
2196 first_entry = entry;
2198 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
2200 if (likely(priv->extend_desc))
2201 desc = (struct dma_desc *)(priv->dma_etx + entry);
2203 desc = priv->dma_tx + entry;
2207 priv->tx_skbuff[first_entry] = skb;
2209 enh_desc = priv->plat->enh_desc;
2210 /* To program the descriptors according to the size of the frame */
2212 is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc);
2214 if (unlikely(is_jumbo) && likely(priv->synopsys_id <
2216 entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion);
2217 if (unlikely(entry < 0))
2221 for (i = 0; i < nfrags; i++) {
2222 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2223 int len = skb_frag_size(frag);
2224 bool last_segment = (i == (nfrags - 1));
2226 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
2228 if (likely(priv->extend_desc))
2229 desc = (struct dma_desc *)(priv->dma_etx + entry);
2231 desc = priv->dma_tx + entry;
2233 des = skb_frag_dma_map(priv->device, frag, 0, len,
2235 if (dma_mapping_error(priv->device, des))
2236 goto dma_map_err; /* should reuse desc w/o issues */
2238 priv->tx_skbuff[entry] = NULL;
2240 priv->tx_skbuff_dma[entry].buf = des;
2241 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
2242 desc->des0 = cpu_to_le32(des);
2244 desc->des2 = cpu_to_le32(des);
2246 priv->tx_skbuff_dma[entry].map_as_page = true;
2247 priv->tx_skbuff_dma[entry].len = len;
2248 priv->tx_skbuff_dma[entry].last_segment = last_segment;
2250 /* Prepare the descriptor and set the own bit too */
2251 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
2252 priv->mode, 1, last_segment);
2255 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
2257 priv->cur_tx = entry;
2259 if (netif_msg_pktdata(priv)) {
2262 netdev_dbg(priv->dev,
2263 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
2264 __func__, priv->cur_tx, priv->dirty_tx, first_entry,
2265 entry, first, nfrags);
2267 if (priv->extend_desc)
2268 tx_head = (void *)priv->dma_etx;
2270 tx_head = (void *)priv->dma_tx;
2272 priv->hw->desc->display_ring(tx_head, DMA_TX_SIZE, false);
2274 netdev_dbg(priv->dev, ">>> frame to be transmitted: ");
2275 print_pkt(skb->data, skb->len);
2278 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
2279 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
2281 netif_stop_queue(dev);
2284 dev->stats.tx_bytes += skb->len;
2286 /* According to the coalesce parameter the IC bit for the latest
2287 * segment is reset and the timer re-started to clean the tx status.
2288 * This approach takes care about the fragments: desc is the first
2289 * element in case of no SG.
2291 priv->tx_count_frames += nfrags + 1;
2292 if (likely(priv->tx_coal_frames > priv->tx_count_frames)) {
2293 mod_timer(&priv->txtimer,
2294 STMMAC_COAL_TIMER(priv->tx_coal_timer));
2296 priv->tx_count_frames = 0;
2297 priv->hw->desc->set_tx_ic(desc);
2298 priv->xstats.tx_set_ic_bit++;
2301 if (!priv->hwts_tx_en)
2302 skb_tx_timestamp(skb);
2304 /* Ready to fill the first descriptor and set the OWN bit w/o any
2305 * problems because all the descriptors are actually ready to be
2306 * passed to the DMA engine.
2308 if (likely(!is_jumbo)) {
2309 bool last_segment = (nfrags == 0);
2311 des = dma_map_single(priv->device, skb->data,
2312 nopaged_len, DMA_TO_DEVICE);
2313 if (dma_mapping_error(priv->device, des))
2316 priv->tx_skbuff_dma[first_entry].buf = des;
2317 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
2318 first->des0 = cpu_to_le32(des);
2320 first->des2 = cpu_to_le32(des);
2322 priv->tx_skbuff_dma[first_entry].len = nopaged_len;
2323 priv->tx_skbuff_dma[first_entry].last_segment = last_segment;
2325 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2326 priv->hwts_tx_en)) {
2327 /* declare that device is doing timestamping */
2328 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2329 priv->hw->desc->enable_tx_timestamp(first);
2332 /* Prepare the first descriptor setting the OWN bit too */
2333 priv->hw->desc->prepare_tx_desc(first, 1, nopaged_len,
2334 csum_insertion, priv->mode, 1,
2337 /* The own bit must be the latest setting done when prepare the
2338 * descriptor and then barrier is needed to make sure that
2339 * all is coherent before granting the DMA engine.
2344 netdev_sent_queue(dev, skb->len);
2346 if (priv->synopsys_id < DWMAC_CORE_4_00)
2347 priv->hw->dma->enable_dma_transmission(priv->ioaddr);
2349 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr,
2352 return NETDEV_TX_OK;
2355 netdev_err(priv->dev, "Tx DMA map failed\n");
2357 priv->dev->stats.tx_dropped++;
2358 return NETDEV_TX_OK;
2361 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
2363 struct ethhdr *ehdr;
2366 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) ==
2367 NETIF_F_HW_VLAN_CTAG_RX &&
2368 !__vlan_get_tag(skb, &vlanid)) {
2369 /* pop the vlan tag */
2370 ehdr = (struct ethhdr *)skb->data;
2371 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
2372 skb_pull(skb, VLAN_HLEN);
2373 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
2378 static inline int stmmac_rx_threshold_count(struct stmmac_priv *priv)
2380 if (priv->rx_zeroc_thresh < STMMAC_RX_THRESH)
2387 * stmmac_rx_refill - refill used skb preallocated buffers
2388 * @priv: driver private structure
2389 * Description : this is to reallocate the skb for the reception process
2390 * that is based on zero-copy.
2392 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
2394 int bfsize = priv->dma_buf_sz;
2395 unsigned int entry = priv->dirty_rx;
2396 int dirty = stmmac_rx_dirty(priv);
2398 while (dirty-- > 0) {
2401 if (priv->extend_desc)
2402 p = (struct dma_desc *)(priv->dma_erx + entry);
2404 p = priv->dma_rx + entry;
2406 if (likely(priv->rx_skbuff[entry] == NULL)) {
2407 struct sk_buff *skb;
2409 skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
2410 if (unlikely(!skb)) {
2411 /* so for a while no zero-copy! */
2412 priv->rx_zeroc_thresh = STMMAC_RX_THRESH;
2413 if (unlikely(net_ratelimit()))
2414 dev_err(priv->device,
2415 "fail to alloc skb entry %d\n",
2420 priv->rx_skbuff[entry] = skb;
2421 priv->rx_skbuff_dma[entry] =
2422 dma_map_single(priv->device, skb->data, bfsize,
2424 if (dma_mapping_error(priv->device,
2425 priv->rx_skbuff_dma[entry])) {
2426 netdev_err(priv->dev, "Rx DMA map failed\n");
2431 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) {
2432 p->des0 = cpu_to_le32(priv->rx_skbuff_dma[entry]);
2435 p->des2 = cpu_to_le32(priv->rx_skbuff_dma[entry]);
2437 if (priv->hw->mode->refill_desc3)
2438 priv->hw->mode->refill_desc3(priv, p);
2440 if (priv->rx_zeroc_thresh > 0)
2441 priv->rx_zeroc_thresh--;
2443 netif_dbg(priv, rx_status, priv->dev,
2444 "refill entry #%d\n", entry);
2448 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
2449 priv->hw->desc->init_rx_desc(p, priv->use_riwt, 0, 0);
2451 priv->hw->desc->set_rx_owner(p);
2455 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE);
2457 priv->dirty_rx = entry;
2461 * stmmac_rx - manage the receive process
2462 * @priv: driver private structure
2463 * @limit: napi bugget.
2464 * Description : this the function called by the napi poll method.
2465 * It gets all the frames inside the ring.
2467 static int stmmac_rx(struct stmmac_priv *priv, int limit)
2469 unsigned int entry = priv->cur_rx;
2470 unsigned int next_entry;
2471 unsigned int count = 0;
2472 int coe = priv->hw->rx_csum;
2474 if (netif_msg_rx_status(priv)) {
2477 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
2478 if (priv->extend_desc)
2479 rx_head = (void *)priv->dma_erx;
2481 rx_head = (void *)priv->dma_rx;
2483 priv->hw->desc->display_ring(rx_head, DMA_RX_SIZE, true);
2485 while (count < limit) {
2488 struct dma_desc *np;
2490 if (priv->extend_desc)
2491 p = (struct dma_desc *)(priv->dma_erx + entry);
2493 p = priv->dma_rx + entry;
2495 /* read the status of the incoming frame */
2496 status = priv->hw->desc->rx_status(&priv->dev->stats,
2498 /* check if managed by the DMA otherwise go ahead */
2499 if (unlikely(status & dma_own))
2504 priv->cur_rx = STMMAC_GET_ENTRY(priv->cur_rx, DMA_RX_SIZE);
2505 next_entry = priv->cur_rx;
2507 if (priv->extend_desc)
2508 np = (struct dma_desc *)(priv->dma_erx + next_entry);
2510 np = priv->dma_rx + next_entry;
2514 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
2515 priv->hw->desc->rx_extended_status(&priv->dev->stats,
2519 if (unlikely(status == discard_frame)) {
2520 priv->dev->stats.rx_errors++;
2521 if (priv->hwts_rx_en && !priv->extend_desc) {
2522 /* DESC2 & DESC3 will be overwitten by device
2523 * with timestamp value, hence reinitialize
2524 * them in stmmac_rx_refill() function so that
2525 * device can reuse it.
2527 priv->rx_skbuff[entry] = NULL;
2528 dma_unmap_single(priv->device,
2529 priv->rx_skbuff_dma[entry],
2534 struct sk_buff *skb;
2538 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
2539 des = le32_to_cpu(p->des0);
2541 des = le32_to_cpu(p->des2);
2543 frame_len = priv->hw->desc->get_rx_frame_len(p, coe);
2545 /* If frame length is greather than skb buffer size
2546 * (preallocated during init) then the packet is
2549 if (frame_len > priv->dma_buf_sz) {
2550 netdev_err(priv->dev,
2551 "len %d larger than size (%d)\n",
2552 frame_len, priv->dma_buf_sz);
2553 priv->dev->stats.rx_length_errors++;
2557 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
2558 * Type frames (LLC/LLC-SNAP)
2560 if (unlikely(status != llc_snap))
2561 frame_len -= ETH_FCS_LEN;
2563 if (netif_msg_rx_status(priv)) {
2564 netdev_dbg(priv->dev, "\tdesc: %p [entry %d] buff=0x%x\n",
2566 if (frame_len > ETH_FRAME_LEN)
2567 netdev_dbg(priv->dev, "frame size %d, COE: %d\n",
2571 /* The zero-copy is always used for all the sizes
2572 * in case of GMAC4 because it needs
2573 * to refill the used descriptors, always.
2575 if (unlikely(!priv->plat->has_gmac4 &&
2576 ((frame_len < priv->rx_copybreak) ||
2577 stmmac_rx_threshold_count(priv)))) {
2578 skb = netdev_alloc_skb_ip_align(priv->dev,
2580 if (unlikely(!skb)) {
2581 if (net_ratelimit())
2582 dev_warn(priv->device,
2583 "packet dropped\n");
2584 priv->dev->stats.rx_dropped++;
2588 dma_sync_single_for_cpu(priv->device,
2592 skb_copy_to_linear_data(skb,
2594 rx_skbuff[entry]->data,
2597 skb_put(skb, frame_len);
2598 dma_sync_single_for_device(priv->device,
2603 skb = priv->rx_skbuff[entry];
2604 if (unlikely(!skb)) {
2605 netdev_err(priv->dev,
2606 "%s: Inconsistent Rx chain\n",
2608 priv->dev->stats.rx_dropped++;
2611 prefetch(skb->data - NET_IP_ALIGN);
2612 priv->rx_skbuff[entry] = NULL;
2613 priv->rx_zeroc_thresh++;
2615 skb_put(skb, frame_len);
2616 dma_unmap_single(priv->device,
2617 priv->rx_skbuff_dma[entry],
2622 if (netif_msg_pktdata(priv)) {
2623 netdev_dbg(priv->dev, "frame received (%dbytes)",
2625 print_pkt(skb->data, frame_len);
2628 stmmac_get_rx_hwtstamp(priv, p, np, skb);
2630 stmmac_rx_vlan(priv->dev, skb);
2632 skb->protocol = eth_type_trans(skb, priv->dev);
2635 skb_checksum_none_assert(skb);
2637 skb->ip_summed = CHECKSUM_UNNECESSARY;
2639 napi_gro_receive(&priv->napi, skb);
2641 priv->dev->stats.rx_packets++;
2642 priv->dev->stats.rx_bytes += frame_len;
2647 stmmac_rx_refill(priv);
2649 priv->xstats.rx_pkt_n += count;
2655 * stmmac_poll - stmmac poll method (NAPI)
2656 * @napi : pointer to the napi structure.
2657 * @budget : maximum number of packets that the current CPU can receive from
2660 * To look at the incoming frames and clear the tx resources.
2662 static int stmmac_poll(struct napi_struct *napi, int budget)
2664 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
2667 priv->xstats.napi_poll++;
2668 stmmac_tx_clean(priv);
2670 work_done = stmmac_rx(priv, budget);
2671 if (work_done < budget) {
2672 napi_complete(napi);
2673 stmmac_enable_dma_irq(priv);
2680 * @dev : Pointer to net device structure
2681 * Description: this function is called when a packet transmission fails to
2682 * complete within a reasonable time. The driver will mark the error in the
2683 * netdev structure and arrange for the device to be reset to a sane state
2684 * in order to transmit a new packet.
2686 static void stmmac_tx_timeout(struct net_device *dev)
2688 struct stmmac_priv *priv = netdev_priv(dev);
2690 /* Clear Tx resources and restart transmitting again */
2691 stmmac_tx_err(priv);
2695 * stmmac_set_rx_mode - entry point for multicast addressing
2696 * @dev : pointer to the device structure
2698 * This function is a driver entry point which gets called by the kernel
2699 * whenever multicast addresses must be enabled/disabled.
2703 static void stmmac_set_rx_mode(struct net_device *dev)
2705 struct stmmac_priv *priv = netdev_priv(dev);
2707 priv->hw->mac->set_filter(priv->hw, dev);
2711 * stmmac_change_mtu - entry point to change MTU size for the device.
2712 * @dev : device pointer.
2713 * @new_mtu : the new MTU size for the device.
2714 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
2715 * to drive packet transmission. Ethernet has an MTU of 1500 octets
2716 * (ETH_DATA_LEN). This value can be changed with ifconfig.
2718 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2721 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
2723 struct stmmac_priv *priv = netdev_priv(dev);
2725 if (netif_running(dev)) {
2726 netdev_err(priv->dev, "must be stopped to change its MTU\n");
2732 netdev_update_features(dev);
2737 static netdev_features_t stmmac_fix_features(struct net_device *dev,
2738 netdev_features_t features)
2740 struct stmmac_priv *priv = netdev_priv(dev);
2742 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
2743 features &= ~NETIF_F_RXCSUM;
2745 if (!priv->plat->tx_coe)
2746 features &= ~NETIF_F_CSUM_MASK;
2748 /* Some GMAC devices have a bugged Jumbo frame support that
2749 * needs to have the Tx COE disabled for oversized frames
2750 * (due to limited buffer sizes). In this case we disable
2751 * the TX csum insertionin the TDES and not use SF.
2753 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
2754 features &= ~NETIF_F_CSUM_MASK;
2756 /* Disable tso if asked by ethtool */
2757 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
2758 if (features & NETIF_F_TSO)
2767 static int stmmac_set_features(struct net_device *netdev,
2768 netdev_features_t features)
2770 struct stmmac_priv *priv = netdev_priv(netdev);
2772 /* Keep the COE Type in case of csum is supporting */
2773 if (features & NETIF_F_RXCSUM)
2774 priv->hw->rx_csum = priv->plat->rx_coe;
2776 priv->hw->rx_csum = 0;
2777 /* No check needed because rx_coe has been set before and it will be
2778 * fixed in case of issue.
2780 priv->hw->mac->rx_ipc(priv->hw);
2786 * stmmac_interrupt - main ISR
2787 * @irq: interrupt number.
2788 * @dev_id: to pass the net device pointer.
2789 * Description: this is the main driver interrupt service routine.
2791 * o DMA service routine (to manage incoming frame reception and transmission
2793 * o Core interrupts to manage: remote wake-up, management counter, LPI
2796 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
2798 struct net_device *dev = (struct net_device *)dev_id;
2799 struct stmmac_priv *priv = netdev_priv(dev);
2802 pm_wakeup_event(priv->device, 0);
2804 if (unlikely(!dev)) {
2805 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
2809 /* To handle GMAC own interrupts */
2810 if ((priv->plat->has_gmac) || (priv->plat->has_gmac4)) {
2811 int status = priv->hw->mac->host_irq_status(priv->hw,
2813 if (unlikely(status)) {
2814 /* For LPI we need to save the tx status */
2815 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
2816 priv->tx_path_in_lpi_mode = true;
2817 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
2818 priv->tx_path_in_lpi_mode = false;
2819 if (status & CORE_IRQ_MTL_RX_OVERFLOW && priv->hw->dma->set_rx_tail_ptr)
2820 priv->hw->dma->set_rx_tail_ptr(priv->ioaddr,
2825 /* PCS link status */
2826 if (priv->hw->pcs) {
2827 if (priv->xstats.pcs_link)
2828 netif_carrier_on(dev);
2830 netif_carrier_off(dev);
2834 /* To handle DMA interrupts */
2835 stmmac_dma_interrupt(priv);
2840 #ifdef CONFIG_NET_POLL_CONTROLLER
2841 /* Polling receive - used by NETCONSOLE and other diagnostic tools
2842 * to allow network I/O with interrupts disabled.
2844 static void stmmac_poll_controller(struct net_device *dev)
2846 disable_irq(dev->irq);
2847 stmmac_interrupt(dev->irq, dev);
2848 enable_irq(dev->irq);
2853 * stmmac_ioctl - Entry point for the Ioctl
2854 * @dev: Device pointer.
2855 * @rq: An IOCTL specefic structure, that can contain a pointer to
2856 * a proprietary structure used to pass information to the driver.
2857 * @cmd: IOCTL command
2859 * Currently it supports the phy_mii_ioctl(...) and HW time stamping.
2861 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2863 int ret = -EOPNOTSUPP;
2865 if (!netif_running(dev))
2874 ret = phy_mii_ioctl(dev->phydev, rq, cmd);
2877 ret = stmmac_hwtstamp_ioctl(dev, rq);
2886 #ifdef CONFIG_DEBUG_FS
2887 static struct dentry *stmmac_fs_dir;
2889 static void sysfs_display_ring(void *head, int size, int extend_desc,
2890 struct seq_file *seq)
2893 struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
2894 struct dma_desc *p = (struct dma_desc *)head;
2896 for (i = 0; i < size; i++) {
2900 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2901 i, (unsigned int)virt_to_phys(ep),
2902 le32_to_cpu(ep->basic.des0),
2903 le32_to_cpu(ep->basic.des1),
2904 le32_to_cpu(ep->basic.des2),
2905 le32_to_cpu(ep->basic.des3));
2909 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2910 i, (unsigned int)virt_to_phys(ep),
2911 le32_to_cpu(p->des0), le32_to_cpu(p->des1),
2912 le32_to_cpu(p->des2), le32_to_cpu(p->des3));
2915 seq_printf(seq, "\n");
2919 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
2921 struct net_device *dev = seq->private;
2922 struct stmmac_priv *priv = netdev_priv(dev);
2924 if (priv->extend_desc) {
2925 seq_printf(seq, "Extended RX descriptor ring:\n");
2926 sysfs_display_ring((void *)priv->dma_erx, DMA_RX_SIZE, 1, seq);
2927 seq_printf(seq, "Extended TX descriptor ring:\n");
2928 sysfs_display_ring((void *)priv->dma_etx, DMA_TX_SIZE, 1, seq);
2930 seq_printf(seq, "RX descriptor ring:\n");
2931 sysfs_display_ring((void *)priv->dma_rx, DMA_RX_SIZE, 0, seq);
2932 seq_printf(seq, "TX descriptor ring:\n");
2933 sysfs_display_ring((void *)priv->dma_tx, DMA_TX_SIZE, 0, seq);
2939 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
2941 return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
2944 /* Debugfs files, should appear in /sys/kernel/debug/stmmaceth/eth0 */
2946 static const struct file_operations stmmac_rings_status_fops = {
2947 .owner = THIS_MODULE,
2948 .open = stmmac_sysfs_ring_open,
2950 .llseek = seq_lseek,
2951 .release = single_release,
2954 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
2956 struct net_device *dev = seq->private;
2957 struct stmmac_priv *priv = netdev_priv(dev);
2959 if (!priv->hw_cap_support) {
2960 seq_printf(seq, "DMA HW features not supported\n");
2964 seq_printf(seq, "==============================\n");
2965 seq_printf(seq, "\tDMA HW features\n");
2966 seq_printf(seq, "==============================\n");
2968 seq_printf(seq, "\t10/100 Mbps: %s\n",
2969 (priv->dma_cap.mbps_10_100) ? "Y" : "N");
2970 seq_printf(seq, "\t1000 Mbps: %s\n",
2971 (priv->dma_cap.mbps_1000) ? "Y" : "N");
2972 seq_printf(seq, "\tHalf duplex: %s\n",
2973 (priv->dma_cap.half_duplex) ? "Y" : "N");
2974 seq_printf(seq, "\tHash Filter: %s\n",
2975 (priv->dma_cap.hash_filter) ? "Y" : "N");
2976 seq_printf(seq, "\tMultiple MAC address registers: %s\n",
2977 (priv->dma_cap.multi_addr) ? "Y" : "N");
2978 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
2979 (priv->dma_cap.pcs) ? "Y" : "N");
2980 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
2981 (priv->dma_cap.sma_mdio) ? "Y" : "N");
2982 seq_printf(seq, "\tPMT Remote wake up: %s\n",
2983 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
2984 seq_printf(seq, "\tPMT Magic Frame: %s\n",
2985 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
2986 seq_printf(seq, "\tRMON module: %s\n",
2987 (priv->dma_cap.rmon) ? "Y" : "N");
2988 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
2989 (priv->dma_cap.time_stamp) ? "Y" : "N");
2990 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n",
2991 (priv->dma_cap.atime_stamp) ? "Y" : "N");
2992 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n",
2993 (priv->dma_cap.eee) ? "Y" : "N");
2994 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
2995 seq_printf(seq, "\tChecksum Offload in TX: %s\n",
2996 (priv->dma_cap.tx_coe) ? "Y" : "N");
2997 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
2998 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n",
2999 (priv->dma_cap.rx_coe) ? "Y" : "N");
3001 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
3002 (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
3003 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
3004 (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
3006 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
3007 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
3008 seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
3009 priv->dma_cap.number_rx_channel);
3010 seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
3011 priv->dma_cap.number_tx_channel);
3012 seq_printf(seq, "\tEnhanced descriptors: %s\n",
3013 (priv->dma_cap.enh_desc) ? "Y" : "N");
3018 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
3020 return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
3023 static const struct file_operations stmmac_dma_cap_fops = {
3024 .owner = THIS_MODULE,
3025 .open = stmmac_sysfs_dma_cap_open,
3027 .llseek = seq_lseek,
3028 .release = single_release,
3031 static int stmmac_init_fs(struct net_device *dev)
3033 struct stmmac_priv *priv = netdev_priv(dev);
3035 /* Create per netdev entries */
3036 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
3038 if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) {
3039 netdev_err(priv->dev, "ERROR failed to create debugfs directory\n");
3044 /* Entry to report DMA RX/TX rings */
3045 priv->dbgfs_rings_status =
3046 debugfs_create_file("descriptors_status", S_IRUGO,
3047 priv->dbgfs_dir, dev,
3048 &stmmac_rings_status_fops);
3050 if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) {
3051 netdev_err(priv->dev, "ERROR creating stmmac ring debugfs file\n");
3052 debugfs_remove_recursive(priv->dbgfs_dir);
3057 /* Entry to report the DMA HW features */
3058 priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", S_IRUGO,
3060 dev, &stmmac_dma_cap_fops);
3062 if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) {
3063 netdev_err(priv->dev, "ERROR creating stmmac MMC debugfs file\n");
3064 debugfs_remove_recursive(priv->dbgfs_dir);
3072 static void stmmac_exit_fs(struct net_device *dev)
3074 struct stmmac_priv *priv = netdev_priv(dev);
3076 debugfs_remove_recursive(priv->dbgfs_dir);
3078 #endif /* CONFIG_DEBUG_FS */
3080 static const struct net_device_ops stmmac_netdev_ops = {
3081 .ndo_open = stmmac_open,
3082 .ndo_start_xmit = stmmac_xmit,
3083 .ndo_stop = stmmac_release,
3084 .ndo_change_mtu = stmmac_change_mtu,
3085 .ndo_fix_features = stmmac_fix_features,
3086 .ndo_set_features = stmmac_set_features,
3087 .ndo_set_rx_mode = stmmac_set_rx_mode,
3088 .ndo_tx_timeout = stmmac_tx_timeout,
3089 .ndo_do_ioctl = stmmac_ioctl,
3090 #ifdef CONFIG_NET_POLL_CONTROLLER
3091 .ndo_poll_controller = stmmac_poll_controller,
3093 .ndo_set_mac_address = eth_mac_addr,
3097 * stmmac_hw_init - Init the MAC device
3098 * @priv: driver private structure
3099 * Description: this function is to configure the MAC device according to
3100 * some platform parameters or the HW capability register. It prepares the
3101 * driver to use either ring or chain modes and to setup either enhanced or
3102 * normal descriptors.
3104 static int stmmac_hw_init(struct stmmac_priv *priv)
3106 struct mac_device_info *mac;
3108 /* Identify the MAC HW device */
3109 if (priv->plat->has_gmac) {
3110 priv->dev->priv_flags |= IFF_UNICAST_FLT;
3111 mac = dwmac1000_setup(priv->ioaddr,
3112 priv->plat->multicast_filter_bins,
3113 priv->plat->unicast_filter_entries,
3114 &priv->synopsys_id);
3115 } else if (priv->plat->has_gmac4) {
3116 priv->dev->priv_flags |= IFF_UNICAST_FLT;
3117 mac = dwmac4_setup(priv->ioaddr,
3118 priv->plat->multicast_filter_bins,
3119 priv->plat->unicast_filter_entries,
3120 &priv->synopsys_id);
3122 mac = dwmac100_setup(priv->ioaddr, &priv->synopsys_id);
3129 /* To use the chained or ring mode */
3130 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
3131 priv->hw->mode = &dwmac4_ring_mode_ops;
3134 priv->hw->mode = &chain_mode_ops;
3135 dev_info(priv->device, "Chain mode enabled\n");
3136 priv->mode = STMMAC_CHAIN_MODE;
3138 priv->hw->mode = &ring_mode_ops;
3139 dev_info(priv->device, "Ring mode enabled\n");
3140 priv->mode = STMMAC_RING_MODE;
3144 /* Get the HW capability (new GMAC newer than 3.50a) */
3145 priv->hw_cap_support = stmmac_get_hw_features(priv);
3146 if (priv->hw_cap_support) {
3147 dev_info(priv->device, "DMA HW capability register supported\n");
3149 /* We can override some gmac/dma configuration fields: e.g.
3150 * enh_desc, tx_coe (e.g. that are passed through the
3151 * platform) with the values from the HW capability
3152 * register (if supported).
3154 priv->plat->enh_desc = priv->dma_cap.enh_desc;
3155 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
3156 priv->hw->pmt = priv->plat->pmt;
3158 /* TXCOE doesn't work in thresh DMA mode */
3159 if (priv->plat->force_thresh_dma_mode)
3160 priv->plat->tx_coe = 0;
3162 priv->plat->tx_coe = priv->dma_cap.tx_coe;
3164 /* In case of GMAC4 rx_coe is from HW cap register. */
3165 priv->plat->rx_coe = priv->dma_cap.rx_coe;
3167 if (priv->dma_cap.rx_coe_type2)
3168 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
3169 else if (priv->dma_cap.rx_coe_type1)
3170 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
3173 dev_info(priv->device, "No HW DMA feature register supported\n");
3176 /* To use alternate (extended), normal or GMAC4 descriptor structures */
3177 if (priv->synopsys_id >= DWMAC_CORE_4_00)
3178 priv->hw->desc = &dwmac4_desc_ops;
3180 stmmac_selec_desc_mode(priv);
3182 if (priv->plat->rx_coe) {
3183 priv->hw->rx_csum = priv->plat->rx_coe;
3184 dev_info(priv->device, "RX Checksum Offload Engine supported\n");
3185 if (priv->synopsys_id < DWMAC_CORE_4_00)
3186 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum);
3188 if (priv->plat->tx_coe)
3189 dev_info(priv->device, "TX Checksum insertion supported\n");
3191 if (priv->plat->pmt) {
3192 dev_info(priv->device, "Wake-Up On Lan supported\n");
3193 device_set_wakeup_capable(priv->device, 1);
3196 if (priv->dma_cap.tsoen)
3197 dev_info(priv->device, "TSO supported\n");
3204 * @device: device pointer
3205 * @plat_dat: platform data pointer
3206 * @res: stmmac resource pointer
3207 * Description: this is the main probe function used to
3208 * call the alloc_etherdev, allocate the priv structure.
3210 * returns 0 on success, otherwise errno.
3212 int stmmac_dvr_probe(struct device *device,
3213 struct plat_stmmacenet_data *plat_dat,
3214 struct stmmac_resources *res)
3217 struct net_device *ndev = NULL;
3218 struct stmmac_priv *priv;
3220 ndev = alloc_etherdev(sizeof(struct stmmac_priv));
3224 SET_NETDEV_DEV(ndev, device);
3226 priv = netdev_priv(ndev);
3227 priv->device = device;
3230 stmmac_set_ethtool_ops(ndev);
3231 priv->pause = pause;
3232 priv->plat = plat_dat;
3233 priv->ioaddr = res->addr;
3234 priv->dev->base_addr = (unsigned long)res->addr;
3236 priv->dev->irq = res->irq;
3237 priv->wol_irq = res->wol_irq;
3238 priv->lpi_irq = res->lpi_irq;
3241 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
3243 dev_set_drvdata(device, priv->dev);
3245 /* Verify driver arguments */
3246 stmmac_verify_args();
3248 /* Override with kernel parameters if supplied XXX CRS XXX
3249 * this needs to have multiple instances
3251 if ((phyaddr >= 0) && (phyaddr <= 31))
3252 priv->plat->phy_addr = phyaddr;
3254 priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME);
3255 if (IS_ERR(priv->stmmac_clk)) {
3256 netdev_warn(priv->dev, "%s: warning: cannot get CSR clock\n",
3258 /* If failed to obtain stmmac_clk and specific clk_csr value
3259 * is NOT passed from the platform, probe fail.
3261 if (!priv->plat->clk_csr) {
3262 ret = PTR_ERR(priv->stmmac_clk);
3265 priv->stmmac_clk = NULL;
3268 clk_prepare_enable(priv->stmmac_clk);
3270 priv->pclk = devm_clk_get(priv->device, "pclk");
3271 if (IS_ERR(priv->pclk)) {
3272 if (PTR_ERR(priv->pclk) == -EPROBE_DEFER) {
3273 ret = -EPROBE_DEFER;
3274 goto error_pclk_get;
3278 clk_prepare_enable(priv->pclk);
3280 priv->stmmac_rst = devm_reset_control_get(priv->device,
3281 STMMAC_RESOURCE_NAME);
3282 if (IS_ERR(priv->stmmac_rst)) {
3283 if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) {
3284 ret = -EPROBE_DEFER;
3287 dev_info(priv->device, "no reset control found\n");
3288 priv->stmmac_rst = NULL;
3290 if (priv->stmmac_rst)
3291 reset_control_deassert(priv->stmmac_rst);
3293 /* Init MAC and get the capabilities */
3294 ret = stmmac_hw_init(priv);
3298 ndev->netdev_ops = &stmmac_netdev_ops;
3300 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3303 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
3304 ndev->hw_features |= NETIF_F_TSO;
3306 dev_info(priv->device, "TSO feature enabled\n");
3308 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
3309 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
3310 #ifdef STMMAC_VLAN_TAG_USED
3311 /* Both mac100 and gmac support receive VLAN tag detection */
3312 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3314 priv->msg_enable = netif_msg_init(debug, default_msg_level);
3316 /* MTU range: 46 - hw-specific max */
3317 ndev->min_mtu = ETH_ZLEN - ETH_HLEN;
3318 if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00))
3319 ndev->max_mtu = JUMBO_LEN;
3321 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
3322 if (priv->plat->maxmtu < ndev->max_mtu)
3323 ndev->max_mtu = priv->plat->maxmtu;
3326 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
3328 /* Rx Watchdog is available in the COREs newer than the 3.40.
3329 * In some case, for example on bugged HW this feature
3330 * has to be disable and this can be done by passing the
3331 * riwt_off field from the platform.
3333 if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
3335 netdev_info(priv->dev, "Enable RX Mitigation via HW Watchdog Timer\n");
3338 netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
3340 spin_lock_init(&priv->lock);
3342 ret = register_netdev(ndev);
3344 netdev_err(priv->dev, "%s: ERROR %i registering the device\n",
3346 goto error_netdev_register;
3349 /* If a specific clk_csr value is passed from the platform
3350 * this means that the CSR Clock Range selection cannot be
3351 * changed at run-time and it is fixed. Viceversa the driver'll try to
3352 * set the MDC clock dynamically according to the csr actual
3355 if (!priv->plat->clk_csr)
3356 stmmac_clk_csr_set(priv);
3358 priv->clk_csr = priv->plat->clk_csr;
3360 stmmac_check_pcs_mode(priv);
3362 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
3363 priv->hw->pcs != STMMAC_PCS_TBI &&
3364 priv->hw->pcs != STMMAC_PCS_RTBI) {
3365 /* MDIO bus Registration */
3366 ret = stmmac_mdio_register(ndev);
3368 netdev_err(priv->dev,
3369 "%s: MDIO bus (id: %d) registration failed",
3370 __func__, priv->plat->bus_id);
3371 goto error_mdio_register;
3377 error_mdio_register:
3378 unregister_netdev(ndev);
3379 error_netdev_register:
3380 netif_napi_del(&priv->napi);
3382 clk_disable_unprepare(priv->pclk);
3384 clk_disable_unprepare(priv->stmmac_clk);
3390 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
3394 * @dev: device pointer
3395 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
3396 * changes the link status, releases the DMA descriptor rings.
3398 int stmmac_dvr_remove(struct device *dev)
3400 struct net_device *ndev = dev_get_drvdata(dev);
3401 struct stmmac_priv *priv = netdev_priv(ndev);
3403 netdev_info(priv->dev, "%s: removing driver", __func__);
3405 priv->hw->dma->stop_rx(priv->ioaddr);
3406 priv->hw->dma->stop_tx(priv->ioaddr);
3408 stmmac_set_mac(priv->ioaddr, false);
3409 netif_carrier_off(ndev);
3410 unregister_netdev(ndev);
3411 if (priv->stmmac_rst)
3412 reset_control_assert(priv->stmmac_rst);
3413 clk_disable_unprepare(priv->pclk);
3414 clk_disable_unprepare(priv->stmmac_clk);
3415 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
3416 priv->hw->pcs != STMMAC_PCS_TBI &&
3417 priv->hw->pcs != STMMAC_PCS_RTBI)
3418 stmmac_mdio_unregister(ndev);
3423 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
3426 * stmmac_suspend - suspend callback
3427 * @dev: device pointer
3428 * Description: this is the function to suspend the device and it is called
3429 * by the platform driver to stop the network queue, release the resources,
3430 * program the PMT register (for WoL), clean and release driver resources.
3432 int stmmac_suspend(struct device *dev)
3434 struct net_device *ndev = dev_get_drvdata(dev);
3435 struct stmmac_priv *priv = netdev_priv(ndev);
3436 unsigned long flags;
3438 if (!ndev || !netif_running(ndev))
3442 phy_stop(ndev->phydev);
3444 spin_lock_irqsave(&priv->lock, flags);
3446 netif_device_detach(ndev);
3447 netif_stop_queue(ndev);
3449 napi_disable(&priv->napi);
3451 /* Stop TX/RX DMA */
3452 priv->hw->dma->stop_tx(priv->ioaddr);
3453 priv->hw->dma->stop_rx(priv->ioaddr);
3455 /* Enable Power down mode by programming the PMT regs */
3456 if (device_may_wakeup(priv->device)) {
3457 priv->hw->mac->pmt(priv->hw, priv->wolopts);
3460 stmmac_set_mac(priv->ioaddr, false);
3461 pinctrl_pm_select_sleep_state(priv->device);
3462 /* Disable clock in case of PWM is off */
3463 clk_disable(priv->pclk);
3464 clk_disable(priv->stmmac_clk);
3466 spin_unlock_irqrestore(&priv->lock, flags);
3470 priv->oldduplex = -1;
3473 EXPORT_SYMBOL_GPL(stmmac_suspend);
3476 * stmmac_resume - resume callback
3477 * @dev: device pointer
3478 * Description: when resume this function is invoked to setup the DMA and CORE
3479 * in a usable state.
3481 int stmmac_resume(struct device *dev)
3483 struct net_device *ndev = dev_get_drvdata(dev);
3484 struct stmmac_priv *priv = netdev_priv(ndev);
3485 unsigned long flags;
3487 if (!netif_running(ndev))
3490 /* Power Down bit, into the PM register, is cleared
3491 * automatically as soon as a magic packet or a Wake-up frame
3492 * is received. Anyway, it's better to manually clear
3493 * this bit because it can generate problems while resuming
3494 * from another devices (e.g. serial console).
3496 if (device_may_wakeup(priv->device)) {
3497 spin_lock_irqsave(&priv->lock, flags);
3498 priv->hw->mac->pmt(priv->hw, 0);
3499 spin_unlock_irqrestore(&priv->lock, flags);
3502 pinctrl_pm_select_default_state(priv->device);
3503 /* enable the clk prevously disabled */
3504 clk_enable(priv->stmmac_clk);
3505 clk_enable(priv->pclk);
3506 /* reset the phy so that it's ready */
3508 stmmac_mdio_reset(priv->mii);
3511 netif_device_attach(ndev);
3513 spin_lock_irqsave(&priv->lock, flags);
3519 /* reset private mss value to force mss context settings at
3520 * next tso xmit (only used for gmac4).
3524 stmmac_clear_descriptors(priv);
3526 stmmac_hw_setup(ndev, false);
3527 stmmac_init_tx_coalesce(priv);
3528 stmmac_set_rx_mode(ndev);
3530 napi_enable(&priv->napi);
3532 netif_start_queue(ndev);
3534 spin_unlock_irqrestore(&priv->lock, flags);
3537 phy_start(ndev->phydev);
3541 EXPORT_SYMBOL_GPL(stmmac_resume);
3544 static int __init stmmac_cmdline_opt(char *str)
3550 while ((opt = strsep(&str, ",")) != NULL) {
3551 if (!strncmp(opt, "debug:", 6)) {
3552 if (kstrtoint(opt + 6, 0, &debug))
3554 } else if (!strncmp(opt, "phyaddr:", 8)) {
3555 if (kstrtoint(opt + 8, 0, &phyaddr))
3557 } else if (!strncmp(opt, "buf_sz:", 7)) {
3558 if (kstrtoint(opt + 7, 0, &buf_sz))
3560 } else if (!strncmp(opt, "tc:", 3)) {
3561 if (kstrtoint(opt + 3, 0, &tc))
3563 } else if (!strncmp(opt, "watchdog:", 9)) {
3564 if (kstrtoint(opt + 9, 0, &watchdog))
3566 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
3567 if (kstrtoint(opt + 10, 0, &flow_ctrl))
3569 } else if (!strncmp(opt, "pause:", 6)) {
3570 if (kstrtoint(opt + 6, 0, &pause))
3572 } else if (!strncmp(opt, "eee_timer:", 10)) {
3573 if (kstrtoint(opt + 10, 0, &eee_timer))
3575 } else if (!strncmp(opt, "chain_mode:", 11)) {
3576 if (kstrtoint(opt + 11, 0, &chain_mode))
3583 pr_err("%s: ERROR broken module parameter conversion", __func__);
3587 __setup("stmmaceth=", stmmac_cmdline_opt);
3590 static int __init stmmac_init(void)
3592 #ifdef CONFIG_DEBUG_FS
3593 /* Create debugfs main directory if it doesn't exist yet */
3594 if (!stmmac_fs_dir) {
3595 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
3597 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
3598 pr_err("ERROR %s, debugfs create directory failed\n",
3599 STMMAC_RESOURCE_NAME);
3609 static void __exit stmmac_exit(void)
3611 #ifdef CONFIG_DEBUG_FS
3612 debugfs_remove_recursive(stmmac_fs_dir);
3616 module_init(stmmac_init)
3617 module_exit(stmmac_exit)
3619 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
3620 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
3621 MODULE_LICENSE("GPL");