1 /*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
5 Copyright(C) 2007-2011 STMicroelectronics Ltd
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 The full GNU General Public License is included in this distribution in
17 the file called "COPYING".
19 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
21 Documentation available at:
22 http://www.stlinux.com
24 https://bugzilla.stlinux.com/
25 *******************************************************************************/
27 #include <linux/clk.h>
28 #include <linux/kernel.h>
29 #include <linux/interrupt.h>
31 #include <linux/tcp.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/if_ether.h>
35 #include <linux/crc32.h>
36 #include <linux/mii.h>
38 #include <linux/if_vlan.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/slab.h>
41 #include <linux/prefetch.h>
42 #include <linux/pinctrl/consumer.h>
43 #ifdef CONFIG_DEBUG_FS
44 #include <linux/debugfs.h>
45 #include <linux/seq_file.h>
46 #endif /* CONFIG_DEBUG_FS */
47 #include <linux/net_tstamp.h>
48 #include "stmmac_ptp.h"
50 #include <linux/reset.h>
51 #include <linux/of_mdio.h>
52 #include "dwmac1000.h"
54 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
55 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1)
57 /* Module parameters */
59 static int watchdog = TX_TIMEO;
60 module_param(watchdog, int, S_IRUGO | S_IWUSR);
61 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
63 static int debug = -1;
64 module_param(debug, int, S_IRUGO | S_IWUSR);
65 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
67 static int phyaddr = -1;
68 module_param(phyaddr, int, S_IRUGO);
69 MODULE_PARM_DESC(phyaddr, "Physical device address");
71 #define STMMAC_TX_THRESH (DMA_TX_SIZE / 4)
72 #define STMMAC_RX_THRESH (DMA_RX_SIZE / 4)
74 static int flow_ctrl = FLOW_OFF;
75 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
76 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
78 static int pause = PAUSE_TIME;
79 module_param(pause, int, S_IRUGO | S_IWUSR);
80 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
83 static int tc = TC_DEFAULT;
84 module_param(tc, int, S_IRUGO | S_IWUSR);
85 MODULE_PARM_DESC(tc, "DMA threshold control value");
87 #define DEFAULT_BUFSIZE 1536
88 static int buf_sz = DEFAULT_BUFSIZE;
89 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
90 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
92 #define STMMAC_RX_COPYBREAK 256
94 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
95 NETIF_MSG_LINK | NETIF_MSG_IFUP |
96 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
98 #define STMMAC_DEFAULT_LPI_TIMER 1000
99 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
100 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
101 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
102 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
104 /* By default the driver will use the ring mode to manage tx and rx descriptors,
105 * but allow user to force to use the chain instead of the ring
107 static unsigned int chain_mode;
108 module_param(chain_mode, int, S_IRUGO);
109 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
111 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
113 #ifdef CONFIG_DEBUG_FS
114 static int stmmac_init_fs(struct net_device *dev);
115 static void stmmac_exit_fs(struct net_device *dev);
118 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
121 * stmmac_verify_args - verify the driver parameters.
122 * Description: it checks the driver parameters and set a default in case of
125 static void stmmac_verify_args(void)
127 if (unlikely(watchdog < 0))
129 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
130 buf_sz = DEFAULT_BUFSIZE;
131 if (unlikely(flow_ctrl > 1))
132 flow_ctrl = FLOW_AUTO;
133 else if (likely(flow_ctrl < 0))
134 flow_ctrl = FLOW_OFF;
135 if (unlikely((pause < 0) || (pause > 0xffff)))
138 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
142 * stmmac_clk_csr_set - dynamically set the MDC clock
143 * @priv: driver private structure
144 * Description: this is to dynamically set the MDC clock according to the csr
147 * If a specific clk_csr value is passed from the platform
148 * this means that the CSR Clock Range selection cannot be
149 * changed at run-time and it is fixed (as reported in the driver
150 * documentation). Viceversa the driver will try to set the MDC
151 * clock dynamically according to the actual clock input.
153 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
157 clk_rate = clk_get_rate(priv->plat->stmmac_clk);
159 /* Platform provided default clk_csr would be assumed valid
160 * for all other cases except for the below mentioned ones.
161 * For values higher than the IEEE 802.3 specified frequency
162 * we can not estimate the proper divider as it is not known
163 * the frequency of clk_csr_i. So we do not change the default
166 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
167 if (clk_rate < CSR_F_35M)
168 priv->clk_csr = STMMAC_CSR_20_35M;
169 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
170 priv->clk_csr = STMMAC_CSR_35_60M;
171 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
172 priv->clk_csr = STMMAC_CSR_60_100M;
173 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
174 priv->clk_csr = STMMAC_CSR_100_150M;
175 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
176 priv->clk_csr = STMMAC_CSR_150_250M;
177 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
178 priv->clk_csr = STMMAC_CSR_250_300M;
182 static void print_pkt(unsigned char *buf, int len)
184 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
185 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
188 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
192 if (priv->dirty_tx > priv->cur_tx)
193 avail = priv->dirty_tx - priv->cur_tx - 1;
195 avail = DMA_TX_SIZE - priv->cur_tx + priv->dirty_tx - 1;
200 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv)
204 if (priv->dirty_rx <= priv->cur_rx)
205 dirty = priv->cur_rx - priv->dirty_rx;
207 dirty = DMA_RX_SIZE - priv->dirty_rx + priv->cur_rx;
213 * stmmac_hw_fix_mac_speed - callback for speed selection
214 * @priv: driver private structure
215 * Description: on some platforms (e.g. ST), some HW system configuration
216 * registers have to be set according to the link speed negotiated.
218 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
220 struct net_device *ndev = priv->dev;
221 struct phy_device *phydev = ndev->phydev;
223 if (likely(priv->plat->fix_mac_speed))
224 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
228 * stmmac_enable_eee_mode - check and enter in LPI mode
229 * @priv: driver private structure
230 * Description: this function is to verify and enter in LPI mode in case of
233 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
235 /* Check and enter in LPI mode */
236 if ((priv->dirty_tx == priv->cur_tx) &&
237 (priv->tx_path_in_lpi_mode == false))
238 priv->hw->mac->set_eee_mode(priv->hw,
239 priv->plat->en_tx_lpi_clockgating);
243 * stmmac_disable_eee_mode - disable and exit from LPI mode
244 * @priv: driver private structure
245 * Description: this function is to exit and disable EEE in case of
246 * LPI state is true. This is called by the xmit.
248 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
250 priv->hw->mac->reset_eee_mode(priv->hw);
251 del_timer_sync(&priv->eee_ctrl_timer);
252 priv->tx_path_in_lpi_mode = false;
256 * stmmac_eee_ctrl_timer - EEE TX SW timer.
259 * if there is no data transfer and if we are not in LPI state,
260 * then MAC Transmitter can be moved to LPI state.
262 static void stmmac_eee_ctrl_timer(unsigned long arg)
264 struct stmmac_priv *priv = (struct stmmac_priv *)arg;
266 stmmac_enable_eee_mode(priv);
267 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
271 * stmmac_eee_init - init EEE
272 * @priv: driver private structure
274 * if the GMAC supports the EEE (from the HW cap reg) and the phy device
275 * can also manage EEE, this function enable the LPI state and start related
278 bool stmmac_eee_init(struct stmmac_priv *priv)
280 struct net_device *ndev = priv->dev;
284 /* Using PCS we cannot dial with the phy registers at this stage
285 * so we do not support extra feature like EEE.
287 if ((priv->hw->pcs == STMMAC_PCS_RGMII) ||
288 (priv->hw->pcs == STMMAC_PCS_TBI) ||
289 (priv->hw->pcs == STMMAC_PCS_RTBI))
292 /* MAC core supports the EEE feature. */
293 if (priv->dma_cap.eee) {
294 int tx_lpi_timer = priv->tx_lpi_timer;
296 /* Check if the PHY supports EEE */
297 if (phy_init_eee(ndev->phydev, 1)) {
298 /* To manage at run-time if the EEE cannot be supported
299 * anymore (for example because the lp caps have been
301 * In that case the driver disable own timers.
303 spin_lock_irqsave(&priv->lock, flags);
304 if (priv->eee_active) {
305 netdev_dbg(priv->dev, "disable EEE\n");
306 del_timer_sync(&priv->eee_ctrl_timer);
307 priv->hw->mac->set_eee_timer(priv->hw, 0,
310 priv->eee_active = 0;
311 spin_unlock_irqrestore(&priv->lock, flags);
314 /* Activate the EEE and start timers */
315 spin_lock_irqsave(&priv->lock, flags);
316 if (!priv->eee_active) {
317 priv->eee_active = 1;
318 setup_timer(&priv->eee_ctrl_timer,
319 stmmac_eee_ctrl_timer,
320 (unsigned long)priv);
321 mod_timer(&priv->eee_ctrl_timer,
322 STMMAC_LPI_T(eee_timer));
324 priv->hw->mac->set_eee_timer(priv->hw,
325 STMMAC_DEFAULT_LIT_LS,
328 /* Set HW EEE according to the speed */
329 priv->hw->mac->set_eee_pls(priv->hw, ndev->phydev->link);
332 spin_unlock_irqrestore(&priv->lock, flags);
334 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n");
340 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
341 * @priv: driver private structure
342 * @p : descriptor pointer
343 * @skb : the socket buffer
345 * This function will read timestamp from the descriptor & pass it to stack.
346 * and also perform some sanity checks.
348 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
349 struct dma_desc *p, struct sk_buff *skb)
351 struct skb_shared_hwtstamps shhwtstamp;
354 if (!priv->hwts_tx_en)
357 /* exit if skb doesn't support hw tstamp */
358 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
361 /* check tx tstamp status */
362 if (!priv->hw->desc->get_tx_timestamp_status(p)) {
363 /* get the valid tstamp */
364 ns = priv->hw->desc->get_timestamp(p, priv->adv_ts);
366 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
367 shhwtstamp.hwtstamp = ns_to_ktime(ns);
369 netdev_info(priv->dev, "get valid TX hw timestamp %llu\n", ns);
370 /* pass tstamp to stack */
371 skb_tstamp_tx(skb, &shhwtstamp);
377 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
378 * @priv: driver private structure
379 * @p : descriptor pointer
380 * @np : next descriptor pointer
381 * @skb : the socket buffer
383 * This function will read received packet's timestamp from the descriptor
384 * and pass it to stack. It also perform some sanity checks.
386 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p,
387 struct dma_desc *np, struct sk_buff *skb)
389 struct skb_shared_hwtstamps *shhwtstamp = NULL;
392 if (!priv->hwts_rx_en)
395 /* Check if timestamp is available */
396 if (!priv->hw->desc->get_rx_timestamp_status(p, priv->adv_ts)) {
397 /* For GMAC4, the valid timestamp is from CTX next desc. */
398 if (priv->plat->has_gmac4)
399 ns = priv->hw->desc->get_timestamp(np, priv->adv_ts);
401 ns = priv->hw->desc->get_timestamp(p, priv->adv_ts);
403 netdev_info(priv->dev, "get valid RX hw timestamp %llu\n", ns);
404 shhwtstamp = skb_hwtstamps(skb);
405 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
406 shhwtstamp->hwtstamp = ns_to_ktime(ns);
408 netdev_err(priv->dev, "cannot get RX hw timestamp\n");
413 * stmmac_hwtstamp_ioctl - control hardware timestamping.
414 * @dev: device pointer.
415 * @ifr: An IOCTL specific structure, that can contain a pointer to
416 * a proprietary structure used to pass information to the driver.
418 * This function configures the MAC to enable/disable both outgoing(TX)
419 * and incoming(RX) packets time stamping based on user input.
421 * 0 on success and an appropriate -ve integer on failure.
423 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
425 struct stmmac_priv *priv = netdev_priv(dev);
426 struct hwtstamp_config config;
427 struct timespec64 now;
431 u32 ptp_over_ipv4_udp = 0;
432 u32 ptp_over_ipv6_udp = 0;
433 u32 ptp_over_ethernet = 0;
434 u32 snap_type_sel = 0;
435 u32 ts_master_en = 0;
440 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
441 netdev_alert(priv->dev, "No support for HW time stamping\n");
442 priv->hwts_tx_en = 0;
443 priv->hwts_rx_en = 0;
448 if (copy_from_user(&config, ifr->ifr_data,
449 sizeof(struct hwtstamp_config)))
452 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
453 __func__, config.flags, config.tx_type, config.rx_filter);
455 /* reserved for future extensions */
459 if (config.tx_type != HWTSTAMP_TX_OFF &&
460 config.tx_type != HWTSTAMP_TX_ON)
464 switch (config.rx_filter) {
465 case HWTSTAMP_FILTER_NONE:
466 /* time stamp no incoming packet at all */
467 config.rx_filter = HWTSTAMP_FILTER_NONE;
470 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
471 /* PTP v1, UDP, any kind of event packet */
472 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
473 /* take time stamp for all event messages */
474 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
476 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
477 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
480 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
481 /* PTP v1, UDP, Sync packet */
482 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
483 /* take time stamp for SYNC messages only */
484 ts_event_en = PTP_TCR_TSEVNTENA;
486 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
487 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
490 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
491 /* PTP v1, UDP, Delay_req packet */
492 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
493 /* take time stamp for Delay_Req messages only */
494 ts_master_en = PTP_TCR_TSMSTRENA;
495 ts_event_en = PTP_TCR_TSEVNTENA;
497 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
498 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
501 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
502 /* PTP v2, UDP, any kind of event packet */
503 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
504 ptp_v2 = PTP_TCR_TSVER2ENA;
505 /* take time stamp for all event messages */
506 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
508 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
509 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
512 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
513 /* PTP v2, UDP, Sync packet */
514 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
515 ptp_v2 = PTP_TCR_TSVER2ENA;
516 /* take time stamp for SYNC messages only */
517 ts_event_en = PTP_TCR_TSEVNTENA;
519 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
520 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
523 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
524 /* PTP v2, UDP, Delay_req packet */
525 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
526 ptp_v2 = PTP_TCR_TSVER2ENA;
527 /* take time stamp for Delay_Req messages only */
528 ts_master_en = PTP_TCR_TSMSTRENA;
529 ts_event_en = PTP_TCR_TSEVNTENA;
531 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
532 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
535 case HWTSTAMP_FILTER_PTP_V2_EVENT:
536 /* PTP v2/802.AS1 any layer, any kind of event packet */
537 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
538 ptp_v2 = PTP_TCR_TSVER2ENA;
539 /* take time stamp for all event messages */
540 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
542 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
543 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
544 ptp_over_ethernet = PTP_TCR_TSIPENA;
547 case HWTSTAMP_FILTER_PTP_V2_SYNC:
548 /* PTP v2/802.AS1, any layer, Sync packet */
549 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
550 ptp_v2 = PTP_TCR_TSVER2ENA;
551 /* take time stamp for SYNC messages only */
552 ts_event_en = PTP_TCR_TSEVNTENA;
554 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
555 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
556 ptp_over_ethernet = PTP_TCR_TSIPENA;
559 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
560 /* PTP v2/802.AS1, any layer, Delay_req packet */
561 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
562 ptp_v2 = PTP_TCR_TSVER2ENA;
563 /* take time stamp for Delay_Req messages only */
564 ts_master_en = PTP_TCR_TSMSTRENA;
565 ts_event_en = PTP_TCR_TSEVNTENA;
567 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
568 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
569 ptp_over_ethernet = PTP_TCR_TSIPENA;
572 case HWTSTAMP_FILTER_ALL:
573 /* time stamp any incoming packet */
574 config.rx_filter = HWTSTAMP_FILTER_ALL;
575 tstamp_all = PTP_TCR_TSENALL;
582 switch (config.rx_filter) {
583 case HWTSTAMP_FILTER_NONE:
584 config.rx_filter = HWTSTAMP_FILTER_NONE;
587 /* PTP v1, UDP, any kind of event packet */
588 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
592 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
593 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
595 if (!priv->hwts_tx_en && !priv->hwts_rx_en)
596 priv->hw->ptp->config_hw_tstamping(priv->ptpaddr, 0);
598 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
599 tstamp_all | ptp_v2 | ptp_over_ethernet |
600 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
601 ts_master_en | snap_type_sel);
602 priv->hw->ptp->config_hw_tstamping(priv->ptpaddr, value);
604 /* program Sub Second Increment reg */
605 sec_inc = priv->hw->ptp->config_sub_second_increment(
606 priv->ptpaddr, priv->plat->clk_ptp_rate,
607 priv->plat->has_gmac4);
608 temp = div_u64(1000000000ULL, sec_inc);
610 /* calculate default added value:
612 * addend = (2^32)/freq_div_ratio;
613 * where, freq_div_ratio = 1e9ns/sec_inc
615 temp = (u64)(temp << 32);
616 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate);
617 priv->hw->ptp->config_addend(priv->ptpaddr,
618 priv->default_addend);
620 /* initialize system time */
621 ktime_get_real_ts64(&now);
623 /* lower 32 bits of tv_sec are safe until y2106 */
624 priv->hw->ptp->init_systime(priv->ptpaddr, (u32)now.tv_sec,
628 return copy_to_user(ifr->ifr_data, &config,
629 sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
633 * stmmac_init_ptp - init PTP
634 * @priv: driver private structure
635 * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
636 * This is done by looking at the HW cap. register.
637 * This function also registers the ptp driver.
639 static int stmmac_init_ptp(struct stmmac_priv *priv)
641 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
645 /* Check if adv_ts can be enabled for dwmac 4.x core */
646 if (priv->plat->has_gmac4 && priv->dma_cap.atime_stamp)
648 /* Dwmac 3.x core with extend_desc can support adv_ts */
649 else if (priv->extend_desc && priv->dma_cap.atime_stamp)
652 if (priv->dma_cap.time_stamp)
653 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n");
656 netdev_info(priv->dev,
657 "IEEE 1588-2008 Advanced Timestamp supported\n");
659 priv->hw->ptp = &stmmac_ptp;
660 priv->hwts_tx_en = 0;
661 priv->hwts_rx_en = 0;
663 stmmac_ptp_register(priv);
668 static void stmmac_release_ptp(struct stmmac_priv *priv)
670 if (priv->plat->clk_ptp_ref)
671 clk_disable_unprepare(priv->plat->clk_ptp_ref);
672 stmmac_ptp_unregister(priv);
676 * stmmac_mac_flow_ctrl - Configure flow control in all queues
677 * @priv: driver private structure
678 * Description: It is used for configuring the flow control in all queues
680 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex)
682 u32 tx_cnt = priv->plat->tx_queues_to_use;
684 priv->hw->mac->flow_ctrl(priv->hw, duplex, priv->flow_ctrl,
685 priv->pause, tx_cnt);
689 * stmmac_adjust_link - adjusts the link parameters
690 * @dev: net device structure
691 * Description: this is the helper called by the physical abstraction layer
692 * drivers to communicate the phy link status. According the speed and duplex
693 * this driver can invoke registered glue-logic as well.
694 * It also invoke the eee initialization because it could happen when switch
695 * on different networks (that are eee capable).
697 static void stmmac_adjust_link(struct net_device *dev)
699 struct stmmac_priv *priv = netdev_priv(dev);
700 struct phy_device *phydev = dev->phydev;
707 spin_lock_irqsave(&priv->lock, flags);
710 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
712 /* Now we make sure that we can be in full duplex mode.
713 * If not, we operate in half-duplex mode. */
714 if (phydev->duplex != priv->oldduplex) {
716 if (!(phydev->duplex))
717 ctrl &= ~priv->hw->link.duplex;
719 ctrl |= priv->hw->link.duplex;
720 priv->oldduplex = phydev->duplex;
722 /* Flow Control operation */
724 stmmac_mac_flow_ctrl(priv, phydev->duplex);
726 if (phydev->speed != priv->speed) {
728 switch (phydev->speed) {
730 if (priv->plat->has_gmac ||
731 priv->plat->has_gmac4)
732 ctrl &= ~priv->hw->link.port;
735 if (priv->plat->has_gmac ||
736 priv->plat->has_gmac4) {
737 ctrl |= priv->hw->link.port;
738 ctrl |= priv->hw->link.speed;
740 ctrl &= ~priv->hw->link.port;
744 if (priv->plat->has_gmac ||
745 priv->plat->has_gmac4) {
746 ctrl |= priv->hw->link.port;
747 ctrl &= ~(priv->hw->link.speed);
749 ctrl &= ~priv->hw->link.port;
753 netif_warn(priv, link, priv->dev,
754 "broken speed: %d\n", phydev->speed);
755 phydev->speed = SPEED_UNKNOWN;
758 if (phydev->speed != SPEED_UNKNOWN)
759 stmmac_hw_fix_mac_speed(priv);
760 priv->speed = phydev->speed;
763 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
765 if (!priv->oldlink) {
769 } else if (priv->oldlink) {
772 priv->speed = SPEED_UNKNOWN;
773 priv->oldduplex = DUPLEX_UNKNOWN;
776 if (new_state && netif_msg_link(priv))
777 phy_print_status(phydev);
779 spin_unlock_irqrestore(&priv->lock, flags);
781 if (phydev->is_pseudo_fixed_link)
782 /* Stop PHY layer to call the hook to adjust the link in case
783 * of a switch is attached to the stmmac driver.
785 phydev->irq = PHY_IGNORE_INTERRUPT;
787 /* At this stage, init the EEE if supported.
788 * Never called in case of fixed_link.
790 priv->eee_enabled = stmmac_eee_init(priv);
794 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
795 * @priv: driver private structure
796 * Description: this is to verify if the HW supports the PCS.
797 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
798 * configured for the TBI, RTBI, or SGMII PHY interface.
800 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
802 int interface = priv->plat->interface;
804 if (priv->dma_cap.pcs) {
805 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
806 (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
807 (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
808 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
809 netdev_dbg(priv->dev, "PCS RGMII support enabled\n");
810 priv->hw->pcs = STMMAC_PCS_RGMII;
811 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
812 netdev_dbg(priv->dev, "PCS SGMII support enabled\n");
813 priv->hw->pcs = STMMAC_PCS_SGMII;
819 * stmmac_init_phy - PHY initialization
820 * @dev: net device structure
821 * Description: it initializes the driver's PHY state, and attaches the PHY
826 static int stmmac_init_phy(struct net_device *dev)
828 struct stmmac_priv *priv = netdev_priv(dev);
829 struct phy_device *phydev;
830 char phy_id_fmt[MII_BUS_ID_SIZE + 3];
831 char bus_id[MII_BUS_ID_SIZE];
832 int interface = priv->plat->interface;
833 int max_speed = priv->plat->max_speed;
835 priv->speed = SPEED_UNKNOWN;
836 priv->oldduplex = DUPLEX_UNKNOWN;
838 if (priv->plat->phy_node) {
839 phydev = of_phy_connect(dev, priv->plat->phy_node,
840 &stmmac_adjust_link, 0, interface);
842 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
845 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
846 priv->plat->phy_addr);
847 netdev_dbg(priv->dev, "%s: trying to attach to %s\n", __func__,
850 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link,
854 if (IS_ERR_OR_NULL(phydev)) {
855 netdev_err(priv->dev, "Could not attach to PHY\n");
859 return PTR_ERR(phydev);
862 /* Stop Advertising 1000BASE Capability if interface is not GMII */
863 if ((interface == PHY_INTERFACE_MODE_MII) ||
864 (interface == PHY_INTERFACE_MODE_RMII) ||
865 (max_speed < 1000 && max_speed > 0))
866 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
867 SUPPORTED_1000baseT_Full);
870 * Broken HW is sometimes missing the pull-up resistor on the
871 * MDIO line, which results in reads to non-existent devices returning
872 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
874 * Note: phydev->phy_id is the result of reading the UID PHY registers.
876 if (!priv->plat->phy_node && phydev->phy_id == 0) {
877 phy_disconnect(phydev);
881 /* stmmac_adjust_link will change this to PHY_IGNORE_INTERRUPT to avoid
882 * subsequent PHY polling, make sure we force a link transition if
883 * we have a UP/DOWN/UP transition
885 if (phydev->is_pseudo_fixed_link)
886 phydev->irq = PHY_POLL;
888 phy_attached_info(phydev);
892 static void stmmac_display_rings(struct stmmac_priv *priv)
894 void *head_rx, *head_tx;
896 if (priv->extend_desc) {
897 head_rx = (void *)priv->dma_erx;
898 head_tx = (void *)priv->dma_etx;
900 head_rx = (void *)priv->dma_rx;
901 head_tx = (void *)priv->dma_tx;
904 /* Display Rx ring */
905 priv->hw->desc->display_ring(head_rx, DMA_RX_SIZE, true);
906 /* Display Tx ring */
907 priv->hw->desc->display_ring(head_tx, DMA_TX_SIZE, false);
910 static int stmmac_set_bfsize(int mtu, int bufsize)
914 if (mtu >= BUF_SIZE_4KiB)
916 else if (mtu >= BUF_SIZE_2KiB)
918 else if (mtu > DEFAULT_BUFSIZE)
921 ret = DEFAULT_BUFSIZE;
927 * stmmac_clear_descriptors - clear descriptors
928 * @priv: driver private structure
929 * Description: this function is called to clear the tx and rx descriptors
930 * in case of both basic and extended descriptors are used.
932 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
936 /* Clear the Rx/Tx descriptors */
937 for (i = 0; i < DMA_RX_SIZE; i++)
938 if (priv->extend_desc)
939 priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
940 priv->use_riwt, priv->mode,
941 (i == DMA_RX_SIZE - 1));
943 priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
944 priv->use_riwt, priv->mode,
945 (i == DMA_RX_SIZE - 1));
946 for (i = 0; i < DMA_TX_SIZE; i++)
947 if (priv->extend_desc)
948 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
950 (i == DMA_TX_SIZE - 1));
952 priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
954 (i == DMA_TX_SIZE - 1));
958 * stmmac_init_rx_buffers - init the RX descriptor buffer.
959 * @priv: driver private structure
960 * @p: descriptor pointer
961 * @i: descriptor index
963 * Description: this function is called to allocate a receive buffer, perform
964 * the DMA mapping and init the descriptor.
966 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
971 skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags);
973 netdev_err(priv->dev,
974 "%s: Rx init fails; skb is NULL\n", __func__);
977 priv->rx_skbuff[i] = skb;
978 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
981 if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) {
982 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__);
983 dev_kfree_skb_any(skb);
987 if (priv->synopsys_id >= DWMAC_CORE_4_00)
988 p->des0 = cpu_to_le32(priv->rx_skbuff_dma[i]);
990 p->des2 = cpu_to_le32(priv->rx_skbuff_dma[i]);
992 if ((priv->hw->mode->init_desc3) &&
993 (priv->dma_buf_sz == BUF_SIZE_16KiB))
994 priv->hw->mode->init_desc3(p);
999 static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i)
1001 if (priv->rx_skbuff[i]) {
1002 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
1003 priv->dma_buf_sz, DMA_FROM_DEVICE);
1004 dev_kfree_skb_any(priv->rx_skbuff[i]);
1006 priv->rx_skbuff[i] = NULL;
1010 * init_dma_desc_rings - init the RX/TX descriptor rings
1011 * @dev: net device structure
1013 * Description: this function initializes the DMA RX/TX descriptors
1014 * and allocates the socket buffers. It supports the chained and ring
1017 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1020 struct stmmac_priv *priv = netdev_priv(dev);
1021 unsigned int bfsize = 0;
1024 if (priv->hw->mode->set_16kib_bfsize)
1025 bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu);
1027 if (bfsize < BUF_SIZE_16KiB)
1028 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1030 priv->dma_buf_sz = bfsize;
1032 netif_dbg(priv, probe, priv->dev,
1033 "(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n",
1034 __func__, (u32)priv->dma_rx_phy, (u32)priv->dma_tx_phy);
1036 /* RX INITIALIZATION */
1037 netif_dbg(priv, probe, priv->dev,
1038 "SKB addresses:\nskb\t\tskb data\tdma data\n");
1040 for (i = 0; i < DMA_RX_SIZE; i++) {
1042 if (priv->extend_desc)
1043 p = &((priv->dma_erx + i)->basic);
1045 p = priv->dma_rx + i;
1047 ret = stmmac_init_rx_buffers(priv, p, i, flags);
1049 goto err_init_rx_buffers;
1051 netif_dbg(priv, probe, priv->dev, "[%p]\t[%p]\t[%x]\n",
1052 priv->rx_skbuff[i], priv->rx_skbuff[i]->data,
1053 (unsigned int)priv->rx_skbuff_dma[i]);
1056 priv->dirty_rx = (unsigned int)(i - DMA_RX_SIZE);
1059 /* Setup the chained descriptor addresses */
1060 if (priv->mode == STMMAC_CHAIN_MODE) {
1061 if (priv->extend_desc) {
1062 priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy,
1064 priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy,
1067 priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy,
1069 priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy,
1074 /* TX INITIALIZATION */
1075 for (i = 0; i < DMA_TX_SIZE; i++) {
1077 if (priv->extend_desc)
1078 p = &((priv->dma_etx + i)->basic);
1080 p = priv->dma_tx + i;
1082 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
1091 priv->tx_skbuff_dma[i].buf = 0;
1092 priv->tx_skbuff_dma[i].map_as_page = false;
1093 priv->tx_skbuff_dma[i].len = 0;
1094 priv->tx_skbuff_dma[i].last_segment = false;
1095 priv->tx_skbuff[i] = NULL;
1100 netdev_reset_queue(priv->dev);
1102 stmmac_clear_descriptors(priv);
1104 if (netif_msg_hw(priv))
1105 stmmac_display_rings(priv);
1108 err_init_rx_buffers:
1110 stmmac_free_rx_buffers(priv, i);
1114 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
1118 for (i = 0; i < DMA_RX_SIZE; i++)
1119 stmmac_free_rx_buffers(priv, i);
1122 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
1126 for (i = 0; i < DMA_TX_SIZE; i++) {
1127 if (priv->tx_skbuff_dma[i].buf) {
1128 if (priv->tx_skbuff_dma[i].map_as_page)
1129 dma_unmap_page(priv->device,
1130 priv->tx_skbuff_dma[i].buf,
1131 priv->tx_skbuff_dma[i].len,
1134 dma_unmap_single(priv->device,
1135 priv->tx_skbuff_dma[i].buf,
1136 priv->tx_skbuff_dma[i].len,
1140 if (priv->tx_skbuff[i]) {
1141 dev_kfree_skb_any(priv->tx_skbuff[i]);
1142 priv->tx_skbuff[i] = NULL;
1143 priv->tx_skbuff_dma[i].buf = 0;
1144 priv->tx_skbuff_dma[i].map_as_page = false;
1150 * alloc_dma_desc_resources - alloc TX/RX resources.
1151 * @priv: private structure
1152 * Description: according to which descriptor can be used (extend or basic)
1153 * this function allocates the resources for TX and RX paths. In case of
1154 * reception, for example, it pre-allocated the RX socket buffer in order to
1155 * allow zero-copy mechanism.
1157 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1161 priv->rx_skbuff_dma = kmalloc_array(DMA_RX_SIZE, sizeof(dma_addr_t),
1163 if (!priv->rx_skbuff_dma)
1166 priv->rx_skbuff = kmalloc_array(DMA_RX_SIZE, sizeof(struct sk_buff *),
1168 if (!priv->rx_skbuff)
1171 priv->tx_skbuff_dma = kmalloc_array(DMA_TX_SIZE,
1172 sizeof(*priv->tx_skbuff_dma),
1174 if (!priv->tx_skbuff_dma)
1175 goto err_tx_skbuff_dma;
1177 priv->tx_skbuff = kmalloc_array(DMA_TX_SIZE, sizeof(struct sk_buff *),
1179 if (!priv->tx_skbuff)
1182 if (priv->extend_desc) {
1183 priv->dma_erx = dma_zalloc_coherent(priv->device, DMA_RX_SIZE *
1191 priv->dma_etx = dma_zalloc_coherent(priv->device, DMA_TX_SIZE *
1196 if (!priv->dma_etx) {
1197 dma_free_coherent(priv->device, DMA_RX_SIZE *
1198 sizeof(struct dma_extended_desc),
1199 priv->dma_erx, priv->dma_rx_phy);
1203 priv->dma_rx = dma_zalloc_coherent(priv->device, DMA_RX_SIZE *
1204 sizeof(struct dma_desc),
1210 priv->dma_tx = dma_zalloc_coherent(priv->device, DMA_TX_SIZE *
1211 sizeof(struct dma_desc),
1214 if (!priv->dma_tx) {
1215 dma_free_coherent(priv->device, DMA_RX_SIZE *
1216 sizeof(struct dma_desc),
1217 priv->dma_rx, priv->dma_rx_phy);
1225 kfree(priv->tx_skbuff);
1227 kfree(priv->tx_skbuff_dma);
1229 kfree(priv->rx_skbuff);
1231 kfree(priv->rx_skbuff_dma);
1235 static void free_dma_desc_resources(struct stmmac_priv *priv)
1237 /* Release the DMA TX/RX socket buffers */
1238 dma_free_rx_skbufs(priv);
1239 dma_free_tx_skbufs(priv);
1241 /* Free DMA regions of consistent memory previously allocated */
1242 if (!priv->extend_desc) {
1243 dma_free_coherent(priv->device,
1244 DMA_TX_SIZE * sizeof(struct dma_desc),
1245 priv->dma_tx, priv->dma_tx_phy);
1246 dma_free_coherent(priv->device,
1247 DMA_RX_SIZE * sizeof(struct dma_desc),
1248 priv->dma_rx, priv->dma_rx_phy);
1250 dma_free_coherent(priv->device, DMA_TX_SIZE *
1251 sizeof(struct dma_extended_desc),
1252 priv->dma_etx, priv->dma_tx_phy);
1253 dma_free_coherent(priv->device, DMA_RX_SIZE *
1254 sizeof(struct dma_extended_desc),
1255 priv->dma_erx, priv->dma_rx_phy);
1257 kfree(priv->rx_skbuff_dma);
1258 kfree(priv->rx_skbuff);
1259 kfree(priv->tx_skbuff_dma);
1260 kfree(priv->tx_skbuff);
1264 * stmmac_mac_enable_rx_queues - Enable MAC rx queues
1265 * @priv: driver private structure
1266 * Description: It is used for enabling the rx queues in the MAC
1268 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)
1270 u32 rx_queues_count = priv->plat->rx_queues_to_use;
1274 for (queue = 0; queue < rx_queues_count; queue++) {
1275 mode = priv->plat->rx_queues_cfg[queue].mode_to_use;
1276 priv->hw->mac->rx_queue_enable(priv->hw, mode, queue);
1281 * stmmac_start_rx_dma - start RX DMA channel
1282 * @priv: driver private structure
1283 * @chan: RX channel index
1285 * This starts a RX DMA channel
1287 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan)
1289 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan);
1290 priv->hw->dma->start_rx(priv->ioaddr, chan);
1294 * stmmac_start_tx_dma - start TX DMA channel
1295 * @priv: driver private structure
1296 * @chan: TX channel index
1298 * This starts a TX DMA channel
1300 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan)
1302 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan);
1303 priv->hw->dma->start_tx(priv->ioaddr, chan);
1307 * stmmac_stop_rx_dma - stop RX DMA channel
1308 * @priv: driver private structure
1309 * @chan: RX channel index
1311 * This stops a RX DMA channel
1313 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan)
1315 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan);
1316 priv->hw->dma->stop_rx(priv->ioaddr, chan);
1320 * stmmac_stop_tx_dma - stop TX DMA channel
1321 * @priv: driver private structure
1322 * @chan: TX channel index
1324 * This stops a TX DMA channel
1326 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan)
1328 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan);
1329 priv->hw->dma->stop_tx(priv->ioaddr, chan);
1333 * stmmac_start_all_dma - start all RX and TX DMA channels
1334 * @priv: driver private structure
1336 * This starts all the RX and TX DMA channels
1338 static void stmmac_start_all_dma(struct stmmac_priv *priv)
1340 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1341 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1344 for (chan = 0; chan < rx_channels_count; chan++)
1345 stmmac_start_rx_dma(priv, chan);
1347 for (chan = 0; chan < tx_channels_count; chan++)
1348 stmmac_start_tx_dma(priv, chan);
1352 * stmmac_stop_all_dma - stop all RX and TX DMA channels
1353 * @priv: driver private structure
1355 * This stops the RX and TX DMA channels
1357 static void stmmac_stop_all_dma(struct stmmac_priv *priv)
1359 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1360 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1363 for (chan = 0; chan < rx_channels_count; chan++)
1364 stmmac_stop_rx_dma(priv, chan);
1366 for (chan = 0; chan < tx_channels_count; chan++)
1367 stmmac_stop_tx_dma(priv, chan);
1371 * stmmac_dma_operation_mode - HW DMA operation mode
1372 * @priv: driver private structure
1373 * Description: it is used for configuring the DMA operation mode register in
1374 * order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1376 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1378 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1379 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1380 int rxfifosz = priv->plat->rx_fifo_size;
1386 rxfifosz = priv->dma_cap.rx_fifo_size;
1388 if (priv->plat->force_thresh_dma_mode) {
1391 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1393 * In case of GMAC, SF mode can be enabled
1394 * to perform the TX COE in HW. This depends on:
1395 * 1) TX COE if actually supported
1396 * 2) There is no bugged Jumbo frame support
1397 * that needs to not insert csum in the TDES.
1399 txmode = SF_DMA_MODE;
1400 rxmode = SF_DMA_MODE;
1401 priv->xstats.threshold = SF_DMA_MODE;
1404 rxmode = SF_DMA_MODE;
1407 /* configure all channels */
1408 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
1409 for (chan = 0; chan < rx_channels_count; chan++)
1410 priv->hw->dma->dma_rx_mode(priv->ioaddr, rxmode, chan,
1413 for (chan = 0; chan < tx_channels_count; chan++)
1414 priv->hw->dma->dma_tx_mode(priv->ioaddr, txmode, chan);
1416 priv->hw->dma->dma_mode(priv->ioaddr, txmode, rxmode,
1422 * stmmac_tx_clean - to manage the transmission completion
1423 * @priv: driver private structure
1424 * Description: it reclaims the transmit resources after transmission completes.
1426 static void stmmac_tx_clean(struct stmmac_priv *priv)
1428 unsigned int bytes_compl = 0, pkts_compl = 0;
1429 unsigned int entry = priv->dirty_tx;
1431 netif_tx_lock(priv->dev);
1433 priv->xstats.tx_clean++;
1435 while (entry != priv->cur_tx) {
1436 struct sk_buff *skb = priv->tx_skbuff[entry];
1440 if (priv->extend_desc)
1441 p = (struct dma_desc *)(priv->dma_etx + entry);
1443 p = priv->dma_tx + entry;
1445 status = priv->hw->desc->tx_status(&priv->dev->stats,
1448 /* Check if the descriptor is owned by the DMA */
1449 if (unlikely(status & tx_dma_own))
1452 /* Just consider the last segment and ...*/
1453 if (likely(!(status & tx_not_ls))) {
1454 /* ... verify the status error condition */
1455 if (unlikely(status & tx_err)) {
1456 priv->dev->stats.tx_errors++;
1458 priv->dev->stats.tx_packets++;
1459 priv->xstats.tx_pkt_n++;
1461 stmmac_get_tx_hwtstamp(priv, p, skb);
1464 if (likely(priv->tx_skbuff_dma[entry].buf)) {
1465 if (priv->tx_skbuff_dma[entry].map_as_page)
1466 dma_unmap_page(priv->device,
1467 priv->tx_skbuff_dma[entry].buf,
1468 priv->tx_skbuff_dma[entry].len,
1471 dma_unmap_single(priv->device,
1472 priv->tx_skbuff_dma[entry].buf,
1473 priv->tx_skbuff_dma[entry].len,
1475 priv->tx_skbuff_dma[entry].buf = 0;
1476 priv->tx_skbuff_dma[entry].len = 0;
1477 priv->tx_skbuff_dma[entry].map_as_page = false;
1480 if (priv->hw->mode->clean_desc3)
1481 priv->hw->mode->clean_desc3(priv, p);
1483 priv->tx_skbuff_dma[entry].last_segment = false;
1484 priv->tx_skbuff_dma[entry].is_jumbo = false;
1486 if (likely(skb != NULL)) {
1488 bytes_compl += skb->len;
1489 dev_consume_skb_any(skb);
1490 priv->tx_skbuff[entry] = NULL;
1493 priv->hw->desc->release_tx_desc(p, priv->mode);
1495 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
1497 priv->dirty_tx = entry;
1499 netdev_completed_queue(priv->dev, pkts_compl, bytes_compl);
1501 if (unlikely(netif_queue_stopped(priv->dev) &&
1502 stmmac_tx_avail(priv) > STMMAC_TX_THRESH)) {
1503 netif_dbg(priv, tx_done, priv->dev,
1504 "%s: restart transmit\n", __func__);
1505 netif_wake_queue(priv->dev);
1508 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1509 stmmac_enable_eee_mode(priv);
1510 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1512 netif_tx_unlock(priv->dev);
1515 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv, u32 chan)
1517 priv->hw->dma->enable_dma_irq(priv->ioaddr, chan);
1520 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv, u32 chan)
1522 priv->hw->dma->disable_dma_irq(priv->ioaddr, chan);
1526 * stmmac_tx_err - to manage the tx error
1527 * @priv: driver private structure
1528 * @chan: channel index
1529 * Description: it cleans the descriptors and restarts the transmission
1530 * in case of transmission errors.
1532 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan)
1535 netif_stop_queue(priv->dev);
1537 stmmac_stop_tx_dma(priv, chan);
1538 dma_free_tx_skbufs(priv);
1539 for (i = 0; i < DMA_TX_SIZE; i++)
1540 if (priv->extend_desc)
1541 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
1543 (i == DMA_TX_SIZE - 1));
1545 priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
1547 (i == DMA_TX_SIZE - 1));
1550 netdev_reset_queue(priv->dev);
1551 stmmac_start_tx_dma(priv, chan);
1553 priv->dev->stats.tx_errors++;
1554 netif_wake_queue(priv->dev);
1558 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel
1559 * @priv: driver private structure
1560 * @txmode: TX operating mode
1561 * @rxmode: RX operating mode
1562 * @chan: channel index
1563 * Description: it is used for configuring of the DMA operation mode in
1564 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward
1567 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
1568 u32 rxmode, u32 chan)
1570 int rxfifosz = priv->plat->rx_fifo_size;
1573 rxfifosz = priv->dma_cap.rx_fifo_size;
1575 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
1576 priv->hw->dma->dma_rx_mode(priv->ioaddr, rxmode, chan,
1578 priv->hw->dma->dma_tx_mode(priv->ioaddr, txmode, chan);
1580 priv->hw->dma->dma_mode(priv->ioaddr, txmode, rxmode,
1586 * stmmac_dma_interrupt - DMA ISR
1587 * @priv: driver private structure
1588 * Description: this is the DMA ISR. It is called by the main ISR.
1589 * It calls the dwmac dma routine and schedule poll method in case of some
1592 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
1594 u32 tx_channel_count = priv->plat->tx_queues_to_use;
1598 for (chan = 0; chan < tx_channel_count; chan++) {
1599 status = priv->hw->dma->dma_interrupt(priv->ioaddr,
1600 &priv->xstats, chan);
1601 if (likely((status & handle_rx)) || (status & handle_tx)) {
1602 if (likely(napi_schedule_prep(&priv->napi))) {
1603 stmmac_disable_dma_irq(priv, chan);
1604 __napi_schedule(&priv->napi);
1608 if (unlikely(status & tx_hard_error_bump_tc)) {
1609 /* Try to bump up the dma threshold on this failure */
1610 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
1613 if (priv->plat->force_thresh_dma_mode)
1614 stmmac_set_dma_operation_mode(priv,
1619 stmmac_set_dma_operation_mode(priv,
1623 priv->xstats.threshold = tc;
1625 } else if (unlikely(status == tx_hard_error)) {
1626 stmmac_tx_err(priv, chan);
1632 * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1633 * @priv: driver private structure
1634 * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1636 static void stmmac_mmc_setup(struct stmmac_priv *priv)
1638 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
1639 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1641 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
1642 priv->ptpaddr = priv->ioaddr + PTP_GMAC4_OFFSET;
1643 priv->mmcaddr = priv->ioaddr + MMC_GMAC4_OFFSET;
1645 priv->ptpaddr = priv->ioaddr + PTP_GMAC3_X_OFFSET;
1646 priv->mmcaddr = priv->ioaddr + MMC_GMAC3_X_OFFSET;
1649 dwmac_mmc_intr_all_mask(priv->mmcaddr);
1651 if (priv->dma_cap.rmon) {
1652 dwmac_mmc_ctrl(priv->mmcaddr, mode);
1653 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
1655 netdev_info(priv->dev, "No MAC Management Counters available\n");
1659 * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors
1660 * @priv: driver private structure
1661 * Description: select the Enhanced/Alternate or Normal descriptors.
1662 * In case of Enhanced/Alternate, it checks if the extended descriptors are
1663 * supported by the HW capability register.
1665 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
1667 if (priv->plat->enh_desc) {
1668 dev_info(priv->device, "Enhanced/Alternate descriptors\n");
1670 /* GMAC older than 3.50 has no extended descriptors */
1671 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
1672 dev_info(priv->device, "Enabled extended descriptors\n");
1673 priv->extend_desc = 1;
1675 dev_warn(priv->device, "Extended descriptors not supported\n");
1677 priv->hw->desc = &enh_desc_ops;
1679 dev_info(priv->device, "Normal descriptors\n");
1680 priv->hw->desc = &ndesc_ops;
1685 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
1686 * @priv: driver private structure
1688 * new GMAC chip generations have a new register to indicate the
1689 * presence of the optional feature/functions.
1690 * This can be also used to override the value passed through the
1691 * platform and necessary for old MAC10/100 and GMAC chips.
1693 static int stmmac_get_hw_features(struct stmmac_priv *priv)
1697 if (priv->hw->dma->get_hw_feature) {
1698 priv->hw->dma->get_hw_feature(priv->ioaddr,
1707 * stmmac_check_ether_addr - check if the MAC addr is valid
1708 * @priv: driver private structure
1710 * it is to verify if the MAC address is valid, in case of failures it
1711 * generates a random MAC address
1713 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
1715 if (!is_valid_ether_addr(priv->dev->dev_addr)) {
1716 priv->hw->mac->get_umac_addr(priv->hw,
1717 priv->dev->dev_addr, 0);
1718 if (!is_valid_ether_addr(priv->dev->dev_addr))
1719 eth_hw_addr_random(priv->dev);
1720 netdev_info(priv->dev, "device MAC address %pM\n",
1721 priv->dev->dev_addr);
1726 * stmmac_init_dma_engine - DMA init.
1727 * @priv: driver private structure
1729 * It inits the DMA invoking the specific MAC/GMAC callback.
1730 * Some DMA parameters can be passed from the platform;
1731 * in case of these are not passed a default is kept for the MAC or GMAC.
1733 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
1735 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1736 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1737 u32 dummy_dma_rx_phy = 0;
1738 u32 dummy_dma_tx_phy = 0;
1743 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) {
1744 dev_err(priv->device, "Invalid DMA configuration\n");
1748 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
1751 ret = priv->hw->dma->reset(priv->ioaddr);
1753 dev_err(priv->device, "Failed to reset the dma\n");
1757 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
1758 /* DMA Configuration */
1759 priv->hw->dma->init(priv->ioaddr, priv->plat->dma_cfg,
1760 dummy_dma_tx_phy, dummy_dma_rx_phy, atds);
1762 /* DMA RX Channel Configuration */
1763 for (chan = 0; chan < rx_channels_count; chan++) {
1764 priv->hw->dma->init_rx_chan(priv->ioaddr,
1765 priv->plat->dma_cfg,
1766 priv->dma_rx_phy, chan);
1768 priv->rx_tail_addr = priv->dma_rx_phy +
1769 (DMA_RX_SIZE * sizeof(struct dma_desc));
1770 priv->hw->dma->set_rx_tail_ptr(priv->ioaddr,
1775 /* DMA TX Channel Configuration */
1776 for (chan = 0; chan < tx_channels_count; chan++) {
1777 priv->hw->dma->init_chan(priv->ioaddr,
1778 priv->plat->dma_cfg,
1781 priv->hw->dma->init_tx_chan(priv->ioaddr,
1782 priv->plat->dma_cfg,
1783 priv->dma_tx_phy, chan);
1785 priv->tx_tail_addr = priv->dma_tx_phy +
1786 (DMA_TX_SIZE * sizeof(struct dma_desc));
1787 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr,
1792 priv->hw->dma->init(priv->ioaddr, priv->plat->dma_cfg,
1793 priv->dma_tx_phy, priv->dma_rx_phy, atds);
1796 if (priv->plat->axi && priv->hw->dma->axi)
1797 priv->hw->dma->axi(priv->ioaddr, priv->plat->axi);
1803 * stmmac_tx_timer - mitigation sw timer for tx.
1804 * @data: data pointer
1806 * This is the timer handler to directly invoke the stmmac_tx_clean.
1808 static void stmmac_tx_timer(unsigned long data)
1810 struct stmmac_priv *priv = (struct stmmac_priv *)data;
1812 stmmac_tx_clean(priv);
1816 * stmmac_init_tx_coalesce - init tx mitigation options.
1817 * @priv: driver private structure
1819 * This inits the transmit coalesce parameters: i.e. timer rate,
1820 * timer handler and default threshold used for enabling the
1821 * interrupt on completion bit.
1823 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
1825 priv->tx_coal_frames = STMMAC_TX_FRAMES;
1826 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
1827 init_timer(&priv->txtimer);
1828 priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
1829 priv->txtimer.data = (unsigned long)priv;
1830 priv->txtimer.function = stmmac_tx_timer;
1831 add_timer(&priv->txtimer);
1834 static void stmmac_set_rings_length(struct stmmac_priv *priv)
1836 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1837 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1840 /* set TX ring length */
1841 if (priv->hw->dma->set_tx_ring_len) {
1842 for (chan = 0; chan < tx_channels_count; chan++)
1843 priv->hw->dma->set_tx_ring_len(priv->ioaddr,
1844 (DMA_TX_SIZE - 1), chan);
1847 /* set RX ring length */
1848 if (priv->hw->dma->set_rx_ring_len) {
1849 for (chan = 0; chan < rx_channels_count; chan++)
1850 priv->hw->dma->set_rx_ring_len(priv->ioaddr,
1851 (DMA_RX_SIZE - 1), chan);
1856 * stmmac_set_tx_queue_weight - Set TX queue weight
1857 * @priv: driver private structure
1858 * Description: It is used for setting TX queues weight
1860 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv)
1862 u32 tx_queues_count = priv->plat->tx_queues_to_use;
1866 for (queue = 0; queue < tx_queues_count; queue++) {
1867 weight = priv->plat->tx_queues_cfg[queue].weight;
1868 priv->hw->mac->set_mtl_tx_queue_weight(priv->hw, weight, queue);
1873 * stmmac_configure_cbs - Configure CBS in TX queue
1874 * @priv: driver private structure
1875 * Description: It is used for configuring CBS in AVB TX queues
1877 static void stmmac_configure_cbs(struct stmmac_priv *priv)
1879 u32 tx_queues_count = priv->plat->tx_queues_to_use;
1883 for (queue = 0; queue < tx_queues_count; queue++) {
1884 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use;
1885 if (mode_to_use == MTL_QUEUE_DCB)
1888 priv->hw->mac->config_cbs(priv->hw,
1889 priv->plat->tx_queues_cfg[queue].send_slope,
1890 priv->plat->tx_queues_cfg[queue].idle_slope,
1891 priv->plat->tx_queues_cfg[queue].high_credit,
1892 priv->plat->tx_queues_cfg[queue].low_credit,
1898 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel
1899 * @priv: driver private structure
1900 * Description: It is used for mapping RX queues to RX dma channels
1902 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv)
1904 u32 rx_queues_count = priv->plat->rx_queues_to_use;
1908 for (queue = 0; queue < rx_queues_count; queue++) {
1909 chan = priv->plat->rx_queues_cfg[queue].chan;
1910 priv->hw->mac->map_mtl_to_dma(priv->hw, queue, chan);
1915 * stmmac_mtl_configuration - Configure MTL
1916 * @priv: driver private structure
1917 * Description: It is used for configurring MTL
1919 static void stmmac_mtl_configuration(struct stmmac_priv *priv)
1921 u32 rx_queues_count = priv->plat->rx_queues_to_use;
1922 u32 tx_queues_count = priv->plat->tx_queues_to_use;
1924 if (tx_queues_count > 1 && priv->hw->mac->set_mtl_tx_queue_weight)
1925 stmmac_set_tx_queue_weight(priv);
1927 /* Configure MTL RX algorithms */
1928 if (rx_queues_count > 1 && priv->hw->mac->prog_mtl_rx_algorithms)
1929 priv->hw->mac->prog_mtl_rx_algorithms(priv->hw,
1930 priv->plat->rx_sched_algorithm);
1932 /* Configure MTL TX algorithms */
1933 if (tx_queues_count > 1 && priv->hw->mac->prog_mtl_tx_algorithms)
1934 priv->hw->mac->prog_mtl_tx_algorithms(priv->hw,
1935 priv->plat->tx_sched_algorithm);
1937 /* Configure CBS in AVB TX queues */
1938 if (tx_queues_count > 1 && priv->hw->mac->config_cbs)
1939 stmmac_configure_cbs(priv);
1941 /* Map RX MTL to DMA channels */
1942 if (rx_queues_count > 1 && priv->hw->mac->map_mtl_to_dma)
1943 stmmac_rx_queue_dma_chan_map(priv);
1945 /* Enable MAC RX Queues */
1946 if (rx_queues_count > 1 && priv->hw->mac->rx_queue_enable)
1947 stmmac_mac_enable_rx_queues(priv);
1949 /* Set the HW DMA mode and the COE */
1950 stmmac_dma_operation_mode(priv);
1954 * stmmac_hw_setup - setup mac in a usable state.
1955 * @dev : pointer to the device structure.
1957 * this is the main function to setup the HW in a usable state because the
1958 * dma engine is reset, the core registers are configured (e.g. AXI,
1959 * Checksum features, timers). The DMA is ready to start receiving and
1962 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1965 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
1967 struct stmmac_priv *priv = netdev_priv(dev);
1968 u32 rx_cnt = priv->plat->rx_queues_to_use;
1969 u32 tx_cnt = priv->plat->tx_queues_to_use;
1973 /* DMA initialization and SW reset */
1974 ret = stmmac_init_dma_engine(priv);
1976 netdev_err(priv->dev, "%s: DMA engine initialization failed\n",
1981 /* Copy the MAC addr into the HW */
1982 priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0);
1984 /* PS and related bits will be programmed according to the speed */
1985 if (priv->hw->pcs) {
1986 int speed = priv->plat->mac_port_sel_speed;
1988 if ((speed == SPEED_10) || (speed == SPEED_100) ||
1989 (speed == SPEED_1000)) {
1990 priv->hw->ps = speed;
1992 dev_warn(priv->device, "invalid port speed\n");
1997 /* Initialize the MAC Core */
1998 priv->hw->mac->core_init(priv->hw, dev->mtu);
2001 if (priv->synopsys_id >= DWMAC_CORE_4_00)
2002 stmmac_mtl_configuration(priv);
2004 ret = priv->hw->mac->rx_ipc(priv->hw);
2006 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n");
2007 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
2008 priv->hw->rx_csum = 0;
2011 /* Enable the MAC Rx/Tx */
2012 if (priv->synopsys_id >= DWMAC_CORE_4_00)
2013 stmmac_dwmac4_set_mac(priv->ioaddr, true);
2015 stmmac_set_mac(priv->ioaddr, true);
2017 stmmac_mmc_setup(priv);
2020 ret = clk_prepare_enable(priv->plat->clk_ptp_ref);
2022 netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret);
2024 ret = stmmac_init_ptp(priv);
2025 if (ret == -EOPNOTSUPP)
2026 netdev_warn(priv->dev, "PTP not supported by HW\n");
2028 netdev_warn(priv->dev, "PTP init failed\n");
2031 #ifdef CONFIG_DEBUG_FS
2032 ret = stmmac_init_fs(dev);
2034 netdev_warn(priv->dev, "%s: failed debugFS registration\n",
2037 /* Start the ball rolling... */
2038 stmmac_start_all_dma(priv);
2040 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
2042 if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
2043 priv->rx_riwt = MAX_DMA_RIWT;
2044 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT, rx_cnt);
2047 if (priv->hw->pcs && priv->hw->mac->pcs_ctrl_ane)
2048 priv->hw->mac->pcs_ctrl_ane(priv->hw, 1, priv->hw->ps, 0);
2050 /* set TX and RX rings length */
2051 stmmac_set_rings_length(priv);
2055 for (chan = 0; chan < tx_cnt; chan++)
2056 priv->hw->dma->enable_tso(priv->ioaddr, 1, chan);
2062 static void stmmac_hw_teardown(struct net_device *dev)
2064 struct stmmac_priv *priv = netdev_priv(dev);
2066 clk_disable_unprepare(priv->plat->clk_ptp_ref);
2070 * stmmac_open - open entry point of the driver
2071 * @dev : pointer to the device structure.
2073 * This function is the open entry point of the driver.
2075 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2078 static int stmmac_open(struct net_device *dev)
2080 struct stmmac_priv *priv = netdev_priv(dev);
2083 stmmac_check_ether_addr(priv);
2085 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
2086 priv->hw->pcs != STMMAC_PCS_TBI &&
2087 priv->hw->pcs != STMMAC_PCS_RTBI) {
2088 ret = stmmac_init_phy(dev);
2090 netdev_err(priv->dev,
2091 "%s: Cannot attach to PHY (error: %d)\n",
2097 /* Extra statistics */
2098 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
2099 priv->xstats.threshold = tc;
2101 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
2102 priv->rx_copybreak = STMMAC_RX_COPYBREAK;
2104 ret = alloc_dma_desc_resources(priv);
2106 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n",
2108 goto dma_desc_error;
2111 ret = init_dma_desc_rings(dev, GFP_KERNEL);
2113 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n",
2118 ret = stmmac_hw_setup(dev, true);
2120 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__);
2124 stmmac_init_tx_coalesce(priv);
2127 phy_start(dev->phydev);
2129 /* Request the IRQ lines */
2130 ret = request_irq(dev->irq, stmmac_interrupt,
2131 IRQF_SHARED, dev->name, dev);
2132 if (unlikely(ret < 0)) {
2133 netdev_err(priv->dev,
2134 "%s: ERROR: allocating the IRQ %d (error: %d)\n",
2135 __func__, dev->irq, ret);
2139 /* Request the Wake IRQ in case of another line is used for WoL */
2140 if (priv->wol_irq != dev->irq) {
2141 ret = request_irq(priv->wol_irq, stmmac_interrupt,
2142 IRQF_SHARED, dev->name, dev);
2143 if (unlikely(ret < 0)) {
2144 netdev_err(priv->dev,
2145 "%s: ERROR: allocating the WoL IRQ %d (%d)\n",
2146 __func__, priv->wol_irq, ret);
2151 /* Request the IRQ lines */
2152 if (priv->lpi_irq > 0) {
2153 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
2155 if (unlikely(ret < 0)) {
2156 netdev_err(priv->dev,
2157 "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
2158 __func__, priv->lpi_irq, ret);
2163 napi_enable(&priv->napi);
2164 netif_start_queue(dev);
2169 if (priv->wol_irq != dev->irq)
2170 free_irq(priv->wol_irq, dev);
2172 free_irq(dev->irq, dev);
2175 phy_stop(dev->phydev);
2177 del_timer_sync(&priv->txtimer);
2178 stmmac_hw_teardown(dev);
2180 free_dma_desc_resources(priv);
2183 phy_disconnect(dev->phydev);
2189 * stmmac_release - close entry point of the driver
2190 * @dev : device pointer.
2192 * This is the stop entry point of the driver.
2194 static int stmmac_release(struct net_device *dev)
2196 struct stmmac_priv *priv = netdev_priv(dev);
2198 if (priv->eee_enabled)
2199 del_timer_sync(&priv->eee_ctrl_timer);
2201 /* Stop and disconnect the PHY */
2203 phy_stop(dev->phydev);
2204 phy_disconnect(dev->phydev);
2207 netif_stop_queue(dev);
2209 napi_disable(&priv->napi);
2211 del_timer_sync(&priv->txtimer);
2213 /* Free the IRQ lines */
2214 free_irq(dev->irq, dev);
2215 if (priv->wol_irq != dev->irq)
2216 free_irq(priv->wol_irq, dev);
2217 if (priv->lpi_irq > 0)
2218 free_irq(priv->lpi_irq, dev);
2220 /* Stop TX/RX DMA and clear the descriptors */
2221 stmmac_stop_all_dma(priv);
2223 /* Release and free the Rx/Tx resources */
2224 free_dma_desc_resources(priv);
2226 /* Disable the MAC Rx/Tx */
2227 stmmac_set_mac(priv->ioaddr, false);
2229 netif_carrier_off(dev);
2231 #ifdef CONFIG_DEBUG_FS
2232 stmmac_exit_fs(dev);
2235 stmmac_release_ptp(priv);
2241 * stmmac_tso_allocator - close entry point of the driver
2242 * @priv: driver private structure
2243 * @des: buffer start address
2244 * @total_len: total length to fill in descriptors
2245 * @last_segmant: condition for the last descriptor
2247 * This function fills descriptor and request new descriptors according to
2248 * buffer length to fill
2250 static void stmmac_tso_allocator(struct stmmac_priv *priv, unsigned int des,
2251 int total_len, bool last_segment)
2253 struct dma_desc *desc;
2257 tmp_len = total_len;
2259 while (tmp_len > 0) {
2260 priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE);
2261 desc = priv->dma_tx + priv->cur_tx;
2263 desc->des0 = cpu_to_le32(des + (total_len - tmp_len));
2264 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?
2265 TSO_MAX_BUFF_SIZE : tmp_len;
2267 priv->hw->desc->prepare_tso_tx_desc(desc, 0, buff_size,
2269 (last_segment) && (buff_size < TSO_MAX_BUFF_SIZE),
2272 tmp_len -= TSO_MAX_BUFF_SIZE;
2277 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
2278 * @skb : the socket buffer
2279 * @dev : device pointer
2280 * Description: this is the transmit function that is called on TSO frames
2281 * (support available on GMAC4 and newer chips).
2282 * Diagram below show the ring programming in case of TSO frames:
2286 * | DES0 |---> buffer1 = L2/L3/L4 header
2287 * | DES1 |---> TCP Payload (can continue on next descr...)
2288 * | DES2 |---> buffer 1 and 2 len
2289 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
2295 * | DES0 | --| Split TCP Payload on Buffers 1 and 2
2297 * | DES2 | --> buffer 1 and 2 len
2301 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
2303 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
2306 int tmp_pay_len = 0;
2307 struct stmmac_priv *priv = netdev_priv(dev);
2308 int nfrags = skb_shinfo(skb)->nr_frags;
2309 unsigned int first_entry, des;
2310 struct dma_desc *desc, *first, *mss_desc = NULL;
2314 /* Compute header lengths */
2315 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2317 /* Desc availability based on threshold should be enough safe */
2318 if (unlikely(stmmac_tx_avail(priv) <
2319 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) {
2320 if (!netif_queue_stopped(dev)) {
2321 netif_stop_queue(dev);
2322 /* This is a hard error, log it. */
2323 netdev_err(priv->dev,
2324 "%s: Tx Ring full when queue awake\n",
2327 return NETDEV_TX_BUSY;
2330 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */
2332 mss = skb_shinfo(skb)->gso_size;
2334 /* set new MSS value if needed */
2335 if (mss != priv->mss) {
2336 mss_desc = priv->dma_tx + priv->cur_tx;
2337 priv->hw->desc->set_mss(mss_desc, mss);
2339 priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE);
2342 if (netif_msg_tx_queued(priv)) {
2343 pr_info("%s: tcphdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
2344 __func__, tcp_hdrlen(skb), proto_hdr_len, pay_len, mss);
2345 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len,
2349 first_entry = priv->cur_tx;
2351 desc = priv->dma_tx + first_entry;
2354 /* first descriptor: fill Headers on Buf1 */
2355 des = dma_map_single(priv->device, skb->data, skb_headlen(skb),
2357 if (dma_mapping_error(priv->device, des))
2360 priv->tx_skbuff_dma[first_entry].buf = des;
2361 priv->tx_skbuff_dma[first_entry].len = skb_headlen(skb);
2362 priv->tx_skbuff[first_entry] = skb;
2364 first->des0 = cpu_to_le32(des);
2366 /* Fill start of payload in buff2 of first descriptor */
2368 first->des1 = cpu_to_le32(des + proto_hdr_len);
2370 /* If needed take extra descriptors to fill the remaining payload */
2371 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE;
2373 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0));
2375 /* Prepare fragments */
2376 for (i = 0; i < nfrags; i++) {
2377 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2379 des = skb_frag_dma_map(priv->device, frag, 0,
2380 skb_frag_size(frag),
2382 if (dma_mapping_error(priv->device, des))
2385 stmmac_tso_allocator(priv, des, skb_frag_size(frag),
2388 priv->tx_skbuff_dma[priv->cur_tx].buf = des;
2389 priv->tx_skbuff_dma[priv->cur_tx].len = skb_frag_size(frag);
2390 priv->tx_skbuff[priv->cur_tx] = NULL;
2391 priv->tx_skbuff_dma[priv->cur_tx].map_as_page = true;
2394 priv->tx_skbuff_dma[priv->cur_tx].last_segment = true;
2396 priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE);
2398 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
2399 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
2401 netif_stop_queue(dev);
2404 dev->stats.tx_bytes += skb->len;
2405 priv->xstats.tx_tso_frames++;
2406 priv->xstats.tx_tso_nfrags += nfrags;
2408 /* Manage tx mitigation */
2409 priv->tx_count_frames += nfrags + 1;
2410 if (likely(priv->tx_coal_frames > priv->tx_count_frames)) {
2411 mod_timer(&priv->txtimer,
2412 STMMAC_COAL_TIMER(priv->tx_coal_timer));
2414 priv->tx_count_frames = 0;
2415 priv->hw->desc->set_tx_ic(desc);
2416 priv->xstats.tx_set_ic_bit++;
2419 if (!priv->hwts_tx_en)
2420 skb_tx_timestamp(skb);
2422 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2423 priv->hwts_tx_en)) {
2424 /* declare that device is doing timestamping */
2425 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2426 priv->hw->desc->enable_tx_timestamp(first);
2429 /* Complete the first descriptor before granting the DMA */
2430 priv->hw->desc->prepare_tso_tx_desc(first, 1,
2433 1, priv->tx_skbuff_dma[first_entry].last_segment,
2434 tcp_hdrlen(skb) / 4, (skb->len - proto_hdr_len));
2436 /* If context desc is used to change MSS */
2438 priv->hw->desc->set_tx_owner(mss_desc);
2440 /* The own bit must be the latest setting done when prepare the
2441 * descriptor and then barrier is needed to make sure that
2442 * all is coherent before granting the DMA engine.
2446 if (netif_msg_pktdata(priv)) {
2447 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
2448 __func__, priv->cur_tx, priv->dirty_tx, first_entry,
2449 priv->cur_tx, first, nfrags);
2451 priv->hw->desc->display_ring((void *)priv->dma_tx, DMA_TX_SIZE,
2454 pr_info(">>> frame to be transmitted: ");
2455 print_pkt(skb->data, skb_headlen(skb));
2458 netdev_sent_queue(dev, skb->len);
2460 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr,
2463 return NETDEV_TX_OK;
2466 dev_err(priv->device, "Tx dma map failed\n");
2468 priv->dev->stats.tx_dropped++;
2469 return NETDEV_TX_OK;
2473 * stmmac_xmit - Tx entry point of the driver
2474 * @skb : the socket buffer
2475 * @dev : device pointer
2476 * Description : this is the tx entry point of the driver.
2477 * It programs the chain or the ring and supports oversized frames
2480 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
2482 struct stmmac_priv *priv = netdev_priv(dev);
2483 unsigned int nopaged_len = skb_headlen(skb);
2484 int i, csum_insertion = 0, is_jumbo = 0;
2485 int nfrags = skb_shinfo(skb)->nr_frags;
2486 unsigned int entry, first_entry;
2487 struct dma_desc *desc, *first;
2488 unsigned int enh_desc;
2491 /* Manage oversized TCP frames for GMAC4 device */
2492 if (skb_is_gso(skb) && priv->tso) {
2493 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2494 return stmmac_tso_xmit(skb, dev);
2497 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
2498 if (!netif_queue_stopped(dev)) {
2499 netif_stop_queue(dev);
2500 /* This is a hard error, log it. */
2501 netdev_err(priv->dev,
2502 "%s: Tx Ring full when queue awake\n",
2505 return NETDEV_TX_BUSY;
2508 if (priv->tx_path_in_lpi_mode)
2509 stmmac_disable_eee_mode(priv);
2511 entry = priv->cur_tx;
2512 first_entry = entry;
2514 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
2516 if (likely(priv->extend_desc))
2517 desc = (struct dma_desc *)(priv->dma_etx + entry);
2519 desc = priv->dma_tx + entry;
2523 priv->tx_skbuff[first_entry] = skb;
2525 enh_desc = priv->plat->enh_desc;
2526 /* To program the descriptors according to the size of the frame */
2528 is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc);
2530 if (unlikely(is_jumbo) && likely(priv->synopsys_id <
2532 entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion);
2533 if (unlikely(entry < 0))
2537 for (i = 0; i < nfrags; i++) {
2538 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2539 int len = skb_frag_size(frag);
2540 bool last_segment = (i == (nfrags - 1));
2542 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
2544 if (likely(priv->extend_desc))
2545 desc = (struct dma_desc *)(priv->dma_etx + entry);
2547 desc = priv->dma_tx + entry;
2549 des = skb_frag_dma_map(priv->device, frag, 0, len,
2551 if (dma_mapping_error(priv->device, des))
2552 goto dma_map_err; /* should reuse desc w/o issues */
2554 priv->tx_skbuff[entry] = NULL;
2556 priv->tx_skbuff_dma[entry].buf = des;
2557 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
2558 desc->des0 = cpu_to_le32(des);
2560 desc->des2 = cpu_to_le32(des);
2562 priv->tx_skbuff_dma[entry].map_as_page = true;
2563 priv->tx_skbuff_dma[entry].len = len;
2564 priv->tx_skbuff_dma[entry].last_segment = last_segment;
2566 /* Prepare the descriptor and set the own bit too */
2567 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
2568 priv->mode, 1, last_segment);
2571 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
2573 priv->cur_tx = entry;
2575 if (netif_msg_pktdata(priv)) {
2578 netdev_dbg(priv->dev,
2579 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
2580 __func__, priv->cur_tx, priv->dirty_tx, first_entry,
2581 entry, first, nfrags);
2583 if (priv->extend_desc)
2584 tx_head = (void *)priv->dma_etx;
2586 tx_head = (void *)priv->dma_tx;
2588 priv->hw->desc->display_ring(tx_head, DMA_TX_SIZE, false);
2590 netdev_dbg(priv->dev, ">>> frame to be transmitted: ");
2591 print_pkt(skb->data, skb->len);
2594 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
2595 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
2597 netif_stop_queue(dev);
2600 dev->stats.tx_bytes += skb->len;
2602 /* According to the coalesce parameter the IC bit for the latest
2603 * segment is reset and the timer re-started to clean the tx status.
2604 * This approach takes care about the fragments: desc is the first
2605 * element in case of no SG.
2607 priv->tx_count_frames += nfrags + 1;
2608 if (likely(priv->tx_coal_frames > priv->tx_count_frames)) {
2609 mod_timer(&priv->txtimer,
2610 STMMAC_COAL_TIMER(priv->tx_coal_timer));
2612 priv->tx_count_frames = 0;
2613 priv->hw->desc->set_tx_ic(desc);
2614 priv->xstats.tx_set_ic_bit++;
2617 if (!priv->hwts_tx_en)
2618 skb_tx_timestamp(skb);
2620 /* Ready to fill the first descriptor and set the OWN bit w/o any
2621 * problems because all the descriptors are actually ready to be
2622 * passed to the DMA engine.
2624 if (likely(!is_jumbo)) {
2625 bool last_segment = (nfrags == 0);
2627 des = dma_map_single(priv->device, skb->data,
2628 nopaged_len, DMA_TO_DEVICE);
2629 if (dma_mapping_error(priv->device, des))
2632 priv->tx_skbuff_dma[first_entry].buf = des;
2633 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
2634 first->des0 = cpu_to_le32(des);
2636 first->des2 = cpu_to_le32(des);
2638 priv->tx_skbuff_dma[first_entry].len = nopaged_len;
2639 priv->tx_skbuff_dma[first_entry].last_segment = last_segment;
2641 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2642 priv->hwts_tx_en)) {
2643 /* declare that device is doing timestamping */
2644 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2645 priv->hw->desc->enable_tx_timestamp(first);
2648 /* Prepare the first descriptor setting the OWN bit too */
2649 priv->hw->desc->prepare_tx_desc(first, 1, nopaged_len,
2650 csum_insertion, priv->mode, 1,
2653 /* The own bit must be the latest setting done when prepare the
2654 * descriptor and then barrier is needed to make sure that
2655 * all is coherent before granting the DMA engine.
2660 netdev_sent_queue(dev, skb->len);
2662 if (priv->synopsys_id < DWMAC_CORE_4_00)
2663 priv->hw->dma->enable_dma_transmission(priv->ioaddr);
2665 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr,
2668 return NETDEV_TX_OK;
2671 netdev_err(priv->dev, "Tx DMA map failed\n");
2673 priv->dev->stats.tx_dropped++;
2674 return NETDEV_TX_OK;
2677 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
2679 struct ethhdr *ehdr;
2682 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) ==
2683 NETIF_F_HW_VLAN_CTAG_RX &&
2684 !__vlan_get_tag(skb, &vlanid)) {
2685 /* pop the vlan tag */
2686 ehdr = (struct ethhdr *)skb->data;
2687 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
2688 skb_pull(skb, VLAN_HLEN);
2689 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
2694 static inline int stmmac_rx_threshold_count(struct stmmac_priv *priv)
2696 if (priv->rx_zeroc_thresh < STMMAC_RX_THRESH)
2703 * stmmac_rx_refill - refill used skb preallocated buffers
2704 * @priv: driver private structure
2705 * Description : this is to reallocate the skb for the reception process
2706 * that is based on zero-copy.
2708 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
2710 int bfsize = priv->dma_buf_sz;
2711 unsigned int entry = priv->dirty_rx;
2712 int dirty = stmmac_rx_dirty(priv);
2714 while (dirty-- > 0) {
2717 if (priv->extend_desc)
2718 p = (struct dma_desc *)(priv->dma_erx + entry);
2720 p = priv->dma_rx + entry;
2722 if (likely(priv->rx_skbuff[entry] == NULL)) {
2723 struct sk_buff *skb;
2725 skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
2726 if (unlikely(!skb)) {
2727 /* so for a while no zero-copy! */
2728 priv->rx_zeroc_thresh = STMMAC_RX_THRESH;
2729 if (unlikely(net_ratelimit()))
2730 dev_err(priv->device,
2731 "fail to alloc skb entry %d\n",
2736 priv->rx_skbuff[entry] = skb;
2737 priv->rx_skbuff_dma[entry] =
2738 dma_map_single(priv->device, skb->data, bfsize,
2740 if (dma_mapping_error(priv->device,
2741 priv->rx_skbuff_dma[entry])) {
2742 netdev_err(priv->dev, "Rx DMA map failed\n");
2747 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) {
2748 p->des0 = cpu_to_le32(priv->rx_skbuff_dma[entry]);
2751 p->des2 = cpu_to_le32(priv->rx_skbuff_dma[entry]);
2753 if (priv->hw->mode->refill_desc3)
2754 priv->hw->mode->refill_desc3(priv, p);
2756 if (priv->rx_zeroc_thresh > 0)
2757 priv->rx_zeroc_thresh--;
2759 netif_dbg(priv, rx_status, priv->dev,
2760 "refill entry #%d\n", entry);
2764 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
2765 priv->hw->desc->init_rx_desc(p, priv->use_riwt, 0, 0);
2767 priv->hw->desc->set_rx_owner(p);
2771 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE);
2773 priv->dirty_rx = entry;
2777 * stmmac_rx - manage the receive process
2778 * @priv: driver private structure
2779 * @limit: napi bugget.
2780 * Description : this the function called by the napi poll method.
2781 * It gets all the frames inside the ring.
2783 static int stmmac_rx(struct stmmac_priv *priv, int limit)
2785 unsigned int entry = priv->cur_rx;
2786 unsigned int next_entry;
2787 unsigned int count = 0;
2788 int coe = priv->hw->rx_csum;
2790 if (netif_msg_rx_status(priv)) {
2793 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
2794 if (priv->extend_desc)
2795 rx_head = (void *)priv->dma_erx;
2797 rx_head = (void *)priv->dma_rx;
2799 priv->hw->desc->display_ring(rx_head, DMA_RX_SIZE, true);
2801 while (count < limit) {
2804 struct dma_desc *np;
2806 if (priv->extend_desc)
2807 p = (struct dma_desc *)(priv->dma_erx + entry);
2809 p = priv->dma_rx + entry;
2811 /* read the status of the incoming frame */
2812 status = priv->hw->desc->rx_status(&priv->dev->stats,
2814 /* check if managed by the DMA otherwise go ahead */
2815 if (unlikely(status & dma_own))
2820 priv->cur_rx = STMMAC_GET_ENTRY(priv->cur_rx, DMA_RX_SIZE);
2821 next_entry = priv->cur_rx;
2823 if (priv->extend_desc)
2824 np = (struct dma_desc *)(priv->dma_erx + next_entry);
2826 np = priv->dma_rx + next_entry;
2830 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
2831 priv->hw->desc->rx_extended_status(&priv->dev->stats,
2835 if (unlikely(status == discard_frame)) {
2836 priv->dev->stats.rx_errors++;
2837 if (priv->hwts_rx_en && !priv->extend_desc) {
2838 /* DESC2 & DESC3 will be overwritten by device
2839 * with timestamp value, hence reinitialize
2840 * them in stmmac_rx_refill() function so that
2841 * device can reuse it.
2843 priv->rx_skbuff[entry] = NULL;
2844 dma_unmap_single(priv->device,
2845 priv->rx_skbuff_dma[entry],
2850 struct sk_buff *skb;
2854 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
2855 des = le32_to_cpu(p->des0);
2857 des = le32_to_cpu(p->des2);
2859 frame_len = priv->hw->desc->get_rx_frame_len(p, coe);
2861 /* If frame length is greater than skb buffer size
2862 * (preallocated during init) then the packet is
2865 if (frame_len > priv->dma_buf_sz) {
2866 netdev_err(priv->dev,
2867 "len %d larger than size (%d)\n",
2868 frame_len, priv->dma_buf_sz);
2869 priv->dev->stats.rx_length_errors++;
2873 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
2874 * Type frames (LLC/LLC-SNAP)
2876 if (unlikely(status != llc_snap))
2877 frame_len -= ETH_FCS_LEN;
2879 if (netif_msg_rx_status(priv)) {
2880 netdev_dbg(priv->dev, "\tdesc: %p [entry %d] buff=0x%x\n",
2882 if (frame_len > ETH_FRAME_LEN)
2883 netdev_dbg(priv->dev, "frame size %d, COE: %d\n",
2887 /* The zero-copy is always used for all the sizes
2888 * in case of GMAC4 because it needs
2889 * to refill the used descriptors, always.
2891 if (unlikely(!priv->plat->has_gmac4 &&
2892 ((frame_len < priv->rx_copybreak) ||
2893 stmmac_rx_threshold_count(priv)))) {
2894 skb = netdev_alloc_skb_ip_align(priv->dev,
2896 if (unlikely(!skb)) {
2897 if (net_ratelimit())
2898 dev_warn(priv->device,
2899 "packet dropped\n");
2900 priv->dev->stats.rx_dropped++;
2904 dma_sync_single_for_cpu(priv->device,
2908 skb_copy_to_linear_data(skb,
2910 rx_skbuff[entry]->data,
2913 skb_put(skb, frame_len);
2914 dma_sync_single_for_device(priv->device,
2919 skb = priv->rx_skbuff[entry];
2920 if (unlikely(!skb)) {
2921 netdev_err(priv->dev,
2922 "%s: Inconsistent Rx chain\n",
2924 priv->dev->stats.rx_dropped++;
2927 prefetch(skb->data - NET_IP_ALIGN);
2928 priv->rx_skbuff[entry] = NULL;
2929 priv->rx_zeroc_thresh++;
2931 skb_put(skb, frame_len);
2932 dma_unmap_single(priv->device,
2933 priv->rx_skbuff_dma[entry],
2938 if (netif_msg_pktdata(priv)) {
2939 netdev_dbg(priv->dev, "frame received (%dbytes)",
2941 print_pkt(skb->data, frame_len);
2944 stmmac_get_rx_hwtstamp(priv, p, np, skb);
2946 stmmac_rx_vlan(priv->dev, skb);
2948 skb->protocol = eth_type_trans(skb, priv->dev);
2951 skb_checksum_none_assert(skb);
2953 skb->ip_summed = CHECKSUM_UNNECESSARY;
2955 napi_gro_receive(&priv->napi, skb);
2957 priv->dev->stats.rx_packets++;
2958 priv->dev->stats.rx_bytes += frame_len;
2963 stmmac_rx_refill(priv);
2965 priv->xstats.rx_pkt_n += count;
2971 * stmmac_poll - stmmac poll method (NAPI)
2972 * @napi : pointer to the napi structure.
2973 * @budget : maximum number of packets that the current CPU can receive from
2976 * To look at the incoming frames and clear the tx resources.
2978 static int stmmac_poll(struct napi_struct *napi, int budget)
2980 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
2982 u32 chan = STMMAC_CHAN0;
2984 priv->xstats.napi_poll++;
2985 stmmac_tx_clean(priv);
2987 work_done = stmmac_rx(priv, budget);
2988 if (work_done < budget) {
2989 napi_complete_done(napi, work_done);
2990 stmmac_enable_dma_irq(priv, chan);
2997 * @dev : Pointer to net device structure
2998 * Description: this function is called when a packet transmission fails to
2999 * complete within a reasonable time. The driver will mark the error in the
3000 * netdev structure and arrange for the device to be reset to a sane state
3001 * in order to transmit a new packet.
3003 static void stmmac_tx_timeout(struct net_device *dev)
3005 struct stmmac_priv *priv = netdev_priv(dev);
3006 u32 chan = STMMAC_CHAN0;
3008 /* Clear Tx resources and restart transmitting again */
3009 stmmac_tx_err(priv, chan);
3013 * stmmac_set_rx_mode - entry point for multicast addressing
3014 * @dev : pointer to the device structure
3016 * This function is a driver entry point which gets called by the kernel
3017 * whenever multicast addresses must be enabled/disabled.
3021 static void stmmac_set_rx_mode(struct net_device *dev)
3023 struct stmmac_priv *priv = netdev_priv(dev);
3025 priv->hw->mac->set_filter(priv->hw, dev);
3029 * stmmac_change_mtu - entry point to change MTU size for the device.
3030 * @dev : device pointer.
3031 * @new_mtu : the new MTU size for the device.
3032 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
3033 * to drive packet transmission. Ethernet has an MTU of 1500 octets
3034 * (ETH_DATA_LEN). This value can be changed with ifconfig.
3036 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3039 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
3041 struct stmmac_priv *priv = netdev_priv(dev);
3043 if (netif_running(dev)) {
3044 netdev_err(priv->dev, "must be stopped to change its MTU\n");
3050 netdev_update_features(dev);
3055 static netdev_features_t stmmac_fix_features(struct net_device *dev,
3056 netdev_features_t features)
3058 struct stmmac_priv *priv = netdev_priv(dev);
3060 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
3061 features &= ~NETIF_F_RXCSUM;
3063 if (!priv->plat->tx_coe)
3064 features &= ~NETIF_F_CSUM_MASK;
3066 /* Some GMAC devices have a bugged Jumbo frame support that
3067 * needs to have the Tx COE disabled for oversized frames
3068 * (due to limited buffer sizes). In this case we disable
3069 * the TX csum insertion in the TDES and not use SF.
3071 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
3072 features &= ~NETIF_F_CSUM_MASK;
3074 /* Disable tso if asked by ethtool */
3075 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
3076 if (features & NETIF_F_TSO)
3085 static int stmmac_set_features(struct net_device *netdev,
3086 netdev_features_t features)
3088 struct stmmac_priv *priv = netdev_priv(netdev);
3090 /* Keep the COE Type in case of csum is supporting */
3091 if (features & NETIF_F_RXCSUM)
3092 priv->hw->rx_csum = priv->plat->rx_coe;
3094 priv->hw->rx_csum = 0;
3095 /* No check needed because rx_coe has been set before and it will be
3096 * fixed in case of issue.
3098 priv->hw->mac->rx_ipc(priv->hw);
3104 * stmmac_interrupt - main ISR
3105 * @irq: interrupt number.
3106 * @dev_id: to pass the net device pointer.
3107 * Description: this is the main driver interrupt service routine.
3109 * o DMA service routine (to manage incoming frame reception and transmission
3111 * o Core interrupts to manage: remote wake-up, management counter, LPI
3114 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
3116 struct net_device *dev = (struct net_device *)dev_id;
3117 struct stmmac_priv *priv = netdev_priv(dev);
3120 pm_wakeup_event(priv->device, 0);
3122 if (unlikely(!dev)) {
3123 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
3127 /* To handle GMAC own interrupts */
3128 if ((priv->plat->has_gmac) || (priv->plat->has_gmac4)) {
3129 int status = priv->hw->mac->host_irq_status(priv->hw,
3132 if (priv->synopsys_id >= DWMAC_CORE_4_00)
3133 status |= priv->hw->mac->host_mtl_irq_status(priv->hw,
3136 if (unlikely(status)) {
3137 /* For LPI we need to save the tx status */
3138 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
3139 priv->tx_path_in_lpi_mode = true;
3140 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
3141 priv->tx_path_in_lpi_mode = false;
3142 if (status & CORE_IRQ_MTL_RX_OVERFLOW && priv->hw->dma->set_rx_tail_ptr)
3143 priv->hw->dma->set_rx_tail_ptr(priv->ioaddr,
3148 /* PCS link status */
3149 if (priv->hw->pcs) {
3150 if (priv->xstats.pcs_link)
3151 netif_carrier_on(dev);
3153 netif_carrier_off(dev);
3157 /* To handle DMA interrupts */
3158 stmmac_dma_interrupt(priv);
3163 #ifdef CONFIG_NET_POLL_CONTROLLER
3164 /* Polling receive - used by NETCONSOLE and other diagnostic tools
3165 * to allow network I/O with interrupts disabled.
3167 static void stmmac_poll_controller(struct net_device *dev)
3169 disable_irq(dev->irq);
3170 stmmac_interrupt(dev->irq, dev);
3171 enable_irq(dev->irq);
3176 * stmmac_ioctl - Entry point for the Ioctl
3177 * @dev: Device pointer.
3178 * @rq: An IOCTL specefic structure, that can contain a pointer to
3179 * a proprietary structure used to pass information to the driver.
3180 * @cmd: IOCTL command
3182 * Currently it supports the phy_mii_ioctl(...) and HW time stamping.
3184 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3186 int ret = -EOPNOTSUPP;
3188 if (!netif_running(dev))
3197 ret = phy_mii_ioctl(dev->phydev, rq, cmd);
3200 ret = stmmac_hwtstamp_ioctl(dev, rq);
3209 #ifdef CONFIG_DEBUG_FS
3210 static struct dentry *stmmac_fs_dir;
3212 static void sysfs_display_ring(void *head, int size, int extend_desc,
3213 struct seq_file *seq)
3216 struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
3217 struct dma_desc *p = (struct dma_desc *)head;
3219 for (i = 0; i < size; i++) {
3221 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
3222 i, (unsigned int)virt_to_phys(ep),
3223 le32_to_cpu(ep->basic.des0),
3224 le32_to_cpu(ep->basic.des1),
3225 le32_to_cpu(ep->basic.des2),
3226 le32_to_cpu(ep->basic.des3));
3229 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
3230 i, (unsigned int)virt_to_phys(ep),
3231 le32_to_cpu(p->des0), le32_to_cpu(p->des1),
3232 le32_to_cpu(p->des2), le32_to_cpu(p->des3));
3235 seq_printf(seq, "\n");
3239 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
3241 struct net_device *dev = seq->private;
3242 struct stmmac_priv *priv = netdev_priv(dev);
3244 if (priv->extend_desc) {
3245 seq_printf(seq, "Extended RX descriptor ring:\n");
3246 sysfs_display_ring((void *)priv->dma_erx, DMA_RX_SIZE, 1, seq);
3247 seq_printf(seq, "Extended TX descriptor ring:\n");
3248 sysfs_display_ring((void *)priv->dma_etx, DMA_TX_SIZE, 1, seq);
3250 seq_printf(seq, "RX descriptor ring:\n");
3251 sysfs_display_ring((void *)priv->dma_rx, DMA_RX_SIZE, 0, seq);
3252 seq_printf(seq, "TX descriptor ring:\n");
3253 sysfs_display_ring((void *)priv->dma_tx, DMA_TX_SIZE, 0, seq);
3259 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
3261 return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
3264 /* Debugfs files, should appear in /sys/kernel/debug/stmmaceth/eth0 */
3266 static const struct file_operations stmmac_rings_status_fops = {
3267 .owner = THIS_MODULE,
3268 .open = stmmac_sysfs_ring_open,
3270 .llseek = seq_lseek,
3271 .release = single_release,
3274 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
3276 struct net_device *dev = seq->private;
3277 struct stmmac_priv *priv = netdev_priv(dev);
3279 if (!priv->hw_cap_support) {
3280 seq_printf(seq, "DMA HW features not supported\n");
3284 seq_printf(seq, "==============================\n");
3285 seq_printf(seq, "\tDMA HW features\n");
3286 seq_printf(seq, "==============================\n");
3288 seq_printf(seq, "\t10/100 Mbps: %s\n",
3289 (priv->dma_cap.mbps_10_100) ? "Y" : "N");
3290 seq_printf(seq, "\t1000 Mbps: %s\n",
3291 (priv->dma_cap.mbps_1000) ? "Y" : "N");
3292 seq_printf(seq, "\tHalf duplex: %s\n",
3293 (priv->dma_cap.half_duplex) ? "Y" : "N");
3294 seq_printf(seq, "\tHash Filter: %s\n",
3295 (priv->dma_cap.hash_filter) ? "Y" : "N");
3296 seq_printf(seq, "\tMultiple MAC address registers: %s\n",
3297 (priv->dma_cap.multi_addr) ? "Y" : "N");
3298 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n",
3299 (priv->dma_cap.pcs) ? "Y" : "N");
3300 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
3301 (priv->dma_cap.sma_mdio) ? "Y" : "N");
3302 seq_printf(seq, "\tPMT Remote wake up: %s\n",
3303 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
3304 seq_printf(seq, "\tPMT Magic Frame: %s\n",
3305 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
3306 seq_printf(seq, "\tRMON module: %s\n",
3307 (priv->dma_cap.rmon) ? "Y" : "N");
3308 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
3309 (priv->dma_cap.time_stamp) ? "Y" : "N");
3310 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n",
3311 (priv->dma_cap.atime_stamp) ? "Y" : "N");
3312 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n",
3313 (priv->dma_cap.eee) ? "Y" : "N");
3314 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
3315 seq_printf(seq, "\tChecksum Offload in TX: %s\n",
3316 (priv->dma_cap.tx_coe) ? "Y" : "N");
3317 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
3318 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n",
3319 (priv->dma_cap.rx_coe) ? "Y" : "N");
3321 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
3322 (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
3323 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
3324 (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
3326 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
3327 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
3328 seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
3329 priv->dma_cap.number_rx_channel);
3330 seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
3331 priv->dma_cap.number_tx_channel);
3332 seq_printf(seq, "\tEnhanced descriptors: %s\n",
3333 (priv->dma_cap.enh_desc) ? "Y" : "N");
3338 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
3340 return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
3343 static const struct file_operations stmmac_dma_cap_fops = {
3344 .owner = THIS_MODULE,
3345 .open = stmmac_sysfs_dma_cap_open,
3347 .llseek = seq_lseek,
3348 .release = single_release,
3351 static int stmmac_init_fs(struct net_device *dev)
3353 struct stmmac_priv *priv = netdev_priv(dev);
3355 /* Create per netdev entries */
3356 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
3358 if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) {
3359 netdev_err(priv->dev, "ERROR failed to create debugfs directory\n");
3364 /* Entry to report DMA RX/TX rings */
3365 priv->dbgfs_rings_status =
3366 debugfs_create_file("descriptors_status", S_IRUGO,
3367 priv->dbgfs_dir, dev,
3368 &stmmac_rings_status_fops);
3370 if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) {
3371 netdev_err(priv->dev, "ERROR creating stmmac ring debugfs file\n");
3372 debugfs_remove_recursive(priv->dbgfs_dir);
3377 /* Entry to report the DMA HW features */
3378 priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", S_IRUGO,
3380 dev, &stmmac_dma_cap_fops);
3382 if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) {
3383 netdev_err(priv->dev, "ERROR creating stmmac MMC debugfs file\n");
3384 debugfs_remove_recursive(priv->dbgfs_dir);
3392 static void stmmac_exit_fs(struct net_device *dev)
3394 struct stmmac_priv *priv = netdev_priv(dev);
3396 debugfs_remove_recursive(priv->dbgfs_dir);
3398 #endif /* CONFIG_DEBUG_FS */
3400 static const struct net_device_ops stmmac_netdev_ops = {
3401 .ndo_open = stmmac_open,
3402 .ndo_start_xmit = stmmac_xmit,
3403 .ndo_stop = stmmac_release,
3404 .ndo_change_mtu = stmmac_change_mtu,
3405 .ndo_fix_features = stmmac_fix_features,
3406 .ndo_set_features = stmmac_set_features,
3407 .ndo_set_rx_mode = stmmac_set_rx_mode,
3408 .ndo_tx_timeout = stmmac_tx_timeout,
3409 .ndo_do_ioctl = stmmac_ioctl,
3410 #ifdef CONFIG_NET_POLL_CONTROLLER
3411 .ndo_poll_controller = stmmac_poll_controller,
3413 .ndo_set_mac_address = eth_mac_addr,
3417 * stmmac_hw_init - Init the MAC device
3418 * @priv: driver private structure
3419 * Description: this function is to configure the MAC device according to
3420 * some platform parameters or the HW capability register. It prepares the
3421 * driver to use either ring or chain modes and to setup either enhanced or
3422 * normal descriptors.
3424 static int stmmac_hw_init(struct stmmac_priv *priv)
3426 struct mac_device_info *mac;
3428 /* Identify the MAC HW device */
3429 if (priv->plat->has_gmac) {
3430 priv->dev->priv_flags |= IFF_UNICAST_FLT;
3431 mac = dwmac1000_setup(priv->ioaddr,
3432 priv->plat->multicast_filter_bins,
3433 priv->plat->unicast_filter_entries,
3434 &priv->synopsys_id);
3435 } else if (priv->plat->has_gmac4) {
3436 priv->dev->priv_flags |= IFF_UNICAST_FLT;
3437 mac = dwmac4_setup(priv->ioaddr,
3438 priv->plat->multicast_filter_bins,
3439 priv->plat->unicast_filter_entries,
3440 &priv->synopsys_id);
3442 mac = dwmac100_setup(priv->ioaddr, &priv->synopsys_id);
3449 /* To use the chained or ring mode */
3450 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
3451 priv->hw->mode = &dwmac4_ring_mode_ops;
3454 priv->hw->mode = &chain_mode_ops;
3455 dev_info(priv->device, "Chain mode enabled\n");
3456 priv->mode = STMMAC_CHAIN_MODE;
3458 priv->hw->mode = &ring_mode_ops;
3459 dev_info(priv->device, "Ring mode enabled\n");
3460 priv->mode = STMMAC_RING_MODE;
3464 /* Get the HW capability (new GMAC newer than 3.50a) */
3465 priv->hw_cap_support = stmmac_get_hw_features(priv);
3466 if (priv->hw_cap_support) {
3467 dev_info(priv->device, "DMA HW capability register supported\n");
3469 /* We can override some gmac/dma configuration fields: e.g.
3470 * enh_desc, tx_coe (e.g. that are passed through the
3471 * platform) with the values from the HW capability
3472 * register (if supported).
3474 priv->plat->enh_desc = priv->dma_cap.enh_desc;
3475 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
3476 priv->hw->pmt = priv->plat->pmt;
3478 /* TXCOE doesn't work in thresh DMA mode */
3479 if (priv->plat->force_thresh_dma_mode)
3480 priv->plat->tx_coe = 0;
3482 priv->plat->tx_coe = priv->dma_cap.tx_coe;
3484 /* In case of GMAC4 rx_coe is from HW cap register. */
3485 priv->plat->rx_coe = priv->dma_cap.rx_coe;
3487 if (priv->dma_cap.rx_coe_type2)
3488 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
3489 else if (priv->dma_cap.rx_coe_type1)
3490 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
3493 dev_info(priv->device, "No HW DMA feature register supported\n");
3496 /* To use alternate (extended), normal or GMAC4 descriptor structures */
3497 if (priv->synopsys_id >= DWMAC_CORE_4_00)
3498 priv->hw->desc = &dwmac4_desc_ops;
3500 stmmac_selec_desc_mode(priv);
3502 if (priv->plat->rx_coe) {
3503 priv->hw->rx_csum = priv->plat->rx_coe;
3504 dev_info(priv->device, "RX Checksum Offload Engine supported\n");
3505 if (priv->synopsys_id < DWMAC_CORE_4_00)
3506 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum);
3508 if (priv->plat->tx_coe)
3509 dev_info(priv->device, "TX Checksum insertion supported\n");
3511 if (priv->plat->pmt) {
3512 dev_info(priv->device, "Wake-Up On Lan supported\n");
3513 device_set_wakeup_capable(priv->device, 1);
3516 if (priv->dma_cap.tsoen)
3517 dev_info(priv->device, "TSO supported\n");
3524 * @device: device pointer
3525 * @plat_dat: platform data pointer
3526 * @res: stmmac resource pointer
3527 * Description: this is the main probe function used to
3528 * call the alloc_etherdev, allocate the priv structure.
3530 * returns 0 on success, otherwise errno.
3532 int stmmac_dvr_probe(struct device *device,
3533 struct plat_stmmacenet_data *plat_dat,
3534 struct stmmac_resources *res)
3537 struct net_device *ndev = NULL;
3538 struct stmmac_priv *priv;
3540 ndev = alloc_etherdev(sizeof(struct stmmac_priv));
3544 SET_NETDEV_DEV(ndev, device);
3546 priv = netdev_priv(ndev);
3547 priv->device = device;
3550 stmmac_set_ethtool_ops(ndev);
3551 priv->pause = pause;
3552 priv->plat = plat_dat;
3553 priv->ioaddr = res->addr;
3554 priv->dev->base_addr = (unsigned long)res->addr;
3556 priv->dev->irq = res->irq;
3557 priv->wol_irq = res->wol_irq;
3558 priv->lpi_irq = res->lpi_irq;
3561 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
3563 dev_set_drvdata(device, priv->dev);
3565 /* Verify driver arguments */
3566 stmmac_verify_args();
3568 /* Override with kernel parameters if supplied XXX CRS XXX
3569 * this needs to have multiple instances
3571 if ((phyaddr >= 0) && (phyaddr <= 31))
3572 priv->plat->phy_addr = phyaddr;
3574 if (priv->plat->stmmac_rst)
3575 reset_control_deassert(priv->plat->stmmac_rst);
3577 /* Init MAC and get the capabilities */
3578 ret = stmmac_hw_init(priv);
3582 ndev->netdev_ops = &stmmac_netdev_ops;
3584 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3587 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
3588 ndev->hw_features |= NETIF_F_TSO;
3590 dev_info(priv->device, "TSO feature enabled\n");
3592 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
3593 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
3594 #ifdef STMMAC_VLAN_TAG_USED
3595 /* Both mac100 and gmac support receive VLAN tag detection */
3596 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3598 priv->msg_enable = netif_msg_init(debug, default_msg_level);
3600 /* MTU range: 46 - hw-specific max */
3601 ndev->min_mtu = ETH_ZLEN - ETH_HLEN;
3602 if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00))
3603 ndev->max_mtu = JUMBO_LEN;
3605 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
3606 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu
3607 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range.
3609 if ((priv->plat->maxmtu < ndev->max_mtu) &&
3610 (priv->plat->maxmtu >= ndev->min_mtu))
3611 ndev->max_mtu = priv->plat->maxmtu;
3612 else if (priv->plat->maxmtu < ndev->min_mtu)
3613 dev_warn(priv->device,
3614 "%s: warning: maxmtu having invalid value (%d)\n",
3615 __func__, priv->plat->maxmtu);
3618 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
3620 /* Rx Watchdog is available in the COREs newer than the 3.40.
3621 * In some case, for example on bugged HW this feature
3622 * has to be disable and this can be done by passing the
3623 * riwt_off field from the platform.
3625 if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
3627 dev_info(priv->device,
3628 "Enable RX Mitigation via HW Watchdog Timer\n");
3631 netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
3633 spin_lock_init(&priv->lock);
3635 /* If a specific clk_csr value is passed from the platform
3636 * this means that the CSR Clock Range selection cannot be
3637 * changed at run-time and it is fixed. Viceversa the driver'll try to
3638 * set the MDC clock dynamically according to the csr actual
3641 if (!priv->plat->clk_csr)
3642 stmmac_clk_csr_set(priv);
3644 priv->clk_csr = priv->plat->clk_csr;
3646 stmmac_check_pcs_mode(priv);
3648 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
3649 priv->hw->pcs != STMMAC_PCS_TBI &&
3650 priv->hw->pcs != STMMAC_PCS_RTBI) {
3651 /* MDIO bus Registration */
3652 ret = stmmac_mdio_register(ndev);
3654 dev_err(priv->device,
3655 "%s: MDIO bus (id: %d) registration failed",
3656 __func__, priv->plat->bus_id);
3657 goto error_mdio_register;
3661 ret = register_netdev(ndev);
3663 dev_err(priv->device, "%s: ERROR %i registering the device\n",
3665 goto error_netdev_register;
3670 error_netdev_register:
3671 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
3672 priv->hw->pcs != STMMAC_PCS_TBI &&
3673 priv->hw->pcs != STMMAC_PCS_RTBI)
3674 stmmac_mdio_unregister(ndev);
3675 error_mdio_register:
3676 netif_napi_del(&priv->napi);
3682 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
3686 * @dev: device pointer
3687 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
3688 * changes the link status, releases the DMA descriptor rings.
3690 int stmmac_dvr_remove(struct device *dev)
3692 struct net_device *ndev = dev_get_drvdata(dev);
3693 struct stmmac_priv *priv = netdev_priv(ndev);
3695 netdev_info(priv->dev, "%s: removing driver", __func__);
3697 stmmac_stop_all_dma(priv);
3699 stmmac_set_mac(priv->ioaddr, false);
3700 netif_carrier_off(ndev);
3701 unregister_netdev(ndev);
3702 if (priv->plat->stmmac_rst)
3703 reset_control_assert(priv->plat->stmmac_rst);
3704 clk_disable_unprepare(priv->plat->pclk);
3705 clk_disable_unprepare(priv->plat->stmmac_clk);
3706 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
3707 priv->hw->pcs != STMMAC_PCS_TBI &&
3708 priv->hw->pcs != STMMAC_PCS_RTBI)
3709 stmmac_mdio_unregister(ndev);
3714 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
3717 * stmmac_suspend - suspend callback
3718 * @dev: device pointer
3719 * Description: this is the function to suspend the device and it is called
3720 * by the platform driver to stop the network queue, release the resources,
3721 * program the PMT register (for WoL), clean and release driver resources.
3723 int stmmac_suspend(struct device *dev)
3725 struct net_device *ndev = dev_get_drvdata(dev);
3726 struct stmmac_priv *priv = netdev_priv(ndev);
3727 unsigned long flags;
3729 if (!ndev || !netif_running(ndev))
3733 phy_stop(ndev->phydev);
3735 spin_lock_irqsave(&priv->lock, flags);
3737 netif_device_detach(ndev);
3738 netif_stop_queue(ndev);
3740 napi_disable(&priv->napi);
3742 /* Stop TX/RX DMA */
3743 stmmac_stop_all_dma(priv);
3745 /* Enable Power down mode by programming the PMT regs */
3746 if (device_may_wakeup(priv->device)) {
3747 priv->hw->mac->pmt(priv->hw, priv->wolopts);
3750 stmmac_set_mac(priv->ioaddr, false);
3751 pinctrl_pm_select_sleep_state(priv->device);
3752 /* Disable clock in case of PWM is off */
3753 clk_disable(priv->plat->pclk);
3754 clk_disable(priv->plat->stmmac_clk);
3756 spin_unlock_irqrestore(&priv->lock, flags);
3759 priv->speed = SPEED_UNKNOWN;
3760 priv->oldduplex = DUPLEX_UNKNOWN;
3763 EXPORT_SYMBOL_GPL(stmmac_suspend);
3766 * stmmac_resume - resume callback
3767 * @dev: device pointer
3768 * Description: when resume this function is invoked to setup the DMA and CORE
3769 * in a usable state.
3771 int stmmac_resume(struct device *dev)
3773 struct net_device *ndev = dev_get_drvdata(dev);
3774 struct stmmac_priv *priv = netdev_priv(ndev);
3775 unsigned long flags;
3777 if (!netif_running(ndev))
3780 /* Power Down bit, into the PM register, is cleared
3781 * automatically as soon as a magic packet or a Wake-up frame
3782 * is received. Anyway, it's better to manually clear
3783 * this bit because it can generate problems while resuming
3784 * from another devices (e.g. serial console).
3786 if (device_may_wakeup(priv->device)) {
3787 spin_lock_irqsave(&priv->lock, flags);
3788 priv->hw->mac->pmt(priv->hw, 0);
3789 spin_unlock_irqrestore(&priv->lock, flags);
3792 pinctrl_pm_select_default_state(priv->device);
3793 /* enable the clk previously disabled */
3794 clk_enable(priv->plat->stmmac_clk);
3795 clk_enable(priv->plat->pclk);
3796 /* reset the phy so that it's ready */
3798 stmmac_mdio_reset(priv->mii);
3801 netif_device_attach(ndev);
3803 spin_lock_irqsave(&priv->lock, flags);
3809 /* reset private mss value to force mss context settings at
3810 * next tso xmit (only used for gmac4).
3814 stmmac_clear_descriptors(priv);
3816 stmmac_hw_setup(ndev, false);
3817 stmmac_init_tx_coalesce(priv);
3818 stmmac_set_rx_mode(ndev);
3820 napi_enable(&priv->napi);
3822 netif_start_queue(ndev);
3824 spin_unlock_irqrestore(&priv->lock, flags);
3827 phy_start(ndev->phydev);
3831 EXPORT_SYMBOL_GPL(stmmac_resume);
3834 static int __init stmmac_cmdline_opt(char *str)
3840 while ((opt = strsep(&str, ",")) != NULL) {
3841 if (!strncmp(opt, "debug:", 6)) {
3842 if (kstrtoint(opt + 6, 0, &debug))
3844 } else if (!strncmp(opt, "phyaddr:", 8)) {
3845 if (kstrtoint(opt + 8, 0, &phyaddr))
3847 } else if (!strncmp(opt, "buf_sz:", 7)) {
3848 if (kstrtoint(opt + 7, 0, &buf_sz))
3850 } else if (!strncmp(opt, "tc:", 3)) {
3851 if (kstrtoint(opt + 3, 0, &tc))
3853 } else if (!strncmp(opt, "watchdog:", 9)) {
3854 if (kstrtoint(opt + 9, 0, &watchdog))
3856 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
3857 if (kstrtoint(opt + 10, 0, &flow_ctrl))
3859 } else if (!strncmp(opt, "pause:", 6)) {
3860 if (kstrtoint(opt + 6, 0, &pause))
3862 } else if (!strncmp(opt, "eee_timer:", 10)) {
3863 if (kstrtoint(opt + 10, 0, &eee_timer))
3865 } else if (!strncmp(opt, "chain_mode:", 11)) {
3866 if (kstrtoint(opt + 11, 0, &chain_mode))
3873 pr_err("%s: ERROR broken module parameter conversion", __func__);
3877 __setup("stmmaceth=", stmmac_cmdline_opt);
3880 static int __init stmmac_init(void)
3882 #ifdef CONFIG_DEBUG_FS
3883 /* Create debugfs main directory if it doesn't exist yet */
3884 if (!stmmac_fs_dir) {
3885 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
3887 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
3888 pr_err("ERROR %s, debugfs create directory failed\n",
3889 STMMAC_RESOURCE_NAME);
3899 static void __exit stmmac_exit(void)
3901 #ifdef CONFIG_DEBUG_FS
3902 debugfs_remove_recursive(stmmac_fs_dir);
3906 module_init(stmmac_init)
3907 module_exit(stmmac_exit)
3909 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
3910 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
3911 MODULE_LICENSE("GPL");