1 /*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
5 Copyright(C) 2007-2011 STMicroelectronics Ltd
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 The full GNU General Public License is included in this distribution in
17 the file called "COPYING".
19 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
21 Documentation available at:
22 http://www.stlinux.com
24 https://bugzilla.stlinux.com/
25 *******************************************************************************/
27 #include <linux/clk.h>
28 #include <linux/kernel.h>
29 #include <linux/interrupt.h>
31 #include <linux/tcp.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/if_ether.h>
35 #include <linux/crc32.h>
36 #include <linux/mii.h>
38 #include <linux/if_vlan.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/slab.h>
41 #include <linux/prefetch.h>
42 #include <linux/pinctrl/consumer.h>
43 #ifdef CONFIG_DEBUG_FS
44 #include <linux/debugfs.h>
45 #include <linux/seq_file.h>
46 #endif /* CONFIG_DEBUG_FS */
47 #include <linux/net_tstamp.h>
48 #include "stmmac_ptp.h"
50 #include <linux/reset.h>
51 #include <linux/of_mdio.h>
52 #include "dwmac1000.h"
54 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
55 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1)
57 /* Module parameters */
59 static int watchdog = TX_TIMEO;
60 module_param(watchdog, int, S_IRUGO | S_IWUSR);
61 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
63 static int debug = -1;
64 module_param(debug, int, S_IRUGO | S_IWUSR);
65 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
67 static int phyaddr = -1;
68 module_param(phyaddr, int, S_IRUGO);
69 MODULE_PARM_DESC(phyaddr, "Physical device address");
71 #define STMMAC_TX_THRESH (DMA_TX_SIZE / 4)
72 #define STMMAC_RX_THRESH (DMA_RX_SIZE / 4)
74 static int flow_ctrl = FLOW_OFF;
75 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
76 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
78 static int pause = PAUSE_TIME;
79 module_param(pause, int, S_IRUGO | S_IWUSR);
80 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
83 static int tc = TC_DEFAULT;
84 module_param(tc, int, S_IRUGO | S_IWUSR);
85 MODULE_PARM_DESC(tc, "DMA threshold control value");
87 #define DEFAULT_BUFSIZE 1536
88 static int buf_sz = DEFAULT_BUFSIZE;
89 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
90 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
92 #define STMMAC_RX_COPYBREAK 256
94 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
95 NETIF_MSG_LINK | NETIF_MSG_IFUP |
96 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
98 #define STMMAC_DEFAULT_LPI_TIMER 1000
99 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
100 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
101 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
102 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
104 /* By default the driver will use the ring mode to manage tx and rx descriptors,
105 * but allow user to force to use the chain instead of the ring
107 static unsigned int chain_mode;
108 module_param(chain_mode, int, S_IRUGO);
109 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
111 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
113 #ifdef CONFIG_DEBUG_FS
114 static int stmmac_init_fs(struct net_device *dev);
115 static void stmmac_exit_fs(struct net_device *dev);
118 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
121 * stmmac_verify_args - verify the driver parameters.
122 * Description: it checks the driver parameters and set a default in case of
125 static void stmmac_verify_args(void)
127 if (unlikely(watchdog < 0))
129 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
130 buf_sz = DEFAULT_BUFSIZE;
131 if (unlikely(flow_ctrl > 1))
132 flow_ctrl = FLOW_AUTO;
133 else if (likely(flow_ctrl < 0))
134 flow_ctrl = FLOW_OFF;
135 if (unlikely((pause < 0) || (pause > 0xffff)))
138 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
142 * stmmac_disable_all_queues - Disable all queues
143 * @priv: driver private structure
145 static void stmmac_disable_all_queues(struct stmmac_priv *priv)
147 u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
150 for (queue = 0; queue < rx_queues_cnt; queue++) {
151 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
153 napi_disable(&rx_q->napi);
158 * stmmac_enable_all_queues - Enable all queues
159 * @priv: driver private structure
161 static void stmmac_enable_all_queues(struct stmmac_priv *priv)
163 u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
166 for (queue = 0; queue < rx_queues_cnt; queue++) {
167 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
169 napi_enable(&rx_q->napi);
174 * stmmac_stop_all_queues - Stop all queues
175 * @priv: driver private structure
177 static void stmmac_stop_all_queues(struct stmmac_priv *priv)
179 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
182 for (queue = 0; queue < tx_queues_cnt; queue++)
183 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
187 * stmmac_start_all_queues - Start all queues
188 * @priv: driver private structure
190 static void stmmac_start_all_queues(struct stmmac_priv *priv)
192 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
195 for (queue = 0; queue < tx_queues_cnt; queue++)
196 netif_tx_start_queue(netdev_get_tx_queue(priv->dev, queue));
200 * stmmac_clk_csr_set - dynamically set the MDC clock
201 * @priv: driver private structure
202 * Description: this is to dynamically set the MDC clock according to the csr
205 * If a specific clk_csr value is passed from the platform
206 * this means that the CSR Clock Range selection cannot be
207 * changed at run-time and it is fixed (as reported in the driver
208 * documentation). Viceversa the driver will try to set the MDC
209 * clock dynamically according to the actual clock input.
211 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
215 clk_rate = clk_get_rate(priv->plat->stmmac_clk);
217 /* Platform provided default clk_csr would be assumed valid
218 * for all other cases except for the below mentioned ones.
219 * For values higher than the IEEE 802.3 specified frequency
220 * we can not estimate the proper divider as it is not known
221 * the frequency of clk_csr_i. So we do not change the default
224 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
225 if (clk_rate < CSR_F_35M)
226 priv->clk_csr = STMMAC_CSR_20_35M;
227 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
228 priv->clk_csr = STMMAC_CSR_35_60M;
229 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
230 priv->clk_csr = STMMAC_CSR_60_100M;
231 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
232 priv->clk_csr = STMMAC_CSR_100_150M;
233 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
234 priv->clk_csr = STMMAC_CSR_150_250M;
235 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
236 priv->clk_csr = STMMAC_CSR_250_300M;
240 static void print_pkt(unsigned char *buf, int len)
242 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
243 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
246 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue)
248 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
251 if (tx_q->dirty_tx > tx_q->cur_tx)
252 avail = tx_q->dirty_tx - tx_q->cur_tx - 1;
254 avail = DMA_TX_SIZE - tx_q->cur_tx + tx_q->dirty_tx - 1;
260 * stmmac_rx_dirty - Get RX queue dirty
261 * @priv: driver private structure
262 * @queue: RX queue index
264 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue)
266 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
269 if (rx_q->dirty_rx <= rx_q->cur_rx)
270 dirty = rx_q->cur_rx - rx_q->dirty_rx;
272 dirty = DMA_RX_SIZE - rx_q->dirty_rx + rx_q->cur_rx;
278 * stmmac_hw_fix_mac_speed - callback for speed selection
279 * @priv: driver private structure
280 * Description: on some platforms (e.g. ST), some HW system configuration
281 * registers have to be set according to the link speed negotiated.
283 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
285 struct net_device *ndev = priv->dev;
286 struct phy_device *phydev = ndev->phydev;
288 if (likely(priv->plat->fix_mac_speed))
289 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
293 * stmmac_enable_eee_mode - check and enter in LPI mode
294 * @priv: driver private structure
295 * Description: this function is to verify and enter in LPI mode in case of
298 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
300 u32 tx_cnt = priv->plat->tx_queues_to_use;
303 /* check if all TX queues have the work finished */
304 for (queue = 0; queue < tx_cnt; queue++) {
305 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
307 if (tx_q->dirty_tx != tx_q->cur_tx)
308 return; /* still unfinished work */
311 /* Check and enter in LPI mode */
312 if (!priv->tx_path_in_lpi_mode)
313 priv->hw->mac->set_eee_mode(priv->hw,
314 priv->plat->en_tx_lpi_clockgating);
318 * stmmac_disable_eee_mode - disable and exit from LPI mode
319 * @priv: driver private structure
320 * Description: this function is to exit and disable EEE in case of
321 * LPI state is true. This is called by the xmit.
323 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
325 priv->hw->mac->reset_eee_mode(priv->hw);
326 del_timer_sync(&priv->eee_ctrl_timer);
327 priv->tx_path_in_lpi_mode = false;
331 * stmmac_eee_ctrl_timer - EEE TX SW timer.
334 * if there is no data transfer and if we are not in LPI state,
335 * then MAC Transmitter can be moved to LPI state.
337 static void stmmac_eee_ctrl_timer(unsigned long arg)
339 struct stmmac_priv *priv = (struct stmmac_priv *)arg;
341 stmmac_enable_eee_mode(priv);
342 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
346 * stmmac_eee_init - init EEE
347 * @priv: driver private structure
349 * if the GMAC supports the EEE (from the HW cap reg) and the phy device
350 * can also manage EEE, this function enable the LPI state and start related
353 bool stmmac_eee_init(struct stmmac_priv *priv)
355 struct net_device *ndev = priv->dev;
359 /* Using PCS we cannot dial with the phy registers at this stage
360 * so we do not support extra feature like EEE.
362 if ((priv->hw->pcs == STMMAC_PCS_RGMII) ||
363 (priv->hw->pcs == STMMAC_PCS_TBI) ||
364 (priv->hw->pcs == STMMAC_PCS_RTBI))
367 /* MAC core supports the EEE feature. */
368 if (priv->dma_cap.eee) {
369 int tx_lpi_timer = priv->tx_lpi_timer;
371 /* Check if the PHY supports EEE */
372 if (phy_init_eee(ndev->phydev, 1)) {
373 /* To manage at run-time if the EEE cannot be supported
374 * anymore (for example because the lp caps have been
376 * In that case the driver disable own timers.
378 spin_lock_irqsave(&priv->lock, flags);
379 if (priv->eee_active) {
380 netdev_dbg(priv->dev, "disable EEE\n");
381 del_timer_sync(&priv->eee_ctrl_timer);
382 priv->hw->mac->set_eee_timer(priv->hw, 0,
385 priv->eee_active = 0;
386 spin_unlock_irqrestore(&priv->lock, flags);
389 /* Activate the EEE and start timers */
390 spin_lock_irqsave(&priv->lock, flags);
391 if (!priv->eee_active) {
392 priv->eee_active = 1;
393 setup_timer(&priv->eee_ctrl_timer,
394 stmmac_eee_ctrl_timer,
395 (unsigned long)priv);
396 mod_timer(&priv->eee_ctrl_timer,
397 STMMAC_LPI_T(eee_timer));
399 priv->hw->mac->set_eee_timer(priv->hw,
400 STMMAC_DEFAULT_LIT_LS,
403 /* Set HW EEE according to the speed */
404 priv->hw->mac->set_eee_pls(priv->hw, ndev->phydev->link);
407 spin_unlock_irqrestore(&priv->lock, flags);
409 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n");
415 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
416 * @priv: driver private structure
417 * @p : descriptor pointer
418 * @skb : the socket buffer
420 * This function will read timestamp from the descriptor & pass it to stack.
421 * and also perform some sanity checks.
423 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
424 struct dma_desc *p, struct sk_buff *skb)
426 struct skb_shared_hwtstamps shhwtstamp;
429 if (!priv->hwts_tx_en)
432 /* exit if skb doesn't support hw tstamp */
433 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
436 /* check tx tstamp status */
437 if (!priv->hw->desc->get_tx_timestamp_status(p)) {
438 /* get the valid tstamp */
439 ns = priv->hw->desc->get_timestamp(p, priv->adv_ts);
441 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
442 shhwtstamp.hwtstamp = ns_to_ktime(ns);
444 netdev_info(priv->dev, "get valid TX hw timestamp %llu\n", ns);
445 /* pass tstamp to stack */
446 skb_tstamp_tx(skb, &shhwtstamp);
452 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
453 * @priv: driver private structure
454 * @p : descriptor pointer
455 * @np : next descriptor pointer
456 * @skb : the socket buffer
458 * This function will read received packet's timestamp from the descriptor
459 * and pass it to stack. It also perform some sanity checks.
461 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p,
462 struct dma_desc *np, struct sk_buff *skb)
464 struct skb_shared_hwtstamps *shhwtstamp = NULL;
467 if (!priv->hwts_rx_en)
470 /* Check if timestamp is available */
471 if (!priv->hw->desc->get_rx_timestamp_status(p, priv->adv_ts)) {
472 /* For GMAC4, the valid timestamp is from CTX next desc. */
473 if (priv->plat->has_gmac4)
474 ns = priv->hw->desc->get_timestamp(np, priv->adv_ts);
476 ns = priv->hw->desc->get_timestamp(p, priv->adv_ts);
478 netdev_info(priv->dev, "get valid RX hw timestamp %llu\n", ns);
479 shhwtstamp = skb_hwtstamps(skb);
480 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
481 shhwtstamp->hwtstamp = ns_to_ktime(ns);
483 netdev_err(priv->dev, "cannot get RX hw timestamp\n");
488 * stmmac_hwtstamp_ioctl - control hardware timestamping.
489 * @dev: device pointer.
490 * @ifr: An IOCTL specific structure, that can contain a pointer to
491 * a proprietary structure used to pass information to the driver.
493 * This function configures the MAC to enable/disable both outgoing(TX)
494 * and incoming(RX) packets time stamping based on user input.
496 * 0 on success and an appropriate -ve integer on failure.
498 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
500 struct stmmac_priv *priv = netdev_priv(dev);
501 struct hwtstamp_config config;
502 struct timespec64 now;
506 u32 ptp_over_ipv4_udp = 0;
507 u32 ptp_over_ipv6_udp = 0;
508 u32 ptp_over_ethernet = 0;
509 u32 snap_type_sel = 0;
510 u32 ts_master_en = 0;
515 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
516 netdev_alert(priv->dev, "No support for HW time stamping\n");
517 priv->hwts_tx_en = 0;
518 priv->hwts_rx_en = 0;
523 if (copy_from_user(&config, ifr->ifr_data,
524 sizeof(struct hwtstamp_config)))
527 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
528 __func__, config.flags, config.tx_type, config.rx_filter);
530 /* reserved for future extensions */
534 if (config.tx_type != HWTSTAMP_TX_OFF &&
535 config.tx_type != HWTSTAMP_TX_ON)
539 switch (config.rx_filter) {
540 case HWTSTAMP_FILTER_NONE:
541 /* time stamp no incoming packet at all */
542 config.rx_filter = HWTSTAMP_FILTER_NONE;
545 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
546 /* PTP v1, UDP, any kind of event packet */
547 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
548 /* take time stamp for all event messages */
549 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
551 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
552 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
555 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
556 /* PTP v1, UDP, Sync packet */
557 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
558 /* take time stamp for SYNC messages only */
559 ts_event_en = PTP_TCR_TSEVNTENA;
561 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
562 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
565 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
566 /* PTP v1, UDP, Delay_req packet */
567 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
568 /* take time stamp for Delay_Req messages only */
569 ts_master_en = PTP_TCR_TSMSTRENA;
570 ts_event_en = PTP_TCR_TSEVNTENA;
572 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
573 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
576 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
577 /* PTP v2, UDP, any kind of event packet */
578 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
579 ptp_v2 = PTP_TCR_TSVER2ENA;
580 /* take time stamp for all event messages */
581 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
583 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
584 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
587 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
588 /* PTP v2, UDP, Sync packet */
589 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
590 ptp_v2 = PTP_TCR_TSVER2ENA;
591 /* take time stamp for SYNC messages only */
592 ts_event_en = PTP_TCR_TSEVNTENA;
594 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
595 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
598 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
599 /* PTP v2, UDP, Delay_req packet */
600 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
601 ptp_v2 = PTP_TCR_TSVER2ENA;
602 /* take time stamp for Delay_Req messages only */
603 ts_master_en = PTP_TCR_TSMSTRENA;
604 ts_event_en = PTP_TCR_TSEVNTENA;
606 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
607 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
610 case HWTSTAMP_FILTER_PTP_V2_EVENT:
611 /* PTP v2/802.AS1 any layer, any kind of event packet */
612 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
613 ptp_v2 = PTP_TCR_TSVER2ENA;
614 /* take time stamp for all event messages */
615 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
617 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
618 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
619 ptp_over_ethernet = PTP_TCR_TSIPENA;
622 case HWTSTAMP_FILTER_PTP_V2_SYNC:
623 /* PTP v2/802.AS1, any layer, Sync packet */
624 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
625 ptp_v2 = PTP_TCR_TSVER2ENA;
626 /* take time stamp for SYNC messages only */
627 ts_event_en = PTP_TCR_TSEVNTENA;
629 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
630 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
631 ptp_over_ethernet = PTP_TCR_TSIPENA;
634 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
635 /* PTP v2/802.AS1, any layer, Delay_req packet */
636 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
637 ptp_v2 = PTP_TCR_TSVER2ENA;
638 /* take time stamp for Delay_Req messages only */
639 ts_master_en = PTP_TCR_TSMSTRENA;
640 ts_event_en = PTP_TCR_TSEVNTENA;
642 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
643 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
644 ptp_over_ethernet = PTP_TCR_TSIPENA;
647 case HWTSTAMP_FILTER_ALL:
648 /* time stamp any incoming packet */
649 config.rx_filter = HWTSTAMP_FILTER_ALL;
650 tstamp_all = PTP_TCR_TSENALL;
657 switch (config.rx_filter) {
658 case HWTSTAMP_FILTER_NONE:
659 config.rx_filter = HWTSTAMP_FILTER_NONE;
662 /* PTP v1, UDP, any kind of event packet */
663 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
667 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
668 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
670 if (!priv->hwts_tx_en && !priv->hwts_rx_en)
671 priv->hw->ptp->config_hw_tstamping(priv->ptpaddr, 0);
673 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
674 tstamp_all | ptp_v2 | ptp_over_ethernet |
675 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
676 ts_master_en | snap_type_sel);
677 priv->hw->ptp->config_hw_tstamping(priv->ptpaddr, value);
679 /* program Sub Second Increment reg */
680 sec_inc = priv->hw->ptp->config_sub_second_increment(
681 priv->ptpaddr, priv->plat->clk_ptp_rate,
682 priv->plat->has_gmac4);
683 temp = div_u64(1000000000ULL, sec_inc);
685 /* calculate default added value:
687 * addend = (2^32)/freq_div_ratio;
688 * where, freq_div_ratio = 1e9ns/sec_inc
690 temp = (u64)(temp << 32);
691 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate);
692 priv->hw->ptp->config_addend(priv->ptpaddr,
693 priv->default_addend);
695 /* initialize system time */
696 ktime_get_real_ts64(&now);
698 /* lower 32 bits of tv_sec are safe until y2106 */
699 priv->hw->ptp->init_systime(priv->ptpaddr, (u32)now.tv_sec,
703 return copy_to_user(ifr->ifr_data, &config,
704 sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
708 * stmmac_init_ptp - init PTP
709 * @priv: driver private structure
710 * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
711 * This is done by looking at the HW cap. register.
712 * This function also registers the ptp driver.
714 static int stmmac_init_ptp(struct stmmac_priv *priv)
716 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
720 /* Check if adv_ts can be enabled for dwmac 4.x core */
721 if (priv->plat->has_gmac4 && priv->dma_cap.atime_stamp)
723 /* Dwmac 3.x core with extend_desc can support adv_ts */
724 else if (priv->extend_desc && priv->dma_cap.atime_stamp)
727 if (priv->dma_cap.time_stamp)
728 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n");
731 netdev_info(priv->dev,
732 "IEEE 1588-2008 Advanced Timestamp supported\n");
734 priv->hw->ptp = &stmmac_ptp;
735 priv->hwts_tx_en = 0;
736 priv->hwts_rx_en = 0;
738 stmmac_ptp_register(priv);
743 static void stmmac_release_ptp(struct stmmac_priv *priv)
745 if (priv->plat->clk_ptp_ref)
746 clk_disable_unprepare(priv->plat->clk_ptp_ref);
747 stmmac_ptp_unregister(priv);
751 * stmmac_mac_flow_ctrl - Configure flow control in all queues
752 * @priv: driver private structure
753 * Description: It is used for configuring the flow control in all queues
755 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex)
757 u32 tx_cnt = priv->plat->tx_queues_to_use;
759 priv->hw->mac->flow_ctrl(priv->hw, duplex, priv->flow_ctrl,
760 priv->pause, tx_cnt);
764 * stmmac_adjust_link - adjusts the link parameters
765 * @dev: net device structure
766 * Description: this is the helper called by the physical abstraction layer
767 * drivers to communicate the phy link status. According the speed and duplex
768 * this driver can invoke registered glue-logic as well.
769 * It also invoke the eee initialization because it could happen when switch
770 * on different networks (that are eee capable).
772 static void stmmac_adjust_link(struct net_device *dev)
774 struct stmmac_priv *priv = netdev_priv(dev);
775 struct phy_device *phydev = dev->phydev;
782 spin_lock_irqsave(&priv->lock, flags);
785 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
787 /* Now we make sure that we can be in full duplex mode.
788 * If not, we operate in half-duplex mode. */
789 if (phydev->duplex != priv->oldduplex) {
791 if (!(phydev->duplex))
792 ctrl &= ~priv->hw->link.duplex;
794 ctrl |= priv->hw->link.duplex;
795 priv->oldduplex = phydev->duplex;
797 /* Flow Control operation */
799 stmmac_mac_flow_ctrl(priv, phydev->duplex);
801 if (phydev->speed != priv->speed) {
803 switch (phydev->speed) {
805 if (priv->plat->has_gmac ||
806 priv->plat->has_gmac4)
807 ctrl &= ~priv->hw->link.port;
810 if (priv->plat->has_gmac ||
811 priv->plat->has_gmac4) {
812 ctrl |= priv->hw->link.port;
813 ctrl |= priv->hw->link.speed;
815 ctrl &= ~priv->hw->link.port;
819 if (priv->plat->has_gmac ||
820 priv->plat->has_gmac4) {
821 ctrl |= priv->hw->link.port;
822 ctrl &= ~(priv->hw->link.speed);
824 ctrl &= ~priv->hw->link.port;
828 netif_warn(priv, link, priv->dev,
829 "broken speed: %d\n", phydev->speed);
830 phydev->speed = SPEED_UNKNOWN;
833 if (phydev->speed != SPEED_UNKNOWN)
834 stmmac_hw_fix_mac_speed(priv);
835 priv->speed = phydev->speed;
838 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
840 if (!priv->oldlink) {
844 } else if (priv->oldlink) {
847 priv->speed = SPEED_UNKNOWN;
848 priv->oldduplex = DUPLEX_UNKNOWN;
851 if (new_state && netif_msg_link(priv))
852 phy_print_status(phydev);
854 spin_unlock_irqrestore(&priv->lock, flags);
856 if (phydev->is_pseudo_fixed_link)
857 /* Stop PHY layer to call the hook to adjust the link in case
858 * of a switch is attached to the stmmac driver.
860 phydev->irq = PHY_IGNORE_INTERRUPT;
862 /* At this stage, init the EEE if supported.
863 * Never called in case of fixed_link.
865 priv->eee_enabled = stmmac_eee_init(priv);
869 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
870 * @priv: driver private structure
871 * Description: this is to verify if the HW supports the PCS.
872 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
873 * configured for the TBI, RTBI, or SGMII PHY interface.
875 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
877 int interface = priv->plat->interface;
879 if (priv->dma_cap.pcs) {
880 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
881 (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
882 (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
883 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
884 netdev_dbg(priv->dev, "PCS RGMII support enabled\n");
885 priv->hw->pcs = STMMAC_PCS_RGMII;
886 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
887 netdev_dbg(priv->dev, "PCS SGMII support enabled\n");
888 priv->hw->pcs = STMMAC_PCS_SGMII;
894 * stmmac_init_phy - PHY initialization
895 * @dev: net device structure
896 * Description: it initializes the driver's PHY state, and attaches the PHY
901 static int stmmac_init_phy(struct net_device *dev)
903 struct stmmac_priv *priv = netdev_priv(dev);
904 struct phy_device *phydev;
905 char phy_id_fmt[MII_BUS_ID_SIZE + 3];
906 char bus_id[MII_BUS_ID_SIZE];
907 int interface = priv->plat->interface;
908 int max_speed = priv->plat->max_speed;
910 priv->speed = SPEED_UNKNOWN;
911 priv->oldduplex = DUPLEX_UNKNOWN;
913 if (priv->plat->phy_node) {
914 phydev = of_phy_connect(dev, priv->plat->phy_node,
915 &stmmac_adjust_link, 0, interface);
917 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
920 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
921 priv->plat->phy_addr);
922 netdev_dbg(priv->dev, "%s: trying to attach to %s\n", __func__,
925 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link,
929 if (IS_ERR_OR_NULL(phydev)) {
930 netdev_err(priv->dev, "Could not attach to PHY\n");
934 return PTR_ERR(phydev);
937 /* Stop Advertising 1000BASE Capability if interface is not GMII */
938 if ((interface == PHY_INTERFACE_MODE_MII) ||
939 (interface == PHY_INTERFACE_MODE_RMII) ||
940 (max_speed < 1000 && max_speed > 0))
941 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
942 SUPPORTED_1000baseT_Full);
945 * Broken HW is sometimes missing the pull-up resistor on the
946 * MDIO line, which results in reads to non-existent devices returning
947 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
949 * Note: phydev->phy_id is the result of reading the UID PHY registers.
951 if (!priv->plat->phy_node && phydev->phy_id == 0) {
952 phy_disconnect(phydev);
956 /* stmmac_adjust_link will change this to PHY_IGNORE_INTERRUPT to avoid
957 * subsequent PHY polling, make sure we force a link transition if
958 * we have a UP/DOWN/UP transition
960 if (phydev->is_pseudo_fixed_link)
961 phydev->irq = PHY_POLL;
963 phy_attached_info(phydev);
967 static void stmmac_display_rx_rings(struct stmmac_priv *priv)
969 u32 rx_cnt = priv->plat->rx_queues_to_use;
973 /* Display RX rings */
974 for (queue = 0; queue < rx_cnt; queue++) {
975 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
977 pr_info("\tRX Queue %u rings\n", queue);
979 if (priv->extend_desc)
980 head_rx = (void *)rx_q->dma_erx;
982 head_rx = (void *)rx_q->dma_rx;
984 /* Display RX ring */
985 priv->hw->desc->display_ring(head_rx, DMA_RX_SIZE, true);
989 static void stmmac_display_tx_rings(struct stmmac_priv *priv)
991 u32 tx_cnt = priv->plat->tx_queues_to_use;
995 /* Display TX rings */
996 for (queue = 0; queue < tx_cnt; queue++) {
997 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
999 pr_info("\tTX Queue %d rings\n", queue);
1001 if (priv->extend_desc)
1002 head_tx = (void *)tx_q->dma_etx;
1004 head_tx = (void *)tx_q->dma_tx;
1006 priv->hw->desc->display_ring(head_tx, DMA_TX_SIZE, false);
1010 static void stmmac_display_rings(struct stmmac_priv *priv)
1012 /* Display RX ring */
1013 stmmac_display_rx_rings(priv);
1015 /* Display TX ring */
1016 stmmac_display_tx_rings(priv);
1019 static int stmmac_set_bfsize(int mtu, int bufsize)
1023 if (mtu >= BUF_SIZE_4KiB)
1024 ret = BUF_SIZE_8KiB;
1025 else if (mtu >= BUF_SIZE_2KiB)
1026 ret = BUF_SIZE_4KiB;
1027 else if (mtu > DEFAULT_BUFSIZE)
1028 ret = BUF_SIZE_2KiB;
1030 ret = DEFAULT_BUFSIZE;
1036 * stmmac_clear_rx_descriptors - clear RX descriptors
1037 * @priv: driver private structure
1038 * @queue: RX queue index
1039 * Description: this function is called to clear the RX descriptors
1040 * in case of both basic and extended descriptors are used.
1042 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue)
1044 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1047 /* Clear the RX descriptors */
1048 for (i = 0; i < DMA_RX_SIZE; i++)
1049 if (priv->extend_desc)
1050 priv->hw->desc->init_rx_desc(&rx_q->dma_erx[i].basic,
1051 priv->use_riwt, priv->mode,
1052 (i == DMA_RX_SIZE - 1));
1054 priv->hw->desc->init_rx_desc(&rx_q->dma_rx[i],
1055 priv->use_riwt, priv->mode,
1056 (i == DMA_RX_SIZE - 1));
1060 * stmmac_clear_tx_descriptors - clear tx descriptors
1061 * @priv: driver private structure
1062 * @queue: TX queue index.
1063 * Description: this function is called to clear the TX descriptors
1064 * in case of both basic and extended descriptors are used.
1066 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue)
1068 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1071 /* Clear the TX descriptors */
1072 for (i = 0; i < DMA_TX_SIZE; i++)
1073 if (priv->extend_desc)
1074 priv->hw->desc->init_tx_desc(&tx_q->dma_etx[i].basic,
1076 (i == DMA_TX_SIZE - 1));
1078 priv->hw->desc->init_tx_desc(&tx_q->dma_tx[i],
1080 (i == DMA_TX_SIZE - 1));
1084 * stmmac_clear_descriptors - clear descriptors
1085 * @priv: driver private structure
1086 * Description: this function is called to clear the TX and RX descriptors
1087 * in case of both basic and extended descriptors are used.
1089 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
1091 u32 rx_queue_cnt = priv->plat->rx_queues_to_use;
1092 u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1095 /* Clear the RX descriptors */
1096 for (queue = 0; queue < rx_queue_cnt; queue++)
1097 stmmac_clear_rx_descriptors(priv, queue);
1099 /* Clear the TX descriptors */
1100 for (queue = 0; queue < tx_queue_cnt; queue++)
1101 stmmac_clear_tx_descriptors(priv, queue);
1105 * stmmac_init_rx_buffers - init the RX descriptor buffer.
1106 * @priv: driver private structure
1107 * @p: descriptor pointer
1108 * @i: descriptor index
1110 * @queue: RX queue index
1111 * Description: this function is called to allocate a receive buffer, perform
1112 * the DMA mapping and init the descriptor.
1114 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
1115 int i, gfp_t flags, u32 queue)
1117 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1118 struct sk_buff *skb;
1120 skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags);
1122 netdev_err(priv->dev,
1123 "%s: Rx init fails; skb is NULL\n", __func__);
1126 rx_q->rx_skbuff[i] = skb;
1127 rx_q->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
1130 if (dma_mapping_error(priv->device, rx_q->rx_skbuff_dma[i])) {
1131 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__);
1132 dev_kfree_skb_any(skb);
1136 if (priv->synopsys_id >= DWMAC_CORE_4_00)
1137 p->des0 = cpu_to_le32(rx_q->rx_skbuff_dma[i]);
1139 p->des2 = cpu_to_le32(rx_q->rx_skbuff_dma[i]);
1141 if ((priv->hw->mode->init_desc3) &&
1142 (priv->dma_buf_sz == BUF_SIZE_16KiB))
1143 priv->hw->mode->init_desc3(p);
1149 * stmmac_free_rx_buffer - free RX dma buffers
1150 * @priv: private structure
1151 * @queue: RX queue index
1154 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1156 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1158 if (rx_q->rx_skbuff[i]) {
1159 dma_unmap_single(priv->device, rx_q->rx_skbuff_dma[i],
1160 priv->dma_buf_sz, DMA_FROM_DEVICE);
1161 dev_kfree_skb_any(rx_q->rx_skbuff[i]);
1163 rx_q->rx_skbuff[i] = NULL;
1167 * stmmac_free_tx_buffer - free RX dma buffers
1168 * @priv: private structure
1169 * @queue: RX queue index
1172 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1174 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1176 if (tx_q->tx_skbuff_dma[i].buf) {
1177 if (tx_q->tx_skbuff_dma[i].map_as_page)
1178 dma_unmap_page(priv->device,
1179 tx_q->tx_skbuff_dma[i].buf,
1180 tx_q->tx_skbuff_dma[i].len,
1183 dma_unmap_single(priv->device,
1184 tx_q->tx_skbuff_dma[i].buf,
1185 tx_q->tx_skbuff_dma[i].len,
1189 if (tx_q->tx_skbuff[i]) {
1190 dev_kfree_skb_any(tx_q->tx_skbuff[i]);
1191 tx_q->tx_skbuff[i] = NULL;
1192 tx_q->tx_skbuff_dma[i].buf = 0;
1193 tx_q->tx_skbuff_dma[i].map_as_page = false;
1198 * init_dma_rx_desc_rings - init the RX descriptor rings
1199 * @dev: net device structure
1201 * Description: this function initializes the DMA RX descriptors
1202 * and allocates the socket buffers. It supports the chained and ring
1205 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags)
1207 struct stmmac_priv *priv = netdev_priv(dev);
1208 u32 rx_count = priv->plat->rx_queues_to_use;
1209 unsigned int bfsize = 0;
1214 if (priv->hw->mode->set_16kib_bfsize)
1215 bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu);
1217 if (bfsize < BUF_SIZE_16KiB)
1218 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1220 priv->dma_buf_sz = bfsize;
1222 /* RX INITIALIZATION */
1223 netif_dbg(priv, probe, priv->dev,
1224 "SKB addresses:\nskb\t\tskb data\tdma data\n");
1226 for (queue = 0; queue < rx_count; queue++) {
1227 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1229 netif_dbg(priv, probe, priv->dev,
1230 "(%s) dma_rx_phy=0x%08x\n", __func__,
1231 (u32)rx_q->dma_rx_phy);
1233 for (i = 0; i < DMA_RX_SIZE; i++) {
1236 if (priv->extend_desc)
1237 p = &((rx_q->dma_erx + i)->basic);
1239 p = rx_q->dma_rx + i;
1241 ret = stmmac_init_rx_buffers(priv, p, i, flags,
1244 goto err_init_rx_buffers;
1246 netif_dbg(priv, probe, priv->dev, "[%p]\t[%p]\t[%x]\n",
1247 rx_q->rx_skbuff[i], rx_q->rx_skbuff[i]->data,
1248 (unsigned int)rx_q->rx_skbuff_dma[i]);
1252 rx_q->dirty_rx = (unsigned int)(i - DMA_RX_SIZE);
1254 stmmac_clear_rx_descriptors(priv, queue);
1256 /* Setup the chained descriptor addresses */
1257 if (priv->mode == STMMAC_CHAIN_MODE) {
1258 if (priv->extend_desc)
1259 priv->hw->mode->init(rx_q->dma_erx,
1263 priv->hw->mode->init(rx_q->dma_rx,
1273 err_init_rx_buffers:
1274 while (queue >= 0) {
1276 stmmac_free_rx_buffer(priv, queue, i);
1289 * init_dma_tx_desc_rings - init the TX descriptor rings
1290 * @dev: net device structure.
1291 * Description: this function initializes the DMA TX descriptors
1292 * and allocates the socket buffers. It supports the chained and ring
1295 static int init_dma_tx_desc_rings(struct net_device *dev)
1297 struct stmmac_priv *priv = netdev_priv(dev);
1298 u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1302 for (queue = 0; queue < tx_queue_cnt; queue++) {
1303 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1305 netif_dbg(priv, probe, priv->dev,
1306 "(%s) dma_tx_phy=0x%08x\n", __func__,
1307 (u32)tx_q->dma_tx_phy);
1309 /* Setup the chained descriptor addresses */
1310 if (priv->mode == STMMAC_CHAIN_MODE) {
1311 if (priv->extend_desc)
1312 priv->hw->mode->init(tx_q->dma_etx,
1316 priv->hw->mode->init(tx_q->dma_tx,
1321 for (i = 0; i < DMA_TX_SIZE; i++) {
1323 if (priv->extend_desc)
1324 p = &((tx_q->dma_etx + i)->basic);
1326 p = tx_q->dma_tx + i;
1328 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
1337 tx_q->tx_skbuff_dma[i].buf = 0;
1338 tx_q->tx_skbuff_dma[i].map_as_page = false;
1339 tx_q->tx_skbuff_dma[i].len = 0;
1340 tx_q->tx_skbuff_dma[i].last_segment = false;
1341 tx_q->tx_skbuff[i] = NULL;
1347 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
1354 * init_dma_desc_rings - init the RX/TX descriptor rings
1355 * @dev: net device structure
1357 * Description: this function initializes the DMA RX/TX descriptors
1358 * and allocates the socket buffers. It supports the chained and ring
1361 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1363 struct stmmac_priv *priv = netdev_priv(dev);
1366 ret = init_dma_rx_desc_rings(dev, flags);
1370 ret = init_dma_tx_desc_rings(dev);
1372 stmmac_clear_descriptors(priv);
1374 if (netif_msg_hw(priv))
1375 stmmac_display_rings(priv);
1381 * dma_free_rx_skbufs - free RX dma buffers
1382 * @priv: private structure
1383 * @queue: RX queue index
1385 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue)
1389 for (i = 0; i < DMA_RX_SIZE; i++)
1390 stmmac_free_rx_buffer(priv, queue, i);
1394 * dma_free_tx_skbufs - free TX dma buffers
1395 * @priv: private structure
1396 * @queue: TX queue index
1398 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue)
1402 for (i = 0; i < DMA_TX_SIZE; i++)
1403 stmmac_free_tx_buffer(priv, queue, i);
1407 * free_dma_rx_desc_resources - free RX dma desc resources
1408 * @priv: private structure
1410 static void free_dma_rx_desc_resources(struct stmmac_priv *priv)
1412 u32 rx_count = priv->plat->rx_queues_to_use;
1415 /* Free RX queue resources */
1416 for (queue = 0; queue < rx_count; queue++) {
1417 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1419 /* Release the DMA RX socket buffers */
1420 dma_free_rx_skbufs(priv, queue);
1422 /* Free DMA regions of consistent memory previously allocated */
1423 if (!priv->extend_desc)
1424 dma_free_coherent(priv->device,
1425 DMA_RX_SIZE * sizeof(struct dma_desc),
1426 rx_q->dma_rx, rx_q->dma_rx_phy);
1428 dma_free_coherent(priv->device, DMA_RX_SIZE *
1429 sizeof(struct dma_extended_desc),
1430 rx_q->dma_erx, rx_q->dma_rx_phy);
1432 kfree(rx_q->rx_skbuff_dma);
1433 kfree(rx_q->rx_skbuff);
1438 * free_dma_tx_desc_resources - free TX dma desc resources
1439 * @priv: private structure
1441 static void free_dma_tx_desc_resources(struct stmmac_priv *priv)
1443 u32 tx_count = priv->plat->tx_queues_to_use;
1446 /* Free TX queue resources */
1447 for (queue = 0; queue < tx_count; queue++) {
1448 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1450 /* Release the DMA TX socket buffers */
1451 dma_free_tx_skbufs(priv, queue);
1453 /* Free DMA regions of consistent memory previously allocated */
1454 if (!priv->extend_desc)
1455 dma_free_coherent(priv->device,
1456 DMA_TX_SIZE * sizeof(struct dma_desc),
1457 tx_q->dma_tx, tx_q->dma_tx_phy);
1459 dma_free_coherent(priv->device, DMA_TX_SIZE *
1460 sizeof(struct dma_extended_desc),
1461 tx_q->dma_etx, tx_q->dma_tx_phy);
1463 kfree(tx_q->tx_skbuff_dma);
1464 kfree(tx_q->tx_skbuff);
1469 * alloc_dma_rx_desc_resources - alloc RX resources.
1470 * @priv: private structure
1471 * Description: according to which descriptor can be used (extend or basic)
1472 * this function allocates the resources for TX and RX paths. In case of
1473 * reception, for example, it pre-allocated the RX socket buffer in order to
1474 * allow zero-copy mechanism.
1476 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv)
1478 u32 rx_count = priv->plat->rx_queues_to_use;
1482 /* RX queues buffers and DMA */
1483 for (queue = 0; queue < rx_count; queue++) {
1484 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1486 rx_q->queue_index = queue;
1487 rx_q->priv_data = priv;
1489 rx_q->rx_skbuff_dma = kmalloc_array(DMA_RX_SIZE,
1492 if (!rx_q->rx_skbuff_dma)
1495 rx_q->rx_skbuff = kmalloc_array(DMA_RX_SIZE,
1496 sizeof(struct sk_buff *),
1498 if (!rx_q->rx_skbuff)
1501 if (priv->extend_desc) {
1502 rx_q->dma_erx = dma_zalloc_coherent(priv->device,
1512 rx_q->dma_rx = dma_zalloc_coherent(priv->device,
1526 free_dma_rx_desc_resources(priv);
1532 * alloc_dma_tx_desc_resources - alloc TX resources.
1533 * @priv: private structure
1534 * Description: according to which descriptor can be used (extend or basic)
1535 * this function allocates the resources for TX and RX paths. In case of
1536 * reception, for example, it pre-allocated the RX socket buffer in order to
1537 * allow zero-copy mechanism.
1539 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv)
1541 u32 tx_count = priv->plat->tx_queues_to_use;
1545 /* TX queues buffers and DMA */
1546 for (queue = 0; queue < tx_count; queue++) {
1547 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1549 tx_q->queue_index = queue;
1550 tx_q->priv_data = priv;
1552 tx_q->tx_skbuff_dma = kmalloc_array(DMA_TX_SIZE,
1553 sizeof(*tx_q->tx_skbuff_dma),
1555 if (!tx_q->tx_skbuff_dma)
1558 tx_q->tx_skbuff = kmalloc_array(DMA_TX_SIZE,
1559 sizeof(struct sk_buff *),
1561 if (!tx_q->tx_skbuff)
1562 goto err_dma_buffers;
1564 if (priv->extend_desc) {
1565 tx_q->dma_etx = dma_zalloc_coherent(priv->device,
1572 goto err_dma_buffers;
1574 tx_q->dma_tx = dma_zalloc_coherent(priv->device,
1581 goto err_dma_buffers;
1588 free_dma_tx_desc_resources(priv);
1594 * alloc_dma_desc_resources - alloc TX/RX resources.
1595 * @priv: private structure
1596 * Description: according to which descriptor can be used (extend or basic)
1597 * this function allocates the resources for TX and RX paths. In case of
1598 * reception, for example, it pre-allocated the RX socket buffer in order to
1599 * allow zero-copy mechanism.
1601 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1604 int ret = alloc_dma_rx_desc_resources(priv);
1609 ret = alloc_dma_tx_desc_resources(priv);
1615 * free_dma_desc_resources - free dma desc resources
1616 * @priv: private structure
1618 static void free_dma_desc_resources(struct stmmac_priv *priv)
1620 /* Release the DMA RX socket buffers */
1621 free_dma_rx_desc_resources(priv);
1623 /* Release the DMA TX socket buffers */
1624 free_dma_tx_desc_resources(priv);
1628 * stmmac_mac_enable_rx_queues - Enable MAC rx queues
1629 * @priv: driver private structure
1630 * Description: It is used for enabling the rx queues in the MAC
1632 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)
1634 u32 rx_queues_count = priv->plat->rx_queues_to_use;
1638 for (queue = 0; queue < rx_queues_count; queue++) {
1639 mode = priv->plat->rx_queues_cfg[queue].mode_to_use;
1640 priv->hw->mac->rx_queue_enable(priv->hw, mode, queue);
1645 * stmmac_start_rx_dma - start RX DMA channel
1646 * @priv: driver private structure
1647 * @chan: RX channel index
1649 * This starts a RX DMA channel
1651 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan)
1653 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan);
1654 priv->hw->dma->start_rx(priv->ioaddr, chan);
1658 * stmmac_start_tx_dma - start TX DMA channel
1659 * @priv: driver private structure
1660 * @chan: TX channel index
1662 * This starts a TX DMA channel
1664 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan)
1666 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan);
1667 priv->hw->dma->start_tx(priv->ioaddr, chan);
1671 * stmmac_stop_rx_dma - stop RX DMA channel
1672 * @priv: driver private structure
1673 * @chan: RX channel index
1675 * This stops a RX DMA channel
1677 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan)
1679 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan);
1680 priv->hw->dma->stop_rx(priv->ioaddr, chan);
1684 * stmmac_stop_tx_dma - stop TX DMA channel
1685 * @priv: driver private structure
1686 * @chan: TX channel index
1688 * This stops a TX DMA channel
1690 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan)
1692 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan);
1693 priv->hw->dma->stop_tx(priv->ioaddr, chan);
1697 * stmmac_start_all_dma - start all RX and TX DMA channels
1698 * @priv: driver private structure
1700 * This starts all the RX and TX DMA channels
1702 static void stmmac_start_all_dma(struct stmmac_priv *priv)
1704 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1705 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1708 for (chan = 0; chan < rx_channels_count; chan++)
1709 stmmac_start_rx_dma(priv, chan);
1711 for (chan = 0; chan < tx_channels_count; chan++)
1712 stmmac_start_tx_dma(priv, chan);
1716 * stmmac_stop_all_dma - stop all RX and TX DMA channels
1717 * @priv: driver private structure
1719 * This stops the RX and TX DMA channels
1721 static void stmmac_stop_all_dma(struct stmmac_priv *priv)
1723 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1724 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1727 for (chan = 0; chan < rx_channels_count; chan++)
1728 stmmac_stop_rx_dma(priv, chan);
1730 for (chan = 0; chan < tx_channels_count; chan++)
1731 stmmac_stop_tx_dma(priv, chan);
1735 * stmmac_dma_operation_mode - HW DMA operation mode
1736 * @priv: driver private structure
1737 * Description: it is used for configuring the DMA operation mode register in
1738 * order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1740 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1742 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1743 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1744 int rxfifosz = priv->plat->rx_fifo_size;
1750 rxfifosz = priv->dma_cap.rx_fifo_size;
1752 if (priv->plat->force_thresh_dma_mode) {
1755 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1757 * In case of GMAC, SF mode can be enabled
1758 * to perform the TX COE in HW. This depends on:
1759 * 1) TX COE if actually supported
1760 * 2) There is no bugged Jumbo frame support
1761 * that needs to not insert csum in the TDES.
1763 txmode = SF_DMA_MODE;
1764 rxmode = SF_DMA_MODE;
1765 priv->xstats.threshold = SF_DMA_MODE;
1768 rxmode = SF_DMA_MODE;
1771 /* configure all channels */
1772 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
1773 for (chan = 0; chan < rx_channels_count; chan++)
1774 priv->hw->dma->dma_rx_mode(priv->ioaddr, rxmode, chan,
1777 for (chan = 0; chan < tx_channels_count; chan++)
1778 priv->hw->dma->dma_tx_mode(priv->ioaddr, txmode, chan);
1780 priv->hw->dma->dma_mode(priv->ioaddr, txmode, rxmode,
1786 * stmmac_tx_clean - to manage the transmission completion
1787 * @priv: driver private structure
1788 * @queue: TX queue index
1789 * Description: it reclaims the transmit resources after transmission completes.
1791 static void stmmac_tx_clean(struct stmmac_priv *priv, u32 queue)
1793 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1794 unsigned int bytes_compl = 0, pkts_compl = 0;
1795 unsigned int entry = tx_q->dirty_tx;
1797 netif_tx_lock(priv->dev);
1799 priv->xstats.tx_clean++;
1801 while (entry != tx_q->cur_tx) {
1802 struct sk_buff *skb = tx_q->tx_skbuff[entry];
1806 if (priv->extend_desc)
1807 p = (struct dma_desc *)(tx_q->dma_etx + entry);
1809 p = tx_q->dma_tx + entry;
1811 status = priv->hw->desc->tx_status(&priv->dev->stats,
1814 /* Check if the descriptor is owned by the DMA */
1815 if (unlikely(status & tx_dma_own))
1818 /* Just consider the last segment and ...*/
1819 if (likely(!(status & tx_not_ls))) {
1820 /* ... verify the status error condition */
1821 if (unlikely(status & tx_err)) {
1822 priv->dev->stats.tx_errors++;
1824 priv->dev->stats.tx_packets++;
1825 priv->xstats.tx_pkt_n++;
1827 stmmac_get_tx_hwtstamp(priv, p, skb);
1830 if (likely(tx_q->tx_skbuff_dma[entry].buf)) {
1831 if (tx_q->tx_skbuff_dma[entry].map_as_page)
1832 dma_unmap_page(priv->device,
1833 tx_q->tx_skbuff_dma[entry].buf,
1834 tx_q->tx_skbuff_dma[entry].len,
1837 dma_unmap_single(priv->device,
1838 tx_q->tx_skbuff_dma[entry].buf,
1839 tx_q->tx_skbuff_dma[entry].len,
1841 tx_q->tx_skbuff_dma[entry].buf = 0;
1842 tx_q->tx_skbuff_dma[entry].len = 0;
1843 tx_q->tx_skbuff_dma[entry].map_as_page = false;
1846 if (priv->hw->mode->clean_desc3)
1847 priv->hw->mode->clean_desc3(tx_q, p);
1849 tx_q->tx_skbuff_dma[entry].last_segment = false;
1850 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
1852 if (likely(skb != NULL)) {
1854 bytes_compl += skb->len;
1855 dev_consume_skb_any(skb);
1856 tx_q->tx_skbuff[entry] = NULL;
1859 priv->hw->desc->release_tx_desc(p, priv->mode);
1861 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
1863 tx_q->dirty_tx = entry;
1865 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue),
1866 pkts_compl, bytes_compl);
1868 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev,
1870 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH) {
1872 netif_dbg(priv, tx_done, priv->dev,
1873 "%s: restart transmit\n", __func__);
1874 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue));
1877 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1878 stmmac_enable_eee_mode(priv);
1879 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1881 netif_tx_unlock(priv->dev);
1884 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv, u32 chan)
1886 priv->hw->dma->enable_dma_irq(priv->ioaddr, chan);
1889 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv, u32 chan)
1891 priv->hw->dma->disable_dma_irq(priv->ioaddr, chan);
1895 * stmmac_tx_err - to manage the tx error
1896 * @priv: driver private structure
1897 * @chan: channel index
1898 * Description: it cleans the descriptors and restarts the transmission
1899 * in case of transmission errors.
1901 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan)
1903 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
1906 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan));
1908 stmmac_stop_tx_dma(priv, chan);
1909 dma_free_tx_skbufs(priv, chan);
1910 for (i = 0; i < DMA_TX_SIZE; i++)
1911 if (priv->extend_desc)
1912 priv->hw->desc->init_tx_desc(&tx_q->dma_etx[i].basic,
1914 (i == DMA_TX_SIZE - 1));
1916 priv->hw->desc->init_tx_desc(&tx_q->dma_tx[i],
1918 (i == DMA_TX_SIZE - 1));
1921 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan));
1922 stmmac_start_tx_dma(priv, chan);
1924 priv->dev->stats.tx_errors++;
1925 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan));
1929 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel
1930 * @priv: driver private structure
1931 * @txmode: TX operating mode
1932 * @rxmode: RX operating mode
1933 * @chan: channel index
1934 * Description: it is used for configuring of the DMA operation mode in
1935 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward
1938 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
1939 u32 rxmode, u32 chan)
1941 int rxfifosz = priv->plat->rx_fifo_size;
1944 rxfifosz = priv->dma_cap.rx_fifo_size;
1946 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
1947 priv->hw->dma->dma_rx_mode(priv->ioaddr, rxmode, chan,
1949 priv->hw->dma->dma_tx_mode(priv->ioaddr, txmode, chan);
1951 priv->hw->dma->dma_mode(priv->ioaddr, txmode, rxmode,
1957 * stmmac_dma_interrupt - DMA ISR
1958 * @priv: driver private structure
1959 * Description: this is the DMA ISR. It is called by the main ISR.
1960 * It calls the dwmac dma routine and schedule poll method in case of some
1963 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
1965 u32 tx_channel_count = priv->plat->tx_queues_to_use;
1969 for (chan = 0; chan < tx_channel_count; chan++) {
1970 struct stmmac_rx_queue *rx_q = &priv->rx_queue[chan];
1972 status = priv->hw->dma->dma_interrupt(priv->ioaddr,
1973 &priv->xstats, chan);
1974 if (likely((status & handle_rx)) || (status & handle_tx)) {
1975 if (likely(napi_schedule_prep(&rx_q->napi))) {
1976 stmmac_disable_dma_irq(priv, chan);
1977 __napi_schedule(&rx_q->napi);
1981 if (unlikely(status & tx_hard_error_bump_tc)) {
1982 /* Try to bump up the dma threshold on this failure */
1983 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
1986 if (priv->plat->force_thresh_dma_mode)
1987 stmmac_set_dma_operation_mode(priv,
1992 stmmac_set_dma_operation_mode(priv,
1996 priv->xstats.threshold = tc;
1998 } else if (unlikely(status == tx_hard_error)) {
1999 stmmac_tx_err(priv, chan);
2005 * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
2006 * @priv: driver private structure
2007 * Description: this masks the MMC irq, in fact, the counters are managed in SW.
2009 static void stmmac_mmc_setup(struct stmmac_priv *priv)
2011 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
2012 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
2014 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
2015 priv->ptpaddr = priv->ioaddr + PTP_GMAC4_OFFSET;
2016 priv->mmcaddr = priv->ioaddr + MMC_GMAC4_OFFSET;
2018 priv->ptpaddr = priv->ioaddr + PTP_GMAC3_X_OFFSET;
2019 priv->mmcaddr = priv->ioaddr + MMC_GMAC3_X_OFFSET;
2022 dwmac_mmc_intr_all_mask(priv->mmcaddr);
2024 if (priv->dma_cap.rmon) {
2025 dwmac_mmc_ctrl(priv->mmcaddr, mode);
2026 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
2028 netdev_info(priv->dev, "No MAC Management Counters available\n");
2032 * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors
2033 * @priv: driver private structure
2034 * Description: select the Enhanced/Alternate or Normal descriptors.
2035 * In case of Enhanced/Alternate, it checks if the extended descriptors are
2036 * supported by the HW capability register.
2038 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
2040 if (priv->plat->enh_desc) {
2041 dev_info(priv->device, "Enhanced/Alternate descriptors\n");
2043 /* GMAC older than 3.50 has no extended descriptors */
2044 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
2045 dev_info(priv->device, "Enabled extended descriptors\n");
2046 priv->extend_desc = 1;
2048 dev_warn(priv->device, "Extended descriptors not supported\n");
2050 priv->hw->desc = &enh_desc_ops;
2052 dev_info(priv->device, "Normal descriptors\n");
2053 priv->hw->desc = &ndesc_ops;
2058 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
2059 * @priv: driver private structure
2061 * new GMAC chip generations have a new register to indicate the
2062 * presence of the optional feature/functions.
2063 * This can be also used to override the value passed through the
2064 * platform and necessary for old MAC10/100 and GMAC chips.
2066 static int stmmac_get_hw_features(struct stmmac_priv *priv)
2070 if (priv->hw->dma->get_hw_feature) {
2071 priv->hw->dma->get_hw_feature(priv->ioaddr,
2080 * stmmac_check_ether_addr - check if the MAC addr is valid
2081 * @priv: driver private structure
2083 * it is to verify if the MAC address is valid, in case of failures it
2084 * generates a random MAC address
2086 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
2088 if (!is_valid_ether_addr(priv->dev->dev_addr)) {
2089 priv->hw->mac->get_umac_addr(priv->hw,
2090 priv->dev->dev_addr, 0);
2091 if (!is_valid_ether_addr(priv->dev->dev_addr))
2092 eth_hw_addr_random(priv->dev);
2093 netdev_info(priv->dev, "device MAC address %pM\n",
2094 priv->dev->dev_addr);
2099 * stmmac_init_dma_engine - DMA init.
2100 * @priv: driver private structure
2102 * It inits the DMA invoking the specific MAC/GMAC callback.
2103 * Some DMA parameters can be passed from the platform;
2104 * in case of these are not passed a default is kept for the MAC or GMAC.
2106 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
2108 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2109 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2110 struct stmmac_rx_queue *rx_q;
2111 struct stmmac_tx_queue *tx_q;
2112 u32 dummy_dma_rx_phy = 0;
2113 u32 dummy_dma_tx_phy = 0;
2118 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) {
2119 dev_err(priv->device, "Invalid DMA configuration\n");
2123 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
2126 ret = priv->hw->dma->reset(priv->ioaddr);
2128 dev_err(priv->device, "Failed to reset the dma\n");
2132 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
2133 /* DMA Configuration */
2134 priv->hw->dma->init(priv->ioaddr, priv->plat->dma_cfg,
2135 dummy_dma_tx_phy, dummy_dma_rx_phy, atds);
2137 /* DMA RX Channel Configuration */
2138 for (chan = 0; chan < rx_channels_count; chan++) {
2139 rx_q = &priv->rx_queue[chan];
2141 priv->hw->dma->init_rx_chan(priv->ioaddr,
2142 priv->plat->dma_cfg,
2143 rx_q->dma_rx_phy, chan);
2145 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
2146 (DMA_RX_SIZE * sizeof(struct dma_desc));
2147 priv->hw->dma->set_rx_tail_ptr(priv->ioaddr,
2152 /* DMA TX Channel Configuration */
2153 for (chan = 0; chan < tx_channels_count; chan++) {
2154 tx_q = &priv->tx_queue[chan];
2156 priv->hw->dma->init_chan(priv->ioaddr,
2157 priv->plat->dma_cfg,
2160 priv->hw->dma->init_tx_chan(priv->ioaddr,
2161 priv->plat->dma_cfg,
2162 tx_q->dma_tx_phy, chan);
2164 tx_q->tx_tail_addr = tx_q->dma_tx_phy +
2165 (DMA_TX_SIZE * sizeof(struct dma_desc));
2166 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr,
2171 rx_q = &priv->rx_queue[chan];
2172 tx_q = &priv->tx_queue[chan];
2173 priv->hw->dma->init(priv->ioaddr, priv->plat->dma_cfg,
2174 tx_q->dma_tx_phy, rx_q->dma_rx_phy, atds);
2177 if (priv->plat->axi && priv->hw->dma->axi)
2178 priv->hw->dma->axi(priv->ioaddr, priv->plat->axi);
2184 * stmmac_tx_timer - mitigation sw timer for tx.
2185 * @data: data pointer
2187 * This is the timer handler to directly invoke the stmmac_tx_clean.
2189 static void stmmac_tx_timer(unsigned long data)
2191 struct stmmac_priv *priv = (struct stmmac_priv *)data;
2192 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2195 /* let's scan all the tx queues */
2196 for (queue = 0; queue < tx_queues_count; queue++)
2197 stmmac_tx_clean(priv, queue);
2201 * stmmac_init_tx_coalesce - init tx mitigation options.
2202 * @priv: driver private structure
2204 * This inits the transmit coalesce parameters: i.e. timer rate,
2205 * timer handler and default threshold used for enabling the
2206 * interrupt on completion bit.
2208 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
2210 priv->tx_coal_frames = STMMAC_TX_FRAMES;
2211 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
2212 init_timer(&priv->txtimer);
2213 priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
2214 priv->txtimer.data = (unsigned long)priv;
2215 priv->txtimer.function = stmmac_tx_timer;
2216 add_timer(&priv->txtimer);
2219 static void stmmac_set_rings_length(struct stmmac_priv *priv)
2221 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2222 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2225 /* set TX ring length */
2226 if (priv->hw->dma->set_tx_ring_len) {
2227 for (chan = 0; chan < tx_channels_count; chan++)
2228 priv->hw->dma->set_tx_ring_len(priv->ioaddr,
2229 (DMA_TX_SIZE - 1), chan);
2232 /* set RX ring length */
2233 if (priv->hw->dma->set_rx_ring_len) {
2234 for (chan = 0; chan < rx_channels_count; chan++)
2235 priv->hw->dma->set_rx_ring_len(priv->ioaddr,
2236 (DMA_RX_SIZE - 1), chan);
2241 * stmmac_set_tx_queue_weight - Set TX queue weight
2242 * @priv: driver private structure
2243 * Description: It is used for setting TX queues weight
2245 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv)
2247 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2251 for (queue = 0; queue < tx_queues_count; queue++) {
2252 weight = priv->plat->tx_queues_cfg[queue].weight;
2253 priv->hw->mac->set_mtl_tx_queue_weight(priv->hw, weight, queue);
2258 * stmmac_configure_cbs - Configure CBS in TX queue
2259 * @priv: driver private structure
2260 * Description: It is used for configuring CBS in AVB TX queues
2262 static void stmmac_configure_cbs(struct stmmac_priv *priv)
2264 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2268 /* queue 0 is reserved for legacy traffic */
2269 for (queue = 1; queue < tx_queues_count; queue++) {
2270 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use;
2271 if (mode_to_use == MTL_QUEUE_DCB)
2274 priv->hw->mac->config_cbs(priv->hw,
2275 priv->plat->tx_queues_cfg[queue].send_slope,
2276 priv->plat->tx_queues_cfg[queue].idle_slope,
2277 priv->plat->tx_queues_cfg[queue].high_credit,
2278 priv->plat->tx_queues_cfg[queue].low_credit,
2284 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel
2285 * @priv: driver private structure
2286 * Description: It is used for mapping RX queues to RX dma channels
2288 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv)
2290 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2294 for (queue = 0; queue < rx_queues_count; queue++) {
2295 chan = priv->plat->rx_queues_cfg[queue].chan;
2296 priv->hw->mac->map_mtl_to_dma(priv->hw, queue, chan);
2301 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority
2302 * @priv: driver private structure
2303 * Description: It is used for configuring the RX Queue Priority
2305 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv)
2307 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2311 for (queue = 0; queue < rx_queues_count; queue++) {
2312 if (!priv->plat->rx_queues_cfg[queue].use_prio)
2315 prio = priv->plat->rx_queues_cfg[queue].prio;
2316 priv->hw->mac->rx_queue_prio(priv->hw, prio, queue);
2321 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority
2322 * @priv: driver private structure
2323 * Description: It is used for configuring the TX Queue Priority
2325 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv)
2327 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2331 for (queue = 0; queue < tx_queues_count; queue++) {
2332 if (!priv->plat->tx_queues_cfg[queue].use_prio)
2335 prio = priv->plat->tx_queues_cfg[queue].prio;
2336 priv->hw->mac->tx_queue_prio(priv->hw, prio, queue);
2341 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing
2342 * @priv: driver private structure
2343 * Description: It is used for configuring the RX queue routing
2345 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv)
2347 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2351 for (queue = 0; queue < rx_queues_count; queue++) {
2352 /* no specific packet type routing specified for the queue */
2353 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0)
2356 packet = priv->plat->rx_queues_cfg[queue].pkt_route;
2357 priv->hw->mac->rx_queue_prio(priv->hw, packet, queue);
2362 * stmmac_mtl_configuration - Configure MTL
2363 * @priv: driver private structure
2364 * Description: It is used for configurring MTL
2366 static void stmmac_mtl_configuration(struct stmmac_priv *priv)
2368 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2369 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2371 if (tx_queues_count > 1 && priv->hw->mac->set_mtl_tx_queue_weight)
2372 stmmac_set_tx_queue_weight(priv);
2374 /* Configure MTL RX algorithms */
2375 if (rx_queues_count > 1 && priv->hw->mac->prog_mtl_rx_algorithms)
2376 priv->hw->mac->prog_mtl_rx_algorithms(priv->hw,
2377 priv->plat->rx_sched_algorithm);
2379 /* Configure MTL TX algorithms */
2380 if (tx_queues_count > 1 && priv->hw->mac->prog_mtl_tx_algorithms)
2381 priv->hw->mac->prog_mtl_tx_algorithms(priv->hw,
2382 priv->plat->tx_sched_algorithm);
2384 /* Configure CBS in AVB TX queues */
2385 if (tx_queues_count > 1 && priv->hw->mac->config_cbs)
2386 stmmac_configure_cbs(priv);
2388 /* Map RX MTL to DMA channels */
2389 if (priv->hw->mac->map_mtl_to_dma)
2390 stmmac_rx_queue_dma_chan_map(priv);
2392 /* Enable MAC RX Queues */
2393 if (priv->hw->mac->rx_queue_enable)
2394 stmmac_mac_enable_rx_queues(priv);
2396 /* Set RX priorities */
2397 if (rx_queues_count > 1 && priv->hw->mac->rx_queue_prio)
2398 stmmac_mac_config_rx_queues_prio(priv);
2400 /* Set TX priorities */
2401 if (tx_queues_count > 1 && priv->hw->mac->tx_queue_prio)
2402 stmmac_mac_config_tx_queues_prio(priv);
2404 /* Set RX routing */
2405 if (rx_queues_count > 1 && priv->hw->mac->rx_queue_routing)
2406 stmmac_mac_config_rx_queues_routing(priv);
2410 * stmmac_hw_setup - setup mac in a usable state.
2411 * @dev : pointer to the device structure.
2413 * this is the main function to setup the HW in a usable state because the
2414 * dma engine is reset, the core registers are configured (e.g. AXI,
2415 * Checksum features, timers). The DMA is ready to start receiving and
2418 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2421 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
2423 struct stmmac_priv *priv = netdev_priv(dev);
2424 u32 rx_cnt = priv->plat->rx_queues_to_use;
2425 u32 tx_cnt = priv->plat->tx_queues_to_use;
2429 /* DMA initialization and SW reset */
2430 ret = stmmac_init_dma_engine(priv);
2432 netdev_err(priv->dev, "%s: DMA engine initialization failed\n",
2437 /* Copy the MAC addr into the HW */
2438 priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0);
2440 /* PS and related bits will be programmed according to the speed */
2441 if (priv->hw->pcs) {
2442 int speed = priv->plat->mac_port_sel_speed;
2444 if ((speed == SPEED_10) || (speed == SPEED_100) ||
2445 (speed == SPEED_1000)) {
2446 priv->hw->ps = speed;
2448 dev_warn(priv->device, "invalid port speed\n");
2453 /* Initialize the MAC Core */
2454 priv->hw->mac->core_init(priv->hw, dev->mtu);
2457 if (priv->synopsys_id >= DWMAC_CORE_4_00)
2458 stmmac_mtl_configuration(priv);
2460 ret = priv->hw->mac->rx_ipc(priv->hw);
2462 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n");
2463 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
2464 priv->hw->rx_csum = 0;
2467 /* Enable the MAC Rx/Tx */
2468 priv->hw->mac->set_mac(priv->ioaddr, true);
2470 /* Set the HW DMA mode and the COE */
2471 stmmac_dma_operation_mode(priv);
2473 stmmac_mmc_setup(priv);
2476 ret = clk_prepare_enable(priv->plat->clk_ptp_ref);
2478 netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret);
2480 ret = stmmac_init_ptp(priv);
2481 if (ret == -EOPNOTSUPP)
2482 netdev_warn(priv->dev, "PTP not supported by HW\n");
2484 netdev_warn(priv->dev, "PTP init failed\n");
2487 #ifdef CONFIG_DEBUG_FS
2488 ret = stmmac_init_fs(dev);
2490 netdev_warn(priv->dev, "%s: failed debugFS registration\n",
2493 /* Start the ball rolling... */
2494 stmmac_start_all_dma(priv);
2496 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
2498 if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
2499 priv->rx_riwt = MAX_DMA_RIWT;
2500 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT, rx_cnt);
2503 if (priv->hw->pcs && priv->hw->mac->pcs_ctrl_ane)
2504 priv->hw->mac->pcs_ctrl_ane(priv->hw, 1, priv->hw->ps, 0);
2506 /* set TX and RX rings length */
2507 stmmac_set_rings_length(priv);
2511 for (chan = 0; chan < tx_cnt; chan++)
2512 priv->hw->dma->enable_tso(priv->ioaddr, 1, chan);
2518 static void stmmac_hw_teardown(struct net_device *dev)
2520 struct stmmac_priv *priv = netdev_priv(dev);
2522 clk_disable_unprepare(priv->plat->clk_ptp_ref);
2526 * stmmac_open - open entry point of the driver
2527 * @dev : pointer to the device structure.
2529 * This function is the open entry point of the driver.
2531 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2534 static int stmmac_open(struct net_device *dev)
2536 struct stmmac_priv *priv = netdev_priv(dev);
2539 stmmac_check_ether_addr(priv);
2541 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
2542 priv->hw->pcs != STMMAC_PCS_TBI &&
2543 priv->hw->pcs != STMMAC_PCS_RTBI) {
2544 ret = stmmac_init_phy(dev);
2546 netdev_err(priv->dev,
2547 "%s: Cannot attach to PHY (error: %d)\n",
2553 /* Extra statistics */
2554 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
2555 priv->xstats.threshold = tc;
2557 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
2558 priv->rx_copybreak = STMMAC_RX_COPYBREAK;
2560 ret = alloc_dma_desc_resources(priv);
2562 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n",
2564 goto dma_desc_error;
2567 ret = init_dma_desc_rings(dev, GFP_KERNEL);
2569 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n",
2574 ret = stmmac_hw_setup(dev, true);
2576 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__);
2580 stmmac_init_tx_coalesce(priv);
2583 phy_start(dev->phydev);
2585 /* Request the IRQ lines */
2586 ret = request_irq(dev->irq, stmmac_interrupt,
2587 IRQF_SHARED, dev->name, dev);
2588 if (unlikely(ret < 0)) {
2589 netdev_err(priv->dev,
2590 "%s: ERROR: allocating the IRQ %d (error: %d)\n",
2591 __func__, dev->irq, ret);
2595 /* Request the Wake IRQ in case of another line is used for WoL */
2596 if (priv->wol_irq != dev->irq) {
2597 ret = request_irq(priv->wol_irq, stmmac_interrupt,
2598 IRQF_SHARED, dev->name, dev);
2599 if (unlikely(ret < 0)) {
2600 netdev_err(priv->dev,
2601 "%s: ERROR: allocating the WoL IRQ %d (%d)\n",
2602 __func__, priv->wol_irq, ret);
2607 /* Request the IRQ lines */
2608 if (priv->lpi_irq > 0) {
2609 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
2611 if (unlikely(ret < 0)) {
2612 netdev_err(priv->dev,
2613 "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
2614 __func__, priv->lpi_irq, ret);
2619 stmmac_enable_all_queues(priv);
2620 stmmac_start_all_queues(priv);
2625 if (priv->wol_irq != dev->irq)
2626 free_irq(priv->wol_irq, dev);
2628 free_irq(dev->irq, dev);
2631 phy_stop(dev->phydev);
2633 del_timer_sync(&priv->txtimer);
2634 stmmac_hw_teardown(dev);
2636 free_dma_desc_resources(priv);
2639 phy_disconnect(dev->phydev);
2645 * stmmac_release - close entry point of the driver
2646 * @dev : device pointer.
2648 * This is the stop entry point of the driver.
2650 static int stmmac_release(struct net_device *dev)
2652 struct stmmac_priv *priv = netdev_priv(dev);
2654 if (priv->eee_enabled)
2655 del_timer_sync(&priv->eee_ctrl_timer);
2657 /* Stop and disconnect the PHY */
2659 phy_stop(dev->phydev);
2660 phy_disconnect(dev->phydev);
2663 stmmac_stop_all_queues(priv);
2665 stmmac_disable_all_queues(priv);
2667 del_timer_sync(&priv->txtimer);
2669 /* Free the IRQ lines */
2670 free_irq(dev->irq, dev);
2671 if (priv->wol_irq != dev->irq)
2672 free_irq(priv->wol_irq, dev);
2673 if (priv->lpi_irq > 0)
2674 free_irq(priv->lpi_irq, dev);
2676 /* Stop TX/RX DMA and clear the descriptors */
2677 stmmac_stop_all_dma(priv);
2679 /* Release and free the Rx/Tx resources */
2680 free_dma_desc_resources(priv);
2682 /* Disable the MAC Rx/Tx */
2683 priv->hw->mac->set_mac(priv->ioaddr, false);
2685 netif_carrier_off(dev);
2687 #ifdef CONFIG_DEBUG_FS
2688 stmmac_exit_fs(dev);
2691 stmmac_release_ptp(priv);
2697 * stmmac_tso_allocator - close entry point of the driver
2698 * @priv: driver private structure
2699 * @des: buffer start address
2700 * @total_len: total length to fill in descriptors
2701 * @last_segmant: condition for the last descriptor
2702 * @queue: TX queue index
2704 * This function fills descriptor and request new descriptors according to
2705 * buffer length to fill
2707 static void stmmac_tso_allocator(struct stmmac_priv *priv, unsigned int des,
2708 int total_len, bool last_segment, u32 queue)
2710 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2711 struct dma_desc *desc;
2715 tmp_len = total_len;
2717 while (tmp_len > 0) {
2718 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2719 desc = tx_q->dma_tx + tx_q->cur_tx;
2721 desc->des0 = cpu_to_le32(des + (total_len - tmp_len));
2722 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?
2723 TSO_MAX_BUFF_SIZE : tmp_len;
2725 priv->hw->desc->prepare_tso_tx_desc(desc, 0, buff_size,
2727 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE),
2730 tmp_len -= TSO_MAX_BUFF_SIZE;
2735 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
2736 * @skb : the socket buffer
2737 * @dev : device pointer
2738 * Description: this is the transmit function that is called on TSO frames
2739 * (support available on GMAC4 and newer chips).
2740 * Diagram below show the ring programming in case of TSO frames:
2744 * | DES0 |---> buffer1 = L2/L3/L4 header
2745 * | DES1 |---> TCP Payload (can continue on next descr...)
2746 * | DES2 |---> buffer 1 and 2 len
2747 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
2753 * | DES0 | --| Split TCP Payload on Buffers 1 and 2
2755 * | DES2 | --> buffer 1 and 2 len
2759 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
2761 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
2763 struct dma_desc *desc, *first, *mss_desc = NULL;
2764 struct stmmac_priv *priv = netdev_priv(dev);
2765 int nfrags = skb_shinfo(skb)->nr_frags;
2766 u32 queue = skb_get_queue_mapping(skb);
2767 unsigned int first_entry, des;
2768 struct stmmac_tx_queue *tx_q;
2769 int tmp_pay_len = 0;
2774 tx_q = &priv->tx_queue[queue];
2776 /* Compute header lengths */
2777 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2779 /* Desc availability based on threshold should be enough safe */
2780 if (unlikely(stmmac_tx_avail(priv, queue) <
2781 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) {
2782 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
2783 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
2785 /* This is a hard error, log it. */
2786 netdev_err(priv->dev,
2787 "%s: Tx Ring full when queue awake\n",
2790 return NETDEV_TX_BUSY;
2793 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */
2795 mss = skb_shinfo(skb)->gso_size;
2797 /* set new MSS value if needed */
2798 if (mss != priv->mss) {
2799 mss_desc = tx_q->dma_tx + tx_q->cur_tx;
2800 priv->hw->desc->set_mss(mss_desc, mss);
2802 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2805 if (netif_msg_tx_queued(priv)) {
2806 pr_info("%s: tcphdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
2807 __func__, tcp_hdrlen(skb), proto_hdr_len, pay_len, mss);
2808 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len,
2812 first_entry = tx_q->cur_tx;
2814 desc = tx_q->dma_tx + first_entry;
2817 /* first descriptor: fill Headers on Buf1 */
2818 des = dma_map_single(priv->device, skb->data, skb_headlen(skb),
2820 if (dma_mapping_error(priv->device, des))
2823 tx_q->tx_skbuff_dma[first_entry].buf = des;
2824 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb);
2825 tx_q->tx_skbuff[first_entry] = skb;
2827 first->des0 = cpu_to_le32(des);
2829 /* Fill start of payload in buff2 of first descriptor */
2831 first->des1 = cpu_to_le32(des + proto_hdr_len);
2833 /* If needed take extra descriptors to fill the remaining payload */
2834 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE;
2836 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue);
2838 /* Prepare fragments */
2839 for (i = 0; i < nfrags; i++) {
2840 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2842 des = skb_frag_dma_map(priv->device, frag, 0,
2843 skb_frag_size(frag),
2845 if (dma_mapping_error(priv->device, des))
2848 stmmac_tso_allocator(priv, des, skb_frag_size(frag),
2849 (i == nfrags - 1), queue);
2851 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des;
2852 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag);
2853 tx_q->tx_skbuff[tx_q->cur_tx] = NULL;
2854 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true;
2857 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true;
2859 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2861 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
2862 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
2864 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
2867 dev->stats.tx_bytes += skb->len;
2868 priv->xstats.tx_tso_frames++;
2869 priv->xstats.tx_tso_nfrags += nfrags;
2871 /* Manage tx mitigation */
2872 priv->tx_count_frames += nfrags + 1;
2873 if (likely(priv->tx_coal_frames > priv->tx_count_frames)) {
2874 mod_timer(&priv->txtimer,
2875 STMMAC_COAL_TIMER(priv->tx_coal_timer));
2877 priv->tx_count_frames = 0;
2878 priv->hw->desc->set_tx_ic(desc);
2879 priv->xstats.tx_set_ic_bit++;
2882 if (!priv->hwts_tx_en)
2883 skb_tx_timestamp(skb);
2885 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2886 priv->hwts_tx_en)) {
2887 /* declare that device is doing timestamping */
2888 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2889 priv->hw->desc->enable_tx_timestamp(first);
2892 /* Complete the first descriptor before granting the DMA */
2893 priv->hw->desc->prepare_tso_tx_desc(first, 1,
2896 1, tx_q->tx_skbuff_dma[first_entry].last_segment,
2897 tcp_hdrlen(skb) / 4, (skb->len - proto_hdr_len));
2899 /* If context desc is used to change MSS */
2901 priv->hw->desc->set_tx_owner(mss_desc);
2903 /* The own bit must be the latest setting done when prepare the
2904 * descriptor and then barrier is needed to make sure that
2905 * all is coherent before granting the DMA engine.
2909 if (netif_msg_pktdata(priv)) {
2910 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
2911 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
2912 tx_q->cur_tx, first, nfrags);
2914 priv->hw->desc->display_ring((void *)tx_q->dma_tx, DMA_TX_SIZE,
2917 pr_info(">>> frame to be transmitted: ");
2918 print_pkt(skb->data, skb_headlen(skb));
2921 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
2923 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, tx_q->tx_tail_addr,
2926 return NETDEV_TX_OK;
2929 dev_err(priv->device, "Tx dma map failed\n");
2931 priv->dev->stats.tx_dropped++;
2932 return NETDEV_TX_OK;
2936 * stmmac_xmit - Tx entry point of the driver
2937 * @skb : the socket buffer
2938 * @dev : device pointer
2939 * Description : this is the tx entry point of the driver.
2940 * It programs the chain or the ring and supports oversized frames
2943 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
2945 struct stmmac_priv *priv = netdev_priv(dev);
2946 unsigned int nopaged_len = skb_headlen(skb);
2947 int i, csum_insertion = 0, is_jumbo = 0;
2948 u32 queue = skb_get_queue_mapping(skb);
2949 int nfrags = skb_shinfo(skb)->nr_frags;
2951 unsigned int first_entry;
2952 struct dma_desc *desc, *first;
2953 struct stmmac_tx_queue *tx_q;
2954 unsigned int enh_desc;
2957 tx_q = &priv->tx_queue[queue];
2959 /* Manage oversized TCP frames for GMAC4 device */
2960 if (skb_is_gso(skb) && priv->tso) {
2961 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2962 return stmmac_tso_xmit(skb, dev);
2965 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) {
2966 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
2967 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
2969 /* This is a hard error, log it. */
2970 netdev_err(priv->dev,
2971 "%s: Tx Ring full when queue awake\n",
2974 return NETDEV_TX_BUSY;
2977 if (priv->tx_path_in_lpi_mode)
2978 stmmac_disable_eee_mode(priv);
2980 entry = tx_q->cur_tx;
2981 first_entry = entry;
2983 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
2985 if (likely(priv->extend_desc))
2986 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
2988 desc = tx_q->dma_tx + entry;
2992 tx_q->tx_skbuff[first_entry] = skb;
2994 enh_desc = priv->plat->enh_desc;
2995 /* To program the descriptors according to the size of the frame */
2997 is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc);
2999 if (unlikely(is_jumbo) && likely(priv->synopsys_id <
3001 entry = priv->hw->mode->jumbo_frm(tx_q, skb, csum_insertion);
3002 if (unlikely(entry < 0))
3006 for (i = 0; i < nfrags; i++) {
3007 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3008 int len = skb_frag_size(frag);
3009 bool last_segment = (i == (nfrags - 1));
3011 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
3013 if (likely(priv->extend_desc))
3014 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
3016 desc = tx_q->dma_tx + entry;
3018 des = skb_frag_dma_map(priv->device, frag, 0, len,
3020 if (dma_mapping_error(priv->device, des))
3021 goto dma_map_err; /* should reuse desc w/o issues */
3023 tx_q->tx_skbuff[entry] = NULL;
3025 tx_q->tx_skbuff_dma[entry].buf = des;
3026 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
3027 desc->des0 = cpu_to_le32(des);
3029 desc->des2 = cpu_to_le32(des);
3031 tx_q->tx_skbuff_dma[entry].map_as_page = true;
3032 tx_q->tx_skbuff_dma[entry].len = len;
3033 tx_q->tx_skbuff_dma[entry].last_segment = last_segment;
3035 /* Prepare the descriptor and set the own bit too */
3036 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
3037 priv->mode, 1, last_segment,
3041 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
3043 tx_q->cur_tx = entry;
3045 if (netif_msg_pktdata(priv)) {
3048 netdev_dbg(priv->dev,
3049 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
3050 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
3051 entry, first, nfrags);
3053 if (priv->extend_desc)
3054 tx_head = (void *)tx_q->dma_etx;
3056 tx_head = (void *)tx_q->dma_tx;
3058 priv->hw->desc->display_ring(tx_head, DMA_TX_SIZE, false);
3060 netdev_dbg(priv->dev, ">>> frame to be transmitted: ");
3061 print_pkt(skb->data, skb->len);
3064 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
3065 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
3067 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
3070 dev->stats.tx_bytes += skb->len;
3072 /* According to the coalesce parameter the IC bit for the latest
3073 * segment is reset and the timer re-started to clean the tx status.
3074 * This approach takes care about the fragments: desc is the first
3075 * element in case of no SG.
3077 priv->tx_count_frames += nfrags + 1;
3078 if (likely(priv->tx_coal_frames > priv->tx_count_frames)) {
3079 mod_timer(&priv->txtimer,
3080 STMMAC_COAL_TIMER(priv->tx_coal_timer));
3082 priv->tx_count_frames = 0;
3083 priv->hw->desc->set_tx_ic(desc);
3084 priv->xstats.tx_set_ic_bit++;
3087 if (!priv->hwts_tx_en)
3088 skb_tx_timestamp(skb);
3090 /* Ready to fill the first descriptor and set the OWN bit w/o any
3091 * problems because all the descriptors are actually ready to be
3092 * passed to the DMA engine.
3094 if (likely(!is_jumbo)) {
3095 bool last_segment = (nfrags == 0);
3097 des = dma_map_single(priv->device, skb->data,
3098 nopaged_len, DMA_TO_DEVICE);
3099 if (dma_mapping_error(priv->device, des))
3102 tx_q->tx_skbuff_dma[first_entry].buf = des;
3103 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
3104 first->des0 = cpu_to_le32(des);
3106 first->des2 = cpu_to_le32(des);
3108 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len;
3109 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment;
3111 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
3112 priv->hwts_tx_en)) {
3113 /* declare that device is doing timestamping */
3114 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
3115 priv->hw->desc->enable_tx_timestamp(first);
3118 /* Prepare the first descriptor setting the OWN bit too */
3119 priv->hw->desc->prepare_tx_desc(first, 1, nopaged_len,
3120 csum_insertion, priv->mode, 1,
3121 last_segment, skb->len);
3123 /* The own bit must be the latest setting done when prepare the
3124 * descriptor and then barrier is needed to make sure that
3125 * all is coherent before granting the DMA engine.
3130 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
3132 if (priv->synopsys_id < DWMAC_CORE_4_00)
3133 priv->hw->dma->enable_dma_transmission(priv->ioaddr);
3135 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, tx_q->tx_tail_addr,
3138 return NETDEV_TX_OK;
3141 netdev_err(priv->dev, "Tx DMA map failed\n");
3143 priv->dev->stats.tx_dropped++;
3144 return NETDEV_TX_OK;
3147 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
3149 struct ethhdr *ehdr;
3152 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) ==
3153 NETIF_F_HW_VLAN_CTAG_RX &&
3154 !__vlan_get_tag(skb, &vlanid)) {
3155 /* pop the vlan tag */
3156 ehdr = (struct ethhdr *)skb->data;
3157 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
3158 skb_pull(skb, VLAN_HLEN);
3159 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
3164 static inline int stmmac_rx_threshold_count(struct stmmac_rx_queue *rx_q)
3166 if (rx_q->rx_zeroc_thresh < STMMAC_RX_THRESH)
3173 * stmmac_rx_refill - refill used skb preallocated buffers
3174 * @priv: driver private structure
3175 * @queue: RX queue index
3176 * Description : this is to reallocate the skb for the reception process
3177 * that is based on zero-copy.
3179 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)
3181 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3182 int dirty = stmmac_rx_dirty(priv, queue);
3183 unsigned int entry = rx_q->dirty_rx;
3185 int bfsize = priv->dma_buf_sz;
3187 while (dirty-- > 0) {
3190 if (priv->extend_desc)
3191 p = (struct dma_desc *)(rx_q->dma_erx + entry);
3193 p = rx_q->dma_rx + entry;
3195 if (likely(!rx_q->rx_skbuff[entry])) {
3196 struct sk_buff *skb;
3198 skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
3199 if (unlikely(!skb)) {
3200 /* so for a while no zero-copy! */
3201 rx_q->rx_zeroc_thresh = STMMAC_RX_THRESH;
3202 if (unlikely(net_ratelimit()))
3203 dev_err(priv->device,
3204 "fail to alloc skb entry %d\n",
3209 rx_q->rx_skbuff[entry] = skb;
3210 rx_q->rx_skbuff_dma[entry] =
3211 dma_map_single(priv->device, skb->data, bfsize,
3213 if (dma_mapping_error(priv->device,
3214 rx_q->rx_skbuff_dma[entry])) {
3215 netdev_err(priv->dev, "Rx DMA map failed\n");
3220 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) {
3221 p->des0 = cpu_to_le32(rx_q->rx_skbuff_dma[entry]);
3224 p->des2 = cpu_to_le32(rx_q->rx_skbuff_dma[entry]);
3226 if (priv->hw->mode->refill_desc3)
3227 priv->hw->mode->refill_desc3(rx_q, p);
3229 if (rx_q->rx_zeroc_thresh > 0)
3230 rx_q->rx_zeroc_thresh--;
3232 netif_dbg(priv, rx_status, priv->dev,
3233 "refill entry #%d\n", entry);
3237 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
3238 priv->hw->desc->init_rx_desc(p, priv->use_riwt, 0, 0);
3240 priv->hw->desc->set_rx_owner(p);
3244 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE);
3246 rx_q->dirty_rx = entry;
3250 * stmmac_rx - manage the receive process
3251 * @priv: driver private structure
3252 * @limit: napi bugget
3253 * @queue: RX queue index.
3254 * Description : this the function called by the napi poll method.
3255 * It gets all the frames inside the ring.
3257 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
3259 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3260 unsigned int entry = rx_q->cur_rx;
3261 int coe = priv->hw->rx_csum;
3262 unsigned int next_entry;
3263 unsigned int count = 0;
3265 if (netif_msg_rx_status(priv)) {
3268 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
3269 if (priv->extend_desc)
3270 rx_head = (void *)rx_q->dma_erx;
3272 rx_head = (void *)rx_q->dma_rx;
3274 priv->hw->desc->display_ring(rx_head, DMA_RX_SIZE, true);
3276 while (count < limit) {
3279 struct dma_desc *np;
3281 if (priv->extend_desc)
3282 p = (struct dma_desc *)(rx_q->dma_erx + entry);
3284 p = rx_q->dma_rx + entry;
3286 /* read the status of the incoming frame */
3287 status = priv->hw->desc->rx_status(&priv->dev->stats,
3289 /* check if managed by the DMA otherwise go ahead */
3290 if (unlikely(status & dma_own))
3295 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, DMA_RX_SIZE);
3296 next_entry = rx_q->cur_rx;
3298 if (priv->extend_desc)
3299 np = (struct dma_desc *)(rx_q->dma_erx + next_entry);
3301 np = rx_q->dma_rx + next_entry;
3305 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
3306 priv->hw->desc->rx_extended_status(&priv->dev->stats,
3310 if (unlikely(status == discard_frame)) {
3311 priv->dev->stats.rx_errors++;
3312 if (priv->hwts_rx_en && !priv->extend_desc) {
3313 /* DESC2 & DESC3 will be overwritten by device
3314 * with timestamp value, hence reinitialize
3315 * them in stmmac_rx_refill() function so that
3316 * device can reuse it.
3318 rx_q->rx_skbuff[entry] = NULL;
3319 dma_unmap_single(priv->device,
3320 rx_q->rx_skbuff_dma[entry],
3325 struct sk_buff *skb;
3329 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
3330 des = le32_to_cpu(p->des0);
3332 des = le32_to_cpu(p->des2);
3334 frame_len = priv->hw->desc->get_rx_frame_len(p, coe);
3336 /* If frame length is greater than skb buffer size
3337 * (preallocated during init) then the packet is
3340 if (frame_len > priv->dma_buf_sz) {
3341 netdev_err(priv->dev,
3342 "len %d larger than size (%d)\n",
3343 frame_len, priv->dma_buf_sz);
3344 priv->dev->stats.rx_length_errors++;
3348 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
3349 * Type frames (LLC/LLC-SNAP)
3351 if (unlikely(status != llc_snap))
3352 frame_len -= ETH_FCS_LEN;
3354 if (netif_msg_rx_status(priv)) {
3355 netdev_dbg(priv->dev, "\tdesc: %p [entry %d] buff=0x%x\n",
3357 if (frame_len > ETH_FRAME_LEN)
3358 netdev_dbg(priv->dev, "frame size %d, COE: %d\n",
3362 /* The zero-copy is always used for all the sizes
3363 * in case of GMAC4 because it needs
3364 * to refill the used descriptors, always.
3366 if (unlikely(!priv->plat->has_gmac4 &&
3367 ((frame_len < priv->rx_copybreak) ||
3368 stmmac_rx_threshold_count(rx_q)))) {
3369 skb = netdev_alloc_skb_ip_align(priv->dev,
3371 if (unlikely(!skb)) {
3372 if (net_ratelimit())
3373 dev_warn(priv->device,
3374 "packet dropped\n");
3375 priv->dev->stats.rx_dropped++;
3379 dma_sync_single_for_cpu(priv->device,
3383 skb_copy_to_linear_data(skb,
3385 rx_skbuff[entry]->data,
3388 skb_put(skb, frame_len);
3389 dma_sync_single_for_device(priv->device,
3394 skb = rx_q->rx_skbuff[entry];
3395 if (unlikely(!skb)) {
3396 netdev_err(priv->dev,
3397 "%s: Inconsistent Rx chain\n",
3399 priv->dev->stats.rx_dropped++;
3402 prefetch(skb->data - NET_IP_ALIGN);
3403 rx_q->rx_skbuff[entry] = NULL;
3404 rx_q->rx_zeroc_thresh++;
3406 skb_put(skb, frame_len);
3407 dma_unmap_single(priv->device,
3408 rx_q->rx_skbuff_dma[entry],
3413 if (netif_msg_pktdata(priv)) {
3414 netdev_dbg(priv->dev, "frame received (%dbytes)",
3416 print_pkt(skb->data, frame_len);
3419 stmmac_get_rx_hwtstamp(priv, p, np, skb);
3421 stmmac_rx_vlan(priv->dev, skb);
3423 skb->protocol = eth_type_trans(skb, priv->dev);
3426 skb_checksum_none_assert(skb);
3428 skb->ip_summed = CHECKSUM_UNNECESSARY;
3430 napi_gro_receive(&rx_q->napi, skb);
3432 priv->dev->stats.rx_packets++;
3433 priv->dev->stats.rx_bytes += frame_len;
3438 stmmac_rx_refill(priv, queue);
3440 priv->xstats.rx_pkt_n += count;
3446 * stmmac_poll - stmmac poll method (NAPI)
3447 * @napi : pointer to the napi structure.
3448 * @budget : maximum number of packets that the current CPU can receive from
3451 * To look at the incoming frames and clear the tx resources.
3453 static int stmmac_poll(struct napi_struct *napi, int budget)
3455 struct stmmac_rx_queue *rx_q =
3456 container_of(napi, struct stmmac_rx_queue, napi);
3457 struct stmmac_priv *priv = rx_q->priv_data;
3458 u32 tx_count = priv->plat->tx_queues_to_use;
3459 u32 chan = rx_q->queue_index;
3463 priv->xstats.napi_poll++;
3465 /* check all the queues */
3466 for (queue = 0; queue < tx_count; queue++)
3467 stmmac_tx_clean(priv, queue);
3469 work_done = stmmac_rx(priv, budget, rx_q->queue_index);
3470 if (work_done < budget) {
3471 napi_complete_done(napi, work_done);
3472 stmmac_enable_dma_irq(priv, chan);
3479 * @dev : Pointer to net device structure
3480 * Description: this function is called when a packet transmission fails to
3481 * complete within a reasonable time. The driver will mark the error in the
3482 * netdev structure and arrange for the device to be reset to a sane state
3483 * in order to transmit a new packet.
3485 static void stmmac_tx_timeout(struct net_device *dev)
3487 struct stmmac_priv *priv = netdev_priv(dev);
3488 u32 tx_count = priv->plat->tx_queues_to_use;
3491 /* Clear Tx resources and restart transmitting again */
3492 for (chan = 0; chan < tx_count; chan++)
3493 stmmac_tx_err(priv, chan);
3497 * stmmac_set_rx_mode - entry point for multicast addressing
3498 * @dev : pointer to the device structure
3500 * This function is a driver entry point which gets called by the kernel
3501 * whenever multicast addresses must be enabled/disabled.
3505 static void stmmac_set_rx_mode(struct net_device *dev)
3507 struct stmmac_priv *priv = netdev_priv(dev);
3509 priv->hw->mac->set_filter(priv->hw, dev);
3513 * stmmac_change_mtu - entry point to change MTU size for the device.
3514 * @dev : device pointer.
3515 * @new_mtu : the new MTU size for the device.
3516 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
3517 * to drive packet transmission. Ethernet has an MTU of 1500 octets
3518 * (ETH_DATA_LEN). This value can be changed with ifconfig.
3520 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3523 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
3525 struct stmmac_priv *priv = netdev_priv(dev);
3527 if (netif_running(dev)) {
3528 netdev_err(priv->dev, "must be stopped to change its MTU\n");
3534 netdev_update_features(dev);
3539 static netdev_features_t stmmac_fix_features(struct net_device *dev,
3540 netdev_features_t features)
3542 struct stmmac_priv *priv = netdev_priv(dev);
3544 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
3545 features &= ~NETIF_F_RXCSUM;
3547 if (!priv->plat->tx_coe)
3548 features &= ~NETIF_F_CSUM_MASK;
3550 /* Some GMAC devices have a bugged Jumbo frame support that
3551 * needs to have the Tx COE disabled for oversized frames
3552 * (due to limited buffer sizes). In this case we disable
3553 * the TX csum insertion in the TDES and not use SF.
3555 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
3556 features &= ~NETIF_F_CSUM_MASK;
3558 /* Disable tso if asked by ethtool */
3559 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
3560 if (features & NETIF_F_TSO)
3569 static int stmmac_set_features(struct net_device *netdev,
3570 netdev_features_t features)
3572 struct stmmac_priv *priv = netdev_priv(netdev);
3574 /* Keep the COE Type in case of csum is supporting */
3575 if (features & NETIF_F_RXCSUM)
3576 priv->hw->rx_csum = priv->plat->rx_coe;
3578 priv->hw->rx_csum = 0;
3579 /* No check needed because rx_coe has been set before and it will be
3580 * fixed in case of issue.
3582 priv->hw->mac->rx_ipc(priv->hw);
3588 * stmmac_interrupt - main ISR
3589 * @irq: interrupt number.
3590 * @dev_id: to pass the net device pointer.
3591 * Description: this is the main driver interrupt service routine.
3593 * o DMA service routine (to manage incoming frame reception and transmission
3595 * o Core interrupts to manage: remote wake-up, management counter, LPI
3598 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
3600 struct net_device *dev = (struct net_device *)dev_id;
3601 struct stmmac_priv *priv = netdev_priv(dev);
3602 u32 rx_cnt = priv->plat->rx_queues_to_use;
3603 u32 tx_cnt = priv->plat->tx_queues_to_use;
3607 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt;
3610 pm_wakeup_event(priv->device, 0);
3612 if (unlikely(!dev)) {
3613 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
3617 /* To handle GMAC own interrupts */
3618 if ((priv->plat->has_gmac) || (priv->plat->has_gmac4)) {
3619 int status = priv->hw->mac->host_irq_status(priv->hw,
3622 if (unlikely(status)) {
3623 /* For LPI we need to save the tx status */
3624 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
3625 priv->tx_path_in_lpi_mode = true;
3626 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
3627 priv->tx_path_in_lpi_mode = false;
3630 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
3631 for (queue = 0; queue < queues_count; queue++) {
3632 struct stmmac_rx_queue *rx_q =
3633 &priv->rx_queue[queue];
3636 priv->hw->mac->host_mtl_irq_status(priv->hw,
3639 if (status & CORE_IRQ_MTL_RX_OVERFLOW &&
3640 priv->hw->dma->set_rx_tail_ptr)
3641 priv->hw->dma->set_rx_tail_ptr(priv->ioaddr,
3647 /* PCS link status */
3648 if (priv->hw->pcs) {
3649 if (priv->xstats.pcs_link)
3650 netif_carrier_on(dev);
3652 netif_carrier_off(dev);
3656 /* To handle DMA interrupts */
3657 stmmac_dma_interrupt(priv);
3662 #ifdef CONFIG_NET_POLL_CONTROLLER
3663 /* Polling receive - used by NETCONSOLE and other diagnostic tools
3664 * to allow network I/O with interrupts disabled.
3666 static void stmmac_poll_controller(struct net_device *dev)
3668 disable_irq(dev->irq);
3669 stmmac_interrupt(dev->irq, dev);
3670 enable_irq(dev->irq);
3675 * stmmac_ioctl - Entry point for the Ioctl
3676 * @dev: Device pointer.
3677 * @rq: An IOCTL specefic structure, that can contain a pointer to
3678 * a proprietary structure used to pass information to the driver.
3679 * @cmd: IOCTL command
3681 * Currently it supports the phy_mii_ioctl(...) and HW time stamping.
3683 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3685 int ret = -EOPNOTSUPP;
3687 if (!netif_running(dev))
3696 ret = phy_mii_ioctl(dev->phydev, rq, cmd);
3699 ret = stmmac_hwtstamp_ioctl(dev, rq);
3708 #ifdef CONFIG_DEBUG_FS
3709 static struct dentry *stmmac_fs_dir;
3711 static void sysfs_display_ring(void *head, int size, int extend_desc,
3712 struct seq_file *seq)
3715 struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
3716 struct dma_desc *p = (struct dma_desc *)head;
3718 for (i = 0; i < size; i++) {
3720 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
3721 i, (unsigned int)virt_to_phys(ep),
3722 le32_to_cpu(ep->basic.des0),
3723 le32_to_cpu(ep->basic.des1),
3724 le32_to_cpu(ep->basic.des2),
3725 le32_to_cpu(ep->basic.des3));
3728 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
3729 i, (unsigned int)virt_to_phys(p),
3730 le32_to_cpu(p->des0), le32_to_cpu(p->des1),
3731 le32_to_cpu(p->des2), le32_to_cpu(p->des3));
3734 seq_printf(seq, "\n");
3738 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
3740 struct net_device *dev = seq->private;
3741 struct stmmac_priv *priv = netdev_priv(dev);
3742 u32 rx_count = priv->plat->rx_queues_to_use;
3743 u32 tx_count = priv->plat->tx_queues_to_use;
3746 for (queue = 0; queue < rx_count; queue++) {
3747 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3749 seq_printf(seq, "RX Queue %d:\n", queue);
3751 if (priv->extend_desc) {
3752 seq_printf(seq, "Extended descriptor ring:\n");
3753 sysfs_display_ring((void *)rx_q->dma_erx,
3754 DMA_RX_SIZE, 1, seq);
3756 seq_printf(seq, "Descriptor ring:\n");
3757 sysfs_display_ring((void *)rx_q->dma_rx,
3758 DMA_RX_SIZE, 0, seq);
3762 for (queue = 0; queue < tx_count; queue++) {
3763 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
3765 seq_printf(seq, "TX Queue %d:\n", queue);
3767 if (priv->extend_desc) {
3768 seq_printf(seq, "Extended descriptor ring:\n");
3769 sysfs_display_ring((void *)tx_q->dma_etx,
3770 DMA_TX_SIZE, 1, seq);
3772 seq_printf(seq, "Descriptor ring:\n");
3773 sysfs_display_ring((void *)tx_q->dma_tx,
3774 DMA_TX_SIZE, 0, seq);
3781 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
3783 return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
3786 /* Debugfs files, should appear in /sys/kernel/debug/stmmaceth/eth0 */
3788 static const struct file_operations stmmac_rings_status_fops = {
3789 .owner = THIS_MODULE,
3790 .open = stmmac_sysfs_ring_open,
3792 .llseek = seq_lseek,
3793 .release = single_release,
3796 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
3798 struct net_device *dev = seq->private;
3799 struct stmmac_priv *priv = netdev_priv(dev);
3801 if (!priv->hw_cap_support) {
3802 seq_printf(seq, "DMA HW features not supported\n");
3806 seq_printf(seq, "==============================\n");
3807 seq_printf(seq, "\tDMA HW features\n");
3808 seq_printf(seq, "==============================\n");
3810 seq_printf(seq, "\t10/100 Mbps: %s\n",
3811 (priv->dma_cap.mbps_10_100) ? "Y" : "N");
3812 seq_printf(seq, "\t1000 Mbps: %s\n",
3813 (priv->dma_cap.mbps_1000) ? "Y" : "N");
3814 seq_printf(seq, "\tHalf duplex: %s\n",
3815 (priv->dma_cap.half_duplex) ? "Y" : "N");
3816 seq_printf(seq, "\tHash Filter: %s\n",
3817 (priv->dma_cap.hash_filter) ? "Y" : "N");
3818 seq_printf(seq, "\tMultiple MAC address registers: %s\n",
3819 (priv->dma_cap.multi_addr) ? "Y" : "N");
3820 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n",
3821 (priv->dma_cap.pcs) ? "Y" : "N");
3822 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
3823 (priv->dma_cap.sma_mdio) ? "Y" : "N");
3824 seq_printf(seq, "\tPMT Remote wake up: %s\n",
3825 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
3826 seq_printf(seq, "\tPMT Magic Frame: %s\n",
3827 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
3828 seq_printf(seq, "\tRMON module: %s\n",
3829 (priv->dma_cap.rmon) ? "Y" : "N");
3830 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
3831 (priv->dma_cap.time_stamp) ? "Y" : "N");
3832 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n",
3833 (priv->dma_cap.atime_stamp) ? "Y" : "N");
3834 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n",
3835 (priv->dma_cap.eee) ? "Y" : "N");
3836 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
3837 seq_printf(seq, "\tChecksum Offload in TX: %s\n",
3838 (priv->dma_cap.tx_coe) ? "Y" : "N");
3839 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
3840 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n",
3841 (priv->dma_cap.rx_coe) ? "Y" : "N");
3843 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
3844 (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
3845 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
3846 (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
3848 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
3849 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
3850 seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
3851 priv->dma_cap.number_rx_channel);
3852 seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
3853 priv->dma_cap.number_tx_channel);
3854 seq_printf(seq, "\tEnhanced descriptors: %s\n",
3855 (priv->dma_cap.enh_desc) ? "Y" : "N");
3860 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
3862 return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
3865 static const struct file_operations stmmac_dma_cap_fops = {
3866 .owner = THIS_MODULE,
3867 .open = stmmac_sysfs_dma_cap_open,
3869 .llseek = seq_lseek,
3870 .release = single_release,
3873 static int stmmac_init_fs(struct net_device *dev)
3875 struct stmmac_priv *priv = netdev_priv(dev);
3877 /* Create per netdev entries */
3878 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
3880 if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) {
3881 netdev_err(priv->dev, "ERROR failed to create debugfs directory\n");
3886 /* Entry to report DMA RX/TX rings */
3887 priv->dbgfs_rings_status =
3888 debugfs_create_file("descriptors_status", S_IRUGO,
3889 priv->dbgfs_dir, dev,
3890 &stmmac_rings_status_fops);
3892 if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) {
3893 netdev_err(priv->dev, "ERROR creating stmmac ring debugfs file\n");
3894 debugfs_remove_recursive(priv->dbgfs_dir);
3899 /* Entry to report the DMA HW features */
3900 priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", S_IRUGO,
3902 dev, &stmmac_dma_cap_fops);
3904 if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) {
3905 netdev_err(priv->dev, "ERROR creating stmmac MMC debugfs file\n");
3906 debugfs_remove_recursive(priv->dbgfs_dir);
3914 static void stmmac_exit_fs(struct net_device *dev)
3916 struct stmmac_priv *priv = netdev_priv(dev);
3918 debugfs_remove_recursive(priv->dbgfs_dir);
3920 #endif /* CONFIG_DEBUG_FS */
3922 static const struct net_device_ops stmmac_netdev_ops = {
3923 .ndo_open = stmmac_open,
3924 .ndo_start_xmit = stmmac_xmit,
3925 .ndo_stop = stmmac_release,
3926 .ndo_change_mtu = stmmac_change_mtu,
3927 .ndo_fix_features = stmmac_fix_features,
3928 .ndo_set_features = stmmac_set_features,
3929 .ndo_set_rx_mode = stmmac_set_rx_mode,
3930 .ndo_tx_timeout = stmmac_tx_timeout,
3931 .ndo_do_ioctl = stmmac_ioctl,
3932 #ifdef CONFIG_NET_POLL_CONTROLLER
3933 .ndo_poll_controller = stmmac_poll_controller,
3935 .ndo_set_mac_address = eth_mac_addr,
3939 * stmmac_hw_init - Init the MAC device
3940 * @priv: driver private structure
3941 * Description: this function is to configure the MAC device according to
3942 * some platform parameters or the HW capability register. It prepares the
3943 * driver to use either ring or chain modes and to setup either enhanced or
3944 * normal descriptors.
3946 static int stmmac_hw_init(struct stmmac_priv *priv)
3948 struct mac_device_info *mac;
3950 /* Identify the MAC HW device */
3951 if (priv->plat->has_gmac) {
3952 priv->dev->priv_flags |= IFF_UNICAST_FLT;
3953 mac = dwmac1000_setup(priv->ioaddr,
3954 priv->plat->multicast_filter_bins,
3955 priv->plat->unicast_filter_entries,
3956 &priv->synopsys_id);
3957 } else if (priv->plat->has_gmac4) {
3958 priv->dev->priv_flags |= IFF_UNICAST_FLT;
3959 mac = dwmac4_setup(priv->ioaddr,
3960 priv->plat->multicast_filter_bins,
3961 priv->plat->unicast_filter_entries,
3962 &priv->synopsys_id);
3964 mac = dwmac100_setup(priv->ioaddr, &priv->synopsys_id);
3971 /* To use the chained or ring mode */
3972 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
3973 priv->hw->mode = &dwmac4_ring_mode_ops;
3976 priv->hw->mode = &chain_mode_ops;
3977 dev_info(priv->device, "Chain mode enabled\n");
3978 priv->mode = STMMAC_CHAIN_MODE;
3980 priv->hw->mode = &ring_mode_ops;
3981 dev_info(priv->device, "Ring mode enabled\n");
3982 priv->mode = STMMAC_RING_MODE;
3986 /* Get the HW capability (new GMAC newer than 3.50a) */
3987 priv->hw_cap_support = stmmac_get_hw_features(priv);
3988 if (priv->hw_cap_support) {
3989 dev_info(priv->device, "DMA HW capability register supported\n");
3991 /* We can override some gmac/dma configuration fields: e.g.
3992 * enh_desc, tx_coe (e.g. that are passed through the
3993 * platform) with the values from the HW capability
3994 * register (if supported).
3996 priv->plat->enh_desc = priv->dma_cap.enh_desc;
3997 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
3998 priv->hw->pmt = priv->plat->pmt;
4000 /* TXCOE doesn't work in thresh DMA mode */
4001 if (priv->plat->force_thresh_dma_mode)
4002 priv->plat->tx_coe = 0;
4004 priv->plat->tx_coe = priv->dma_cap.tx_coe;
4006 /* In case of GMAC4 rx_coe is from HW cap register. */
4007 priv->plat->rx_coe = priv->dma_cap.rx_coe;
4009 if (priv->dma_cap.rx_coe_type2)
4010 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
4011 else if (priv->dma_cap.rx_coe_type1)
4012 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
4015 dev_info(priv->device, "No HW DMA feature register supported\n");
4018 /* To use alternate (extended), normal or GMAC4 descriptor structures */
4019 if (priv->synopsys_id >= DWMAC_CORE_4_00)
4020 priv->hw->desc = &dwmac4_desc_ops;
4022 stmmac_selec_desc_mode(priv);
4024 if (priv->plat->rx_coe) {
4025 priv->hw->rx_csum = priv->plat->rx_coe;
4026 dev_info(priv->device, "RX Checksum Offload Engine supported\n");
4027 if (priv->synopsys_id < DWMAC_CORE_4_00)
4028 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum);
4030 if (priv->plat->tx_coe)
4031 dev_info(priv->device, "TX Checksum insertion supported\n");
4033 if (priv->plat->pmt) {
4034 dev_info(priv->device, "Wake-Up On Lan supported\n");
4035 device_set_wakeup_capable(priv->device, 1);
4038 if (priv->dma_cap.tsoen)
4039 dev_info(priv->device, "TSO supported\n");
4046 * @device: device pointer
4047 * @plat_dat: platform data pointer
4048 * @res: stmmac resource pointer
4049 * Description: this is the main probe function used to
4050 * call the alloc_etherdev, allocate the priv structure.
4052 * returns 0 on success, otherwise errno.
4054 int stmmac_dvr_probe(struct device *device,
4055 struct plat_stmmacenet_data *plat_dat,
4056 struct stmmac_resources *res)
4058 struct net_device *ndev = NULL;
4059 struct stmmac_priv *priv;
4063 ndev = alloc_etherdev_mqs(sizeof(struct stmmac_priv),
4069 SET_NETDEV_DEV(ndev, device);
4071 priv = netdev_priv(ndev);
4072 priv->device = device;
4075 stmmac_set_ethtool_ops(ndev);
4076 priv->pause = pause;
4077 priv->plat = plat_dat;
4078 priv->ioaddr = res->addr;
4079 priv->dev->base_addr = (unsigned long)res->addr;
4081 priv->dev->irq = res->irq;
4082 priv->wol_irq = res->wol_irq;
4083 priv->lpi_irq = res->lpi_irq;
4086 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
4088 dev_set_drvdata(device, priv->dev);
4090 /* Verify driver arguments */
4091 stmmac_verify_args();
4093 /* Override with kernel parameters if supplied XXX CRS XXX
4094 * this needs to have multiple instances
4096 if ((phyaddr >= 0) && (phyaddr <= 31))
4097 priv->plat->phy_addr = phyaddr;
4099 if (priv->plat->stmmac_rst)
4100 reset_control_deassert(priv->plat->stmmac_rst);
4102 /* Init MAC and get the capabilities */
4103 ret = stmmac_hw_init(priv);
4107 /* Configure real RX and TX queues */
4108 netif_set_real_num_rx_queues(ndev, priv->plat->rx_queues_to_use);
4109 netif_set_real_num_tx_queues(ndev, priv->plat->tx_queues_to_use);
4111 ndev->netdev_ops = &stmmac_netdev_ops;
4113 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4116 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
4117 ndev->hw_features |= NETIF_F_TSO;
4119 dev_info(priv->device, "TSO feature enabled\n");
4121 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
4122 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
4123 #ifdef STMMAC_VLAN_TAG_USED
4124 /* Both mac100 and gmac support receive VLAN tag detection */
4125 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
4127 priv->msg_enable = netif_msg_init(debug, default_msg_level);
4129 /* MTU range: 46 - hw-specific max */
4130 ndev->min_mtu = ETH_ZLEN - ETH_HLEN;
4131 if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00))
4132 ndev->max_mtu = JUMBO_LEN;
4134 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
4135 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu
4136 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range.
4138 if ((priv->plat->maxmtu < ndev->max_mtu) &&
4139 (priv->plat->maxmtu >= ndev->min_mtu))
4140 ndev->max_mtu = priv->plat->maxmtu;
4141 else if (priv->plat->maxmtu < ndev->min_mtu)
4142 dev_warn(priv->device,
4143 "%s: warning: maxmtu having invalid value (%d)\n",
4144 __func__, priv->plat->maxmtu);
4147 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
4149 /* Rx Watchdog is available in the COREs newer than the 3.40.
4150 * In some case, for example on bugged HW this feature
4151 * has to be disable and this can be done by passing the
4152 * riwt_off field from the platform.
4154 if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
4156 dev_info(priv->device,
4157 "Enable RX Mitigation via HW Watchdog Timer\n");
4160 for (queue = 0; queue < priv->plat->rx_queues_to_use; queue++) {
4161 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4163 netif_napi_add(ndev, &rx_q->napi, stmmac_poll,
4164 (8 * priv->plat->rx_queues_to_use));
4167 spin_lock_init(&priv->lock);
4169 /* If a specific clk_csr value is passed from the platform
4170 * this means that the CSR Clock Range selection cannot be
4171 * changed at run-time and it is fixed. Viceversa the driver'll try to
4172 * set the MDC clock dynamically according to the csr actual
4175 if (!priv->plat->clk_csr)
4176 stmmac_clk_csr_set(priv);
4178 priv->clk_csr = priv->plat->clk_csr;
4180 stmmac_check_pcs_mode(priv);
4182 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4183 priv->hw->pcs != STMMAC_PCS_TBI &&
4184 priv->hw->pcs != STMMAC_PCS_RTBI) {
4185 /* MDIO bus Registration */
4186 ret = stmmac_mdio_register(ndev);
4188 dev_err(priv->device,
4189 "%s: MDIO bus (id: %d) registration failed",
4190 __func__, priv->plat->bus_id);
4191 goto error_mdio_register;
4195 ret = register_netdev(ndev);
4197 dev_err(priv->device, "%s: ERROR %i registering the device\n",
4199 goto error_netdev_register;
4204 error_netdev_register:
4205 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4206 priv->hw->pcs != STMMAC_PCS_TBI &&
4207 priv->hw->pcs != STMMAC_PCS_RTBI)
4208 stmmac_mdio_unregister(ndev);
4209 error_mdio_register:
4210 for (queue = 0; queue < priv->plat->rx_queues_to_use; queue++) {
4211 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4213 netif_napi_del(&rx_q->napi);
4220 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
4224 * @dev: device pointer
4225 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
4226 * changes the link status, releases the DMA descriptor rings.
4228 int stmmac_dvr_remove(struct device *dev)
4230 struct net_device *ndev = dev_get_drvdata(dev);
4231 struct stmmac_priv *priv = netdev_priv(ndev);
4233 netdev_info(priv->dev, "%s: removing driver", __func__);
4235 stmmac_stop_all_dma(priv);
4237 priv->hw->mac->set_mac(priv->ioaddr, false);
4238 netif_carrier_off(ndev);
4239 unregister_netdev(ndev);
4240 if (priv->plat->stmmac_rst)
4241 reset_control_assert(priv->plat->stmmac_rst);
4242 clk_disable_unprepare(priv->plat->pclk);
4243 clk_disable_unprepare(priv->plat->stmmac_clk);
4244 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4245 priv->hw->pcs != STMMAC_PCS_TBI &&
4246 priv->hw->pcs != STMMAC_PCS_RTBI)
4247 stmmac_mdio_unregister(ndev);
4252 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
4255 * stmmac_suspend - suspend callback
4256 * @dev: device pointer
4257 * Description: this is the function to suspend the device and it is called
4258 * by the platform driver to stop the network queue, release the resources,
4259 * program the PMT register (for WoL), clean and release driver resources.
4261 int stmmac_suspend(struct device *dev)
4263 struct net_device *ndev = dev_get_drvdata(dev);
4264 struct stmmac_priv *priv = netdev_priv(ndev);
4265 unsigned long flags;
4267 if (!ndev || !netif_running(ndev))
4271 phy_stop(ndev->phydev);
4273 spin_lock_irqsave(&priv->lock, flags);
4275 netif_device_detach(ndev);
4276 stmmac_stop_all_queues(priv);
4278 stmmac_disable_all_queues(priv);
4280 /* Stop TX/RX DMA */
4281 stmmac_stop_all_dma(priv);
4283 /* Enable Power down mode by programming the PMT regs */
4284 if (device_may_wakeup(priv->device)) {
4285 priv->hw->mac->pmt(priv->hw, priv->wolopts);
4288 priv->hw->mac->set_mac(priv->ioaddr, false);
4289 pinctrl_pm_select_sleep_state(priv->device);
4290 /* Disable clock in case of PWM is off */
4291 clk_disable(priv->plat->pclk);
4292 clk_disable(priv->plat->stmmac_clk);
4294 spin_unlock_irqrestore(&priv->lock, flags);
4297 priv->speed = SPEED_UNKNOWN;
4298 priv->oldduplex = DUPLEX_UNKNOWN;
4301 EXPORT_SYMBOL_GPL(stmmac_suspend);
4304 * stmmac_reset_queues_param - reset queue parameters
4305 * @dev: device pointer
4307 static void stmmac_reset_queues_param(struct stmmac_priv *priv)
4309 u32 rx_cnt = priv->plat->rx_queues_to_use;
4310 u32 tx_cnt = priv->plat->tx_queues_to_use;
4313 for (queue = 0; queue < rx_cnt; queue++) {
4314 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4320 for (queue = 0; queue < tx_cnt; queue++) {
4321 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
4329 * stmmac_resume - resume callback
4330 * @dev: device pointer
4331 * Description: when resume this function is invoked to setup the DMA and CORE
4332 * in a usable state.
4334 int stmmac_resume(struct device *dev)
4336 struct net_device *ndev = dev_get_drvdata(dev);
4337 struct stmmac_priv *priv = netdev_priv(ndev);
4338 unsigned long flags;
4340 if (!netif_running(ndev))
4343 /* Power Down bit, into the PM register, is cleared
4344 * automatically as soon as a magic packet or a Wake-up frame
4345 * is received. Anyway, it's better to manually clear
4346 * this bit because it can generate problems while resuming
4347 * from another devices (e.g. serial console).
4349 if (device_may_wakeup(priv->device)) {
4350 spin_lock_irqsave(&priv->lock, flags);
4351 priv->hw->mac->pmt(priv->hw, 0);
4352 spin_unlock_irqrestore(&priv->lock, flags);
4355 pinctrl_pm_select_default_state(priv->device);
4356 /* enable the clk previously disabled */
4357 clk_enable(priv->plat->stmmac_clk);
4358 clk_enable(priv->plat->pclk);
4359 /* reset the phy so that it's ready */
4361 stmmac_mdio_reset(priv->mii);
4364 netif_device_attach(ndev);
4366 spin_lock_irqsave(&priv->lock, flags);
4368 stmmac_reset_queues_param(priv);
4370 /* reset private mss value to force mss context settings at
4371 * next tso xmit (only used for gmac4).
4375 stmmac_clear_descriptors(priv);
4377 stmmac_hw_setup(ndev, false);
4378 stmmac_init_tx_coalesce(priv);
4379 stmmac_set_rx_mode(ndev);
4381 stmmac_enable_all_queues(priv);
4383 stmmac_start_all_queues(priv);
4385 spin_unlock_irqrestore(&priv->lock, flags);
4388 phy_start(ndev->phydev);
4392 EXPORT_SYMBOL_GPL(stmmac_resume);
4395 static int __init stmmac_cmdline_opt(char *str)
4401 while ((opt = strsep(&str, ",")) != NULL) {
4402 if (!strncmp(opt, "debug:", 6)) {
4403 if (kstrtoint(opt + 6, 0, &debug))
4405 } else if (!strncmp(opt, "phyaddr:", 8)) {
4406 if (kstrtoint(opt + 8, 0, &phyaddr))
4408 } else if (!strncmp(opt, "buf_sz:", 7)) {
4409 if (kstrtoint(opt + 7, 0, &buf_sz))
4411 } else if (!strncmp(opt, "tc:", 3)) {
4412 if (kstrtoint(opt + 3, 0, &tc))
4414 } else if (!strncmp(opt, "watchdog:", 9)) {
4415 if (kstrtoint(opt + 9, 0, &watchdog))
4417 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
4418 if (kstrtoint(opt + 10, 0, &flow_ctrl))
4420 } else if (!strncmp(opt, "pause:", 6)) {
4421 if (kstrtoint(opt + 6, 0, &pause))
4423 } else if (!strncmp(opt, "eee_timer:", 10)) {
4424 if (kstrtoint(opt + 10, 0, &eee_timer))
4426 } else if (!strncmp(opt, "chain_mode:", 11)) {
4427 if (kstrtoint(opt + 11, 0, &chain_mode))
4434 pr_err("%s: ERROR broken module parameter conversion", __func__);
4438 __setup("stmmaceth=", stmmac_cmdline_opt);
4441 static int __init stmmac_init(void)
4443 #ifdef CONFIG_DEBUG_FS
4444 /* Create debugfs main directory if it doesn't exist yet */
4445 if (!stmmac_fs_dir) {
4446 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
4448 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
4449 pr_err("ERROR %s, debugfs create directory failed\n",
4450 STMMAC_RESOURCE_NAME);
4460 static void __exit stmmac_exit(void)
4462 #ifdef CONFIG_DEBUG_FS
4463 debugfs_remove_recursive(stmmac_fs_dir);
4467 module_init(stmmac_init)
4468 module_exit(stmmac_exit)
4470 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
4471 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
4472 MODULE_LICENSE("GPL");