drivers/net/ethernet/ti/cpsw.c

   1 /*
   2  * Texas Instruments Ethernet Switch Driver
   3  *
   4  * Copyright (C) 2012 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/io.h>
  18 #include <linux/clk.h>
  19 #include <linux/timer.h>
  20 #include <linux/module.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/irqreturn.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/if_ether.h>
  25 #include <linux/etherdevice.h>
  26 #include <linux/netdevice.h>
  27 #include <linux/net_tstamp.h>
  28 #include <linux/phy.h>
  29 #include <linux/workqueue.h>
  30 #include <linux/delay.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/gpio.h>
  33 #include <linux/of.h>
  34 #include <linux/of_mdio.h>
  35 #include <linux/of_net.h>
  36 #include <linux/of_device.h>
  37 #include <linux/if_vlan.h>
  38
  39 #include <linux/pinctrl/consumer.h>
  40
  41 #include "cpsw.h"
  42 #include "cpsw_ale.h"
  43 #include "cpts.h"
  44 #include "davinci_cpdma.h"
  45
  46 #define CPSW_DEBUG      (NETIF_MSG_HW           | NETIF_MSG_WOL         | \
  47                          NETIF_MSG_DRV          | NETIF_MSG_LINK        | \
  48                          NETIF_MSG_IFUP         | NETIF_MSG_INTR        | \
  49                          NETIF_MSG_PROBE        | NETIF_MSG_TIMER       | \
  50                          NETIF_MSG_IFDOWN       | NETIF_MSG_RX_ERR      | \
  51                          NETIF_MSG_TX_ERR       | NETIF_MSG_TX_DONE     | \
  52                          NETIF_MSG_PKTDATA      | NETIF_MSG_TX_QUEUED   | \
  53                          NETIF_MSG_RX_STATUS)
  54
  55 #define cpsw_info(priv, type, format, ...)              \
  56 do {                                                            \
  57         if (netif_msg_##type(priv) && net_ratelimit())          \
  58                 dev_info(priv->dev, format, ## __VA_ARGS__);    \
  59 } while (0)
  60
  61 #define cpsw_err(priv, type, format, ...)               \
  62 do {                                                            \
  63         if (netif_msg_##type(priv) && net_ratelimit())          \
  64                 dev_err(priv->dev, format, ## __VA_ARGS__);     \
  65 } while (0)
  66
  67 #define cpsw_dbg(priv, type, format, ...)               \
  68 do {                                                            \
  69         if (netif_msg_##type(priv) && net_ratelimit())          \
  70                 dev_dbg(priv->dev, format, ## __VA_ARGS__);     \
  71 } while (0)
  72
  73 #define cpsw_notice(priv, type, format, ...)            \
  74 do {                                                            \
  75         if (netif_msg_##type(priv) && net_ratelimit())          \
  76                 dev_notice(priv->dev, format, ## __VA_ARGS__);  \
  77 } while (0)
  78
  79 #define ALE_ALL_PORTS           0x7
  80
  81 #define CPSW_MAJOR_VERSION(reg)         (reg >> 8 & 0x7)
  82 #define CPSW_MINOR_VERSION(reg)         (reg & 0xff)
  83 #define CPSW_RTL_VERSION(reg)           ((reg >> 11) & 0x1f)
  84
  85 #define CPSW_VERSION_1          0x19010a
  86 #define CPSW_VERSION_2          0x19010c
  87 #define CPSW_VERSION_3          0x19010f
  88 #define CPSW_VERSION_4          0x190112
  89
  90 #define HOST_PORT_NUM           0
  91 #define SLIVER_SIZE             0x40
  92
  93 #define CPSW1_HOST_PORT_OFFSET  0x028
  94 #define CPSW1_SLAVE_OFFSET      0x050
  95 #define CPSW1_SLAVE_SIZE        0x040
  96 #define CPSW1_CPDMA_OFFSET      0x100
  97 #define CPSW1_STATERAM_OFFSET   0x200
  98 #define CPSW1_HW_STATS          0x400
  99 #define CPSW1_CPTS_OFFSET       0x500
 100 #define CPSW1_ALE_OFFSET        0x600
 101 #define CPSW1_SLIVER_OFFSET     0x700
 102
 103 #define CPSW2_HOST_PORT_OFFSET  0x108
 104 #define CPSW2_SLAVE_OFFSET      0x200
 105 #define CPSW2_SLAVE_SIZE        0x100
 106 #define CPSW2_CPDMA_OFFSET      0x800
 107 #define CPSW2_HW_STATS          0x900
 108 #define CPSW2_STATERAM_OFFSET   0xa00
 109 #define CPSW2_CPTS_OFFSET       0xc00
 110 #define CPSW2_ALE_OFFSET        0xd00
 111 #define CPSW2_SLIVER_OFFSET     0xd80
 112 #define CPSW2_BD_OFFSET         0x2000
 113
 114 #define CPDMA_RXTHRESH          0x0c0
 115 #define CPDMA_RXFREE            0x0e0
 116 #define CPDMA_TXHDP             0x00
 117 #define CPDMA_RXHDP             0x20
 118 #define CPDMA_TXCP              0x40
 119 #define CPDMA_RXCP              0x60
 120
 121 #define CPSW_POLL_WEIGHT        64
 122 #define CPSW_MIN_PACKET_SIZE    60
 123 #define CPSW_MAX_PACKET_SIZE    (1500 + 14 + 4 + 4)
 124
 125 #define RX_PRIORITY_MAPPING     0x76543210
 126 #define TX_PRIORITY_MAPPING     0x33221100
 127 #define CPDMA_TX_PRIORITY_MAP   0x76543210
 128
 129 #define CPSW_VLAN_AWARE         BIT(1)
 130 #define CPSW_ALE_VLAN_AWARE     1
 131
 132 #define CPSW_FIFO_NORMAL_MODE           (0 << 16)
 133 #define CPSW_FIFO_DUAL_MAC_MODE         (1 << 16)
 134 #define CPSW_FIFO_RATE_LIMIT_MODE       (2 << 16)
 135
 136 #define CPSW_INTPACEEN          (0x3f << 16)
 137 #define CPSW_INTPRESCALE_MASK   (0x7FF << 0)
 138 #define CPSW_CMINTMAX_CNT       63
 139 #define CPSW_CMINTMIN_CNT       2
 140 #define CPSW_CMINTMAX_INTVL     (1000 / CPSW_CMINTMIN_CNT)
 141 #define CPSW_CMINTMIN_INTVL     ((1000 / CPSW_CMINTMAX_CNT) + 1)
 142
 143 #define cpsw_slave_index(priv)                          \
 144                 ((priv->data.dual_emac) ? priv->emac_port :     \
 145                 priv->data.active_slave)
 146
 147 static int debug_level;
 148 module_param(debug_level, int, 0);
 149 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
 150
 151 static int ale_ageout = 10;
 152 module_param(ale_ageout, int, 0);
 153 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
 154
 155 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
 156 module_param(rx_packet_max, int, 0);
 157 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
 158
 159 struct cpsw_wr_regs {
 160         u32     id_ver;
 161         u32     soft_reset;
 162         u32     control;
 163         u32     int_control;
 164         u32     rx_thresh_en;
 165         u32     rx_en;
 166         u32     tx_en;
 167         u32     misc_en;
 168         u32     mem_allign1[8];
 169         u32     rx_thresh_stat;
 170         u32     rx_stat;
 171         u32     tx_stat;
 172         u32     misc_stat;
 173         u32     mem_allign2[8];
 174         u32     rx_imax;
 175         u32     tx_imax;
 176
 177 };
 178
 179 struct cpsw_ss_regs {
 180         u32     id_ver;
 181         u32     control;
 182         u32     soft_reset;
 183         u32     stat_port_en;
 184         u32     ptype;
 185         u32     soft_idle;
 186         u32     thru_rate;
 187         u32     gap_thresh;
 188         u32     tx_start_wds;
 189         u32     flow_control;
 190         u32     vlan_ltype;
 191         u32     ts_ltype;
 192         u32     dlr_ltype;
 193 };
 194
 195 /* CPSW_PORT_V1 */
 196 #define CPSW1_MAX_BLKS      0x00 /* Maximum FIFO Blocks */
 197 #define CPSW1_BLK_CNT       0x04 /* FIFO Block Usage Count (Read Only) */
 198 #define CPSW1_TX_IN_CTL     0x08 /* Transmit FIFO Control */
 199 #define CPSW1_PORT_VLAN     0x0c /* VLAN Register */
 200 #define CPSW1_TX_PRI_MAP    0x10 /* Tx Header Priority to Switch Pri Mapping */
 201 #define CPSW1_TS_CTL        0x14 /* Time Sync Control */
 202 #define CPSW1_TS_SEQ_LTYPE  0x18 /* Time Sync Sequence ID Offset and Msg Type */
 203 #define CPSW1_TS_VLAN       0x1c /* Time Sync VLAN1 and VLAN2 */
 204
 205 /* CPSW_PORT_V2 */
 206 #define CPSW2_CONTROL       0x00 /* Control Register */
 207 #define CPSW2_MAX_BLKS      0x08 /* Maximum FIFO Blocks */
 208 #define CPSW2_BLK_CNT       0x0c /* FIFO Block Usage Count (Read Only) */
 209 #define CPSW2_TX_IN_CTL     0x10 /* Transmit FIFO Control */
 210 #define CPSW2_PORT_VLAN     0x14 /* VLAN Register */
 211 #define CPSW2_TX_PRI_MAP    0x18 /* Tx Header Priority to Switch Pri Mapping */
 212 #define CPSW2_TS_SEQ_MTYPE  0x1c /* Time Sync Sequence ID Offset and Msg Type */
 213
 214 /* CPSW_PORT_V1 and V2 */
 215 #define SA_LO               0x20 /* CPGMAC_SL Source Address Low */
 216 #define SA_HI               0x24 /* CPGMAC_SL Source Address High */
 217 #define SEND_PERCENT        0x28 /* Transmit Queue Send Percentages */
 218
 219 /* CPSW_PORT_V2 only */
 220 #define RX_DSCP_PRI_MAP0    0x30 /* Rx DSCP Priority to Rx Packet Mapping */
 221 #define RX_DSCP_PRI_MAP1    0x34 /* Rx DSCP Priority to Rx Packet Mapping */
 222 #define RX_DSCP_PRI_MAP2    0x38 /* Rx DSCP Priority to Rx Packet Mapping */
 223 #define RX_DSCP_PRI_MAP3    0x3c /* Rx DSCP Priority to Rx Packet Mapping */
 224 #define RX_DSCP_PRI_MAP4    0x40 /* Rx DSCP Priority to Rx Packet Mapping */
 225 #define RX_DSCP_PRI_MAP5    0x44 /* Rx DSCP Priority to Rx Packet Mapping */
 226 #define RX_DSCP_PRI_MAP6    0x48 /* Rx DSCP Priority to Rx Packet Mapping */
 227 #define RX_DSCP_PRI_MAP7    0x4c /* Rx DSCP Priority to Rx Packet Mapping */
 228
 229 /* Bit definitions for the CPSW2_CONTROL register */
 230 #define PASS_PRI_TAGGED     (1<<24) /* Pass Priority Tagged */
 231 #define VLAN_LTYPE2_EN      (1<<21) /* VLAN LTYPE 2 enable */
 232 #define VLAN_LTYPE1_EN      (1<<20) /* VLAN LTYPE 1 enable */
 233 #define DSCP_PRI_EN         (1<<16) /* DSCP Priority Enable */
 234 #define TS_320              (1<<14) /* Time Sync Dest Port 320 enable */
 235 #define TS_319              (1<<13) /* Time Sync Dest Port 319 enable */
 236 #define TS_132              (1<<12) /* Time Sync Dest IP Addr 132 enable */
 237 #define TS_131              (1<<11) /* Time Sync Dest IP Addr 131 enable */
 238 #define TS_130              (1<<10) /* Time Sync Dest IP Addr 130 enable */
 239 #define TS_129              (1<<9)  /* Time Sync Dest IP Addr 129 enable */
 240 #define TS_TTL_NONZERO      (1<<8)  /* Time Sync Time To Live Non-zero enable */
 241 #define TS_ANNEX_F_EN       (1<<6)  /* Time Sync Annex F enable */
 242 #define TS_ANNEX_D_EN       (1<<4)  /* Time Sync Annex D enable */
 243 #define TS_LTYPE2_EN        (1<<3)  /* Time Sync LTYPE 2 enable */
 244 #define TS_LTYPE1_EN        (1<<2)  /* Time Sync LTYPE 1 enable */
 245 #define TS_TX_EN            (1<<1)  /* Time Sync Transmit Enable */
 246 #define TS_RX_EN            (1<<0)  /* Time Sync Receive Enable */
 247
 248 #define CTRL_V2_TS_BITS \
 249         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 250          TS_TTL_NONZERO  | TS_ANNEX_D_EN | TS_LTYPE1_EN)
 251
 252 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
 253 #define CTRL_V2_TX_TS_BITS  (CTRL_V2_TS_BITS | TS_TX_EN)
 254 #define CTRL_V2_RX_TS_BITS  (CTRL_V2_TS_BITS | TS_RX_EN)
 255
 256
 257 #define CTRL_V3_TS_BITS \
 258         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 259          TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
 260          TS_LTYPE1_EN)
 261
 262 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
 263 #define CTRL_V3_TX_TS_BITS  (CTRL_V3_TS_BITS | TS_TX_EN)
 264 #define CTRL_V3_RX_TS_BITS  (CTRL_V3_TS_BITS | TS_RX_EN)
 265
 266 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
 267 #define TS_SEQ_ID_OFFSET_SHIFT   (16)    /* Time Sync Sequence ID Offset */
 268 #define TS_SEQ_ID_OFFSET_MASK    (0x3f)
 269 #define TS_MSG_TYPE_EN_SHIFT     (0)     /* Time Sync Message Type Enable */
 270 #define TS_MSG_TYPE_EN_MASK      (0xffff)
 271
 272 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
 273 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
 274
 275 /* Bit definitions for the CPSW1_TS_CTL register */
 276 #define CPSW_V1_TS_RX_EN                BIT(0)
 277 #define CPSW_V1_TS_TX_EN                BIT(4)
 278 #define CPSW_V1_MSG_TYPE_OFS            16
 279
 280 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
 281 #define CPSW_V1_SEQ_ID_OFS_SHIFT        16
 282
 283 struct cpsw_host_regs {
 284         u32     max_blks;
 285         u32     blk_cnt;
 286         u32     tx_in_ctl;
 287         u32     port_vlan;
 288         u32     tx_pri_map;
 289         u32     cpdma_tx_pri_map;
 290         u32     cpdma_rx_chan_map;
 291 };
 292
 293 struct cpsw_sliver_regs {
 294         u32     id_ver;
 295         u32     mac_control;
 296         u32     mac_status;
 297         u32     soft_reset;
 298         u32     rx_maxlen;
 299         u32     __reserved_0;
 300         u32     rx_pause;
 301         u32     tx_pause;
 302         u32     __reserved_1;
 303         u32     rx_pri_map;
 304 };
 305
 306 struct cpsw_hw_stats {
 307         u32     rxgoodframes;
 308         u32     rxbroadcastframes;
 309         u32     rxmulticastframes;
 310         u32     rxpauseframes;
 311         u32     rxcrcerrors;
 312         u32     rxaligncodeerrors;
 313         u32     rxoversizedframes;
 314         u32     rxjabberframes;
 315         u32     rxundersizedframes;
 316         u32     rxfragments;
 317         u32     __pad_0[2];
 318         u32     rxoctets;
 319         u32     txgoodframes;
 320         u32     txbroadcastframes;
 321         u32     txmulticastframes;
 322         u32     txpauseframes;
 323         u32     txdeferredframes;
 324         u32     txcollisionframes;
 325         u32     txsinglecollframes;
 326         u32     txmultcollframes;
 327         u32     txexcessivecollisions;
 328         u32     txlatecollisions;
 329         u32     txunderrun;
 330         u32     txcarriersenseerrors;
 331         u32     txoctets;
 332         u32     octetframes64;
 333         u32     octetframes65t127;
 334         u32     octetframes128t255;
 335         u32     octetframes256t511;
 336         u32     octetframes512t1023;
 337         u32     octetframes1024tup;
 338         u32     netoctets;
 339         u32     rxsofoverruns;
 340         u32     rxmofoverruns;
 341         u32     rxdmaoverruns;
 342 };
 343
 344 struct cpsw_slave {
 345         void __iomem                    *regs;
 346         struct cpsw_sliver_regs __iomem *sliver;
 347         int                             slave_num;
 348         u32                             mac_control;
 349         struct cpsw_slave_data          *data;
 350         struct phy_device               *phy;
 351         struct net_device               *ndev;
 352         u32                             port_vlan;
 353         u32                             open_stat;
 354 };
 355
 356 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
 357 {
 358         return __raw_readl(slave->regs + offset);
 359 }
 360
 361 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
 362 {
 363         __raw_writel(val, slave->regs + offset);
 364 }
 365
 366 struct cpsw_priv {
 367         spinlock_t                      lock;
 368         struct platform_device          *pdev;
 369         struct net_device               *ndev;
 370         struct device_node              *phy_node;
 371         struct napi_struct              napi_rx;
 372         struct napi_struct              napi_tx;
 373         struct device                   *dev;
 374         struct cpsw_platform_data       data;
 375         struct cpsw_ss_regs __iomem     *regs;
 376         struct cpsw_wr_regs __iomem     *wr_regs;
 377         u8 __iomem                      *hw_stats;
 378         struct cpsw_host_regs __iomem   *host_port_regs;
 379         u32                             msg_enable;
 380         u32                             version;
 381         u32                             coal_intvl;
 382         u32                             bus_freq_mhz;
 383         int                             rx_packet_max;
 384         struct clk                      *clk;
 385         u8                              mac_addr[ETH_ALEN];
 386         struct cpsw_slave               *slaves;
 387         struct cpdma_ctlr               *dma;
 388         struct cpdma_chan               *txch, *rxch;
 389         struct cpsw_ale                 *ale;
 390         bool                            rx_pause;
 391         bool                            tx_pause;
 392         bool                            quirk_irq;
 393         bool                            rx_irq_disabled;
 394         bool                            tx_irq_disabled;
 395         /* snapshot of IRQ numbers */
 396         u32 irqs_table[4];
 397         u32 num_irqs;
 398         struct cpts *cpts;
 399         u32 emac_port;
 400 };
 401
 402 struct cpsw_stats {
 403         char stat_string[ETH_GSTRING_LEN];
 404         int type;
 405         int sizeof_stat;
 406         int stat_offset;
 407 };
 408
 409 enum {
 410         CPSW_STATS,
 411         CPDMA_RX_STATS,
 412         CPDMA_TX_STATS,
 413 };
 414
 415 #define CPSW_STAT(m)            CPSW_STATS,                             \
 416                                 sizeof(((struct cpsw_hw_stats *)0)->m), \
 417                                 offsetof(struct cpsw_hw_stats, m)
 418 #define CPDMA_RX_STAT(m)        CPDMA_RX_STATS,                            \
 419                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 420                                 offsetof(struct cpdma_chan_stats, m)
 421 #define CPDMA_TX_STAT(m)        CPDMA_TX_STATS,                            \
 422                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 423                                 offsetof(struct cpdma_chan_stats, m)
 424
 425 static const struct cpsw_stats cpsw_gstrings_stats[] = {
 426         { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
 427         { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
 428         { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
 429         { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
 430         { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
 431         { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
 432         { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
 433         { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
 434         { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
 435         { "Rx Fragments", CPSW_STAT(rxfragments) },
 436         { "Rx Octets", CPSW_STAT(rxoctets) },
 437         { "Good Tx Frames", CPSW_STAT(txgoodframes) },
 438         { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
 439         { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
 440         { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
 441         { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
 442         { "Collisions", CPSW_STAT(txcollisionframes) },
 443         { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
 444         { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
 445         { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
 446         { "Late Collisions", CPSW_STAT(txlatecollisions) },
 447         { "Tx Underrun", CPSW_STAT(txunderrun) },
 448         { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
 449         { "Tx Octets", CPSW_STAT(txoctets) },
 450         { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
 451         { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
 452         { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
 453         { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
 454         { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
 455         { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
 456         { "Net Octets", CPSW_STAT(netoctets) },
 457         { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
 458         { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
 459         { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
 460         { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) },
 461         { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
 462         { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
 463         { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) },
 464         { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
 465         { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
 466         { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
 467         { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
 468         { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
 469         { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
 470         { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) },
 471         { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) },
 472         { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
 473         { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) },
 474         { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) },
 475         { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) },
 476         { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) },
 477         { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) },
 478         { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) },
 479         { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) },
 480         { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) },
 481         { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) },
 482         { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) },
 483         { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) },
 484         { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) },
 485         { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) },
 486 };
 487
 488 #define CPSW_STATS_LEN  ARRAY_SIZE(cpsw_gstrings_stats)
 489
 490 #define napi_to_priv(napi)      container_of(napi, struct cpsw_priv, napi)
 491 #define for_each_slave(priv, func, arg...)                              \
 492         do {                                                            \
 493                 struct cpsw_slave *slave;                               \
 494                 int n;                                                  \
 495                 if (priv->data.dual_emac)                               \
 496                         (func)((priv)->slaves + priv->emac_port, ##arg);\
 497                 else                                                    \
 498                         for (n = (priv)->data.slaves,                   \
 499                                         slave = (priv)->slaves;         \
 500                                         n; n--)                         \
 501                                 (func)(slave++, ##arg);                 \
 502         } while (0)
 503 #define cpsw_get_slave_ndev(priv, __slave_no__)                         \
 504         ((__slave_no__ < priv->data.slaves) ?                           \
 505                 priv->slaves[__slave_no__].ndev : NULL)
 506 #define cpsw_get_slave_priv(priv, __slave_no__)                         \
 507         (((__slave_no__ < priv->data.slaves) &&                         \
 508                 (priv->slaves[__slave_no__].ndev)) ?                    \
 509                 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL)    \
 510
 511 #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb)         \
 512         do {                                                            \
 513                 if (!priv->data.dual_emac)                              \
 514                         break;                                          \
 515                 if (CPDMA_RX_SOURCE_PORT(status) == 1) {                \
 516                         ndev = cpsw_get_slave_ndev(priv, 0);            \
 517                         priv = netdev_priv(ndev);                       \
 518                         skb->dev = ndev;                                \
 519                 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) {         \
 520                         ndev = cpsw_get_slave_ndev(priv, 1);            \
 521                         priv = netdev_priv(ndev);                       \
 522                         skb->dev = ndev;                                \
 523                 }                                                       \
 524         } while (0)
 525 #define cpsw_add_mcast(priv, addr)                                      \
 526         do {                                                            \
 527                 if (priv->data.dual_emac) {                             \
 528                         struct cpsw_slave *slave = priv->slaves +       \
 529                                                 priv->emac_port;        \
 530                         int slave_port = cpsw_get_slave_port(priv,      \
 531                                                 slave->slave_num);      \
 532                         cpsw_ale_add_mcast(priv->ale, addr,             \
 533                                 1 << slave_port | ALE_PORT_HOST,        \
 534                                 ALE_VLAN, slave->port_vlan, 0);         \
 535                 } else {                                                \
 536                         cpsw_ale_add_mcast(priv->ale, addr,             \
 537                                 ALE_ALL_PORTS,                          \
 538                                 0, 0, 0);                               \
 539                 }                                                       \
 540         } while (0)
 541
 542 static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
 543 {
 544         return slave_num + 1;
 545 }
 546
 547 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
 548 {
 549         struct cpsw_priv *priv = netdev_priv(ndev);
 550         struct cpsw_ale *ale = priv->ale;
 551         int i;
 552
 553         if (priv->data.dual_emac) {
 554                 bool flag = false;
 555
 556                 /* Enabling promiscuous mode for one interface will be
 557                  * common for both the interface as the interface shares
 558                  * the same hardware resource.
 559                  */
 560                 for (i = 0; i < priv->data.slaves; i++)
 561                         if (priv->slaves[i].ndev->flags & IFF_PROMISC)
 562                                 flag = true;
 563
 564                 if (!enable && flag) {
 565                         enable = true;
 566                         dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
 567                 }
 568
 569                 if (enable) {
 570                         /* Enable Bypass */
 571                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
 572
 573                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 574                 } else {
 575                         /* Disable Bypass */
 576                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
 577                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 578                 }
 579         } else {
 580                 if (enable) {
 581                         unsigned long timeout = jiffies + HZ;
 582
 583                         /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
 584                         for (i = 0; i <= priv->data.slaves; i++) {
 585                                 cpsw_ale_control_set(ale, i,
 586                                                      ALE_PORT_NOLEARN, 1);
 587                                 cpsw_ale_control_set(ale, i,
 588                                                      ALE_PORT_NO_SA_UPDATE, 1);
 589                         }
 590
 591                         /* Clear All Untouched entries */
 592                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 593                         do {
 594                                 cpu_relax();
 595                                 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
 596                                         break;
 597                         } while (time_after(timeout, jiffies));
 598                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 599
 600                         /* Clear all mcast from ALE */
 601                         cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS, -1);
 602
 603                         /* Flood All Unicast Packets to Host port */
 604                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
 605                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 606                 } else {
 607                         /* Don't Flood All Unicast Packets to Host port */
 608                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
 609
 610                         /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
 611                         for (i = 0; i <= priv->data.slaves; i++) {
 612                                 cpsw_ale_control_set(ale, i,
 613                                                      ALE_PORT_NOLEARN, 0);
 614                                 cpsw_ale_control_set(ale, i,
 615                                                      ALE_PORT_NO_SA_UPDATE, 0);
 616                         }
 617                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 618                 }
 619         }
 620 }
 621
 622 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
 623 {
 624         struct cpsw_priv *priv = netdev_priv(ndev);
 625         int vid;
 626
 627         if (priv->data.dual_emac)
 628                 vid = priv->slaves[priv->emac_port].port_vlan;
 629         else
 630                 vid = priv->data.default_vlan;
 631
 632         if (ndev->flags & IFF_PROMISC) {
 633                 /* Enable promiscuous mode */
 634                 cpsw_set_promiscious(ndev, true);
 635                 cpsw_ale_set_allmulti(priv->ale, IFF_ALLMULTI);
 636                 return;
 637         } else {
 638                 /* Disable promiscuous mode */
 639                 cpsw_set_promiscious(ndev, false);
 640         }
 641
 642         /* Restore allmulti on vlans if necessary */
 643         cpsw_ale_set_allmulti(priv->ale, priv->ndev->flags & IFF_ALLMULTI);
 644
 645         /* Clear all mcast from ALE */
 646         cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS, vid);
 647
 648         if (!netdev_mc_empty(ndev)) {
 649                 struct netdev_hw_addr *ha;
 650
 651                 /* program multicast address list into ALE register */
 652                 netdev_for_each_mc_addr(ha, ndev) {
 653                         cpsw_add_mcast(priv, (u8 *)ha->addr);
 654                 }
 655         }
 656 }
 657
 658 static void cpsw_intr_enable(struct cpsw_priv *priv)
 659 {
 660         __raw_writel(0xFF, &priv->wr_regs->tx_en);
 661         __raw_writel(0xFF, &priv->wr_regs->rx_en);
 662
 663         cpdma_ctlr_int_ctrl(priv->dma, true);
 664         return;
 665 }
 666
 667 static void cpsw_intr_disable(struct cpsw_priv *priv)
 668 {
 669         __raw_writel(0, &priv->wr_regs->tx_en);
 670         __raw_writel(0, &priv->wr_regs->rx_en);
 671
 672         cpdma_ctlr_int_ctrl(priv->dma, false);
 673         return;
 674 }
 675
 676 static void cpsw_tx_handler(void *token, int len, int status)
 677 {
 678         struct sk_buff          *skb = token;
 679         struct net_device       *ndev = skb->dev;
 680         struct cpsw_priv        *priv = netdev_priv(ndev);
 681
 682         /* Check whether the queue is stopped due to stalled tx dma, if the
 683          * queue is stopped then start the queue as we have free desc for tx
 684          */
 685         if (unlikely(netif_queue_stopped(ndev)))
 686                 netif_wake_queue(ndev);
 687         cpts_tx_timestamp(priv->cpts, skb);
 688         ndev->stats.tx_packets++;
 689         ndev->stats.tx_bytes += len;
 690         dev_kfree_skb_any(skb);
 691 }
 692
 693 static void cpsw_rx_handler(void *token, int len, int status)
 694 {
 695         struct sk_buff          *skb = token;
 696         struct sk_buff          *new_skb;
 697         struct net_device       *ndev = skb->dev;
 698         struct cpsw_priv        *priv = netdev_priv(ndev);
 699         int                     ret = 0;
 700
 701         cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
 702
 703         if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
 704                 bool ndev_status = false;
 705                 struct cpsw_slave *slave = priv->slaves;
 706                 int n;
 707
 708                 if (priv->data.dual_emac) {
 709                         /* In dual emac mode check for all interfaces */
 710                         for (n = priv->data.slaves; n; n--, slave++)
 711                                 if (netif_running(slave->ndev))
 712                                         ndev_status = true;
 713                 }
 714
 715                 if (ndev_status && (status >= 0)) {
 716                         /* The packet received is for the interface which
 717                          * is already down and the other interface is up
 718                          * and running, instead of freeing which results
 719                          * in reducing of the number of rx descriptor in
 720                          * DMA engine, requeue skb back to cpdma.
 721                          */
 722                         new_skb = skb;
 723                         goto requeue;
 724                 }
 725
 726                 /* the interface is going down, skbs are purged */
 727                 dev_kfree_skb_any(skb);
 728                 return;
 729         }
 730
 731         new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
 732         if (new_skb) {
 733                 skb_put(skb, len);
 734                 cpts_rx_timestamp(priv->cpts, skb);
 735                 skb->protocol = eth_type_trans(skb, ndev);
 736                 netif_receive_skb(skb);
 737                 ndev->stats.rx_bytes += len;
 738                 ndev->stats.rx_packets++;
 739         } else {
 740                 ndev->stats.rx_dropped++;
 741                 new_skb = skb;
 742         }
 743
 744 requeue:
 745         ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
 746                         skb_tailroom(new_skb), 0);
 747         if (WARN_ON(ret < 0))
 748                 dev_kfree_skb_any(new_skb);
 749 }
 750
 751 static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
 752 {
 753         struct cpsw_priv *priv = dev_id;
 754
 755         writel(0, &priv->wr_regs->tx_en);
 756         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
 757
 758         if (priv->quirk_irq) {
 759                 disable_irq_nosync(priv->irqs_table[1]);
 760                 priv->tx_irq_disabled = true;
 761         }
 762
 763         napi_schedule(&priv->napi_tx);
 764         return IRQ_HANDLED;
 765 }
 766
 767 static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
 768 {
 769         struct cpsw_priv *priv = dev_id;
 770
 771         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
 772         writel(0, &priv->wr_regs->rx_en);
 773
 774         if (priv->quirk_irq) {
 775                 disable_irq_nosync(priv->irqs_table[0]);
 776                 priv->rx_irq_disabled = true;
 777         }
 778
 779         napi_schedule(&priv->napi_rx);
 780         return IRQ_HANDLED;
 781 }
 782
 783 static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
 784 {
 785         struct cpsw_priv        *priv = napi_to_priv(napi_tx);
 786         int                     num_tx;
 787
 788         num_tx = cpdma_chan_process(priv->txch, budget);
 789         if (num_tx < budget) {
 790                 napi_complete(napi_tx);
 791                 writel(0xff, &priv->wr_regs->tx_en);
 792                 if (priv->quirk_irq && priv->tx_irq_disabled) {
 793                         priv->tx_irq_disabled = false;
 794                         enable_irq(priv->irqs_table[1]);
 795                 }
 796         }
 797
 798         if (num_tx)
 799                 cpsw_dbg(priv, intr, "poll %d tx pkts\n", num_tx);
 800
 801         return num_tx;
 802 }
 803
 804 static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
 805 {
 806         struct cpsw_priv        *priv = napi_to_priv(napi_rx);
 807         int                     num_rx;
 808
 809         num_rx = cpdma_chan_process(priv->rxch, budget);
 810         if (num_rx < budget) {
 811                 napi_complete(napi_rx);
 812                 writel(0xff, &priv->wr_regs->rx_en);
 813                 if (priv->quirk_irq && priv->rx_irq_disabled) {
 814                         priv->rx_irq_disabled = false;
 815                         enable_irq(priv->irqs_table[0]);
 816                 }
 817         }
 818
 819         if (num_rx)
 820                 cpsw_dbg(priv, intr, "poll %d rx pkts\n", num_rx);
 821
 822         return num_rx;
 823 }
 824
 825 static inline void soft_reset(const char *module, void __iomem *reg)
 826 {
 827         unsigned long timeout = jiffies + HZ;
 828
 829         __raw_writel(1, reg);
 830         do {
 831                 cpu_relax();
 832         } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
 833
 834         WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
 835 }
 836
 837 #define mac_hi(mac)     (((mac)[0] << 0) | ((mac)[1] << 8) |    \
 838                          ((mac)[2] << 16) | ((mac)[3] << 24))
 839 #define mac_lo(mac)     (((mac)[4] << 0) | ((mac)[5] << 8))
 840
 841 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
 842                                struct cpsw_priv *priv)
 843 {
 844         slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
 845         slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
 846 }
 847
 848 static void _cpsw_adjust_link(struct cpsw_slave *slave,
 849                               struct cpsw_priv *priv, bool *link)
 850 {
 851         struct phy_device       *phy = slave->phy;
 852         u32                     mac_control = 0;
 853         u32                     slave_port;
 854
 855         if (!phy)
 856                 return;
 857
 858         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
 859
 860         if (phy->link) {
 861                 mac_control = priv->data.mac_control;
 862
 863                 /* enable forwarding */
 864                 cpsw_ale_control_set(priv->ale, slave_port,
 865                                      ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
 866
 867                 if (phy->speed == 1000)
 868                         mac_control |= BIT(7);  /* GIGABITEN    */
 869                 if (phy->duplex)
 870                         mac_control |= BIT(0);  /* FULLDUPLEXEN */
 871
 872                 /* set speed_in input in case RMII mode is used in 100Mbps */
 873                 if (phy->speed == 100)
 874                         mac_control |= BIT(15);
 875                 else if (phy->speed == 10)
 876                         mac_control |= BIT(18); /* In Band mode */
 877
 878                 if (priv->rx_pause)
 879                         mac_control |= BIT(3);
 880
 881                 if (priv->tx_pause)
 882                         mac_control |= BIT(4);
 883
 884                 *link = true;
 885         } else {
 886                 mac_control = 0;
 887                 /* disable forwarding */
 888                 cpsw_ale_control_set(priv->ale, slave_port,
 889                                      ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
 890         }
 891
 892         if (mac_control != slave->mac_control) {
 893                 phy_print_status(phy);
 894                 __raw_writel(mac_control, &slave->sliver->mac_control);
 895         }
 896
 897         slave->mac_control = mac_control;
 898 }
 899
 900 static void cpsw_adjust_link(struct net_device *ndev)
 901 {
 902         struct cpsw_priv        *priv = netdev_priv(ndev);
 903         bool                    link = false;
 904
 905         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
 906
 907         if (link) {
 908                 netif_carrier_on(ndev);
 909                 if (netif_running(ndev))
 910                         netif_wake_queue(ndev);
 911         } else {
 912                 netif_carrier_off(ndev);
 913                 netif_stop_queue(ndev);
 914         }
 915 }
 916
 917 static int cpsw_get_coalesce(struct net_device *ndev,
 918                                 struct ethtool_coalesce *coal)
 919 {
 920         struct cpsw_priv *priv = netdev_priv(ndev);
 921
 922         coal->rx_coalesce_usecs = priv->coal_intvl;
 923         return 0;
 924 }
 925
 926 static int cpsw_set_coalesce(struct net_device *ndev,
 927                                 struct ethtool_coalesce *coal)
 928 {
 929         struct cpsw_priv *priv = netdev_priv(ndev);
 930         u32 int_ctrl;
 931         u32 num_interrupts = 0;
 932         u32 prescale = 0;
 933         u32 addnl_dvdr = 1;
 934         u32 coal_intvl = 0;
 935
 936         coal_intvl = coal->rx_coalesce_usecs;
 937
 938         int_ctrl =  readl(&priv->wr_regs->int_control);
 939         prescale = priv->bus_freq_mhz * 4;
 940
 941         if (!coal->rx_coalesce_usecs) {
 942                 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
 943                 goto update_return;
 944         }
 945
 946         if (coal_intvl < CPSW_CMINTMIN_INTVL)
 947                 coal_intvl = CPSW_CMINTMIN_INTVL;
 948
 949         if (coal_intvl > CPSW_CMINTMAX_INTVL) {
 950                 /* Interrupt pacer works with 4us Pulse, we can
 951                  * throttle further by dilating the 4us pulse.
 952                  */
 953                 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
 954
 955                 if (addnl_dvdr > 1) {
 956                         prescale *= addnl_dvdr;
 957                         if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
 958                                 coal_intvl = (CPSW_CMINTMAX_INTVL
 959                                                 * addnl_dvdr);
 960                 } else {
 961                         addnl_dvdr = 1;
 962                         coal_intvl = CPSW_CMINTMAX_INTVL;
 963                 }
 964         }
 965
 966         num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
 967         writel(num_interrupts, &priv->wr_regs->rx_imax);
 968         writel(num_interrupts, &priv->wr_regs->tx_imax);
 969
 970         int_ctrl |= CPSW_INTPACEEN;
 971         int_ctrl &= (~CPSW_INTPRESCALE_MASK);
 972         int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
 973
 974 update_return:
 975         writel(int_ctrl, &priv->wr_regs->int_control);
 976
 977         cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
 978         if (priv->data.dual_emac) {
 979                 int i;
 980
 981                 for (i = 0; i < priv->data.slaves; i++) {
 982                         priv = netdev_priv(priv->slaves[i].ndev);
 983                         priv->coal_intvl = coal_intvl;
 984                 }
 985         } else {
 986                 priv->coal_intvl = coal_intvl;
 987         }
 988
 989         return 0;
 990 }
 991
 992 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
 993 {
 994         switch (sset) {
 995         case ETH_SS_STATS:
 996                 return CPSW_STATS_LEN;
 997         default:
 998                 return -EOPNOTSUPP;
 999         }
1000 }
1001
1002 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1003 {
1004         u8 *p = data;
1005         int i;
1006
1007         switch (stringset) {
1008         case ETH_SS_STATS:
1009                 for (i = 0; i < CPSW_STATS_LEN; i++) {
1010                         memcpy(p, cpsw_gstrings_stats[i].stat_string,
1011                                ETH_GSTRING_LEN);
1012                         p += ETH_GSTRING_LEN;
1013                 }
1014                 break;
1015         }
1016 }
1017
1018 static void cpsw_get_ethtool_stats(struct net_device *ndev,
1019                                     struct ethtool_stats *stats, u64 *data)
1020 {
1021         struct cpsw_priv *priv = netdev_priv(ndev);
1022         struct cpdma_chan_stats rx_stats;
1023         struct cpdma_chan_stats tx_stats;
1024         u32 val;
1025         u8 *p;
1026         int i;
1027
1028         /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1029         cpdma_chan_get_stats(priv->rxch, &rx_stats);
1030         cpdma_chan_get_stats(priv->txch, &tx_stats);
1031
1032         for (i = 0; i < CPSW_STATS_LEN; i++) {
1033                 switch (cpsw_gstrings_stats[i].type) {
1034                 case CPSW_STATS:
1035                         val = readl(priv->hw_stats +
1036                                     cpsw_gstrings_stats[i].stat_offset);
1037                         data[i] = val;
1038                         break;
1039
1040                 case CPDMA_RX_STATS:
1041                         p = (u8 *)&rx_stats +
1042                                 cpsw_gstrings_stats[i].stat_offset;
1043                         data[i] = *(u32 *)p;
1044                         break;
1045
1046                 case CPDMA_TX_STATS:
1047                         p = (u8 *)&tx_stats +
1048                                 cpsw_gstrings_stats[i].stat_offset;
1049                         data[i] = *(u32 *)p;
1050                         break;
1051                 }
1052         }
1053 }
1054
1055 static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
1056 {
1057         u32 i;
1058         u32 usage_count = 0;
1059
1060         if (!priv->data.dual_emac)
1061                 return 0;
1062
1063         for (i = 0; i < priv->data.slaves; i++)
1064                 if (priv->slaves[i].open_stat)
1065                         usage_count++;
1066
1067         return usage_count;
1068 }
1069
1070 static inline int cpsw_tx_packet_submit(struct net_device *ndev,
1071                         struct cpsw_priv *priv, struct sk_buff *skb)
1072 {
1073         if (!priv->data.dual_emac)
1074                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1075                                   skb->len, 0);
1076
1077         if (ndev == cpsw_get_slave_ndev(priv, 0))
1078                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1079                                   skb->len, 1);
1080         else
1081                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1082                                   skb->len, 2);
1083 }
1084
1085 static inline void cpsw_add_dual_emac_def_ale_entries(
1086                 struct cpsw_priv *priv, struct cpsw_slave *slave,
1087                 u32 slave_port)
1088 {
1089         u32 port_mask = 1 << slave_port | ALE_PORT_HOST;
1090
1091         if (priv->version == CPSW_VERSION_1)
1092                 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1093         else
1094                 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1095         cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
1096                           port_mask, port_mask, 0);
1097         cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1098                            port_mask, ALE_VLAN, slave->port_vlan, 0);
1099         cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1100                 HOST_PORT_NUM, ALE_VLAN | ALE_SECURE, slave->port_vlan);
1101 }
1102
1103 static void soft_reset_slave(struct cpsw_slave *slave)
1104 {
1105         char name[32];
1106
1107         snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1108         soft_reset(name, &slave->sliver->soft_reset);
1109 }
1110
1111 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1112 {
1113         u32 slave_port;
1114
1115         soft_reset_slave(slave);
1116
1117         /* setup priority mapping */
1118         __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1119
1120         switch (priv->version) {
1121         case CPSW_VERSION_1:
1122                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1123                 break;
1124         case CPSW_VERSION_2:
1125         case CPSW_VERSION_3:
1126         case CPSW_VERSION_4:
1127                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1128                 break;
1129         }
1130
1131         /* setup max packet size, and mac address */
1132         __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
1133         cpsw_set_slave_mac(slave, priv);
1134
1135         slave->mac_control = 0; /* no link yet */
1136
1137         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1138
1139         if (priv->data.dual_emac)
1140                 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1141         else
1142                 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1143                                    1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1144
1145         if (priv->phy_node)
1146                 slave->phy = of_phy_connect(priv->ndev, priv->phy_node,
1147                                  &cpsw_adjust_link, 0, slave->data->phy_if);
1148         else
1149                 slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
1150                                  &cpsw_adjust_link, slave->data->phy_if);
1151         if (IS_ERR(slave->phy)) {
1152                 dev_err(priv->dev, "phy %s not found on slave %d\n",
1153                         slave->data->phy_id, slave->slave_num);
1154                 slave->phy = NULL;
1155         } else {
1156                 phy_attached_info(slave->phy);
1157
1158                 phy_start(slave->phy);
1159
1160                 /* Configure GMII_SEL register */
1161                 cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface,
1162                              slave->slave_num);
1163         }
1164 }
1165
1166 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1167 {
1168         const int vlan = priv->data.default_vlan;
1169         u32 reg;
1170         int i;
1171         int unreg_mcast_mask;
1172
1173         reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1174                CPSW2_PORT_VLAN;
1175
1176         writel(vlan, &priv->host_port_regs->port_vlan);
1177
1178         for (i = 0; i < priv->data.slaves; i++)
1179                 slave_write(priv->slaves + i, vlan, reg);
1180
1181         if (priv->ndev->flags & IFF_ALLMULTI)
1182                 unreg_mcast_mask = ALE_ALL_PORTS;
1183         else
1184                 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1185
1186         cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS,
1187                           ALE_ALL_PORTS, ALE_ALL_PORTS,
1188                           unreg_mcast_mask);
1189 }
1190
1191 static void cpsw_init_host_port(struct cpsw_priv *priv)
1192 {
1193         u32 control_reg;
1194         u32 fifo_mode;
1195
1196         /* soft reset the controller and initialize ale */
1197         soft_reset("cpsw", &priv->regs->soft_reset);
1198         cpsw_ale_start(priv->ale);
1199
1200         /* switch to vlan unaware mode */
1201         cpsw_ale_control_set(priv->ale, HOST_PORT_NUM, ALE_VLAN_AWARE,
1202                              CPSW_ALE_VLAN_AWARE);
1203         control_reg = readl(&priv->regs->control);
1204         control_reg |= CPSW_VLAN_AWARE;
1205         writel(control_reg, &priv->regs->control);
1206         fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1207                      CPSW_FIFO_NORMAL_MODE;
1208         writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
1209
1210         /* setup host port priority mapping */
1211         __raw_writel(CPDMA_TX_PRIORITY_MAP,
1212                      &priv->host_port_regs->cpdma_tx_pri_map);
1213         __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
1214
1215         cpsw_ale_control_set(priv->ale, HOST_PORT_NUM,
1216                              ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1217
1218         if (!priv->data.dual_emac) {
1219                 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, HOST_PORT_NUM,
1220                                    0, 0);
1221                 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1222                                    ALE_PORT_HOST, 0, 0, ALE_MCAST_FWD_2);
1223         }
1224 }
1225
1226 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
1227 {
1228         u32 slave_port;
1229
1230         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1231
1232         if (!slave->phy)
1233                 return;
1234         phy_stop(slave->phy);
1235         phy_disconnect(slave->phy);
1236         slave->phy = NULL;
1237         cpsw_ale_control_set(priv->ale, slave_port,
1238                              ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1239 }
1240
1241 static int cpsw_ndo_open(struct net_device *ndev)
1242 {
1243         struct cpsw_priv *priv = netdev_priv(ndev);
1244         int i, ret;
1245         u32 reg;
1246
1247         pm_runtime_get_sync(&priv->pdev->dev);
1248
1249         if (!cpsw_common_res_usage_state(priv))
1250                 cpsw_intr_disable(priv);
1251         netif_carrier_off(ndev);
1252
1253         reg = priv->version;
1254
1255         dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1256                  CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1257                  CPSW_RTL_VERSION(reg));
1258
1259         /* initialize host and slave ports */
1260         if (!cpsw_common_res_usage_state(priv))
1261                 cpsw_init_host_port(priv);
1262         for_each_slave(priv, cpsw_slave_open, priv);
1263
1264         /* Add default VLAN */
1265         if (!priv->data.dual_emac)
1266                 cpsw_add_default_vlan(priv);
1267         else
1268                 cpsw_ale_add_vlan(priv->ale, priv->data.default_vlan,
1269                                   ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0);
1270
1271         if (!cpsw_common_res_usage_state(priv)) {
1272                 struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0);
1273
1274                 /* setup tx dma to fixed prio and zero offset */
1275                 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
1276                 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
1277
1278                 /* disable priority elevation */
1279                 __raw_writel(0, &priv->regs->ptype);
1280
1281                 /* enable statistics collection only on all ports */
1282                 __raw_writel(0x7, &priv->regs->stat_port_en);
1283
1284                 /* Enable internal fifo flow control */
1285                 writel(0x7, &priv->regs->flow_control);
1286
1287                 napi_enable(&priv_sl0->napi_rx);
1288                 napi_enable(&priv_sl0->napi_tx);
1289
1290                 if (priv_sl0->tx_irq_disabled) {
1291                         priv_sl0->tx_irq_disabled = false;
1292                         enable_irq(priv->irqs_table[1]);
1293                 }
1294
1295                 if (priv_sl0->rx_irq_disabled) {
1296                         priv_sl0->rx_irq_disabled = false;
1297                         enable_irq(priv->irqs_table[0]);
1298                 }
1299
1300                 if (WARN_ON(!priv->data.rx_descs))
1301                         priv->data.rx_descs = 128;
1302
1303                 for (i = 0; i < priv->data.rx_descs; i++) {
1304                         struct sk_buff *skb;
1305
1306                         ret = -ENOMEM;
1307                         skb = __netdev_alloc_skb_ip_align(priv->ndev,
1308                                         priv->rx_packet_max, GFP_KERNEL);
1309                         if (!skb)
1310                                 goto err_cleanup;
1311                         ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
1312                                         skb_tailroom(skb), 0);
1313                         if (ret < 0) {
1314                                 kfree_skb(skb);
1315                                 goto err_cleanup;
1316                         }
1317                 }
1318                 /* continue even if we didn't manage to submit all
1319                  * receive descs
1320                  */
1321                 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
1322
1323                 if (cpts_register(&priv->pdev->dev, priv->cpts,
1324                                   priv->data.cpts_clock_mult,
1325                                   priv->data.cpts_clock_shift))
1326                         dev_err(priv->dev, "error registering cpts device\n");
1327
1328         }
1329
1330         /* Enable Interrupt pacing if configured */
1331         if (priv->coal_intvl != 0) {
1332                 struct ethtool_coalesce coal;
1333
1334                 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1335                 cpsw_set_coalesce(ndev, &coal);
1336         }
1337
1338         cpdma_ctlr_start(priv->dma);
1339         cpsw_intr_enable(priv);
1340
1341         if (priv->data.dual_emac)
1342                 priv->slaves[priv->emac_port].open_stat = true;
1343         return 0;
1344
1345 err_cleanup:
1346         cpdma_ctlr_stop(priv->dma);
1347         for_each_slave(priv, cpsw_slave_stop, priv);
1348         pm_runtime_put_sync(&priv->pdev->dev);
1349         netif_carrier_off(priv->ndev);
1350         return ret;
1351 }
1352
1353 static int cpsw_ndo_stop(struct net_device *ndev)
1354 {
1355         struct cpsw_priv *priv = netdev_priv(ndev);
1356
1357         cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1358         netif_stop_queue(priv->ndev);
1359         netif_carrier_off(priv->ndev);
1360
1361         if (cpsw_common_res_usage_state(priv) <= 1) {
1362                 struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0);
1363
1364                 napi_disable(&priv_sl0->napi_rx);
1365                 napi_disable(&priv_sl0->napi_tx);
1366                 cpts_unregister(priv->cpts);
1367                 cpsw_intr_disable(priv);
1368                 cpdma_ctlr_stop(priv->dma);
1369                 cpsw_ale_stop(priv->ale);
1370         }
1371         for_each_slave(priv, cpsw_slave_stop, priv);
1372         pm_runtime_put_sync(&priv->pdev->dev);
1373         if (priv->data.dual_emac)
1374                 priv->slaves[priv->emac_port].open_stat = false;
1375         return 0;
1376 }
1377
1378 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1379                                        struct net_device *ndev)
1380 {
1381         struct cpsw_priv *priv = netdev_priv(ndev);
1382         int ret;
1383
1384         ndev->trans_start = jiffies;
1385
1386         if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1387                 cpsw_err(priv, tx_err, "packet pad failed\n");
1388                 ndev->stats.tx_dropped++;
1389                 return NETDEV_TX_OK;
1390         }
1391
1392         if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1393                                 priv->cpts->tx_enable)
1394                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1395
1396         skb_tx_timestamp(skb);
1397
1398         ret = cpsw_tx_packet_submit(ndev, priv, skb);
1399         if (unlikely(ret != 0)) {
1400                 cpsw_err(priv, tx_err, "desc submit failed\n");
1401                 goto fail;
1402         }
1403
1404         /* If there is no more tx desc left free then we need to
1405          * tell the kernel to stop sending us tx frames.
1406          */
1407         if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
1408                 netif_stop_queue(ndev);
1409
1410         return NETDEV_TX_OK;
1411 fail:
1412         ndev->stats.tx_dropped++;
1413         netif_stop_queue(ndev);
1414         return NETDEV_TX_BUSY;
1415 }
1416
1417 #ifdef CONFIG_TI_CPTS
1418
1419 static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1420 {
1421         struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
1422         u32 ts_en, seq_id;
1423
1424         if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
1425                 slave_write(slave, 0, CPSW1_TS_CTL);
1426                 return;
1427         }
1428
1429         seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1430         ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1431
1432         if (priv->cpts->tx_enable)
1433                 ts_en |= CPSW_V1_TS_TX_EN;
1434
1435         if (priv->cpts->rx_enable)
1436                 ts_en |= CPSW_V1_TS_RX_EN;
1437
1438         slave_write(slave, ts_en, CPSW1_TS_CTL);
1439         slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1440 }
1441
1442 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1443 {
1444         struct cpsw_slave *slave;
1445         u32 ctrl, mtype;
1446
1447         if (priv->data.dual_emac)
1448                 slave = &priv->slaves[priv->emac_port];
1449         else
1450                 slave = &priv->slaves[priv->data.active_slave];
1451
1452         ctrl = slave_read(slave, CPSW2_CONTROL);
1453         switch (priv->version) {
1454         case CPSW_VERSION_2:
1455                 ctrl &= ~CTRL_V2_ALL_TS_MASK;
1456
1457                 if (priv->cpts->tx_enable)
1458                         ctrl |= CTRL_V2_TX_TS_BITS;
1459
1460                 if (priv->cpts->rx_enable)
1461                         ctrl |= CTRL_V2_RX_TS_BITS;
1462                 break;
1463         case CPSW_VERSION_3:
1464         default:
1465                 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1466
1467                 if (priv->cpts->tx_enable)
1468                         ctrl |= CTRL_V3_TX_TS_BITS;
1469
1470                 if (priv->cpts->rx_enable)
1471                         ctrl |= CTRL_V3_RX_TS_BITS;
1472                 break;
1473         }
1474
1475         mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1476
1477         slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1478         slave_write(slave, ctrl, CPSW2_CONTROL);
1479         __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
1480 }
1481
1482 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1483 {
1484         struct cpsw_priv *priv = netdev_priv(dev);
1485         struct cpts *cpts = priv->cpts;
1486         struct hwtstamp_config cfg;
1487
1488         if (priv->version != CPSW_VERSION_1 &&
1489             priv->version != CPSW_VERSION_2 &&
1490             priv->version != CPSW_VERSION_3)
1491                 return -EOPNOTSUPP;
1492
1493         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1494                 return -EFAULT;
1495
1496         /* reserved for future extensions */
1497         if (cfg.flags)
1498                 return -EINVAL;
1499
1500         if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
1501                 return -ERANGE;
1502
1503         switch (cfg.rx_filter) {
1504         case HWTSTAMP_FILTER_NONE:
1505                 cpts->rx_enable = 0;
1506                 break;
1507         case HWTSTAMP_FILTER_ALL:
1508         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1509         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1510         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1511                 return -ERANGE;
1512         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1513         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1514         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1515         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1516         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1517         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1518         case HWTSTAMP_FILTER_PTP_V2_EVENT:
1519         case HWTSTAMP_FILTER_PTP_V2_SYNC:
1520         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1521                 cpts->rx_enable = 1;
1522                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1523                 break;
1524         default:
1525                 return -ERANGE;
1526         }
1527
1528         cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;
1529
1530         switch (priv->version) {
1531         case CPSW_VERSION_1:
1532                 cpsw_hwtstamp_v1(priv);
1533                 break;
1534         case CPSW_VERSION_2:
1535         case CPSW_VERSION_3:
1536                 cpsw_hwtstamp_v2(priv);
1537                 break;
1538         default:
1539                 WARN_ON(1);
1540         }
1541
1542         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1543 }
1544
1545 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1546 {
1547         struct cpsw_priv *priv = netdev_priv(dev);
1548         struct cpts *cpts = priv->cpts;
1549         struct hwtstamp_config cfg;
1550
1551         if (priv->version != CPSW_VERSION_1 &&
1552             priv->version != CPSW_VERSION_2 &&
1553             priv->version != CPSW_VERSION_3)
1554                 return -EOPNOTSUPP;
1555
1556         cfg.flags = 0;
1557         cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1558         cfg.rx_filter = (cpts->rx_enable ?
1559                          HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1560
1561         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1562 }
1563
1564 #endif /*CONFIG_TI_CPTS*/
1565
1566 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1567 {
1568         struct cpsw_priv *priv = netdev_priv(dev);
1569         int slave_no = cpsw_slave_index(priv);
1570
1571         if (!netif_running(dev))
1572                 return -EINVAL;
1573
1574         switch (cmd) {
1575 #ifdef CONFIG_TI_CPTS
1576         case SIOCSHWTSTAMP:
1577                 return cpsw_hwtstamp_set(dev, req);
1578         case SIOCGHWTSTAMP:
1579                 return cpsw_hwtstamp_get(dev, req);
1580 #endif
1581         }
1582
1583         if (!priv->slaves[slave_no].phy)
1584                 return -EOPNOTSUPP;
1585         return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd);
1586 }
1587
1588 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1589 {
1590         struct cpsw_priv *priv = netdev_priv(ndev);
1591
1592         cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1593         ndev->stats.tx_errors++;
1594         cpsw_intr_disable(priv);
1595         cpdma_chan_stop(priv->txch);
1596         cpdma_chan_start(priv->txch);
1597         cpsw_intr_enable(priv);
1598 }
1599
1600 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1601 {
1602         struct cpsw_priv *priv = netdev_priv(ndev);
1603         struct sockaddr *addr = (struct sockaddr *)p;
1604         int flags = 0;
1605         u16 vid = 0;
1606
1607         if (!is_valid_ether_addr(addr->sa_data))
1608                 return -EADDRNOTAVAIL;
1609
1610         if (priv->data.dual_emac) {
1611                 vid = priv->slaves[priv->emac_port].port_vlan;
1612                 flags = ALE_VLAN;
1613         }
1614
1615         cpsw_ale_del_ucast(priv->ale, priv->mac_addr, HOST_PORT_NUM,
1616                            flags, vid);
1617         cpsw_ale_add_ucast(priv->ale, addr->sa_data, HOST_PORT_NUM,
1618                            flags, vid);
1619
1620         memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1621         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1622         for_each_slave(priv, cpsw_set_slave_mac, priv);
1623
1624         return 0;
1625 }
1626
1627 #ifdef CONFIG_NET_POLL_CONTROLLER
1628 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1629 {
1630         struct cpsw_priv *priv = netdev_priv(ndev);
1631
1632         cpsw_intr_disable(priv);
1633         cpsw_rx_interrupt(priv->irqs_table[0], priv);
1634         cpsw_tx_interrupt(priv->irqs_table[1], priv);
1635         cpsw_intr_enable(priv);
1636 }
1637 #endif
1638
1639 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1640                                 unsigned short vid)
1641 {
1642         int ret;
1643         int unreg_mcast_mask = 0;
1644         u32 port_mask;
1645
1646         if (priv->data.dual_emac) {
1647                 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
1648
1649                 if (priv->ndev->flags & IFF_ALLMULTI)
1650                         unreg_mcast_mask = port_mask;
1651         } else {
1652                 port_mask = ALE_ALL_PORTS;
1653
1654                 if (priv->ndev->flags & IFF_ALLMULTI)
1655                         unreg_mcast_mask = ALE_ALL_PORTS;
1656                 else
1657                         unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1658         }
1659
1660         ret = cpsw_ale_add_vlan(priv->ale, vid, port_mask, 0, port_mask,
1661                                 unreg_mcast_mask);
1662         if (ret != 0)
1663                 return ret;
1664
1665         ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1666                                  HOST_PORT_NUM, ALE_VLAN, vid);
1667         if (ret != 0)
1668                 goto clean_vid;
1669
1670         ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1671                                  port_mask, ALE_VLAN, vid, 0);
1672         if (ret != 0)
1673                 goto clean_vlan_ucast;
1674         return 0;
1675
1676 clean_vlan_ucast:
1677         cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1678                            HOST_PORT_NUM, ALE_VLAN, vid);
1679 clean_vid:
1680         cpsw_ale_del_vlan(priv->ale, vid, 0);
1681         return ret;
1682 }
1683
1684 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1685                                     __be16 proto, u16 vid)
1686 {
1687         struct cpsw_priv *priv = netdev_priv(ndev);
1688
1689         if (vid == priv->data.default_vlan)
1690                 return 0;
1691
1692         if (priv->data.dual_emac) {
1693                 /* In dual EMAC, reserved VLAN id should not be used for
1694                  * creating VLAN interfaces as this can break the dual
1695                  * EMAC port separation
1696                  */
1697                 int i;
1698
1699                 for (i = 0; i < priv->data.slaves; i++) {
1700                         if (vid == priv->slaves[i].port_vlan)
1701                                 return -EINVAL;
1702                 }
1703         }
1704
1705         dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1706         return cpsw_add_vlan_ale_entry(priv, vid);
1707 }
1708
1709 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1710                                      __be16 proto, u16 vid)
1711 {
1712         struct cpsw_priv *priv = netdev_priv(ndev);
1713         int ret;
1714
1715         if (vid == priv->data.default_vlan)
1716                 return 0;
1717
1718         if (priv->data.dual_emac) {
1719                 int i;
1720
1721                 for (i = 0; i < priv->data.slaves; i++) {
1722                         if (vid == priv->slaves[i].port_vlan)
1723                                 return -EINVAL;
1724                 }
1725         }
1726
1727         dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1728         ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1729         if (ret != 0)
1730                 return ret;
1731
1732         ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1733                                  HOST_PORT_NUM, ALE_VLAN, vid);
1734         if (ret != 0)
1735                 return ret;
1736
1737         return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1738                                   0, ALE_VLAN, vid);
1739 }
1740
1741 static const struct net_device_ops cpsw_netdev_ops = {
1742         .ndo_open               = cpsw_ndo_open,
1743         .ndo_stop               = cpsw_ndo_stop,
1744         .ndo_start_xmit         = cpsw_ndo_start_xmit,
1745         .ndo_set_mac_address    = cpsw_ndo_set_mac_address,
1746         .ndo_do_ioctl           = cpsw_ndo_ioctl,
1747         .ndo_validate_addr      = eth_validate_addr,
1748         .ndo_change_mtu         = eth_change_mtu,
1749         .ndo_tx_timeout         = cpsw_ndo_tx_timeout,
1750         .ndo_set_rx_mode        = cpsw_ndo_set_rx_mode,
1751 #ifdef CONFIG_NET_POLL_CONTROLLER
1752         .ndo_poll_controller    = cpsw_ndo_poll_controller,
1753 #endif
1754         .ndo_vlan_rx_add_vid    = cpsw_ndo_vlan_rx_add_vid,
1755         .ndo_vlan_rx_kill_vid   = cpsw_ndo_vlan_rx_kill_vid,
1756 };
1757
1758 static int cpsw_get_regs_len(struct net_device *ndev)
1759 {
1760         struct cpsw_priv *priv = netdev_priv(ndev);
1761
1762         return priv->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
1763 }
1764
1765 static void cpsw_get_regs(struct net_device *ndev,
1766                           struct ethtool_regs *regs, void *p)
1767 {
1768         struct cpsw_priv *priv = netdev_priv(ndev);
1769         u32 *reg = p;
1770
1771         /* update CPSW IP version */
1772         regs->version = priv->version;
1773
1774         cpsw_ale_dump(priv->ale, reg);
1775 }
1776
1777 static void cpsw_get_drvinfo(struct net_device *ndev,
1778                              struct ethtool_drvinfo *info)
1779 {
1780         struct cpsw_priv *priv = netdev_priv(ndev);
1781
1782         strlcpy(info->driver, "cpsw", sizeof(info->driver));
1783         strlcpy(info->version, "1.0", sizeof(info->version));
1784         strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
1785 }
1786
1787 static u32 cpsw_get_msglevel(struct net_device *ndev)
1788 {
1789         struct cpsw_priv *priv = netdev_priv(ndev);
1790         return priv->msg_enable;
1791 }
1792
1793 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1794 {
1795         struct cpsw_priv *priv = netdev_priv(ndev);
1796         priv->msg_enable = value;
1797 }
1798
1799 static int cpsw_get_ts_info(struct net_device *ndev,
1800                             struct ethtool_ts_info *info)
1801 {
1802 #ifdef CONFIG_TI_CPTS
1803         struct cpsw_priv *priv = netdev_priv(ndev);
1804
1805         info->so_timestamping =
1806                 SOF_TIMESTAMPING_TX_HARDWARE |
1807                 SOF_TIMESTAMPING_TX_SOFTWARE |
1808                 SOF_TIMESTAMPING_RX_HARDWARE |
1809                 SOF_TIMESTAMPING_RX_SOFTWARE |
1810                 SOF_TIMESTAMPING_SOFTWARE |
1811                 SOF_TIMESTAMPING_RAW_HARDWARE;
1812         info->phc_index = priv->cpts->phc_index;
1813         info->tx_types =
1814                 (1 << HWTSTAMP_TX_OFF) |
1815                 (1 << HWTSTAMP_TX_ON);
1816         info->rx_filters =
1817                 (1 << HWTSTAMP_FILTER_NONE) |
1818                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1819 #else
1820         info->so_timestamping =
1821                 SOF_TIMESTAMPING_TX_SOFTWARE |
1822                 SOF_TIMESTAMPING_RX_SOFTWARE |
1823                 SOF_TIMESTAMPING_SOFTWARE;
1824         info->phc_index = -1;
1825         info->tx_types = 0;
1826         info->rx_filters = 0;
1827 #endif
1828         return 0;
1829 }
1830
1831 static int cpsw_get_settings(struct net_device *ndev,
1832                              struct ethtool_cmd *ecmd)
1833 {
1834         struct cpsw_priv *priv = netdev_priv(ndev);
1835         int slave_no = cpsw_slave_index(priv);
1836
1837         if (priv->slaves[slave_no].phy)
1838                 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1839         else
1840                 return -EOPNOTSUPP;
1841 }
1842
1843 static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1844 {
1845         struct cpsw_priv *priv = netdev_priv(ndev);
1846         int slave_no = cpsw_slave_index(priv);
1847
1848         if (priv->slaves[slave_no].phy)
1849                 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1850         else
1851                 return -EOPNOTSUPP;
1852 }
1853
1854 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1855 {
1856         struct cpsw_priv *priv = netdev_priv(ndev);
1857         int slave_no = cpsw_slave_index(priv);
1858
1859         wol->supported = 0;
1860         wol->wolopts = 0;
1861
1862         if (priv->slaves[slave_no].phy)
1863                 phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol);
1864 }
1865
1866 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1867 {
1868         struct cpsw_priv *priv = netdev_priv(ndev);
1869         int slave_no = cpsw_slave_index(priv);
1870
1871         if (priv->slaves[slave_no].phy)
1872                 return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol);
1873         else
1874                 return -EOPNOTSUPP;
1875 }
1876
1877 static void cpsw_get_pauseparam(struct net_device *ndev,
1878                                 struct ethtool_pauseparam *pause)
1879 {
1880         struct cpsw_priv *priv = netdev_priv(ndev);
1881
1882         pause->autoneg = AUTONEG_DISABLE;
1883         pause->rx_pause = priv->rx_pause ? true : false;
1884         pause->tx_pause = priv->tx_pause ? true : false;
1885 }
1886
1887 static int cpsw_set_pauseparam(struct net_device *ndev,
1888                                struct ethtool_pauseparam *pause)
1889 {
1890         struct cpsw_priv *priv = netdev_priv(ndev);
1891         bool link;
1892
1893         priv->rx_pause = pause->rx_pause ? true : false;
1894         priv->tx_pause = pause->tx_pause ? true : false;
1895
1896         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1897
1898         return 0;
1899 }
1900
1901 static const struct ethtool_ops cpsw_ethtool_ops = {
1902         .get_drvinfo    = cpsw_get_drvinfo,
1903         .get_msglevel   = cpsw_get_msglevel,
1904         .set_msglevel   = cpsw_set_msglevel,
1905         .get_link       = ethtool_op_get_link,
1906         .get_ts_info    = cpsw_get_ts_info,
1907         .get_settings   = cpsw_get_settings,
1908         .set_settings   = cpsw_set_settings,
1909         .get_coalesce   = cpsw_get_coalesce,
1910         .set_coalesce   = cpsw_set_coalesce,
1911         .get_sset_count         = cpsw_get_sset_count,
1912         .get_strings            = cpsw_get_strings,
1913         .get_ethtool_stats      = cpsw_get_ethtool_stats,
1914         .get_pauseparam         = cpsw_get_pauseparam,
1915         .set_pauseparam         = cpsw_set_pauseparam,
1916         .get_wol        = cpsw_get_wol,
1917         .set_wol        = cpsw_set_wol,
1918         .get_regs_len   = cpsw_get_regs_len,
1919         .get_regs       = cpsw_get_regs,
1920 };
1921
1922 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1923                             u32 slave_reg_ofs, u32 sliver_reg_ofs)
1924 {
1925         void __iomem            *regs = priv->regs;
1926         int                     slave_num = slave->slave_num;
1927         struct cpsw_slave_data  *data = priv->data.slave_data + slave_num;
1928
1929         slave->data     = data;
1930         slave->regs     = regs + slave_reg_ofs;
1931         slave->sliver   = regs + sliver_reg_ofs;
1932         slave->port_vlan = data->dual_emac_res_vlan;
1933 }
1934
1935 static int cpsw_probe_dt(struct cpsw_priv *priv,
1936                          struct platform_device *pdev)
1937 {
1938         struct device_node *node = pdev->dev.of_node;
1939         struct device_node *slave_node;
1940         struct cpsw_platform_data *data = &priv->data;
1941         int i = 0, ret;
1942         u32 prop;
1943
1944         if (!node)
1945                 return -EINVAL;
1946
1947         if (of_property_read_u32(node, "slaves", &prop)) {
1948                 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
1949                 return -EINVAL;
1950         }
1951         data->slaves = prop;
1952
1953         if (of_property_read_u32(node, "active_slave", &prop)) {
1954                 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
1955                 return -EINVAL;
1956         }
1957         data->active_slave = prop;
1958
1959         if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
1960                 dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n");
1961                 return -EINVAL;
1962         }
1963         data->cpts_clock_mult = prop;
1964
1965         if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
1966                 dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n");
1967                 return -EINVAL;
1968         }
1969         data->cpts_clock_shift = prop;
1970
1971         data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
1972                                         * sizeof(struct cpsw_slave_data),
1973                                         GFP_KERNEL);
1974         if (!data->slave_data)
1975                 return -ENOMEM;
1976
1977         if (of_property_read_u32(node, "cpdma_channels", &prop)) {
1978                 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
1979                 return -EINVAL;
1980         }
1981         data->channels = prop;
1982
1983         if (of_property_read_u32(node, "ale_entries", &prop)) {
1984                 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
1985                 return -EINVAL;
1986         }
1987         data->ale_entries = prop;
1988
1989         if (of_property_read_u32(node, "bd_ram_size", &prop)) {
1990                 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
1991                 return -EINVAL;
1992         }
1993         data->bd_ram_size = prop;
1994
1995         if (of_property_read_u32(node, "rx_descs", &prop)) {
1996                 dev_err(&pdev->dev, "Missing rx_descs property in the DT.\n");
1997                 return -EINVAL;
1998         }
1999         data->rx_descs = prop;
2000
2001         if (of_property_read_u32(node, "mac_control", &prop)) {
2002                 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
2003                 return -EINVAL;
2004         }
2005         data->mac_control = prop;
2006
2007         if (of_property_read_bool(node, "dual_emac"))
2008                 data->dual_emac = 1;
2009
2010         /*
2011          * Populate all the child nodes here...
2012          */
2013         ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2014         /* We do not want to force this, as in some cases may not have child */
2015         if (ret)
2016                 dev_warn(&pdev->dev, "Doesn't have any child node\n");
2017
2018         for_each_child_of_node(node, slave_node) {
2019                 struct cpsw_slave_data *slave_data = data->slave_data + i;
2020                 const void *mac_addr = NULL;
2021                 int lenp;
2022                 const __be32 *parp;
2023
2024                 /* This is no slave child node, continue */
2025                 if (strcmp(slave_node->name, "slave"))
2026                         continue;
2027
2028                 priv->phy_node = of_parse_phandle(slave_node, "phy-handle", 0);
2029                 parp = of_get_property(slave_node, "phy_id", &lenp);
2030                 if (of_phy_is_fixed_link(slave_node)) {
2031                         struct device_node *phy_node;
2032                         struct phy_device *phy_dev;
2033
2034                         /* In the case of a fixed PHY, the DT node associated
2035                          * to the PHY is the Ethernet MAC DT node.
2036                          */
2037                         ret = of_phy_register_fixed_link(slave_node);
2038                         if (ret)
2039                                 return ret;
2040                         phy_node = of_node_get(slave_node);
2041                         phy_dev = of_phy_find_device(phy_node);
2042                         if (!phy_dev)
2043                                 return -ENODEV;
2044                         snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2045                                  PHY_ID_FMT, phy_dev->mdio.bus->id,
2046                                  phy_dev->mdio.addr);
2047                 } else if (parp) {
2048                         u32 phyid;
2049                         struct device_node *mdio_node;
2050                         struct platform_device *mdio;
2051
2052                         if (lenp != (sizeof(__be32) * 2)) {
2053                                 dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i);
2054                                 goto no_phy_slave;
2055                         }
2056                         mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2057                         phyid = be32_to_cpup(parp+1);
2058                         mdio = of_find_device_by_node(mdio_node);
2059                         of_node_put(mdio_node);
2060                         if (!mdio) {
2061                                 dev_err(&pdev->dev, "Missing mdio platform device\n");
2062                                 return -EINVAL;
2063                         }
2064                         snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2065                                  PHY_ID_FMT, mdio->name, phyid);
2066                 } else {
2067                         dev_err(&pdev->dev, "No slave[%d] phy_id or fixed-link property\n", i);
2068                         goto no_phy_slave;
2069                 }
2070                 slave_data->phy_if = of_get_phy_mode(slave_node);
2071                 if (slave_data->phy_if < 0) {
2072                         dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2073                                 i);
2074                         return slave_data->phy_if;
2075                 }
2076
2077 no_phy_slave:
2078                 mac_addr = of_get_mac_address(slave_node);
2079                 if (mac_addr) {
2080                         memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
2081                 } else {
2082                         ret = ti_cm_get_macid(&pdev->dev, i,
2083                                               slave_data->mac_addr);
2084                         if (ret)
2085                                 return ret;
2086                 }
2087                 if (data->dual_emac) {
2088                         if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
2089                                                  &prop)) {
2090                                 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
2091                                 slave_data->dual_emac_res_vlan = i+1;
2092                                 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2093                                         slave_data->dual_emac_res_vlan, i);
2094                         } else {
2095                                 slave_data->dual_emac_res_vlan = prop;
2096                         }
2097                 }
2098
2099                 i++;
2100                 if (i == data->slaves)
2101                         break;
2102         }
2103
2104         return 0;
2105 }
2106
2107 static int cpsw_probe_dual_emac(struct platform_device *pdev,
2108                                 struct cpsw_priv *priv)
2109 {
2110         struct cpsw_platform_data       *data = &priv->data;
2111         struct net_device               *ndev;
2112         struct cpsw_priv                *priv_sl2;
2113         int ret = 0, i;
2114
2115         ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2116         if (!ndev) {
2117                 dev_err(&pdev->dev, "cpsw: error allocating net_device\n");
2118                 return -ENOMEM;
2119         }
2120
2121         priv_sl2 = netdev_priv(ndev);
2122         spin_lock_init(&priv_sl2->lock);
2123         priv_sl2->data = *data;
2124         priv_sl2->pdev = pdev;
2125         priv_sl2->ndev = ndev;
2126         priv_sl2->dev  = &ndev->dev;
2127         priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2128         priv_sl2->rx_packet_max = max(rx_packet_max, 128);
2129
2130         if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2131                 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2132                         ETH_ALEN);
2133                 dev_info(&pdev->dev, "cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
2134         } else {
2135                 random_ether_addr(priv_sl2->mac_addr);
2136                 dev_info(&pdev->dev, "cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
2137         }
2138         memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2139
2140         priv_sl2->slaves = priv->slaves;
2141         priv_sl2->clk = priv->clk;
2142
2143         priv_sl2->coal_intvl = 0;
2144         priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
2145
2146         priv_sl2->regs = priv->regs;
2147         priv_sl2->host_port_regs = priv->host_port_regs;
2148         priv_sl2->wr_regs = priv->wr_regs;
2149         priv_sl2->hw_stats = priv->hw_stats;
2150         priv_sl2->dma = priv->dma;
2151         priv_sl2->txch = priv->txch;
2152         priv_sl2->rxch = priv->rxch;
2153         priv_sl2->ale = priv->ale;
2154         priv_sl2->emac_port = 1;
2155         priv->slaves[1].ndev = ndev;
2156         priv_sl2->cpts = priv->cpts;
2157         priv_sl2->version = priv->version;
2158
2159         for (i = 0; i < priv->num_irqs; i++) {
2160                 priv_sl2->irqs_table[i] = priv->irqs_table[i];
2161                 priv_sl2->num_irqs = priv->num_irqs;
2162         }
2163         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2164
2165         ndev->netdev_ops = &cpsw_netdev_ops;
2166         ndev->ethtool_ops = &cpsw_ethtool_ops;
2167
2168         /* register the network device */
2169         SET_NETDEV_DEV(ndev, &pdev->dev);
2170         ret = register_netdev(ndev);
2171         if (ret) {
2172                 dev_err(&pdev->dev, "cpsw: error registering net device\n");
2173                 free_netdev(ndev);
2174                 ret = -ENODEV;
2175         }
2176
2177         return ret;
2178 }
2179
2180 #define CPSW_QUIRK_IRQ          BIT(0)
2181
2182 static struct platform_device_id cpsw_devtype[] = {
2183         {
2184                 /* keep it for existing comaptibles */
2185                 .name = "cpsw",
2186                 .driver_data = CPSW_QUIRK_IRQ,
2187         }, {
2188                 .name = "am335x-cpsw",
2189                 .driver_data = CPSW_QUIRK_IRQ,
2190         }, {
2191                 .name = "am4372-cpsw",
2192                 .driver_data = 0,
2193         }, {
2194                 .name = "dra7-cpsw",
2195                 .driver_data = 0,
2196         }, {
2197                 /* sentinel */
2198         }
2199 };
2200 MODULE_DEVICE_TABLE(platform, cpsw_devtype);
2201
2202 enum ti_cpsw_type {
2203         CPSW = 0,
2204         AM335X_CPSW,
2205         AM4372_CPSW,
2206         DRA7_CPSW,
2207 };
2208
2209 static const struct of_device_id cpsw_of_mtable[] = {
2210         { .compatible = "ti,cpsw", .data = &cpsw_devtype[CPSW], },
2211         { .compatible = "ti,am335x-cpsw", .data = &cpsw_devtype[AM335X_CPSW], },
2212         { .compatible = "ti,am4372-cpsw", .data = &cpsw_devtype[AM4372_CPSW], },
2213         { .compatible = "ti,dra7-cpsw", .data = &cpsw_devtype[DRA7_CPSW], },
2214         { /* sentinel */ },
2215 };
2216 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2217
2218 static int cpsw_probe(struct platform_device *pdev)
2219 {
2220         struct cpsw_platform_data       *data;
2221         struct net_device               *ndev;
2222         struct cpsw_priv                *priv;
2223         struct cpdma_params             dma_params;
2224         struct cpsw_ale_params          ale_params;
2225         void __iomem                    *ss_regs;
2226         struct resource                 *res, *ss_res;
2227         const struct of_device_id       *of_id;
2228         struct gpio_descs               *mode;
2229         u32 slave_offset, sliver_offset, slave_size;
2230         int ret = 0, i;
2231         int irq;
2232
2233         ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2234         if (!ndev) {
2235                 dev_err(&pdev->dev, "error allocating net_device\n");
2236                 return -ENOMEM;
2237         }
2238
2239         platform_set_drvdata(pdev, ndev);
2240         priv = netdev_priv(ndev);
2241         spin_lock_init(&priv->lock);
2242         priv->pdev = pdev;
2243         priv->ndev = ndev;
2244         priv->dev  = &ndev->dev;
2245         priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2246         priv->rx_packet_max = max(rx_packet_max, 128);
2247         priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
2248         if (!priv->cpts) {
2249                 dev_err(&pdev->dev, "error allocating cpts\n");
2250                 ret = -ENOMEM;
2251                 goto clean_ndev_ret;
2252         }
2253
2254         mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW);
2255         if (IS_ERR(mode)) {
2256                 ret = PTR_ERR(mode);
2257                 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
2258                 goto clean_ndev_ret;
2259         }
2260
2261         /*
2262          * This may be required here for child devices.
2263          */
2264         pm_runtime_enable(&pdev->dev);
2265
2266         /* Select default pin state */
2267         pinctrl_pm_select_default_state(&pdev->dev);
2268
2269         if (cpsw_probe_dt(priv, pdev)) {
2270                 dev_err(&pdev->dev, "cpsw: platform data missing\n");
2271                 ret = -ENODEV;
2272                 goto clean_runtime_disable_ret;
2273         }
2274         data = &priv->data;
2275
2276         if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2277                 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
2278                 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
2279         } else {
2280                 eth_random_addr(priv->mac_addr);
2281                 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
2282         }
2283
2284         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2285
2286         priv->slaves = devm_kzalloc(&pdev->dev,
2287                                     sizeof(struct cpsw_slave) * data->slaves,
2288                                     GFP_KERNEL);
2289         if (!priv->slaves) {
2290                 ret = -ENOMEM;
2291                 goto clean_runtime_disable_ret;
2292         }
2293         for (i = 0; i < data->slaves; i++)
2294                 priv->slaves[i].slave_num = i;
2295
2296         priv->slaves[0].ndev = ndev;
2297         priv->emac_port = 0;
2298
2299         priv->clk = devm_clk_get(&pdev->dev, "fck");
2300         if (IS_ERR(priv->clk)) {
2301                 dev_err(priv->dev, "fck is not found\n");
2302                 ret = -ENODEV;
2303                 goto clean_runtime_disable_ret;
2304         }
2305         priv->coal_intvl = 0;
2306         priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
2307
2308         ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2309         ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2310         if (IS_ERR(ss_regs)) {
2311                 ret = PTR_ERR(ss_regs);
2312                 goto clean_runtime_disable_ret;
2313         }
2314         priv->regs = ss_regs;
2315
2316         /* Need to enable clocks with runtime PM api to access module
2317          * registers
2318          */
2319         pm_runtime_get_sync(&pdev->dev);
2320         priv->version = readl(&priv->regs->id_ver);
2321         pm_runtime_put_sync(&pdev->dev);
2322
2323         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2324         priv->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2325         if (IS_ERR(priv->wr_regs)) {
2326                 ret = PTR_ERR(priv->wr_regs);
2327                 goto clean_runtime_disable_ret;
2328         }
2329
2330         memset(&dma_params, 0, sizeof(dma_params));
2331         memset(&ale_params, 0, sizeof(ale_params));
2332
2333         switch (priv->version) {
2334         case CPSW_VERSION_1:
2335                 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
2336                 priv->cpts->reg      = ss_regs + CPSW1_CPTS_OFFSET;
2337                 priv->hw_stats       = ss_regs + CPSW1_HW_STATS;
2338                 dma_params.dmaregs   = ss_regs + CPSW1_CPDMA_OFFSET;
2339                 dma_params.txhdp     = ss_regs + CPSW1_STATERAM_OFFSET;
2340                 ale_params.ale_regs  = ss_regs + CPSW1_ALE_OFFSET;
2341                 slave_offset         = CPSW1_SLAVE_OFFSET;
2342                 slave_size           = CPSW1_SLAVE_SIZE;
2343                 sliver_offset        = CPSW1_SLIVER_OFFSET;
2344                 dma_params.desc_mem_phys = 0;
2345                 break;
2346         case CPSW_VERSION_2:
2347         case CPSW_VERSION_3:
2348         case CPSW_VERSION_4:
2349                 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
2350                 priv->cpts->reg      = ss_regs + CPSW2_CPTS_OFFSET;
2351                 priv->hw_stats       = ss_regs + CPSW2_HW_STATS;
2352                 dma_params.dmaregs   = ss_regs + CPSW2_CPDMA_OFFSET;
2353                 dma_params.txhdp     = ss_regs + CPSW2_STATERAM_OFFSET;
2354                 ale_params.ale_regs  = ss_regs + CPSW2_ALE_OFFSET;
2355                 slave_offset         = CPSW2_SLAVE_OFFSET;
2356                 slave_size           = CPSW2_SLAVE_SIZE;
2357                 sliver_offset        = CPSW2_SLIVER_OFFSET;
2358                 dma_params.desc_mem_phys =
2359                         (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
2360                 break;
2361         default:
2362                 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
2363                 ret = -ENODEV;
2364                 goto clean_runtime_disable_ret;
2365         }
2366         for (i = 0; i < priv->data.slaves; i++) {
2367                 struct cpsw_slave *slave = &priv->slaves[i];
2368                 cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
2369                 slave_offset  += slave_size;
2370                 sliver_offset += SLIVER_SIZE;
2371         }
2372
2373         dma_params.dev          = &pdev->dev;
2374         dma_params.rxthresh     = dma_params.dmaregs + CPDMA_RXTHRESH;
2375         dma_params.rxfree       = dma_params.dmaregs + CPDMA_RXFREE;
2376         dma_params.rxhdp        = dma_params.txhdp + CPDMA_RXHDP;
2377         dma_params.txcp         = dma_params.txhdp + CPDMA_TXCP;
2378         dma_params.rxcp         = dma_params.txhdp + CPDMA_RXCP;
2379
2380         dma_params.num_chan             = data->channels;
2381         dma_params.has_soft_reset       = true;
2382         dma_params.min_packet_size      = CPSW_MIN_PACKET_SIZE;
2383         dma_params.desc_mem_size        = data->bd_ram_size;
2384         dma_params.desc_align           = 16;
2385         dma_params.has_ext_regs         = true;
2386         dma_params.desc_hw_addr         = dma_params.desc_mem_phys;
2387
2388         priv->dma = cpdma_ctlr_create(&dma_params);
2389         if (!priv->dma) {
2390                 dev_err(priv->dev, "error initializing dma\n");
2391                 ret = -ENOMEM;
2392                 goto clean_runtime_disable_ret;
2393         }
2394
2395         priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
2396                                        cpsw_tx_handler);
2397         priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
2398                                        cpsw_rx_handler);
2399
2400         if (WARN_ON(!priv->txch || !priv->rxch)) {
2401                 dev_err(priv->dev, "error initializing dma channels\n");
2402                 ret = -ENOMEM;
2403                 goto clean_dma_ret;
2404         }
2405
2406         ale_params.dev                  = &ndev->dev;
2407         ale_params.ale_ageout           = ale_ageout;
2408         ale_params.ale_entries          = data->ale_entries;
2409         ale_params.ale_ports            = data->slaves;
2410
2411         priv->ale = cpsw_ale_create(&ale_params);
2412         if (!priv->ale) {
2413                 dev_err(priv->dev, "error initializing ale engine\n");
2414                 ret = -ENODEV;
2415                 goto clean_dma_ret;
2416         }
2417
2418         ndev->irq = platform_get_irq(pdev, 1);
2419         if (ndev->irq < 0) {
2420                 dev_err(priv->dev, "error getting irq resource\n");
2421                 ret = ndev->irq;
2422                 goto clean_ale_ret;
2423         }
2424
2425         of_id = of_match_device(cpsw_of_mtable, &pdev->dev);
2426         if (of_id) {
2427                 pdev->id_entry = of_id->data;
2428                 if (pdev->id_entry->driver_data)
2429                         priv->quirk_irq = true;
2430         }
2431
2432         /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
2433          * MISC IRQs which are always kept disabled with this driver so
2434          * we will not request them.
2435          *
2436          * If anyone wants to implement support for those, make sure to
2437          * first request and append them to irqs_table array.
2438          */
2439
2440         /* RX IRQ */
2441         irq = platform_get_irq(pdev, 1);
2442         if (irq < 0) {
2443                 ret = irq;
2444                 goto clean_ale_ret;
2445         }
2446
2447         priv->irqs_table[0] = irq;
2448         ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
2449                                0, dev_name(&pdev->dev), priv);
2450         if (ret < 0) {
2451                 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2452                 goto clean_ale_ret;
2453         }
2454
2455         /* TX IRQ */
2456         irq = platform_get_irq(pdev, 2);
2457         if (irq < 0) {
2458                 ret = irq;
2459                 goto clean_ale_ret;
2460         }
2461
2462         priv->irqs_table[1] = irq;
2463         ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
2464                                0, dev_name(&pdev->dev), priv);
2465         if (ret < 0) {
2466                 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2467                 goto clean_ale_ret;
2468         }
2469         priv->num_irqs = 2;
2470
2471         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2472
2473         ndev->netdev_ops = &cpsw_netdev_ops;
2474         ndev->ethtool_ops = &cpsw_ethtool_ops;
2475         netif_napi_add(ndev, &priv->napi_rx, cpsw_rx_poll, CPSW_POLL_WEIGHT);
2476         netif_tx_napi_add(ndev, &priv->napi_tx, cpsw_tx_poll, CPSW_POLL_WEIGHT);
2477
2478         /* register the network device */
2479         SET_NETDEV_DEV(ndev, &pdev->dev);
2480         ret = register_netdev(ndev);
2481         if (ret) {
2482                 dev_err(priv->dev, "error registering net device\n");
2483                 ret = -ENODEV;
2484                 goto clean_ale_ret;
2485         }
2486
2487         cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
2488                     &ss_res->start, ndev->irq);
2489
2490         if (priv->data.dual_emac) {
2491                 ret = cpsw_probe_dual_emac(pdev, priv);
2492                 if (ret) {
2493                         cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
2494                         goto clean_ale_ret;
2495                 }
2496         }
2497
2498         return 0;
2499
2500 clean_ale_ret:
2501         cpsw_ale_destroy(priv->ale);
2502 clean_dma_ret:
2503         cpdma_chan_destroy(priv->txch);
2504         cpdma_chan_destroy(priv->rxch);
2505         cpdma_ctlr_destroy(priv->dma);
2506 clean_runtime_disable_ret:
2507         pm_runtime_disable(&pdev->dev);
2508 clean_ndev_ret:
2509         free_netdev(priv->ndev);
2510         return ret;
2511 }
2512
2513 static int cpsw_remove_child_device(struct device *dev, void *c)
2514 {
2515         struct platform_device *pdev = to_platform_device(dev);
2516
2517         of_device_unregister(pdev);
2518
2519         return 0;
2520 }
2521
2522 static int cpsw_remove(struct platform_device *pdev)
2523 {
2524         struct net_device *ndev = platform_get_drvdata(pdev);
2525         struct cpsw_priv *priv = netdev_priv(ndev);
2526
2527         if (priv->data.dual_emac)
2528                 unregister_netdev(cpsw_get_slave_ndev(priv, 1));
2529         unregister_netdev(ndev);
2530
2531         cpsw_ale_destroy(priv->ale);
2532         cpdma_chan_destroy(priv->txch);
2533         cpdma_chan_destroy(priv->rxch);
2534         cpdma_ctlr_destroy(priv->dma);
2535         pm_runtime_disable(&pdev->dev);
2536         device_for_each_child(&pdev->dev, NULL, cpsw_remove_child_device);
2537         if (priv->data.dual_emac)
2538                 free_netdev(cpsw_get_slave_ndev(priv, 1));
2539         free_netdev(ndev);
2540         return 0;
2541 }
2542
2543 #ifdef CONFIG_PM_SLEEP
2544 static int cpsw_suspend(struct device *dev)
2545 {
2546         struct platform_device  *pdev = to_platform_device(dev);
2547         struct net_device       *ndev = platform_get_drvdata(pdev);
2548         struct cpsw_priv        *priv = netdev_priv(ndev);
2549
2550         if (priv->data.dual_emac) {
2551                 int i;
2552
2553                 for (i = 0; i < priv->data.slaves; i++) {
2554                         if (netif_running(priv->slaves[i].ndev))
2555                                 cpsw_ndo_stop(priv->slaves[i].ndev);
2556                         soft_reset_slave(priv->slaves + i);
2557                 }
2558         } else {
2559                 if (netif_running(ndev))
2560                         cpsw_ndo_stop(ndev);
2561                 for_each_slave(priv, soft_reset_slave);
2562         }
2563
2564         pm_runtime_put_sync(&pdev->dev);
2565
2566         /* Select sleep pin state */
2567         pinctrl_pm_select_sleep_state(&pdev->dev);
2568
2569         return 0;
2570 }
2571
2572 static int cpsw_resume(struct device *dev)
2573 {
2574         struct platform_device  *pdev = to_platform_device(dev);
2575         struct net_device       *ndev = platform_get_drvdata(pdev);
2576         struct cpsw_priv        *priv = netdev_priv(ndev);
2577
2578         pm_runtime_get_sync(&pdev->dev);
2579
2580         /* Select default pin state */
2581         pinctrl_pm_select_default_state(&pdev->dev);
2582
2583         if (priv->data.dual_emac) {
2584                 int i;
2585
2586                 for (i = 0; i < priv->data.slaves; i++) {
2587                         if (netif_running(priv->slaves[i].ndev))
2588                                 cpsw_ndo_open(priv->slaves[i].ndev);
2589                 }
2590         } else {
2591                 if (netif_running(ndev))
2592                         cpsw_ndo_open(ndev);
2593         }
2594         return 0;
2595 }
2596 #endif
2597
2598 static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
2599
2600 static struct platform_driver cpsw_driver = {
2601         .driver = {
2602                 .name    = "cpsw",
2603                 .pm      = &cpsw_pm_ops,
2604                 .of_match_table = cpsw_of_mtable,
2605         },
2606         .probe = cpsw_probe,
2607         .remove = cpsw_remove,
2608 };
2609
2610 module_platform_driver(cpsw_driver);
2611
2612 MODULE_LICENSE("GPL");
2613 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2614 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2615 MODULE_DESCRIPTION("TI CPSW Ethernet driver");