drivers/net/ethernet/ti/cpsw.c

   1 /*
   2  * Texas Instruments Ethernet Switch Driver
   3  *
   4  * Copyright (C) 2012 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/io.h>
  18 #include <linux/clk.h>
  19 #include <linux/timer.h>
  20 #include <linux/module.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/irqreturn.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/if_ether.h>
  25 #include <linux/etherdevice.h>
  26 #include <linux/netdevice.h>
  27 #include <linux/net_tstamp.h>
  28 #include <linux/phy.h>
  29 #include <linux/workqueue.h>
  30 #include <linux/delay.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/gpio.h>
  33 #include <linux/of.h>
  34 #include <linux/of_mdio.h>
  35 #include <linux/of_net.h>
  36 #include <linux/of_device.h>
  37 #include <linux/if_vlan.h>
  38
  39 #include <linux/pinctrl/consumer.h>
  40
  41 #include "cpsw.h"
  42 #include "cpsw_ale.h"
  43 #include "cpts.h"
  44 #include "davinci_cpdma.h"
  45
  46 #define CPSW_DEBUG      (NETIF_MSG_HW           | NETIF_MSG_WOL         | \
  47                          NETIF_MSG_DRV          | NETIF_MSG_LINK        | \
  48                          NETIF_MSG_IFUP         | NETIF_MSG_INTR        | \
  49                          NETIF_MSG_PROBE        | NETIF_MSG_TIMER       | \
  50                          NETIF_MSG_IFDOWN       | NETIF_MSG_RX_ERR      | \
  51                          NETIF_MSG_TX_ERR       | NETIF_MSG_TX_DONE     | \
  52                          NETIF_MSG_PKTDATA      | NETIF_MSG_TX_QUEUED   | \
  53                          NETIF_MSG_RX_STATUS)
  54
  55 #define cpsw_info(priv, type, format, ...)              \
  56 do {                                                            \
  57         if (netif_msg_##type(priv) && net_ratelimit())          \
  58                 dev_info(priv->dev, format, ## __VA_ARGS__);    \
  59 } while (0)
  60
  61 #define cpsw_err(priv, type, format, ...)               \
  62 do {                                                            \
  63         if (netif_msg_##type(priv) && net_ratelimit())          \
  64                 dev_err(priv->dev, format, ## __VA_ARGS__);     \
  65 } while (0)
  66
  67 #define cpsw_dbg(priv, type, format, ...)               \
  68 do {                                                            \
  69         if (netif_msg_##type(priv) && net_ratelimit())          \
  70                 dev_dbg(priv->dev, format, ## __VA_ARGS__);     \
  71 } while (0)
  72
  73 #define cpsw_notice(priv, type, format, ...)            \
  74 do {                                                            \
  75         if (netif_msg_##type(priv) && net_ratelimit())          \
  76                 dev_notice(priv->dev, format, ## __VA_ARGS__);  \
  77 } while (0)
  78
  79 #define ALE_ALL_PORTS           0x7
  80
  81 #define CPSW_MAJOR_VERSION(reg)         (reg >> 8 & 0x7)
  82 #define CPSW_MINOR_VERSION(reg)         (reg & 0xff)
  83 #define CPSW_RTL_VERSION(reg)           ((reg >> 11) & 0x1f)
  84
  85 #define CPSW_VERSION_1          0x19010a
  86 #define CPSW_VERSION_2          0x19010c
  87 #define CPSW_VERSION_3          0x19010f
  88 #define CPSW_VERSION_4          0x190112
  89
  90 #define HOST_PORT_NUM           0
  91 #define SLIVER_SIZE             0x40
  92
  93 #define CPSW1_HOST_PORT_OFFSET  0x028
  94 #define CPSW1_SLAVE_OFFSET      0x050
  95 #define CPSW1_SLAVE_SIZE        0x040
  96 #define CPSW1_CPDMA_OFFSET      0x100
  97 #define CPSW1_STATERAM_OFFSET   0x200
  98 #define CPSW1_HW_STATS          0x400
  99 #define CPSW1_CPTS_OFFSET       0x500
 100 #define CPSW1_ALE_OFFSET        0x600
 101 #define CPSW1_SLIVER_OFFSET     0x700
 102
 103 #define CPSW2_HOST_PORT_OFFSET  0x108
 104 #define CPSW2_SLAVE_OFFSET      0x200
 105 #define CPSW2_SLAVE_SIZE        0x100
 106 #define CPSW2_CPDMA_OFFSET      0x800
 107 #define CPSW2_HW_STATS          0x900
 108 #define CPSW2_STATERAM_OFFSET   0xa00
 109 #define CPSW2_CPTS_OFFSET       0xc00
 110 #define CPSW2_ALE_OFFSET        0xd00
 111 #define CPSW2_SLIVER_OFFSET     0xd80
 112 #define CPSW2_BD_OFFSET         0x2000
 113
 114 #define CPDMA_RXTHRESH          0x0c0
 115 #define CPDMA_RXFREE            0x0e0
 116 #define CPDMA_TXHDP             0x00
 117 #define CPDMA_RXHDP             0x20
 118 #define CPDMA_TXCP              0x40
 119 #define CPDMA_RXCP              0x60
 120
 121 #define CPSW_POLL_WEIGHT        64
 122 #define CPSW_MIN_PACKET_SIZE    60
 123 #define CPSW_MAX_PACKET_SIZE    (1500 + 14 + 4 + 4)
 124
 125 #define RX_PRIORITY_MAPPING     0x76543210
 126 #define TX_PRIORITY_MAPPING     0x33221100
 127 #define CPDMA_TX_PRIORITY_MAP   0x01234567
 128
 129 #define CPSW_VLAN_AWARE         BIT(1)
 130 #define CPSW_ALE_VLAN_AWARE     1
 131
 132 #define CPSW_FIFO_NORMAL_MODE           (0 << 16)
 133 #define CPSW_FIFO_DUAL_MAC_MODE         (1 << 16)
 134 #define CPSW_FIFO_RATE_LIMIT_MODE       (2 << 16)
 135
 136 #define CPSW_INTPACEEN          (0x3f << 16)
 137 #define CPSW_INTPRESCALE_MASK   (0x7FF << 0)
 138 #define CPSW_CMINTMAX_CNT       63
 139 #define CPSW_CMINTMIN_CNT       2
 140 #define CPSW_CMINTMAX_INTVL     (1000 / CPSW_CMINTMIN_CNT)
 141 #define CPSW_CMINTMIN_INTVL     ((1000 / CPSW_CMINTMAX_CNT) + 1)
 142
 143 #define cpsw_slave_index(cpsw, priv)                            \
 144                 ((cpsw->data.dual_emac) ? priv->emac_port :     \
 145                 cpsw->data.active_slave)
 146 #define IRQ_NUM                 2
 147 #define CPSW_MAX_QUEUES         8
 148
 149 static int debug_level;
 150 module_param(debug_level, int, 0);
 151 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
 152
 153 static int ale_ageout = 10;
 154 module_param(ale_ageout, int, 0);
 155 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
 156
 157 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
 158 module_param(rx_packet_max, int, 0);
 159 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
 160
 161 struct cpsw_wr_regs {
 162         u32     id_ver;
 163         u32     soft_reset;
 164         u32     control;
 165         u32     int_control;
 166         u32     rx_thresh_en;
 167         u32     rx_en;
 168         u32     tx_en;
 169         u32     misc_en;
 170         u32     mem_allign1[8];
 171         u32     rx_thresh_stat;
 172         u32     rx_stat;
 173         u32     tx_stat;
 174         u32     misc_stat;
 175         u32     mem_allign2[8];
 176         u32     rx_imax;
 177         u32     tx_imax;
 178
 179 };
 180
 181 struct cpsw_ss_regs {
 182         u32     id_ver;
 183         u32     control;
 184         u32     soft_reset;
 185         u32     stat_port_en;
 186         u32     ptype;
 187         u32     soft_idle;
 188         u32     thru_rate;
 189         u32     gap_thresh;
 190         u32     tx_start_wds;
 191         u32     flow_control;
 192         u32     vlan_ltype;
 193         u32     ts_ltype;
 194         u32     dlr_ltype;
 195 };
 196
 197 /* CPSW_PORT_V1 */
 198 #define CPSW1_MAX_BLKS      0x00 /* Maximum FIFO Blocks */
 199 #define CPSW1_BLK_CNT       0x04 /* FIFO Block Usage Count (Read Only) */
 200 #define CPSW1_TX_IN_CTL     0x08 /* Transmit FIFO Control */
 201 #define CPSW1_PORT_VLAN     0x0c /* VLAN Register */
 202 #define CPSW1_TX_PRI_MAP    0x10 /* Tx Header Priority to Switch Pri Mapping */
 203 #define CPSW1_TS_CTL        0x14 /* Time Sync Control */
 204 #define CPSW1_TS_SEQ_LTYPE  0x18 /* Time Sync Sequence ID Offset and Msg Type */
 205 #define CPSW1_TS_VLAN       0x1c /* Time Sync VLAN1 and VLAN2 */
 206
 207 /* CPSW_PORT_V2 */
 208 #define CPSW2_CONTROL       0x00 /* Control Register */
 209 #define CPSW2_MAX_BLKS      0x08 /* Maximum FIFO Blocks */
 210 #define CPSW2_BLK_CNT       0x0c /* FIFO Block Usage Count (Read Only) */
 211 #define CPSW2_TX_IN_CTL     0x10 /* Transmit FIFO Control */
 212 #define CPSW2_PORT_VLAN     0x14 /* VLAN Register */
 213 #define CPSW2_TX_PRI_MAP    0x18 /* Tx Header Priority to Switch Pri Mapping */
 214 #define CPSW2_TS_SEQ_MTYPE  0x1c /* Time Sync Sequence ID Offset and Msg Type */
 215
 216 /* CPSW_PORT_V1 and V2 */
 217 #define SA_LO               0x20 /* CPGMAC_SL Source Address Low */
 218 #define SA_HI               0x24 /* CPGMAC_SL Source Address High */
 219 #define SEND_PERCENT        0x28 /* Transmit Queue Send Percentages */
 220
 221 /* CPSW_PORT_V2 only */
 222 #define RX_DSCP_PRI_MAP0    0x30 /* Rx DSCP Priority to Rx Packet Mapping */
 223 #define RX_DSCP_PRI_MAP1    0x34 /* Rx DSCP Priority to Rx Packet Mapping */
 224 #define RX_DSCP_PRI_MAP2    0x38 /* Rx DSCP Priority to Rx Packet Mapping */
 225 #define RX_DSCP_PRI_MAP3    0x3c /* Rx DSCP Priority to Rx Packet Mapping */
 226 #define RX_DSCP_PRI_MAP4    0x40 /* Rx DSCP Priority to Rx Packet Mapping */
 227 #define RX_DSCP_PRI_MAP5    0x44 /* Rx DSCP Priority to Rx Packet Mapping */
 228 #define RX_DSCP_PRI_MAP6    0x48 /* Rx DSCP Priority to Rx Packet Mapping */
 229 #define RX_DSCP_PRI_MAP7    0x4c /* Rx DSCP Priority to Rx Packet Mapping */
 230
 231 /* Bit definitions for the CPSW2_CONTROL register */
 232 #define PASS_PRI_TAGGED     (1<<24) /* Pass Priority Tagged */
 233 #define VLAN_LTYPE2_EN      (1<<21) /* VLAN LTYPE 2 enable */
 234 #define VLAN_LTYPE1_EN      (1<<20) /* VLAN LTYPE 1 enable */
 235 #define DSCP_PRI_EN         (1<<16) /* DSCP Priority Enable */
 236 #define TS_320              (1<<14) /* Time Sync Dest Port 320 enable */
 237 #define TS_319              (1<<13) /* Time Sync Dest Port 319 enable */
 238 #define TS_132              (1<<12) /* Time Sync Dest IP Addr 132 enable */
 239 #define TS_131              (1<<11) /* Time Sync Dest IP Addr 131 enable */
 240 #define TS_130              (1<<10) /* Time Sync Dest IP Addr 130 enable */
 241 #define TS_129              (1<<9)  /* Time Sync Dest IP Addr 129 enable */
 242 #define TS_TTL_NONZERO      (1<<8)  /* Time Sync Time To Live Non-zero enable */
 243 #define TS_ANNEX_F_EN       (1<<6)  /* Time Sync Annex F enable */
 244 #define TS_ANNEX_D_EN       (1<<4)  /* Time Sync Annex D enable */
 245 #define TS_LTYPE2_EN        (1<<3)  /* Time Sync LTYPE 2 enable */
 246 #define TS_LTYPE1_EN        (1<<2)  /* Time Sync LTYPE 1 enable */
 247 #define TS_TX_EN            (1<<1)  /* Time Sync Transmit Enable */
 248 #define TS_RX_EN            (1<<0)  /* Time Sync Receive Enable */
 249
 250 #define CTRL_V2_TS_BITS \
 251         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 252          TS_TTL_NONZERO  | TS_ANNEX_D_EN | TS_LTYPE1_EN)
 253
 254 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
 255 #define CTRL_V2_TX_TS_BITS  (CTRL_V2_TS_BITS | TS_TX_EN)
 256 #define CTRL_V2_RX_TS_BITS  (CTRL_V2_TS_BITS | TS_RX_EN)
 257
 258
 259 #define CTRL_V3_TS_BITS \
 260         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 261          TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
 262          TS_LTYPE1_EN)
 263
 264 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
 265 #define CTRL_V3_TX_TS_BITS  (CTRL_V3_TS_BITS | TS_TX_EN)
 266 #define CTRL_V3_RX_TS_BITS  (CTRL_V3_TS_BITS | TS_RX_EN)
 267
 268 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
 269 #define TS_SEQ_ID_OFFSET_SHIFT   (16)    /* Time Sync Sequence ID Offset */
 270 #define TS_SEQ_ID_OFFSET_MASK    (0x3f)
 271 #define TS_MSG_TYPE_EN_SHIFT     (0)     /* Time Sync Message Type Enable */
 272 #define TS_MSG_TYPE_EN_MASK      (0xffff)
 273
 274 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
 275 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
 276
 277 /* Bit definitions for the CPSW1_TS_CTL register */
 278 #define CPSW_V1_TS_RX_EN                BIT(0)
 279 #define CPSW_V1_TS_TX_EN                BIT(4)
 280 #define CPSW_V1_MSG_TYPE_OFS            16
 281
 282 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
 283 #define CPSW_V1_SEQ_ID_OFS_SHIFT        16
 284
 285 struct cpsw_host_regs {
 286         u32     max_blks;
 287         u32     blk_cnt;
 288         u32     tx_in_ctl;
 289         u32     port_vlan;
 290         u32     tx_pri_map;
 291         u32     cpdma_tx_pri_map;
 292         u32     cpdma_rx_chan_map;
 293 };
 294
 295 struct cpsw_sliver_regs {
 296         u32     id_ver;
 297         u32     mac_control;
 298         u32     mac_status;
 299         u32     soft_reset;
 300         u32     rx_maxlen;
 301         u32     __reserved_0;
 302         u32     rx_pause;
 303         u32     tx_pause;
 304         u32     __reserved_1;
 305         u32     rx_pri_map;
 306 };
 307
 308 struct cpsw_hw_stats {
 309         u32     rxgoodframes;
 310         u32     rxbroadcastframes;
 311         u32     rxmulticastframes;
 312         u32     rxpauseframes;
 313         u32     rxcrcerrors;
 314         u32     rxaligncodeerrors;
 315         u32     rxoversizedframes;
 316         u32     rxjabberframes;
 317         u32     rxundersizedframes;
 318         u32     rxfragments;
 319         u32     __pad_0[2];
 320         u32     rxoctets;
 321         u32     txgoodframes;
 322         u32     txbroadcastframes;
 323         u32     txmulticastframes;
 324         u32     txpauseframes;
 325         u32     txdeferredframes;
 326         u32     txcollisionframes;
 327         u32     txsinglecollframes;
 328         u32     txmultcollframes;
 329         u32     txexcessivecollisions;
 330         u32     txlatecollisions;
 331         u32     txunderrun;
 332         u32     txcarriersenseerrors;
 333         u32     txoctets;
 334         u32     octetframes64;
 335         u32     octetframes65t127;
 336         u32     octetframes128t255;
 337         u32     octetframes256t511;
 338         u32     octetframes512t1023;
 339         u32     octetframes1024tup;
 340         u32     netoctets;
 341         u32     rxsofoverruns;
 342         u32     rxmofoverruns;
 343         u32     rxdmaoverruns;
 344 };
 345
 346 struct cpsw_slave {
 347         void __iomem                    *regs;
 348         struct cpsw_sliver_regs __iomem *sliver;
 349         int                             slave_num;
 350         u32                             mac_control;
 351         struct cpsw_slave_data          *data;
 352         struct phy_device               *phy;
 353         struct net_device               *ndev;
 354         u32                             port_vlan;
 355         u32                             open_stat;
 356 };
 357
 358 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
 359 {
 360         return __raw_readl(slave->regs + offset);
 361 }
 362
 363 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
 364 {
 365         __raw_writel(val, slave->regs + offset);
 366 }
 367
 368 struct cpsw_common {
 369         struct device                   *dev;
 370         struct cpsw_platform_data       data;
 371         struct napi_struct              napi_rx;
 372         struct napi_struct              napi_tx;
 373         struct cpsw_ss_regs __iomem     *regs;
 374         struct cpsw_wr_regs __iomem     *wr_regs;
 375         u8 __iomem                      *hw_stats;
 376         struct cpsw_host_regs __iomem   *host_port_regs;
 377         u32                             version;
 378         u32                             coal_intvl;
 379         u32                             bus_freq_mhz;
 380         int                             rx_packet_max;
 381         struct cpsw_slave               *slaves;
 382         struct cpdma_ctlr               *dma;
 383         struct cpdma_chan               *txch[CPSW_MAX_QUEUES];
 384         struct cpdma_chan               *rxch[CPSW_MAX_QUEUES];
 385         struct cpsw_ale                 *ale;
 386         bool                            quirk_irq;
 387         bool                            rx_irq_disabled;
 388         bool                            tx_irq_disabled;
 389         u32 irqs_table[IRQ_NUM];
 390         struct cpts                     *cpts;
 391         int                             rx_ch_num, tx_ch_num;
 392 };
 393
 394 struct cpsw_priv {
 395         struct net_device               *ndev;
 396         struct device                   *dev;
 397         u32                             msg_enable;
 398         u8                              mac_addr[ETH_ALEN];
 399         bool                            rx_pause;
 400         bool                            tx_pause;
 401         u32 emac_port;
 402         struct cpsw_common *cpsw;
 403 };
 404
 405 struct cpsw_stats {
 406         char stat_string[ETH_GSTRING_LEN];
 407         int type;
 408         int sizeof_stat;
 409         int stat_offset;
 410 };
 411
 412 enum {
 413         CPSW_STATS,
 414         CPDMA_RX_STATS,
 415         CPDMA_TX_STATS,
 416 };
 417
 418 #define CPSW_STAT(m)            CPSW_STATS,                             \
 419                                 sizeof(((struct cpsw_hw_stats *)0)->m), \
 420                                 offsetof(struct cpsw_hw_stats, m)
 421 #define CPDMA_RX_STAT(m)        CPDMA_RX_STATS,                            \
 422                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 423                                 offsetof(struct cpdma_chan_stats, m)
 424 #define CPDMA_TX_STAT(m)        CPDMA_TX_STATS,                            \
 425                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 426                                 offsetof(struct cpdma_chan_stats, m)
 427
 428 static const struct cpsw_stats cpsw_gstrings_stats[] = {
 429         { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
 430         { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
 431         { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
 432         { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
 433         { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
 434         { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
 435         { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
 436         { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
 437         { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
 438         { "Rx Fragments", CPSW_STAT(rxfragments) },
 439         { "Rx Octets", CPSW_STAT(rxoctets) },
 440         { "Good Tx Frames", CPSW_STAT(txgoodframes) },
 441         { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
 442         { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
 443         { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
 444         { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
 445         { "Collisions", CPSW_STAT(txcollisionframes) },
 446         { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
 447         { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
 448         { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
 449         { "Late Collisions", CPSW_STAT(txlatecollisions) },
 450         { "Tx Underrun", CPSW_STAT(txunderrun) },
 451         { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
 452         { "Tx Octets", CPSW_STAT(txoctets) },
 453         { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
 454         { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
 455         { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
 456         { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
 457         { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
 458         { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
 459         { "Net Octets", CPSW_STAT(netoctets) },
 460         { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
 461         { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
 462         { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
 463 };
 464
 465 static const struct cpsw_stats cpsw_gstrings_ch_stats[] = {
 466         { "head_enqueue", CPDMA_RX_STAT(head_enqueue) },
 467         { "tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
 468         { "pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
 469         { "misqueued", CPDMA_RX_STAT(misqueued) },
 470         { "desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
 471         { "pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
 472         { "runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
 473         { "runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
 474         { "empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
 475         { "busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
 476         { "good_dequeue", CPDMA_RX_STAT(good_dequeue) },
 477         { "requeue", CPDMA_RX_STAT(requeue) },
 478         { "teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
 479 };
 480
 481 #define CPSW_STATS_COMMON_LEN   ARRAY_SIZE(cpsw_gstrings_stats)
 482 #define CPSW_STATS_CH_LEN       ARRAY_SIZE(cpsw_gstrings_ch_stats)
 483
 484 #define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw)
 485 #define napi_to_cpsw(napi)      container_of(napi, struct cpsw_common, napi)
 486 #define for_each_slave(priv, func, arg...)                              \
 487         do {                                                            \
 488                 struct cpsw_slave *slave;                               \
 489                 struct cpsw_common *cpsw = (priv)->cpsw;                \
 490                 int n;                                                  \
 491                 if (cpsw->data.dual_emac)                               \
 492                         (func)((cpsw)->slaves + priv->emac_port, ##arg);\
 493                 else                                                    \
 494                         for (n = cpsw->data.slaves,                     \
 495                                         slave = cpsw->slaves;           \
 496                                         n; n--)                         \
 497                                 (func)(slave++, ##arg);                 \
 498         } while (0)
 499
 500 #define cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb)         \
 501         do {                                                            \
 502                 if (!cpsw->data.dual_emac)                              \
 503                         break;                                          \
 504                 if (CPDMA_RX_SOURCE_PORT(status) == 1) {                \
 505                         ndev = cpsw->slaves[0].ndev;                    \
 506                         skb->dev = ndev;                                \
 507                 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) {         \
 508                         ndev = cpsw->slaves[1].ndev;                    \
 509                         skb->dev = ndev;                                \
 510                 }                                                       \
 511         } while (0)
 512 #define cpsw_add_mcast(cpsw, priv, addr)                                \
 513         do {                                                            \
 514                 if (cpsw->data.dual_emac) {                             \
 515                         struct cpsw_slave *slave = cpsw->slaves +       \
 516                                                 priv->emac_port;        \
 517                         int slave_port = cpsw_get_slave_port(           \
 518                                                 slave->slave_num);      \
 519                         cpsw_ale_add_mcast(cpsw->ale, addr,             \
 520                                 1 << slave_port | ALE_PORT_HOST,        \
 521                                 ALE_VLAN, slave->port_vlan, 0);         \
 522                 } else {                                                \
 523                         cpsw_ale_add_mcast(cpsw->ale, addr,             \
 524                                 ALE_ALL_PORTS,                          \
 525                                 0, 0, 0);                               \
 526                 }                                                       \
 527         } while (0)
 528
 529 static inline int cpsw_get_slave_port(u32 slave_num)
 530 {
 531         return slave_num + 1;
 532 }
 533
 534 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
 535 {
 536         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
 537         struct cpsw_ale *ale = cpsw->ale;
 538         int i;
 539
 540         if (cpsw->data.dual_emac) {
 541                 bool flag = false;
 542
 543                 /* Enabling promiscuous mode for one interface will be
 544                  * common for both the interface as the interface shares
 545                  * the same hardware resource.
 546                  */
 547                 for (i = 0; i < cpsw->data.slaves; i++)
 548                         if (cpsw->slaves[i].ndev->flags & IFF_PROMISC)
 549                                 flag = true;
 550
 551                 if (!enable && flag) {
 552                         enable = true;
 553                         dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
 554                 }
 555
 556                 if (enable) {
 557                         /* Enable Bypass */
 558                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
 559
 560                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 561                 } else {
 562                         /* Disable Bypass */
 563                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
 564                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 565                 }
 566         } else {
 567                 if (enable) {
 568                         unsigned long timeout = jiffies + HZ;
 569
 570                         /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
 571                         for (i = 0; i <= cpsw->data.slaves; i++) {
 572                                 cpsw_ale_control_set(ale, i,
 573                                                      ALE_PORT_NOLEARN, 1);
 574                                 cpsw_ale_control_set(ale, i,
 575                                                      ALE_PORT_NO_SA_UPDATE, 1);
 576                         }
 577
 578                         /* Clear All Untouched entries */
 579                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 580                         do {
 581                                 cpu_relax();
 582                                 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
 583                                         break;
 584                         } while (time_after(timeout, jiffies));
 585                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 586
 587                         /* Clear all mcast from ALE */
 588                         cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS, -1);
 589
 590                         /* Flood All Unicast Packets to Host port */
 591                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
 592                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 593                 } else {
 594                         /* Don't Flood All Unicast Packets to Host port */
 595                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
 596
 597                         /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
 598                         for (i = 0; i <= cpsw->data.slaves; i++) {
 599                                 cpsw_ale_control_set(ale, i,
 600                                                      ALE_PORT_NOLEARN, 0);
 601                                 cpsw_ale_control_set(ale, i,
 602                                                      ALE_PORT_NO_SA_UPDATE, 0);
 603                         }
 604                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 605                 }
 606         }
 607 }
 608
 609 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
 610 {
 611         struct cpsw_priv *priv = netdev_priv(ndev);
 612         struct cpsw_common *cpsw = priv->cpsw;
 613         int vid;
 614
 615         if (cpsw->data.dual_emac)
 616                 vid = cpsw->slaves[priv->emac_port].port_vlan;
 617         else
 618                 vid = cpsw->data.default_vlan;
 619
 620         if (ndev->flags & IFF_PROMISC) {
 621                 /* Enable promiscuous mode */
 622                 cpsw_set_promiscious(ndev, true);
 623                 cpsw_ale_set_allmulti(cpsw->ale, IFF_ALLMULTI);
 624                 return;
 625         } else {
 626                 /* Disable promiscuous mode */
 627                 cpsw_set_promiscious(ndev, false);
 628         }
 629
 630         /* Restore allmulti on vlans if necessary */
 631         cpsw_ale_set_allmulti(cpsw->ale, priv->ndev->flags & IFF_ALLMULTI);
 632
 633         /* Clear all mcast from ALE */
 634         cpsw_ale_flush_multicast(cpsw->ale, ALE_ALL_PORTS, vid);
 635
 636         if (!netdev_mc_empty(ndev)) {
 637                 struct netdev_hw_addr *ha;
 638
 639                 /* program multicast address list into ALE register */
 640                 netdev_for_each_mc_addr(ha, ndev) {
 641                         cpsw_add_mcast(cpsw, priv, (u8 *)ha->addr);
 642                 }
 643         }
 644 }
 645
 646 static void cpsw_intr_enable(struct cpsw_common *cpsw)
 647 {
 648         __raw_writel(0xFF, &cpsw->wr_regs->tx_en);
 649         __raw_writel(0xFF, &cpsw->wr_regs->rx_en);
 650
 651         cpdma_ctlr_int_ctrl(cpsw->dma, true);
 652         return;
 653 }
 654
 655 static void cpsw_intr_disable(struct cpsw_common *cpsw)
 656 {
 657         __raw_writel(0, &cpsw->wr_regs->tx_en);
 658         __raw_writel(0, &cpsw->wr_regs->rx_en);
 659
 660         cpdma_ctlr_int_ctrl(cpsw->dma, false);
 661         return;
 662 }
 663
 664 static void cpsw_tx_handler(void *token, int len, int status)
 665 {
 666         struct netdev_queue     *txq;
 667         struct sk_buff          *skb = token;
 668         struct net_device       *ndev = skb->dev;
 669         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
 670
 671         /* Check whether the queue is stopped due to stalled tx dma, if the
 672          * queue is stopped then start the queue as we have free desc for tx
 673          */
 674         txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb));
 675         if (unlikely(netif_tx_queue_stopped(txq)))
 676                 netif_tx_wake_queue(txq);
 677
 678         cpts_tx_timestamp(cpsw->cpts, skb);
 679         ndev->stats.tx_packets++;
 680         ndev->stats.tx_bytes += len;
 681         dev_kfree_skb_any(skb);
 682 }
 683
 684 static void cpsw_rx_handler(void *token, int len, int status)
 685 {
 686         struct cpdma_chan       *ch;
 687         struct sk_buff          *skb = token;
 688         struct sk_buff          *new_skb;
 689         struct net_device       *ndev = skb->dev;
 690         int                     ret = 0;
 691         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
 692
 693         cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb);
 694
 695         if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
 696                 bool ndev_status = false;
 697                 struct cpsw_slave *slave = cpsw->slaves;
 698                 int n;
 699
 700                 if (cpsw->data.dual_emac) {
 701                         /* In dual emac mode check for all interfaces */
 702                         for (n = cpsw->data.slaves; n; n--, slave++)
 703                                 if (netif_running(slave->ndev))
 704                                         ndev_status = true;
 705                 }
 706
 707                 if (ndev_status && (status >= 0)) {
 708                         /* The packet received is for the interface which
 709                          * is already down and the other interface is up
 710                          * and running, instead of freeing which results
 711                          * in reducing of the number of rx descriptor in
 712                          * DMA engine, requeue skb back to cpdma.
 713                          */
 714                         new_skb = skb;
 715                         goto requeue;
 716                 }
 717
 718                 /* the interface is going down, skbs are purged */
 719                 dev_kfree_skb_any(skb);
 720                 return;
 721         }
 722
 723         new_skb = netdev_alloc_skb_ip_align(ndev, cpsw->rx_packet_max);
 724         if (new_skb) {
 725                 skb_copy_queue_mapping(new_skb, skb);
 726                 skb_put(skb, len);
 727                 cpts_rx_timestamp(cpsw->cpts, skb);
 728                 skb->protocol = eth_type_trans(skb, ndev);
 729                 netif_receive_skb(skb);
 730                 ndev->stats.rx_bytes += len;
 731                 ndev->stats.rx_packets++;
 732                 kmemleak_not_leak(new_skb);
 733         } else {
 734                 ndev->stats.rx_dropped++;
 735                 new_skb = skb;
 736         }
 737
 738 requeue:
 739         ch = cpsw->rxch[skb_get_queue_mapping(new_skb)];
 740         ret = cpdma_chan_submit(ch, new_skb, new_skb->data,
 741                                 skb_tailroom(new_skb), 0);
 742         if (WARN_ON(ret < 0))
 743                 dev_kfree_skb_any(new_skb);
 744 }
 745
 746 static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
 747 {
 748         struct cpsw_common *cpsw = dev_id;
 749
 750         writel(0, &cpsw->wr_regs->tx_en);
 751         cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_TX);
 752
 753         if (cpsw->quirk_irq) {
 754                 disable_irq_nosync(cpsw->irqs_table[1]);
 755                 cpsw->tx_irq_disabled = true;
 756         }
 757
 758         napi_schedule(&cpsw->napi_tx);
 759         return IRQ_HANDLED;
 760 }
 761
 762 static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
 763 {
 764         struct cpsw_common *cpsw = dev_id;
 765
 766         cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_RX);
 767         writel(0, &cpsw->wr_regs->rx_en);
 768
 769         if (cpsw->quirk_irq) {
 770                 disable_irq_nosync(cpsw->irqs_table[0]);
 771                 cpsw->rx_irq_disabled = true;
 772         }
 773
 774         napi_schedule(&cpsw->napi_rx);
 775         return IRQ_HANDLED;
 776 }
 777
 778 static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
 779 {
 780         u32                     ch_map;
 781         int                     num_tx, ch;
 782         struct cpsw_common      *cpsw = napi_to_cpsw(napi_tx);
 783
 784         /* process every unprocessed channel */
 785         ch_map = cpdma_ctrl_txchs_state(cpsw->dma);
 786         for (ch = 0, num_tx = 0; num_tx < budget; ch_map >>= 1, ch++) {
 787                 if (!ch_map) {
 788                         ch_map = cpdma_ctrl_txchs_state(cpsw->dma);
 789                         if (!ch_map)
 790                                 break;
 791
 792                         ch = 0;
 793                 }
 794
 795                 if (!(ch_map & 0x01))
 796                         continue;
 797
 798                 num_tx += cpdma_chan_process(cpsw->txch[ch], budget - num_tx);
 799         }
 800
 801         if (num_tx < budget) {
 802                 napi_complete(napi_tx);
 803                 writel(0xff, &cpsw->wr_regs->tx_en);
 804                 if (cpsw->quirk_irq && cpsw->tx_irq_disabled) {
 805                         cpsw->tx_irq_disabled = false;
 806                         enable_irq(cpsw->irqs_table[1]);
 807                 }
 808         }
 809
 810         return num_tx;
 811 }
 812
 813 static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
 814 {
 815         u32                     ch_map;
 816         int                     num_rx, ch;
 817         struct cpsw_common      *cpsw = napi_to_cpsw(napi_rx);
 818
 819         /* process every unprocessed channel */
 820         ch_map = cpdma_ctrl_rxchs_state(cpsw->dma);
 821         for (ch = 0, num_rx = 0; num_rx < budget; ch_map >>= 1, ch++) {
 822                 if (!ch_map) {
 823                         ch_map = cpdma_ctrl_rxchs_state(cpsw->dma);
 824                         if (!ch_map)
 825                                 break;
 826
 827                         ch = 0;
 828                 }
 829
 830                 if (!(ch_map & 0x01))
 831                         continue;
 832
 833                 num_rx += cpdma_chan_process(cpsw->rxch[ch], budget - num_rx);
 834         }
 835
 836         if (num_rx < budget) {
 837                 napi_complete(napi_rx);
 838                 writel(0xff, &cpsw->wr_regs->rx_en);
 839                 if (cpsw->quirk_irq && cpsw->rx_irq_disabled) {
 840                         cpsw->rx_irq_disabled = false;
 841                         enable_irq(cpsw->irqs_table[0]);
 842                 }
 843         }
 844
 845         return num_rx;
 846 }
 847
 848 static inline void soft_reset(const char *module, void __iomem *reg)
 849 {
 850         unsigned long timeout = jiffies + HZ;
 851
 852         __raw_writel(1, reg);
 853         do {
 854                 cpu_relax();
 855         } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
 856
 857         WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
 858 }
 859
 860 #define mac_hi(mac)     (((mac)[0] << 0) | ((mac)[1] << 8) |    \
 861                          ((mac)[2] << 16) | ((mac)[3] << 24))
 862 #define mac_lo(mac)     (((mac)[4] << 0) | ((mac)[5] << 8))
 863
 864 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
 865                                struct cpsw_priv *priv)
 866 {
 867         slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
 868         slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
 869 }
 870
 871 static void _cpsw_adjust_link(struct cpsw_slave *slave,
 872                               struct cpsw_priv *priv, bool *link)
 873 {
 874         struct phy_device       *phy = slave->phy;
 875         u32                     mac_control = 0;
 876         u32                     slave_port;
 877         struct cpsw_common *cpsw = priv->cpsw;
 878
 879         if (!phy)
 880                 return;
 881
 882         slave_port = cpsw_get_slave_port(slave->slave_num);
 883
 884         if (phy->link) {
 885                 mac_control = cpsw->data.mac_control;
 886
 887                 /* enable forwarding */
 888                 cpsw_ale_control_set(cpsw->ale, slave_port,
 889                                      ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
 890
 891                 if (phy->speed == 1000)
 892                         mac_control |= BIT(7);  /* GIGABITEN    */
 893                 if (phy->duplex)
 894                         mac_control |= BIT(0);  /* FULLDUPLEXEN */
 895
 896                 /* set speed_in input in case RMII mode is used in 100Mbps */
 897                 if (phy->speed == 100)
 898                         mac_control |= BIT(15);
 899                 else if (phy->speed == 10)
 900                         mac_control |= BIT(18); /* In Band mode */
 901
 902                 if (priv->rx_pause)
 903                         mac_control |= BIT(3);
 904
 905                 if (priv->tx_pause)
 906                         mac_control |= BIT(4);
 907
 908                 *link = true;
 909         } else {
 910                 mac_control = 0;
 911                 /* disable forwarding */
 912                 cpsw_ale_control_set(cpsw->ale, slave_port,
 913                                      ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
 914         }
 915
 916         if (mac_control != slave->mac_control) {
 917                 phy_print_status(phy);
 918                 __raw_writel(mac_control, &slave->sliver->mac_control);
 919         }
 920
 921         slave->mac_control = mac_control;
 922 }
 923
 924 static void cpsw_adjust_link(struct net_device *ndev)
 925 {
 926         struct cpsw_priv        *priv = netdev_priv(ndev);
 927         bool                    link = false;
 928
 929         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
 930
 931         if (link) {
 932                 netif_carrier_on(ndev);
 933                 if (netif_running(ndev))
 934                         netif_tx_wake_all_queues(ndev);
 935         } else {
 936                 netif_carrier_off(ndev);
 937                 netif_tx_stop_all_queues(ndev);
 938         }
 939 }
 940
 941 static int cpsw_get_coalesce(struct net_device *ndev,
 942                                 struct ethtool_coalesce *coal)
 943 {
 944         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
 945
 946         coal->rx_coalesce_usecs = cpsw->coal_intvl;
 947         return 0;
 948 }
 949
 950 static int cpsw_set_coalesce(struct net_device *ndev,
 951                                 struct ethtool_coalesce *coal)
 952 {
 953         struct cpsw_priv *priv = netdev_priv(ndev);
 954         u32 int_ctrl;
 955         u32 num_interrupts = 0;
 956         u32 prescale = 0;
 957         u32 addnl_dvdr = 1;
 958         u32 coal_intvl = 0;
 959         struct cpsw_common *cpsw = priv->cpsw;
 960
 961         coal_intvl = coal->rx_coalesce_usecs;
 962
 963         int_ctrl =  readl(&cpsw->wr_regs->int_control);
 964         prescale = cpsw->bus_freq_mhz * 4;
 965
 966         if (!coal->rx_coalesce_usecs) {
 967                 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
 968                 goto update_return;
 969         }
 970
 971         if (coal_intvl < CPSW_CMINTMIN_INTVL)
 972                 coal_intvl = CPSW_CMINTMIN_INTVL;
 973
 974         if (coal_intvl > CPSW_CMINTMAX_INTVL) {
 975                 /* Interrupt pacer works with 4us Pulse, we can
 976                  * throttle further by dilating the 4us pulse.
 977                  */
 978                 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
 979
 980                 if (addnl_dvdr > 1) {
 981                         prescale *= addnl_dvdr;
 982                         if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
 983                                 coal_intvl = (CPSW_CMINTMAX_INTVL
 984                                                 * addnl_dvdr);
 985                 } else {
 986                         addnl_dvdr = 1;
 987                         coal_intvl = CPSW_CMINTMAX_INTVL;
 988                 }
 989         }
 990
 991         num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
 992         writel(num_interrupts, &cpsw->wr_regs->rx_imax);
 993         writel(num_interrupts, &cpsw->wr_regs->tx_imax);
 994
 995         int_ctrl |= CPSW_INTPACEEN;
 996         int_ctrl &= (~CPSW_INTPRESCALE_MASK);
 997         int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
 998
 999 update_return:
1000         writel(int_ctrl, &cpsw->wr_regs->int_control);
1001
1002         cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
1003         cpsw->coal_intvl = coal_intvl;
1004
1005         return 0;
1006 }
1007
1008 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
1009 {
1010         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1011
1012         switch (sset) {
1013         case ETH_SS_STATS:
1014                 return (CPSW_STATS_COMMON_LEN +
1015                        (cpsw->rx_ch_num + cpsw->tx_ch_num) *
1016                        CPSW_STATS_CH_LEN);
1017         default:
1018                 return -EOPNOTSUPP;
1019         }
1020 }
1021
1022 static void cpsw_add_ch_strings(u8 **p, int ch_num, int rx_dir)
1023 {
1024         int ch_stats_len;
1025         int line;
1026         int i;
1027
1028         ch_stats_len = CPSW_STATS_CH_LEN * ch_num;
1029         for (i = 0; i < ch_stats_len; i++) {
1030                 line = i % CPSW_STATS_CH_LEN;
1031                 snprintf(*p, ETH_GSTRING_LEN,
1032                          "%s DMA chan %d: %s", rx_dir ? "Rx" : "Tx",
1033                          i / CPSW_STATS_CH_LEN,
1034                          cpsw_gstrings_ch_stats[line].stat_string);
1035                 *p += ETH_GSTRING_LEN;
1036         }
1037 }
1038
1039 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1040 {
1041         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1042         u8 *p = data;
1043         int i;
1044
1045         switch (stringset) {
1046         case ETH_SS_STATS:
1047                 for (i = 0; i < CPSW_STATS_COMMON_LEN; i++) {
1048                         memcpy(p, cpsw_gstrings_stats[i].stat_string,
1049                                ETH_GSTRING_LEN);
1050                         p += ETH_GSTRING_LEN;
1051                 }
1052
1053                 cpsw_add_ch_strings(&p, cpsw->rx_ch_num, 1);
1054                 cpsw_add_ch_strings(&p, cpsw->tx_ch_num, 0);
1055                 break;
1056         }
1057 }
1058
1059 static void cpsw_get_ethtool_stats(struct net_device *ndev,
1060                                     struct ethtool_stats *stats, u64 *data)
1061 {
1062         u8 *p;
1063         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1064         struct cpdma_chan_stats ch_stats;
1065         int i, l, ch;
1066
1067         /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1068         for (l = 0; l < CPSW_STATS_COMMON_LEN; l++)
1069                 data[l] = readl(cpsw->hw_stats +
1070                                 cpsw_gstrings_stats[l].stat_offset);
1071
1072         for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1073                 cpdma_chan_get_stats(cpsw->rxch[ch], &ch_stats);
1074                 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1075                         p = (u8 *)&ch_stats +
1076                                 cpsw_gstrings_ch_stats[i].stat_offset;
1077                         data[l] = *(u32 *)p;
1078                 }
1079         }
1080
1081         for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
1082                 cpdma_chan_get_stats(cpsw->txch[ch], &ch_stats);
1083                 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1084                         p = (u8 *)&ch_stats +
1085                                 cpsw_gstrings_ch_stats[i].stat_offset;
1086                         data[l] = *(u32 *)p;
1087                 }
1088         }
1089 }
1090
1091 static int cpsw_common_res_usage_state(struct cpsw_common *cpsw)
1092 {
1093         u32 i;
1094         u32 usage_count = 0;
1095
1096         if (!cpsw->data.dual_emac)
1097                 return 0;
1098
1099         for (i = 0; i < cpsw->data.slaves; i++)
1100                 if (cpsw->slaves[i].open_stat)
1101                         usage_count++;
1102
1103         return usage_count;
1104 }
1105
1106 static inline int cpsw_tx_packet_submit(struct cpsw_priv *priv,
1107                                         struct sk_buff *skb,
1108                                         struct cpdma_chan *txch)
1109 {
1110         struct cpsw_common *cpsw = priv->cpsw;
1111
1112         return cpdma_chan_submit(txch, skb, skb->data, skb->len,
1113                                  priv->emac_port + cpsw->data.dual_emac);
1114 }
1115
1116 static inline void cpsw_add_dual_emac_def_ale_entries(
1117                 struct cpsw_priv *priv, struct cpsw_slave *slave,
1118                 u32 slave_port)
1119 {
1120         struct cpsw_common *cpsw = priv->cpsw;
1121         u32 port_mask = 1 << slave_port | ALE_PORT_HOST;
1122
1123         if (cpsw->version == CPSW_VERSION_1)
1124                 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1125         else
1126                 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1127         cpsw_ale_add_vlan(cpsw->ale, slave->port_vlan, port_mask,
1128                           port_mask, port_mask, 0);
1129         cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1130                            port_mask, ALE_VLAN, slave->port_vlan, 0);
1131         cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
1132                            HOST_PORT_NUM, ALE_VLAN |
1133                            ALE_SECURE, slave->port_vlan);
1134 }
1135
1136 static void soft_reset_slave(struct cpsw_slave *slave)
1137 {
1138         char name[32];
1139
1140         snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1141         soft_reset(name, &slave->sliver->soft_reset);
1142 }
1143
1144 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1145 {
1146         u32 slave_port;
1147         struct cpsw_common *cpsw = priv->cpsw;
1148
1149         soft_reset_slave(slave);
1150
1151         /* setup priority mapping */
1152         __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1153
1154         switch (cpsw->version) {
1155         case CPSW_VERSION_1:
1156                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1157                 break;
1158         case CPSW_VERSION_2:
1159         case CPSW_VERSION_3:
1160         case CPSW_VERSION_4:
1161                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1162                 break;
1163         }
1164
1165         /* setup max packet size, and mac address */
1166         __raw_writel(cpsw->rx_packet_max, &slave->sliver->rx_maxlen);
1167         cpsw_set_slave_mac(slave, priv);
1168
1169         slave->mac_control = 0; /* no link yet */
1170
1171         slave_port = cpsw_get_slave_port(slave->slave_num);
1172
1173         if (cpsw->data.dual_emac)
1174                 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1175         else
1176                 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1177                                    1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1178
1179         if (slave->data->phy_node) {
1180                 slave->phy = of_phy_connect(priv->ndev, slave->data->phy_node,
1181                                  &cpsw_adjust_link, 0, slave->data->phy_if);
1182                 if (!slave->phy) {
1183                         dev_err(priv->dev, "phy \"%s\" not found on slave %d\n",
1184                                 slave->data->phy_node->full_name,
1185                                 slave->slave_num);
1186                         return;
1187                 }
1188         } else {
1189                 slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
1190                                  &cpsw_adjust_link, slave->data->phy_if);
1191                 if (IS_ERR(slave->phy)) {
1192                         dev_err(priv->dev,
1193                                 "phy \"%s\" not found on slave %d, err %ld\n",
1194                                 slave->data->phy_id, slave->slave_num,
1195                                 PTR_ERR(slave->phy));
1196                         slave->phy = NULL;
1197                         return;
1198                 }
1199         }
1200
1201         phy_attached_info(slave->phy);
1202
1203         phy_start(slave->phy);
1204
1205         /* Configure GMII_SEL register */
1206         cpsw_phy_sel(cpsw->dev, slave->phy->interface, slave->slave_num);
1207 }
1208
1209 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1210 {
1211         struct cpsw_common *cpsw = priv->cpsw;
1212         const int vlan = cpsw->data.default_vlan;
1213         u32 reg;
1214         int i;
1215         int unreg_mcast_mask;
1216
1217         reg = (cpsw->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1218                CPSW2_PORT_VLAN;
1219
1220         writel(vlan, &cpsw->host_port_regs->port_vlan);
1221
1222         for (i = 0; i < cpsw->data.slaves; i++)
1223                 slave_write(cpsw->slaves + i, vlan, reg);
1224
1225         if (priv->ndev->flags & IFF_ALLMULTI)
1226                 unreg_mcast_mask = ALE_ALL_PORTS;
1227         else
1228                 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1229
1230         cpsw_ale_add_vlan(cpsw->ale, vlan, ALE_ALL_PORTS,
1231                           ALE_ALL_PORTS, ALE_ALL_PORTS,
1232                           unreg_mcast_mask);
1233 }
1234
1235 static void cpsw_init_host_port(struct cpsw_priv *priv)
1236 {
1237         u32 fifo_mode;
1238         u32 control_reg;
1239         struct cpsw_common *cpsw = priv->cpsw;
1240
1241         /* soft reset the controller and initialize ale */
1242         soft_reset("cpsw", &cpsw->regs->soft_reset);
1243         cpsw_ale_start(cpsw->ale);
1244
1245         /* switch to vlan unaware mode */
1246         cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_VLAN_AWARE,
1247                              CPSW_ALE_VLAN_AWARE);
1248         control_reg = readl(&cpsw->regs->control);
1249         control_reg |= CPSW_VLAN_AWARE;
1250         writel(control_reg, &cpsw->regs->control);
1251         fifo_mode = (cpsw->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1252                      CPSW_FIFO_NORMAL_MODE;
1253         writel(fifo_mode, &cpsw->host_port_regs->tx_in_ctl);
1254
1255         /* setup host port priority mapping */
1256         __raw_writel(CPDMA_TX_PRIORITY_MAP,
1257                      &cpsw->host_port_regs->cpdma_tx_pri_map);
1258         __raw_writel(0, &cpsw->host_port_regs->cpdma_rx_chan_map);
1259
1260         cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM,
1261                              ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1262
1263         if (!cpsw->data.dual_emac) {
1264                 cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
1265                                    0, 0);
1266                 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1267                                    ALE_PORT_HOST, 0, 0, ALE_MCAST_FWD_2);
1268         }
1269 }
1270
1271 static int cpsw_fill_rx_channels(struct cpsw_priv *priv)
1272 {
1273         struct cpsw_common *cpsw = priv->cpsw;
1274         struct sk_buff *skb;
1275         int ch_buf_num;
1276         int ch, i, ret;
1277
1278         for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1279                 ch_buf_num = cpdma_chan_get_rx_buf_num(cpsw->rxch[ch]);
1280                 for (i = 0; i < ch_buf_num; i++) {
1281                         skb = __netdev_alloc_skb_ip_align(priv->ndev,
1282                                                           cpsw->rx_packet_max,
1283                                                           GFP_KERNEL);
1284                         if (!skb) {
1285                                 cpsw_err(priv, ifup, "cannot allocate skb\n");
1286                                 return -ENOMEM;
1287                         }
1288
1289                         skb_set_queue_mapping(skb, ch);
1290                         ret = cpdma_chan_submit(cpsw->rxch[ch], skb, skb->data,
1291                                                 skb_tailroom(skb), 0);
1292                         if (ret < 0) {
1293                                 cpsw_err(priv, ifup,
1294                                          "cannot submit skb to channel %d rx, error %d\n",
1295                                          ch, ret);
1296                                 kfree_skb(skb);
1297                                 return ret;
1298                         }
1299                         kmemleak_not_leak(skb);
1300                 }
1301
1302                 cpsw_info(priv, ifup, "ch %d rx, submitted %d descriptors\n",
1303                           ch, ch_buf_num);
1304         }
1305
1306         return 0;
1307 }
1308
1309 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_common *cpsw)
1310 {
1311         u32 slave_port;
1312
1313         slave_port = cpsw_get_slave_port(slave->slave_num);
1314
1315         if (!slave->phy)
1316                 return;
1317         phy_stop(slave->phy);
1318         phy_disconnect(slave->phy);
1319         slave->phy = NULL;
1320         cpsw_ale_control_set(cpsw->ale, slave_port,
1321                              ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1322         soft_reset_slave(slave);
1323 }
1324
1325 static int cpsw_ndo_open(struct net_device *ndev)
1326 {
1327         struct cpsw_priv *priv = netdev_priv(ndev);
1328         struct cpsw_common *cpsw = priv->cpsw;
1329         int ret;
1330         u32 reg;
1331
1332         ret = pm_runtime_get_sync(cpsw->dev);
1333         if (ret < 0) {
1334                 pm_runtime_put_noidle(cpsw->dev);
1335                 return ret;
1336         }
1337
1338         if (!cpsw_common_res_usage_state(cpsw))
1339                 cpsw_intr_disable(cpsw);
1340         netif_carrier_off(ndev);
1341
1342         /* Notify the stack of the actual queue counts. */
1343         ret = netif_set_real_num_tx_queues(ndev, cpsw->tx_ch_num);
1344         if (ret) {
1345                 dev_err(priv->dev, "cannot set real number of tx queues\n");
1346                 goto err_cleanup;
1347         }
1348
1349         ret = netif_set_real_num_rx_queues(ndev, cpsw->rx_ch_num);
1350         if (ret) {
1351                 dev_err(priv->dev, "cannot set real number of rx queues\n");
1352                 goto err_cleanup;
1353         }
1354
1355         reg = cpsw->version;
1356
1357         dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1358                  CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1359                  CPSW_RTL_VERSION(reg));
1360
1361         /* initialize host and slave ports */
1362         if (!cpsw_common_res_usage_state(cpsw))
1363                 cpsw_init_host_port(priv);
1364         for_each_slave(priv, cpsw_slave_open, priv);
1365
1366         /* Add default VLAN */
1367         if (!cpsw->data.dual_emac)
1368                 cpsw_add_default_vlan(priv);
1369         else
1370                 cpsw_ale_add_vlan(cpsw->ale, cpsw->data.default_vlan,
1371                                   ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0);
1372
1373         if (!cpsw_common_res_usage_state(cpsw)) {
1374                 /* setup tx dma to fixed prio and zero offset */
1375                 cpdma_control_set(cpsw->dma, CPDMA_TX_PRIO_FIXED, 1);
1376                 cpdma_control_set(cpsw->dma, CPDMA_RX_BUFFER_OFFSET, 0);
1377
1378                 /* disable priority elevation */
1379                 __raw_writel(0, &cpsw->regs->ptype);
1380
1381                 /* enable statistics collection only on all ports */
1382                 __raw_writel(0x7, &cpsw->regs->stat_port_en);
1383
1384                 /* Enable internal fifo flow control */
1385                 writel(0x7, &cpsw->regs->flow_control);
1386
1387                 napi_enable(&cpsw->napi_rx);
1388                 napi_enable(&cpsw->napi_tx);
1389
1390                 if (cpsw->tx_irq_disabled) {
1391                         cpsw->tx_irq_disabled = false;
1392                         enable_irq(cpsw->irqs_table[1]);
1393                 }
1394
1395                 if (cpsw->rx_irq_disabled) {
1396                         cpsw->rx_irq_disabled = false;
1397                         enable_irq(cpsw->irqs_table[0]);
1398                 }
1399
1400                 ret = cpsw_fill_rx_channels(priv);
1401                 if (ret < 0)
1402                         goto err_cleanup;
1403
1404                 if (cpts_register(cpsw->dev, cpsw->cpts,
1405                                   cpsw->data.cpts_clock_mult,
1406                                   cpsw->data.cpts_clock_shift))
1407                         dev_err(priv->dev, "error registering cpts device\n");
1408
1409         }
1410
1411         /* Enable Interrupt pacing if configured */
1412         if (cpsw->coal_intvl != 0) {
1413                 struct ethtool_coalesce coal;
1414
1415                 coal.rx_coalesce_usecs = cpsw->coal_intvl;
1416                 cpsw_set_coalesce(ndev, &coal);
1417         }
1418
1419         cpdma_ctlr_start(cpsw->dma);
1420         cpsw_intr_enable(cpsw);
1421
1422         if (cpsw->data.dual_emac)
1423                 cpsw->slaves[priv->emac_port].open_stat = true;
1424
1425         netif_tx_start_all_queues(ndev);
1426
1427         return 0;
1428
1429 err_cleanup:
1430         cpdma_ctlr_stop(cpsw->dma);
1431         for_each_slave(priv, cpsw_slave_stop, cpsw);
1432         pm_runtime_put_sync(cpsw->dev);
1433         netif_carrier_off(priv->ndev);
1434         return ret;
1435 }
1436
1437 static int cpsw_ndo_stop(struct net_device *ndev)
1438 {
1439         struct cpsw_priv *priv = netdev_priv(ndev);
1440         struct cpsw_common *cpsw = priv->cpsw;
1441
1442         cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1443         netif_tx_stop_all_queues(priv->ndev);
1444         netif_carrier_off(priv->ndev);
1445
1446         if (cpsw_common_res_usage_state(cpsw) <= 1) {
1447                 napi_disable(&cpsw->napi_rx);
1448                 napi_disable(&cpsw->napi_tx);
1449                 cpts_unregister(cpsw->cpts);
1450                 cpsw_intr_disable(cpsw);
1451                 cpdma_ctlr_stop(cpsw->dma);
1452                 cpsw_ale_stop(cpsw->ale);
1453         }
1454         for_each_slave(priv, cpsw_slave_stop, cpsw);
1455         pm_runtime_put_sync(cpsw->dev);
1456         if (cpsw->data.dual_emac)
1457                 cpsw->slaves[priv->emac_port].open_stat = false;
1458         return 0;
1459 }
1460
1461 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1462                                        struct net_device *ndev)
1463 {
1464         struct cpsw_priv *priv = netdev_priv(ndev);
1465         struct cpsw_common *cpsw = priv->cpsw;
1466         struct netdev_queue *txq;
1467         struct cpdma_chan *txch;
1468         int ret, q_idx;
1469
1470         netif_trans_update(ndev);
1471
1472         if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1473                 cpsw_err(priv, tx_err, "packet pad failed\n");
1474                 ndev->stats.tx_dropped++;
1475                 return NETDEV_TX_OK;
1476         }
1477
1478         if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1479                                 cpsw->cpts->tx_enable)
1480                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1481
1482         skb_tx_timestamp(skb);
1483
1484         q_idx = skb_get_queue_mapping(skb);
1485         if (q_idx >= cpsw->tx_ch_num)
1486                 q_idx = q_idx % cpsw->tx_ch_num;
1487
1488         txch = cpsw->txch[q_idx];
1489         ret = cpsw_tx_packet_submit(priv, skb, txch);
1490         if (unlikely(ret != 0)) {
1491                 cpsw_err(priv, tx_err, "desc submit failed\n");
1492                 goto fail;
1493         }
1494
1495         /* If there is no more tx desc left free then we need to
1496          * tell the kernel to stop sending us tx frames.
1497          */
1498         if (unlikely(!cpdma_check_free_tx_desc(txch))) {
1499                 txq = netdev_get_tx_queue(ndev, q_idx);
1500                 netif_tx_stop_queue(txq);
1501         }
1502
1503         return NETDEV_TX_OK;
1504 fail:
1505         ndev->stats.tx_dropped++;
1506         txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb));
1507         netif_tx_stop_queue(txq);
1508         return NETDEV_TX_BUSY;
1509 }
1510
1511 #ifdef CONFIG_TI_CPTS
1512
1513 static void cpsw_hwtstamp_v1(struct cpsw_common *cpsw)
1514 {
1515         struct cpsw_slave *slave = &cpsw->slaves[cpsw->data.active_slave];
1516         u32 ts_en, seq_id;
1517
1518         if (!cpsw->cpts->tx_enable && !cpsw->cpts->rx_enable) {
1519                 slave_write(slave, 0, CPSW1_TS_CTL);
1520                 return;
1521         }
1522
1523         seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1524         ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1525
1526         if (cpsw->cpts->tx_enable)
1527                 ts_en |= CPSW_V1_TS_TX_EN;
1528
1529         if (cpsw->cpts->rx_enable)
1530                 ts_en |= CPSW_V1_TS_RX_EN;
1531
1532         slave_write(slave, ts_en, CPSW1_TS_CTL);
1533         slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1534 }
1535
1536 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1537 {
1538         struct cpsw_slave *slave;
1539         struct cpsw_common *cpsw = priv->cpsw;
1540         u32 ctrl, mtype;
1541
1542         if (cpsw->data.dual_emac)
1543                 slave = &cpsw->slaves[priv->emac_port];
1544         else
1545                 slave = &cpsw->slaves[cpsw->data.active_slave];
1546
1547         ctrl = slave_read(slave, CPSW2_CONTROL);
1548         switch (cpsw->version) {
1549         case CPSW_VERSION_2:
1550                 ctrl &= ~CTRL_V2_ALL_TS_MASK;
1551
1552                 if (cpsw->cpts->tx_enable)
1553                         ctrl |= CTRL_V2_TX_TS_BITS;
1554
1555                 if (cpsw->cpts->rx_enable)
1556                         ctrl |= CTRL_V2_RX_TS_BITS;
1557                 break;
1558         case CPSW_VERSION_3:
1559         default:
1560                 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1561
1562                 if (cpsw->cpts->tx_enable)
1563                         ctrl |= CTRL_V3_TX_TS_BITS;
1564
1565                 if (cpsw->cpts->rx_enable)
1566                         ctrl |= CTRL_V3_RX_TS_BITS;
1567                 break;
1568         }
1569
1570         mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1571
1572         slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1573         slave_write(slave, ctrl, CPSW2_CONTROL);
1574         __raw_writel(ETH_P_1588, &cpsw->regs->ts_ltype);
1575 }
1576
1577 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1578 {
1579         struct cpsw_priv *priv = netdev_priv(dev);
1580         struct hwtstamp_config cfg;
1581         struct cpsw_common *cpsw = priv->cpsw;
1582         struct cpts *cpts = cpsw->cpts;
1583
1584         if (cpsw->version != CPSW_VERSION_1 &&
1585             cpsw->version != CPSW_VERSION_2 &&
1586             cpsw->version != CPSW_VERSION_3)
1587                 return -EOPNOTSUPP;
1588
1589         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1590                 return -EFAULT;
1591
1592         /* reserved for future extensions */
1593         if (cfg.flags)
1594                 return -EINVAL;
1595
1596         if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
1597                 return -ERANGE;
1598
1599         switch (cfg.rx_filter) {
1600         case HWTSTAMP_FILTER_NONE:
1601                 cpts->rx_enable = 0;
1602                 break;
1603         case HWTSTAMP_FILTER_ALL:
1604         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1605         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1606         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1607                 return -ERANGE;
1608         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1609         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1610         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1611         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1612         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1613         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1614         case HWTSTAMP_FILTER_PTP_V2_EVENT:
1615         case HWTSTAMP_FILTER_PTP_V2_SYNC:
1616         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1617                 cpts->rx_enable = 1;
1618                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1619                 break;
1620         default:
1621                 return -ERANGE;
1622         }
1623
1624         cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;
1625
1626         switch (cpsw->version) {
1627         case CPSW_VERSION_1:
1628                 cpsw_hwtstamp_v1(cpsw);
1629                 break;
1630         case CPSW_VERSION_2:
1631         case CPSW_VERSION_3:
1632                 cpsw_hwtstamp_v2(priv);
1633                 break;
1634         default:
1635                 WARN_ON(1);
1636         }
1637
1638         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1639 }
1640
1641 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1642 {
1643         struct cpsw_common *cpsw = ndev_to_cpsw(dev);
1644         struct cpts *cpts = cpsw->cpts;
1645         struct hwtstamp_config cfg;
1646
1647         if (cpsw->version != CPSW_VERSION_1 &&
1648             cpsw->version != CPSW_VERSION_2 &&
1649             cpsw->version != CPSW_VERSION_3)
1650                 return -EOPNOTSUPP;
1651
1652         cfg.flags = 0;
1653         cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1654         cfg.rx_filter = (cpts->rx_enable ?
1655                          HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1656
1657         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1658 }
1659
1660 #endif /*CONFIG_TI_CPTS*/
1661
1662 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1663 {
1664         struct cpsw_priv *priv = netdev_priv(dev);
1665         struct cpsw_common *cpsw = priv->cpsw;
1666         int slave_no = cpsw_slave_index(cpsw, priv);
1667
1668         if (!netif_running(dev))
1669                 return -EINVAL;
1670
1671         switch (cmd) {
1672 #ifdef CONFIG_TI_CPTS
1673         case SIOCSHWTSTAMP:
1674                 return cpsw_hwtstamp_set(dev, req);
1675         case SIOCGHWTSTAMP:
1676                 return cpsw_hwtstamp_get(dev, req);
1677 #endif
1678         }
1679
1680         if (!cpsw->slaves[slave_no].phy)
1681                 return -EOPNOTSUPP;
1682         return phy_mii_ioctl(cpsw->slaves[slave_no].phy, req, cmd);
1683 }
1684
1685 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1686 {
1687         struct cpsw_priv *priv = netdev_priv(ndev);
1688         struct cpsw_common *cpsw = priv->cpsw;
1689         int ch;
1690
1691         cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1692         ndev->stats.tx_errors++;
1693         cpsw_intr_disable(cpsw);
1694         for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
1695                 cpdma_chan_stop(cpsw->txch[ch]);
1696                 cpdma_chan_start(cpsw->txch[ch]);
1697         }
1698
1699         cpsw_intr_enable(cpsw);
1700 }
1701
1702 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1703 {
1704         struct cpsw_priv *priv = netdev_priv(ndev);
1705         struct sockaddr *addr = (struct sockaddr *)p;
1706         struct cpsw_common *cpsw = priv->cpsw;
1707         int flags = 0;
1708         u16 vid = 0;
1709         int ret;
1710
1711         if (!is_valid_ether_addr(addr->sa_data))
1712                 return -EADDRNOTAVAIL;
1713
1714         ret = pm_runtime_get_sync(cpsw->dev);
1715         if (ret < 0) {
1716                 pm_runtime_put_noidle(cpsw->dev);
1717                 return ret;
1718         }
1719
1720         if (cpsw->data.dual_emac) {
1721                 vid = cpsw->slaves[priv->emac_port].port_vlan;
1722                 flags = ALE_VLAN;
1723         }
1724
1725         cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
1726                            flags, vid);
1727         cpsw_ale_add_ucast(cpsw->ale, addr->sa_data, HOST_PORT_NUM,
1728                            flags, vid);
1729
1730         memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1731         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1732         for_each_slave(priv, cpsw_set_slave_mac, priv);
1733
1734         pm_runtime_put(cpsw->dev);
1735
1736         return 0;
1737 }
1738
1739 #ifdef CONFIG_NET_POLL_CONTROLLER
1740 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1741 {
1742         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1743
1744         cpsw_intr_disable(cpsw);
1745         cpsw_rx_interrupt(cpsw->irqs_table[0], cpsw);
1746         cpsw_tx_interrupt(cpsw->irqs_table[1], cpsw);
1747         cpsw_intr_enable(cpsw);
1748 }
1749 #endif
1750
1751 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1752                                 unsigned short vid)
1753 {
1754         int ret;
1755         int unreg_mcast_mask = 0;
1756         u32 port_mask;
1757         struct cpsw_common *cpsw = priv->cpsw;
1758
1759         if (cpsw->data.dual_emac) {
1760                 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
1761
1762                 if (priv->ndev->flags & IFF_ALLMULTI)
1763                         unreg_mcast_mask = port_mask;
1764         } else {
1765                 port_mask = ALE_ALL_PORTS;
1766
1767                 if (priv->ndev->flags & IFF_ALLMULTI)
1768                         unreg_mcast_mask = ALE_ALL_PORTS;
1769                 else
1770                         unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1771         }
1772
1773         ret = cpsw_ale_add_vlan(cpsw->ale, vid, port_mask, 0, port_mask,
1774                                 unreg_mcast_mask);
1775         if (ret != 0)
1776                 return ret;
1777
1778         ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
1779                                  HOST_PORT_NUM, ALE_VLAN, vid);
1780         if (ret != 0)
1781                 goto clean_vid;
1782
1783         ret = cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1784                                  port_mask, ALE_VLAN, vid, 0);
1785         if (ret != 0)
1786                 goto clean_vlan_ucast;
1787         return 0;
1788
1789 clean_vlan_ucast:
1790         cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
1791                            HOST_PORT_NUM, ALE_VLAN, vid);
1792 clean_vid:
1793         cpsw_ale_del_vlan(cpsw->ale, vid, 0);
1794         return ret;
1795 }
1796
1797 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1798                                     __be16 proto, u16 vid)
1799 {
1800         struct cpsw_priv *priv = netdev_priv(ndev);
1801         struct cpsw_common *cpsw = priv->cpsw;
1802         int ret;
1803
1804         if (vid == cpsw->data.default_vlan)
1805                 return 0;
1806
1807         ret = pm_runtime_get_sync(cpsw->dev);
1808         if (ret < 0) {
1809                 pm_runtime_put_noidle(cpsw->dev);
1810                 return ret;
1811         }
1812
1813         if (cpsw->data.dual_emac) {
1814                 /* In dual EMAC, reserved VLAN id should not be used for
1815                  * creating VLAN interfaces as this can break the dual
1816                  * EMAC port separation
1817                  */
1818                 int i;
1819
1820                 for (i = 0; i < cpsw->data.slaves; i++) {
1821                         if (vid == cpsw->slaves[i].port_vlan)
1822                                 return -EINVAL;
1823                 }
1824         }
1825
1826         dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1827         ret = cpsw_add_vlan_ale_entry(priv, vid);
1828
1829         pm_runtime_put(cpsw->dev);
1830         return ret;
1831 }
1832
1833 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1834                                      __be16 proto, u16 vid)
1835 {
1836         struct cpsw_priv *priv = netdev_priv(ndev);
1837         struct cpsw_common *cpsw = priv->cpsw;
1838         int ret;
1839
1840         if (vid == cpsw->data.default_vlan)
1841                 return 0;
1842
1843         ret = pm_runtime_get_sync(cpsw->dev);
1844         if (ret < 0) {
1845                 pm_runtime_put_noidle(cpsw->dev);
1846                 return ret;
1847         }
1848
1849         if (cpsw->data.dual_emac) {
1850                 int i;
1851
1852                 for (i = 0; i < cpsw->data.slaves; i++) {
1853                         if (vid == cpsw->slaves[i].port_vlan)
1854                                 return -EINVAL;
1855                 }
1856         }
1857
1858         dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1859         ret = cpsw_ale_del_vlan(cpsw->ale, vid, 0);
1860         if (ret != 0)
1861                 return ret;
1862
1863         ret = cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
1864                                  HOST_PORT_NUM, ALE_VLAN, vid);
1865         if (ret != 0)
1866                 return ret;
1867
1868         ret = cpsw_ale_del_mcast(cpsw->ale, priv->ndev->broadcast,
1869                                  0, ALE_VLAN, vid);
1870         pm_runtime_put(cpsw->dev);
1871         return ret;
1872 }
1873
1874 static const struct net_device_ops cpsw_netdev_ops = {
1875         .ndo_open               = cpsw_ndo_open,
1876         .ndo_stop               = cpsw_ndo_stop,
1877         .ndo_start_xmit         = cpsw_ndo_start_xmit,
1878         .ndo_set_mac_address    = cpsw_ndo_set_mac_address,
1879         .ndo_do_ioctl           = cpsw_ndo_ioctl,
1880         .ndo_validate_addr      = eth_validate_addr,
1881         .ndo_change_mtu         = eth_change_mtu,
1882         .ndo_tx_timeout         = cpsw_ndo_tx_timeout,
1883         .ndo_set_rx_mode        = cpsw_ndo_set_rx_mode,
1884 #ifdef CONFIG_NET_POLL_CONTROLLER
1885         .ndo_poll_controller    = cpsw_ndo_poll_controller,
1886 #endif
1887         .ndo_vlan_rx_add_vid    = cpsw_ndo_vlan_rx_add_vid,
1888         .ndo_vlan_rx_kill_vid   = cpsw_ndo_vlan_rx_kill_vid,
1889 };
1890
1891 static int cpsw_get_regs_len(struct net_device *ndev)
1892 {
1893         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1894
1895         return cpsw->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
1896 }
1897
1898 static void cpsw_get_regs(struct net_device *ndev,
1899                           struct ethtool_regs *regs, void *p)
1900 {
1901         u32 *reg = p;
1902         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1903
1904         /* update CPSW IP version */
1905         regs->version = cpsw->version;
1906
1907         cpsw_ale_dump(cpsw->ale, reg);
1908 }
1909
1910 static void cpsw_get_drvinfo(struct net_device *ndev,
1911                              struct ethtool_drvinfo *info)
1912 {
1913         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1914         struct platform_device  *pdev = to_platform_device(cpsw->dev);
1915
1916         strlcpy(info->driver, "cpsw", sizeof(info->driver));
1917         strlcpy(info->version, "1.0", sizeof(info->version));
1918         strlcpy(info->bus_info, pdev->name, sizeof(info->bus_info));
1919 }
1920
1921 static u32 cpsw_get_msglevel(struct net_device *ndev)
1922 {
1923         struct cpsw_priv *priv = netdev_priv(ndev);
1924         return priv->msg_enable;
1925 }
1926
1927 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1928 {
1929         struct cpsw_priv *priv = netdev_priv(ndev);
1930         priv->msg_enable = value;
1931 }
1932
1933 static int cpsw_get_ts_info(struct net_device *ndev,
1934                             struct ethtool_ts_info *info)
1935 {
1936 #ifdef CONFIG_TI_CPTS
1937         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1938
1939         info->so_timestamping =
1940                 SOF_TIMESTAMPING_TX_HARDWARE |
1941                 SOF_TIMESTAMPING_TX_SOFTWARE |
1942                 SOF_TIMESTAMPING_RX_HARDWARE |
1943                 SOF_TIMESTAMPING_RX_SOFTWARE |
1944                 SOF_TIMESTAMPING_SOFTWARE |
1945                 SOF_TIMESTAMPING_RAW_HARDWARE;
1946         info->phc_index = cpsw->cpts->phc_index;
1947         info->tx_types =
1948                 (1 << HWTSTAMP_TX_OFF) |
1949                 (1 << HWTSTAMP_TX_ON);
1950         info->rx_filters =
1951                 (1 << HWTSTAMP_FILTER_NONE) |
1952                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1953 #else
1954         info->so_timestamping =
1955                 SOF_TIMESTAMPING_TX_SOFTWARE |
1956                 SOF_TIMESTAMPING_RX_SOFTWARE |
1957                 SOF_TIMESTAMPING_SOFTWARE;
1958         info->phc_index = -1;
1959         info->tx_types = 0;
1960         info->rx_filters = 0;
1961 #endif
1962         return 0;
1963 }
1964
1965 static int cpsw_get_settings(struct net_device *ndev,
1966                              struct ethtool_cmd *ecmd)
1967 {
1968         struct cpsw_priv *priv = netdev_priv(ndev);
1969         struct cpsw_common *cpsw = priv->cpsw;
1970         int slave_no = cpsw_slave_index(cpsw, priv);
1971
1972         if (cpsw->slaves[slave_no].phy)
1973                 return phy_ethtool_gset(cpsw->slaves[slave_no].phy, ecmd);
1974         else
1975                 return -EOPNOTSUPP;
1976 }
1977
1978 static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1979 {
1980         struct cpsw_priv *priv = netdev_priv(ndev);
1981         struct cpsw_common *cpsw = priv->cpsw;
1982         int slave_no = cpsw_slave_index(cpsw, priv);
1983
1984         if (cpsw->slaves[slave_no].phy)
1985                 return phy_ethtool_sset(cpsw->slaves[slave_no].phy, ecmd);
1986         else
1987                 return -EOPNOTSUPP;
1988 }
1989
1990 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1991 {
1992         struct cpsw_priv *priv = netdev_priv(ndev);
1993         struct cpsw_common *cpsw = priv->cpsw;
1994         int slave_no = cpsw_slave_index(cpsw, priv);
1995
1996         wol->supported = 0;
1997         wol->wolopts = 0;
1998
1999         if (cpsw->slaves[slave_no].phy)
2000                 phy_ethtool_get_wol(cpsw->slaves[slave_no].phy, wol);
2001 }
2002
2003 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2004 {
2005         struct cpsw_priv *priv = netdev_priv(ndev);
2006         struct cpsw_common *cpsw = priv->cpsw;
2007         int slave_no = cpsw_slave_index(cpsw, priv);
2008
2009         if (cpsw->slaves[slave_no].phy)
2010                 return phy_ethtool_set_wol(cpsw->slaves[slave_no].phy, wol);
2011         else
2012                 return -EOPNOTSUPP;
2013 }
2014
2015 static void cpsw_get_pauseparam(struct net_device *ndev,
2016                                 struct ethtool_pauseparam *pause)
2017 {
2018         struct cpsw_priv *priv = netdev_priv(ndev);
2019
2020         pause->autoneg = AUTONEG_DISABLE;
2021         pause->rx_pause = priv->rx_pause ? true : false;
2022         pause->tx_pause = priv->tx_pause ? true : false;
2023 }
2024
2025 static int cpsw_set_pauseparam(struct net_device *ndev,
2026                                struct ethtool_pauseparam *pause)
2027 {
2028         struct cpsw_priv *priv = netdev_priv(ndev);
2029         bool link;
2030
2031         priv->rx_pause = pause->rx_pause ? true : false;
2032         priv->tx_pause = pause->tx_pause ? true : false;
2033
2034         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
2035         return 0;
2036 }
2037
2038 static int cpsw_ethtool_op_begin(struct net_device *ndev)
2039 {
2040         struct cpsw_priv *priv = netdev_priv(ndev);
2041         struct cpsw_common *cpsw = priv->cpsw;
2042         int ret;
2043
2044         ret = pm_runtime_get_sync(cpsw->dev);
2045         if (ret < 0) {
2046                 cpsw_err(priv, drv, "ethtool begin failed %d\n", ret);
2047                 pm_runtime_put_noidle(cpsw->dev);
2048         }
2049
2050         return ret;
2051 }
2052
2053 static void cpsw_ethtool_op_complete(struct net_device *ndev)
2054 {
2055         struct cpsw_priv *priv = netdev_priv(ndev);
2056         int ret;
2057
2058         ret = pm_runtime_put(priv->cpsw->dev);
2059         if (ret < 0)
2060                 cpsw_err(priv, drv, "ethtool complete failed %d\n", ret);
2061 }
2062
2063 static const struct ethtool_ops cpsw_ethtool_ops = {
2064         .get_drvinfo    = cpsw_get_drvinfo,
2065         .get_msglevel   = cpsw_get_msglevel,
2066         .set_msglevel   = cpsw_set_msglevel,
2067         .get_link       = ethtool_op_get_link,
2068         .get_ts_info    = cpsw_get_ts_info,
2069         .get_settings   = cpsw_get_settings,
2070         .set_settings   = cpsw_set_settings,
2071         .get_coalesce   = cpsw_get_coalesce,
2072         .set_coalesce   = cpsw_set_coalesce,
2073         .get_sset_count         = cpsw_get_sset_count,
2074         .get_strings            = cpsw_get_strings,
2075         .get_ethtool_stats      = cpsw_get_ethtool_stats,
2076         .get_pauseparam         = cpsw_get_pauseparam,
2077         .set_pauseparam         = cpsw_set_pauseparam,
2078         .get_wol        = cpsw_get_wol,
2079         .set_wol        = cpsw_set_wol,
2080         .get_regs_len   = cpsw_get_regs_len,
2081         .get_regs       = cpsw_get_regs,
2082         .begin          = cpsw_ethtool_op_begin,
2083         .complete       = cpsw_ethtool_op_complete,
2084 };
2085
2086 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_common *cpsw,
2087                             u32 slave_reg_ofs, u32 sliver_reg_ofs)
2088 {
2089         void __iomem            *regs = cpsw->regs;
2090         int                     slave_num = slave->slave_num;
2091         struct cpsw_slave_data  *data = cpsw->data.slave_data + slave_num;
2092
2093         slave->data     = data;
2094         slave->regs     = regs + slave_reg_ofs;
2095         slave->sliver   = regs + sliver_reg_ofs;
2096         slave->port_vlan = data->dual_emac_res_vlan;
2097 }
2098
2099 static int cpsw_probe_dt(struct cpsw_platform_data *data,
2100                          struct platform_device *pdev)
2101 {
2102         struct device_node *node = pdev->dev.of_node;
2103         struct device_node *slave_node;
2104         int i = 0, ret;
2105         u32 prop;
2106
2107         if (!node)
2108                 return -EINVAL;
2109
2110         if (of_property_read_u32(node, "slaves", &prop)) {
2111                 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
2112                 return -EINVAL;
2113         }
2114         data->slaves = prop;
2115
2116         if (of_property_read_u32(node, "active_slave", &prop)) {
2117                 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
2118                 return -EINVAL;
2119         }
2120         data->active_slave = prop;
2121
2122         if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
2123                 dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n");
2124                 return -EINVAL;
2125         }
2126         data->cpts_clock_mult = prop;
2127
2128         if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
2129                 dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n");
2130                 return -EINVAL;
2131         }
2132         data->cpts_clock_shift = prop;
2133
2134         data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
2135                                         * sizeof(struct cpsw_slave_data),
2136                                         GFP_KERNEL);
2137         if (!data->slave_data)
2138                 return -ENOMEM;
2139
2140         if (of_property_read_u32(node, "cpdma_channels", &prop)) {
2141                 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
2142                 return -EINVAL;
2143         }
2144         data->channels = prop;
2145
2146         if (of_property_read_u32(node, "ale_entries", &prop)) {
2147                 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
2148                 return -EINVAL;
2149         }
2150         data->ale_entries = prop;
2151
2152         if (of_property_read_u32(node, "bd_ram_size", &prop)) {
2153                 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
2154                 return -EINVAL;
2155         }
2156         data->bd_ram_size = prop;
2157
2158         if (of_property_read_u32(node, "mac_control", &prop)) {
2159                 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
2160                 return -EINVAL;
2161         }
2162         data->mac_control = prop;
2163
2164         if (of_property_read_bool(node, "dual_emac"))
2165                 data->dual_emac = 1;
2166
2167         /*
2168          * Populate all the child nodes here...
2169          */
2170         ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2171         /* We do not want to force this, as in some cases may not have child */
2172         if (ret)
2173                 dev_warn(&pdev->dev, "Doesn't have any child node\n");
2174
2175         for_each_available_child_of_node(node, slave_node) {
2176                 struct cpsw_slave_data *slave_data = data->slave_data + i;
2177                 const void *mac_addr = NULL;
2178                 int lenp;
2179                 const __be32 *parp;
2180
2181                 /* This is no slave child node, continue */
2182                 if (strcmp(slave_node->name, "slave"))
2183                         continue;
2184
2185                 slave_data->phy_node = of_parse_phandle(slave_node,
2186                                                         "phy-handle", 0);
2187                 parp = of_get_property(slave_node, "phy_id", &lenp);
2188                 if (slave_data->phy_node) {
2189                         dev_dbg(&pdev->dev,
2190                                 "slave[%d] using phy-handle=\"%s\"\n",
2191                                 i, slave_data->phy_node->full_name);
2192                 } else if (of_phy_is_fixed_link(slave_node)) {
2193                         /* In the case of a fixed PHY, the DT node associated
2194                          * to the PHY is the Ethernet MAC DT node.
2195                          */
2196                         ret = of_phy_register_fixed_link(slave_node);
2197                         if (ret)
2198                                 return ret;
2199                         slave_data->phy_node = of_node_get(slave_node);
2200                 } else if (parp) {
2201                         u32 phyid;
2202                         struct device_node *mdio_node;
2203                         struct platform_device *mdio;
2204
2205                         if (lenp != (sizeof(__be32) * 2)) {
2206                                 dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i);
2207                                 goto no_phy_slave;
2208                         }
2209                         mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2210                         phyid = be32_to_cpup(parp+1);
2211                         mdio = of_find_device_by_node(mdio_node);
2212                         of_node_put(mdio_node);
2213                         if (!mdio) {
2214                                 dev_err(&pdev->dev, "Missing mdio platform device\n");
2215                                 return -EINVAL;
2216                         }
2217                         snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2218                                  PHY_ID_FMT, mdio->name, phyid);
2219                 } else {
2220                         dev_err(&pdev->dev,
2221                                 "No slave[%d] phy_id, phy-handle, or fixed-link property\n",
2222                                 i);
2223                         goto no_phy_slave;
2224                 }
2225                 slave_data->phy_if = of_get_phy_mode(slave_node);
2226                 if (slave_data->phy_if < 0) {
2227                         dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2228                                 i);
2229                         return slave_data->phy_if;
2230                 }
2231
2232 no_phy_slave:
2233                 mac_addr = of_get_mac_address(slave_node);
2234                 if (mac_addr) {
2235                         memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
2236                 } else {
2237                         ret = ti_cm_get_macid(&pdev->dev, i,
2238                                               slave_data->mac_addr);
2239                         if (ret)
2240                                 return ret;
2241                 }
2242                 if (data->dual_emac) {
2243                         if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
2244                                                  &prop)) {
2245                                 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
2246                                 slave_data->dual_emac_res_vlan = i+1;
2247                                 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2248                                         slave_data->dual_emac_res_vlan, i);
2249                         } else {
2250                                 slave_data->dual_emac_res_vlan = prop;
2251                         }
2252                 }
2253
2254                 i++;
2255                 if (i == data->slaves)
2256                         break;
2257         }
2258
2259         return 0;
2260 }
2261
2262 static int cpsw_probe_dual_emac(struct cpsw_priv *priv)
2263 {
2264         struct cpsw_common              *cpsw = priv->cpsw;
2265         struct cpsw_platform_data       *data = &cpsw->data;
2266         struct net_device               *ndev;
2267         struct cpsw_priv                *priv_sl2;
2268         int ret = 0;
2269
2270         ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
2271         if (!ndev) {
2272                 dev_err(cpsw->dev, "cpsw: error allocating net_device\n");
2273                 return -ENOMEM;
2274         }
2275
2276         priv_sl2 = netdev_priv(ndev);
2277         priv_sl2->cpsw = cpsw;
2278         priv_sl2->ndev = ndev;
2279         priv_sl2->dev  = &ndev->dev;
2280         priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2281
2282         if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2283                 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2284                         ETH_ALEN);
2285                 dev_info(cpsw->dev, "cpsw: Detected MACID = %pM\n",
2286                          priv_sl2->mac_addr);
2287         } else {
2288                 random_ether_addr(priv_sl2->mac_addr);
2289                 dev_info(cpsw->dev, "cpsw: Random MACID = %pM\n",
2290                          priv_sl2->mac_addr);
2291         }
2292         memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2293
2294         priv_sl2->emac_port = 1;
2295         cpsw->slaves[1].ndev = ndev;
2296         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2297
2298         ndev->netdev_ops = &cpsw_netdev_ops;
2299         ndev->ethtool_ops = &cpsw_ethtool_ops;
2300
2301         /* register the network device */
2302         SET_NETDEV_DEV(ndev, cpsw->dev);
2303         ret = register_netdev(ndev);
2304         if (ret) {
2305                 dev_err(cpsw->dev, "cpsw: error registering net device\n");
2306                 free_netdev(ndev);
2307                 ret = -ENODEV;
2308         }
2309
2310         return ret;
2311 }
2312
2313 #define CPSW_QUIRK_IRQ          BIT(0)
2314
2315 static struct platform_device_id cpsw_devtype[] = {
2316         {
2317                 /* keep it for existing comaptibles */
2318                 .name = "cpsw",
2319                 .driver_data = CPSW_QUIRK_IRQ,
2320         }, {
2321                 .name = "am335x-cpsw",
2322                 .driver_data = CPSW_QUIRK_IRQ,
2323         }, {
2324                 .name = "am4372-cpsw",
2325                 .driver_data = 0,
2326         }, {
2327                 .name = "dra7-cpsw",
2328                 .driver_data = 0,
2329         }, {
2330                 /* sentinel */
2331         }
2332 };
2333 MODULE_DEVICE_TABLE(platform, cpsw_devtype);
2334
2335 enum ti_cpsw_type {
2336         CPSW = 0,
2337         AM335X_CPSW,
2338         AM4372_CPSW,
2339         DRA7_CPSW,
2340 };
2341
2342 static const struct of_device_id cpsw_of_mtable[] = {
2343         { .compatible = "ti,cpsw", .data = &cpsw_devtype[CPSW], },
2344         { .compatible = "ti,am335x-cpsw", .data = &cpsw_devtype[AM335X_CPSW], },
2345         { .compatible = "ti,am4372-cpsw", .data = &cpsw_devtype[AM4372_CPSW], },
2346         { .compatible = "ti,dra7-cpsw", .data = &cpsw_devtype[DRA7_CPSW], },
2347         { /* sentinel */ },
2348 };
2349 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2350
2351 static int cpsw_probe(struct platform_device *pdev)
2352 {
2353         struct clk                      *clk;
2354         struct cpsw_platform_data       *data;
2355         struct net_device               *ndev;
2356         struct cpsw_priv                *priv;
2357         struct cpdma_params             dma_params;
2358         struct cpsw_ale_params          ale_params;
2359         void __iomem                    *ss_regs;
2360         struct resource                 *res, *ss_res;
2361         const struct of_device_id       *of_id;
2362         struct gpio_descs               *mode;
2363         u32 slave_offset, sliver_offset, slave_size;
2364         struct cpsw_common              *cpsw;
2365         int ret = 0, i;
2366         int irq;
2367
2368         cpsw = devm_kzalloc(&pdev->dev, sizeof(struct cpsw_common), GFP_KERNEL);
2369         cpsw->dev = &pdev->dev;
2370
2371         ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
2372         if (!ndev) {
2373                 dev_err(&pdev->dev, "error allocating net_device\n");
2374                 return -ENOMEM;
2375         }
2376
2377         platform_set_drvdata(pdev, ndev);
2378         priv = netdev_priv(ndev);
2379         priv->cpsw = cpsw;
2380         priv->ndev = ndev;
2381         priv->dev  = &ndev->dev;
2382         priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2383         cpsw->rx_packet_max = max(rx_packet_max, 128);
2384         cpsw->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
2385         if (!cpsw->cpts) {
2386                 dev_err(&pdev->dev, "error allocating cpts\n");
2387                 ret = -ENOMEM;
2388                 goto clean_ndev_ret;
2389         }
2390
2391         mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW);
2392         if (IS_ERR(mode)) {
2393                 ret = PTR_ERR(mode);
2394                 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
2395                 goto clean_ndev_ret;
2396         }
2397
2398         /*
2399          * This may be required here for child devices.
2400          */
2401         pm_runtime_enable(&pdev->dev);
2402
2403         /* Select default pin state */
2404         pinctrl_pm_select_default_state(&pdev->dev);
2405
2406         if (cpsw_probe_dt(&cpsw->data, pdev)) {
2407                 dev_err(&pdev->dev, "cpsw: platform data missing\n");
2408                 ret = -ENODEV;
2409                 goto clean_runtime_disable_ret;
2410         }
2411         data = &cpsw->data;
2412         cpsw->rx_ch_num = 1;
2413         cpsw->tx_ch_num = 1;
2414
2415         if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2416                 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
2417                 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
2418         } else {
2419                 eth_random_addr(priv->mac_addr);
2420                 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
2421         }
2422
2423         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2424
2425         cpsw->slaves = devm_kzalloc(&pdev->dev,
2426                                     sizeof(struct cpsw_slave) * data->slaves,
2427                                     GFP_KERNEL);
2428         if (!cpsw->slaves) {
2429                 ret = -ENOMEM;
2430                 goto clean_runtime_disable_ret;
2431         }
2432         for (i = 0; i < data->slaves; i++)
2433                 cpsw->slaves[i].slave_num = i;
2434
2435         cpsw->slaves[0].ndev = ndev;
2436         priv->emac_port = 0;
2437
2438         clk = devm_clk_get(&pdev->dev, "fck");
2439         if (IS_ERR(clk)) {
2440                 dev_err(priv->dev, "fck is not found\n");
2441                 ret = -ENODEV;
2442                 goto clean_runtime_disable_ret;
2443         }
2444         cpsw->bus_freq_mhz = clk_get_rate(clk) / 1000000;
2445
2446         ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2447         ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2448         if (IS_ERR(ss_regs)) {
2449                 ret = PTR_ERR(ss_regs);
2450                 goto clean_runtime_disable_ret;
2451         }
2452         cpsw->regs = ss_regs;
2453
2454         /* Need to enable clocks with runtime PM api to access module
2455          * registers
2456          */
2457         ret = pm_runtime_get_sync(&pdev->dev);
2458         if (ret < 0) {
2459                 pm_runtime_put_noidle(&pdev->dev);
2460                 goto clean_runtime_disable_ret;
2461         }
2462         cpsw->version = readl(&cpsw->regs->id_ver);
2463         pm_runtime_put_sync(&pdev->dev);
2464
2465         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2466         cpsw->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2467         if (IS_ERR(cpsw->wr_regs)) {
2468                 ret = PTR_ERR(cpsw->wr_regs);
2469                 goto clean_runtime_disable_ret;
2470         }
2471
2472         memset(&dma_params, 0, sizeof(dma_params));
2473         memset(&ale_params, 0, sizeof(ale_params));
2474
2475         switch (cpsw->version) {
2476         case CPSW_VERSION_1:
2477                 cpsw->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
2478                 cpsw->cpts->reg      = ss_regs + CPSW1_CPTS_OFFSET;
2479                 cpsw->hw_stats       = ss_regs + CPSW1_HW_STATS;
2480                 dma_params.dmaregs   = ss_regs + CPSW1_CPDMA_OFFSET;
2481                 dma_params.txhdp     = ss_regs + CPSW1_STATERAM_OFFSET;
2482                 ale_params.ale_regs  = ss_regs + CPSW1_ALE_OFFSET;
2483                 slave_offset         = CPSW1_SLAVE_OFFSET;
2484                 slave_size           = CPSW1_SLAVE_SIZE;
2485                 sliver_offset        = CPSW1_SLIVER_OFFSET;
2486                 dma_params.desc_mem_phys = 0;
2487                 break;
2488         case CPSW_VERSION_2:
2489         case CPSW_VERSION_3:
2490         case CPSW_VERSION_4:
2491                 cpsw->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
2492                 cpsw->cpts->reg      = ss_regs + CPSW2_CPTS_OFFSET;
2493                 cpsw->hw_stats       = ss_regs + CPSW2_HW_STATS;
2494                 dma_params.dmaregs   = ss_regs + CPSW2_CPDMA_OFFSET;
2495                 dma_params.txhdp     = ss_regs + CPSW2_STATERAM_OFFSET;
2496                 ale_params.ale_regs  = ss_regs + CPSW2_ALE_OFFSET;
2497                 slave_offset         = CPSW2_SLAVE_OFFSET;
2498                 slave_size           = CPSW2_SLAVE_SIZE;
2499                 sliver_offset        = CPSW2_SLIVER_OFFSET;
2500                 dma_params.desc_mem_phys =
2501                         (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
2502                 break;
2503         default:
2504                 dev_err(priv->dev, "unknown version 0x%08x\n", cpsw->version);
2505                 ret = -ENODEV;
2506                 goto clean_runtime_disable_ret;
2507         }
2508         for (i = 0; i < cpsw->data.slaves; i++) {
2509                 struct cpsw_slave *slave = &cpsw->slaves[i];
2510
2511                 cpsw_slave_init(slave, cpsw, slave_offset, sliver_offset);
2512                 slave_offset  += slave_size;
2513                 sliver_offset += SLIVER_SIZE;
2514         }
2515
2516         dma_params.dev          = &pdev->dev;
2517         dma_params.rxthresh     = dma_params.dmaregs + CPDMA_RXTHRESH;
2518         dma_params.rxfree       = dma_params.dmaregs + CPDMA_RXFREE;
2519         dma_params.rxhdp        = dma_params.txhdp + CPDMA_RXHDP;
2520         dma_params.txcp         = dma_params.txhdp + CPDMA_TXCP;
2521         dma_params.rxcp         = dma_params.txhdp + CPDMA_RXCP;
2522
2523         dma_params.num_chan             = data->channels;
2524         dma_params.has_soft_reset       = true;
2525         dma_params.min_packet_size      = CPSW_MIN_PACKET_SIZE;
2526         dma_params.desc_mem_size        = data->bd_ram_size;
2527         dma_params.desc_align           = 16;
2528         dma_params.has_ext_regs         = true;
2529         dma_params.desc_hw_addr         = dma_params.desc_mem_phys;
2530
2531         cpsw->dma = cpdma_ctlr_create(&dma_params);
2532         if (!cpsw->dma) {
2533                 dev_err(priv->dev, "error initializing dma\n");
2534                 ret = -ENOMEM;
2535                 goto clean_runtime_disable_ret;
2536         }
2537
2538         cpsw->txch[0] = cpdma_chan_create(cpsw->dma, tx_chan_num(0),
2539                                           cpsw_tx_handler);
2540         cpsw->rxch[0] = cpdma_chan_create(cpsw->dma, rx_chan_num(0),
2541                                           cpsw_rx_handler);
2542
2543         if (WARN_ON(!cpsw->rxch[0] || !cpsw->txch[0])) {
2544                 dev_err(priv->dev, "error initializing dma channels\n");
2545                 ret = -ENOMEM;
2546                 goto clean_dma_ret;
2547         }
2548
2549         ale_params.dev                  = &ndev->dev;
2550         ale_params.ale_ageout           = ale_ageout;
2551         ale_params.ale_entries          = data->ale_entries;
2552         ale_params.ale_ports            = data->slaves;
2553
2554         cpsw->ale = cpsw_ale_create(&ale_params);
2555         if (!cpsw->ale) {
2556                 dev_err(priv->dev, "error initializing ale engine\n");
2557                 ret = -ENODEV;
2558                 goto clean_dma_ret;
2559         }
2560
2561         ndev->irq = platform_get_irq(pdev, 1);
2562         if (ndev->irq < 0) {
2563                 dev_err(priv->dev, "error getting irq resource\n");
2564                 ret = ndev->irq;
2565                 goto clean_ale_ret;
2566         }
2567
2568         of_id = of_match_device(cpsw_of_mtable, &pdev->dev);
2569         if (of_id) {
2570                 pdev->id_entry = of_id->data;
2571                 if (pdev->id_entry->driver_data)
2572                         cpsw->quirk_irq = true;
2573         }
2574
2575         /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
2576          * MISC IRQs which are always kept disabled with this driver so
2577          * we will not request them.
2578          *
2579          * If anyone wants to implement support for those, make sure to
2580          * first request and append them to irqs_table array.
2581          */
2582
2583         /* RX IRQ */
2584         irq = platform_get_irq(pdev, 1);
2585         if (irq < 0) {
2586                 ret = irq;
2587                 goto clean_ale_ret;
2588         }
2589
2590         cpsw->irqs_table[0] = irq;
2591         ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
2592                                0, dev_name(&pdev->dev), cpsw);
2593         if (ret < 0) {
2594                 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2595                 goto clean_ale_ret;
2596         }
2597
2598         /* TX IRQ */
2599         irq = platform_get_irq(pdev, 2);
2600         if (irq < 0) {
2601                 ret = irq;
2602                 goto clean_ale_ret;
2603         }
2604
2605         cpsw->irqs_table[1] = irq;
2606         ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
2607                                0, dev_name(&pdev->dev), cpsw);
2608         if (ret < 0) {
2609                 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2610                 goto clean_ale_ret;
2611         }
2612
2613         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2614
2615         ndev->netdev_ops = &cpsw_netdev_ops;
2616         ndev->ethtool_ops = &cpsw_ethtool_ops;
2617         netif_napi_add(ndev, &cpsw->napi_rx, cpsw_rx_poll, CPSW_POLL_WEIGHT);
2618         netif_tx_napi_add(ndev, &cpsw->napi_tx, cpsw_tx_poll, CPSW_POLL_WEIGHT);
2619
2620         /* register the network device */
2621         SET_NETDEV_DEV(ndev, &pdev->dev);
2622         ret = register_netdev(ndev);
2623         if (ret) {
2624                 dev_err(priv->dev, "error registering net device\n");
2625                 ret = -ENODEV;
2626                 goto clean_ale_ret;
2627         }
2628
2629         cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
2630                     &ss_res->start, ndev->irq);
2631
2632         if (cpsw->data.dual_emac) {
2633                 ret = cpsw_probe_dual_emac(priv);
2634                 if (ret) {
2635                         cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
2636                         goto clean_ale_ret;
2637                 }
2638         }
2639
2640         return 0;
2641
2642 clean_ale_ret:
2643         cpsw_ale_destroy(cpsw->ale);
2644 clean_dma_ret:
2645         cpdma_ctlr_destroy(cpsw->dma);
2646 clean_runtime_disable_ret:
2647         pm_runtime_disable(&pdev->dev);
2648 clean_ndev_ret:
2649         free_netdev(priv->ndev);
2650         return ret;
2651 }
2652
2653 static int cpsw_remove(struct platform_device *pdev)
2654 {
2655         struct net_device *ndev = platform_get_drvdata(pdev);
2656         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2657         int ret;
2658
2659         ret = pm_runtime_get_sync(&pdev->dev);
2660         if (ret < 0) {
2661                 pm_runtime_put_noidle(&pdev->dev);
2662                 return ret;
2663         }
2664
2665         if (cpsw->data.dual_emac)
2666                 unregister_netdev(cpsw->slaves[1].ndev);
2667         unregister_netdev(ndev);
2668
2669         cpsw_ale_destroy(cpsw->ale);
2670         cpdma_ctlr_destroy(cpsw->dma);
2671         of_platform_depopulate(&pdev->dev);
2672         pm_runtime_put_sync(&pdev->dev);
2673         pm_runtime_disable(&pdev->dev);
2674         if (cpsw->data.dual_emac)
2675                 free_netdev(cpsw->slaves[1].ndev);
2676         free_netdev(ndev);
2677         return 0;
2678 }
2679
2680 #ifdef CONFIG_PM_SLEEP
2681 static int cpsw_suspend(struct device *dev)
2682 {
2683         struct platform_device  *pdev = to_platform_device(dev);
2684         struct net_device       *ndev = platform_get_drvdata(pdev);
2685         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
2686
2687         if (cpsw->data.dual_emac) {
2688                 int i;
2689
2690                 for (i = 0; i < cpsw->data.slaves; i++) {
2691                         if (netif_running(cpsw->slaves[i].ndev))
2692                                 cpsw_ndo_stop(cpsw->slaves[i].ndev);
2693                 }
2694         } else {
2695                 if (netif_running(ndev))
2696                         cpsw_ndo_stop(ndev);
2697         }
2698
2699         /* Select sleep pin state */
2700         pinctrl_pm_select_sleep_state(dev);
2701
2702         return 0;
2703 }
2704
2705 static int cpsw_resume(struct device *dev)
2706 {
2707         struct platform_device  *pdev = to_platform_device(dev);
2708         struct net_device       *ndev = platform_get_drvdata(pdev);
2709         struct cpsw_common      *cpsw = netdev_priv(ndev);
2710
2711         /* Select default pin state */
2712         pinctrl_pm_select_default_state(dev);
2713
2714         if (cpsw->data.dual_emac) {
2715                 int i;
2716
2717                 for (i = 0; i < cpsw->data.slaves; i++) {
2718                         if (netif_running(cpsw->slaves[i].ndev))
2719                                 cpsw_ndo_open(cpsw->slaves[i].ndev);
2720                 }
2721         } else {
2722                 if (netif_running(ndev))
2723                         cpsw_ndo_open(ndev);
2724         }
2725         return 0;
2726 }
2727 #endif
2728
2729 static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
2730
2731 static struct platform_driver cpsw_driver = {
2732         .driver = {
2733                 .name    = "cpsw",
2734                 .pm      = &cpsw_pm_ops,
2735                 .of_match_table = cpsw_of_mtable,
2736         },
2737         .probe = cpsw_probe,
2738         .remove = cpsw_remove,
2739 };
2740
2741 module_platform_driver(cpsw_driver);
2742
2743 MODULE_LICENSE("GPL");
2744 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2745 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2746 MODULE_DESCRIPTION("TI CPSW Ethernet driver");