drivers/net/ethernet/ti/cpsw.c

   1 /*
   2  * Texas Instruments Ethernet Switch Driver
   3  *
   4  * Copyright (C) 2012 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/io.h>
  18 #include <linux/clk.h>
  19 #include <linux/timer.h>
  20 #include <linux/module.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/irqreturn.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/if_ether.h>
  25 #include <linux/etherdevice.h>
  26 #include <linux/netdevice.h>
  27 #include <linux/net_tstamp.h>
  28 #include <linux/phy.h>
  29 #include <linux/workqueue.h>
  30 #include <linux/delay.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/of.h>
  33 #include <linux/of_net.h>
  34 #include <linux/of_device.h>
  35 #include <linux/if_vlan.h>
  36
  37 #include <linux/pinctrl/consumer.h>
  38
  39 #include "cpsw.h"
  40 #include "cpsw_ale.h"
  41 #include "cpts.h"
  42 #include "davinci_cpdma.h"
  43
  44 #define CPSW_DEBUG      (NETIF_MSG_HW           | NETIF_MSG_WOL         | \
  45                          NETIF_MSG_DRV          | NETIF_MSG_LINK        | \
  46                          NETIF_MSG_IFUP         | NETIF_MSG_INTR        | \
  47                          NETIF_MSG_PROBE        | NETIF_MSG_TIMER       | \
  48                          NETIF_MSG_IFDOWN       | NETIF_MSG_RX_ERR      | \
  49                          NETIF_MSG_TX_ERR       | NETIF_MSG_TX_DONE     | \
  50                          NETIF_MSG_PKTDATA      | NETIF_MSG_TX_QUEUED   | \
  51                          NETIF_MSG_RX_STATUS)
  52
  53 #define cpsw_info(priv, type, format, ...)              \
  54 do {                                                            \
  55         if (netif_msg_##type(priv) && net_ratelimit())          \
  56                 dev_info(priv->dev, format, ## __VA_ARGS__);    \
  57 } while (0)
  58
  59 #define cpsw_err(priv, type, format, ...)               \
  60 do {                                                            \
  61         if (netif_msg_##type(priv) && net_ratelimit())          \
  62                 dev_err(priv->dev, format, ## __VA_ARGS__);     \
  63 } while (0)
  64
  65 #define cpsw_dbg(priv, type, format, ...)               \
  66 do {                                                            \
  67         if (netif_msg_##type(priv) && net_ratelimit())          \
  68                 dev_dbg(priv->dev, format, ## __VA_ARGS__);     \
  69 } while (0)
  70
  71 #define cpsw_notice(priv, type, format, ...)            \
  72 do {                                                            \
  73         if (netif_msg_##type(priv) && net_ratelimit())          \
  74                 dev_notice(priv->dev, format, ## __VA_ARGS__);  \
  75 } while (0)
  76
  77 #define ALE_ALL_PORTS           0x7
  78
  79 #define CPSW_MAJOR_VERSION(reg)         (reg >> 8 & 0x7)
  80 #define CPSW_MINOR_VERSION(reg)         (reg & 0xff)
  81 #define CPSW_RTL_VERSION(reg)           ((reg >> 11) & 0x1f)
  82
  83 #define CPSW_VERSION_1          0x19010a
  84 #define CPSW_VERSION_2          0x19010c
  85 #define CPSW_VERSION_3          0x19010f
  86 #define CPSW_VERSION_4          0x190112
  87
  88 #define HOST_PORT_NUM           0
  89 #define SLIVER_SIZE             0x40
  90
  91 #define CPSW1_HOST_PORT_OFFSET  0x028
  92 #define CPSW1_SLAVE_OFFSET      0x050
  93 #define CPSW1_SLAVE_SIZE        0x040
  94 #define CPSW1_CPDMA_OFFSET      0x100
  95 #define CPSW1_STATERAM_OFFSET   0x200
  96 #define CPSW1_HW_STATS          0x400
  97 #define CPSW1_CPTS_OFFSET       0x500
  98 #define CPSW1_ALE_OFFSET        0x600
  99 #define CPSW1_SLIVER_OFFSET     0x700
 100
 101 #define CPSW2_HOST_PORT_OFFSET  0x108
 102 #define CPSW2_SLAVE_OFFSET      0x200
 103 #define CPSW2_SLAVE_SIZE        0x100
 104 #define CPSW2_CPDMA_OFFSET      0x800
 105 #define CPSW2_HW_STATS          0x900
 106 #define CPSW2_STATERAM_OFFSET   0xa00
 107 #define CPSW2_CPTS_OFFSET       0xc00
 108 #define CPSW2_ALE_OFFSET        0xd00
 109 #define CPSW2_SLIVER_OFFSET     0xd80
 110 #define CPSW2_BD_OFFSET         0x2000
 111
 112 #define CPDMA_RXTHRESH          0x0c0
 113 #define CPDMA_RXFREE            0x0e0
 114 #define CPDMA_TXHDP             0x00
 115 #define CPDMA_RXHDP             0x20
 116 #define CPDMA_TXCP              0x40
 117 #define CPDMA_RXCP              0x60
 118
 119 #define CPSW_POLL_WEIGHT        64
 120 #define CPSW_MIN_PACKET_SIZE    60
 121 #define CPSW_MAX_PACKET_SIZE    (1500 + 14 + 4 + 4)
 122
 123 #define RX_PRIORITY_MAPPING     0x76543210
 124 #define TX_PRIORITY_MAPPING     0x33221100
 125 #define CPDMA_TX_PRIORITY_MAP   0x76543210
 126
 127 #define CPSW_VLAN_AWARE         BIT(1)
 128 #define CPSW_ALE_VLAN_AWARE     1
 129
 130 #define CPSW_FIFO_NORMAL_MODE           (0 << 16)
 131 #define CPSW_FIFO_DUAL_MAC_MODE         (1 << 16)
 132 #define CPSW_FIFO_RATE_LIMIT_MODE       (2 << 16)
 133
 134 #define CPSW_INTPACEEN          (0x3f << 16)
 135 #define CPSW_INTPRESCALE_MASK   (0x7FF << 0)
 136 #define CPSW_CMINTMAX_CNT       63
 137 #define CPSW_CMINTMIN_CNT       2
 138 #define CPSW_CMINTMAX_INTVL     (1000 / CPSW_CMINTMIN_CNT)
 139 #define CPSW_CMINTMIN_INTVL     ((1000 / CPSW_CMINTMAX_CNT) + 1)
 140
 141 #define cpsw_slave_index(priv)                          \
 142                 ((priv->data.dual_emac) ? priv->emac_port :     \
 143                 priv->data.active_slave)
 144
 145 static int debug_level;
 146 module_param(debug_level, int, 0);
 147 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
 148
 149 static int ale_ageout = 10;
 150 module_param(ale_ageout, int, 0);
 151 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
 152
 153 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
 154 module_param(rx_packet_max, int, 0);
 155 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
 156
 157 struct cpsw_wr_regs {
 158         u32     id_ver;
 159         u32     soft_reset;
 160         u32     control;
 161         u32     int_control;
 162         u32     rx_thresh_en;
 163         u32     rx_en;
 164         u32     tx_en;
 165         u32     misc_en;
 166         u32     mem_allign1[8];
 167         u32     rx_thresh_stat;
 168         u32     rx_stat;
 169         u32     tx_stat;
 170         u32     misc_stat;
 171         u32     mem_allign2[8];
 172         u32     rx_imax;
 173         u32     tx_imax;
 174
 175 };
 176
 177 struct cpsw_ss_regs {
 178         u32     id_ver;
 179         u32     control;
 180         u32     soft_reset;
 181         u32     stat_port_en;
 182         u32     ptype;
 183         u32     soft_idle;
 184         u32     thru_rate;
 185         u32     gap_thresh;
 186         u32     tx_start_wds;
 187         u32     flow_control;
 188         u32     vlan_ltype;
 189         u32     ts_ltype;
 190         u32     dlr_ltype;
 191 };
 192
 193 /* CPSW_PORT_V1 */
 194 #define CPSW1_MAX_BLKS      0x00 /* Maximum FIFO Blocks */
 195 #define CPSW1_BLK_CNT       0x04 /* FIFO Block Usage Count (Read Only) */
 196 #define CPSW1_TX_IN_CTL     0x08 /* Transmit FIFO Control */
 197 #define CPSW1_PORT_VLAN     0x0c /* VLAN Register */
 198 #define CPSW1_TX_PRI_MAP    0x10 /* Tx Header Priority to Switch Pri Mapping */
 199 #define CPSW1_TS_CTL        0x14 /* Time Sync Control */
 200 #define CPSW1_TS_SEQ_LTYPE  0x18 /* Time Sync Sequence ID Offset and Msg Type */
 201 #define CPSW1_TS_VLAN       0x1c /* Time Sync VLAN1 and VLAN2 */
 202
 203 /* CPSW_PORT_V2 */
 204 #define CPSW2_CONTROL       0x00 /* Control Register */
 205 #define CPSW2_MAX_BLKS      0x08 /* Maximum FIFO Blocks */
 206 #define CPSW2_BLK_CNT       0x0c /* FIFO Block Usage Count (Read Only) */
 207 #define CPSW2_TX_IN_CTL     0x10 /* Transmit FIFO Control */
 208 #define CPSW2_PORT_VLAN     0x14 /* VLAN Register */
 209 #define CPSW2_TX_PRI_MAP    0x18 /* Tx Header Priority to Switch Pri Mapping */
 210 #define CPSW2_TS_SEQ_MTYPE  0x1c /* Time Sync Sequence ID Offset and Msg Type */
 211
 212 /* CPSW_PORT_V1 and V2 */
 213 #define SA_LO               0x20 /* CPGMAC_SL Source Address Low */
 214 #define SA_HI               0x24 /* CPGMAC_SL Source Address High */
 215 #define SEND_PERCENT        0x28 /* Transmit Queue Send Percentages */
 216
 217 /* CPSW_PORT_V2 only */
 218 #define RX_DSCP_PRI_MAP0    0x30 /* Rx DSCP Priority to Rx Packet Mapping */
 219 #define RX_DSCP_PRI_MAP1    0x34 /* Rx DSCP Priority to Rx Packet Mapping */
 220 #define RX_DSCP_PRI_MAP2    0x38 /* Rx DSCP Priority to Rx Packet Mapping */
 221 #define RX_DSCP_PRI_MAP3    0x3c /* Rx DSCP Priority to Rx Packet Mapping */
 222 #define RX_DSCP_PRI_MAP4    0x40 /* Rx DSCP Priority to Rx Packet Mapping */
 223 #define RX_DSCP_PRI_MAP5    0x44 /* Rx DSCP Priority to Rx Packet Mapping */
 224 #define RX_DSCP_PRI_MAP6    0x48 /* Rx DSCP Priority to Rx Packet Mapping */
 225 #define RX_DSCP_PRI_MAP7    0x4c /* Rx DSCP Priority to Rx Packet Mapping */
 226
 227 /* Bit definitions for the CPSW2_CONTROL register */
 228 #define PASS_PRI_TAGGED     (1<<24) /* Pass Priority Tagged */
 229 #define VLAN_LTYPE2_EN      (1<<21) /* VLAN LTYPE 2 enable */
 230 #define VLAN_LTYPE1_EN      (1<<20) /* VLAN LTYPE 1 enable */
 231 #define DSCP_PRI_EN         (1<<16) /* DSCP Priority Enable */
 232 #define TS_320              (1<<14) /* Time Sync Dest Port 320 enable */
 233 #define TS_319              (1<<13) /* Time Sync Dest Port 319 enable */
 234 #define TS_132              (1<<12) /* Time Sync Dest IP Addr 132 enable */
 235 #define TS_131              (1<<11) /* Time Sync Dest IP Addr 131 enable */
 236 #define TS_130              (1<<10) /* Time Sync Dest IP Addr 130 enable */
 237 #define TS_129              (1<<9)  /* Time Sync Dest IP Addr 129 enable */
 238 #define TS_TTL_NONZERO      (1<<8)  /* Time Sync Time To Live Non-zero enable */
 239 #define TS_ANNEX_F_EN       (1<<6)  /* Time Sync Annex F enable */
 240 #define TS_ANNEX_D_EN       (1<<4)  /* Time Sync Annex D enable */
 241 #define TS_LTYPE2_EN        (1<<3)  /* Time Sync LTYPE 2 enable */
 242 #define TS_LTYPE1_EN        (1<<2)  /* Time Sync LTYPE 1 enable */
 243 #define TS_TX_EN            (1<<1)  /* Time Sync Transmit Enable */
 244 #define TS_RX_EN            (1<<0)  /* Time Sync Receive Enable */
 245
 246 #define CTRL_V2_TS_BITS \
 247         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 248          TS_TTL_NONZERO  | TS_ANNEX_D_EN | TS_LTYPE1_EN)
 249
 250 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
 251 #define CTRL_V2_TX_TS_BITS  (CTRL_V2_TS_BITS | TS_TX_EN)
 252 #define CTRL_V2_RX_TS_BITS  (CTRL_V2_TS_BITS | TS_RX_EN)
 253
 254
 255 #define CTRL_V3_TS_BITS \
 256         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 257          TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
 258          TS_LTYPE1_EN)
 259
 260 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
 261 #define CTRL_V3_TX_TS_BITS  (CTRL_V3_TS_BITS | TS_TX_EN)
 262 #define CTRL_V3_RX_TS_BITS  (CTRL_V3_TS_BITS | TS_RX_EN)
 263
 264 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
 265 #define TS_SEQ_ID_OFFSET_SHIFT   (16)    /* Time Sync Sequence ID Offset */
 266 #define TS_SEQ_ID_OFFSET_MASK    (0x3f)
 267 #define TS_MSG_TYPE_EN_SHIFT     (0)     /* Time Sync Message Type Enable */
 268 #define TS_MSG_TYPE_EN_MASK      (0xffff)
 269
 270 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
 271 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
 272
 273 /* Bit definitions for the CPSW1_TS_CTL register */
 274 #define CPSW_V1_TS_RX_EN                BIT(0)
 275 #define CPSW_V1_TS_TX_EN                BIT(4)
 276 #define CPSW_V1_MSG_TYPE_OFS            16
 277
 278 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
 279 #define CPSW_V1_SEQ_ID_OFS_SHIFT        16
 280
 281 struct cpsw_host_regs {
 282         u32     max_blks;
 283         u32     blk_cnt;
 284         u32     tx_in_ctl;
 285         u32     port_vlan;
 286         u32     tx_pri_map;
 287         u32     cpdma_tx_pri_map;
 288         u32     cpdma_rx_chan_map;
 289 };
 290
 291 struct cpsw_sliver_regs {
 292         u32     id_ver;
 293         u32     mac_control;
 294         u32     mac_status;
 295         u32     soft_reset;
 296         u32     rx_maxlen;
 297         u32     __reserved_0;
 298         u32     rx_pause;
 299         u32     tx_pause;
 300         u32     __reserved_1;
 301         u32     rx_pri_map;
 302 };
 303
 304 struct cpsw_hw_stats {
 305         u32     rxgoodframes;
 306         u32     rxbroadcastframes;
 307         u32     rxmulticastframes;
 308         u32     rxpauseframes;
 309         u32     rxcrcerrors;
 310         u32     rxaligncodeerrors;
 311         u32     rxoversizedframes;
 312         u32     rxjabberframes;
 313         u32     rxundersizedframes;
 314         u32     rxfragments;
 315         u32     __pad_0[2];
 316         u32     rxoctets;
 317         u32     txgoodframes;
 318         u32     txbroadcastframes;
 319         u32     txmulticastframes;
 320         u32     txpauseframes;
 321         u32     txdeferredframes;
 322         u32     txcollisionframes;
 323         u32     txsinglecollframes;
 324         u32     txmultcollframes;
 325         u32     txexcessivecollisions;
 326         u32     txlatecollisions;
 327         u32     txunderrun;
 328         u32     txcarriersenseerrors;
 329         u32     txoctets;
 330         u32     octetframes64;
 331         u32     octetframes65t127;
 332         u32     octetframes128t255;
 333         u32     octetframes256t511;
 334         u32     octetframes512t1023;
 335         u32     octetframes1024tup;
 336         u32     netoctets;
 337         u32     rxsofoverruns;
 338         u32     rxmofoverruns;
 339         u32     rxdmaoverruns;
 340 };
 341
 342 struct cpsw_slave {
 343         void __iomem                    *regs;
 344         struct cpsw_sliver_regs __iomem *sliver;
 345         int                             slave_num;
 346         u32                             mac_control;
 347         struct cpsw_slave_data          *data;
 348         struct phy_device               *phy;
 349         struct net_device               *ndev;
 350         u32                             port_vlan;
 351         u32                             open_stat;
 352 };
 353
 354 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
 355 {
 356         return __raw_readl(slave->regs + offset);
 357 }
 358
 359 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
 360 {
 361         __raw_writel(val, slave->regs + offset);
 362 }
 363
 364 struct cpsw_priv {
 365         spinlock_t                      lock;
 366         struct platform_device          *pdev;
 367         struct net_device               *ndev;
 368         struct napi_struct              napi_rx;
 369         struct napi_struct              napi_tx;
 370         struct device                   *dev;
 371         struct cpsw_platform_data       data;
 372         struct cpsw_ss_regs __iomem     *regs;
 373         struct cpsw_wr_regs __iomem     *wr_regs;
 374         u8 __iomem                      *hw_stats;
 375         struct cpsw_host_regs __iomem   *host_port_regs;
 376         u32                             msg_enable;
 377         u32                             version;
 378         u32                             coal_intvl;
 379         u32                             bus_freq_mhz;
 380         int                             rx_packet_max;
 381         int                             host_port;
 382         struct clk                      *clk;
 383         u8                              mac_addr[ETH_ALEN];
 384         struct cpsw_slave               *slaves;
 385         struct cpdma_ctlr               *dma;
 386         struct cpdma_chan               *txch, *rxch;
 387         struct cpsw_ale                 *ale;
 388         bool                            rx_pause;
 389         bool                            tx_pause;
 390         /* snapshot of IRQ numbers */
 391         u32 irqs_table[4];
 392         u32 num_irqs;
 393         struct cpts *cpts;
 394         u32 emac_port;
 395 };
 396
 397 struct cpsw_stats {
 398         char stat_string[ETH_GSTRING_LEN];
 399         int type;
 400         int sizeof_stat;
 401         int stat_offset;
 402 };
 403
 404 enum {
 405         CPSW_STATS,
 406         CPDMA_RX_STATS,
 407         CPDMA_TX_STATS,
 408 };
 409
 410 #define CPSW_STAT(m)            CPSW_STATS,                             \
 411                                 sizeof(((struct cpsw_hw_stats *)0)->m), \
 412                                 offsetof(struct cpsw_hw_stats, m)
 413 #define CPDMA_RX_STAT(m)        CPDMA_RX_STATS,                            \
 414                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 415                                 offsetof(struct cpdma_chan_stats, m)
 416 #define CPDMA_TX_STAT(m)        CPDMA_TX_STATS,                            \
 417                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 418                                 offsetof(struct cpdma_chan_stats, m)
 419
 420 static const struct cpsw_stats cpsw_gstrings_stats[] = {
 421         { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
 422         { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
 423         { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
 424         { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
 425         { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
 426         { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
 427         { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
 428         { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
 429         { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
 430         { "Rx Fragments", CPSW_STAT(rxfragments) },
 431         { "Rx Octets", CPSW_STAT(rxoctets) },
 432         { "Good Tx Frames", CPSW_STAT(txgoodframes) },
 433         { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
 434         { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
 435         { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
 436         { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
 437         { "Collisions", CPSW_STAT(txcollisionframes) },
 438         { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
 439         { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
 440         { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
 441         { "Late Collisions", CPSW_STAT(txlatecollisions) },
 442         { "Tx Underrun", CPSW_STAT(txunderrun) },
 443         { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
 444         { "Tx Octets", CPSW_STAT(txoctets) },
 445         { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
 446         { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
 447         { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
 448         { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
 449         { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
 450         { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
 451         { "Net Octets", CPSW_STAT(netoctets) },
 452         { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
 453         { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
 454         { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
 455         { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) },
 456         { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
 457         { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
 458         { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) },
 459         { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
 460         { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
 461         { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
 462         { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
 463         { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
 464         { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
 465         { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) },
 466         { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) },
 467         { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
 468         { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) },
 469         { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) },
 470         { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) },
 471         { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) },
 472         { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) },
 473         { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) },
 474         { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) },
 475         { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) },
 476         { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) },
 477         { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) },
 478         { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) },
 479         { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) },
 480         { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) },
 481 };
 482
 483 #define CPSW_STATS_LEN  ARRAY_SIZE(cpsw_gstrings_stats)
 484
 485 #define napi_to_priv(napi)      container_of(napi, struct cpsw_priv, napi)
 486 #define for_each_slave(priv, func, arg...)                              \
 487         do {                                                            \
 488                 struct cpsw_slave *slave;                               \
 489                 int n;                                                  \
 490                 if (priv->data.dual_emac)                               \
 491                         (func)((priv)->slaves + priv->emac_port, ##arg);\
 492                 else                                                    \
 493                         for (n = (priv)->data.slaves,                   \
 494                                         slave = (priv)->slaves;         \
 495                                         n; n--)                         \
 496                                 (func)(slave++, ##arg);                 \
 497         } while (0)
 498 #define cpsw_get_slave_ndev(priv, __slave_no__)                         \
 499         ((__slave_no__ < priv->data.slaves) ?                           \
 500                 priv->slaves[__slave_no__].ndev : NULL)
 501 #define cpsw_get_slave_priv(priv, __slave_no__)                         \
 502         (((__slave_no__ < priv->data.slaves) &&                         \
 503                 (priv->slaves[__slave_no__].ndev)) ?                    \
 504                 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL)    \
 505
 506 #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb)         \
 507         do {                                                            \
 508                 if (!priv->data.dual_emac)                              \
 509                         break;                                          \
 510                 if (CPDMA_RX_SOURCE_PORT(status) == 1) {                \
 511                         ndev = cpsw_get_slave_ndev(priv, 0);            \
 512                         priv = netdev_priv(ndev);                       \
 513                         skb->dev = ndev;                                \
 514                 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) {         \
 515                         ndev = cpsw_get_slave_ndev(priv, 1);            \
 516                         priv = netdev_priv(ndev);                       \
 517                         skb->dev = ndev;                                \
 518                 }                                                       \
 519         } while (0)
 520 #define cpsw_add_mcast(priv, addr)                                      \
 521         do {                                                            \
 522                 if (priv->data.dual_emac) {                             \
 523                         struct cpsw_slave *slave = priv->slaves +       \
 524                                                 priv->emac_port;        \
 525                         int slave_port = cpsw_get_slave_port(priv,      \
 526                                                 slave->slave_num);      \
 527                         cpsw_ale_add_mcast(priv->ale, addr,             \
 528                                 1 << slave_port | 1 << priv->host_port, \
 529                                 ALE_VLAN, slave->port_vlan, 0);         \
 530                 } else {                                                \
 531                         cpsw_ale_add_mcast(priv->ale, addr,             \
 532                                 ALE_ALL_PORTS << priv->host_port,       \
 533                                 0, 0, 0);                               \
 534                 }                                                       \
 535         } while (0)
 536
 537 static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
 538 {
 539         if (priv->host_port == 0)
 540                 return slave_num + 1;
 541         else
 542                 return slave_num;
 543 }
 544
 545 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
 546 {
 547         struct cpsw_priv *priv = netdev_priv(ndev);
 548         struct cpsw_ale *ale = priv->ale;
 549         int i;
 550
 551         if (priv->data.dual_emac) {
 552                 bool flag = false;
 553
 554                 /* Enabling promiscuous mode for one interface will be
 555                  * common for both the interface as the interface shares
 556                  * the same hardware resource.
 557                  */
 558                 for (i = 0; i < priv->data.slaves; i++)
 559                         if (priv->slaves[i].ndev->flags & IFF_PROMISC)
 560                                 flag = true;
 561
 562                 if (!enable && flag) {
 563                         enable = true;
 564                         dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
 565                 }
 566
 567                 if (enable) {
 568                         /* Enable Bypass */
 569                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
 570
 571                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 572                 } else {
 573                         /* Disable Bypass */
 574                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
 575                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 576                 }
 577         } else {
 578                 if (enable) {
 579                         unsigned long timeout = jiffies + HZ;
 580
 581                         /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
 582                         for (i = 0; i <= priv->data.slaves; i++) {
 583                                 cpsw_ale_control_set(ale, i,
 584                                                      ALE_PORT_NOLEARN, 1);
 585                                 cpsw_ale_control_set(ale, i,
 586                                                      ALE_PORT_NO_SA_UPDATE, 1);
 587                         }
 588
 589                         /* Clear All Untouched entries */
 590                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 591                         do {
 592                                 cpu_relax();
 593                                 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
 594                                         break;
 595                         } while (time_after(timeout, jiffies));
 596                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 597
 598                         /* Clear all mcast from ALE */
 599                         cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS <<
 600                                                  priv->host_port, -1);
 601
 602                         /* Flood All Unicast Packets to Host port */
 603                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
 604                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 605                 } else {
 606                         /* Don't Flood All Unicast Packets to Host port */
 607                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
 608
 609                         /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
 610                         for (i = 0; i <= priv->data.slaves; i++) {
 611                                 cpsw_ale_control_set(ale, i,
 612                                                      ALE_PORT_NOLEARN, 0);
 613                                 cpsw_ale_control_set(ale, i,
 614                                                      ALE_PORT_NO_SA_UPDATE, 0);
 615                         }
 616                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 617                 }
 618         }
 619 }
 620
 621 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
 622 {
 623         struct cpsw_priv *priv = netdev_priv(ndev);
 624         int vid;
 625
 626         if (priv->data.dual_emac)
 627                 vid = priv->slaves[priv->emac_port].port_vlan;
 628         else
 629                 vid = priv->data.default_vlan;
 630
 631         if (ndev->flags & IFF_PROMISC) {
 632                 /* Enable promiscuous mode */
 633                 cpsw_set_promiscious(ndev, true);
 634                 cpsw_ale_set_allmulti(priv->ale, IFF_ALLMULTI);
 635                 return;
 636         } else {
 637                 /* Disable promiscuous mode */
 638                 cpsw_set_promiscious(ndev, false);
 639         }
 640
 641         /* Restore allmulti on vlans if necessary */
 642         cpsw_ale_set_allmulti(priv->ale, priv->ndev->flags & IFF_ALLMULTI);
 643
 644         /* Clear all mcast from ALE */
 645         cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port,
 646                                  vid);
 647
 648         if (!netdev_mc_empty(ndev)) {
 649                 struct netdev_hw_addr *ha;
 650
 651                 /* program multicast address list into ALE register */
 652                 netdev_for_each_mc_addr(ha, ndev) {
 653                         cpsw_add_mcast(priv, (u8 *)ha->addr);
 654                 }
 655         }
 656 }
 657
 658 static void cpsw_intr_enable(struct cpsw_priv *priv)
 659 {
 660         __raw_writel(0xFF, &priv->wr_regs->tx_en);
 661         __raw_writel(0xFF, &priv->wr_regs->rx_en);
 662
 663         cpdma_ctlr_int_ctrl(priv->dma, true);
 664         return;
 665 }
 666
 667 static void cpsw_intr_disable(struct cpsw_priv *priv)
 668 {
 669         __raw_writel(0, &priv->wr_regs->tx_en);
 670         __raw_writel(0, &priv->wr_regs->rx_en);
 671
 672         cpdma_ctlr_int_ctrl(priv->dma, false);
 673         return;
 674 }
 675
 676 static void cpsw_tx_handler(void *token, int len, int status)
 677 {
 678         struct sk_buff          *skb = token;
 679         struct net_device       *ndev = skb->dev;
 680         struct cpsw_priv        *priv = netdev_priv(ndev);
 681
 682         /* Check whether the queue is stopped due to stalled tx dma, if the
 683          * queue is stopped then start the queue as we have free desc for tx
 684          */
 685         if (unlikely(netif_queue_stopped(ndev)))
 686                 netif_wake_queue(ndev);
 687         cpts_tx_timestamp(priv->cpts, skb);
 688         ndev->stats.tx_packets++;
 689         ndev->stats.tx_bytes += len;
 690         dev_kfree_skb_any(skb);
 691 }
 692
 693 static void cpsw_rx_handler(void *token, int len, int status)
 694 {
 695         struct sk_buff          *skb = token;
 696         struct sk_buff          *new_skb;
 697         struct net_device       *ndev = skb->dev;
 698         struct cpsw_priv        *priv = netdev_priv(ndev);
 699         int                     ret = 0;
 700
 701         cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
 702
 703         if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
 704                 bool ndev_status = false;
 705                 struct cpsw_slave *slave = priv->slaves;
 706                 int n;
 707
 708                 if (priv->data.dual_emac) {
 709                         /* In dual emac mode check for all interfaces */
 710                         for (n = priv->data.slaves; n; n--, slave++)
 711                                 if (netif_running(slave->ndev))
 712                                         ndev_status = true;
 713                 }
 714
 715                 if (ndev_status && (status >= 0)) {
 716                         /* The packet received is for the interface which
 717                          * is already down and the other interface is up
 718                          * and running, instead of freeing which results
 719                          * in reducing of the number of rx descriptor in
 720                          * DMA engine, requeue skb back to cpdma.
 721                          */
 722                         new_skb = skb;
 723                         goto requeue;
 724                 }
 725
 726                 /* the interface is going down, skbs are purged */
 727                 dev_kfree_skb_any(skb);
 728                 return;
 729         }
 730
 731         new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
 732         if (new_skb) {
 733                 skb_put(skb, len);
 734                 cpts_rx_timestamp(priv->cpts, skb);
 735                 skb->protocol = eth_type_trans(skb, ndev);
 736                 netif_receive_skb(skb);
 737                 ndev->stats.rx_bytes += len;
 738                 ndev->stats.rx_packets++;
 739         } else {
 740                 ndev->stats.rx_dropped++;
 741                 new_skb = skb;
 742         }
 743
 744 requeue:
 745         ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
 746                         skb_tailroom(new_skb), 0);
 747         if (WARN_ON(ret < 0))
 748                 dev_kfree_skb_any(new_skb);
 749 }
 750
 751 static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
 752 {
 753         struct cpsw_priv *priv = dev_id;
 754
 755         writel(0, &priv->wr_regs->tx_en);
 756         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
 757
 758         napi_schedule(&priv->napi_tx);
 759         return IRQ_HANDLED;
 760 }
 761
 762 static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
 763 {
 764         struct cpsw_priv *priv = dev_id;
 765
 766         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
 767         writel(0, &priv->wr_regs->rx_en);
 768
 769         napi_schedule(&priv->napi_rx);
 770         return IRQ_HANDLED;
 771 }
 772
 773 static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
 774 {
 775         struct cpsw_priv        *priv = napi_to_priv(napi_tx);
 776         int                     num_tx;
 777
 778         num_tx = cpdma_chan_process(priv->txch, budget);
 779         if (num_tx < budget) {
 780                 napi_complete(napi_tx);
 781                 writel(0xff, &priv->wr_regs->tx_en);
 782         }
 783
 784         if (num_tx)
 785                 cpsw_dbg(priv, intr, "poll %d tx pkts\n", num_tx);
 786
 787         return num_tx;
 788 }
 789
 790 static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
 791 {
 792         struct cpsw_priv        *priv = napi_to_priv(napi_rx);
 793         int                     num_rx;
 794
 795         num_rx = cpdma_chan_process(priv->rxch, budget);
 796         if (num_rx < budget) {
 797                 napi_complete(napi_rx);
 798                 writel(0xff, &priv->wr_regs->rx_en);
 799         }
 800
 801         if (num_rx)
 802                 cpsw_dbg(priv, intr, "poll %d rx pkts\n", num_rx);
 803
 804         return num_rx;
 805 }
 806
 807 static inline void soft_reset(const char *module, void __iomem *reg)
 808 {
 809         unsigned long timeout = jiffies + HZ;
 810
 811         __raw_writel(1, reg);
 812         do {
 813                 cpu_relax();
 814         } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
 815
 816         WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
 817 }
 818
 819 #define mac_hi(mac)     (((mac)[0] << 0) | ((mac)[1] << 8) |    \
 820                          ((mac)[2] << 16) | ((mac)[3] << 24))
 821 #define mac_lo(mac)     (((mac)[4] << 0) | ((mac)[5] << 8))
 822
 823 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
 824                                struct cpsw_priv *priv)
 825 {
 826         slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
 827         slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
 828 }
 829
 830 static void _cpsw_adjust_link(struct cpsw_slave *slave,
 831                               struct cpsw_priv *priv, bool *link)
 832 {
 833         struct phy_device       *phy = slave->phy;
 834         u32                     mac_control = 0;
 835         u32                     slave_port;
 836
 837         if (!phy)
 838                 return;
 839
 840         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
 841
 842         if (phy->link) {
 843                 mac_control = priv->data.mac_control;
 844
 845                 /* enable forwarding */
 846                 cpsw_ale_control_set(priv->ale, slave_port,
 847                                      ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
 848
 849                 if (phy->speed == 1000)
 850                         mac_control |= BIT(7);  /* GIGABITEN    */
 851                 if (phy->duplex)
 852                         mac_control |= BIT(0);  /* FULLDUPLEXEN */
 853
 854                 /* set speed_in input in case RMII mode is used in 100Mbps */
 855                 if (phy->speed == 100)
 856                         mac_control |= BIT(15);
 857                 else if (phy->speed == 10)
 858                         mac_control |= BIT(18); /* In Band mode */
 859
 860                 if (priv->rx_pause)
 861                         mac_control |= BIT(3);
 862
 863                 if (priv->tx_pause)
 864                         mac_control |= BIT(4);
 865
 866                 *link = true;
 867         } else {
 868                 mac_control = 0;
 869                 /* disable forwarding */
 870                 cpsw_ale_control_set(priv->ale, slave_port,
 871                                      ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
 872         }
 873
 874         if (mac_control != slave->mac_control) {
 875                 phy_print_status(phy);
 876                 __raw_writel(mac_control, &slave->sliver->mac_control);
 877         }
 878
 879         slave->mac_control = mac_control;
 880 }
 881
 882 static void cpsw_adjust_link(struct net_device *ndev)
 883 {
 884         struct cpsw_priv        *priv = netdev_priv(ndev);
 885         bool                    link = false;
 886
 887         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
 888
 889         if (link) {
 890                 netif_carrier_on(ndev);
 891                 if (netif_running(ndev))
 892                         netif_wake_queue(ndev);
 893         } else {
 894                 netif_carrier_off(ndev);
 895                 netif_stop_queue(ndev);
 896         }
 897 }
 898
 899 static int cpsw_get_coalesce(struct net_device *ndev,
 900                                 struct ethtool_coalesce *coal)
 901 {
 902         struct cpsw_priv *priv = netdev_priv(ndev);
 903
 904         coal->rx_coalesce_usecs = priv->coal_intvl;
 905         return 0;
 906 }
 907
 908 static int cpsw_set_coalesce(struct net_device *ndev,
 909                                 struct ethtool_coalesce *coal)
 910 {
 911         struct cpsw_priv *priv = netdev_priv(ndev);
 912         u32 int_ctrl;
 913         u32 num_interrupts = 0;
 914         u32 prescale = 0;
 915         u32 addnl_dvdr = 1;
 916         u32 coal_intvl = 0;
 917
 918         coal_intvl = coal->rx_coalesce_usecs;
 919
 920         int_ctrl =  readl(&priv->wr_regs->int_control);
 921         prescale = priv->bus_freq_mhz * 4;
 922
 923         if (!coal->rx_coalesce_usecs) {
 924                 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
 925                 goto update_return;
 926         }
 927
 928         if (coal_intvl < CPSW_CMINTMIN_INTVL)
 929                 coal_intvl = CPSW_CMINTMIN_INTVL;
 930
 931         if (coal_intvl > CPSW_CMINTMAX_INTVL) {
 932                 /* Interrupt pacer works with 4us Pulse, we can
 933                  * throttle further by dilating the 4us pulse.
 934                  */
 935                 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
 936
 937                 if (addnl_dvdr > 1) {
 938                         prescale *= addnl_dvdr;
 939                         if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
 940                                 coal_intvl = (CPSW_CMINTMAX_INTVL
 941                                                 * addnl_dvdr);
 942                 } else {
 943                         addnl_dvdr = 1;
 944                         coal_intvl = CPSW_CMINTMAX_INTVL;
 945                 }
 946         }
 947
 948         num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
 949         writel(num_interrupts, &priv->wr_regs->rx_imax);
 950         writel(num_interrupts, &priv->wr_regs->tx_imax);
 951
 952         int_ctrl |= CPSW_INTPACEEN;
 953         int_ctrl &= (~CPSW_INTPRESCALE_MASK);
 954         int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
 955
 956 update_return:
 957         writel(int_ctrl, &priv->wr_regs->int_control);
 958
 959         cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
 960         if (priv->data.dual_emac) {
 961                 int i;
 962
 963                 for (i = 0; i < priv->data.slaves; i++) {
 964                         priv = netdev_priv(priv->slaves[i].ndev);
 965                         priv->coal_intvl = coal_intvl;
 966                 }
 967         } else {
 968                 priv->coal_intvl = coal_intvl;
 969         }
 970
 971         return 0;
 972 }
 973
 974 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
 975 {
 976         switch (sset) {
 977         case ETH_SS_STATS:
 978                 return CPSW_STATS_LEN;
 979         default:
 980                 return -EOPNOTSUPP;
 981         }
 982 }
 983
 984 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
 985 {
 986         u8 *p = data;
 987         int i;
 988
 989         switch (stringset) {
 990         case ETH_SS_STATS:
 991                 for (i = 0; i < CPSW_STATS_LEN; i++) {
 992                         memcpy(p, cpsw_gstrings_stats[i].stat_string,
 993                                ETH_GSTRING_LEN);
 994                         p += ETH_GSTRING_LEN;
 995                 }
 996                 break;
 997         }
 998 }
 999
1000 static void cpsw_get_ethtool_stats(struct net_device *ndev,
1001                                     struct ethtool_stats *stats, u64 *data)
1002 {
1003         struct cpsw_priv *priv = netdev_priv(ndev);
1004         struct cpdma_chan_stats rx_stats;
1005         struct cpdma_chan_stats tx_stats;
1006         u32 val;
1007         u8 *p;
1008         int i;
1009
1010         /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1011         cpdma_chan_get_stats(priv->rxch, &rx_stats);
1012         cpdma_chan_get_stats(priv->txch, &tx_stats);
1013
1014         for (i = 0; i < CPSW_STATS_LEN; i++) {
1015                 switch (cpsw_gstrings_stats[i].type) {
1016                 case CPSW_STATS:
1017                         val = readl(priv->hw_stats +
1018                                     cpsw_gstrings_stats[i].stat_offset);
1019                         data[i] = val;
1020                         break;
1021
1022                 case CPDMA_RX_STATS:
1023                         p = (u8 *)&rx_stats +
1024                                 cpsw_gstrings_stats[i].stat_offset;
1025                         data[i] = *(u32 *)p;
1026                         break;
1027
1028                 case CPDMA_TX_STATS:
1029                         p = (u8 *)&tx_stats +
1030                                 cpsw_gstrings_stats[i].stat_offset;
1031                         data[i] = *(u32 *)p;
1032                         break;
1033                 }
1034         }
1035 }
1036
1037 static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
1038 {
1039         u32 i;
1040         u32 usage_count = 0;
1041
1042         if (!priv->data.dual_emac)
1043                 return 0;
1044
1045         for (i = 0; i < priv->data.slaves; i++)
1046                 if (priv->slaves[i].open_stat)
1047                         usage_count++;
1048
1049         return usage_count;
1050 }
1051
1052 static inline int cpsw_tx_packet_submit(struct net_device *ndev,
1053                         struct cpsw_priv *priv, struct sk_buff *skb)
1054 {
1055         if (!priv->data.dual_emac)
1056                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1057                                   skb->len, 0);
1058
1059         if (ndev == cpsw_get_slave_ndev(priv, 0))
1060                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1061                                   skb->len, 1);
1062         else
1063                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1064                                   skb->len, 2);
1065 }
1066
1067 static inline void cpsw_add_dual_emac_def_ale_entries(
1068                 struct cpsw_priv *priv, struct cpsw_slave *slave,
1069                 u32 slave_port)
1070 {
1071         u32 port_mask = 1 << slave_port | 1 << priv->host_port;
1072
1073         if (priv->version == CPSW_VERSION_1)
1074                 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1075         else
1076                 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1077         cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
1078                           port_mask, port_mask, 0);
1079         cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1080                            port_mask, ALE_VLAN, slave->port_vlan, 0);
1081         cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1082                 priv->host_port, ALE_VLAN | ALE_SECURE, slave->port_vlan);
1083 }
1084
1085 static void soft_reset_slave(struct cpsw_slave *slave)
1086 {
1087         char name[32];
1088
1089         snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1090         soft_reset(name, &slave->sliver->soft_reset);
1091 }
1092
1093 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1094 {
1095         u32 slave_port;
1096
1097         soft_reset_slave(slave);
1098
1099         /* setup priority mapping */
1100         __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1101
1102         switch (priv->version) {
1103         case CPSW_VERSION_1:
1104                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1105                 break;
1106         case CPSW_VERSION_2:
1107         case CPSW_VERSION_3:
1108         case CPSW_VERSION_4:
1109                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1110                 break;
1111         }
1112
1113         /* setup max packet size, and mac address */
1114         __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
1115         cpsw_set_slave_mac(slave, priv);
1116
1117         slave->mac_control = 0; /* no link yet */
1118
1119         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1120
1121         if (priv->data.dual_emac)
1122                 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1123         else
1124                 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1125                                    1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1126
1127         slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
1128                                  &cpsw_adjust_link, slave->data->phy_if);
1129         if (IS_ERR(slave->phy)) {
1130                 dev_err(priv->dev, "phy %s not found on slave %d\n",
1131                         slave->data->phy_id, slave->slave_num);
1132                 slave->phy = NULL;
1133         } else {
1134                 dev_info(priv->dev, "phy found : id is : 0x%x\n",
1135                          slave->phy->phy_id);
1136                 phy_start(slave->phy);
1137
1138                 /* Configure GMII_SEL register */
1139                 cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface,
1140                              slave->slave_num);
1141         }
1142 }
1143
1144 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1145 {
1146         const int vlan = priv->data.default_vlan;
1147         const int port = priv->host_port;
1148         u32 reg;
1149         int i;
1150         int unreg_mcast_mask;
1151
1152         reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1153                CPSW2_PORT_VLAN;
1154
1155         writel(vlan, &priv->host_port_regs->port_vlan);
1156
1157         for (i = 0; i < priv->data.slaves; i++)
1158                 slave_write(priv->slaves + i, vlan, reg);
1159
1160         if (priv->ndev->flags & IFF_ALLMULTI)
1161                 unreg_mcast_mask = ALE_ALL_PORTS;
1162         else
1163                 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1164
1165         cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port,
1166                           ALE_ALL_PORTS << port, ALE_ALL_PORTS << port,
1167                           unreg_mcast_mask << port);
1168 }
1169
1170 static void cpsw_init_host_port(struct cpsw_priv *priv)
1171 {
1172         u32 control_reg;
1173         u32 fifo_mode;
1174
1175         /* soft reset the controller and initialize ale */
1176         soft_reset("cpsw", &priv->regs->soft_reset);
1177         cpsw_ale_start(priv->ale);
1178
1179         /* switch to vlan unaware mode */
1180         cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE,
1181                              CPSW_ALE_VLAN_AWARE);
1182         control_reg = readl(&priv->regs->control);
1183         control_reg |= CPSW_VLAN_AWARE;
1184         writel(control_reg, &priv->regs->control);
1185         fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1186                      CPSW_FIFO_NORMAL_MODE;
1187         writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
1188
1189         /* setup host port priority mapping */
1190         __raw_writel(CPDMA_TX_PRIORITY_MAP,
1191                      &priv->host_port_regs->cpdma_tx_pri_map);
1192         __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
1193
1194         cpsw_ale_control_set(priv->ale, priv->host_port,
1195                              ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1196
1197         if (!priv->data.dual_emac) {
1198                 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port,
1199                                    0, 0);
1200                 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1201                                    1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2);
1202         }
1203 }
1204
1205 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
1206 {
1207         u32 slave_port;
1208
1209         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1210
1211         if (!slave->phy)
1212                 return;
1213         phy_stop(slave->phy);
1214         phy_disconnect(slave->phy);
1215         slave->phy = NULL;
1216         cpsw_ale_control_set(priv->ale, slave_port,
1217                              ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1218 }
1219
1220 static int cpsw_ndo_open(struct net_device *ndev)
1221 {
1222         struct cpsw_priv *priv = netdev_priv(ndev);
1223         int i, ret;
1224         u32 reg;
1225
1226         if (!cpsw_common_res_usage_state(priv))
1227                 cpsw_intr_disable(priv);
1228         netif_carrier_off(ndev);
1229
1230         pm_runtime_get_sync(&priv->pdev->dev);
1231
1232         reg = priv->version;
1233
1234         dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1235                  CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1236                  CPSW_RTL_VERSION(reg));
1237
1238         /* initialize host and slave ports */
1239         if (!cpsw_common_res_usage_state(priv))
1240                 cpsw_init_host_port(priv);
1241         for_each_slave(priv, cpsw_slave_open, priv);
1242
1243         /* Add default VLAN */
1244         if (!priv->data.dual_emac)
1245                 cpsw_add_default_vlan(priv);
1246         else
1247                 cpsw_ale_add_vlan(priv->ale, priv->data.default_vlan,
1248                                   ALE_ALL_PORTS << priv->host_port,
1249                                   ALE_ALL_PORTS << priv->host_port, 0, 0);
1250
1251         if (!cpsw_common_res_usage_state(priv)) {
1252                 struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0);
1253
1254                 /* setup tx dma to fixed prio and zero offset */
1255                 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
1256                 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
1257
1258                 /* disable priority elevation */
1259                 __raw_writel(0, &priv->regs->ptype);
1260
1261                 /* enable statistics collection only on all ports */
1262                 __raw_writel(0x7, &priv->regs->stat_port_en);
1263
1264                 /* Enable internal fifo flow control */
1265                 writel(0x7, &priv->regs->flow_control);
1266
1267                 napi_enable(&priv_sl0->napi_rx);
1268                 napi_enable(&priv_sl0->napi_tx);
1269
1270                 if (WARN_ON(!priv->data.rx_descs))
1271                         priv->data.rx_descs = 128;
1272
1273                 for (i = 0; i < priv->data.rx_descs; i++) {
1274                         struct sk_buff *skb;
1275
1276                         ret = -ENOMEM;
1277                         skb = __netdev_alloc_skb_ip_align(priv->ndev,
1278                                         priv->rx_packet_max, GFP_KERNEL);
1279                         if (!skb)
1280                                 goto err_cleanup;
1281                         ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
1282                                         skb_tailroom(skb), 0);
1283                         if (ret < 0) {
1284                                 kfree_skb(skb);
1285                                 goto err_cleanup;
1286                         }
1287                 }
1288                 /* continue even if we didn't manage to submit all
1289                  * receive descs
1290                  */
1291                 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
1292
1293                 if (cpts_register(&priv->pdev->dev, priv->cpts,
1294                                   priv->data.cpts_clock_mult,
1295                                   priv->data.cpts_clock_shift))
1296                         dev_err(priv->dev, "error registering cpts device\n");
1297
1298         }
1299
1300         /* Enable Interrupt pacing if configured */
1301         if (priv->coal_intvl != 0) {
1302                 struct ethtool_coalesce coal;
1303
1304                 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1305                 cpsw_set_coalesce(ndev, &coal);
1306         }
1307
1308         cpdma_ctlr_start(priv->dma);
1309         cpsw_intr_enable(priv);
1310
1311         if (priv->data.dual_emac)
1312                 priv->slaves[priv->emac_port].open_stat = true;
1313         return 0;
1314
1315 err_cleanup:
1316         cpdma_ctlr_stop(priv->dma);
1317         for_each_slave(priv, cpsw_slave_stop, priv);
1318         pm_runtime_put_sync(&priv->pdev->dev);
1319         netif_carrier_off(priv->ndev);
1320         return ret;
1321 }
1322
1323 static int cpsw_ndo_stop(struct net_device *ndev)
1324 {
1325         struct cpsw_priv *priv = netdev_priv(ndev);
1326
1327         cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1328         netif_stop_queue(priv->ndev);
1329         netif_carrier_off(priv->ndev);
1330
1331         if (cpsw_common_res_usage_state(priv) <= 1) {
1332                 struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0);
1333
1334                 napi_disable(&priv_sl0->napi_rx);
1335                 napi_disable(&priv_sl0->napi_tx);
1336                 cpts_unregister(priv->cpts);
1337                 cpsw_intr_disable(priv);
1338                 cpdma_ctlr_stop(priv->dma);
1339                 cpsw_ale_stop(priv->ale);
1340         }
1341         for_each_slave(priv, cpsw_slave_stop, priv);
1342         pm_runtime_put_sync(&priv->pdev->dev);
1343         if (priv->data.dual_emac)
1344                 priv->slaves[priv->emac_port].open_stat = false;
1345         return 0;
1346 }
1347
1348 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1349                                        struct net_device *ndev)
1350 {
1351         struct cpsw_priv *priv = netdev_priv(ndev);
1352         int ret;
1353
1354         ndev->trans_start = jiffies;
1355
1356         if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1357                 cpsw_err(priv, tx_err, "packet pad failed\n");
1358                 ndev->stats.tx_dropped++;
1359                 return NETDEV_TX_OK;
1360         }
1361
1362         if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1363                                 priv->cpts->tx_enable)
1364                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1365
1366         skb_tx_timestamp(skb);
1367
1368         ret = cpsw_tx_packet_submit(ndev, priv, skb);
1369         if (unlikely(ret != 0)) {
1370                 cpsw_err(priv, tx_err, "desc submit failed\n");
1371                 goto fail;
1372         }
1373
1374         /* If there is no more tx desc left free then we need to
1375          * tell the kernel to stop sending us tx frames.
1376          */
1377         if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
1378                 netif_stop_queue(ndev);
1379
1380         return NETDEV_TX_OK;
1381 fail:
1382         ndev->stats.tx_dropped++;
1383         netif_stop_queue(ndev);
1384         return NETDEV_TX_BUSY;
1385 }
1386
1387 #ifdef CONFIG_TI_CPTS
1388
1389 static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1390 {
1391         struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
1392         u32 ts_en, seq_id;
1393
1394         if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
1395                 slave_write(slave, 0, CPSW1_TS_CTL);
1396                 return;
1397         }
1398
1399         seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1400         ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1401
1402         if (priv->cpts->tx_enable)
1403                 ts_en |= CPSW_V1_TS_TX_EN;
1404
1405         if (priv->cpts->rx_enable)
1406                 ts_en |= CPSW_V1_TS_RX_EN;
1407
1408         slave_write(slave, ts_en, CPSW1_TS_CTL);
1409         slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1410 }
1411
1412 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1413 {
1414         struct cpsw_slave *slave;
1415         u32 ctrl, mtype;
1416
1417         if (priv->data.dual_emac)
1418                 slave = &priv->slaves[priv->emac_port];
1419         else
1420                 slave = &priv->slaves[priv->data.active_slave];
1421
1422         ctrl = slave_read(slave, CPSW2_CONTROL);
1423         switch (priv->version) {
1424         case CPSW_VERSION_2:
1425                 ctrl &= ~CTRL_V2_ALL_TS_MASK;
1426
1427                 if (priv->cpts->tx_enable)
1428                         ctrl |= CTRL_V2_TX_TS_BITS;
1429
1430                 if (priv->cpts->rx_enable)
1431                         ctrl |= CTRL_V2_RX_TS_BITS;
1432                 break;
1433         case CPSW_VERSION_3:
1434         default:
1435                 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1436
1437                 if (priv->cpts->tx_enable)
1438                         ctrl |= CTRL_V3_TX_TS_BITS;
1439
1440                 if (priv->cpts->rx_enable)
1441                         ctrl |= CTRL_V3_RX_TS_BITS;
1442                 break;
1443         }
1444
1445         mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1446
1447         slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1448         slave_write(slave, ctrl, CPSW2_CONTROL);
1449         __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
1450 }
1451
1452 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1453 {
1454         struct cpsw_priv *priv = netdev_priv(dev);
1455         struct cpts *cpts = priv->cpts;
1456         struct hwtstamp_config cfg;
1457
1458         if (priv->version != CPSW_VERSION_1 &&
1459             priv->version != CPSW_VERSION_2 &&
1460             priv->version != CPSW_VERSION_3)
1461                 return -EOPNOTSUPP;
1462
1463         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1464                 return -EFAULT;
1465
1466         /* reserved for future extensions */
1467         if (cfg.flags)
1468                 return -EINVAL;
1469
1470         if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
1471                 return -ERANGE;
1472
1473         switch (cfg.rx_filter) {
1474         case HWTSTAMP_FILTER_NONE:
1475                 cpts->rx_enable = 0;
1476                 break;
1477         case HWTSTAMP_FILTER_ALL:
1478         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1479         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1480         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1481                 return -ERANGE;
1482         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1483         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1484         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1485         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1486         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1487         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1488         case HWTSTAMP_FILTER_PTP_V2_EVENT:
1489         case HWTSTAMP_FILTER_PTP_V2_SYNC:
1490         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1491                 cpts->rx_enable = 1;
1492                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1493                 break;
1494         default:
1495                 return -ERANGE;
1496         }
1497
1498         cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;
1499
1500         switch (priv->version) {
1501         case CPSW_VERSION_1:
1502                 cpsw_hwtstamp_v1(priv);
1503                 break;
1504         case CPSW_VERSION_2:
1505         case CPSW_VERSION_3:
1506                 cpsw_hwtstamp_v2(priv);
1507                 break;
1508         default:
1509                 WARN_ON(1);
1510         }
1511
1512         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1513 }
1514
1515 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1516 {
1517         struct cpsw_priv *priv = netdev_priv(dev);
1518         struct cpts *cpts = priv->cpts;
1519         struct hwtstamp_config cfg;
1520
1521         if (priv->version != CPSW_VERSION_1 &&
1522             priv->version != CPSW_VERSION_2 &&
1523             priv->version != CPSW_VERSION_3)
1524                 return -EOPNOTSUPP;
1525
1526         cfg.flags = 0;
1527         cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1528         cfg.rx_filter = (cpts->rx_enable ?
1529                          HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1530
1531         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1532 }
1533
1534 #endif /*CONFIG_TI_CPTS*/
1535
1536 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1537 {
1538         struct cpsw_priv *priv = netdev_priv(dev);
1539         int slave_no = cpsw_slave_index(priv);
1540
1541         if (!netif_running(dev))
1542                 return -EINVAL;
1543
1544         switch (cmd) {
1545 #ifdef CONFIG_TI_CPTS
1546         case SIOCSHWTSTAMP:
1547                 return cpsw_hwtstamp_set(dev, req);
1548         case SIOCGHWTSTAMP:
1549                 return cpsw_hwtstamp_get(dev, req);
1550 #endif
1551         }
1552
1553         if (!priv->slaves[slave_no].phy)
1554                 return -EOPNOTSUPP;
1555         return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd);
1556 }
1557
1558 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1559 {
1560         struct cpsw_priv *priv = netdev_priv(ndev);
1561
1562         cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1563         ndev->stats.tx_errors++;
1564         cpsw_intr_disable(priv);
1565         cpdma_chan_stop(priv->txch);
1566         cpdma_chan_start(priv->txch);
1567         cpsw_intr_enable(priv);
1568 }
1569
1570 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1571 {
1572         struct cpsw_priv *priv = netdev_priv(ndev);
1573         struct sockaddr *addr = (struct sockaddr *)p;
1574         int flags = 0;
1575         u16 vid = 0;
1576
1577         if (!is_valid_ether_addr(addr->sa_data))
1578                 return -EADDRNOTAVAIL;
1579
1580         if (priv->data.dual_emac) {
1581                 vid = priv->slaves[priv->emac_port].port_vlan;
1582                 flags = ALE_VLAN;
1583         }
1584
1585         cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port,
1586                            flags, vid);
1587         cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port,
1588                            flags, vid);
1589
1590         memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1591         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1592         for_each_slave(priv, cpsw_set_slave_mac, priv);
1593
1594         return 0;
1595 }
1596
1597 #ifdef CONFIG_NET_POLL_CONTROLLER
1598 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1599 {
1600         struct cpsw_priv *priv = netdev_priv(ndev);
1601
1602         cpsw_intr_disable(priv);
1603         cpsw_rx_interrupt(priv->irqs_table[0], priv);
1604         cpsw_tx_interrupt(priv->irqs_table[1], priv);
1605         cpsw_intr_enable(priv);
1606 }
1607 #endif
1608
1609 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1610                                 unsigned short vid)
1611 {
1612         int ret;
1613         int unreg_mcast_mask = 0;
1614         u32 port_mask;
1615
1616         if (priv->data.dual_emac) {
1617                 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
1618
1619                 if (priv->ndev->flags & IFF_ALLMULTI)
1620                         unreg_mcast_mask = port_mask;
1621         } else {
1622                 port_mask = ALE_ALL_PORTS;
1623
1624                 if (priv->ndev->flags & IFF_ALLMULTI)
1625                         unreg_mcast_mask = ALE_ALL_PORTS;
1626                 else
1627                         unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1628         }
1629
1630         ret = cpsw_ale_add_vlan(priv->ale, vid, port_mask, 0, port_mask,
1631                                 unreg_mcast_mask << priv->host_port);
1632         if (ret != 0)
1633                 return ret;
1634
1635         ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1636                                  priv->host_port, ALE_VLAN, vid);
1637         if (ret != 0)
1638                 goto clean_vid;
1639
1640         ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1641                                  port_mask, ALE_VLAN, vid, 0);
1642         if (ret != 0)
1643                 goto clean_vlan_ucast;
1644         return 0;
1645
1646 clean_vlan_ucast:
1647         cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1648                             priv->host_port, ALE_VLAN, vid);
1649 clean_vid:
1650         cpsw_ale_del_vlan(priv->ale, vid, 0);
1651         return ret;
1652 }
1653
1654 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1655                                     __be16 proto, u16 vid)
1656 {
1657         struct cpsw_priv *priv = netdev_priv(ndev);
1658
1659         if (vid == priv->data.default_vlan)
1660                 return 0;
1661
1662         if (priv->data.dual_emac) {
1663                 /* In dual EMAC, reserved VLAN id should not be used for
1664                  * creating VLAN interfaces as this can break the dual
1665                  * EMAC port separation
1666                  */
1667                 int i;
1668
1669                 for (i = 0; i < priv->data.slaves; i++) {
1670                         if (vid == priv->slaves[i].port_vlan)
1671                                 return -EINVAL;
1672                 }
1673         }
1674
1675         dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1676         return cpsw_add_vlan_ale_entry(priv, vid);
1677 }
1678
1679 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1680                                      __be16 proto, u16 vid)
1681 {
1682         struct cpsw_priv *priv = netdev_priv(ndev);
1683         int ret;
1684
1685         if (vid == priv->data.default_vlan)
1686                 return 0;
1687
1688         if (priv->data.dual_emac) {
1689                 int i;
1690
1691                 for (i = 0; i < priv->data.slaves; i++) {
1692                         if (vid == priv->slaves[i].port_vlan)
1693                                 return -EINVAL;
1694                 }
1695         }
1696
1697         dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1698         ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1699         if (ret != 0)
1700                 return ret;
1701
1702         ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1703                                  priv->host_port, ALE_VLAN, vid);
1704         if (ret != 0)
1705                 return ret;
1706
1707         return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1708                                   0, ALE_VLAN, vid);
1709 }
1710
1711 static const struct net_device_ops cpsw_netdev_ops = {
1712         .ndo_open               = cpsw_ndo_open,
1713         .ndo_stop               = cpsw_ndo_stop,
1714         .ndo_start_xmit         = cpsw_ndo_start_xmit,
1715         .ndo_set_mac_address    = cpsw_ndo_set_mac_address,
1716         .ndo_do_ioctl           = cpsw_ndo_ioctl,
1717         .ndo_validate_addr      = eth_validate_addr,
1718         .ndo_change_mtu         = eth_change_mtu,
1719         .ndo_tx_timeout         = cpsw_ndo_tx_timeout,
1720         .ndo_set_rx_mode        = cpsw_ndo_set_rx_mode,
1721 #ifdef CONFIG_NET_POLL_CONTROLLER
1722         .ndo_poll_controller    = cpsw_ndo_poll_controller,
1723 #endif
1724         .ndo_vlan_rx_add_vid    = cpsw_ndo_vlan_rx_add_vid,
1725         .ndo_vlan_rx_kill_vid   = cpsw_ndo_vlan_rx_kill_vid,
1726 };
1727
1728 static int cpsw_get_regs_len(struct net_device *ndev)
1729 {
1730         struct cpsw_priv *priv = netdev_priv(ndev);
1731
1732         return priv->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
1733 }
1734
1735 static void cpsw_get_regs(struct net_device *ndev,
1736                           struct ethtool_regs *regs, void *p)
1737 {
1738         struct cpsw_priv *priv = netdev_priv(ndev);
1739         u32 *reg = p;
1740
1741         /* update CPSW IP version */
1742         regs->version = priv->version;
1743
1744         cpsw_ale_dump(priv->ale, reg);
1745 }
1746
1747 static void cpsw_get_drvinfo(struct net_device *ndev,
1748                              struct ethtool_drvinfo *info)
1749 {
1750         struct cpsw_priv *priv = netdev_priv(ndev);
1751
1752         strlcpy(info->driver, "cpsw", sizeof(info->driver));
1753         strlcpy(info->version, "1.0", sizeof(info->version));
1754         strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
1755         info->regdump_len = cpsw_get_regs_len(ndev);
1756 }
1757
1758 static u32 cpsw_get_msglevel(struct net_device *ndev)
1759 {
1760         struct cpsw_priv *priv = netdev_priv(ndev);
1761         return priv->msg_enable;
1762 }
1763
1764 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1765 {
1766         struct cpsw_priv *priv = netdev_priv(ndev);
1767         priv->msg_enable = value;
1768 }
1769
1770 static int cpsw_get_ts_info(struct net_device *ndev,
1771                             struct ethtool_ts_info *info)
1772 {
1773 #ifdef CONFIG_TI_CPTS
1774         struct cpsw_priv *priv = netdev_priv(ndev);
1775
1776         info->so_timestamping =
1777                 SOF_TIMESTAMPING_TX_HARDWARE |
1778                 SOF_TIMESTAMPING_TX_SOFTWARE |
1779                 SOF_TIMESTAMPING_RX_HARDWARE |
1780                 SOF_TIMESTAMPING_RX_SOFTWARE |
1781                 SOF_TIMESTAMPING_SOFTWARE |
1782                 SOF_TIMESTAMPING_RAW_HARDWARE;
1783         info->phc_index = priv->cpts->phc_index;
1784         info->tx_types =
1785                 (1 << HWTSTAMP_TX_OFF) |
1786                 (1 << HWTSTAMP_TX_ON);
1787         info->rx_filters =
1788                 (1 << HWTSTAMP_FILTER_NONE) |
1789                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1790 #else
1791         info->so_timestamping =
1792                 SOF_TIMESTAMPING_TX_SOFTWARE |
1793                 SOF_TIMESTAMPING_RX_SOFTWARE |
1794                 SOF_TIMESTAMPING_SOFTWARE;
1795         info->phc_index = -1;
1796         info->tx_types = 0;
1797         info->rx_filters = 0;
1798 #endif
1799         return 0;
1800 }
1801
1802 static int cpsw_get_settings(struct net_device *ndev,
1803                              struct ethtool_cmd *ecmd)
1804 {
1805         struct cpsw_priv *priv = netdev_priv(ndev);
1806         int slave_no = cpsw_slave_index(priv);
1807
1808         if (priv->slaves[slave_no].phy)
1809                 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1810         else
1811                 return -EOPNOTSUPP;
1812 }
1813
1814 static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1815 {
1816         struct cpsw_priv *priv = netdev_priv(ndev);
1817         int slave_no = cpsw_slave_index(priv);
1818
1819         if (priv->slaves[slave_no].phy)
1820                 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1821         else
1822                 return -EOPNOTSUPP;
1823 }
1824
1825 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1826 {
1827         struct cpsw_priv *priv = netdev_priv(ndev);
1828         int slave_no = cpsw_slave_index(priv);
1829
1830         wol->supported = 0;
1831         wol->wolopts = 0;
1832
1833         if (priv->slaves[slave_no].phy)
1834                 phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol);
1835 }
1836
1837 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1838 {
1839         struct cpsw_priv *priv = netdev_priv(ndev);
1840         int slave_no = cpsw_slave_index(priv);
1841
1842         if (priv->slaves[slave_no].phy)
1843                 return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol);
1844         else
1845                 return -EOPNOTSUPP;
1846 }
1847
1848 static void cpsw_get_pauseparam(struct net_device *ndev,
1849                                 struct ethtool_pauseparam *pause)
1850 {
1851         struct cpsw_priv *priv = netdev_priv(ndev);
1852
1853         pause->autoneg = AUTONEG_DISABLE;
1854         pause->rx_pause = priv->rx_pause ? true : false;
1855         pause->tx_pause = priv->tx_pause ? true : false;
1856 }
1857
1858 static int cpsw_set_pauseparam(struct net_device *ndev,
1859                                struct ethtool_pauseparam *pause)
1860 {
1861         struct cpsw_priv *priv = netdev_priv(ndev);
1862         bool link;
1863
1864         priv->rx_pause = pause->rx_pause ? true : false;
1865         priv->tx_pause = pause->tx_pause ? true : false;
1866
1867         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1868
1869         return 0;
1870 }
1871
1872 static const struct ethtool_ops cpsw_ethtool_ops = {
1873         .get_drvinfo    = cpsw_get_drvinfo,
1874         .get_msglevel   = cpsw_get_msglevel,
1875         .set_msglevel   = cpsw_set_msglevel,
1876         .get_link       = ethtool_op_get_link,
1877         .get_ts_info    = cpsw_get_ts_info,
1878         .get_settings   = cpsw_get_settings,
1879         .set_settings   = cpsw_set_settings,
1880         .get_coalesce   = cpsw_get_coalesce,
1881         .set_coalesce   = cpsw_set_coalesce,
1882         .get_sset_count         = cpsw_get_sset_count,
1883         .get_strings            = cpsw_get_strings,
1884         .get_ethtool_stats      = cpsw_get_ethtool_stats,
1885         .get_pauseparam         = cpsw_get_pauseparam,
1886         .set_pauseparam         = cpsw_set_pauseparam,
1887         .get_wol        = cpsw_get_wol,
1888         .set_wol        = cpsw_set_wol,
1889         .get_regs_len   = cpsw_get_regs_len,
1890         .get_regs       = cpsw_get_regs,
1891 };
1892
1893 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1894                             u32 slave_reg_ofs, u32 sliver_reg_ofs)
1895 {
1896         void __iomem            *regs = priv->regs;
1897         int                     slave_num = slave->slave_num;
1898         struct cpsw_slave_data  *data = priv->data.slave_data + slave_num;
1899
1900         slave->data     = data;
1901         slave->regs     = regs + slave_reg_ofs;
1902         slave->sliver   = regs + sliver_reg_ofs;
1903         slave->port_vlan = data->dual_emac_res_vlan;
1904 }
1905
1906 static int cpsw_probe_dt(struct cpsw_platform_data *data,
1907                          struct platform_device *pdev)
1908 {
1909         struct device_node *node = pdev->dev.of_node;
1910         struct device_node *slave_node;
1911         int i = 0, ret;
1912         u32 prop;
1913
1914         if (!node)
1915                 return -EINVAL;
1916
1917         if (of_property_read_u32(node, "slaves", &prop)) {
1918                 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
1919                 return -EINVAL;
1920         }
1921         data->slaves = prop;
1922
1923         if (of_property_read_u32(node, "active_slave", &prop)) {
1924                 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
1925                 return -EINVAL;
1926         }
1927         data->active_slave = prop;
1928
1929         if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
1930                 dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n");
1931                 return -EINVAL;
1932         }
1933         data->cpts_clock_mult = prop;
1934
1935         if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
1936                 dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n");
1937                 return -EINVAL;
1938         }
1939         data->cpts_clock_shift = prop;
1940
1941         data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
1942                                         * sizeof(struct cpsw_slave_data),
1943                                         GFP_KERNEL);
1944         if (!data->slave_data)
1945                 return -ENOMEM;
1946
1947         if (of_property_read_u32(node, "cpdma_channels", &prop)) {
1948                 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
1949                 return -EINVAL;
1950         }
1951         data->channels = prop;
1952
1953         if (of_property_read_u32(node, "ale_entries", &prop)) {
1954                 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
1955                 return -EINVAL;
1956         }
1957         data->ale_entries = prop;
1958
1959         if (of_property_read_u32(node, "bd_ram_size", &prop)) {
1960                 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
1961                 return -EINVAL;
1962         }
1963         data->bd_ram_size = prop;
1964
1965         if (of_property_read_u32(node, "rx_descs", &prop)) {
1966                 dev_err(&pdev->dev, "Missing rx_descs property in the DT.\n");
1967                 return -EINVAL;
1968         }
1969         data->rx_descs = prop;
1970
1971         if (of_property_read_u32(node, "mac_control", &prop)) {
1972                 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
1973                 return -EINVAL;
1974         }
1975         data->mac_control = prop;
1976
1977         if (of_property_read_bool(node, "dual_emac"))
1978                 data->dual_emac = 1;
1979
1980         /*
1981          * Populate all the child nodes here...
1982          */
1983         ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
1984         /* We do not want to force this, as in some cases may not have child */
1985         if (ret)
1986                 dev_warn(&pdev->dev, "Doesn't have any child node\n");
1987
1988         for_each_child_of_node(node, slave_node) {
1989                 struct cpsw_slave_data *slave_data = data->slave_data + i;
1990                 const void *mac_addr = NULL;
1991                 u32 phyid;
1992                 int lenp;
1993                 const __be32 *parp;
1994                 struct device_node *mdio_node;
1995                 struct platform_device *mdio;
1996
1997                 /* This is no slave child node, continue */
1998                 if (strcmp(slave_node->name, "slave"))
1999                         continue;
2000
2001                 parp = of_get_property(slave_node, "phy_id", &lenp);
2002                 if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) {
2003                         dev_err(&pdev->dev, "Missing slave[%d] phy_id property\n", i);
2004                         goto no_phy_slave;
2005                 }
2006                 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2007                 phyid = be32_to_cpup(parp+1);
2008                 mdio = of_find_device_by_node(mdio_node);
2009                 of_node_put(mdio_node);
2010                 if (!mdio) {
2011                         dev_err(&pdev->dev, "Missing mdio platform device\n");
2012                         return -EINVAL;
2013                 }
2014                 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2015                          PHY_ID_FMT, mdio->name, phyid);
2016
2017                 slave_data->phy_if = of_get_phy_mode(slave_node);
2018                 if (slave_data->phy_if < 0) {
2019                         dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2020                                 i);
2021                         return slave_data->phy_if;
2022                 }
2023
2024 no_phy_slave:
2025                 mac_addr = of_get_mac_address(slave_node);
2026                 if (mac_addr) {
2027                         memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
2028                 } else {
2029                         if (of_machine_is_compatible("ti,am33xx")) {
2030                                 ret = cpsw_am33xx_cm_get_macid(&pdev->dev,
2031                                                         0x630, i,
2032                                                         slave_data->mac_addr);
2033                                 if (ret)
2034                                         return ret;
2035                         }
2036                 }
2037                 if (data->dual_emac) {
2038                         if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
2039                                                  &prop)) {
2040                                 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
2041                                 slave_data->dual_emac_res_vlan = i+1;
2042                                 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2043                                         slave_data->dual_emac_res_vlan, i);
2044                         } else {
2045                                 slave_data->dual_emac_res_vlan = prop;
2046                         }
2047                 }
2048
2049                 i++;
2050                 if (i == data->slaves)
2051                         break;
2052         }
2053
2054         return 0;
2055 }
2056
2057 static int cpsw_probe_dual_emac(struct platform_device *pdev,
2058                                 struct cpsw_priv *priv)
2059 {
2060         struct cpsw_platform_data       *data = &priv->data;
2061         struct net_device               *ndev;
2062         struct cpsw_priv                *priv_sl2;
2063         int ret = 0, i;
2064
2065         ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2066         if (!ndev) {
2067                 dev_err(&pdev->dev, "cpsw: error allocating net_device\n");
2068                 return -ENOMEM;
2069         }
2070
2071         priv_sl2 = netdev_priv(ndev);
2072         spin_lock_init(&priv_sl2->lock);
2073         priv_sl2->data = *data;
2074         priv_sl2->pdev = pdev;
2075         priv_sl2->ndev = ndev;
2076         priv_sl2->dev  = &ndev->dev;
2077         priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2078         priv_sl2->rx_packet_max = max(rx_packet_max, 128);
2079
2080         if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2081                 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2082                         ETH_ALEN);
2083                 dev_info(&pdev->dev, "cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
2084         } else {
2085                 random_ether_addr(priv_sl2->mac_addr);
2086                 dev_info(&pdev->dev, "cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
2087         }
2088         memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2089
2090         priv_sl2->slaves = priv->slaves;
2091         priv_sl2->clk = priv->clk;
2092
2093         priv_sl2->coal_intvl = 0;
2094         priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
2095
2096         priv_sl2->regs = priv->regs;
2097         priv_sl2->host_port = priv->host_port;
2098         priv_sl2->host_port_regs = priv->host_port_regs;
2099         priv_sl2->wr_regs = priv->wr_regs;
2100         priv_sl2->hw_stats = priv->hw_stats;
2101         priv_sl2->dma = priv->dma;
2102         priv_sl2->txch = priv->txch;
2103         priv_sl2->rxch = priv->rxch;
2104         priv_sl2->ale = priv->ale;
2105         priv_sl2->emac_port = 1;
2106         priv->slaves[1].ndev = ndev;
2107         priv_sl2->cpts = priv->cpts;
2108         priv_sl2->version = priv->version;
2109
2110         for (i = 0; i < priv->num_irqs; i++) {
2111                 priv_sl2->irqs_table[i] = priv->irqs_table[i];
2112                 priv_sl2->num_irqs = priv->num_irqs;
2113         }
2114         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2115
2116         ndev->netdev_ops = &cpsw_netdev_ops;
2117         ndev->ethtool_ops = &cpsw_ethtool_ops;
2118
2119         /* register the network device */
2120         SET_NETDEV_DEV(ndev, &pdev->dev);
2121         ret = register_netdev(ndev);
2122         if (ret) {
2123                 dev_err(&pdev->dev, "cpsw: error registering net device\n");
2124                 free_netdev(ndev);
2125                 ret = -ENODEV;
2126         }
2127
2128         return ret;
2129 }
2130
2131 static int cpsw_probe(struct platform_device *pdev)
2132 {
2133         struct cpsw_platform_data       *data;
2134         struct net_device               *ndev;
2135         struct cpsw_priv                *priv;
2136         struct cpdma_params             dma_params;
2137         struct cpsw_ale_params          ale_params;
2138         void __iomem                    *ss_regs;
2139         struct resource                 *res, *ss_res;
2140         u32 slave_offset, sliver_offset, slave_size;
2141         int ret = 0, i;
2142         int irq;
2143
2144         ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2145         if (!ndev) {
2146                 dev_err(&pdev->dev, "error allocating net_device\n");
2147                 return -ENOMEM;
2148         }
2149
2150         platform_set_drvdata(pdev, ndev);
2151         priv = netdev_priv(ndev);
2152         spin_lock_init(&priv->lock);
2153         priv->pdev = pdev;
2154         priv->ndev = ndev;
2155         priv->dev  = &ndev->dev;
2156         priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2157         priv->rx_packet_max = max(rx_packet_max, 128);
2158         priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
2159         if (!priv->cpts) {
2160                 dev_err(&pdev->dev, "error allocating cpts\n");
2161                 ret = -ENOMEM;
2162                 goto clean_ndev_ret;
2163         }
2164
2165         /*
2166          * This may be required here for child devices.
2167          */
2168         pm_runtime_enable(&pdev->dev);
2169
2170         /* Select default pin state */
2171         pinctrl_pm_select_default_state(&pdev->dev);
2172
2173         if (cpsw_probe_dt(&priv->data, pdev)) {
2174                 dev_err(&pdev->dev, "cpsw: platform data missing\n");
2175                 ret = -ENODEV;
2176                 goto clean_runtime_disable_ret;
2177         }
2178         data = &priv->data;
2179
2180         if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2181                 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
2182                 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
2183         } else {
2184                 eth_random_addr(priv->mac_addr);
2185                 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
2186         }
2187
2188         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2189
2190         priv->slaves = devm_kzalloc(&pdev->dev,
2191                                     sizeof(struct cpsw_slave) * data->slaves,
2192                                     GFP_KERNEL);
2193         if (!priv->slaves) {
2194                 ret = -ENOMEM;
2195                 goto clean_runtime_disable_ret;
2196         }
2197         for (i = 0; i < data->slaves; i++)
2198                 priv->slaves[i].slave_num = i;
2199
2200         priv->slaves[0].ndev = ndev;
2201         priv->emac_port = 0;
2202
2203         priv->clk = devm_clk_get(&pdev->dev, "fck");
2204         if (IS_ERR(priv->clk)) {
2205                 dev_err(priv->dev, "fck is not found\n");
2206                 ret = -ENODEV;
2207                 goto clean_runtime_disable_ret;
2208         }
2209         priv->coal_intvl = 0;
2210         priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
2211
2212         ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2213         ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2214         if (IS_ERR(ss_regs)) {
2215                 ret = PTR_ERR(ss_regs);
2216                 goto clean_runtime_disable_ret;
2217         }
2218         priv->regs = ss_regs;
2219         priv->host_port = HOST_PORT_NUM;
2220
2221         /* Need to enable clocks with runtime PM api to access module
2222          * registers
2223          */
2224         pm_runtime_get_sync(&pdev->dev);
2225         priv->version = readl(&priv->regs->id_ver);
2226         pm_runtime_put_sync(&pdev->dev);
2227
2228         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2229         priv->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2230         if (IS_ERR(priv->wr_regs)) {
2231                 ret = PTR_ERR(priv->wr_regs);
2232                 goto clean_runtime_disable_ret;
2233         }
2234
2235         memset(&dma_params, 0, sizeof(dma_params));
2236         memset(&ale_params, 0, sizeof(ale_params));
2237
2238         switch (priv->version) {
2239         case CPSW_VERSION_1:
2240                 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
2241                 priv->cpts->reg      = ss_regs + CPSW1_CPTS_OFFSET;
2242                 priv->hw_stats       = ss_regs + CPSW1_HW_STATS;
2243                 dma_params.dmaregs   = ss_regs + CPSW1_CPDMA_OFFSET;
2244                 dma_params.txhdp     = ss_regs + CPSW1_STATERAM_OFFSET;
2245                 ale_params.ale_regs  = ss_regs + CPSW1_ALE_OFFSET;
2246                 slave_offset         = CPSW1_SLAVE_OFFSET;
2247                 slave_size           = CPSW1_SLAVE_SIZE;
2248                 sliver_offset        = CPSW1_SLIVER_OFFSET;
2249                 dma_params.desc_mem_phys = 0;
2250                 break;
2251         case CPSW_VERSION_2:
2252         case CPSW_VERSION_3:
2253         case CPSW_VERSION_4:
2254                 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
2255                 priv->cpts->reg      = ss_regs + CPSW2_CPTS_OFFSET;
2256                 priv->hw_stats       = ss_regs + CPSW2_HW_STATS;
2257                 dma_params.dmaregs   = ss_regs + CPSW2_CPDMA_OFFSET;
2258                 dma_params.txhdp     = ss_regs + CPSW2_STATERAM_OFFSET;
2259                 ale_params.ale_regs  = ss_regs + CPSW2_ALE_OFFSET;
2260                 slave_offset         = CPSW2_SLAVE_OFFSET;
2261                 slave_size           = CPSW2_SLAVE_SIZE;
2262                 sliver_offset        = CPSW2_SLIVER_OFFSET;
2263                 dma_params.desc_mem_phys =
2264                         (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
2265                 break;
2266         default:
2267                 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
2268                 ret = -ENODEV;
2269                 goto clean_runtime_disable_ret;
2270         }
2271         for (i = 0; i < priv->data.slaves; i++) {
2272                 struct cpsw_slave *slave = &priv->slaves[i];
2273                 cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
2274                 slave_offset  += slave_size;
2275                 sliver_offset += SLIVER_SIZE;
2276         }
2277
2278         dma_params.dev          = &pdev->dev;
2279         dma_params.rxthresh     = dma_params.dmaregs + CPDMA_RXTHRESH;
2280         dma_params.rxfree       = dma_params.dmaregs + CPDMA_RXFREE;
2281         dma_params.rxhdp        = dma_params.txhdp + CPDMA_RXHDP;
2282         dma_params.txcp         = dma_params.txhdp + CPDMA_TXCP;
2283         dma_params.rxcp         = dma_params.txhdp + CPDMA_RXCP;
2284
2285         dma_params.num_chan             = data->channels;
2286         dma_params.has_soft_reset       = true;
2287         dma_params.min_packet_size      = CPSW_MIN_PACKET_SIZE;
2288         dma_params.desc_mem_size        = data->bd_ram_size;
2289         dma_params.desc_align           = 16;
2290         dma_params.has_ext_regs         = true;
2291         dma_params.desc_hw_addr         = dma_params.desc_mem_phys;
2292
2293         priv->dma = cpdma_ctlr_create(&dma_params);
2294         if (!priv->dma) {
2295                 dev_err(priv->dev, "error initializing dma\n");
2296                 ret = -ENOMEM;
2297                 goto clean_runtime_disable_ret;
2298         }
2299
2300         priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
2301                                        cpsw_tx_handler);
2302         priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
2303                                        cpsw_rx_handler);
2304
2305         if (WARN_ON(!priv->txch || !priv->rxch)) {
2306                 dev_err(priv->dev, "error initializing dma channels\n");
2307                 ret = -ENOMEM;
2308                 goto clean_dma_ret;
2309         }
2310
2311         ale_params.dev                  = &ndev->dev;
2312         ale_params.ale_ageout           = ale_ageout;
2313         ale_params.ale_entries          = data->ale_entries;
2314         ale_params.ale_ports            = data->slaves;
2315
2316         priv->ale = cpsw_ale_create(&ale_params);
2317         if (!priv->ale) {
2318                 dev_err(priv->dev, "error initializing ale engine\n");
2319                 ret = -ENODEV;
2320                 goto clean_dma_ret;
2321         }
2322
2323         ndev->irq = platform_get_irq(pdev, 1);
2324         if (ndev->irq < 0) {
2325                 dev_err(priv->dev, "error getting irq resource\n");
2326                 ret = -ENOENT;
2327                 goto clean_ale_ret;
2328         }
2329
2330         /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
2331          * MISC IRQs which are always kept disabled with this driver so
2332          * we will not request them.
2333          *
2334          * If anyone wants to implement support for those, make sure to
2335          * first request and append them to irqs_table array.
2336          */
2337
2338         /* RX IRQ */
2339         irq = platform_get_irq(pdev, 1);
2340         if (irq < 0)
2341                 goto clean_ale_ret;
2342
2343         priv->irqs_table[0] = irq;
2344         ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
2345                                0, dev_name(&pdev->dev), priv);
2346         if (ret < 0) {
2347                 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2348                 goto clean_ale_ret;
2349         }
2350
2351         /* TX IRQ */
2352         irq = platform_get_irq(pdev, 2);
2353         if (irq < 0)
2354                 goto clean_ale_ret;
2355
2356         priv->irqs_table[1] = irq;
2357         ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
2358                                0, dev_name(&pdev->dev), priv);
2359         if (ret < 0) {
2360                 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2361                 goto clean_ale_ret;
2362         }
2363         priv->num_irqs = 2;
2364
2365         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2366
2367         ndev->netdev_ops = &cpsw_netdev_ops;
2368         ndev->ethtool_ops = &cpsw_ethtool_ops;
2369         netif_napi_add(ndev, &priv->napi_rx, cpsw_rx_poll, CPSW_POLL_WEIGHT);
2370         netif_napi_add(ndev, &priv->napi_tx, cpsw_tx_poll, CPSW_POLL_WEIGHT);
2371
2372         /* register the network device */
2373         SET_NETDEV_DEV(ndev, &pdev->dev);
2374         ret = register_netdev(ndev);
2375         if (ret) {
2376                 dev_err(priv->dev, "error registering net device\n");
2377                 ret = -ENODEV;
2378                 goto clean_ale_ret;
2379         }
2380
2381         cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
2382                     &ss_res->start, ndev->irq);
2383
2384         if (priv->data.dual_emac) {
2385                 ret = cpsw_probe_dual_emac(pdev, priv);
2386                 if (ret) {
2387                         cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
2388                         goto clean_ale_ret;
2389                 }
2390         }
2391
2392         return 0;
2393
2394 clean_ale_ret:
2395         cpsw_ale_destroy(priv->ale);
2396 clean_dma_ret:
2397         cpdma_chan_destroy(priv->txch);
2398         cpdma_chan_destroy(priv->rxch);
2399         cpdma_ctlr_destroy(priv->dma);
2400 clean_runtime_disable_ret:
2401         pm_runtime_disable(&pdev->dev);
2402 clean_ndev_ret:
2403         free_netdev(priv->ndev);
2404         return ret;
2405 }
2406
2407 static int cpsw_remove_child_device(struct device *dev, void *c)
2408 {
2409         struct platform_device *pdev = to_platform_device(dev);
2410
2411         of_device_unregister(pdev);
2412
2413         return 0;
2414 }
2415
2416 static int cpsw_remove(struct platform_device *pdev)
2417 {
2418         struct net_device *ndev = platform_get_drvdata(pdev);
2419         struct cpsw_priv *priv = netdev_priv(ndev);
2420
2421         if (priv->data.dual_emac)
2422                 unregister_netdev(cpsw_get_slave_ndev(priv, 1));
2423         unregister_netdev(ndev);
2424
2425         cpsw_ale_destroy(priv->ale);
2426         cpdma_chan_destroy(priv->txch);
2427         cpdma_chan_destroy(priv->rxch);
2428         cpdma_ctlr_destroy(priv->dma);
2429         pm_runtime_disable(&pdev->dev);
2430         device_for_each_child(&pdev->dev, NULL, cpsw_remove_child_device);
2431         if (priv->data.dual_emac)
2432                 free_netdev(cpsw_get_slave_ndev(priv, 1));
2433         free_netdev(ndev);
2434         return 0;
2435 }
2436
2437 #ifdef CONFIG_PM_SLEEP
2438 static int cpsw_suspend(struct device *dev)
2439 {
2440         struct platform_device  *pdev = to_platform_device(dev);
2441         struct net_device       *ndev = platform_get_drvdata(pdev);
2442         struct cpsw_priv        *priv = netdev_priv(ndev);
2443
2444         if (priv->data.dual_emac) {
2445                 int i;
2446
2447                 for (i = 0; i < priv->data.slaves; i++) {
2448                         if (netif_running(priv->slaves[i].ndev))
2449                                 cpsw_ndo_stop(priv->slaves[i].ndev);
2450                         soft_reset_slave(priv->slaves + i);
2451                 }
2452         } else {
2453                 if (netif_running(ndev))
2454                         cpsw_ndo_stop(ndev);
2455                 for_each_slave(priv, soft_reset_slave);
2456         }
2457
2458         pm_runtime_put_sync(&pdev->dev);
2459
2460         /* Select sleep pin state */
2461         pinctrl_pm_select_sleep_state(&pdev->dev);
2462
2463         return 0;
2464 }
2465
2466 static int cpsw_resume(struct device *dev)
2467 {
2468         struct platform_device  *pdev = to_platform_device(dev);
2469         struct net_device       *ndev = platform_get_drvdata(pdev);
2470         struct cpsw_priv        *priv = netdev_priv(ndev);
2471
2472         pm_runtime_get_sync(&pdev->dev);
2473
2474         /* Select default pin state */
2475         pinctrl_pm_select_default_state(&pdev->dev);
2476
2477         if (priv->data.dual_emac) {
2478                 int i;
2479
2480                 for (i = 0; i < priv->data.slaves; i++) {
2481                         if (netif_running(priv->slaves[i].ndev))
2482                                 cpsw_ndo_open(priv->slaves[i].ndev);
2483                 }
2484         } else {
2485                 if (netif_running(ndev))
2486                         cpsw_ndo_open(ndev);
2487         }
2488         return 0;
2489 }
2490 #endif
2491
2492 static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
2493
2494 static const struct of_device_id cpsw_of_mtable[] = {
2495         { .compatible = "ti,cpsw", },
2496         { /* sentinel */ },
2497 };
2498 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2499
2500 static struct platform_driver cpsw_driver = {
2501         .driver = {
2502                 .name    = "cpsw",
2503                 .pm      = &cpsw_pm_ops,
2504                 .of_match_table = cpsw_of_mtable,
2505         },
2506         .probe = cpsw_probe,
2507         .remove = cpsw_remove,
2508 };
2509
2510 static int __init cpsw_init(void)
2511 {
2512         return platform_driver_register(&cpsw_driver);
2513 }
2514 late_initcall(cpsw_init);
2515
2516 static void __exit cpsw_exit(void)
2517 {
2518         platform_driver_unregister(&cpsw_driver);
2519 }
2520 module_exit(cpsw_exit);
2521
2522 MODULE_LICENSE("GPL");
2523 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2524 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2525 MODULE_DESCRIPTION("TI CPSW Ethernet driver");