2 * Texas Instruments Ethernet Switch Driver
4 * Copyright (C) 2012 Texas Instruments
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/kernel.h>
18 #include <linux/clk.h>
19 #include <linux/timer.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/irqreturn.h>
23 #include <linux/interrupt.h>
24 #include <linux/if_ether.h>
25 #include <linux/etherdevice.h>
26 #include <linux/netdevice.h>
27 #include <linux/net_tstamp.h>
28 #include <linux/phy.h>
29 #include <linux/workqueue.h>
30 #include <linux/delay.h>
31 #include <linux/pm_runtime.h>
33 #include <linux/of_net.h>
34 #include <linux/of_device.h>
35 #include <linux/if_vlan.h>
37 #include <linux/pinctrl/consumer.h>
42 #include "davinci_cpdma.h"
44 #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
45 NETIF_MSG_DRV | NETIF_MSG_LINK | \
46 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
47 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
48 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
49 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
50 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
53 #define cpsw_info(priv, type, format, ...) \
55 if (netif_msg_##type(priv) && net_ratelimit()) \
56 dev_info(priv->dev, format, ## __VA_ARGS__); \
59 #define cpsw_err(priv, type, format, ...) \
61 if (netif_msg_##type(priv) && net_ratelimit()) \
62 dev_err(priv->dev, format, ## __VA_ARGS__); \
65 #define cpsw_dbg(priv, type, format, ...) \
67 if (netif_msg_##type(priv) && net_ratelimit()) \
68 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
71 #define cpsw_notice(priv, type, format, ...) \
73 if (netif_msg_##type(priv) && net_ratelimit()) \
74 dev_notice(priv->dev, format, ## __VA_ARGS__); \
77 #define ALE_ALL_PORTS 0x7
79 #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
80 #define CPSW_MINOR_VERSION(reg) (reg & 0xff)
81 #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
83 #define CPSW_VERSION_1 0x19010a
84 #define CPSW_VERSION_2 0x19010c
85 #define CPSW_VERSION_3 0x19010f
86 #define CPSW_VERSION_4 0x190112
88 #define HOST_PORT_NUM 0
89 #define SLIVER_SIZE 0x40
91 #define CPSW1_HOST_PORT_OFFSET 0x028
92 #define CPSW1_SLAVE_OFFSET 0x050
93 #define CPSW1_SLAVE_SIZE 0x040
94 #define CPSW1_CPDMA_OFFSET 0x100
95 #define CPSW1_STATERAM_OFFSET 0x200
96 #define CPSW1_HW_STATS 0x400
97 #define CPSW1_CPTS_OFFSET 0x500
98 #define CPSW1_ALE_OFFSET 0x600
99 #define CPSW1_SLIVER_OFFSET 0x700
101 #define CPSW2_HOST_PORT_OFFSET 0x108
102 #define CPSW2_SLAVE_OFFSET 0x200
103 #define CPSW2_SLAVE_SIZE 0x100
104 #define CPSW2_CPDMA_OFFSET 0x800
105 #define CPSW2_HW_STATS 0x900
106 #define CPSW2_STATERAM_OFFSET 0xa00
107 #define CPSW2_CPTS_OFFSET 0xc00
108 #define CPSW2_ALE_OFFSET 0xd00
109 #define CPSW2_SLIVER_OFFSET 0xd80
110 #define CPSW2_BD_OFFSET 0x2000
112 #define CPDMA_RXTHRESH 0x0c0
113 #define CPDMA_RXFREE 0x0e0
114 #define CPDMA_TXHDP 0x00
115 #define CPDMA_RXHDP 0x20
116 #define CPDMA_TXCP 0x40
117 #define CPDMA_RXCP 0x60
119 #define CPSW_POLL_WEIGHT 64
120 #define CPSW_MIN_PACKET_SIZE 60
121 #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4)
123 #define RX_PRIORITY_MAPPING 0x76543210
124 #define TX_PRIORITY_MAPPING 0x33221100
125 #define CPDMA_TX_PRIORITY_MAP 0x76543210
127 #define CPSW_VLAN_AWARE BIT(1)
128 #define CPSW_ALE_VLAN_AWARE 1
130 #define CPSW_FIFO_NORMAL_MODE (0 << 16)
131 #define CPSW_FIFO_DUAL_MAC_MODE (1 << 16)
132 #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16)
134 #define CPSW_INTPACEEN (0x3f << 16)
135 #define CPSW_INTPRESCALE_MASK (0x7FF << 0)
136 #define CPSW_CMINTMAX_CNT 63
137 #define CPSW_CMINTMIN_CNT 2
138 #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
139 #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
141 #define cpsw_slave_index(priv) \
142 ((priv->data.dual_emac) ? priv->emac_port : \
143 priv->data.active_slave)
145 static int debug_level;
146 module_param(debug_level, int, 0);
147 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
149 static int ale_ageout = 10;
150 module_param(ale_ageout, int, 0);
151 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
153 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
154 module_param(rx_packet_max, int, 0);
155 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
157 struct cpsw_wr_regs {
177 struct cpsw_ss_regs {
194 #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
195 #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
196 #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
197 #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
198 #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
199 #define CPSW1_TS_CTL 0x14 /* Time Sync Control */
200 #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
201 #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
204 #define CPSW2_CONTROL 0x00 /* Control Register */
205 #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
206 #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
207 #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
208 #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
209 #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
210 #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
212 /* CPSW_PORT_V1 and V2 */
213 #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
214 #define SA_HI 0x24 /* CPGMAC_SL Source Address High */
215 #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
217 /* CPSW_PORT_V2 only */
218 #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
219 #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
220 #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
221 #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
222 #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
223 #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
224 #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
225 #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
227 /* Bit definitions for the CPSW2_CONTROL register */
228 #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */
229 #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */
230 #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */
231 #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */
232 #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */
233 #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */
234 #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */
235 #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */
236 #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */
237 #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */
238 #define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */
239 #define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */
240 #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */
241 #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */
242 #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */
243 #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */
244 #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */
246 #define CTRL_V2_TS_BITS \
247 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
248 TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN)
250 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
251 #define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN)
252 #define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN)
255 #define CTRL_V3_TS_BITS \
256 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
257 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
260 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
261 #define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN)
262 #define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN)
264 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
265 #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
266 #define TS_SEQ_ID_OFFSET_MASK (0x3f)
267 #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
268 #define TS_MSG_TYPE_EN_MASK (0xffff)
270 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
271 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
273 /* Bit definitions for the CPSW1_TS_CTL register */
274 #define CPSW_V1_TS_RX_EN BIT(0)
275 #define CPSW_V1_TS_TX_EN BIT(4)
276 #define CPSW_V1_MSG_TYPE_OFS 16
278 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
279 #define CPSW_V1_SEQ_ID_OFS_SHIFT 16
281 struct cpsw_host_regs {
287 u32 cpdma_tx_pri_map;
288 u32 cpdma_rx_chan_map;
291 struct cpsw_sliver_regs {
304 struct cpsw_hw_stats {
306 u32 rxbroadcastframes;
307 u32 rxmulticastframes;
310 u32 rxaligncodeerrors;
311 u32 rxoversizedframes;
313 u32 rxundersizedframes;
318 u32 txbroadcastframes;
319 u32 txmulticastframes;
321 u32 txdeferredframes;
322 u32 txcollisionframes;
323 u32 txsinglecollframes;
324 u32 txmultcollframes;
325 u32 txexcessivecollisions;
326 u32 txlatecollisions;
328 u32 txcarriersenseerrors;
331 u32 octetframes65t127;
332 u32 octetframes128t255;
333 u32 octetframes256t511;
334 u32 octetframes512t1023;
335 u32 octetframes1024tup;
344 struct cpsw_sliver_regs __iomem *sliver;
347 struct cpsw_slave_data *data;
348 struct phy_device *phy;
349 struct net_device *ndev;
354 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
356 return __raw_readl(slave->regs + offset);
359 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
361 __raw_writel(val, slave->regs + offset);
366 struct platform_device *pdev;
367 struct net_device *ndev;
368 struct napi_struct napi;
370 struct cpsw_platform_data data;
371 struct cpsw_ss_regs __iomem *regs;
372 struct cpsw_wr_regs __iomem *wr_regs;
373 u8 __iomem *hw_stats;
374 struct cpsw_host_regs __iomem *host_port_regs;
382 u8 mac_addr[ETH_ALEN];
383 struct cpsw_slave *slaves;
384 struct cpdma_ctlr *dma;
385 struct cpdma_chan *txch, *rxch;
386 struct cpsw_ale *ale;
389 /* snapshot of IRQ numbers */
398 char stat_string[ETH_GSTRING_LEN];
410 #define CPSW_STAT(m) CPSW_STATS, \
411 sizeof(((struct cpsw_hw_stats *)0)->m), \
412 offsetof(struct cpsw_hw_stats, m)
413 #define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \
414 sizeof(((struct cpdma_chan_stats *)0)->m), \
415 offsetof(struct cpdma_chan_stats, m)
416 #define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \
417 sizeof(((struct cpdma_chan_stats *)0)->m), \
418 offsetof(struct cpdma_chan_stats, m)
420 static const struct cpsw_stats cpsw_gstrings_stats[] = {
421 { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
422 { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
423 { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
424 { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
425 { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
426 { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
427 { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
428 { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
429 { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
430 { "Rx Fragments", CPSW_STAT(rxfragments) },
431 { "Rx Octets", CPSW_STAT(rxoctets) },
432 { "Good Tx Frames", CPSW_STAT(txgoodframes) },
433 { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
434 { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
435 { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
436 { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
437 { "Collisions", CPSW_STAT(txcollisionframes) },
438 { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
439 { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
440 { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
441 { "Late Collisions", CPSW_STAT(txlatecollisions) },
442 { "Tx Underrun", CPSW_STAT(txunderrun) },
443 { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
444 { "Tx Octets", CPSW_STAT(txoctets) },
445 { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
446 { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
447 { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
448 { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
449 { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
450 { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
451 { "Net Octets", CPSW_STAT(netoctets) },
452 { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
453 { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
454 { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
455 { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) },
456 { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
457 { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
458 { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) },
459 { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
460 { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
461 { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
462 { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
463 { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
464 { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
465 { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) },
466 { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) },
467 { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
468 { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) },
469 { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) },
470 { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) },
471 { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) },
472 { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) },
473 { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) },
474 { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) },
475 { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) },
476 { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) },
477 { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) },
478 { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) },
479 { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) },
480 { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) },
483 #define CPSW_STATS_LEN ARRAY_SIZE(cpsw_gstrings_stats)
485 #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
486 #define for_each_slave(priv, func, arg...) \
488 struct cpsw_slave *slave; \
490 if (priv->data.dual_emac) \
491 (func)((priv)->slaves + priv->emac_port, ##arg);\
493 for (n = (priv)->data.slaves, \
494 slave = (priv)->slaves; \
496 (func)(slave++, ##arg); \
498 #define cpsw_get_slave_ndev(priv, __slave_no__) \
499 ((__slave_no__ < priv->data.slaves) ? \
500 priv->slaves[__slave_no__].ndev : NULL)
501 #define cpsw_get_slave_priv(priv, __slave_no__) \
502 (((__slave_no__ < priv->data.slaves) && \
503 (priv->slaves[__slave_no__].ndev)) ? \
504 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \
506 #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \
508 if (!priv->data.dual_emac) \
510 if (CPDMA_RX_SOURCE_PORT(status) == 1) { \
511 ndev = cpsw_get_slave_ndev(priv, 0); \
512 priv = netdev_priv(ndev); \
514 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \
515 ndev = cpsw_get_slave_ndev(priv, 1); \
516 priv = netdev_priv(ndev); \
520 #define cpsw_add_mcast(priv, addr) \
522 if (priv->data.dual_emac) { \
523 struct cpsw_slave *slave = priv->slaves + \
525 int slave_port = cpsw_get_slave_port(priv, \
527 cpsw_ale_add_mcast(priv->ale, addr, \
528 1 << slave_port | 1 << priv->host_port, \
529 ALE_VLAN, slave->port_vlan, 0); \
531 cpsw_ale_add_mcast(priv->ale, addr, \
532 ALE_ALL_PORTS << priv->host_port, \
537 static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
539 if (priv->host_port == 0)
540 return slave_num + 1;
545 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
547 struct cpsw_priv *priv = netdev_priv(ndev);
548 struct cpsw_ale *ale = priv->ale;
551 if (priv->data.dual_emac) {
554 /* Enabling promiscuous mode for one interface will be
555 * common for both the interface as the interface shares
556 * the same hardware resource.
558 for (i = 0; i < priv->data.slaves; i++)
559 if (priv->slaves[i].ndev->flags & IFF_PROMISC)
562 if (!enable && flag) {
564 dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
569 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
571 dev_dbg(&ndev->dev, "promiscuity enabled\n");
574 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
575 dev_dbg(&ndev->dev, "promiscuity disabled\n");
579 unsigned long timeout = jiffies + HZ;
581 /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
582 for (i = 0; i <= priv->data.slaves; i++) {
583 cpsw_ale_control_set(ale, i,
584 ALE_PORT_NOLEARN, 1);
585 cpsw_ale_control_set(ale, i,
586 ALE_PORT_NO_SA_UPDATE, 1);
589 /* Clear All Untouched entries */
590 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
593 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
595 } while (time_after(timeout, jiffies));
596 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
598 /* Clear all mcast from ALE */
599 cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS <<
600 priv->host_port, -1);
602 /* Flood All Unicast Packets to Host port */
603 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
604 dev_dbg(&ndev->dev, "promiscuity enabled\n");
606 /* Don't Flood All Unicast Packets to Host port */
607 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
609 /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
610 for (i = 0; i <= priv->data.slaves; i++) {
611 cpsw_ale_control_set(ale, i,
612 ALE_PORT_NOLEARN, 0);
613 cpsw_ale_control_set(ale, i,
614 ALE_PORT_NO_SA_UPDATE, 0);
616 dev_dbg(&ndev->dev, "promiscuity disabled\n");
621 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
623 struct cpsw_priv *priv = netdev_priv(ndev);
626 if (priv->data.dual_emac)
627 vid = priv->slaves[priv->emac_port].port_vlan;
629 vid = priv->data.default_vlan;
631 if (ndev->flags & IFF_PROMISC) {
632 /* Enable promiscuous mode */
633 cpsw_set_promiscious(ndev, true);
634 cpsw_ale_set_allmulti(priv->ale, IFF_ALLMULTI);
637 /* Disable promiscuous mode */
638 cpsw_set_promiscious(ndev, false);
641 /* Restore allmulti on vlans if necessary */
642 cpsw_ale_set_allmulti(priv->ale, priv->ndev->flags & IFF_ALLMULTI);
644 /* Clear all mcast from ALE */
645 cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port,
648 if (!netdev_mc_empty(ndev)) {
649 struct netdev_hw_addr *ha;
651 /* program multicast address list into ALE register */
652 netdev_for_each_mc_addr(ha, ndev) {
653 cpsw_add_mcast(priv, (u8 *)ha->addr);
658 static void cpsw_intr_enable(struct cpsw_priv *priv)
660 __raw_writel(0xFF, &priv->wr_regs->tx_en);
661 __raw_writel(0xFF, &priv->wr_regs->rx_en);
663 cpdma_ctlr_int_ctrl(priv->dma, true);
667 static void cpsw_intr_disable(struct cpsw_priv *priv)
669 __raw_writel(0, &priv->wr_regs->tx_en);
670 __raw_writel(0, &priv->wr_regs->rx_en);
672 cpdma_ctlr_int_ctrl(priv->dma, false);
676 static void cpsw_tx_handler(void *token, int len, int status)
678 struct sk_buff *skb = token;
679 struct net_device *ndev = skb->dev;
680 struct cpsw_priv *priv = netdev_priv(ndev);
682 /* Check whether the queue is stopped due to stalled tx dma, if the
683 * queue is stopped then start the queue as we have free desc for tx
685 if (unlikely(netif_queue_stopped(ndev)))
686 netif_wake_queue(ndev);
687 cpts_tx_timestamp(priv->cpts, skb);
688 ndev->stats.tx_packets++;
689 ndev->stats.tx_bytes += len;
690 dev_kfree_skb_any(skb);
693 static void cpsw_rx_handler(void *token, int len, int status)
695 struct sk_buff *skb = token;
696 struct sk_buff *new_skb;
697 struct net_device *ndev = skb->dev;
698 struct cpsw_priv *priv = netdev_priv(ndev);
701 cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
703 if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
704 bool ndev_status = false;
705 struct cpsw_slave *slave = priv->slaves;
708 if (priv->data.dual_emac) {
709 /* In dual emac mode check for all interfaces */
710 for (n = priv->data.slaves; n; n--, slave++)
711 if (netif_running(slave->ndev))
715 if (ndev_status && (status >= 0)) {
716 /* The packet received is for the interface which
717 * is already down and the other interface is up
718 * and running, instead of freeing which results
719 * in reducing of the number of rx descriptor in
720 * DMA engine, requeue skb back to cpdma.
726 /* the interface is going down, skbs are purged */
727 dev_kfree_skb_any(skb);
731 new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
734 cpts_rx_timestamp(priv->cpts, skb);
735 skb->protocol = eth_type_trans(skb, ndev);
736 netif_receive_skb(skb);
737 ndev->stats.rx_bytes += len;
738 ndev->stats.rx_packets++;
740 ndev->stats.rx_dropped++;
745 ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
746 skb_tailroom(new_skb), 0);
747 if (WARN_ON(ret < 0))
748 dev_kfree_skb_any(new_skb);
751 static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
753 struct cpsw_priv *priv = dev_id;
755 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
756 cpdma_chan_process(priv->txch, 128);
758 priv = cpsw_get_slave_priv(priv, 1);
760 cpdma_chan_process(priv->txch, 128);
765 static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
767 struct cpsw_priv *priv = dev_id;
769 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
771 cpsw_intr_disable(priv);
772 if (priv->irq_enabled == true) {
773 disable_irq_nosync(priv->irqs_table[0]);
774 priv->irq_enabled = false;
777 if (netif_running(priv->ndev)) {
778 napi_schedule(&priv->napi);
782 priv = cpsw_get_slave_priv(priv, 1);
786 if (netif_running(priv->ndev)) {
787 napi_schedule(&priv->napi);
793 static int cpsw_poll(struct napi_struct *napi, int budget)
795 struct cpsw_priv *priv = napi_to_priv(napi);
798 num_tx = cpdma_chan_process(priv->txch, 128);
800 num_rx = cpdma_chan_process(priv->rxch, budget);
801 if (num_rx < budget) {
802 struct cpsw_priv *prim_cpsw;
805 cpsw_intr_enable(priv);
806 prim_cpsw = cpsw_get_slave_priv(priv, 0);
807 if (prim_cpsw->irq_enabled == false) {
808 prim_cpsw->irq_enabled = true;
809 enable_irq(priv->irqs_table[0]);
813 if (num_rx || num_tx)
814 cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n",
820 static inline void soft_reset(const char *module, void __iomem *reg)
822 unsigned long timeout = jiffies + HZ;
824 __raw_writel(1, reg);
827 } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
829 WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
832 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
833 ((mac)[2] << 16) | ((mac)[3] << 24))
834 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
836 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
837 struct cpsw_priv *priv)
839 slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
840 slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
843 static void _cpsw_adjust_link(struct cpsw_slave *slave,
844 struct cpsw_priv *priv, bool *link)
846 struct phy_device *phy = slave->phy;
853 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
856 mac_control = priv->data.mac_control;
858 /* enable forwarding */
859 cpsw_ale_control_set(priv->ale, slave_port,
860 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
862 if (phy->speed == 1000)
863 mac_control |= BIT(7); /* GIGABITEN */
865 mac_control |= BIT(0); /* FULLDUPLEXEN */
867 /* set speed_in input in case RMII mode is used in 100Mbps */
868 if (phy->speed == 100)
869 mac_control |= BIT(15);
870 else if (phy->speed == 10)
871 mac_control |= BIT(18); /* In Band mode */
874 mac_control |= BIT(3);
877 mac_control |= BIT(4);
882 /* disable forwarding */
883 cpsw_ale_control_set(priv->ale, slave_port,
884 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
887 if (mac_control != slave->mac_control) {
888 phy_print_status(phy);
889 __raw_writel(mac_control, &slave->sliver->mac_control);
892 slave->mac_control = mac_control;
895 static void cpsw_adjust_link(struct net_device *ndev)
897 struct cpsw_priv *priv = netdev_priv(ndev);
900 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
903 netif_carrier_on(ndev);
904 if (netif_running(ndev))
905 netif_wake_queue(ndev);
907 netif_carrier_off(ndev);
908 netif_stop_queue(ndev);
912 static int cpsw_get_coalesce(struct net_device *ndev,
913 struct ethtool_coalesce *coal)
915 struct cpsw_priv *priv = netdev_priv(ndev);
917 coal->rx_coalesce_usecs = priv->coal_intvl;
921 static int cpsw_set_coalesce(struct net_device *ndev,
922 struct ethtool_coalesce *coal)
924 struct cpsw_priv *priv = netdev_priv(ndev);
926 u32 num_interrupts = 0;
931 coal_intvl = coal->rx_coalesce_usecs;
933 int_ctrl = readl(&priv->wr_regs->int_control);
934 prescale = priv->bus_freq_mhz * 4;
936 if (!coal->rx_coalesce_usecs) {
937 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
941 if (coal_intvl < CPSW_CMINTMIN_INTVL)
942 coal_intvl = CPSW_CMINTMIN_INTVL;
944 if (coal_intvl > CPSW_CMINTMAX_INTVL) {
945 /* Interrupt pacer works with 4us Pulse, we can
946 * throttle further by dilating the 4us pulse.
948 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
950 if (addnl_dvdr > 1) {
951 prescale *= addnl_dvdr;
952 if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
953 coal_intvl = (CPSW_CMINTMAX_INTVL
957 coal_intvl = CPSW_CMINTMAX_INTVL;
961 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
962 writel(num_interrupts, &priv->wr_regs->rx_imax);
963 writel(num_interrupts, &priv->wr_regs->tx_imax);
965 int_ctrl |= CPSW_INTPACEEN;
966 int_ctrl &= (~CPSW_INTPRESCALE_MASK);
967 int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
970 writel(int_ctrl, &priv->wr_regs->int_control);
972 cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
973 if (priv->data.dual_emac) {
976 for (i = 0; i < priv->data.slaves; i++) {
977 priv = netdev_priv(priv->slaves[i].ndev);
978 priv->coal_intvl = coal_intvl;
981 priv->coal_intvl = coal_intvl;
987 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
991 return CPSW_STATS_LEN;
997 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1002 switch (stringset) {
1004 for (i = 0; i < CPSW_STATS_LEN; i++) {
1005 memcpy(p, cpsw_gstrings_stats[i].stat_string,
1007 p += ETH_GSTRING_LEN;
1013 static void cpsw_get_ethtool_stats(struct net_device *ndev,
1014 struct ethtool_stats *stats, u64 *data)
1016 struct cpsw_priv *priv = netdev_priv(ndev);
1017 struct cpdma_chan_stats rx_stats;
1018 struct cpdma_chan_stats tx_stats;
1023 /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1024 cpdma_chan_get_stats(priv->rxch, &rx_stats);
1025 cpdma_chan_get_stats(priv->txch, &tx_stats);
1027 for (i = 0; i < CPSW_STATS_LEN; i++) {
1028 switch (cpsw_gstrings_stats[i].type) {
1030 val = readl(priv->hw_stats +
1031 cpsw_gstrings_stats[i].stat_offset);
1035 case CPDMA_RX_STATS:
1036 p = (u8 *)&rx_stats +
1037 cpsw_gstrings_stats[i].stat_offset;
1038 data[i] = *(u32 *)p;
1041 case CPDMA_TX_STATS:
1042 p = (u8 *)&tx_stats +
1043 cpsw_gstrings_stats[i].stat_offset;
1044 data[i] = *(u32 *)p;
1050 static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
1053 u32 usage_count = 0;
1055 if (!priv->data.dual_emac)
1058 for (i = 0; i < priv->data.slaves; i++)
1059 if (priv->slaves[i].open_stat)
1065 static inline int cpsw_tx_packet_submit(struct net_device *ndev,
1066 struct cpsw_priv *priv, struct sk_buff *skb)
1068 if (!priv->data.dual_emac)
1069 return cpdma_chan_submit(priv->txch, skb, skb->data,
1072 if (ndev == cpsw_get_slave_ndev(priv, 0))
1073 return cpdma_chan_submit(priv->txch, skb, skb->data,
1076 return cpdma_chan_submit(priv->txch, skb, skb->data,
1080 static inline void cpsw_add_dual_emac_def_ale_entries(
1081 struct cpsw_priv *priv, struct cpsw_slave *slave,
1084 u32 port_mask = 1 << slave_port | 1 << priv->host_port;
1086 if (priv->version == CPSW_VERSION_1)
1087 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1089 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1090 cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
1091 port_mask, port_mask, 0);
1092 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1093 port_mask, ALE_VLAN, slave->port_vlan, 0);
1094 cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1095 priv->host_port, ALE_VLAN | ALE_SECURE, slave->port_vlan);
1098 static void soft_reset_slave(struct cpsw_slave *slave)
1102 snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1103 soft_reset(name, &slave->sliver->soft_reset);
1106 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1110 soft_reset_slave(slave);
1112 /* setup priority mapping */
1113 __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1115 switch (priv->version) {
1116 case CPSW_VERSION_1:
1117 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1119 case CPSW_VERSION_2:
1120 case CPSW_VERSION_3:
1121 case CPSW_VERSION_4:
1122 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1126 /* setup max packet size, and mac address */
1127 __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
1128 cpsw_set_slave_mac(slave, priv);
1130 slave->mac_control = 0; /* no link yet */
1132 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1134 if (priv->data.dual_emac)
1135 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1137 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1138 1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1140 slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
1141 &cpsw_adjust_link, slave->data->phy_if);
1142 if (IS_ERR(slave->phy)) {
1143 dev_err(priv->dev, "phy %s not found on slave %d\n",
1144 slave->data->phy_id, slave->slave_num);
1147 dev_info(priv->dev, "phy found : id is : 0x%x\n",
1148 slave->phy->phy_id);
1149 phy_start(slave->phy);
1151 /* Configure GMII_SEL register */
1152 cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface,
1157 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1159 const int vlan = priv->data.default_vlan;
1160 const int port = priv->host_port;
1163 int unreg_mcast_mask;
1165 reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1168 writel(vlan, &priv->host_port_regs->port_vlan);
1170 for (i = 0; i < priv->data.slaves; i++)
1171 slave_write(priv->slaves + i, vlan, reg);
1173 if (priv->ndev->flags & IFF_ALLMULTI)
1174 unreg_mcast_mask = ALE_ALL_PORTS;
1176 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1178 cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port,
1179 ALE_ALL_PORTS << port, ALE_ALL_PORTS << port,
1180 unreg_mcast_mask << port);
1183 static void cpsw_init_host_port(struct cpsw_priv *priv)
1188 /* soft reset the controller and initialize ale */
1189 soft_reset("cpsw", &priv->regs->soft_reset);
1190 cpsw_ale_start(priv->ale);
1192 /* switch to vlan unaware mode */
1193 cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE,
1194 CPSW_ALE_VLAN_AWARE);
1195 control_reg = readl(&priv->regs->control);
1196 control_reg |= CPSW_VLAN_AWARE;
1197 writel(control_reg, &priv->regs->control);
1198 fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1199 CPSW_FIFO_NORMAL_MODE;
1200 writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
1202 /* setup host port priority mapping */
1203 __raw_writel(CPDMA_TX_PRIORITY_MAP,
1204 &priv->host_port_regs->cpdma_tx_pri_map);
1205 __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
1207 cpsw_ale_control_set(priv->ale, priv->host_port,
1208 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1210 if (!priv->data.dual_emac) {
1211 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port,
1213 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1214 1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2);
1218 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
1222 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1226 phy_stop(slave->phy);
1227 phy_disconnect(slave->phy);
1229 cpsw_ale_control_set(priv->ale, slave_port,
1230 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1233 static int cpsw_ndo_open(struct net_device *ndev)
1235 struct cpsw_priv *priv = netdev_priv(ndev);
1236 struct cpsw_priv *prim_cpsw;
1240 if (!cpsw_common_res_usage_state(priv))
1241 cpsw_intr_disable(priv);
1242 netif_carrier_off(ndev);
1244 pm_runtime_get_sync(&priv->pdev->dev);
1246 reg = priv->version;
1248 dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1249 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1250 CPSW_RTL_VERSION(reg));
1252 /* initialize host and slave ports */
1253 if (!cpsw_common_res_usage_state(priv))
1254 cpsw_init_host_port(priv);
1255 for_each_slave(priv, cpsw_slave_open, priv);
1257 /* Add default VLAN */
1258 if (!priv->data.dual_emac)
1259 cpsw_add_default_vlan(priv);
1261 cpsw_ale_add_vlan(priv->ale, priv->data.default_vlan,
1262 ALE_ALL_PORTS << priv->host_port,
1263 ALE_ALL_PORTS << priv->host_port, 0, 0);
1265 if (!cpsw_common_res_usage_state(priv)) {
1266 /* setup tx dma to fixed prio and zero offset */
1267 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
1268 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
1270 /* disable priority elevation */
1271 __raw_writel(0, &priv->regs->ptype);
1273 /* enable statistics collection only on all ports */
1274 __raw_writel(0x7, &priv->regs->stat_port_en);
1276 /* Enable internal fifo flow control */
1277 writel(0x7, &priv->regs->flow_control);
1279 if (WARN_ON(!priv->data.rx_descs))
1280 priv->data.rx_descs = 128;
1282 for (i = 0; i < priv->data.rx_descs; i++) {
1283 struct sk_buff *skb;
1286 skb = __netdev_alloc_skb_ip_align(priv->ndev,
1287 priv->rx_packet_max, GFP_KERNEL);
1290 ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
1291 skb_tailroom(skb), 0);
1297 /* continue even if we didn't manage to submit all
1300 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
1302 if (cpts_register(&priv->pdev->dev, priv->cpts,
1303 priv->data.cpts_clock_mult,
1304 priv->data.cpts_clock_shift))
1305 dev_err(priv->dev, "error registering cpts device\n");
1309 /* Enable Interrupt pacing if configured */
1310 if (priv->coal_intvl != 0) {
1311 struct ethtool_coalesce coal;
1313 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1314 cpsw_set_coalesce(ndev, &coal);
1317 napi_enable(&priv->napi);
1318 cpdma_ctlr_start(priv->dma);
1319 cpsw_intr_enable(priv);
1321 prim_cpsw = cpsw_get_slave_priv(priv, 0);
1322 if (prim_cpsw->irq_enabled == false) {
1323 if ((priv == prim_cpsw) || !netif_running(prim_cpsw->ndev)) {
1324 prim_cpsw->irq_enabled = true;
1325 enable_irq(prim_cpsw->irqs_table[0]);
1329 if (priv->data.dual_emac)
1330 priv->slaves[priv->emac_port].open_stat = true;
1334 cpdma_ctlr_stop(priv->dma);
1335 for_each_slave(priv, cpsw_slave_stop, priv);
1336 pm_runtime_put_sync(&priv->pdev->dev);
1337 netif_carrier_off(priv->ndev);
1341 static int cpsw_ndo_stop(struct net_device *ndev)
1343 struct cpsw_priv *priv = netdev_priv(ndev);
1345 cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1346 netif_stop_queue(priv->ndev);
1347 napi_disable(&priv->napi);
1348 netif_carrier_off(priv->ndev);
1350 if (cpsw_common_res_usage_state(priv) <= 1) {
1351 cpts_unregister(priv->cpts);
1352 cpsw_intr_disable(priv);
1353 cpdma_ctlr_stop(priv->dma);
1354 cpsw_ale_stop(priv->ale);
1356 for_each_slave(priv, cpsw_slave_stop, priv);
1357 pm_runtime_put_sync(&priv->pdev->dev);
1358 if (priv->data.dual_emac)
1359 priv->slaves[priv->emac_port].open_stat = false;
1363 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1364 struct net_device *ndev)
1366 struct cpsw_priv *priv = netdev_priv(ndev);
1369 ndev->trans_start = jiffies;
1371 if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1372 cpsw_err(priv, tx_err, "packet pad failed\n");
1373 ndev->stats.tx_dropped++;
1374 return NETDEV_TX_OK;
1377 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1378 priv->cpts->tx_enable)
1379 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1381 skb_tx_timestamp(skb);
1383 ret = cpsw_tx_packet_submit(ndev, priv, skb);
1384 if (unlikely(ret != 0)) {
1385 cpsw_err(priv, tx_err, "desc submit failed\n");
1389 /* If there is no more tx desc left free then we need to
1390 * tell the kernel to stop sending us tx frames.
1392 if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
1393 netif_stop_queue(ndev);
1395 return NETDEV_TX_OK;
1397 ndev->stats.tx_dropped++;
1398 netif_stop_queue(ndev);
1399 return NETDEV_TX_BUSY;
1402 #ifdef CONFIG_TI_CPTS
1404 static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1406 struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
1409 if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
1410 slave_write(slave, 0, CPSW1_TS_CTL);
1414 seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1415 ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1417 if (priv->cpts->tx_enable)
1418 ts_en |= CPSW_V1_TS_TX_EN;
1420 if (priv->cpts->rx_enable)
1421 ts_en |= CPSW_V1_TS_RX_EN;
1423 slave_write(slave, ts_en, CPSW1_TS_CTL);
1424 slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1427 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1429 struct cpsw_slave *slave;
1432 if (priv->data.dual_emac)
1433 slave = &priv->slaves[priv->emac_port];
1435 slave = &priv->slaves[priv->data.active_slave];
1437 ctrl = slave_read(slave, CPSW2_CONTROL);
1438 switch (priv->version) {
1439 case CPSW_VERSION_2:
1440 ctrl &= ~CTRL_V2_ALL_TS_MASK;
1442 if (priv->cpts->tx_enable)
1443 ctrl |= CTRL_V2_TX_TS_BITS;
1445 if (priv->cpts->rx_enable)
1446 ctrl |= CTRL_V2_RX_TS_BITS;
1448 case CPSW_VERSION_3:
1450 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1452 if (priv->cpts->tx_enable)
1453 ctrl |= CTRL_V3_TX_TS_BITS;
1455 if (priv->cpts->rx_enable)
1456 ctrl |= CTRL_V3_RX_TS_BITS;
1460 mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1462 slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1463 slave_write(slave, ctrl, CPSW2_CONTROL);
1464 __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
1467 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1469 struct cpsw_priv *priv = netdev_priv(dev);
1470 struct cpts *cpts = priv->cpts;
1471 struct hwtstamp_config cfg;
1473 if (priv->version != CPSW_VERSION_1 &&
1474 priv->version != CPSW_VERSION_2 &&
1475 priv->version != CPSW_VERSION_3)
1478 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1481 /* reserved for future extensions */
1485 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
1488 switch (cfg.rx_filter) {
1489 case HWTSTAMP_FILTER_NONE:
1490 cpts->rx_enable = 0;
1492 case HWTSTAMP_FILTER_ALL:
1493 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1494 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1495 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1497 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1498 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1499 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1500 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1501 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1502 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1503 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1504 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1505 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1506 cpts->rx_enable = 1;
1507 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1513 cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;
1515 switch (priv->version) {
1516 case CPSW_VERSION_1:
1517 cpsw_hwtstamp_v1(priv);
1519 case CPSW_VERSION_2:
1520 case CPSW_VERSION_3:
1521 cpsw_hwtstamp_v2(priv);
1527 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1530 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1532 struct cpsw_priv *priv = netdev_priv(dev);
1533 struct cpts *cpts = priv->cpts;
1534 struct hwtstamp_config cfg;
1536 if (priv->version != CPSW_VERSION_1 &&
1537 priv->version != CPSW_VERSION_2 &&
1538 priv->version != CPSW_VERSION_3)
1542 cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1543 cfg.rx_filter = (cpts->rx_enable ?
1544 HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1546 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1549 #endif /*CONFIG_TI_CPTS*/
1551 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1553 struct cpsw_priv *priv = netdev_priv(dev);
1554 int slave_no = cpsw_slave_index(priv);
1556 if (!netif_running(dev))
1560 #ifdef CONFIG_TI_CPTS
1562 return cpsw_hwtstamp_set(dev, req);
1564 return cpsw_hwtstamp_get(dev, req);
1568 if (!priv->slaves[slave_no].phy)
1570 return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd);
1573 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1575 struct cpsw_priv *priv = netdev_priv(ndev);
1577 cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1578 ndev->stats.tx_errors++;
1579 cpsw_intr_disable(priv);
1580 cpdma_chan_stop(priv->txch);
1581 cpdma_chan_start(priv->txch);
1582 cpsw_intr_enable(priv);
1585 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1587 struct cpsw_priv *priv = netdev_priv(ndev);
1588 struct sockaddr *addr = (struct sockaddr *)p;
1592 if (!is_valid_ether_addr(addr->sa_data))
1593 return -EADDRNOTAVAIL;
1595 if (priv->data.dual_emac) {
1596 vid = priv->slaves[priv->emac_port].port_vlan;
1600 cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port,
1602 cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port,
1605 memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1606 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1607 for_each_slave(priv, cpsw_set_slave_mac, priv);
1612 #ifdef CONFIG_NET_POLL_CONTROLLER
1613 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1615 struct cpsw_priv *priv = netdev_priv(ndev);
1617 cpsw_intr_disable(priv);
1618 cpsw_rx_interrupt(priv->irqs_table[0], priv);
1619 cpsw_tx_interrupt(priv->irqs_table[1], priv);
1620 cpsw_intr_enable(priv);
1624 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1628 int unreg_mcast_mask = 0;
1631 if (priv->data.dual_emac) {
1632 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
1634 if (priv->ndev->flags & IFF_ALLMULTI)
1635 unreg_mcast_mask = port_mask;
1637 port_mask = ALE_ALL_PORTS;
1639 if (priv->ndev->flags & IFF_ALLMULTI)
1640 unreg_mcast_mask = ALE_ALL_PORTS;
1642 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1645 ret = cpsw_ale_add_vlan(priv->ale, vid, port_mask, 0, port_mask,
1646 unreg_mcast_mask << priv->host_port);
1650 ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1651 priv->host_port, ALE_VLAN, vid);
1655 ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1656 port_mask, ALE_VLAN, vid, 0);
1658 goto clean_vlan_ucast;
1662 cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1663 priv->host_port, ALE_VLAN, vid);
1665 cpsw_ale_del_vlan(priv->ale, vid, 0);
1669 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1670 __be16 proto, u16 vid)
1672 struct cpsw_priv *priv = netdev_priv(ndev);
1674 if (vid == priv->data.default_vlan)
1677 if (priv->data.dual_emac) {
1678 /* In dual EMAC, reserved VLAN id should not be used for
1679 * creating VLAN interfaces as this can break the dual
1680 * EMAC port separation
1684 for (i = 0; i < priv->data.slaves; i++) {
1685 if (vid == priv->slaves[i].port_vlan)
1690 dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1691 return cpsw_add_vlan_ale_entry(priv, vid);
1694 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1695 __be16 proto, u16 vid)
1697 struct cpsw_priv *priv = netdev_priv(ndev);
1700 if (vid == priv->data.default_vlan)
1703 if (priv->data.dual_emac) {
1706 for (i = 0; i < priv->data.slaves; i++) {
1707 if (vid == priv->slaves[i].port_vlan)
1712 dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1713 ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1717 ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1718 priv->host_port, ALE_VLAN, vid);
1722 return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1726 static const struct net_device_ops cpsw_netdev_ops = {
1727 .ndo_open = cpsw_ndo_open,
1728 .ndo_stop = cpsw_ndo_stop,
1729 .ndo_start_xmit = cpsw_ndo_start_xmit,
1730 .ndo_set_mac_address = cpsw_ndo_set_mac_address,
1731 .ndo_do_ioctl = cpsw_ndo_ioctl,
1732 .ndo_validate_addr = eth_validate_addr,
1733 .ndo_change_mtu = eth_change_mtu,
1734 .ndo_tx_timeout = cpsw_ndo_tx_timeout,
1735 .ndo_set_rx_mode = cpsw_ndo_set_rx_mode,
1736 #ifdef CONFIG_NET_POLL_CONTROLLER
1737 .ndo_poll_controller = cpsw_ndo_poll_controller,
1739 .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid,
1740 .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid,
1743 static int cpsw_get_regs_len(struct net_device *ndev)
1745 struct cpsw_priv *priv = netdev_priv(ndev);
1747 return priv->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
1750 static void cpsw_get_regs(struct net_device *ndev,
1751 struct ethtool_regs *regs, void *p)
1753 struct cpsw_priv *priv = netdev_priv(ndev);
1756 /* update CPSW IP version */
1757 regs->version = priv->version;
1759 cpsw_ale_dump(priv->ale, reg);
1762 static void cpsw_get_drvinfo(struct net_device *ndev,
1763 struct ethtool_drvinfo *info)
1765 struct cpsw_priv *priv = netdev_priv(ndev);
1767 strlcpy(info->driver, "cpsw", sizeof(info->driver));
1768 strlcpy(info->version, "1.0", sizeof(info->version));
1769 strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
1770 info->regdump_len = cpsw_get_regs_len(ndev);
1773 static u32 cpsw_get_msglevel(struct net_device *ndev)
1775 struct cpsw_priv *priv = netdev_priv(ndev);
1776 return priv->msg_enable;
1779 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1781 struct cpsw_priv *priv = netdev_priv(ndev);
1782 priv->msg_enable = value;
1785 static int cpsw_get_ts_info(struct net_device *ndev,
1786 struct ethtool_ts_info *info)
1788 #ifdef CONFIG_TI_CPTS
1789 struct cpsw_priv *priv = netdev_priv(ndev);
1791 info->so_timestamping =
1792 SOF_TIMESTAMPING_TX_HARDWARE |
1793 SOF_TIMESTAMPING_TX_SOFTWARE |
1794 SOF_TIMESTAMPING_RX_HARDWARE |
1795 SOF_TIMESTAMPING_RX_SOFTWARE |
1796 SOF_TIMESTAMPING_SOFTWARE |
1797 SOF_TIMESTAMPING_RAW_HARDWARE;
1798 info->phc_index = priv->cpts->phc_index;
1800 (1 << HWTSTAMP_TX_OFF) |
1801 (1 << HWTSTAMP_TX_ON);
1803 (1 << HWTSTAMP_FILTER_NONE) |
1804 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1806 info->so_timestamping =
1807 SOF_TIMESTAMPING_TX_SOFTWARE |
1808 SOF_TIMESTAMPING_RX_SOFTWARE |
1809 SOF_TIMESTAMPING_SOFTWARE;
1810 info->phc_index = -1;
1812 info->rx_filters = 0;
1817 static int cpsw_get_settings(struct net_device *ndev,
1818 struct ethtool_cmd *ecmd)
1820 struct cpsw_priv *priv = netdev_priv(ndev);
1821 int slave_no = cpsw_slave_index(priv);
1823 if (priv->slaves[slave_no].phy)
1824 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1829 static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1831 struct cpsw_priv *priv = netdev_priv(ndev);
1832 int slave_no = cpsw_slave_index(priv);
1834 if (priv->slaves[slave_no].phy)
1835 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1840 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1842 struct cpsw_priv *priv = netdev_priv(ndev);
1843 int slave_no = cpsw_slave_index(priv);
1848 if (priv->slaves[slave_no].phy)
1849 phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol);
1852 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1854 struct cpsw_priv *priv = netdev_priv(ndev);
1855 int slave_no = cpsw_slave_index(priv);
1857 if (priv->slaves[slave_no].phy)
1858 return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol);
1863 static void cpsw_get_pauseparam(struct net_device *ndev,
1864 struct ethtool_pauseparam *pause)
1866 struct cpsw_priv *priv = netdev_priv(ndev);
1868 pause->autoneg = AUTONEG_DISABLE;
1869 pause->rx_pause = priv->rx_pause ? true : false;
1870 pause->tx_pause = priv->tx_pause ? true : false;
1873 static int cpsw_set_pauseparam(struct net_device *ndev,
1874 struct ethtool_pauseparam *pause)
1876 struct cpsw_priv *priv = netdev_priv(ndev);
1879 priv->rx_pause = pause->rx_pause ? true : false;
1880 priv->tx_pause = pause->tx_pause ? true : false;
1882 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1887 static const struct ethtool_ops cpsw_ethtool_ops = {
1888 .get_drvinfo = cpsw_get_drvinfo,
1889 .get_msglevel = cpsw_get_msglevel,
1890 .set_msglevel = cpsw_set_msglevel,
1891 .get_link = ethtool_op_get_link,
1892 .get_ts_info = cpsw_get_ts_info,
1893 .get_settings = cpsw_get_settings,
1894 .set_settings = cpsw_set_settings,
1895 .get_coalesce = cpsw_get_coalesce,
1896 .set_coalesce = cpsw_set_coalesce,
1897 .get_sset_count = cpsw_get_sset_count,
1898 .get_strings = cpsw_get_strings,
1899 .get_ethtool_stats = cpsw_get_ethtool_stats,
1900 .get_pauseparam = cpsw_get_pauseparam,
1901 .set_pauseparam = cpsw_set_pauseparam,
1902 .get_wol = cpsw_get_wol,
1903 .set_wol = cpsw_set_wol,
1904 .get_regs_len = cpsw_get_regs_len,
1905 .get_regs = cpsw_get_regs,
1908 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1909 u32 slave_reg_ofs, u32 sliver_reg_ofs)
1911 void __iomem *regs = priv->regs;
1912 int slave_num = slave->slave_num;
1913 struct cpsw_slave_data *data = priv->data.slave_data + slave_num;
1916 slave->regs = regs + slave_reg_ofs;
1917 slave->sliver = regs + sliver_reg_ofs;
1918 slave->port_vlan = data->dual_emac_res_vlan;
1921 static int cpsw_probe_dt(struct cpsw_platform_data *data,
1922 struct platform_device *pdev)
1924 struct device_node *node = pdev->dev.of_node;
1925 struct device_node *slave_node;
1932 if (of_property_read_u32(node, "slaves", &prop)) {
1933 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
1936 data->slaves = prop;
1938 if (of_property_read_u32(node, "active_slave", &prop)) {
1939 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
1942 data->active_slave = prop;
1944 if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
1945 dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n");
1948 data->cpts_clock_mult = prop;
1950 if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
1951 dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n");
1954 data->cpts_clock_shift = prop;
1956 data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
1957 * sizeof(struct cpsw_slave_data),
1959 if (!data->slave_data)
1962 if (of_property_read_u32(node, "cpdma_channels", &prop)) {
1963 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
1966 data->channels = prop;
1968 if (of_property_read_u32(node, "ale_entries", &prop)) {
1969 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
1972 data->ale_entries = prop;
1974 if (of_property_read_u32(node, "bd_ram_size", &prop)) {
1975 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
1978 data->bd_ram_size = prop;
1980 if (of_property_read_u32(node, "rx_descs", &prop)) {
1981 dev_err(&pdev->dev, "Missing rx_descs property in the DT.\n");
1984 data->rx_descs = prop;
1986 if (of_property_read_u32(node, "mac_control", &prop)) {
1987 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
1990 data->mac_control = prop;
1992 if (of_property_read_bool(node, "dual_emac"))
1993 data->dual_emac = 1;
1996 * Populate all the child nodes here...
1998 ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
1999 /* We do not want to force this, as in some cases may not have child */
2001 dev_warn(&pdev->dev, "Doesn't have any child node\n");
2003 for_each_child_of_node(node, slave_node) {
2004 struct cpsw_slave_data *slave_data = data->slave_data + i;
2005 const void *mac_addr = NULL;
2009 struct device_node *mdio_node;
2010 struct platform_device *mdio;
2012 /* This is no slave child node, continue */
2013 if (strcmp(slave_node->name, "slave"))
2016 parp = of_get_property(slave_node, "phy_id", &lenp);
2017 if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) {
2018 dev_err(&pdev->dev, "Missing slave[%d] phy_id property\n", i);
2021 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2022 phyid = be32_to_cpup(parp+1);
2023 mdio = of_find_device_by_node(mdio_node);
2024 of_node_put(mdio_node);
2026 dev_err(&pdev->dev, "Missing mdio platform device\n");
2029 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2030 PHY_ID_FMT, mdio->name, phyid);
2032 slave_data->phy_if = of_get_phy_mode(slave_node);
2033 if (slave_data->phy_if < 0) {
2034 dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2036 return slave_data->phy_if;
2040 mac_addr = of_get_mac_address(slave_node);
2042 memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
2044 if (of_machine_is_compatible("ti,am33xx")) {
2045 ret = cpsw_am33xx_cm_get_macid(&pdev->dev,
2047 slave_data->mac_addr);
2052 if (data->dual_emac) {
2053 if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
2055 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
2056 slave_data->dual_emac_res_vlan = i+1;
2057 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2058 slave_data->dual_emac_res_vlan, i);
2060 slave_data->dual_emac_res_vlan = prop;
2065 if (i == data->slaves)
2072 static int cpsw_probe_dual_emac(struct platform_device *pdev,
2073 struct cpsw_priv *priv)
2075 struct cpsw_platform_data *data = &priv->data;
2076 struct net_device *ndev;
2077 struct cpsw_priv *priv_sl2;
2080 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2082 dev_err(&pdev->dev, "cpsw: error allocating net_device\n");
2086 priv_sl2 = netdev_priv(ndev);
2087 spin_lock_init(&priv_sl2->lock);
2088 priv_sl2->data = *data;
2089 priv_sl2->pdev = pdev;
2090 priv_sl2->ndev = ndev;
2091 priv_sl2->dev = &ndev->dev;
2092 priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2093 priv_sl2->rx_packet_max = max(rx_packet_max, 128);
2095 if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2096 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2098 dev_info(&pdev->dev, "cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
2100 random_ether_addr(priv_sl2->mac_addr);
2101 dev_info(&pdev->dev, "cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
2103 memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2105 priv_sl2->slaves = priv->slaves;
2106 priv_sl2->clk = priv->clk;
2108 priv_sl2->coal_intvl = 0;
2109 priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
2111 priv_sl2->regs = priv->regs;
2112 priv_sl2->host_port = priv->host_port;
2113 priv_sl2->host_port_regs = priv->host_port_regs;
2114 priv_sl2->wr_regs = priv->wr_regs;
2115 priv_sl2->hw_stats = priv->hw_stats;
2116 priv_sl2->dma = priv->dma;
2117 priv_sl2->txch = priv->txch;
2118 priv_sl2->rxch = priv->rxch;
2119 priv_sl2->ale = priv->ale;
2120 priv_sl2->emac_port = 1;
2121 priv->slaves[1].ndev = ndev;
2122 priv_sl2->cpts = priv->cpts;
2123 priv_sl2->version = priv->version;
2125 for (i = 0; i < priv->num_irqs; i++) {
2126 priv_sl2->irqs_table[i] = priv->irqs_table[i];
2127 priv_sl2->num_irqs = priv->num_irqs;
2129 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2131 ndev->netdev_ops = &cpsw_netdev_ops;
2132 ndev->ethtool_ops = &cpsw_ethtool_ops;
2133 netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT);
2135 /* register the network device */
2136 SET_NETDEV_DEV(ndev, &pdev->dev);
2137 ret = register_netdev(ndev);
2139 dev_err(&pdev->dev, "cpsw: error registering net device\n");
2147 static int cpsw_probe(struct platform_device *pdev)
2149 struct cpsw_platform_data *data;
2150 struct net_device *ndev;
2151 struct cpsw_priv *priv;
2152 struct cpdma_params dma_params;
2153 struct cpsw_ale_params ale_params;
2154 void __iomem *ss_regs;
2155 struct resource *res, *ss_res;
2156 u32 slave_offset, sliver_offset, slave_size;
2160 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2162 dev_err(&pdev->dev, "error allocating net_device\n");
2166 platform_set_drvdata(pdev, ndev);
2167 priv = netdev_priv(ndev);
2168 spin_lock_init(&priv->lock);
2171 priv->dev = &ndev->dev;
2172 priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2173 priv->rx_packet_max = max(rx_packet_max, 128);
2174 priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
2175 priv->irq_enabled = true;
2177 dev_err(&pdev->dev, "error allocating cpts\n");
2179 goto clean_ndev_ret;
2183 * This may be required here for child devices.
2185 pm_runtime_enable(&pdev->dev);
2187 /* Select default pin state */
2188 pinctrl_pm_select_default_state(&pdev->dev);
2190 if (cpsw_probe_dt(&priv->data, pdev)) {
2191 dev_err(&pdev->dev, "cpsw: platform data missing\n");
2193 goto clean_runtime_disable_ret;
2197 if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2198 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
2199 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
2201 eth_random_addr(priv->mac_addr);
2202 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
2205 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2207 priv->slaves = devm_kzalloc(&pdev->dev,
2208 sizeof(struct cpsw_slave) * data->slaves,
2210 if (!priv->slaves) {
2212 goto clean_runtime_disable_ret;
2214 for (i = 0; i < data->slaves; i++)
2215 priv->slaves[i].slave_num = i;
2217 priv->slaves[0].ndev = ndev;
2218 priv->emac_port = 0;
2220 priv->clk = devm_clk_get(&pdev->dev, "fck");
2221 if (IS_ERR(priv->clk)) {
2222 dev_err(priv->dev, "fck is not found\n");
2224 goto clean_runtime_disable_ret;
2226 priv->coal_intvl = 0;
2227 priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
2229 ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2230 ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2231 if (IS_ERR(ss_regs)) {
2232 ret = PTR_ERR(ss_regs);
2233 goto clean_runtime_disable_ret;
2235 priv->regs = ss_regs;
2236 priv->host_port = HOST_PORT_NUM;
2238 /* Need to enable clocks with runtime PM api to access module
2241 pm_runtime_get_sync(&pdev->dev);
2242 priv->version = readl(&priv->regs->id_ver);
2243 pm_runtime_put_sync(&pdev->dev);
2245 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2246 priv->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2247 if (IS_ERR(priv->wr_regs)) {
2248 ret = PTR_ERR(priv->wr_regs);
2249 goto clean_runtime_disable_ret;
2252 memset(&dma_params, 0, sizeof(dma_params));
2253 memset(&ale_params, 0, sizeof(ale_params));
2255 switch (priv->version) {
2256 case CPSW_VERSION_1:
2257 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
2258 priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET;
2259 priv->hw_stats = ss_regs + CPSW1_HW_STATS;
2260 dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET;
2261 dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET;
2262 ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET;
2263 slave_offset = CPSW1_SLAVE_OFFSET;
2264 slave_size = CPSW1_SLAVE_SIZE;
2265 sliver_offset = CPSW1_SLIVER_OFFSET;
2266 dma_params.desc_mem_phys = 0;
2268 case CPSW_VERSION_2:
2269 case CPSW_VERSION_3:
2270 case CPSW_VERSION_4:
2271 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
2272 priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET;
2273 priv->hw_stats = ss_regs + CPSW2_HW_STATS;
2274 dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET;
2275 dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET;
2276 ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET;
2277 slave_offset = CPSW2_SLAVE_OFFSET;
2278 slave_size = CPSW2_SLAVE_SIZE;
2279 sliver_offset = CPSW2_SLIVER_OFFSET;
2280 dma_params.desc_mem_phys =
2281 (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
2284 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
2286 goto clean_runtime_disable_ret;
2288 for (i = 0; i < priv->data.slaves; i++) {
2289 struct cpsw_slave *slave = &priv->slaves[i];
2290 cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
2291 slave_offset += slave_size;
2292 sliver_offset += SLIVER_SIZE;
2295 dma_params.dev = &pdev->dev;
2296 dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH;
2297 dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE;
2298 dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP;
2299 dma_params.txcp = dma_params.txhdp + CPDMA_TXCP;
2300 dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP;
2302 dma_params.num_chan = data->channels;
2303 dma_params.has_soft_reset = true;
2304 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;
2305 dma_params.desc_mem_size = data->bd_ram_size;
2306 dma_params.desc_align = 16;
2307 dma_params.has_ext_regs = true;
2308 dma_params.desc_hw_addr = dma_params.desc_mem_phys;
2310 priv->dma = cpdma_ctlr_create(&dma_params);
2312 dev_err(priv->dev, "error initializing dma\n");
2314 goto clean_runtime_disable_ret;
2317 priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
2319 priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
2322 if (WARN_ON(!priv->txch || !priv->rxch)) {
2323 dev_err(priv->dev, "error initializing dma channels\n");
2328 ale_params.dev = &ndev->dev;
2329 ale_params.ale_ageout = ale_ageout;
2330 ale_params.ale_entries = data->ale_entries;
2331 ale_params.ale_ports = data->slaves;
2333 priv->ale = cpsw_ale_create(&ale_params);
2335 dev_err(priv->dev, "error initializing ale engine\n");
2340 ndev->irq = platform_get_irq(pdev, 1);
2341 if (ndev->irq < 0) {
2342 dev_err(priv->dev, "error getting irq resource\n");
2347 /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
2348 * MISC IRQs which are always kept disabled with this driver so
2349 * we will not request them.
2351 * If anyone wants to implement support for those, make sure to
2352 * first request and append them to irqs_table array.
2356 irq = platform_get_irq(pdev, 1);
2360 priv->irqs_table[0] = irq;
2361 ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
2362 0, dev_name(&pdev->dev), priv);
2364 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2369 irq = platform_get_irq(pdev, 2);
2373 priv->irqs_table[1] = irq;
2374 ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
2375 0, dev_name(&pdev->dev), priv);
2377 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2382 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2384 ndev->netdev_ops = &cpsw_netdev_ops;
2385 ndev->ethtool_ops = &cpsw_ethtool_ops;
2386 netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT);
2388 /* register the network device */
2389 SET_NETDEV_DEV(ndev, &pdev->dev);
2390 ret = register_netdev(ndev);
2392 dev_err(priv->dev, "error registering net device\n");
2397 cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
2398 &ss_res->start, ndev->irq);
2400 if (priv->data.dual_emac) {
2401 ret = cpsw_probe_dual_emac(pdev, priv);
2403 cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
2411 cpsw_ale_destroy(priv->ale);
2413 cpdma_chan_destroy(priv->txch);
2414 cpdma_chan_destroy(priv->rxch);
2415 cpdma_ctlr_destroy(priv->dma);
2416 clean_runtime_disable_ret:
2417 pm_runtime_disable(&pdev->dev);
2419 free_netdev(priv->ndev);
2423 static int cpsw_remove_child_device(struct device *dev, void *c)
2425 struct platform_device *pdev = to_platform_device(dev);
2427 of_device_unregister(pdev);
2432 static int cpsw_remove(struct platform_device *pdev)
2434 struct net_device *ndev = platform_get_drvdata(pdev);
2435 struct cpsw_priv *priv = netdev_priv(ndev);
2437 if (priv->data.dual_emac)
2438 unregister_netdev(cpsw_get_slave_ndev(priv, 1));
2439 unregister_netdev(ndev);
2441 cpsw_ale_destroy(priv->ale);
2442 cpdma_chan_destroy(priv->txch);
2443 cpdma_chan_destroy(priv->rxch);
2444 cpdma_ctlr_destroy(priv->dma);
2445 pm_runtime_disable(&pdev->dev);
2446 device_for_each_child(&pdev->dev, NULL, cpsw_remove_child_device);
2447 if (priv->data.dual_emac)
2448 free_netdev(cpsw_get_slave_ndev(priv, 1));
2453 #ifdef CONFIG_PM_SLEEP
2454 static int cpsw_suspend(struct device *dev)
2456 struct platform_device *pdev = to_platform_device(dev);
2457 struct net_device *ndev = platform_get_drvdata(pdev);
2458 struct cpsw_priv *priv = netdev_priv(ndev);
2460 if (priv->data.dual_emac) {
2463 for (i = 0; i < priv->data.slaves; i++) {
2464 if (netif_running(priv->slaves[i].ndev))
2465 cpsw_ndo_stop(priv->slaves[i].ndev);
2466 soft_reset_slave(priv->slaves + i);
2469 if (netif_running(ndev))
2470 cpsw_ndo_stop(ndev);
2471 for_each_slave(priv, soft_reset_slave);
2474 pm_runtime_put_sync(&pdev->dev);
2476 /* Select sleep pin state */
2477 pinctrl_pm_select_sleep_state(&pdev->dev);
2482 static int cpsw_resume(struct device *dev)
2484 struct platform_device *pdev = to_platform_device(dev);
2485 struct net_device *ndev = platform_get_drvdata(pdev);
2486 struct cpsw_priv *priv = netdev_priv(ndev);
2488 pm_runtime_get_sync(&pdev->dev);
2490 /* Select default pin state */
2491 pinctrl_pm_select_default_state(&pdev->dev);
2493 if (priv->data.dual_emac) {
2496 for (i = 0; i < priv->data.slaves; i++) {
2497 if (netif_running(priv->slaves[i].ndev))
2498 cpsw_ndo_open(priv->slaves[i].ndev);
2501 if (netif_running(ndev))
2502 cpsw_ndo_open(ndev);
2508 static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
2510 static const struct of_device_id cpsw_of_mtable[] = {
2511 { .compatible = "ti,cpsw", },
2514 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2516 static struct platform_driver cpsw_driver = {
2520 .of_match_table = cpsw_of_mtable,
2522 .probe = cpsw_probe,
2523 .remove = cpsw_remove,
2526 static int __init cpsw_init(void)
2528 return platform_driver_register(&cpsw_driver);
2530 late_initcall(cpsw_init);
2532 static void __exit cpsw_exit(void)
2534 platform_driver_unregister(&cpsw_driver);
2536 module_exit(cpsw_exit);
2538 MODULE_LICENSE("GPL");
2539 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2540 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2541 MODULE_DESCRIPTION("TI CPSW Ethernet driver");