drivers/net/ethernet/ti/cpsw.c

   1 /*
   2  * Texas Instruments Ethernet Switch Driver
   3  *
   4  * Copyright (C) 2012 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/io.h>
  18 #include <linux/clk.h>
  19 #include <linux/timer.h>
  20 #include <linux/module.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/irqreturn.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/if_ether.h>
  25 #include <linux/etherdevice.h>
  26 #include <linux/netdevice.h>
  27 #include <linux/net_tstamp.h>
  28 #include <linux/phy.h>
  29 #include <linux/workqueue.h>
  30 #include <linux/delay.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/of.h>
  33 #include <linux/of_net.h>
  34 #include <linux/of_device.h>
  35 #include <linux/if_vlan.h>
  36
  37 #include <linux/pinctrl/consumer.h>
  38
  39 #include "cpsw.h"
  40 #include "cpsw_ale.h"
  41 #include "cpts.h"
  42 #include "davinci_cpdma.h"
  43
  44 #define CPSW_DEBUG      (NETIF_MSG_HW           | NETIF_MSG_WOL         | \
  45                          NETIF_MSG_DRV          | NETIF_MSG_LINK        | \
  46                          NETIF_MSG_IFUP         | NETIF_MSG_INTR        | \
  47                          NETIF_MSG_PROBE        | NETIF_MSG_TIMER       | \
  48                          NETIF_MSG_IFDOWN       | NETIF_MSG_RX_ERR      | \
  49                          NETIF_MSG_TX_ERR       | NETIF_MSG_TX_DONE     | \
  50                          NETIF_MSG_PKTDATA      | NETIF_MSG_TX_QUEUED   | \
  51                          NETIF_MSG_RX_STATUS)
  52
  53 #define cpsw_info(priv, type, format, ...)              \
  54 do {                                                            \
  55         if (netif_msg_##type(priv) && net_ratelimit())          \
  56                 dev_info(priv->dev, format, ## __VA_ARGS__);    \
  57 } while (0)
  58
  59 #define cpsw_err(priv, type, format, ...)               \
  60 do {                                                            \
  61         if (netif_msg_##type(priv) && net_ratelimit())          \
  62                 dev_err(priv->dev, format, ## __VA_ARGS__);     \
  63 } while (0)
  64
  65 #define cpsw_dbg(priv, type, format, ...)               \
  66 do {                                                            \
  67         if (netif_msg_##type(priv) && net_ratelimit())          \
  68                 dev_dbg(priv->dev, format, ## __VA_ARGS__);     \
  69 } while (0)
  70
  71 #define cpsw_notice(priv, type, format, ...)            \
  72 do {                                                            \
  73         if (netif_msg_##type(priv) && net_ratelimit())          \
  74                 dev_notice(priv->dev, format, ## __VA_ARGS__);  \
  75 } while (0)
  76
  77 #define ALE_ALL_PORTS           0x7
  78
  79 #define CPSW_MAJOR_VERSION(reg)         (reg >> 8 & 0x7)
  80 #define CPSW_MINOR_VERSION(reg)         (reg & 0xff)
  81 #define CPSW_RTL_VERSION(reg)           ((reg >> 11) & 0x1f)
  82
  83 #define CPSW_VERSION_1          0x19010a
  84 #define CPSW_VERSION_2          0x19010c
  85 #define CPSW_VERSION_3          0x19010f
  86 #define CPSW_VERSION_4          0x190112
  87
  88 #define HOST_PORT_NUM           0
  89 #define SLIVER_SIZE             0x40
  90
  91 #define CPSW1_HOST_PORT_OFFSET  0x028
  92 #define CPSW1_SLAVE_OFFSET      0x050
  93 #define CPSW1_SLAVE_SIZE        0x040
  94 #define CPSW1_CPDMA_OFFSET      0x100
  95 #define CPSW1_STATERAM_OFFSET   0x200
  96 #define CPSW1_HW_STATS          0x400
  97 #define CPSW1_CPTS_OFFSET       0x500
  98 #define CPSW1_ALE_OFFSET        0x600
  99 #define CPSW1_SLIVER_OFFSET     0x700
 100
 101 #define CPSW2_HOST_PORT_OFFSET  0x108
 102 #define CPSW2_SLAVE_OFFSET      0x200
 103 #define CPSW2_SLAVE_SIZE        0x100
 104 #define CPSW2_CPDMA_OFFSET      0x800
 105 #define CPSW2_HW_STATS          0x900
 106 #define CPSW2_STATERAM_OFFSET   0xa00
 107 #define CPSW2_CPTS_OFFSET       0xc00
 108 #define CPSW2_ALE_OFFSET        0xd00
 109 #define CPSW2_SLIVER_OFFSET     0xd80
 110 #define CPSW2_BD_OFFSET         0x2000
 111
 112 #define CPDMA_RXTHRESH          0x0c0
 113 #define CPDMA_RXFREE            0x0e0
 114 #define CPDMA_TXHDP             0x00
 115 #define CPDMA_RXHDP             0x20
 116 #define CPDMA_TXCP              0x40
 117 #define CPDMA_RXCP              0x60
 118
 119 #define CPSW_POLL_WEIGHT        64
 120 #define CPSW_MIN_PACKET_SIZE    60
 121 #define CPSW_MAX_PACKET_SIZE    (1500 + 14 + 4 + 4)
 122
 123 #define RX_PRIORITY_MAPPING     0x76543210
 124 #define TX_PRIORITY_MAPPING     0x33221100
 125 #define CPDMA_TX_PRIORITY_MAP   0x76543210
 126
 127 #define CPSW_VLAN_AWARE         BIT(1)
 128 #define CPSW_ALE_VLAN_AWARE     1
 129
 130 #define CPSW_FIFO_NORMAL_MODE           (0 << 16)
 131 #define CPSW_FIFO_DUAL_MAC_MODE         (1 << 16)
 132 #define CPSW_FIFO_RATE_LIMIT_MODE       (2 << 16)
 133
 134 #define CPSW_INTPACEEN          (0x3f << 16)
 135 #define CPSW_INTPRESCALE_MASK   (0x7FF << 0)
 136 #define CPSW_CMINTMAX_CNT       63
 137 #define CPSW_CMINTMIN_CNT       2
 138 #define CPSW_CMINTMAX_INTVL     (1000 / CPSW_CMINTMIN_CNT)
 139 #define CPSW_CMINTMIN_INTVL     ((1000 / CPSW_CMINTMAX_CNT) + 1)
 140
 141 #define cpsw_slave_index(priv)                          \
 142                 ((priv->data.dual_emac) ? priv->emac_port :     \
 143                 priv->data.active_slave)
 144
 145 static int debug_level;
 146 module_param(debug_level, int, 0);
 147 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
 148
 149 static int ale_ageout = 10;
 150 module_param(ale_ageout, int, 0);
 151 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
 152
 153 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
 154 module_param(rx_packet_max, int, 0);
 155 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
 156
 157 struct cpsw_wr_regs {
 158         u32     id_ver;
 159         u32     soft_reset;
 160         u32     control;
 161         u32     int_control;
 162         u32     rx_thresh_en;
 163         u32     rx_en;
 164         u32     tx_en;
 165         u32     misc_en;
 166         u32     mem_allign1[8];
 167         u32     rx_thresh_stat;
 168         u32     rx_stat;
 169         u32     tx_stat;
 170         u32     misc_stat;
 171         u32     mem_allign2[8];
 172         u32     rx_imax;
 173         u32     tx_imax;
 174
 175 };
 176
 177 struct cpsw_ss_regs {
 178         u32     id_ver;
 179         u32     control;
 180         u32     soft_reset;
 181         u32     stat_port_en;
 182         u32     ptype;
 183         u32     soft_idle;
 184         u32     thru_rate;
 185         u32     gap_thresh;
 186         u32     tx_start_wds;
 187         u32     flow_control;
 188         u32     vlan_ltype;
 189         u32     ts_ltype;
 190         u32     dlr_ltype;
 191 };
 192
 193 /* CPSW_PORT_V1 */
 194 #define CPSW1_MAX_BLKS      0x00 /* Maximum FIFO Blocks */
 195 #define CPSW1_BLK_CNT       0x04 /* FIFO Block Usage Count (Read Only) */
 196 #define CPSW1_TX_IN_CTL     0x08 /* Transmit FIFO Control */
 197 #define CPSW1_PORT_VLAN     0x0c /* VLAN Register */
 198 #define CPSW1_TX_PRI_MAP    0x10 /* Tx Header Priority to Switch Pri Mapping */
 199 #define CPSW1_TS_CTL        0x14 /* Time Sync Control */
 200 #define CPSW1_TS_SEQ_LTYPE  0x18 /* Time Sync Sequence ID Offset and Msg Type */
 201 #define CPSW1_TS_VLAN       0x1c /* Time Sync VLAN1 and VLAN2 */
 202
 203 /* CPSW_PORT_V2 */
 204 #define CPSW2_CONTROL       0x00 /* Control Register */
 205 #define CPSW2_MAX_BLKS      0x08 /* Maximum FIFO Blocks */
 206 #define CPSW2_BLK_CNT       0x0c /* FIFO Block Usage Count (Read Only) */
 207 #define CPSW2_TX_IN_CTL     0x10 /* Transmit FIFO Control */
 208 #define CPSW2_PORT_VLAN     0x14 /* VLAN Register */
 209 #define CPSW2_TX_PRI_MAP    0x18 /* Tx Header Priority to Switch Pri Mapping */
 210 #define CPSW2_TS_SEQ_MTYPE  0x1c /* Time Sync Sequence ID Offset and Msg Type */
 211
 212 /* CPSW_PORT_V1 and V2 */
 213 #define SA_LO               0x20 /* CPGMAC_SL Source Address Low */
 214 #define SA_HI               0x24 /* CPGMAC_SL Source Address High */
 215 #define SEND_PERCENT        0x28 /* Transmit Queue Send Percentages */
 216
 217 /* CPSW_PORT_V2 only */
 218 #define RX_DSCP_PRI_MAP0    0x30 /* Rx DSCP Priority to Rx Packet Mapping */
 219 #define RX_DSCP_PRI_MAP1    0x34 /* Rx DSCP Priority to Rx Packet Mapping */
 220 #define RX_DSCP_PRI_MAP2    0x38 /* Rx DSCP Priority to Rx Packet Mapping */
 221 #define RX_DSCP_PRI_MAP3    0x3c /* Rx DSCP Priority to Rx Packet Mapping */
 222 #define RX_DSCP_PRI_MAP4    0x40 /* Rx DSCP Priority to Rx Packet Mapping */
 223 #define RX_DSCP_PRI_MAP5    0x44 /* Rx DSCP Priority to Rx Packet Mapping */
 224 #define RX_DSCP_PRI_MAP6    0x48 /* Rx DSCP Priority to Rx Packet Mapping */
 225 #define RX_DSCP_PRI_MAP7    0x4c /* Rx DSCP Priority to Rx Packet Mapping */
 226
 227 /* Bit definitions for the CPSW2_CONTROL register */
 228 #define PASS_PRI_TAGGED     (1<<24) /* Pass Priority Tagged */
 229 #define VLAN_LTYPE2_EN      (1<<21) /* VLAN LTYPE 2 enable */
 230 #define VLAN_LTYPE1_EN      (1<<20) /* VLAN LTYPE 1 enable */
 231 #define DSCP_PRI_EN         (1<<16) /* DSCP Priority Enable */
 232 #define TS_320              (1<<14) /* Time Sync Dest Port 320 enable */
 233 #define TS_319              (1<<13) /* Time Sync Dest Port 319 enable */
 234 #define TS_132              (1<<12) /* Time Sync Dest IP Addr 132 enable */
 235 #define TS_131              (1<<11) /* Time Sync Dest IP Addr 131 enable */
 236 #define TS_130              (1<<10) /* Time Sync Dest IP Addr 130 enable */
 237 #define TS_129              (1<<9)  /* Time Sync Dest IP Addr 129 enable */
 238 #define TS_TTL_NONZERO      (1<<8)  /* Time Sync Time To Live Non-zero enable */
 239 #define TS_ANNEX_F_EN       (1<<6)  /* Time Sync Annex F enable */
 240 #define TS_ANNEX_D_EN       (1<<4)  /* Time Sync Annex D enable */
 241 #define TS_LTYPE2_EN        (1<<3)  /* Time Sync LTYPE 2 enable */
 242 #define TS_LTYPE1_EN        (1<<2)  /* Time Sync LTYPE 1 enable */
 243 #define TS_TX_EN            (1<<1)  /* Time Sync Transmit Enable */
 244 #define TS_RX_EN            (1<<0)  /* Time Sync Receive Enable */
 245
 246 #define CTRL_V2_TS_BITS \
 247         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 248          TS_TTL_NONZERO  | TS_ANNEX_D_EN | TS_LTYPE1_EN)
 249
 250 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
 251 #define CTRL_V2_TX_TS_BITS  (CTRL_V2_TS_BITS | TS_TX_EN)
 252 #define CTRL_V2_RX_TS_BITS  (CTRL_V2_TS_BITS | TS_RX_EN)
 253
 254
 255 #define CTRL_V3_TS_BITS \
 256         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 257          TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
 258          TS_LTYPE1_EN)
 259
 260 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
 261 #define CTRL_V3_TX_TS_BITS  (CTRL_V3_TS_BITS | TS_TX_EN)
 262 #define CTRL_V3_RX_TS_BITS  (CTRL_V3_TS_BITS | TS_RX_EN)
 263
 264 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
 265 #define TS_SEQ_ID_OFFSET_SHIFT   (16)    /* Time Sync Sequence ID Offset */
 266 #define TS_SEQ_ID_OFFSET_MASK    (0x3f)
 267 #define TS_MSG_TYPE_EN_SHIFT     (0)     /* Time Sync Message Type Enable */
 268 #define TS_MSG_TYPE_EN_MASK      (0xffff)
 269
 270 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
 271 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
 272
 273 /* Bit definitions for the CPSW1_TS_CTL register */
 274 #define CPSW_V1_TS_RX_EN                BIT(0)
 275 #define CPSW_V1_TS_TX_EN                BIT(4)
 276 #define CPSW_V1_MSG_TYPE_OFS            16
 277
 278 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
 279 #define CPSW_V1_SEQ_ID_OFS_SHIFT        16
 280
 281 struct cpsw_host_regs {
 282         u32     max_blks;
 283         u32     blk_cnt;
 284         u32     tx_in_ctl;
 285         u32     port_vlan;
 286         u32     tx_pri_map;
 287         u32     cpdma_tx_pri_map;
 288         u32     cpdma_rx_chan_map;
 289 };
 290
 291 struct cpsw_sliver_regs {
 292         u32     id_ver;
 293         u32     mac_control;
 294         u32     mac_status;
 295         u32     soft_reset;
 296         u32     rx_maxlen;
 297         u32     __reserved_0;
 298         u32     rx_pause;
 299         u32     tx_pause;
 300         u32     __reserved_1;
 301         u32     rx_pri_map;
 302 };
 303
 304 struct cpsw_hw_stats {
 305         u32     rxgoodframes;
 306         u32     rxbroadcastframes;
 307         u32     rxmulticastframes;
 308         u32     rxpauseframes;
 309         u32     rxcrcerrors;
 310         u32     rxaligncodeerrors;
 311         u32     rxoversizedframes;
 312         u32     rxjabberframes;
 313         u32     rxundersizedframes;
 314         u32     rxfragments;
 315         u32     __pad_0[2];
 316         u32     rxoctets;
 317         u32     txgoodframes;
 318         u32     txbroadcastframes;
 319         u32     txmulticastframes;
 320         u32     txpauseframes;
 321         u32     txdeferredframes;
 322         u32     txcollisionframes;
 323         u32     txsinglecollframes;
 324         u32     txmultcollframes;
 325         u32     txexcessivecollisions;
 326         u32     txlatecollisions;
 327         u32     txunderrun;
 328         u32     txcarriersenseerrors;
 329         u32     txoctets;
 330         u32     octetframes64;
 331         u32     octetframes65t127;
 332         u32     octetframes128t255;
 333         u32     octetframes256t511;
 334         u32     octetframes512t1023;
 335         u32     octetframes1024tup;
 336         u32     netoctets;
 337         u32     rxsofoverruns;
 338         u32     rxmofoverruns;
 339         u32     rxdmaoverruns;
 340 };
 341
 342 struct cpsw_slave {
 343         void __iomem                    *regs;
 344         struct cpsw_sliver_regs __iomem *sliver;
 345         int                             slave_num;
 346         u32                             mac_control;
 347         struct cpsw_slave_data          *data;
 348         struct phy_device               *phy;
 349         struct net_device               *ndev;
 350         u32                             port_vlan;
 351         u32                             open_stat;
 352 };
 353
 354 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
 355 {
 356         return __raw_readl(slave->regs + offset);
 357 }
 358
 359 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
 360 {
 361         __raw_writel(val, slave->regs + offset);
 362 }
 363
 364 struct cpsw_priv {
 365         spinlock_t                      lock;
 366         struct platform_device          *pdev;
 367         struct net_device               *ndev;
 368         struct napi_struct              napi;
 369         struct device                   *dev;
 370         struct cpsw_platform_data       data;
 371         struct cpsw_ss_regs __iomem     *regs;
 372         struct cpsw_wr_regs __iomem     *wr_regs;
 373         u8 __iomem                      *hw_stats;
 374         struct cpsw_host_regs __iomem   *host_port_regs;
 375         u32                             msg_enable;
 376         u32                             version;
 377         u32                             coal_intvl;
 378         u32                             bus_freq_mhz;
 379         int                             rx_packet_max;
 380         int                             host_port;
 381         struct clk                      *clk;
 382         u8                              mac_addr[ETH_ALEN];
 383         struct cpsw_slave               *slaves;
 384         struct cpdma_ctlr               *dma;
 385         struct cpdma_chan               *txch, *rxch;
 386         struct cpsw_ale                 *ale;
 387         bool                            rx_pause;
 388         bool                            tx_pause;
 389         /* snapshot of IRQ numbers */
 390         u32 irqs_table[4];
 391         u32 num_irqs;
 392         struct cpts *cpts;
 393         u32 emac_port;
 394 };
 395
 396 struct cpsw_stats {
 397         char stat_string[ETH_GSTRING_LEN];
 398         int type;
 399         int sizeof_stat;
 400         int stat_offset;
 401 };
 402
 403 enum {
 404         CPSW_STATS,
 405         CPDMA_RX_STATS,
 406         CPDMA_TX_STATS,
 407 };
 408
 409 #define CPSW_STAT(m)            CPSW_STATS,                             \
 410                                 sizeof(((struct cpsw_hw_stats *)0)->m), \
 411                                 offsetof(struct cpsw_hw_stats, m)
 412 #define CPDMA_RX_STAT(m)        CPDMA_RX_STATS,                            \
 413                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 414                                 offsetof(struct cpdma_chan_stats, m)
 415 #define CPDMA_TX_STAT(m)        CPDMA_TX_STATS,                            \
 416                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 417                                 offsetof(struct cpdma_chan_stats, m)
 418
 419 static const struct cpsw_stats cpsw_gstrings_stats[] = {
 420         { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
 421         { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
 422         { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
 423         { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
 424         { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
 425         { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
 426         { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
 427         { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
 428         { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
 429         { "Rx Fragments", CPSW_STAT(rxfragments) },
 430         { "Rx Octets", CPSW_STAT(rxoctets) },
 431         { "Good Tx Frames", CPSW_STAT(txgoodframes) },
 432         { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
 433         { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
 434         { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
 435         { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
 436         { "Collisions", CPSW_STAT(txcollisionframes) },
 437         { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
 438         { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
 439         { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
 440         { "Late Collisions", CPSW_STAT(txlatecollisions) },
 441         { "Tx Underrun", CPSW_STAT(txunderrun) },
 442         { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
 443         { "Tx Octets", CPSW_STAT(txoctets) },
 444         { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
 445         { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
 446         { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
 447         { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
 448         { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
 449         { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
 450         { "Net Octets", CPSW_STAT(netoctets) },
 451         { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
 452         { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
 453         { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
 454         { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) },
 455         { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
 456         { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
 457         { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) },
 458         { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
 459         { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
 460         { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
 461         { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
 462         { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
 463         { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
 464         { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) },
 465         { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) },
 466         { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
 467         { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) },
 468         { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) },
 469         { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) },
 470         { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) },
 471         { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) },
 472         { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) },
 473         { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) },
 474         { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) },
 475         { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) },
 476         { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) },
 477         { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) },
 478         { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) },
 479         { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) },
 480 };
 481
 482 #define CPSW_STATS_LEN  ARRAY_SIZE(cpsw_gstrings_stats)
 483
 484 #define napi_to_priv(napi)      container_of(napi, struct cpsw_priv, napi)
 485 #define for_each_slave(priv, func, arg...)                              \
 486         do {                                                            \
 487                 struct cpsw_slave *slave;                               \
 488                 int n;                                                  \
 489                 if (priv->data.dual_emac)                               \
 490                         (func)((priv)->slaves + priv->emac_port, ##arg);\
 491                 else                                                    \
 492                         for (n = (priv)->data.slaves,                   \
 493                                         slave = (priv)->slaves;         \
 494                                         n; n--)                         \
 495                                 (func)(slave++, ##arg);                 \
 496         } while (0)
 497 #define cpsw_get_slave_ndev(priv, __slave_no__)                         \
 498         ((__slave_no__ < priv->data.slaves) ?                           \
 499                 priv->slaves[__slave_no__].ndev : NULL)
 500 #define cpsw_get_slave_priv(priv, __slave_no__)                         \
 501         (((__slave_no__ < priv->data.slaves) &&                         \
 502                 (priv->slaves[__slave_no__].ndev)) ?                    \
 503                 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL)    \
 504
 505 #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb)         \
 506         do {                                                            \
 507                 if (!priv->data.dual_emac)                              \
 508                         break;                                          \
 509                 if (CPDMA_RX_SOURCE_PORT(status) == 1) {                \
 510                         ndev = cpsw_get_slave_ndev(priv, 0);            \
 511                         priv = netdev_priv(ndev);                       \
 512                         skb->dev = ndev;                                \
 513                 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) {         \
 514                         ndev = cpsw_get_slave_ndev(priv, 1);            \
 515                         priv = netdev_priv(ndev);                       \
 516                         skb->dev = ndev;                                \
 517                 }                                                       \
 518         } while (0)
 519 #define cpsw_add_mcast(priv, addr)                                      \
 520         do {                                                            \
 521                 if (priv->data.dual_emac) {                             \
 522                         struct cpsw_slave *slave = priv->slaves +       \
 523                                                 priv->emac_port;        \
 524                         int slave_port = cpsw_get_slave_port(priv,      \
 525                                                 slave->slave_num);      \
 526                         cpsw_ale_add_mcast(priv->ale, addr,             \
 527                                 1 << slave_port | 1 << priv->host_port, \
 528                                 ALE_VLAN, slave->port_vlan, 0);         \
 529                 } else {                                                \
 530                         cpsw_ale_add_mcast(priv->ale, addr,             \
 531                                 ALE_ALL_PORTS << priv->host_port,       \
 532                                 0, 0, 0);                               \
 533                 }                                                       \
 534         } while (0)
 535
 536 static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
 537 {
 538         if (priv->host_port == 0)
 539                 return slave_num + 1;
 540         else
 541                 return slave_num;
 542 }
 543
 544 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
 545 {
 546         struct cpsw_priv *priv = netdev_priv(ndev);
 547         struct cpsw_ale *ale = priv->ale;
 548         int i;
 549
 550         if (priv->data.dual_emac) {
 551                 bool flag = false;
 552
 553                 /* Enabling promiscuous mode for one interface will be
 554                  * common for both the interface as the interface shares
 555                  * the same hardware resource.
 556                  */
 557                 for (i = 0; i < priv->data.slaves; i++)
 558                         if (priv->slaves[i].ndev->flags & IFF_PROMISC)
 559                                 flag = true;
 560
 561                 if (!enable && flag) {
 562                         enable = true;
 563                         dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
 564                 }
 565
 566                 if (enable) {
 567                         /* Enable Bypass */
 568                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
 569
 570                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 571                 } else {
 572                         /* Disable Bypass */
 573                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
 574                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 575                 }
 576         } else {
 577                 if (enable) {
 578                         unsigned long timeout = jiffies + HZ;
 579
 580                         /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
 581                         for (i = 0; i <= priv->data.slaves; i++) {
 582                                 cpsw_ale_control_set(ale, i,
 583                                                      ALE_PORT_NOLEARN, 1);
 584                                 cpsw_ale_control_set(ale, i,
 585                                                      ALE_PORT_NO_SA_UPDATE, 1);
 586                         }
 587
 588                         /* Clear All Untouched entries */
 589                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 590                         do {
 591                                 cpu_relax();
 592                                 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
 593                                         break;
 594                         } while (time_after(timeout, jiffies));
 595                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 596
 597                         /* Clear all mcast from ALE */
 598                         cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS <<
 599                                                  priv->host_port, -1);
 600
 601                         /* Flood All Unicast Packets to Host port */
 602                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
 603                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 604                 } else {
 605                         /* Don't Flood All Unicast Packets to Host port */
 606                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
 607
 608                         /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
 609                         for (i = 0; i <= priv->data.slaves; i++) {
 610                                 cpsw_ale_control_set(ale, i,
 611                                                      ALE_PORT_NOLEARN, 0);
 612                                 cpsw_ale_control_set(ale, i,
 613                                                      ALE_PORT_NO_SA_UPDATE, 0);
 614                         }
 615                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 616                 }
 617         }
 618 }
 619
 620 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
 621 {
 622         struct cpsw_priv *priv = netdev_priv(ndev);
 623         int vid;
 624
 625         if (priv->data.dual_emac)
 626                 vid = priv->slaves[priv->emac_port].port_vlan;
 627         else
 628                 vid = priv->data.default_vlan;
 629
 630         if (ndev->flags & IFF_PROMISC) {
 631                 /* Enable promiscuous mode */
 632                 cpsw_set_promiscious(ndev, true);
 633                 cpsw_ale_set_allmulti(priv->ale, IFF_ALLMULTI);
 634                 return;
 635         } else {
 636                 /* Disable promiscuous mode */
 637                 cpsw_set_promiscious(ndev, false);
 638         }
 639
 640         /* Restore allmulti on vlans if necessary */
 641         cpsw_ale_set_allmulti(priv->ale, priv->ndev->flags & IFF_ALLMULTI);
 642
 643         /* Clear all mcast from ALE */
 644         cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port,
 645                                  vid);
 646
 647         if (!netdev_mc_empty(ndev)) {
 648                 struct netdev_hw_addr *ha;
 649
 650                 /* program multicast address list into ALE register */
 651                 netdev_for_each_mc_addr(ha, ndev) {
 652                         cpsw_add_mcast(priv, (u8 *)ha->addr);
 653                 }
 654         }
 655 }
 656
 657 static void cpsw_intr_enable(struct cpsw_priv *priv)
 658 {
 659         __raw_writel(0xFF, &priv->wr_regs->tx_en);
 660         __raw_writel(0xFF, &priv->wr_regs->rx_en);
 661
 662         cpdma_ctlr_int_ctrl(priv->dma, true);
 663         return;
 664 }
 665
 666 static void cpsw_intr_disable(struct cpsw_priv *priv)
 667 {
 668         __raw_writel(0, &priv->wr_regs->tx_en);
 669         __raw_writel(0, &priv->wr_regs->rx_en);
 670
 671         cpdma_ctlr_int_ctrl(priv->dma, false);
 672         return;
 673 }
 674
 675 static void cpsw_tx_handler(void *token, int len, int status)
 676 {
 677         struct sk_buff          *skb = token;
 678         struct net_device       *ndev = skb->dev;
 679         struct cpsw_priv        *priv = netdev_priv(ndev);
 680
 681         /* Check whether the queue is stopped due to stalled tx dma, if the
 682          * queue is stopped then start the queue as we have free desc for tx
 683          */
 684         if (unlikely(netif_queue_stopped(ndev)))
 685                 netif_wake_queue(ndev);
 686         cpts_tx_timestamp(priv->cpts, skb);
 687         ndev->stats.tx_packets++;
 688         ndev->stats.tx_bytes += len;
 689         dev_kfree_skb_any(skb);
 690 }
 691
 692 static void cpsw_rx_handler(void *token, int len, int status)
 693 {
 694         struct sk_buff          *skb = token;
 695         struct sk_buff          *new_skb;
 696         struct net_device       *ndev = skb->dev;
 697         struct cpsw_priv        *priv = netdev_priv(ndev);
 698         int                     ret = 0;
 699
 700         cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
 701
 702         if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
 703                 bool ndev_status = false;
 704                 struct cpsw_slave *slave = priv->slaves;
 705                 int n;
 706
 707                 if (priv->data.dual_emac) {
 708                         /* In dual emac mode check for all interfaces */
 709                         for (n = priv->data.slaves; n; n--, slave++)
 710                                 if (netif_running(slave->ndev))
 711                                         ndev_status = true;
 712                 }
 713
 714                 if (ndev_status && (status >= 0)) {
 715                         /* The packet received is for the interface which
 716                          * is already down and the other interface is up
 717                          * and running, instead of freeing which results
 718                          * in reducing of the number of rx descriptor in
 719                          * DMA engine, requeue skb back to cpdma.
 720                          */
 721                         new_skb = skb;
 722                         goto requeue;
 723                 }
 724
 725                 /* the interface is going down, skbs are purged */
 726                 dev_kfree_skb_any(skb);
 727                 return;
 728         }
 729
 730         new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
 731         if (new_skb) {
 732                 skb_put(skb, len);
 733                 cpts_rx_timestamp(priv->cpts, skb);
 734                 skb->protocol = eth_type_trans(skb, ndev);
 735                 netif_receive_skb(skb);
 736                 ndev->stats.rx_bytes += len;
 737                 ndev->stats.rx_packets++;
 738         } else {
 739                 ndev->stats.rx_dropped++;
 740                 new_skb = skb;
 741         }
 742
 743 requeue:
 744         ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
 745                         skb_tailroom(new_skb), 0);
 746         if (WARN_ON(ret < 0))
 747                 dev_kfree_skb_any(new_skb);
 748 }
 749
 750 static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
 751 {
 752         struct cpsw_priv *priv = dev_id;
 753
 754         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
 755         cpdma_chan_process(priv->txch, 128);
 756
 757         priv = cpsw_get_slave_priv(priv, 1);
 758         if (priv)
 759                 cpdma_chan_process(priv->txch, 128);
 760
 761         return IRQ_HANDLED;
 762 }
 763
 764 static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
 765 {
 766         struct cpsw_priv *priv = dev_id;
 767
 768         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
 769         writel(0, &priv->wr_regs->rx_en);
 770
 771         napi_schedule(&priv->napi);
 772         return IRQ_HANDLED;
 773 }
 774
 775 static int cpsw_poll(struct napi_struct *napi, int budget)
 776 {
 777         struct cpsw_priv        *priv = napi_to_priv(napi);
 778         int                     num_rx;
 779
 780         num_rx = cpdma_chan_process(priv->rxch, budget);
 781         if (num_rx < budget) {
 782                 napi_complete(napi);
 783                 writel(0xff, &priv->wr_regs->rx_en);
 784         }
 785
 786         if (num_rx)
 787                 cpsw_dbg(priv, intr, "poll %d rx pkts\n", num_rx);
 788
 789         return num_rx;
 790 }
 791
 792 static inline void soft_reset(const char *module, void __iomem *reg)
 793 {
 794         unsigned long timeout = jiffies + HZ;
 795
 796         __raw_writel(1, reg);
 797         do {
 798                 cpu_relax();
 799         } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
 800
 801         WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
 802 }
 803
 804 #define mac_hi(mac)     (((mac)[0] << 0) | ((mac)[1] << 8) |    \
 805                          ((mac)[2] << 16) | ((mac)[3] << 24))
 806 #define mac_lo(mac)     (((mac)[4] << 0) | ((mac)[5] << 8))
 807
 808 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
 809                                struct cpsw_priv *priv)
 810 {
 811         slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
 812         slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
 813 }
 814
 815 static void _cpsw_adjust_link(struct cpsw_slave *slave,
 816                               struct cpsw_priv *priv, bool *link)
 817 {
 818         struct phy_device       *phy = slave->phy;
 819         u32                     mac_control = 0;
 820         u32                     slave_port;
 821
 822         if (!phy)
 823                 return;
 824
 825         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
 826
 827         if (phy->link) {
 828                 mac_control = priv->data.mac_control;
 829
 830                 /* enable forwarding */
 831                 cpsw_ale_control_set(priv->ale, slave_port,
 832                                      ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
 833
 834                 if (phy->speed == 1000)
 835                         mac_control |= BIT(7);  /* GIGABITEN    */
 836                 if (phy->duplex)
 837                         mac_control |= BIT(0);  /* FULLDUPLEXEN */
 838
 839                 /* set speed_in input in case RMII mode is used in 100Mbps */
 840                 if (phy->speed == 100)
 841                         mac_control |= BIT(15);
 842                 else if (phy->speed == 10)
 843                         mac_control |= BIT(18); /* In Band mode */
 844
 845                 if (priv->rx_pause)
 846                         mac_control |= BIT(3);
 847
 848                 if (priv->tx_pause)
 849                         mac_control |= BIT(4);
 850
 851                 *link = true;
 852         } else {
 853                 mac_control = 0;
 854                 /* disable forwarding */
 855                 cpsw_ale_control_set(priv->ale, slave_port,
 856                                      ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
 857         }
 858
 859         if (mac_control != slave->mac_control) {
 860                 phy_print_status(phy);
 861                 __raw_writel(mac_control, &slave->sliver->mac_control);
 862         }
 863
 864         slave->mac_control = mac_control;
 865 }
 866
 867 static void cpsw_adjust_link(struct net_device *ndev)
 868 {
 869         struct cpsw_priv        *priv = netdev_priv(ndev);
 870         bool                    link = false;
 871
 872         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
 873
 874         if (link) {
 875                 netif_carrier_on(ndev);
 876                 if (netif_running(ndev))
 877                         netif_wake_queue(ndev);
 878         } else {
 879                 netif_carrier_off(ndev);
 880                 netif_stop_queue(ndev);
 881         }
 882 }
 883
 884 static int cpsw_get_coalesce(struct net_device *ndev,
 885                                 struct ethtool_coalesce *coal)
 886 {
 887         struct cpsw_priv *priv = netdev_priv(ndev);
 888
 889         coal->rx_coalesce_usecs = priv->coal_intvl;
 890         return 0;
 891 }
 892
 893 static int cpsw_set_coalesce(struct net_device *ndev,
 894                                 struct ethtool_coalesce *coal)
 895 {
 896         struct cpsw_priv *priv = netdev_priv(ndev);
 897         u32 int_ctrl;
 898         u32 num_interrupts = 0;
 899         u32 prescale = 0;
 900         u32 addnl_dvdr = 1;
 901         u32 coal_intvl = 0;
 902
 903         coal_intvl = coal->rx_coalesce_usecs;
 904
 905         int_ctrl =  readl(&priv->wr_regs->int_control);
 906         prescale = priv->bus_freq_mhz * 4;
 907
 908         if (!coal->rx_coalesce_usecs) {
 909                 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
 910                 goto update_return;
 911         }
 912
 913         if (coal_intvl < CPSW_CMINTMIN_INTVL)
 914                 coal_intvl = CPSW_CMINTMIN_INTVL;
 915
 916         if (coal_intvl > CPSW_CMINTMAX_INTVL) {
 917                 /* Interrupt pacer works with 4us Pulse, we can
 918                  * throttle further by dilating the 4us pulse.
 919                  */
 920                 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
 921
 922                 if (addnl_dvdr > 1) {
 923                         prescale *= addnl_dvdr;
 924                         if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
 925                                 coal_intvl = (CPSW_CMINTMAX_INTVL
 926                                                 * addnl_dvdr);
 927                 } else {
 928                         addnl_dvdr = 1;
 929                         coal_intvl = CPSW_CMINTMAX_INTVL;
 930                 }
 931         }
 932
 933         num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
 934         writel(num_interrupts, &priv->wr_regs->rx_imax);
 935         writel(num_interrupts, &priv->wr_regs->tx_imax);
 936
 937         int_ctrl |= CPSW_INTPACEEN;
 938         int_ctrl &= (~CPSW_INTPRESCALE_MASK);
 939         int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
 940
 941 update_return:
 942         writel(int_ctrl, &priv->wr_regs->int_control);
 943
 944         cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
 945         if (priv->data.dual_emac) {
 946                 int i;
 947
 948                 for (i = 0; i < priv->data.slaves; i++) {
 949                         priv = netdev_priv(priv->slaves[i].ndev);
 950                         priv->coal_intvl = coal_intvl;
 951                 }
 952         } else {
 953                 priv->coal_intvl = coal_intvl;
 954         }
 955
 956         return 0;
 957 }
 958
 959 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
 960 {
 961         switch (sset) {
 962         case ETH_SS_STATS:
 963                 return CPSW_STATS_LEN;
 964         default:
 965                 return -EOPNOTSUPP;
 966         }
 967 }
 968
 969 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
 970 {
 971         u8 *p = data;
 972         int i;
 973
 974         switch (stringset) {
 975         case ETH_SS_STATS:
 976                 for (i = 0; i < CPSW_STATS_LEN; i++) {
 977                         memcpy(p, cpsw_gstrings_stats[i].stat_string,
 978                                ETH_GSTRING_LEN);
 979                         p += ETH_GSTRING_LEN;
 980                 }
 981                 break;
 982         }
 983 }
 984
 985 static void cpsw_get_ethtool_stats(struct net_device *ndev,
 986                                     struct ethtool_stats *stats, u64 *data)
 987 {
 988         struct cpsw_priv *priv = netdev_priv(ndev);
 989         struct cpdma_chan_stats rx_stats;
 990         struct cpdma_chan_stats tx_stats;
 991         u32 val;
 992         u8 *p;
 993         int i;
 994
 995         /* Collect Davinci CPDMA stats for Rx and Tx Channel */
 996         cpdma_chan_get_stats(priv->rxch, &rx_stats);
 997         cpdma_chan_get_stats(priv->txch, &tx_stats);
 998
 999         for (i = 0; i < CPSW_STATS_LEN; i++) {
1000                 switch (cpsw_gstrings_stats[i].type) {
1001                 case CPSW_STATS:
1002                         val = readl(priv->hw_stats +
1003                                     cpsw_gstrings_stats[i].stat_offset);
1004                         data[i] = val;
1005                         break;
1006
1007                 case CPDMA_RX_STATS:
1008                         p = (u8 *)&rx_stats +
1009                                 cpsw_gstrings_stats[i].stat_offset;
1010                         data[i] = *(u32 *)p;
1011                         break;
1012
1013                 case CPDMA_TX_STATS:
1014                         p = (u8 *)&tx_stats +
1015                                 cpsw_gstrings_stats[i].stat_offset;
1016                         data[i] = *(u32 *)p;
1017                         break;
1018                 }
1019         }
1020 }
1021
1022 static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
1023 {
1024         u32 i;
1025         u32 usage_count = 0;
1026
1027         if (!priv->data.dual_emac)
1028                 return 0;
1029
1030         for (i = 0; i < priv->data.slaves; i++)
1031                 if (priv->slaves[i].open_stat)
1032                         usage_count++;
1033
1034         return usage_count;
1035 }
1036
1037 static inline int cpsw_tx_packet_submit(struct net_device *ndev,
1038                         struct cpsw_priv *priv, struct sk_buff *skb)
1039 {
1040         if (!priv->data.dual_emac)
1041                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1042                                   skb->len, 0);
1043
1044         if (ndev == cpsw_get_slave_ndev(priv, 0))
1045                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1046                                   skb->len, 1);
1047         else
1048                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1049                                   skb->len, 2);
1050 }
1051
1052 static inline void cpsw_add_dual_emac_def_ale_entries(
1053                 struct cpsw_priv *priv, struct cpsw_slave *slave,
1054                 u32 slave_port)
1055 {
1056         u32 port_mask = 1 << slave_port | 1 << priv->host_port;
1057
1058         if (priv->version == CPSW_VERSION_1)
1059                 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1060         else
1061                 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1062         cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
1063                           port_mask, port_mask, 0);
1064         cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1065                            port_mask, ALE_VLAN, slave->port_vlan, 0);
1066         cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1067                 priv->host_port, ALE_VLAN | ALE_SECURE, slave->port_vlan);
1068 }
1069
1070 static void soft_reset_slave(struct cpsw_slave *slave)
1071 {
1072         char name[32];
1073
1074         snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1075         soft_reset(name, &slave->sliver->soft_reset);
1076 }
1077
1078 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1079 {
1080         u32 slave_port;
1081
1082         soft_reset_slave(slave);
1083
1084         /* setup priority mapping */
1085         __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1086
1087         switch (priv->version) {
1088         case CPSW_VERSION_1:
1089                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1090                 break;
1091         case CPSW_VERSION_2:
1092         case CPSW_VERSION_3:
1093         case CPSW_VERSION_4:
1094                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1095                 break;
1096         }
1097
1098         /* setup max packet size, and mac address */
1099         __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
1100         cpsw_set_slave_mac(slave, priv);
1101
1102         slave->mac_control = 0; /* no link yet */
1103
1104         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1105
1106         if (priv->data.dual_emac)
1107                 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1108         else
1109                 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1110                                    1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1111
1112         slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
1113                                  &cpsw_adjust_link, slave->data->phy_if);
1114         if (IS_ERR(slave->phy)) {
1115                 dev_err(priv->dev, "phy %s not found on slave %d\n",
1116                         slave->data->phy_id, slave->slave_num);
1117                 slave->phy = NULL;
1118         } else {
1119                 dev_info(priv->dev, "phy found : id is : 0x%x\n",
1120                          slave->phy->phy_id);
1121                 phy_start(slave->phy);
1122
1123                 /* Configure GMII_SEL register */
1124                 cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface,
1125                              slave->slave_num);
1126         }
1127 }
1128
1129 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1130 {
1131         const int vlan = priv->data.default_vlan;
1132         const int port = priv->host_port;
1133         u32 reg;
1134         int i;
1135         int unreg_mcast_mask;
1136
1137         reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1138                CPSW2_PORT_VLAN;
1139
1140         writel(vlan, &priv->host_port_regs->port_vlan);
1141
1142         for (i = 0; i < priv->data.slaves; i++)
1143                 slave_write(priv->slaves + i, vlan, reg);
1144
1145         if (priv->ndev->flags & IFF_ALLMULTI)
1146                 unreg_mcast_mask = ALE_ALL_PORTS;
1147         else
1148                 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1149
1150         cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port,
1151                           ALE_ALL_PORTS << port, ALE_ALL_PORTS << port,
1152                           unreg_mcast_mask << port);
1153 }
1154
1155 static void cpsw_init_host_port(struct cpsw_priv *priv)
1156 {
1157         u32 control_reg;
1158         u32 fifo_mode;
1159
1160         /* soft reset the controller and initialize ale */
1161         soft_reset("cpsw", &priv->regs->soft_reset);
1162         cpsw_ale_start(priv->ale);
1163
1164         /* switch to vlan unaware mode */
1165         cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE,
1166                              CPSW_ALE_VLAN_AWARE);
1167         control_reg = readl(&priv->regs->control);
1168         control_reg |= CPSW_VLAN_AWARE;
1169         writel(control_reg, &priv->regs->control);
1170         fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1171                      CPSW_FIFO_NORMAL_MODE;
1172         writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
1173
1174         /* setup host port priority mapping */
1175         __raw_writel(CPDMA_TX_PRIORITY_MAP,
1176                      &priv->host_port_regs->cpdma_tx_pri_map);
1177         __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
1178
1179         cpsw_ale_control_set(priv->ale, priv->host_port,
1180                              ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1181
1182         if (!priv->data.dual_emac) {
1183                 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port,
1184                                    0, 0);
1185                 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1186                                    1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2);
1187         }
1188 }
1189
1190 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
1191 {
1192         u32 slave_port;
1193
1194         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1195
1196         if (!slave->phy)
1197                 return;
1198         phy_stop(slave->phy);
1199         phy_disconnect(slave->phy);
1200         slave->phy = NULL;
1201         cpsw_ale_control_set(priv->ale, slave_port,
1202                              ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1203 }
1204
1205 static int cpsw_ndo_open(struct net_device *ndev)
1206 {
1207         struct cpsw_priv *priv = netdev_priv(ndev);
1208         int i, ret;
1209         u32 reg;
1210
1211         if (!cpsw_common_res_usage_state(priv))
1212                 cpsw_intr_disable(priv);
1213         netif_carrier_off(ndev);
1214
1215         pm_runtime_get_sync(&priv->pdev->dev);
1216
1217         reg = priv->version;
1218
1219         dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1220                  CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1221                  CPSW_RTL_VERSION(reg));
1222
1223         /* initialize host and slave ports */
1224         if (!cpsw_common_res_usage_state(priv))
1225                 cpsw_init_host_port(priv);
1226         for_each_slave(priv, cpsw_slave_open, priv);
1227
1228         /* Add default VLAN */
1229         if (!priv->data.dual_emac)
1230                 cpsw_add_default_vlan(priv);
1231         else
1232                 cpsw_ale_add_vlan(priv->ale, priv->data.default_vlan,
1233                                   ALE_ALL_PORTS << priv->host_port,
1234                                   ALE_ALL_PORTS << priv->host_port, 0, 0);
1235
1236         if (!cpsw_common_res_usage_state(priv)) {
1237                 struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0);
1238
1239                 /* setup tx dma to fixed prio and zero offset */
1240                 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
1241                 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
1242
1243                 /* disable priority elevation */
1244                 __raw_writel(0, &priv->regs->ptype);
1245
1246                 /* enable statistics collection only on all ports */
1247                 __raw_writel(0x7, &priv->regs->stat_port_en);
1248
1249                 /* Enable internal fifo flow control */
1250                 writel(0x7, &priv->regs->flow_control);
1251
1252                 napi_enable(&priv_sl0->napi);
1253
1254                 if (WARN_ON(!priv->data.rx_descs))
1255                         priv->data.rx_descs = 128;
1256
1257                 for (i = 0; i < priv->data.rx_descs; i++) {
1258                         struct sk_buff *skb;
1259
1260                         ret = -ENOMEM;
1261                         skb = __netdev_alloc_skb_ip_align(priv->ndev,
1262                                         priv->rx_packet_max, GFP_KERNEL);
1263                         if (!skb)
1264                                 goto err_cleanup;
1265                         ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
1266                                         skb_tailroom(skb), 0);
1267                         if (ret < 0) {
1268                                 kfree_skb(skb);
1269                                 goto err_cleanup;
1270                         }
1271                 }
1272                 /* continue even if we didn't manage to submit all
1273                  * receive descs
1274                  */
1275                 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
1276
1277                 if (cpts_register(&priv->pdev->dev, priv->cpts,
1278                                   priv->data.cpts_clock_mult,
1279                                   priv->data.cpts_clock_shift))
1280                         dev_err(priv->dev, "error registering cpts device\n");
1281
1282         }
1283
1284         /* Enable Interrupt pacing if configured */
1285         if (priv->coal_intvl != 0) {
1286                 struct ethtool_coalesce coal;
1287
1288                 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1289                 cpsw_set_coalesce(ndev, &coal);
1290         }
1291
1292         cpdma_ctlr_start(priv->dma);
1293         cpsw_intr_enable(priv);
1294
1295         if (priv->data.dual_emac)
1296                 priv->slaves[priv->emac_port].open_stat = true;
1297         return 0;
1298
1299 err_cleanup:
1300         cpdma_ctlr_stop(priv->dma);
1301         for_each_slave(priv, cpsw_slave_stop, priv);
1302         pm_runtime_put_sync(&priv->pdev->dev);
1303         netif_carrier_off(priv->ndev);
1304         return ret;
1305 }
1306
1307 static int cpsw_ndo_stop(struct net_device *ndev)
1308 {
1309         struct cpsw_priv *priv = netdev_priv(ndev);
1310
1311         cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1312         netif_stop_queue(priv->ndev);
1313         netif_carrier_off(priv->ndev);
1314
1315         if (cpsw_common_res_usage_state(priv) <= 1) {
1316                 struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0);
1317
1318                 napi_disable(&priv_sl0->napi);
1319                 cpts_unregister(priv->cpts);
1320                 cpsw_intr_disable(priv);
1321                 cpdma_ctlr_stop(priv->dma);
1322                 cpsw_ale_stop(priv->ale);
1323         }
1324         for_each_slave(priv, cpsw_slave_stop, priv);
1325         pm_runtime_put_sync(&priv->pdev->dev);
1326         if (priv->data.dual_emac)
1327                 priv->slaves[priv->emac_port].open_stat = false;
1328         return 0;
1329 }
1330
1331 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1332                                        struct net_device *ndev)
1333 {
1334         struct cpsw_priv *priv = netdev_priv(ndev);
1335         int ret;
1336
1337         ndev->trans_start = jiffies;
1338
1339         if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1340                 cpsw_err(priv, tx_err, "packet pad failed\n");
1341                 ndev->stats.tx_dropped++;
1342                 return NETDEV_TX_OK;
1343         }
1344
1345         if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1346                                 priv->cpts->tx_enable)
1347                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1348
1349         skb_tx_timestamp(skb);
1350
1351         ret = cpsw_tx_packet_submit(ndev, priv, skb);
1352         if (unlikely(ret != 0)) {
1353                 cpsw_err(priv, tx_err, "desc submit failed\n");
1354                 goto fail;
1355         }
1356
1357         /* If there is no more tx desc left free then we need to
1358          * tell the kernel to stop sending us tx frames.
1359          */
1360         if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
1361                 netif_stop_queue(ndev);
1362
1363         return NETDEV_TX_OK;
1364 fail:
1365         ndev->stats.tx_dropped++;
1366         netif_stop_queue(ndev);
1367         return NETDEV_TX_BUSY;
1368 }
1369
1370 #ifdef CONFIG_TI_CPTS
1371
1372 static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1373 {
1374         struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
1375         u32 ts_en, seq_id;
1376
1377         if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
1378                 slave_write(slave, 0, CPSW1_TS_CTL);
1379                 return;
1380         }
1381
1382         seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1383         ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1384
1385         if (priv->cpts->tx_enable)
1386                 ts_en |= CPSW_V1_TS_TX_EN;
1387
1388         if (priv->cpts->rx_enable)
1389                 ts_en |= CPSW_V1_TS_RX_EN;
1390
1391         slave_write(slave, ts_en, CPSW1_TS_CTL);
1392         slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1393 }
1394
1395 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1396 {
1397         struct cpsw_slave *slave;
1398         u32 ctrl, mtype;
1399
1400         if (priv->data.dual_emac)
1401                 slave = &priv->slaves[priv->emac_port];
1402         else
1403                 slave = &priv->slaves[priv->data.active_slave];
1404
1405         ctrl = slave_read(slave, CPSW2_CONTROL);
1406         switch (priv->version) {
1407         case CPSW_VERSION_2:
1408                 ctrl &= ~CTRL_V2_ALL_TS_MASK;
1409
1410                 if (priv->cpts->tx_enable)
1411                         ctrl |= CTRL_V2_TX_TS_BITS;
1412
1413                 if (priv->cpts->rx_enable)
1414                         ctrl |= CTRL_V2_RX_TS_BITS;
1415                 break;
1416         case CPSW_VERSION_3:
1417         default:
1418                 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1419
1420                 if (priv->cpts->tx_enable)
1421                         ctrl |= CTRL_V3_TX_TS_BITS;
1422
1423                 if (priv->cpts->rx_enable)
1424                         ctrl |= CTRL_V3_RX_TS_BITS;
1425                 break;
1426         }
1427
1428         mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1429
1430         slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1431         slave_write(slave, ctrl, CPSW2_CONTROL);
1432         __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
1433 }
1434
1435 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1436 {
1437         struct cpsw_priv *priv = netdev_priv(dev);
1438         struct cpts *cpts = priv->cpts;
1439         struct hwtstamp_config cfg;
1440
1441         if (priv->version != CPSW_VERSION_1 &&
1442             priv->version != CPSW_VERSION_2 &&
1443             priv->version != CPSW_VERSION_3)
1444                 return -EOPNOTSUPP;
1445
1446         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1447                 return -EFAULT;
1448
1449         /* reserved for future extensions */
1450         if (cfg.flags)
1451                 return -EINVAL;
1452
1453         if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
1454                 return -ERANGE;
1455
1456         switch (cfg.rx_filter) {
1457         case HWTSTAMP_FILTER_NONE:
1458                 cpts->rx_enable = 0;
1459                 break;
1460         case HWTSTAMP_FILTER_ALL:
1461         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1462         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1463         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1464                 return -ERANGE;
1465         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1466         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1467         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1468         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1469         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1470         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1471         case HWTSTAMP_FILTER_PTP_V2_EVENT:
1472         case HWTSTAMP_FILTER_PTP_V2_SYNC:
1473         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1474                 cpts->rx_enable = 1;
1475                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1476                 break;
1477         default:
1478                 return -ERANGE;
1479         }
1480
1481         cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;
1482
1483         switch (priv->version) {
1484         case CPSW_VERSION_1:
1485                 cpsw_hwtstamp_v1(priv);
1486                 break;
1487         case CPSW_VERSION_2:
1488         case CPSW_VERSION_3:
1489                 cpsw_hwtstamp_v2(priv);
1490                 break;
1491         default:
1492                 WARN_ON(1);
1493         }
1494
1495         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1496 }
1497
1498 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1499 {
1500         struct cpsw_priv *priv = netdev_priv(dev);
1501         struct cpts *cpts = priv->cpts;
1502         struct hwtstamp_config cfg;
1503
1504         if (priv->version != CPSW_VERSION_1 &&
1505             priv->version != CPSW_VERSION_2 &&
1506             priv->version != CPSW_VERSION_3)
1507                 return -EOPNOTSUPP;
1508
1509         cfg.flags = 0;
1510         cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1511         cfg.rx_filter = (cpts->rx_enable ?
1512                          HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1513
1514         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1515 }
1516
1517 #endif /*CONFIG_TI_CPTS*/
1518
1519 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1520 {
1521         struct cpsw_priv *priv = netdev_priv(dev);
1522         int slave_no = cpsw_slave_index(priv);
1523
1524         if (!netif_running(dev))
1525                 return -EINVAL;
1526
1527         switch (cmd) {
1528 #ifdef CONFIG_TI_CPTS
1529         case SIOCSHWTSTAMP:
1530                 return cpsw_hwtstamp_set(dev, req);
1531         case SIOCGHWTSTAMP:
1532                 return cpsw_hwtstamp_get(dev, req);
1533 #endif
1534         }
1535
1536         if (!priv->slaves[slave_no].phy)
1537                 return -EOPNOTSUPP;
1538         return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd);
1539 }
1540
1541 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1542 {
1543         struct cpsw_priv *priv = netdev_priv(ndev);
1544
1545         cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1546         ndev->stats.tx_errors++;
1547         cpsw_intr_disable(priv);
1548         cpdma_chan_stop(priv->txch);
1549         cpdma_chan_start(priv->txch);
1550         cpsw_intr_enable(priv);
1551 }
1552
1553 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1554 {
1555         struct cpsw_priv *priv = netdev_priv(ndev);
1556         struct sockaddr *addr = (struct sockaddr *)p;
1557         int flags = 0;
1558         u16 vid = 0;
1559
1560         if (!is_valid_ether_addr(addr->sa_data))
1561                 return -EADDRNOTAVAIL;
1562
1563         if (priv->data.dual_emac) {
1564                 vid = priv->slaves[priv->emac_port].port_vlan;
1565                 flags = ALE_VLAN;
1566         }
1567
1568         cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port,
1569                            flags, vid);
1570         cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port,
1571                            flags, vid);
1572
1573         memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1574         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1575         for_each_slave(priv, cpsw_set_slave_mac, priv);
1576
1577         return 0;
1578 }
1579
1580 #ifdef CONFIG_NET_POLL_CONTROLLER
1581 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1582 {
1583         struct cpsw_priv *priv = netdev_priv(ndev);
1584
1585         cpsw_intr_disable(priv);
1586         cpsw_rx_interrupt(priv->irqs_table[0], priv);
1587         cpsw_tx_interrupt(priv->irqs_table[1], priv);
1588         cpsw_intr_enable(priv);
1589 }
1590 #endif
1591
1592 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1593                                 unsigned short vid)
1594 {
1595         int ret;
1596         int unreg_mcast_mask = 0;
1597         u32 port_mask;
1598
1599         if (priv->data.dual_emac) {
1600                 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
1601
1602                 if (priv->ndev->flags & IFF_ALLMULTI)
1603                         unreg_mcast_mask = port_mask;
1604         } else {
1605                 port_mask = ALE_ALL_PORTS;
1606
1607                 if (priv->ndev->flags & IFF_ALLMULTI)
1608                         unreg_mcast_mask = ALE_ALL_PORTS;
1609                 else
1610                         unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1611         }
1612
1613         ret = cpsw_ale_add_vlan(priv->ale, vid, port_mask, 0, port_mask,
1614                                 unreg_mcast_mask << priv->host_port);
1615         if (ret != 0)
1616                 return ret;
1617
1618         ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1619                                  priv->host_port, ALE_VLAN, vid);
1620         if (ret != 0)
1621                 goto clean_vid;
1622
1623         ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1624                                  port_mask, ALE_VLAN, vid, 0);
1625         if (ret != 0)
1626                 goto clean_vlan_ucast;
1627         return 0;
1628
1629 clean_vlan_ucast:
1630         cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1631                             priv->host_port, ALE_VLAN, vid);
1632 clean_vid:
1633         cpsw_ale_del_vlan(priv->ale, vid, 0);
1634         return ret;
1635 }
1636
1637 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1638                                     __be16 proto, u16 vid)
1639 {
1640         struct cpsw_priv *priv = netdev_priv(ndev);
1641
1642         if (vid == priv->data.default_vlan)
1643                 return 0;
1644
1645         if (priv->data.dual_emac) {
1646                 /* In dual EMAC, reserved VLAN id should not be used for
1647                  * creating VLAN interfaces as this can break the dual
1648                  * EMAC port separation
1649                  */
1650                 int i;
1651
1652                 for (i = 0; i < priv->data.slaves; i++) {
1653                         if (vid == priv->slaves[i].port_vlan)
1654                                 return -EINVAL;
1655                 }
1656         }
1657
1658         dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1659         return cpsw_add_vlan_ale_entry(priv, vid);
1660 }
1661
1662 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1663                                      __be16 proto, u16 vid)
1664 {
1665         struct cpsw_priv *priv = netdev_priv(ndev);
1666         int ret;
1667
1668         if (vid == priv->data.default_vlan)
1669                 return 0;
1670
1671         if (priv->data.dual_emac) {
1672                 int i;
1673
1674                 for (i = 0; i < priv->data.slaves; i++) {
1675                         if (vid == priv->slaves[i].port_vlan)
1676                                 return -EINVAL;
1677                 }
1678         }
1679
1680         dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1681         ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1682         if (ret != 0)
1683                 return ret;
1684
1685         ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1686                                  priv->host_port, ALE_VLAN, vid);
1687         if (ret != 0)
1688                 return ret;
1689
1690         return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1691                                   0, ALE_VLAN, vid);
1692 }
1693
1694 static const struct net_device_ops cpsw_netdev_ops = {
1695         .ndo_open               = cpsw_ndo_open,
1696         .ndo_stop               = cpsw_ndo_stop,
1697         .ndo_start_xmit         = cpsw_ndo_start_xmit,
1698         .ndo_set_mac_address    = cpsw_ndo_set_mac_address,
1699         .ndo_do_ioctl           = cpsw_ndo_ioctl,
1700         .ndo_validate_addr      = eth_validate_addr,
1701         .ndo_change_mtu         = eth_change_mtu,
1702         .ndo_tx_timeout         = cpsw_ndo_tx_timeout,
1703         .ndo_set_rx_mode        = cpsw_ndo_set_rx_mode,
1704 #ifdef CONFIG_NET_POLL_CONTROLLER
1705         .ndo_poll_controller    = cpsw_ndo_poll_controller,
1706 #endif
1707         .ndo_vlan_rx_add_vid    = cpsw_ndo_vlan_rx_add_vid,
1708         .ndo_vlan_rx_kill_vid   = cpsw_ndo_vlan_rx_kill_vid,
1709 };
1710
1711 static int cpsw_get_regs_len(struct net_device *ndev)
1712 {
1713         struct cpsw_priv *priv = netdev_priv(ndev);
1714
1715         return priv->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
1716 }
1717
1718 static void cpsw_get_regs(struct net_device *ndev,
1719                           struct ethtool_regs *regs, void *p)
1720 {
1721         struct cpsw_priv *priv = netdev_priv(ndev);
1722         u32 *reg = p;
1723
1724         /* update CPSW IP version */
1725         regs->version = priv->version;
1726
1727         cpsw_ale_dump(priv->ale, reg);
1728 }
1729
1730 static void cpsw_get_drvinfo(struct net_device *ndev,
1731                              struct ethtool_drvinfo *info)
1732 {
1733         struct cpsw_priv *priv = netdev_priv(ndev);
1734
1735         strlcpy(info->driver, "cpsw", sizeof(info->driver));
1736         strlcpy(info->version, "1.0", sizeof(info->version));
1737         strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
1738         info->regdump_len = cpsw_get_regs_len(ndev);
1739 }
1740
1741 static u32 cpsw_get_msglevel(struct net_device *ndev)
1742 {
1743         struct cpsw_priv *priv = netdev_priv(ndev);
1744         return priv->msg_enable;
1745 }
1746
1747 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1748 {
1749         struct cpsw_priv *priv = netdev_priv(ndev);
1750         priv->msg_enable = value;
1751 }
1752
1753 static int cpsw_get_ts_info(struct net_device *ndev,
1754                             struct ethtool_ts_info *info)
1755 {
1756 #ifdef CONFIG_TI_CPTS
1757         struct cpsw_priv *priv = netdev_priv(ndev);
1758
1759         info->so_timestamping =
1760                 SOF_TIMESTAMPING_TX_HARDWARE |
1761                 SOF_TIMESTAMPING_TX_SOFTWARE |
1762                 SOF_TIMESTAMPING_RX_HARDWARE |
1763                 SOF_TIMESTAMPING_RX_SOFTWARE |
1764                 SOF_TIMESTAMPING_SOFTWARE |
1765                 SOF_TIMESTAMPING_RAW_HARDWARE;
1766         info->phc_index = priv->cpts->phc_index;
1767         info->tx_types =
1768                 (1 << HWTSTAMP_TX_OFF) |
1769                 (1 << HWTSTAMP_TX_ON);
1770         info->rx_filters =
1771                 (1 << HWTSTAMP_FILTER_NONE) |
1772                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1773 #else
1774         info->so_timestamping =
1775                 SOF_TIMESTAMPING_TX_SOFTWARE |
1776                 SOF_TIMESTAMPING_RX_SOFTWARE |
1777                 SOF_TIMESTAMPING_SOFTWARE;
1778         info->phc_index = -1;
1779         info->tx_types = 0;
1780         info->rx_filters = 0;
1781 #endif
1782         return 0;
1783 }
1784
1785 static int cpsw_get_settings(struct net_device *ndev,
1786                              struct ethtool_cmd *ecmd)
1787 {
1788         struct cpsw_priv *priv = netdev_priv(ndev);
1789         int slave_no = cpsw_slave_index(priv);
1790
1791         if (priv->slaves[slave_no].phy)
1792                 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1793         else
1794                 return -EOPNOTSUPP;
1795 }
1796
1797 static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1798 {
1799         struct cpsw_priv *priv = netdev_priv(ndev);
1800         int slave_no = cpsw_slave_index(priv);
1801
1802         if (priv->slaves[slave_no].phy)
1803                 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1804         else
1805                 return -EOPNOTSUPP;
1806 }
1807
1808 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1809 {
1810         struct cpsw_priv *priv = netdev_priv(ndev);
1811         int slave_no = cpsw_slave_index(priv);
1812
1813         wol->supported = 0;
1814         wol->wolopts = 0;
1815
1816         if (priv->slaves[slave_no].phy)
1817                 phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol);
1818 }
1819
1820 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1821 {
1822         struct cpsw_priv *priv = netdev_priv(ndev);
1823         int slave_no = cpsw_slave_index(priv);
1824
1825         if (priv->slaves[slave_no].phy)
1826                 return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol);
1827         else
1828                 return -EOPNOTSUPP;
1829 }
1830
1831 static void cpsw_get_pauseparam(struct net_device *ndev,
1832                                 struct ethtool_pauseparam *pause)
1833 {
1834         struct cpsw_priv *priv = netdev_priv(ndev);
1835
1836         pause->autoneg = AUTONEG_DISABLE;
1837         pause->rx_pause = priv->rx_pause ? true : false;
1838         pause->tx_pause = priv->tx_pause ? true : false;
1839 }
1840
1841 static int cpsw_set_pauseparam(struct net_device *ndev,
1842                                struct ethtool_pauseparam *pause)
1843 {
1844         struct cpsw_priv *priv = netdev_priv(ndev);
1845         bool link;
1846
1847         priv->rx_pause = pause->rx_pause ? true : false;
1848         priv->tx_pause = pause->tx_pause ? true : false;
1849
1850         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1851
1852         return 0;
1853 }
1854
1855 static const struct ethtool_ops cpsw_ethtool_ops = {
1856         .get_drvinfo    = cpsw_get_drvinfo,
1857         .get_msglevel   = cpsw_get_msglevel,
1858         .set_msglevel   = cpsw_set_msglevel,
1859         .get_link       = ethtool_op_get_link,
1860         .get_ts_info    = cpsw_get_ts_info,
1861         .get_settings   = cpsw_get_settings,
1862         .set_settings   = cpsw_set_settings,
1863         .get_coalesce   = cpsw_get_coalesce,
1864         .set_coalesce   = cpsw_set_coalesce,
1865         .get_sset_count         = cpsw_get_sset_count,
1866         .get_strings            = cpsw_get_strings,
1867         .get_ethtool_stats      = cpsw_get_ethtool_stats,
1868         .get_pauseparam         = cpsw_get_pauseparam,
1869         .set_pauseparam         = cpsw_set_pauseparam,
1870         .get_wol        = cpsw_get_wol,
1871         .set_wol        = cpsw_set_wol,
1872         .get_regs_len   = cpsw_get_regs_len,
1873         .get_regs       = cpsw_get_regs,
1874 };
1875
1876 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1877                             u32 slave_reg_ofs, u32 sliver_reg_ofs)
1878 {
1879         void __iomem            *regs = priv->regs;
1880         int                     slave_num = slave->slave_num;
1881         struct cpsw_slave_data  *data = priv->data.slave_data + slave_num;
1882
1883         slave->data     = data;
1884         slave->regs     = regs + slave_reg_ofs;
1885         slave->sliver   = regs + sliver_reg_ofs;
1886         slave->port_vlan = data->dual_emac_res_vlan;
1887 }
1888
1889 static int cpsw_probe_dt(struct cpsw_platform_data *data,
1890                          struct platform_device *pdev)
1891 {
1892         struct device_node *node = pdev->dev.of_node;
1893         struct device_node *slave_node;
1894         int i = 0, ret;
1895         u32 prop;
1896
1897         if (!node)
1898                 return -EINVAL;
1899
1900         if (of_property_read_u32(node, "slaves", &prop)) {
1901                 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
1902                 return -EINVAL;
1903         }
1904         data->slaves = prop;
1905
1906         if (of_property_read_u32(node, "active_slave", &prop)) {
1907                 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
1908                 return -EINVAL;
1909         }
1910         data->active_slave = prop;
1911
1912         if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
1913                 dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n");
1914                 return -EINVAL;
1915         }
1916         data->cpts_clock_mult = prop;
1917
1918         if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
1919                 dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n");
1920                 return -EINVAL;
1921         }
1922         data->cpts_clock_shift = prop;
1923
1924         data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
1925                                         * sizeof(struct cpsw_slave_data),
1926                                         GFP_KERNEL);
1927         if (!data->slave_data)
1928                 return -ENOMEM;
1929
1930         if (of_property_read_u32(node, "cpdma_channels", &prop)) {
1931                 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
1932                 return -EINVAL;
1933         }
1934         data->channels = prop;
1935
1936         if (of_property_read_u32(node, "ale_entries", &prop)) {
1937                 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
1938                 return -EINVAL;
1939         }
1940         data->ale_entries = prop;
1941
1942         if (of_property_read_u32(node, "bd_ram_size", &prop)) {
1943                 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
1944                 return -EINVAL;
1945         }
1946         data->bd_ram_size = prop;
1947
1948         if (of_property_read_u32(node, "rx_descs", &prop)) {
1949                 dev_err(&pdev->dev, "Missing rx_descs property in the DT.\n");
1950                 return -EINVAL;
1951         }
1952         data->rx_descs = prop;
1953
1954         if (of_property_read_u32(node, "mac_control", &prop)) {
1955                 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
1956                 return -EINVAL;
1957         }
1958         data->mac_control = prop;
1959
1960         if (of_property_read_bool(node, "dual_emac"))
1961                 data->dual_emac = 1;
1962
1963         /*
1964          * Populate all the child nodes here...
1965          */
1966         ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
1967         /* We do not want to force this, as in some cases may not have child */
1968         if (ret)
1969                 dev_warn(&pdev->dev, "Doesn't have any child node\n");
1970
1971         for_each_child_of_node(node, slave_node) {
1972                 struct cpsw_slave_data *slave_data = data->slave_data + i;
1973                 const void *mac_addr = NULL;
1974                 u32 phyid;
1975                 int lenp;
1976                 const __be32 *parp;
1977                 struct device_node *mdio_node;
1978                 struct platform_device *mdio;
1979
1980                 /* This is no slave child node, continue */
1981                 if (strcmp(slave_node->name, "slave"))
1982                         continue;
1983
1984                 parp = of_get_property(slave_node, "phy_id", &lenp);
1985                 if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) {
1986                         dev_err(&pdev->dev, "Missing slave[%d] phy_id property\n", i);
1987                         goto no_phy_slave;
1988                 }
1989                 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
1990                 phyid = be32_to_cpup(parp+1);
1991                 mdio = of_find_device_by_node(mdio_node);
1992                 of_node_put(mdio_node);
1993                 if (!mdio) {
1994                         dev_err(&pdev->dev, "Missing mdio platform device\n");
1995                         return -EINVAL;
1996                 }
1997                 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
1998                          PHY_ID_FMT, mdio->name, phyid);
1999
2000                 slave_data->phy_if = of_get_phy_mode(slave_node);
2001                 if (slave_data->phy_if < 0) {
2002                         dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2003                                 i);
2004                         return slave_data->phy_if;
2005                 }
2006
2007 no_phy_slave:
2008                 mac_addr = of_get_mac_address(slave_node);
2009                 if (mac_addr) {
2010                         memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
2011                 } else {
2012                         if (of_machine_is_compatible("ti,am33xx")) {
2013                                 ret = cpsw_am33xx_cm_get_macid(&pdev->dev,
2014                                                         0x630, i,
2015                                                         slave_data->mac_addr);
2016                                 if (ret)
2017                                         return ret;
2018                         }
2019                 }
2020                 if (data->dual_emac) {
2021                         if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
2022                                                  &prop)) {
2023                                 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
2024                                 slave_data->dual_emac_res_vlan = i+1;
2025                                 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2026                                         slave_data->dual_emac_res_vlan, i);
2027                         } else {
2028                                 slave_data->dual_emac_res_vlan = prop;
2029                         }
2030                 }
2031
2032                 i++;
2033                 if (i == data->slaves)
2034                         break;
2035         }
2036
2037         return 0;
2038 }
2039
2040 static int cpsw_probe_dual_emac(struct platform_device *pdev,
2041                                 struct cpsw_priv *priv)
2042 {
2043         struct cpsw_platform_data       *data = &priv->data;
2044         struct net_device               *ndev;
2045         struct cpsw_priv                *priv_sl2;
2046         int ret = 0, i;
2047
2048         ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2049         if (!ndev) {
2050                 dev_err(&pdev->dev, "cpsw: error allocating net_device\n");
2051                 return -ENOMEM;
2052         }
2053
2054         priv_sl2 = netdev_priv(ndev);
2055         spin_lock_init(&priv_sl2->lock);
2056         priv_sl2->data = *data;
2057         priv_sl2->pdev = pdev;
2058         priv_sl2->ndev = ndev;
2059         priv_sl2->dev  = &ndev->dev;
2060         priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2061         priv_sl2->rx_packet_max = max(rx_packet_max, 128);
2062
2063         if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2064                 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2065                         ETH_ALEN);
2066                 dev_info(&pdev->dev, "cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
2067         } else {
2068                 random_ether_addr(priv_sl2->mac_addr);
2069                 dev_info(&pdev->dev, "cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
2070         }
2071         memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2072
2073         priv_sl2->slaves = priv->slaves;
2074         priv_sl2->clk = priv->clk;
2075
2076         priv_sl2->coal_intvl = 0;
2077         priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
2078
2079         priv_sl2->regs = priv->regs;
2080         priv_sl2->host_port = priv->host_port;
2081         priv_sl2->host_port_regs = priv->host_port_regs;
2082         priv_sl2->wr_regs = priv->wr_regs;
2083         priv_sl2->hw_stats = priv->hw_stats;
2084         priv_sl2->dma = priv->dma;
2085         priv_sl2->txch = priv->txch;
2086         priv_sl2->rxch = priv->rxch;
2087         priv_sl2->ale = priv->ale;
2088         priv_sl2->emac_port = 1;
2089         priv->slaves[1].ndev = ndev;
2090         priv_sl2->cpts = priv->cpts;
2091         priv_sl2->version = priv->version;
2092
2093         for (i = 0; i < priv->num_irqs; i++) {
2094                 priv_sl2->irqs_table[i] = priv->irqs_table[i];
2095                 priv_sl2->num_irqs = priv->num_irqs;
2096         }
2097         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2098
2099         ndev->netdev_ops = &cpsw_netdev_ops;
2100         ndev->ethtool_ops = &cpsw_ethtool_ops;
2101
2102         /* register the network device */
2103         SET_NETDEV_DEV(ndev, &pdev->dev);
2104         ret = register_netdev(ndev);
2105         if (ret) {
2106                 dev_err(&pdev->dev, "cpsw: error registering net device\n");
2107                 free_netdev(ndev);
2108                 ret = -ENODEV;
2109         }
2110
2111         return ret;
2112 }
2113
2114 static int cpsw_probe(struct platform_device *pdev)
2115 {
2116         struct cpsw_platform_data       *data;
2117         struct net_device               *ndev;
2118         struct cpsw_priv                *priv;
2119         struct cpdma_params             dma_params;
2120         struct cpsw_ale_params          ale_params;
2121         void __iomem                    *ss_regs;
2122         struct resource                 *res, *ss_res;
2123         u32 slave_offset, sliver_offset, slave_size;
2124         int ret = 0, i;
2125         int irq;
2126
2127         ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2128         if (!ndev) {
2129                 dev_err(&pdev->dev, "error allocating net_device\n");
2130                 return -ENOMEM;
2131         }
2132
2133         platform_set_drvdata(pdev, ndev);
2134         priv = netdev_priv(ndev);
2135         spin_lock_init(&priv->lock);
2136         priv->pdev = pdev;
2137         priv->ndev = ndev;
2138         priv->dev  = &ndev->dev;
2139         priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2140         priv->rx_packet_max = max(rx_packet_max, 128);
2141         priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
2142         if (!priv->cpts) {
2143                 dev_err(&pdev->dev, "error allocating cpts\n");
2144                 ret = -ENOMEM;
2145                 goto clean_ndev_ret;
2146         }
2147
2148         /*
2149          * This may be required here for child devices.
2150          */
2151         pm_runtime_enable(&pdev->dev);
2152
2153         /* Select default pin state */
2154         pinctrl_pm_select_default_state(&pdev->dev);
2155
2156         if (cpsw_probe_dt(&priv->data, pdev)) {
2157                 dev_err(&pdev->dev, "cpsw: platform data missing\n");
2158                 ret = -ENODEV;
2159                 goto clean_runtime_disable_ret;
2160         }
2161         data = &priv->data;
2162
2163         if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2164                 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
2165                 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
2166         } else {
2167                 eth_random_addr(priv->mac_addr);
2168                 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
2169         }
2170
2171         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2172
2173         priv->slaves = devm_kzalloc(&pdev->dev,
2174                                     sizeof(struct cpsw_slave) * data->slaves,
2175                                     GFP_KERNEL);
2176         if (!priv->slaves) {
2177                 ret = -ENOMEM;
2178                 goto clean_runtime_disable_ret;
2179         }
2180         for (i = 0; i < data->slaves; i++)
2181                 priv->slaves[i].slave_num = i;
2182
2183         priv->slaves[0].ndev = ndev;
2184         priv->emac_port = 0;
2185
2186         priv->clk = devm_clk_get(&pdev->dev, "fck");
2187         if (IS_ERR(priv->clk)) {
2188                 dev_err(priv->dev, "fck is not found\n");
2189                 ret = -ENODEV;
2190                 goto clean_runtime_disable_ret;
2191         }
2192         priv->coal_intvl = 0;
2193         priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
2194
2195         ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2196         ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2197         if (IS_ERR(ss_regs)) {
2198                 ret = PTR_ERR(ss_regs);
2199                 goto clean_runtime_disable_ret;
2200         }
2201         priv->regs = ss_regs;
2202         priv->host_port = HOST_PORT_NUM;
2203
2204         /* Need to enable clocks with runtime PM api to access module
2205          * registers
2206          */
2207         pm_runtime_get_sync(&pdev->dev);
2208         priv->version = readl(&priv->regs->id_ver);
2209         pm_runtime_put_sync(&pdev->dev);
2210
2211         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2212         priv->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2213         if (IS_ERR(priv->wr_regs)) {
2214                 ret = PTR_ERR(priv->wr_regs);
2215                 goto clean_runtime_disable_ret;
2216         }
2217
2218         memset(&dma_params, 0, sizeof(dma_params));
2219         memset(&ale_params, 0, sizeof(ale_params));
2220
2221         switch (priv->version) {
2222         case CPSW_VERSION_1:
2223                 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
2224                 priv->cpts->reg      = ss_regs + CPSW1_CPTS_OFFSET;
2225                 priv->hw_stats       = ss_regs + CPSW1_HW_STATS;
2226                 dma_params.dmaregs   = ss_regs + CPSW1_CPDMA_OFFSET;
2227                 dma_params.txhdp     = ss_regs + CPSW1_STATERAM_OFFSET;
2228                 ale_params.ale_regs  = ss_regs + CPSW1_ALE_OFFSET;
2229                 slave_offset         = CPSW1_SLAVE_OFFSET;
2230                 slave_size           = CPSW1_SLAVE_SIZE;
2231                 sliver_offset        = CPSW1_SLIVER_OFFSET;
2232                 dma_params.desc_mem_phys = 0;
2233                 break;
2234         case CPSW_VERSION_2:
2235         case CPSW_VERSION_3:
2236         case CPSW_VERSION_4:
2237                 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
2238                 priv->cpts->reg      = ss_regs + CPSW2_CPTS_OFFSET;
2239                 priv->hw_stats       = ss_regs + CPSW2_HW_STATS;
2240                 dma_params.dmaregs   = ss_regs + CPSW2_CPDMA_OFFSET;
2241                 dma_params.txhdp     = ss_regs + CPSW2_STATERAM_OFFSET;
2242                 ale_params.ale_regs  = ss_regs + CPSW2_ALE_OFFSET;
2243                 slave_offset         = CPSW2_SLAVE_OFFSET;
2244                 slave_size           = CPSW2_SLAVE_SIZE;
2245                 sliver_offset        = CPSW2_SLIVER_OFFSET;
2246                 dma_params.desc_mem_phys =
2247                         (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
2248                 break;
2249         default:
2250                 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
2251                 ret = -ENODEV;
2252                 goto clean_runtime_disable_ret;
2253         }
2254         for (i = 0; i < priv->data.slaves; i++) {
2255                 struct cpsw_slave *slave = &priv->slaves[i];
2256                 cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
2257                 slave_offset  += slave_size;
2258                 sliver_offset += SLIVER_SIZE;
2259         }
2260
2261         dma_params.dev          = &pdev->dev;
2262         dma_params.rxthresh     = dma_params.dmaregs + CPDMA_RXTHRESH;
2263         dma_params.rxfree       = dma_params.dmaregs + CPDMA_RXFREE;
2264         dma_params.rxhdp        = dma_params.txhdp + CPDMA_RXHDP;
2265         dma_params.txcp         = dma_params.txhdp + CPDMA_TXCP;
2266         dma_params.rxcp         = dma_params.txhdp + CPDMA_RXCP;
2267
2268         dma_params.num_chan             = data->channels;
2269         dma_params.has_soft_reset       = true;
2270         dma_params.min_packet_size      = CPSW_MIN_PACKET_SIZE;
2271         dma_params.desc_mem_size        = data->bd_ram_size;
2272         dma_params.desc_align           = 16;
2273         dma_params.has_ext_regs         = true;
2274         dma_params.desc_hw_addr         = dma_params.desc_mem_phys;
2275
2276         priv->dma = cpdma_ctlr_create(&dma_params);
2277         if (!priv->dma) {
2278                 dev_err(priv->dev, "error initializing dma\n");
2279                 ret = -ENOMEM;
2280                 goto clean_runtime_disable_ret;
2281         }
2282
2283         priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
2284                                        cpsw_tx_handler);
2285         priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
2286                                        cpsw_rx_handler);
2287
2288         if (WARN_ON(!priv->txch || !priv->rxch)) {
2289                 dev_err(priv->dev, "error initializing dma channels\n");
2290                 ret = -ENOMEM;
2291                 goto clean_dma_ret;
2292         }
2293
2294         ale_params.dev                  = &ndev->dev;
2295         ale_params.ale_ageout           = ale_ageout;
2296         ale_params.ale_entries          = data->ale_entries;
2297         ale_params.ale_ports            = data->slaves;
2298
2299         priv->ale = cpsw_ale_create(&ale_params);
2300         if (!priv->ale) {
2301                 dev_err(priv->dev, "error initializing ale engine\n");
2302                 ret = -ENODEV;
2303                 goto clean_dma_ret;
2304         }
2305
2306         ndev->irq = platform_get_irq(pdev, 1);
2307         if (ndev->irq < 0) {
2308                 dev_err(priv->dev, "error getting irq resource\n");
2309                 ret = -ENOENT;
2310                 goto clean_ale_ret;
2311         }
2312
2313         /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
2314          * MISC IRQs which are always kept disabled with this driver so
2315          * we will not request them.
2316          *
2317          * If anyone wants to implement support for those, make sure to
2318          * first request and append them to irqs_table array.
2319          */
2320
2321         /* RX IRQ */
2322         irq = platform_get_irq(pdev, 1);
2323         if (irq < 0)
2324                 goto clean_ale_ret;
2325
2326         priv->irqs_table[0] = irq;
2327         ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
2328                                0, dev_name(&pdev->dev), priv);
2329         if (ret < 0) {
2330                 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2331                 goto clean_ale_ret;
2332         }
2333
2334         /* TX IRQ */
2335         irq = platform_get_irq(pdev, 2);
2336         if (irq < 0)
2337                 goto clean_ale_ret;
2338
2339         priv->irqs_table[1] = irq;
2340         ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
2341                                0, dev_name(&pdev->dev), priv);
2342         if (ret < 0) {
2343                 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2344                 goto clean_ale_ret;
2345         }
2346         priv->num_irqs = 2;
2347
2348         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2349
2350         ndev->netdev_ops = &cpsw_netdev_ops;
2351         ndev->ethtool_ops = &cpsw_ethtool_ops;
2352         netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT);
2353
2354         /* register the network device */
2355         SET_NETDEV_DEV(ndev, &pdev->dev);
2356         ret = register_netdev(ndev);
2357         if (ret) {
2358                 dev_err(priv->dev, "error registering net device\n");
2359                 ret = -ENODEV;
2360                 goto clean_ale_ret;
2361         }
2362
2363         cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
2364                     &ss_res->start, ndev->irq);
2365
2366         if (priv->data.dual_emac) {
2367                 ret = cpsw_probe_dual_emac(pdev, priv);
2368                 if (ret) {
2369                         cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
2370                         goto clean_ale_ret;
2371                 }
2372         }
2373
2374         return 0;
2375
2376 clean_ale_ret:
2377         cpsw_ale_destroy(priv->ale);
2378 clean_dma_ret:
2379         cpdma_chan_destroy(priv->txch);
2380         cpdma_chan_destroy(priv->rxch);
2381         cpdma_ctlr_destroy(priv->dma);
2382 clean_runtime_disable_ret:
2383         pm_runtime_disable(&pdev->dev);
2384 clean_ndev_ret:
2385         free_netdev(priv->ndev);
2386         return ret;
2387 }
2388
2389 static int cpsw_remove_child_device(struct device *dev, void *c)
2390 {
2391         struct platform_device *pdev = to_platform_device(dev);
2392
2393         of_device_unregister(pdev);
2394
2395         return 0;
2396 }
2397
2398 static int cpsw_remove(struct platform_device *pdev)
2399 {
2400         struct net_device *ndev = platform_get_drvdata(pdev);
2401         struct cpsw_priv *priv = netdev_priv(ndev);
2402
2403         if (priv->data.dual_emac)
2404                 unregister_netdev(cpsw_get_slave_ndev(priv, 1));
2405         unregister_netdev(ndev);
2406
2407         cpsw_ale_destroy(priv->ale);
2408         cpdma_chan_destroy(priv->txch);
2409         cpdma_chan_destroy(priv->rxch);
2410         cpdma_ctlr_destroy(priv->dma);
2411         pm_runtime_disable(&pdev->dev);
2412         device_for_each_child(&pdev->dev, NULL, cpsw_remove_child_device);
2413         if (priv->data.dual_emac)
2414                 free_netdev(cpsw_get_slave_ndev(priv, 1));
2415         free_netdev(ndev);
2416         return 0;
2417 }
2418
2419 #ifdef CONFIG_PM_SLEEP
2420 static int cpsw_suspend(struct device *dev)
2421 {
2422         struct platform_device  *pdev = to_platform_device(dev);
2423         struct net_device       *ndev = platform_get_drvdata(pdev);
2424         struct cpsw_priv        *priv = netdev_priv(ndev);
2425
2426         if (priv->data.dual_emac) {
2427                 int i;
2428
2429                 for (i = 0; i < priv->data.slaves; i++) {
2430                         if (netif_running(priv->slaves[i].ndev))
2431                                 cpsw_ndo_stop(priv->slaves[i].ndev);
2432                         soft_reset_slave(priv->slaves + i);
2433                 }
2434         } else {
2435                 if (netif_running(ndev))
2436                         cpsw_ndo_stop(ndev);
2437                 for_each_slave(priv, soft_reset_slave);
2438         }
2439
2440         pm_runtime_put_sync(&pdev->dev);
2441
2442         /* Select sleep pin state */
2443         pinctrl_pm_select_sleep_state(&pdev->dev);
2444
2445         return 0;
2446 }
2447
2448 static int cpsw_resume(struct device *dev)
2449 {
2450         struct platform_device  *pdev = to_platform_device(dev);
2451         struct net_device       *ndev = platform_get_drvdata(pdev);
2452         struct cpsw_priv        *priv = netdev_priv(ndev);
2453
2454         pm_runtime_get_sync(&pdev->dev);
2455
2456         /* Select default pin state */
2457         pinctrl_pm_select_default_state(&pdev->dev);
2458
2459         if (priv->data.dual_emac) {
2460                 int i;
2461
2462                 for (i = 0; i < priv->data.slaves; i++) {
2463                         if (netif_running(priv->slaves[i].ndev))
2464                                 cpsw_ndo_open(priv->slaves[i].ndev);
2465                 }
2466         } else {
2467                 if (netif_running(ndev))
2468                         cpsw_ndo_open(ndev);
2469         }
2470         return 0;
2471 }
2472 #endif
2473
2474 static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
2475
2476 static const struct of_device_id cpsw_of_mtable[] = {
2477         { .compatible = "ti,cpsw", },
2478         { /* sentinel */ },
2479 };
2480 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2481
2482 static struct platform_driver cpsw_driver = {
2483         .driver = {
2484                 .name    = "cpsw",
2485                 .pm      = &cpsw_pm_ops,
2486                 .of_match_table = cpsw_of_mtable,
2487         },
2488         .probe = cpsw_probe,
2489         .remove = cpsw_remove,
2490 };
2491
2492 static int __init cpsw_init(void)
2493 {
2494         return platform_driver_register(&cpsw_driver);
2495 }
2496 late_initcall(cpsw_init);
2497
2498 static void __exit cpsw_exit(void)
2499 {
2500         platform_driver_unregister(&cpsw_driver);
2501 }
2502 module_exit(cpsw_exit);
2503
2504 MODULE_LICENSE("GPL");
2505 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2506 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2507 MODULE_DESCRIPTION("TI CPSW Ethernet driver");