2 * DaVinci Ethernet Medium Access Controller
4 * DaVinci EMAC is based upon CPPI 3.0 TI DMA engine
6 * Copyright (C) 2009 Texas Instruments.
8 * ---------------------------------------------------------------------------
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 * ---------------------------------------------------------------------------
25 * 0-5 A number of folks worked on this driver in bits and pieces but the major
26 * contribution came from Suraj Iyer and Anant Gole
27 * 6.0 Anant Gole - rewrote the driver as per Linux conventions
28 * 6.1 Chaithrika U S - added support for Gigabit and RMII features,
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/sched.h>
35 #include <linux/string.h>
36 #include <linux/timer.h>
37 #include <linux/errno.h>
39 #include <linux/ioport.h>
40 #include <linux/slab.h>
42 #include <linux/interrupt.h>
43 #include <linux/init.h>
44 #include <linux/netdevice.h>
45 #include <linux/etherdevice.h>
46 #include <linux/skbuff.h>
47 #include <linux/ethtool.h>
48 #include <linux/highmem.h>
49 #include <linux/proc_fs.h>
50 #include <linux/ctype.h>
51 #include <linux/spinlock.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/clk.h>
54 #include <linux/platform_device.h>
55 #include <linux/semaphore.h>
56 #include <linux/phy.h>
57 #include <linux/bitops.h>
59 #include <linux/uaccess.h>
60 #include <linux/davinci_emac.h>
62 #include <linux/of_address.h>
63 #include <linux/of_irq.h>
64 #include <linux/of_net.h>
69 #include "davinci_cpdma.h"
71 static int debug_level;
72 module_param(debug_level, int, 0);
73 MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)");
75 /* Netif debug messages possible */
76 #define DAVINCI_EMAC_DEBUG (NETIF_MSG_DRV | \
84 NETIF_MSG_TX_QUEUED | \
87 NETIF_MSG_RX_STATUS | \
93 #define EMAC_MAJOR_VERSION 6
94 #define EMAC_MINOR_VERSION 1
95 #define EMAC_MODULE_VERSION "6.1"
96 MODULE_VERSION(EMAC_MODULE_VERSION);
97 static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
99 /* Configuration items */
100 #define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC up to frames */
101 #define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */
102 #define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */
103 #define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */
104 #define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */
105 #define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */
106 #define EMAC_DEF_PROM_EN (0) /* Promiscuous disabled */
107 #define EMAC_DEF_PROM_CH (0) /* Promiscuous channel is 0 */
108 #define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */
109 #define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */
110 #define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */
111 #define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */
113 #define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */
114 #define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/
116 #define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */
117 #define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */
118 #define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4)
119 #define EMAC_DEF_TX_CH (0) /* Default 0th channel */
120 #define EMAC_DEF_RX_CH (0) /* Default 0th channel */
121 #define EMAC_DEF_RX_NUM_DESC (128)
122 #define EMAC_DEF_TX_NUM_DESC (128)
123 #define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */
124 #define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */
125 #define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */
127 /* Buffer descriptor parameters */
128 #define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */
129 #define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */
131 /* EMAC register related defines */
132 #define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF)
133 #define EMAC_NUM_MULTICAST_BITS (64)
134 #define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1)
135 #define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1)
136 #define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2)
137 #define EMAC_RX_UNICAST_CLEAR_ALL (0xFF)
138 #define EMAC_INT_MASK_CLEAR (0xFF)
140 /* RX MBP register bit positions */
141 #define EMAC_RXMBP_PASSCRC_MASK BIT(30)
142 #define EMAC_RXMBP_QOSEN_MASK BIT(29)
143 #define EMAC_RXMBP_NOCHAIN_MASK BIT(28)
144 #define EMAC_RXMBP_CMFEN_MASK BIT(24)
145 #define EMAC_RXMBP_CSFEN_MASK BIT(23)
146 #define EMAC_RXMBP_CEFEN_MASK BIT(22)
147 #define EMAC_RXMBP_CAFEN_MASK BIT(21)
148 #define EMAC_RXMBP_PROMCH_SHIFT (16)
149 #define EMAC_RXMBP_PROMCH_MASK (0x7 << 16)
150 #define EMAC_RXMBP_BROADEN_MASK BIT(13)
151 #define EMAC_RXMBP_BROADCH_SHIFT (8)
152 #define EMAC_RXMBP_BROADCH_MASK (0x7 << 8)
153 #define EMAC_RXMBP_MULTIEN_MASK BIT(5)
154 #define EMAC_RXMBP_MULTICH_SHIFT (0)
155 #define EMAC_RXMBP_MULTICH_MASK (0x7)
156 #define EMAC_RXMBP_CHMASK (0x7)
158 /* EMAC register definitions/bit maps used */
159 # define EMAC_MBP_RXPROMISC (0x00200000)
160 # define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16)
161 # define EMAC_MBP_RXBCAST (0x00002000)
162 # define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8)
163 # define EMAC_MBP_RXMCAST (0x00000020)
164 # define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7)
166 /* EMAC mac_control register */
167 #define EMAC_MACCONTROL_TXPTYPE BIT(9)
168 #define EMAC_MACCONTROL_TXPACEEN BIT(6)
169 #define EMAC_MACCONTROL_GMIIEN BIT(5)
170 #define EMAC_MACCONTROL_GIGABITEN BIT(7)
171 #define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0)
172 #define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15)
174 /* GIGABIT MODE related bits */
175 #define EMAC_DM646X_MACCONTORL_GIG BIT(7)
176 #define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17)
178 /* EMAC mac_status register */
179 #define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000)
180 #define EMAC_MACSTATUS_TXERRCODE_SHIFT (20)
181 #define EMAC_MACSTATUS_TXERRCH_MASK (0x7)
182 #define EMAC_MACSTATUS_TXERRCH_SHIFT (16)
183 #define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000)
184 #define EMAC_MACSTATUS_RXERRCODE_SHIFT (12)
185 #define EMAC_MACSTATUS_RXERRCH_MASK (0x7)
186 #define EMAC_MACSTATUS_RXERRCH_SHIFT (8)
188 /* EMAC RX register masks */
189 #define EMAC_RX_MAX_LEN_MASK (0xFFFF)
190 #define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF)
192 /* MAC_IN_VECTOR (0x180) register bit fields */
193 #define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17)
194 #define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16)
195 #define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8)
196 #define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0)
198 /** NOTE:: For DM646x the IN_VECTOR has changed */
199 #define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH)
200 #define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH)
201 #define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26)
202 #define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27)
204 /* CPPI bit positions */
205 #define EMAC_CPPI_SOP_BIT BIT(31)
206 #define EMAC_CPPI_EOP_BIT BIT(30)
207 #define EMAC_CPPI_OWNERSHIP_BIT BIT(29)
208 #define EMAC_CPPI_EOQ_BIT BIT(28)
209 #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27)
210 #define EMAC_CPPI_PASS_CRC_BIT BIT(26)
211 #define EMAC_RX_BD_BUF_SIZE (0xFFFF)
212 #define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */
213 #define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF)
215 /* Max hardware defines */
216 #define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */
217 #define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */
219 /* EMAC Peripheral Device Register Memory Layout structure */
220 #define EMAC_MACINVECTOR 0x90
222 #define EMAC_DM646X_MACEOIVECTOR 0x94
224 #define EMAC_MACINTSTATRAW 0xB0
225 #define EMAC_MACINTSTATMASKED 0xB4
226 #define EMAC_MACINTMASKSET 0xB8
227 #define EMAC_MACINTMASKCLEAR 0xBC
229 #define EMAC_RXMBPENABLE 0x100
230 #define EMAC_RXUNICASTSET 0x104
231 #define EMAC_RXUNICASTCLEAR 0x108
232 #define EMAC_RXMAXLEN 0x10C
233 #define EMAC_RXBUFFEROFFSET 0x110
234 #define EMAC_RXFILTERLOWTHRESH 0x114
236 #define EMAC_MACCONTROL 0x160
237 #define EMAC_MACSTATUS 0x164
238 #define EMAC_EMCONTROL 0x168
239 #define EMAC_FIFOCONTROL 0x16C
240 #define EMAC_MACCONFIG 0x170
241 #define EMAC_SOFTRESET 0x174
242 #define EMAC_MACSRCADDRLO 0x1D0
243 #define EMAC_MACSRCADDRHI 0x1D4
244 #define EMAC_MACHASH1 0x1D8
245 #define EMAC_MACHASH2 0x1DC
246 #define EMAC_MACADDRLO 0x500
247 #define EMAC_MACADDRHI 0x504
248 #define EMAC_MACINDEX 0x508
250 /* EMAC statistics registers */
251 #define EMAC_RXGOODFRAMES 0x200
252 #define EMAC_RXBCASTFRAMES 0x204
253 #define EMAC_RXMCASTFRAMES 0x208
254 #define EMAC_RXPAUSEFRAMES 0x20C
255 #define EMAC_RXCRCERRORS 0x210
256 #define EMAC_RXALIGNCODEERRORS 0x214
257 #define EMAC_RXOVERSIZED 0x218
258 #define EMAC_RXJABBER 0x21C
259 #define EMAC_RXUNDERSIZED 0x220
260 #define EMAC_RXFRAGMENTS 0x224
261 #define EMAC_RXFILTERED 0x228
262 #define EMAC_RXQOSFILTERED 0x22C
263 #define EMAC_RXOCTETS 0x230
264 #define EMAC_TXGOODFRAMES 0x234
265 #define EMAC_TXBCASTFRAMES 0x238
266 #define EMAC_TXMCASTFRAMES 0x23C
267 #define EMAC_TXPAUSEFRAMES 0x240
268 #define EMAC_TXDEFERRED 0x244
269 #define EMAC_TXCOLLISION 0x248
270 #define EMAC_TXSINGLECOLL 0x24C
271 #define EMAC_TXMULTICOLL 0x250
272 #define EMAC_TXEXCESSIVECOLL 0x254
273 #define EMAC_TXLATECOLL 0x258
274 #define EMAC_TXUNDERRUN 0x25C
275 #define EMAC_TXCARRIERSENSE 0x260
276 #define EMAC_TXOCTETS 0x264
277 #define EMAC_NETOCTETS 0x280
278 #define EMAC_RXSOFOVERRUNS 0x284
279 #define EMAC_RXMOFOVERRUNS 0x288
280 #define EMAC_RXDMAOVERRUNS 0x28C
282 /* EMAC DM644x control registers */
283 #define EMAC_CTRL_EWCTL (0x4)
284 #define EMAC_CTRL_EWINTTCNT (0x8)
286 /* EMAC DM644x control module masks */
287 #define EMAC_DM644X_EWINTCNT_MASK 0x1FFFF
288 #define EMAC_DM644X_INTMIN_INTVL 0x1
289 #define EMAC_DM644X_INTMAX_INTVL (EMAC_DM644X_EWINTCNT_MASK)
291 /* EMAC DM646X control module registers */
292 #define EMAC_DM646X_CMINTCTRL 0x0C
293 #define EMAC_DM646X_CMRXINTEN 0x14
294 #define EMAC_DM646X_CMTXINTEN 0x18
295 #define EMAC_DM646X_CMRXINTMAX 0x70
296 #define EMAC_DM646X_CMTXINTMAX 0x74
298 /* EMAC DM646X control module masks */
299 #define EMAC_DM646X_INTPACEEN (0x3 << 16)
300 #define EMAC_DM646X_INTPRESCALE_MASK (0x7FF << 0)
301 #define EMAC_DM646X_CMINTMAX_CNT 63
302 #define EMAC_DM646X_CMINTMIN_CNT 2
303 #define EMAC_DM646X_CMINTMAX_INTVL (1000 / EMAC_DM646X_CMINTMIN_CNT)
304 #define EMAC_DM646X_CMINTMIN_INTVL ((1000 / EMAC_DM646X_CMINTMAX_CNT) + 1)
307 /* EMAC EOI codes for C0 */
308 #define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01)
309 #define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02)
311 /* EMAC Stats Clear Mask */
312 #define EMAC_STATS_CLR_MASK (0xFFFFFFFF)
314 /* emac_priv: EMAC private data structure
316 * EMAC adapter private data structure
320 struct net_device *ndev;
321 struct platform_device *pdev;
322 struct napi_struct napi;
324 void __iomem *remap_addr;
326 void __iomem *emac_base;
327 void __iomem *ctrl_base;
328 struct cpdma_ctlr *dma;
329 struct cpdma_chan *txchan;
330 struct cpdma_chan *rxchan;
331 u32 link; /* 1=link on, 0=link off */
332 u32 speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */
333 u32 duplex; /* Link duplex: 0=Half, 1=Full */
342 u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS];
347 struct device_node *phy_node;
349 struct phy_device *phydev;
351 /*platform specific members*/
352 void (*int_enable) (void);
353 void (*int_disable) (void);
356 /* clock frequency for EMAC */
357 static struct clk *emac_clk;
358 static unsigned long emac_bus_frequency;
360 /* EMAC TX Host Error description strings */
361 static char *emac_txhost_errcodes[16] = {
362 "No error", "SOP error", "Ownership bit not set in SOP buffer",
363 "Zero Next Buffer Descriptor Pointer Without EOP",
364 "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error",
365 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
366 "Reserved", "Reserved", "Reserved", "Reserved"
369 /* EMAC RX Host Error description strings */
370 static char *emac_rxhost_errcodes[16] = {
371 "No error", "Reserved", "Ownership bit not set in input buffer",
372 "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved",
373 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
374 "Reserved", "Reserved", "Reserved", "Reserved"
378 #define emac_read(reg) ioread32(priv->emac_base + (reg))
379 #define emac_write(reg, val) iowrite32(val, priv->emac_base + (reg))
381 #define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg)))
382 #define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg)))
385 * emac_dump_regs - Dump important EMAC registers to debug terminal
386 * @priv: The DaVinci EMAC private adapter structure
388 * Executes ethtool set cmd & sets phy mode
391 static void emac_dump_regs(struct emac_priv *priv)
393 struct device *emac_dev = &priv->ndev->dev;
395 /* Print important registers in EMAC */
396 dev_info(emac_dev, "EMAC Basic registers\n");
397 if (priv->version == EMAC_VERSION_1) {
398 dev_info(emac_dev, "EMAC: EWCTL: %08X, EWINTTCNT: %08X\n",
399 emac_ctrl_read(EMAC_CTRL_EWCTL),
400 emac_ctrl_read(EMAC_CTRL_EWINTTCNT));
402 dev_info(emac_dev, "EMAC: EmuControl:%08X, FifoControl: %08X\n",
403 emac_read(EMAC_EMCONTROL), emac_read(EMAC_FIFOCONTROL));
404 dev_info(emac_dev, "EMAC: MBPEnable:%08X, RXUnicastSet: %08X, "\
405 "RXMaxLen=%08X\n", emac_read(EMAC_RXMBPENABLE),
406 emac_read(EMAC_RXUNICASTSET), emac_read(EMAC_RXMAXLEN));
407 dev_info(emac_dev, "EMAC: MacControl:%08X, MacStatus: %08X, "\
408 "MacConfig=%08X\n", emac_read(EMAC_MACCONTROL),
409 emac_read(EMAC_MACSTATUS), emac_read(EMAC_MACCONFIG));
410 dev_info(emac_dev, "EMAC Statistics\n");
411 dev_info(emac_dev, "EMAC: rx_good_frames:%d\n",
412 emac_read(EMAC_RXGOODFRAMES));
413 dev_info(emac_dev, "EMAC: rx_broadcast_frames:%d\n",
414 emac_read(EMAC_RXBCASTFRAMES));
415 dev_info(emac_dev, "EMAC: rx_multicast_frames:%d\n",
416 emac_read(EMAC_RXMCASTFRAMES));
417 dev_info(emac_dev, "EMAC: rx_pause_frames:%d\n",
418 emac_read(EMAC_RXPAUSEFRAMES));
419 dev_info(emac_dev, "EMAC: rx_crcerrors:%d\n",
420 emac_read(EMAC_RXCRCERRORS));
421 dev_info(emac_dev, "EMAC: rx_align_code_errors:%d\n",
422 emac_read(EMAC_RXALIGNCODEERRORS));
423 dev_info(emac_dev, "EMAC: rx_oversized_frames:%d\n",
424 emac_read(EMAC_RXOVERSIZED));
425 dev_info(emac_dev, "EMAC: rx_jabber_frames:%d\n",
426 emac_read(EMAC_RXJABBER));
427 dev_info(emac_dev, "EMAC: rx_undersized_frames:%d\n",
428 emac_read(EMAC_RXUNDERSIZED));
429 dev_info(emac_dev, "EMAC: rx_fragments:%d\n",
430 emac_read(EMAC_RXFRAGMENTS));
431 dev_info(emac_dev, "EMAC: rx_filtered_frames:%d\n",
432 emac_read(EMAC_RXFILTERED));
433 dev_info(emac_dev, "EMAC: rx_qos_filtered_frames:%d\n",
434 emac_read(EMAC_RXQOSFILTERED));
435 dev_info(emac_dev, "EMAC: rx_octets:%d\n",
436 emac_read(EMAC_RXOCTETS));
437 dev_info(emac_dev, "EMAC: tx_goodframes:%d\n",
438 emac_read(EMAC_TXGOODFRAMES));
439 dev_info(emac_dev, "EMAC: tx_bcastframes:%d\n",
440 emac_read(EMAC_TXBCASTFRAMES));
441 dev_info(emac_dev, "EMAC: tx_mcastframes:%d\n",
442 emac_read(EMAC_TXMCASTFRAMES));
443 dev_info(emac_dev, "EMAC: tx_pause_frames:%d\n",
444 emac_read(EMAC_TXPAUSEFRAMES));
445 dev_info(emac_dev, "EMAC: tx_deferred_frames:%d\n",
446 emac_read(EMAC_TXDEFERRED));
447 dev_info(emac_dev, "EMAC: tx_collision_frames:%d\n",
448 emac_read(EMAC_TXCOLLISION));
449 dev_info(emac_dev, "EMAC: tx_single_coll_frames:%d\n",
450 emac_read(EMAC_TXSINGLECOLL));
451 dev_info(emac_dev, "EMAC: tx_mult_coll_frames:%d\n",
452 emac_read(EMAC_TXMULTICOLL));
453 dev_info(emac_dev, "EMAC: tx_excessive_collisions:%d\n",
454 emac_read(EMAC_TXEXCESSIVECOLL));
455 dev_info(emac_dev, "EMAC: tx_late_collisions:%d\n",
456 emac_read(EMAC_TXLATECOLL));
457 dev_info(emac_dev, "EMAC: tx_underrun:%d\n",
458 emac_read(EMAC_TXUNDERRUN));
459 dev_info(emac_dev, "EMAC: tx_carrier_sense_errors:%d\n",
460 emac_read(EMAC_TXCARRIERSENSE));
461 dev_info(emac_dev, "EMAC: tx_octets:%d\n",
462 emac_read(EMAC_TXOCTETS));
463 dev_info(emac_dev, "EMAC: net_octets:%d\n",
464 emac_read(EMAC_NETOCTETS));
465 dev_info(emac_dev, "EMAC: rx_sof_overruns:%d\n",
466 emac_read(EMAC_RXSOFOVERRUNS));
467 dev_info(emac_dev, "EMAC: rx_mof_overruns:%d\n",
468 emac_read(EMAC_RXMOFOVERRUNS));
469 dev_info(emac_dev, "EMAC: rx_dma_overruns:%d\n",
470 emac_read(EMAC_RXDMAOVERRUNS));
472 cpdma_ctlr_dump(priv->dma);
476 * emac_get_drvinfo - Get EMAC driver information
477 * @ndev: The DaVinci EMAC network adapter
478 * @info: ethtool info structure containing name and version
480 * Returns EMAC driver information (name and version)
483 static void emac_get_drvinfo(struct net_device *ndev,
484 struct ethtool_drvinfo *info)
486 strcpy(info->driver, emac_version_string);
487 strcpy(info->version, EMAC_MODULE_VERSION);
491 * emac_get_settings - Get EMAC settings
492 * @ndev: The DaVinci EMAC network adapter
493 * @ecmd: ethtool command
495 * Executes ethool get command
498 static int emac_get_settings(struct net_device *ndev,
499 struct ethtool_cmd *ecmd)
501 struct emac_priv *priv = netdev_priv(ndev);
503 return phy_ethtool_gset(priv->phydev, ecmd);
510 * emac_set_settings - Set EMAC settings
511 * @ndev: The DaVinci EMAC network adapter
512 * @ecmd: ethtool command
514 * Executes ethool set command
517 static int emac_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
519 struct emac_priv *priv = netdev_priv(ndev);
521 return phy_ethtool_sset(priv->phydev, ecmd);
528 * emac_get_coalesce - Get interrupt coalesce settings for this device
529 * @ndev : The DaVinci EMAC network adapter
530 * @coal : ethtool coalesce settings structure
532 * Fetch the current interrupt coalesce settings
535 static int emac_get_coalesce(struct net_device *ndev,
536 struct ethtool_coalesce *coal)
538 struct emac_priv *priv = netdev_priv(ndev);
540 coal->rx_coalesce_usecs = priv->coal_intvl;
546 * emac_set_coalesce - Set interrupt coalesce settings for this device
547 * @ndev : The DaVinci EMAC network adapter
548 * @coal : ethtool coalesce settings structure
550 * Set interrupt coalesce parameters
553 static int emac_set_coalesce(struct net_device *ndev,
554 struct ethtool_coalesce *coal)
556 struct emac_priv *priv = netdev_priv(ndev);
557 u32 int_ctrl, num_interrupts = 0;
558 u32 prescale = 0, addnl_dvdr = 1, coal_intvl = 0;
560 if (!coal->rx_coalesce_usecs)
563 coal_intvl = coal->rx_coalesce_usecs;
565 switch (priv->version) {
567 int_ctrl = emac_ctrl_read(EMAC_DM646X_CMINTCTRL);
568 prescale = priv->bus_freq_mhz * 4;
570 if (coal_intvl < EMAC_DM646X_CMINTMIN_INTVL)
571 coal_intvl = EMAC_DM646X_CMINTMIN_INTVL;
573 if (coal_intvl > EMAC_DM646X_CMINTMAX_INTVL) {
575 * Interrupt pacer works with 4us Pulse, we can
576 * throttle further by dilating the 4us pulse.
578 addnl_dvdr = EMAC_DM646X_INTPRESCALE_MASK / prescale;
580 if (addnl_dvdr > 1) {
581 prescale *= addnl_dvdr;
582 if (coal_intvl > (EMAC_DM646X_CMINTMAX_INTVL
584 coal_intvl = (EMAC_DM646X_CMINTMAX_INTVL
588 coal_intvl = EMAC_DM646X_CMINTMAX_INTVL;
592 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
594 int_ctrl |= EMAC_DM646X_INTPACEEN;
595 int_ctrl &= (~EMAC_DM646X_INTPRESCALE_MASK);
596 int_ctrl |= (prescale & EMAC_DM646X_INTPRESCALE_MASK);
597 emac_ctrl_write(EMAC_DM646X_CMINTCTRL, int_ctrl);
599 emac_ctrl_write(EMAC_DM646X_CMRXINTMAX, num_interrupts);
600 emac_ctrl_write(EMAC_DM646X_CMTXINTMAX, num_interrupts);
604 int_ctrl = emac_ctrl_read(EMAC_CTRL_EWINTTCNT);
605 int_ctrl &= (~EMAC_DM644X_EWINTCNT_MASK);
606 prescale = coal_intvl * priv->bus_freq_mhz;
607 if (prescale > EMAC_DM644X_EWINTCNT_MASK) {
608 prescale = EMAC_DM644X_EWINTCNT_MASK;
609 coal_intvl = prescale / priv->bus_freq_mhz;
611 emac_ctrl_write(EMAC_CTRL_EWINTTCNT, (int_ctrl | prescale));
616 printk(KERN_INFO"Set coalesce to %d usecs.\n", coal_intvl);
617 priv->coal_intvl = coal_intvl;
624 /* ethtool_ops: DaVinci EMAC Ethtool structure
626 * Ethtool support for EMAC adapter
628 static const struct ethtool_ops ethtool_ops = {
629 .get_drvinfo = emac_get_drvinfo,
630 .get_settings = emac_get_settings,
631 .set_settings = emac_set_settings,
632 .get_link = ethtool_op_get_link,
633 .get_coalesce = emac_get_coalesce,
634 .set_coalesce = emac_set_coalesce,
635 .get_ts_info = ethtool_op_get_ts_info,
639 * emac_update_phystatus - Update Phy status
640 * @priv: The DaVinci EMAC private adapter structure
642 * Updates phy status and takes action for network queue if required
643 * based upon link status
646 static void emac_update_phystatus(struct emac_priv *priv)
651 struct net_device *ndev = priv->ndev;
653 mac_control = emac_read(EMAC_MACCONTROL);
654 cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ?
655 DUPLEX_FULL : DUPLEX_HALF;
657 new_duplex = priv->phydev->duplex;
659 new_duplex = DUPLEX_FULL;
661 /* We get called only if link has changed (speed/duplex/status) */
662 if ((priv->link) && (new_duplex != cur_duplex)) {
663 priv->duplex = new_duplex;
664 if (DUPLEX_FULL == priv->duplex)
665 mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN);
667 mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN);
670 if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) {
671 mac_control = emac_read(EMAC_MACCONTROL);
672 mac_control |= (EMAC_DM646X_MACCONTORL_GIG |
673 EMAC_DM646X_MACCONTORL_GIGFORCE);
675 /* Clear the GIG bit and GIGFORCE bit */
676 mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE |
677 EMAC_DM646X_MACCONTORL_GIG);
679 if (priv->rmii_en && (priv->speed == SPEED_100))
680 mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK;
682 mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK;
685 /* Update mac_control if changed */
686 emac_write(EMAC_MACCONTROL, mac_control);
690 if (!netif_carrier_ok(ndev))
691 netif_carrier_on(ndev);
692 /* reactivate the transmit queue if it is stopped */
693 if (netif_running(ndev) && netif_queue_stopped(ndev))
694 netif_wake_queue(ndev);
697 if (netif_carrier_ok(ndev))
698 netif_carrier_off(ndev);
699 if (!netif_queue_stopped(ndev))
700 netif_stop_queue(ndev);
705 * hash_get - Calculate hash value from mac address
706 * @addr: mac address to delete from hash table
708 * Calculates hash value from mac address
711 static u32 hash_get(u8 *addr)
718 for (cnt = 0; cnt < 2; cnt++) {
720 hash ^= (tmpval >> 2) ^ (tmpval << 4);
722 hash ^= (tmpval >> 4) ^ (tmpval << 2);
724 hash ^= (tmpval >> 6) ^ (tmpval);
731 * hash_add - Hash function to add mac addr from hash table
732 * @priv: The DaVinci EMAC private adapter structure
733 * @mac_addr: mac address to delete from hash table
735 * Adds mac address to the internal hash table
738 static int hash_add(struct emac_priv *priv, u8 *mac_addr)
740 struct device *emac_dev = &priv->ndev->dev;
743 u32 hash_value = hash_get(mac_addr);
745 if (hash_value >= EMAC_NUM_MULTICAST_BITS) {
746 if (netif_msg_drv(priv)) {
747 dev_err(emac_dev, "DaVinci EMAC: hash_add(): Invalid "\
748 "Hash %08x, should not be greater than %08x",
749 hash_value, (EMAC_NUM_MULTICAST_BITS - 1));
754 /* set the hash bit only if not previously set */
755 if (priv->multicast_hash_cnt[hash_value] == 0) {
756 rc = 1; /* hash value changed */
757 if (hash_value < 32) {
758 hash_bit = BIT(hash_value);
759 priv->mac_hash1 |= hash_bit;
761 hash_bit = BIT((hash_value - 32));
762 priv->mac_hash2 |= hash_bit;
766 /* incr counter for num of mcast addr's mapped to "this" hash bit */
767 ++priv->multicast_hash_cnt[hash_value];
773 * hash_del - Hash function to delete mac addr from hash table
774 * @priv: The DaVinci EMAC private adapter structure
775 * @mac_addr: mac address to delete from hash table
777 * Removes mac address from the internal hash table
780 static int hash_del(struct emac_priv *priv, u8 *mac_addr)
785 hash_value = hash_get(mac_addr);
786 if (priv->multicast_hash_cnt[hash_value] > 0) {
787 /* dec cntr for num of mcast addr's mapped to this hash bit */
788 --priv->multicast_hash_cnt[hash_value];
791 /* if counter still > 0, at least one multicast address refers
792 * to this hash bit. so return 0 */
793 if (priv->multicast_hash_cnt[hash_value] > 0)
796 if (hash_value < 32) {
797 hash_bit = BIT(hash_value);
798 priv->mac_hash1 &= ~hash_bit;
800 hash_bit = BIT((hash_value - 32));
801 priv->mac_hash2 &= ~hash_bit;
804 /* return 1 to indicate change in mac_hash registers reqd */
808 /* EMAC multicast operation */
809 #define EMAC_MULTICAST_ADD 0
810 #define EMAC_MULTICAST_DEL 1
811 #define EMAC_ALL_MULTI_SET 2
812 #define EMAC_ALL_MULTI_CLR 3
815 * emac_add_mcast - Set multicast address in the EMAC adapter (Internal)
816 * @priv: The DaVinci EMAC private adapter structure
817 * @action: multicast operation to perform
818 * mac_addr: mac address to set
820 * Set multicast addresses in EMAC adapter - internal function
823 static void emac_add_mcast(struct emac_priv *priv, u32 action, u8 *mac_addr)
825 struct device *emac_dev = &priv->ndev->dev;
829 case EMAC_MULTICAST_ADD:
830 update = hash_add(priv, mac_addr);
832 case EMAC_MULTICAST_DEL:
833 update = hash_del(priv, mac_addr);
835 case EMAC_ALL_MULTI_SET:
837 priv->mac_hash1 = EMAC_ALL_MULTI_REG_VALUE;
838 priv->mac_hash2 = EMAC_ALL_MULTI_REG_VALUE;
840 case EMAC_ALL_MULTI_CLR:
844 memset(&(priv->multicast_hash_cnt[0]), 0,
845 sizeof(priv->multicast_hash_cnt[0]) *
846 EMAC_NUM_MULTICAST_BITS);
849 if (netif_msg_drv(priv))
850 dev_err(emac_dev, "DaVinci EMAC: add_mcast"\
851 ": bad operation %d", action);
855 /* write to the hardware only if the register status chances */
857 emac_write(EMAC_MACHASH1, priv->mac_hash1);
858 emac_write(EMAC_MACHASH2, priv->mac_hash2);
863 * emac_dev_mcast_set - Set multicast address in the EMAC adapter
864 * @ndev: The DaVinci EMAC network adapter
866 * Set multicast addresses in EMAC adapter
869 static void emac_dev_mcast_set(struct net_device *ndev)
872 struct emac_priv *priv = netdev_priv(ndev);
874 mbp_enable = emac_read(EMAC_RXMBPENABLE);
875 if (ndev->flags & IFF_PROMISC) {
876 mbp_enable &= (~EMAC_MBP_PROMISCCH(EMAC_DEF_PROM_CH));
877 mbp_enable |= (EMAC_MBP_RXPROMISC);
879 mbp_enable = (mbp_enable & ~EMAC_MBP_RXPROMISC);
880 if ((ndev->flags & IFF_ALLMULTI) ||
881 netdev_mc_count(ndev) > EMAC_DEF_MAX_MULTICAST_ADDRESSES) {
882 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
883 emac_add_mcast(priv, EMAC_ALL_MULTI_SET, NULL);
885 if (!netdev_mc_empty(ndev)) {
886 struct netdev_hw_addr *ha;
888 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
889 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
890 /* program multicast address list into EMAC hardware */
891 netdev_for_each_mc_addr(ha, ndev) {
892 emac_add_mcast(priv, EMAC_MULTICAST_ADD,
896 mbp_enable = (mbp_enable & ~EMAC_MBP_RXMCAST);
897 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
900 /* Set mbp config register */
901 emac_write(EMAC_RXMBPENABLE, mbp_enable);
904 /*************************************************************************
905 * EMAC Hardware manipulation
906 *************************************************************************/
909 * emac_int_disable - Disable EMAC module interrupt (from adapter)
910 * @priv: The DaVinci EMAC private adapter structure
912 * Disable EMAC interrupt on the adapter
915 static void emac_int_disable(struct emac_priv *priv)
917 if (priv->version == EMAC_VERSION_2) {
920 local_irq_save(flags);
922 /* Program C0_Int_En to zero to turn off
923 * interrupts to the CPU */
924 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0);
925 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0);
926 /* NOTE: Rx Threshold and Misc interrupts are not disabled */
927 if (priv->int_disable)
930 local_irq_restore(flags);
933 /* Set DM644x control registers for interrupt control */
934 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0);
939 * emac_int_enable - Enable EMAC module interrupt (from adapter)
940 * @priv: The DaVinci EMAC private adapter structure
942 * Enable EMAC interrupt on the adapter
945 static void emac_int_enable(struct emac_priv *priv)
947 if (priv->version == EMAC_VERSION_2) {
948 if (priv->int_enable)
951 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff);
952 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff);
954 /* In addition to turning on interrupt Enable, we need
955 * ack by writing appropriate values to the EOI
958 /* NOTE: Rx Threshold and Misc interrupts are not enabled */
960 /* ack rxen only then a new pulse will be generated */
961 emac_write(EMAC_DM646X_MACEOIVECTOR,
962 EMAC_DM646X_MAC_EOI_C0_RXEN);
964 /* ack txen- only then a new pulse will be generated */
965 emac_write(EMAC_DM646X_MACEOIVECTOR,
966 EMAC_DM646X_MAC_EOI_C0_TXEN);
969 /* Set DM644x control registers for interrupt control */
970 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1);
975 * emac_irq - EMAC interrupt handler
976 * @irq: interrupt number
977 * @dev_id: EMAC network adapter data structure ptr
979 * EMAC Interrupt handler - we only schedule NAPI and not process any packets
980 * here. EVen the interrupt status is checked (TX/RX/Err) in NAPI poll function
982 * Returns interrupt handled condition
984 static irqreturn_t emac_irq(int irq, void *dev_id)
986 struct net_device *ndev = (struct net_device *)dev_id;
987 struct emac_priv *priv = netdev_priv(ndev);
990 if (likely(netif_running(priv->ndev))) {
991 emac_int_disable(priv);
992 napi_schedule(&priv->napi);
994 /* we are closing down, so dont process anything */
999 static struct sk_buff *emac_rx_alloc(struct emac_priv *priv)
1001 struct sk_buff *skb = netdev_alloc_skb(priv->ndev, priv->rx_buf_size);
1004 skb_reserve(skb, NET_IP_ALIGN);
1008 static void emac_rx_handler(void *token, int len, int status)
1010 struct sk_buff *skb = token;
1011 struct net_device *ndev = skb->dev;
1012 struct emac_priv *priv = netdev_priv(ndev);
1013 struct device *emac_dev = &ndev->dev;
1016 /* free and bail if we are shutting down */
1017 if (unlikely(!netif_running(ndev))) {
1018 dev_kfree_skb_any(skb);
1022 /* recycle on receive error */
1024 ndev->stats.rx_errors++;
1028 /* feed received packet up the stack */
1030 skb->protocol = eth_type_trans(skb, ndev);
1031 netif_receive_skb(skb);
1032 ndev->stats.rx_bytes += len;
1033 ndev->stats.rx_packets++;
1035 /* alloc a new packet for receive */
1036 skb = emac_rx_alloc(priv);
1038 if (netif_msg_rx_err(priv) && net_ratelimit())
1039 dev_err(emac_dev, "failed rx buffer alloc\n");
1044 ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
1045 skb_tailroom(skb), GFP_KERNEL);
1047 WARN_ON(ret == -ENOMEM);
1048 if (unlikely(ret < 0))
1049 dev_kfree_skb_any(skb);
1052 static void emac_tx_handler(void *token, int len, int status)
1054 struct sk_buff *skb = token;
1055 struct net_device *ndev = skb->dev;
1056 struct emac_priv *priv = netdev_priv(ndev);
1058 atomic_dec(&priv->cur_tx);
1060 if (unlikely(netif_queue_stopped(ndev)))
1061 netif_start_queue(ndev);
1062 ndev->stats.tx_packets++;
1063 ndev->stats.tx_bytes += len;
1064 dev_kfree_skb_any(skb);
1068 * emac_dev_xmit - EMAC Transmit function
1070 * @ndev: The DaVinci EMAC network adapter
1072 * Called by the system to transmit a packet - we queue the packet in
1073 * EMAC hardware transmit queue
1075 * Returns success(NETDEV_TX_OK) or error code (typically out of desc's)
1077 static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev)
1079 struct device *emac_dev = &ndev->dev;
1081 struct emac_priv *priv = netdev_priv(ndev);
1083 /* If no link, return */
1084 if (unlikely(!priv->link)) {
1085 if (netif_msg_tx_err(priv) && net_ratelimit())
1086 dev_err(emac_dev, "DaVinci EMAC: No link to transmit");
1090 ret_code = skb_padto(skb, EMAC_DEF_MIN_ETHPKTSIZE);
1091 if (unlikely(ret_code < 0)) {
1092 if (netif_msg_tx_err(priv) && net_ratelimit())
1093 dev_err(emac_dev, "DaVinci EMAC: packet pad failed");
1097 skb_tx_timestamp(skb);
1099 ret_code = cpdma_chan_submit(priv->txchan, skb, skb->data, skb->len,
1101 if (unlikely(ret_code != 0)) {
1102 if (netif_msg_tx_err(priv) && net_ratelimit())
1103 dev_err(emac_dev, "DaVinci EMAC: desc submit failed");
1107 if (atomic_inc_return(&priv->cur_tx) >= EMAC_DEF_TX_NUM_DESC)
1108 netif_stop_queue(ndev);
1110 return NETDEV_TX_OK;
1113 ndev->stats.tx_dropped++;
1114 netif_stop_queue(ndev);
1115 return NETDEV_TX_BUSY;
1119 * emac_dev_tx_timeout - EMAC Transmit timeout function
1120 * @ndev: The DaVinci EMAC network adapter
1122 * Called when system detects that a skb timeout period has expired
1123 * potentially due to a fault in the adapter in not being able to send
1124 * it out on the wire. We teardown the TX channel assuming a hardware
1125 * error and re-initialize the TX channel for hardware operation
1128 static void emac_dev_tx_timeout(struct net_device *ndev)
1130 struct emac_priv *priv = netdev_priv(ndev);
1131 struct device *emac_dev = &ndev->dev;
1133 if (netif_msg_tx_err(priv))
1134 dev_err(emac_dev, "DaVinci EMAC: xmit timeout, restarting TX");
1136 emac_dump_regs(priv);
1138 ndev->stats.tx_errors++;
1139 emac_int_disable(priv);
1140 cpdma_chan_stop(priv->txchan);
1141 cpdma_chan_start(priv->txchan);
1142 emac_int_enable(priv);
1146 * emac_set_type0addr - Set EMAC Type0 mac address
1147 * @priv: The DaVinci EMAC private adapter structure
1148 * @ch: RX channel number
1149 * @mac_addr: MAC address to set in device
1151 * Called internally to set Type0 mac address of the adapter (Device)
1153 * Returns success (0) or appropriate error code (none as of now)
1155 static void emac_set_type0addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1158 val = ((mac_addr[5] << 8) | (mac_addr[4]));
1159 emac_write(EMAC_MACSRCADDRLO, val);
1161 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1162 (mac_addr[1] << 8) | (mac_addr[0]));
1163 emac_write(EMAC_MACSRCADDRHI, val);
1164 val = emac_read(EMAC_RXUNICASTSET);
1166 emac_write(EMAC_RXUNICASTSET, val);
1167 val = emac_read(EMAC_RXUNICASTCLEAR);
1169 emac_write(EMAC_RXUNICASTCLEAR, val);
1173 * emac_set_type1addr - Set EMAC Type1 mac address
1174 * @priv: The DaVinci EMAC private adapter structure
1175 * @ch: RX channel number
1176 * @mac_addr: MAC address to set in device
1178 * Called internally to set Type1 mac address of the adapter (Device)
1180 * Returns success (0) or appropriate error code (none as of now)
1182 static void emac_set_type1addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1185 emac_write(EMAC_MACINDEX, ch);
1186 val = ((mac_addr[5] << 8) | mac_addr[4]);
1187 emac_write(EMAC_MACADDRLO, val);
1188 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1189 (mac_addr[1] << 8) | (mac_addr[0]));
1190 emac_write(EMAC_MACADDRHI, val);
1191 emac_set_type0addr(priv, ch, mac_addr);
1195 * emac_set_type2addr - Set EMAC Type2 mac address
1196 * @priv: The DaVinci EMAC private adapter structure
1197 * @ch: RX channel number
1198 * @mac_addr: MAC address to set in device
1199 * @index: index into RX address entries
1200 * @match: match parameter for RX address matching logic
1202 * Called internally to set Type2 mac address of the adapter (Device)
1204 * Returns success (0) or appropriate error code (none as of now)
1206 static void emac_set_type2addr(struct emac_priv *priv, u32 ch,
1207 char *mac_addr, int index, int match)
1210 emac_write(EMAC_MACINDEX, index);
1211 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1212 (mac_addr[1] << 8) | (mac_addr[0]));
1213 emac_write(EMAC_MACADDRHI, val);
1214 val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \
1215 (match << 19) | BIT(20));
1216 emac_write(EMAC_MACADDRLO, val);
1217 emac_set_type0addr(priv, ch, mac_addr);
1221 * emac_setmac - Set mac address in the adapter (internal function)
1222 * @priv: The DaVinci EMAC private adapter structure
1223 * @ch: RX channel number
1224 * @mac_addr: MAC address to set in device
1226 * Called internally to set the mac address of the adapter (Device)
1228 * Returns success (0) or appropriate error code (none as of now)
1230 static void emac_setmac(struct emac_priv *priv, u32 ch, char *mac_addr)
1232 struct device *emac_dev = &priv->ndev->dev;
1234 if (priv->rx_addr_type == 0) {
1235 emac_set_type0addr(priv, ch, mac_addr);
1236 } else if (priv->rx_addr_type == 1) {
1238 for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++)
1239 emac_set_type1addr(priv, ch, mac_addr);
1240 } else if (priv->rx_addr_type == 2) {
1241 emac_set_type2addr(priv, ch, mac_addr, ch, 1);
1242 emac_set_type0addr(priv, ch, mac_addr);
1244 if (netif_msg_drv(priv))
1245 dev_err(emac_dev, "DaVinci EMAC: Wrong addressing\n");
1250 * emac_dev_setmac_addr - Set mac address in the adapter
1251 * @ndev: The DaVinci EMAC network adapter
1252 * @addr: MAC address to set in device
1254 * Called by the system to set the mac address of the adapter (Device)
1256 * Returns success (0) or appropriate error code (none as of now)
1258 static int emac_dev_setmac_addr(struct net_device *ndev, void *addr)
1260 struct emac_priv *priv = netdev_priv(ndev);
1261 struct device *emac_dev = &priv->ndev->dev;
1262 struct sockaddr *sa = addr;
1264 if (!is_valid_ether_addr(sa->sa_data))
1265 return -EADDRNOTAVAIL;
1267 /* Store mac addr in priv and rx channel and set it in EMAC hw */
1268 memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len);
1269 memcpy(ndev->dev_addr, sa->sa_data, ndev->addr_len);
1270 ndev->addr_assign_type &= ~NET_ADDR_RANDOM;
1272 /* MAC address is configured only after the interface is enabled. */
1273 if (netif_running(ndev)) {
1274 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
1277 if (netif_msg_drv(priv))
1278 dev_notice(emac_dev, "DaVinci EMAC: emac_dev_setmac_addr %pM\n",
1285 * emac_hw_enable - Enable EMAC hardware for packet transmission/reception
1286 * @priv: The DaVinci EMAC private adapter structure
1288 * Enables EMAC hardware for packet processing - enables PHY, enables RX
1289 * for packet reception and enables device interrupts and then NAPI
1291 * Returns success (0) or appropriate error code (none right now)
1293 static int emac_hw_enable(struct emac_priv *priv)
1295 u32 val, mbp_enable, mac_control;
1298 emac_write(EMAC_SOFTRESET, 1);
1299 while (emac_read(EMAC_SOFTRESET))
1302 /* Disable interrupt & Set pacing for more interrupts initially */
1303 emac_int_disable(priv);
1305 /* Full duplex enable bit set when auto negotiation happens */
1307 (((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) |
1308 ((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) |
1309 ((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) |
1310 ((priv->duplex == DUPLEX_FULL) ? 0x1 : 0));
1311 emac_write(EMAC_MACCONTROL, mac_control);
1314 (((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) |
1315 ((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) |
1316 ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) |
1317 ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) |
1318 ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) |
1319 ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) |
1320 ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) |
1321 ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \
1322 EMAC_RXMBP_PROMCH_SHIFT) |
1323 ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) |
1324 ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \
1325 EMAC_RXMBP_BROADCH_SHIFT) |
1326 ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) |
1327 ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \
1328 EMAC_RXMBP_MULTICH_SHIFT));
1329 emac_write(EMAC_RXMBPENABLE, mbp_enable);
1330 emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE &
1331 EMAC_RX_MAX_LEN_MASK));
1332 emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET &
1333 EMAC_RX_BUFFER_OFFSET_MASK));
1334 emac_write(EMAC_RXFILTERLOWTHRESH, 0);
1335 emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL);
1336 priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF;
1338 emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL);
1340 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
1343 val = emac_read(EMAC_MACCONTROL);
1344 val |= (EMAC_MACCONTROL_GMIIEN);
1345 emac_write(EMAC_MACCONTROL, val);
1347 /* Enable NAPI and interrupts */
1348 napi_enable(&priv->napi);
1349 emac_int_enable(priv);
1355 * emac_poll - EMAC NAPI Poll function
1356 * @ndev: The DaVinci EMAC network adapter
1357 * @budget: Number of receive packets to process (as told by NAPI layer)
1359 * NAPI Poll function implemented to process packets as per budget. We check
1360 * the type of interrupt on the device and accordingly call the TX or RX
1361 * packet processing functions. We follow the budget for RX processing and
1362 * also put a cap on number of TX pkts processed through config param. The
1363 * NAPI schedule function is called if more packets pending.
1365 * Returns number of packets received (in most cases; else TX pkts - rarely)
1367 static int emac_poll(struct napi_struct *napi, int budget)
1370 struct emac_priv *priv = container_of(napi, struct emac_priv, napi);
1371 struct net_device *ndev = priv->ndev;
1372 struct device *emac_dev = &ndev->dev;
1374 u32 num_tx_pkts = 0, num_rx_pkts = 0;
1376 /* Check interrupt vectors and call packet processing */
1377 status = emac_read(EMAC_MACINVECTOR);
1379 mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC;
1381 if (priv->version == EMAC_VERSION_2)
1382 mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC;
1384 if (status & mask) {
1385 num_tx_pkts = cpdma_chan_process(priv->txchan,
1386 EMAC_DEF_TX_MAX_SERVICE);
1387 } /* TX processing */
1389 mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC;
1391 if (priv->version == EMAC_VERSION_2)
1392 mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC;
1394 if (status & mask) {
1395 num_rx_pkts = cpdma_chan_process(priv->rxchan, budget);
1396 } /* RX processing */
1398 mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT;
1399 if (priv->version == EMAC_VERSION_2)
1400 mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT;
1402 if (unlikely(status & mask)) {
1404 dev_err(emac_dev, "DaVinci EMAC: Fatal Hardware Error\n");
1405 netif_stop_queue(ndev);
1406 napi_disable(&priv->napi);
1408 status = emac_read(EMAC_MACSTATUS);
1409 cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >>
1410 EMAC_MACSTATUS_TXERRCODE_SHIFT);
1412 ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >>
1413 EMAC_MACSTATUS_TXERRCH_SHIFT);
1414 if (net_ratelimit()) {
1415 dev_err(emac_dev, "TX Host error %s on ch=%d\n",
1416 &emac_txhost_errcodes[cause][0], ch);
1419 cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >>
1420 EMAC_MACSTATUS_RXERRCODE_SHIFT);
1422 ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >>
1423 EMAC_MACSTATUS_RXERRCH_SHIFT);
1424 if (netif_msg_hw(priv) && net_ratelimit())
1425 dev_err(emac_dev, "RX Host error %s on ch=%d\n",
1426 &emac_rxhost_errcodes[cause][0], ch);
1428 } else if (num_rx_pkts < budget) {
1429 napi_complete(napi);
1430 emac_int_enable(priv);
1436 #ifdef CONFIG_NET_POLL_CONTROLLER
1438 * emac_poll_controller - EMAC Poll controller function
1439 * @ndev: The DaVinci EMAC network adapter
1441 * Polled functionality used by netconsole and others in non interrupt mode
1444 void emac_poll_controller(struct net_device *ndev)
1446 struct emac_priv *priv = netdev_priv(ndev);
1448 emac_int_disable(priv);
1449 emac_irq(ndev->irq, ndev);
1450 emac_int_enable(priv);
1454 static void emac_adjust_link(struct net_device *ndev)
1456 struct emac_priv *priv = netdev_priv(ndev);
1457 struct phy_device *phydev = priv->phydev;
1458 unsigned long flags;
1461 spin_lock_irqsave(&priv->lock, flags);
1464 /* check the mode of operation - full/half duplex */
1465 if (phydev->duplex != priv->duplex) {
1467 priv->duplex = phydev->duplex;
1469 if (phydev->speed != priv->speed) {
1471 priv->speed = phydev->speed;
1478 } else if (priv->link) {
1485 emac_update_phystatus(priv);
1486 phy_print_status(priv->phydev);
1489 spin_unlock_irqrestore(&priv->lock, flags);
1492 /*************************************************************************
1493 * Linux Driver Model
1494 *************************************************************************/
1497 * emac_devioctl - EMAC adapter ioctl
1498 * @ndev: The DaVinci EMAC network adapter
1499 * @ifrq: request parameter
1500 * @cmd: command parameter
1502 * EMAC driver ioctl function
1504 * Returns success(0) or appropriate error code
1506 static int emac_devioctl(struct net_device *ndev, struct ifreq *ifrq, int cmd)
1508 struct emac_priv *priv = netdev_priv(ndev);
1510 if (!(netif_running(ndev)))
1513 /* TODO: Add phy read and write and private statistics get feature */
1515 return phy_mii_ioctl(priv->phydev, ifrq, cmd);
1518 static int match_first_device(struct device *dev, void *data)
1520 return !strncmp(dev_name(dev), "davinci_mdio", 12);
1524 * emac_dev_open - EMAC device open
1525 * @ndev: The DaVinci EMAC network adapter
1527 * Called when system wants to start the interface. We init TX/RX channels
1528 * and enable the hardware for packet reception/transmission and start the
1531 * Returns 0 for a successful open, or appropriate error code
1533 static int emac_dev_open(struct net_device *ndev)
1535 struct device *emac_dev = &ndev->dev;
1537 struct resource *res;
1541 struct emac_priv *priv = netdev_priv(ndev);
1543 netif_carrier_off(ndev);
1544 for (cnt = 0; cnt < ETH_ALEN; cnt++)
1545 ndev->dev_addr[cnt] = priv->mac_addr[cnt];
1547 /* Configuration items */
1548 priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN;
1550 priv->mac_hash1 = 0;
1551 priv->mac_hash2 = 0;
1552 emac_write(EMAC_MACHASH1, 0);
1553 emac_write(EMAC_MACHASH2, 0);
1555 for (i = 0; i < EMAC_DEF_RX_NUM_DESC; i++) {
1556 struct sk_buff *skb = emac_rx_alloc(priv);
1561 ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
1562 skb_tailroom(skb), GFP_KERNEL);
1563 if (WARN_ON(ret < 0))
1569 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
1570 for (i = res->start; i <= res->end; i++) {
1571 if (request_irq(i, emac_irq, IRQF_DISABLED,
1578 /* Start/Enable EMAC hardware */
1579 emac_hw_enable(priv);
1581 /* Enable Interrupt pacing if configured */
1582 if (priv->coal_intvl != 0) {
1583 struct ethtool_coalesce coal;
1585 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1586 emac_set_coalesce(ndev, &coal);
1589 cpdma_ctlr_start(priv->dma);
1591 priv->phydev = NULL;
1592 /* use the first phy on the bus if pdata did not give us a phy id */
1593 if (!priv->phy_id) {
1596 phy = bus_find_device(&mdio_bus_type, NULL, NULL,
1597 match_first_device);
1599 priv->phy_id = dev_name(phy);
1602 if (priv->phy_id && *priv->phy_id) {
1603 priv->phydev = phy_connect(ndev, priv->phy_id,
1604 &emac_adjust_link, 0,
1605 PHY_INTERFACE_MODE_MII);
1607 if (IS_ERR(priv->phydev)) {
1608 dev_err(emac_dev, "could not connect to phy %s\n",
1610 ret = PTR_ERR(priv->phydev);
1611 priv->phydev = NULL;
1619 dev_info(emac_dev, "attached PHY driver [%s] "
1620 "(mii_bus:phy_addr=%s, id=%x)\n",
1621 priv->phydev->drv->name, dev_name(&priv->phydev->dev),
1622 priv->phydev->phy_id);
1624 /* No PHY , fix the link, speed and duplex settings */
1625 dev_notice(emac_dev, "no phy, defaulting to 100/full\n");
1627 priv->speed = SPEED_100;
1628 priv->duplex = DUPLEX_FULL;
1629 emac_update_phystatus(priv);
1632 if (!netif_running(ndev)) /* debug only - to avoid compiler warning */
1633 emac_dump_regs(priv);
1635 if (netif_msg_drv(priv))
1636 dev_notice(emac_dev, "DaVinci EMAC: Opened %s\n", ndev->name);
1639 phy_start(priv->phydev);
1645 dev_err(emac_dev, "DaVinci EMAC: request_irq() failed");
1647 for (q = k; k >= 0; k--) {
1648 for (m = i; m >= res->start; m--)
1650 res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k-1);
1657 * emac_dev_stop - EMAC device stop
1658 * @ndev: The DaVinci EMAC network adapter
1660 * Called when system wants to stop or down the interface. We stop the network
1661 * queue, disable interrupts and cleanup TX/RX channels.
1663 * We return the statistics in net_device_stats structure pulled from emac
1665 static int emac_dev_stop(struct net_device *ndev)
1667 struct resource *res;
1670 struct emac_priv *priv = netdev_priv(ndev);
1671 struct device *emac_dev = &ndev->dev;
1673 /* inform the upper layers. */
1674 netif_stop_queue(ndev);
1675 napi_disable(&priv->napi);
1677 netif_carrier_off(ndev);
1678 emac_int_disable(priv);
1679 cpdma_ctlr_stop(priv->dma);
1680 emac_write(EMAC_SOFTRESET, 1);
1683 phy_disconnect(priv->phydev);
1686 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, i))) {
1687 for (irq_num = res->start; irq_num <= res->end; irq_num++)
1688 free_irq(irq_num, priv->ndev);
1692 if (netif_msg_drv(priv))
1693 dev_notice(emac_dev, "DaVinci EMAC: %s stopped\n", ndev->name);
1699 * emac_dev_getnetstats - EMAC get statistics function
1700 * @ndev: The DaVinci EMAC network adapter
1702 * Called when system wants to get statistics from the device.
1704 * We return the statistics in net_device_stats structure pulled from emac
1706 static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev)
1708 struct emac_priv *priv = netdev_priv(ndev);
1710 u32 stats_clear_mask;
1712 /* update emac hardware stats and reset the registers*/
1714 mac_control = emac_read(EMAC_MACCONTROL);
1716 if (mac_control & EMAC_MACCONTROL_GMIIEN)
1717 stats_clear_mask = EMAC_STATS_CLR_MASK;
1719 stats_clear_mask = 0;
1721 ndev->stats.multicast += emac_read(EMAC_RXMCASTFRAMES);
1722 emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask);
1724 ndev->stats.collisions += (emac_read(EMAC_TXCOLLISION) +
1725 emac_read(EMAC_TXSINGLECOLL) +
1726 emac_read(EMAC_TXMULTICOLL));
1727 emac_write(EMAC_TXCOLLISION, stats_clear_mask);
1728 emac_write(EMAC_TXSINGLECOLL, stats_clear_mask);
1729 emac_write(EMAC_TXMULTICOLL, stats_clear_mask);
1731 ndev->stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) +
1732 emac_read(EMAC_RXJABBER) +
1733 emac_read(EMAC_RXUNDERSIZED));
1734 emac_write(EMAC_RXOVERSIZED, stats_clear_mask);
1735 emac_write(EMAC_RXJABBER, stats_clear_mask);
1736 emac_write(EMAC_RXUNDERSIZED, stats_clear_mask);
1738 ndev->stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) +
1739 emac_read(EMAC_RXMOFOVERRUNS));
1740 emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask);
1741 emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask);
1743 ndev->stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS);
1744 emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask);
1746 ndev->stats.tx_carrier_errors +=
1747 emac_read(EMAC_TXCARRIERSENSE);
1748 emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask);
1750 ndev->stats.tx_fifo_errors += emac_read(EMAC_TXUNDERRUN);
1751 emac_write(EMAC_TXUNDERRUN, stats_clear_mask);
1753 return &ndev->stats;
1756 static const struct net_device_ops emac_netdev_ops = {
1757 .ndo_open = emac_dev_open,
1758 .ndo_stop = emac_dev_stop,
1759 .ndo_start_xmit = emac_dev_xmit,
1760 .ndo_set_rx_mode = emac_dev_mcast_set,
1761 .ndo_set_mac_address = emac_dev_setmac_addr,
1762 .ndo_do_ioctl = emac_devioctl,
1763 .ndo_tx_timeout = emac_dev_tx_timeout,
1764 .ndo_get_stats = emac_dev_getnetstats,
1765 #ifdef CONFIG_NET_POLL_CONTROLLER
1766 .ndo_poll_controller = emac_poll_controller,
1771 static struct emac_platform_data
1772 *davinci_emac_of_get_pdata(struct platform_device *pdev,
1773 struct emac_priv *priv)
1775 struct device_node *np;
1776 struct emac_platform_data *pdata = NULL;
1781 pdata = pdev->dev.platform_data;
1783 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1788 np = pdev->dev.of_node;
1792 pdata->version = EMAC_VERSION_2;
1794 if (!is_valid_ether_addr(pdata->mac_addr)) {
1795 mac_addr = of_get_mac_address(np);
1797 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
1800 ret = of_property_read_u32(np, "ti,davinci-ctrl-reg-offset", &data);
1802 pdata->ctrl_reg_offset = data;
1804 ret = of_property_read_u32(np, "ti,davinci-ctrl-mod-reg-offset",
1807 pdata->ctrl_mod_reg_offset = data;
1809 ret = of_property_read_u32(np, "ti,davinci-ctrl-ram-offset", &data);
1811 pdata->ctrl_ram_offset = data;
1813 ret = of_property_read_u32(np, "ti,davinci-ctrl-ram-size", &data);
1815 pdata->ctrl_ram_size = data;
1817 ret = of_property_read_u32(np, "ti,davinci-rmii-en", &data);
1819 pdata->rmii_en = data;
1821 ret = of_property_read_u32(np, "ti,davinci-no-bd-ram", &data);
1823 pdata->no_bd_ram = data;
1825 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
1826 if (!priv->phy_node)
1829 pdev->dev.platform_data = pdata;
1834 static struct emac_platform_data
1835 *davinci_emac_of_get_pdata(struct platform_device *pdev,
1836 struct emac_priv *priv)
1838 return pdev->dev.platform_data;
1842 * davinci_emac_probe - EMAC device probe
1843 * @pdev: The DaVinci EMAC device that we are removing
1845 * Called when probing for emac devicesr. We get details of instances and
1846 * resource information from platform init and register a network device
1847 * and allocate resources necessary for driver to perform
1849 static int __devinit davinci_emac_probe(struct platform_device *pdev)
1852 struct resource *res;
1853 struct net_device *ndev;
1854 struct emac_priv *priv;
1855 unsigned long size, hw_ram_addr;
1856 struct emac_platform_data *pdata;
1857 struct device *emac_dev;
1858 struct cpdma_params dma_params;
1860 /* obtain emac clock from kernel */
1861 emac_clk = clk_get(&pdev->dev, NULL);
1862 if (IS_ERR(emac_clk)) {
1863 dev_err(&pdev->dev, "failed to get EMAC clock\n");
1866 emac_bus_frequency = clk_get_rate(emac_clk);
1867 /* TODO: Probe PHY here if possible */
1869 ndev = alloc_etherdev(sizeof(struct emac_priv));
1875 platform_set_drvdata(pdev, ndev);
1876 priv = netdev_priv(ndev);
1879 priv->msg_enable = netif_msg_init(debug_level, DAVINCI_EMAC_DEBUG);
1881 spin_lock_init(&priv->lock);
1883 pdata = davinci_emac_of_get_pdata(pdev, priv);
1885 dev_err(&pdev->dev, "no platform data\n");
1890 /* MAC addr and PHY mask , RMII enable info from platform_data */
1891 memcpy(priv->mac_addr, pdata->mac_addr, 6);
1892 priv->phy_id = pdata->phy_id;
1893 priv->rmii_en = pdata->rmii_en;
1894 priv->version = pdata->version;
1895 priv->int_enable = pdata->interrupt_enable;
1896 priv->int_disable = pdata->interrupt_disable;
1898 priv->coal_intvl = 0;
1899 priv->bus_freq_mhz = (u32)(emac_bus_frequency / 1000000);
1901 emac_dev = &ndev->dev;
1902 /* Get EMAC platform data */
1903 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1905 dev_err(&pdev->dev,"error getting res\n");
1910 priv->emac_base_phys = res->start + pdata->ctrl_reg_offset;
1911 size = resource_size(res);
1912 if (!request_mem_region(res->start, size, ndev->name)) {
1913 dev_err(&pdev->dev, "failed request_mem_region() for regs\n");
1918 priv->remap_addr = ioremap(res->start, size);
1919 if (!priv->remap_addr) {
1920 dev_err(&pdev->dev, "unable to map IO\n");
1922 release_mem_region(res->start, size);
1925 priv->emac_base = priv->remap_addr + pdata->ctrl_reg_offset;
1926 ndev->base_addr = (unsigned long)priv->remap_addr;
1928 priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset;
1930 hw_ram_addr = pdata->hw_ram_addr;
1932 hw_ram_addr = (u32 __force)res->start + pdata->ctrl_ram_offset;
1934 memset(&dma_params, 0, sizeof(dma_params));
1935 dma_params.dev = emac_dev;
1936 dma_params.dmaregs = priv->emac_base;
1937 dma_params.rxthresh = priv->emac_base + 0x120;
1938 dma_params.rxfree = priv->emac_base + 0x140;
1939 dma_params.txhdp = priv->emac_base + 0x600;
1940 dma_params.rxhdp = priv->emac_base + 0x620;
1941 dma_params.txcp = priv->emac_base + 0x640;
1942 dma_params.rxcp = priv->emac_base + 0x660;
1943 dma_params.num_chan = EMAC_MAX_TXRX_CHANNELS;
1944 dma_params.min_packet_size = EMAC_DEF_MIN_ETHPKTSIZE;
1945 dma_params.desc_hw_addr = hw_ram_addr;
1946 dma_params.desc_mem_size = pdata->ctrl_ram_size;
1947 dma_params.desc_align = 16;
1949 dma_params.desc_mem_phys = pdata->no_bd_ram ? 0 :
1950 (u32 __force)res->start + pdata->ctrl_ram_offset;
1952 priv->dma = cpdma_ctlr_create(&dma_params);
1954 dev_err(&pdev->dev, "error initializing DMA\n");
1959 priv->txchan = cpdma_chan_create(priv->dma, tx_chan_num(EMAC_DEF_TX_CH),
1961 priv->rxchan = cpdma_chan_create(priv->dma, rx_chan_num(EMAC_DEF_RX_CH),
1963 if (WARN_ON(!priv->txchan || !priv->rxchan)) {
1968 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1970 dev_err(&pdev->dev, "error getting irq res\n");
1974 ndev->irq = res->start;
1976 if (!is_valid_ether_addr(priv->mac_addr)) {
1977 /* Use random MAC if none passed */
1978 eth_hw_addr_random(ndev);
1979 memcpy(priv->mac_addr, ndev->dev_addr, ndev->addr_len);
1980 dev_warn(&pdev->dev, "using random MAC addr: %pM\n",
1984 ndev->netdev_ops = &emac_netdev_ops;
1985 SET_ETHTOOL_OPS(ndev, ðtool_ops);
1986 netif_napi_add(ndev, &priv->napi, emac_poll, EMAC_POLL_WEIGHT);
1988 clk_enable(emac_clk);
1990 /* register the network device */
1991 SET_NETDEV_DEV(ndev, &pdev->dev);
1992 rc = register_netdev(ndev);
1994 dev_err(&pdev->dev, "error in register_netdev\n");
1996 goto netdev_reg_err;
2000 if (netif_msg_probe(priv)) {
2001 dev_notice(emac_dev, "DaVinci EMAC Probe found device "\
2002 "(regs: %p, irq: %d)\n",
2003 (void *)priv->emac_base_phys, ndev->irq);
2008 clk_disable(emac_clk);
2011 cpdma_chan_destroy(priv->txchan);
2013 cpdma_chan_destroy(priv->rxchan);
2014 cpdma_ctlr_destroy(priv->dma);
2016 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2017 release_mem_region(res->start, resource_size(res));
2018 iounmap(priv->remap_addr);
2028 * davinci_emac_remove - EMAC device remove
2029 * @pdev: The DaVinci EMAC device that we are removing
2031 * Called when removing the device driver. We disable clock usage and release
2032 * the resources taken up by the driver and unregister network device
2034 static int __devexit davinci_emac_remove(struct platform_device *pdev)
2036 struct resource *res;
2037 struct net_device *ndev = platform_get_drvdata(pdev);
2038 struct emac_priv *priv = netdev_priv(ndev);
2040 dev_notice(&ndev->dev, "DaVinci EMAC: davinci_emac_remove()\n");
2042 platform_set_drvdata(pdev, NULL);
2043 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2046 cpdma_chan_destroy(priv->txchan);
2048 cpdma_chan_destroy(priv->rxchan);
2049 cpdma_ctlr_destroy(priv->dma);
2051 release_mem_region(res->start, resource_size(res));
2053 unregister_netdev(ndev);
2054 iounmap(priv->remap_addr);
2057 clk_disable(emac_clk);
2063 static int davinci_emac_suspend(struct device *dev)
2065 struct platform_device *pdev = to_platform_device(dev);
2066 struct net_device *ndev = platform_get_drvdata(pdev);
2068 if (netif_running(ndev))
2069 emac_dev_stop(ndev);
2071 clk_disable(emac_clk);
2076 static int davinci_emac_resume(struct device *dev)
2078 struct platform_device *pdev = to_platform_device(dev);
2079 struct net_device *ndev = platform_get_drvdata(pdev);
2081 clk_enable(emac_clk);
2083 if (netif_running(ndev))
2084 emac_dev_open(ndev);
2089 static const struct dev_pm_ops davinci_emac_pm_ops = {
2090 .suspend = davinci_emac_suspend,
2091 .resume = davinci_emac_resume,
2094 static const struct of_device_id davinci_emac_of_match[] = {
2095 {.compatible = "ti,davinci-dm6467-emac", },
2098 MODULE_DEVICE_TABLE(of, davinci_emac_of_match);
2100 /* davinci_emac_driver: EMAC platform driver structure */
2101 static struct platform_driver davinci_emac_driver = {
2103 .name = "davinci_emac",
2104 .owner = THIS_MODULE,
2105 .pm = &davinci_emac_pm_ops,
2106 .of_match_table = of_match_ptr(davinci_emac_of_match),
2108 .probe = davinci_emac_probe,
2109 .remove = __devexit_p(davinci_emac_remove),
2113 * davinci_emac_init - EMAC driver module init
2115 * Called when initializing the driver. We register the driver with
2118 static int __init davinci_emac_init(void)
2120 return platform_driver_register(&davinci_emac_driver);
2122 late_initcall(davinci_emac_init);
2125 * davinci_emac_exit - EMAC driver module exit
2127 * Called when exiting the driver completely. We unregister the driver with
2128 * the platform and exit
2130 static void __exit davinci_emac_exit(void)
2132 platform_driver_unregister(&davinci_emac_driver);
2134 module_exit(davinci_emac_exit);
2136 MODULE_LICENSE("GPL");
2137 MODULE_AUTHOR("DaVinci EMAC Maintainer: Anant Gole <anantgole@ti.com>");
2138 MODULE_AUTHOR("DaVinci EMAC Maintainer: Chaithrika U S <chaithrika@ti.com>");
2139 MODULE_DESCRIPTION("DaVinci EMAC Ethernet driver");