2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/string.h>
25 #include <linux/ptrace.h>
26 #include <linux/errno.h>
27 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/interrupt.h>
30 #include <linux/pci.h>
31 #include <linux/init.h>
32 #include <linux/delay.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/skbuff.h>
36 #include <linux/spinlock.h>
37 #include <linux/workqueue.h>
38 #include <linux/bitops.h>
41 #include <asm/uaccess.h>
43 #include <asm/pgtable.h>
44 #include <asm/cacheflush.h>
46 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || \
47 defined(CONFIG_M5272) || defined(CONFIG_M528x) || \
48 defined(CONFIG_M520x) || defined(CONFIG_M532x)
49 #include <asm/coldfire.h>
50 #include <asm/mcfsim.h>
53 #include <asm/8xx_immap.h>
54 #include <asm/mpc8xx.h>
58 #if defined(CONFIG_FEC2)
59 #define FEC_MAX_PORTS 2
61 #define FEC_MAX_PORTS 1
64 #if defined(CONFIG_FADS) || defined(CONFIG_RPXCLASSIC) || defined(CONFIG_M5272)
65 #define HAVE_mii_link_interrupt
69 * Define the fixed address of the FEC hardware.
71 static unsigned int fec_hw[] = {
72 #if defined(CONFIG_M5272)
74 #elif defined(CONFIG_M527x)
77 #elif defined(CONFIG_M523x) || defined(CONFIG_M528x)
79 #elif defined(CONFIG_M520x)
81 #elif defined(CONFIG_M532x)
82 (MCF_MBAR+0xfc030000),
84 &(((immap_t *)IMAP_ADDR)->im_cpm.cp_fec),
88 static unsigned char fec_mac_default[] = {
89 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
93 * Some hardware gets it MAC address out of local flash memory.
94 * if this is non-zero then assume it is the address to get MAC from.
96 #if defined(CONFIG_NETtel)
97 #define FEC_FLASHMAC 0xf0006006
98 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
99 #define FEC_FLASHMAC 0xf0006000
100 #elif defined(CONFIG_CANCam)
101 #define FEC_FLASHMAC 0xf0020000
102 #elif defined (CONFIG_M5272C3)
103 #define FEC_FLASHMAC (0xffe04000 + 4)
104 #elif defined(CONFIG_MOD5272)
105 #define FEC_FLASHMAC 0xffc0406b
107 #define FEC_FLASHMAC 0
110 /* Forward declarations of some structures to support different PHYs
115 void (*funct)(uint mii_reg, struct net_device *dev);
122 const phy_cmd_t *config;
123 const phy_cmd_t *startup;
124 const phy_cmd_t *ack_int;
125 const phy_cmd_t *shutdown;
128 /* The number of Tx and Rx buffers. These are allocated from the page
129 * pool. The code may assume these are power of two, so it it best
130 * to keep them that size.
131 * We don't need to allocate pages for the transmitter. We just use
132 * the skbuffer directly.
134 #define FEC_ENET_RX_PAGES 8
135 #define FEC_ENET_RX_FRSIZE 2048
136 #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
137 #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
138 #define FEC_ENET_TX_FRSIZE 2048
139 #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
140 #define TX_RING_SIZE 16 /* Must be power of two */
141 #define TX_RING_MOD_MASK 15 /* for this to work */
143 #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
144 #error "FEC: descriptor ring size constants too large"
147 /* Interrupt events/masks.
149 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
150 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
151 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
152 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
153 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
154 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
155 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
156 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
157 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
158 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
160 /* The FEC stores dest/src/type, data, and checksum for receive packets.
162 #define PKT_MAXBUF_SIZE 1518
163 #define PKT_MINBUF_SIZE 64
164 #define PKT_MAXBLR_SIZE 1520
168 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
169 * size bits. Other FEC hardware does not, so we need to take that into
170 * account when setting it.
172 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
173 defined(CONFIG_M520x) || defined(CONFIG_M532x)
174 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
176 #define OPT_FRAME_SIZE 0
179 /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
180 * tx_bd_base always point to the base of the buffer descriptors. The
181 * cur_rx and cur_tx point to the currently available buffer.
182 * The dirty_tx tracks the current buffer that is being sent by the
183 * controller. The cur_tx and dirty_tx are equal under both completely
184 * empty and completely full conditions. The empty/ready indicator in
185 * the buffer descriptor determines the actual condition.
187 struct fec_enet_private {
188 /* Hardware registers of the FEC device */
191 struct net_device *netdev;
193 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
194 unsigned char *tx_bounce[TX_RING_SIZE];
195 struct sk_buff* tx_skbuff[TX_RING_SIZE];
199 /* CPM dual port RAM relative addresses.
201 cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */
203 cbd_t *cur_rx, *cur_tx; /* The next free ring entry */
204 cbd_t *dirty_tx; /* The ring entries to be free()ed. */
206 /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */
208 /* hold while accessing the mii_list_t() elements */
215 phy_info_t const *phy;
216 struct work_struct phy_task;
219 uint mii_phy_task_queued;
230 static int fec_enet_open(struct net_device *dev);
231 static int fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev);
232 static void fec_enet_mii(struct net_device *dev);
233 static irqreturn_t fec_enet_interrupt(int irq, void * dev_id);
234 static void fec_enet_tx(struct net_device *dev);
235 static void fec_enet_rx(struct net_device *dev);
236 static int fec_enet_close(struct net_device *dev);
237 static void set_multicast_list(struct net_device *dev);
238 static void fec_restart(struct net_device *dev, int duplex);
239 static void fec_stop(struct net_device *dev);
240 static void fec_set_mac_address(struct net_device *dev);
243 /* MII processing. We keep this as simple as possible. Requests are
244 * placed on the list (if there is room). When the request is finished
245 * by the MII, an optional function may be called.
247 typedef struct mii_list {
249 void (*mii_func)(uint val, struct net_device *dev);
250 struct mii_list *mii_next;
254 static mii_list_t mii_cmds[NMII];
255 static mii_list_t *mii_free;
256 static mii_list_t *mii_head;
257 static mii_list_t *mii_tail;
259 static int mii_queue(struct net_device *dev, int request,
260 void (*func)(uint, struct net_device *));
262 /* Make MII read/write commands for the FEC.
264 #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
265 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \
269 /* Transmitter timeout.
271 #define TX_TIMEOUT (2*HZ)
273 /* Register definitions for the PHY.
276 #define MII_REG_CR 0 /* Control Register */
277 #define MII_REG_SR 1 /* Status Register */
278 #define MII_REG_PHYIR1 2 /* PHY Identification Register 1 */
279 #define MII_REG_PHYIR2 3 /* PHY Identification Register 2 */
280 #define MII_REG_ANAR 4 /* A-N Advertisement Register */
281 #define MII_REG_ANLPAR 5 /* A-N Link Partner Ability Register */
282 #define MII_REG_ANER 6 /* A-N Expansion Register */
283 #define MII_REG_ANNPTR 7 /* A-N Next Page Transmit Register */
284 #define MII_REG_ANLPRNPR 8 /* A-N Link Partner Received Next Page Reg. */
286 /* values for phy_status */
288 #define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */
289 #define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */
290 #define PHY_CONF_SPMASK 0x00f0 /* mask for speed */
291 #define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */
292 #define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */
293 #define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */
294 #define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */
296 #define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */
297 #define PHY_STAT_FAULT 0x0200 /* 1 remote fault */
298 #define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */
299 #define PHY_STAT_SPMASK 0xf000 /* mask for speed */
300 #define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */
301 #define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */
302 #define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */
303 #define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */
307 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
309 struct fec_enet_private *fep;
310 volatile fec_t *fecp;
312 unsigned short status;
315 fep = netdev_priv(dev);
316 fecp = (volatile fec_t*)dev->base_addr;
319 /* Link is down or autonegotiation is in progress. */
323 spin_lock_irqsave(&fep->hw_lock, flags);
324 /* Fill in a Tx ring entry */
327 status = bdp->cbd_sc;
328 #ifndef final_version
329 if (status & BD_ENET_TX_READY) {
330 /* Ooops. All transmit buffers are full. Bail out.
331 * This should not happen, since dev->tbusy should be set.
333 printk("%s: tx queue full!.\n", dev->name);
334 spin_unlock_irqrestore(&fep->hw_lock, flags);
339 /* Clear all of the status flags.
341 status &= ~BD_ENET_TX_STATS;
343 /* Set buffer length and buffer pointer.
345 bdp->cbd_bufaddr = __pa(skb->data);
346 bdp->cbd_datlen = skb->len;
349 * On some FEC implementations data must be aligned on
350 * 4-byte boundaries. Use bounce buffers to copy data
351 * and get it aligned. Ugh.
353 if (bdp->cbd_bufaddr & 0x3) {
355 index = bdp - fep->tx_bd_base;
356 memcpy(fep->tx_bounce[index], (void *) bdp->cbd_bufaddr, bdp->cbd_datlen);
357 bdp->cbd_bufaddr = __pa(fep->tx_bounce[index]);
362 fep->tx_skbuff[fep->skb_cur] = skb;
364 dev->stats.tx_bytes += skb->len;
365 fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
367 /* Push the data cache so the CPM does not get stale memory
370 flush_dcache_range((unsigned long)skb->data,
371 (unsigned long)skb->data + skb->len);
373 /* Send it on its way. Tell FEC it's ready, interrupt when done,
374 * it's the last BD of the frame, and to put the CRC on the end.
377 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
378 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
379 bdp->cbd_sc = status;
381 dev->trans_start = jiffies;
383 /* Trigger transmission start */
384 fecp->fec_x_des_active = 0;
386 /* If this was the last BD in the ring, start at the beginning again.
388 if (status & BD_ENET_TX_WRAP) {
389 bdp = fep->tx_bd_base;
394 if (bdp == fep->dirty_tx) {
396 netif_stop_queue(dev);
399 fep->cur_tx = (cbd_t *)bdp;
401 spin_unlock_irqrestore(&fep->hw_lock, flags);
407 fec_timeout(struct net_device *dev)
409 struct fec_enet_private *fep = netdev_priv(dev);
411 printk("%s: transmit timed out.\n", dev->name);
412 dev->stats.tx_errors++;
413 #ifndef final_version
418 printk("Ring data dump: cur_tx %lx%s, dirty_tx %lx cur_rx: %lx\n",
419 (unsigned long)fep->cur_tx, fep->tx_full ? " (full)" : "",
420 (unsigned long)fep->dirty_tx,
421 (unsigned long)fep->cur_rx);
423 bdp = fep->tx_bd_base;
424 printk(" tx: %u buffers\n", TX_RING_SIZE);
425 for (i = 0 ; i < TX_RING_SIZE; i++) {
426 printk(" %08x: %04x %04x %08x\n",
430 (int) bdp->cbd_bufaddr);
434 bdp = fep->rx_bd_base;
435 printk(" rx: %lu buffers\n", (unsigned long) RX_RING_SIZE);
436 for (i = 0 ; i < RX_RING_SIZE; i++) {
437 printk(" %08x: %04x %04x %08x\n",
441 (int) bdp->cbd_bufaddr);
446 fec_restart(dev, fep->full_duplex);
447 netif_wake_queue(dev);
450 /* The interrupt handler.
451 * This is called from the MPC core interrupt.
454 fec_enet_interrupt(int irq, void * dev_id)
456 struct net_device *dev = dev_id;
457 volatile fec_t *fecp;
459 irqreturn_t ret = IRQ_NONE;
461 fecp = (volatile fec_t*)dev->base_addr;
463 /* Get the interrupt events that caused us to be here.
466 int_events = fecp->fec_ievent;
467 fecp->fec_ievent = int_events;
469 /* Handle receive event in its own function.
471 if (int_events & FEC_ENET_RXF) {
476 /* Transmit OK, or non-fatal error. Update the buffer
477 descriptors. FEC handles all errors, we just discover
478 them as part of the transmit process.
480 if (int_events & FEC_ENET_TXF) {
485 if (int_events & FEC_ENET_MII) {
490 } while (int_events);
497 fec_enet_tx(struct net_device *dev)
499 struct fec_enet_private *fep;
501 unsigned short status;
504 fep = netdev_priv(dev);
505 spin_lock_irq(&fep->hw_lock);
508 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
509 if (bdp == fep->cur_tx && fep->tx_full == 0) break;
511 skb = fep->tx_skbuff[fep->skb_dirty];
512 /* Check for errors. */
513 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
514 BD_ENET_TX_RL | BD_ENET_TX_UN |
516 dev->stats.tx_errors++;
517 if (status & BD_ENET_TX_HB) /* No heartbeat */
518 dev->stats.tx_heartbeat_errors++;
519 if (status & BD_ENET_TX_LC) /* Late collision */
520 dev->stats.tx_window_errors++;
521 if (status & BD_ENET_TX_RL) /* Retrans limit */
522 dev->stats.tx_aborted_errors++;
523 if (status & BD_ENET_TX_UN) /* Underrun */
524 dev->stats.tx_fifo_errors++;
525 if (status & BD_ENET_TX_CSL) /* Carrier lost */
526 dev->stats.tx_carrier_errors++;
528 dev->stats.tx_packets++;
531 #ifndef final_version
532 if (status & BD_ENET_TX_READY)
533 printk("HEY! Enet xmit interrupt and TX_READY.\n");
535 /* Deferred means some collisions occurred during transmit,
536 * but we eventually sent the packet OK.
538 if (status & BD_ENET_TX_DEF)
539 dev->stats.collisions++;
541 /* Free the sk buffer associated with this last transmit.
543 dev_kfree_skb_any(skb);
544 fep->tx_skbuff[fep->skb_dirty] = NULL;
545 fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
547 /* Update pointer to next buffer descriptor to be transmitted.
549 if (status & BD_ENET_TX_WRAP)
550 bdp = fep->tx_bd_base;
554 /* Since we have freed up a buffer, the ring is no longer
559 if (netif_queue_stopped(dev))
560 netif_wake_queue(dev);
563 fep->dirty_tx = (cbd_t *)bdp;
564 spin_unlock_irq(&fep->hw_lock);
568 /* During a receive, the cur_rx points to the current incoming buffer.
569 * When we update through the ring, if the next incoming buffer has
570 * not been given to the system, we just set the empty indicator,
571 * effectively tossing the packet.
574 fec_enet_rx(struct net_device *dev)
576 struct fec_enet_private *fep;
577 volatile fec_t *fecp;
579 unsigned short status;
588 fep = netdev_priv(dev);
589 fecp = (volatile fec_t*)dev->base_addr;
591 spin_lock_irq(&fep->hw_lock);
593 /* First, grab all of the stats for the incoming packet.
594 * These get messed up if we get called due to a busy condition.
598 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
600 #ifndef final_version
601 /* Since we have allocated space to hold a complete frame,
602 * the last indicator should be set.
604 if ((status & BD_ENET_RX_LAST) == 0)
605 printk("FEC ENET: rcv is not +last\n");
609 goto rx_processing_done;
611 /* Check for errors. */
612 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
613 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
614 dev->stats.rx_errors++;
615 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
616 /* Frame too long or too short. */
617 dev->stats.rx_length_errors++;
619 if (status & BD_ENET_RX_NO) /* Frame alignment */
620 dev->stats.rx_frame_errors++;
621 if (status & BD_ENET_RX_CR) /* CRC Error */
622 dev->stats.rx_crc_errors++;
623 if (status & BD_ENET_RX_OV) /* FIFO overrun */
624 dev->stats.rx_fifo_errors++;
627 /* Report late collisions as a frame error.
628 * On this error, the BD is closed, but we don't know what we
629 * have in the buffer. So, just drop this frame on the floor.
631 if (status & BD_ENET_RX_CL) {
632 dev->stats.rx_errors++;
633 dev->stats.rx_frame_errors++;
634 goto rx_processing_done;
637 /* Process the incoming frame.
639 dev->stats.rx_packets++;
640 pkt_len = bdp->cbd_datlen;
641 dev->stats.rx_bytes += pkt_len;
642 data = (__u8*)__va(bdp->cbd_bufaddr);
644 /* This does 16 byte alignment, exactly what we need.
645 * The packet length includes FCS, but we don't want to
646 * include that when passing upstream as it messes up
647 * bridging applications.
649 skb = dev_alloc_skb(pkt_len-4);
652 printk("%s: Memory squeeze, dropping packet.\n", dev->name);
653 dev->stats.rx_dropped++;
655 skb_put(skb,pkt_len-4); /* Make room */
656 skb_copy_to_linear_data(skb, data, pkt_len-4);
657 skb->protocol=eth_type_trans(skb,dev);
662 /* Clear the status flags for this buffer.
664 status &= ~BD_ENET_RX_STATS;
666 /* Mark the buffer empty.
668 status |= BD_ENET_RX_EMPTY;
669 bdp->cbd_sc = status;
671 /* Update BD pointer to next entry.
673 if (status & BD_ENET_RX_WRAP)
674 bdp = fep->rx_bd_base;
679 /* Doing this here will keep the FEC running while we process
680 * incoming frames. On a heavily loaded network, we should be
681 * able to keep up at the expense of system resources.
683 fecp->fec_r_des_active = 0;
685 } /* while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) */
686 fep->cur_rx = (cbd_t *)bdp;
689 /* Doing this here will allow us to process all frames in the
690 * ring before the FEC is allowed to put more there. On a heavily
691 * loaded network, some frames may be lost. Unfortunately, this
692 * increases the interrupt overhead since we can potentially work
693 * our way back to the interrupt return only to come right back
696 fecp->fec_r_des_active = 0;
699 spin_unlock_irq(&fep->hw_lock);
703 /* called from interrupt context */
705 fec_enet_mii(struct net_device *dev)
707 struct fec_enet_private *fep;
712 fep = netdev_priv(dev);
713 spin_lock_irq(&fep->mii_lock);
716 mii_reg = ep->fec_mii_data;
718 if ((mip = mii_head) == NULL) {
719 printk("MII and no head!\n");
723 if (mip->mii_func != NULL)
724 (*(mip->mii_func))(mii_reg, dev);
726 mii_head = mip->mii_next;
727 mip->mii_next = mii_free;
730 if ((mip = mii_head) != NULL)
731 ep->fec_mii_data = mip->mii_regval;
734 spin_unlock_irq(&fep->mii_lock);
738 mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_device *))
740 struct fec_enet_private *fep;
745 /* Add PHY address to register command.
747 fep = netdev_priv(dev);
748 spin_lock_irqsave(&fep->mii_lock, flags);
750 regval |= fep->phy_addr << 23;
753 if ((mip = mii_free) != NULL) {
754 mii_free = mip->mii_next;
755 mip->mii_regval = regval;
756 mip->mii_func = func;
757 mip->mii_next = NULL;
759 mii_tail->mii_next = mip;
762 mii_head = mii_tail = mip;
763 fep->hwp->fec_mii_data = regval;
769 spin_unlock_irqrestore(&fep->mii_lock, flags);
773 static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c)
778 for (; c->mii_data != mk_mii_end; c++)
779 mii_queue(dev, c->mii_data, c->funct);
782 static void mii_parse_sr(uint mii_reg, struct net_device *dev)
784 struct fec_enet_private *fep = netdev_priv(dev);
785 volatile uint *s = &(fep->phy_status);
788 status = *s & ~(PHY_STAT_LINK | PHY_STAT_FAULT | PHY_STAT_ANC);
790 if (mii_reg & 0x0004)
791 status |= PHY_STAT_LINK;
792 if (mii_reg & 0x0010)
793 status |= PHY_STAT_FAULT;
794 if (mii_reg & 0x0020)
795 status |= PHY_STAT_ANC;
799 static void mii_parse_cr(uint mii_reg, struct net_device *dev)
801 struct fec_enet_private *fep = netdev_priv(dev);
802 volatile uint *s = &(fep->phy_status);
805 status = *s & ~(PHY_CONF_ANE | PHY_CONF_LOOP);
807 if (mii_reg & 0x1000)
808 status |= PHY_CONF_ANE;
809 if (mii_reg & 0x4000)
810 status |= PHY_CONF_LOOP;
814 static void mii_parse_anar(uint mii_reg, struct net_device *dev)
816 struct fec_enet_private *fep = netdev_priv(dev);
817 volatile uint *s = &(fep->phy_status);
820 status = *s & ~(PHY_CONF_SPMASK);
822 if (mii_reg & 0x0020)
823 status |= PHY_CONF_10HDX;
824 if (mii_reg & 0x0040)
825 status |= PHY_CONF_10FDX;
826 if (mii_reg & 0x0080)
827 status |= PHY_CONF_100HDX;
828 if (mii_reg & 0x00100)
829 status |= PHY_CONF_100FDX;
833 /* ------------------------------------------------------------------------- */
834 /* The Level one LXT970 is used by many boards */
836 #define MII_LXT970_MIRROR 16 /* Mirror register */
837 #define MII_LXT970_IER 17 /* Interrupt Enable Register */
838 #define MII_LXT970_ISR 18 /* Interrupt Status Register */
839 #define MII_LXT970_CONFIG 19 /* Configuration Register */
840 #define MII_LXT970_CSR 20 /* Chip Status Register */
842 static void mii_parse_lxt970_csr(uint mii_reg, struct net_device *dev)
844 struct fec_enet_private *fep = netdev_priv(dev);
845 volatile uint *s = &(fep->phy_status);
848 status = *s & ~(PHY_STAT_SPMASK);
849 if (mii_reg & 0x0800) {
850 if (mii_reg & 0x1000)
851 status |= PHY_STAT_100FDX;
853 status |= PHY_STAT_100HDX;
855 if (mii_reg & 0x1000)
856 status |= PHY_STAT_10FDX;
858 status |= PHY_STAT_10HDX;
863 static phy_cmd_t const phy_cmd_lxt970_config[] = {
864 { mk_mii_read(MII_REG_CR), mii_parse_cr },
865 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
868 static phy_cmd_t const phy_cmd_lxt970_startup[] = { /* enable interrupts */
869 { mk_mii_write(MII_LXT970_IER, 0x0002), NULL },
870 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
873 static phy_cmd_t const phy_cmd_lxt970_ack_int[] = {
874 /* read SR and ISR to acknowledge */
875 { mk_mii_read(MII_REG_SR), mii_parse_sr },
876 { mk_mii_read(MII_LXT970_ISR), NULL },
878 /* find out the current status */
879 { mk_mii_read(MII_LXT970_CSR), mii_parse_lxt970_csr },
882 static phy_cmd_t const phy_cmd_lxt970_shutdown[] = { /* disable interrupts */
883 { mk_mii_write(MII_LXT970_IER, 0x0000), NULL },
886 static phy_info_t const phy_info_lxt970 = {
889 .config = phy_cmd_lxt970_config,
890 .startup = phy_cmd_lxt970_startup,
891 .ack_int = phy_cmd_lxt970_ack_int,
892 .shutdown = phy_cmd_lxt970_shutdown
895 /* ------------------------------------------------------------------------- */
896 /* The Level one LXT971 is used on some of my custom boards */
898 /* register definitions for the 971 */
900 #define MII_LXT971_PCR 16 /* Port Control Register */
901 #define MII_LXT971_SR2 17 /* Status Register 2 */
902 #define MII_LXT971_IER 18 /* Interrupt Enable Register */
903 #define MII_LXT971_ISR 19 /* Interrupt Status Register */
904 #define MII_LXT971_LCR 20 /* LED Control Register */
905 #define MII_LXT971_TCR 30 /* Transmit Control Register */
908 * I had some nice ideas of running the MDIO faster...
909 * The 971 should support 8MHz and I tried it, but things acted really
910 * weird, so 2.5 MHz ought to be enough for anyone...
913 static void mii_parse_lxt971_sr2(uint mii_reg, struct net_device *dev)
915 struct fec_enet_private *fep = netdev_priv(dev);
916 volatile uint *s = &(fep->phy_status);
919 status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC);
921 if (mii_reg & 0x0400) {
923 status |= PHY_STAT_LINK;
927 if (mii_reg & 0x0080)
928 status |= PHY_STAT_ANC;
929 if (mii_reg & 0x4000) {
930 if (mii_reg & 0x0200)
931 status |= PHY_STAT_100FDX;
933 status |= PHY_STAT_100HDX;
935 if (mii_reg & 0x0200)
936 status |= PHY_STAT_10FDX;
938 status |= PHY_STAT_10HDX;
940 if (mii_reg & 0x0008)
941 status |= PHY_STAT_FAULT;
946 static phy_cmd_t const phy_cmd_lxt971_config[] = {
947 /* limit to 10MBit because my prototype board
948 * doesn't work with 100. */
949 { mk_mii_read(MII_REG_CR), mii_parse_cr },
950 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
951 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
954 static phy_cmd_t const phy_cmd_lxt971_startup[] = { /* enable interrupts */
955 { mk_mii_write(MII_LXT971_IER, 0x00f2), NULL },
956 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
957 { mk_mii_write(MII_LXT971_LCR, 0xd422), NULL }, /* LED config */
958 /* Somehow does the 971 tell me that the link is down
959 * the first read after power-up.
960 * read here to get a valid value in ack_int */
961 { mk_mii_read(MII_REG_SR), mii_parse_sr },
964 static phy_cmd_t const phy_cmd_lxt971_ack_int[] = {
965 /* acknowledge the int before reading status ! */
966 { mk_mii_read(MII_LXT971_ISR), NULL },
967 /* find out the current status */
968 { mk_mii_read(MII_REG_SR), mii_parse_sr },
969 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
972 static phy_cmd_t const phy_cmd_lxt971_shutdown[] = { /* disable interrupts */
973 { mk_mii_write(MII_LXT971_IER, 0x0000), NULL },
976 static phy_info_t const phy_info_lxt971 = {
979 .config = phy_cmd_lxt971_config,
980 .startup = phy_cmd_lxt971_startup,
981 .ack_int = phy_cmd_lxt971_ack_int,
982 .shutdown = phy_cmd_lxt971_shutdown
985 /* ------------------------------------------------------------------------- */
986 /* The Quality Semiconductor QS6612 is used on the RPX CLLF */
988 /* register definitions */
990 #define MII_QS6612_MCR 17 /* Mode Control Register */
991 #define MII_QS6612_FTR 27 /* Factory Test Register */
992 #define MII_QS6612_MCO 28 /* Misc. Control Register */
993 #define MII_QS6612_ISR 29 /* Interrupt Source Register */
994 #define MII_QS6612_IMR 30 /* Interrupt Mask Register */
995 #define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */
997 static void mii_parse_qs6612_pcr(uint mii_reg, struct net_device *dev)
999 struct fec_enet_private *fep = netdev_priv(dev);
1000 volatile uint *s = &(fep->phy_status);
1003 status = *s & ~(PHY_STAT_SPMASK);
1005 switch((mii_reg >> 2) & 7) {
1006 case 1: status |= PHY_STAT_10HDX; break;
1007 case 2: status |= PHY_STAT_100HDX; break;
1008 case 5: status |= PHY_STAT_10FDX; break;
1009 case 6: status |= PHY_STAT_100FDX; break;
1015 static phy_cmd_t const phy_cmd_qs6612_config[] = {
1016 /* The PHY powers up isolated on the RPX,
1017 * so send a command to allow operation.
1019 { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL },
1021 /* parse cr and anar to get some info */
1022 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1023 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1026 static phy_cmd_t const phy_cmd_qs6612_startup[] = { /* enable interrupts */
1027 { mk_mii_write(MII_QS6612_IMR, 0x003a), NULL },
1028 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1031 static phy_cmd_t const phy_cmd_qs6612_ack_int[] = {
1032 /* we need to read ISR, SR and ANER to acknowledge */
1033 { mk_mii_read(MII_QS6612_ISR), NULL },
1034 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1035 { mk_mii_read(MII_REG_ANER), NULL },
1037 /* read pcr to get info */
1038 { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr },
1041 static phy_cmd_t const phy_cmd_qs6612_shutdown[] = { /* disable interrupts */
1042 { mk_mii_write(MII_QS6612_IMR, 0x0000), NULL },
1045 static phy_info_t const phy_info_qs6612 = {
1048 .config = phy_cmd_qs6612_config,
1049 .startup = phy_cmd_qs6612_startup,
1050 .ack_int = phy_cmd_qs6612_ack_int,
1051 .shutdown = phy_cmd_qs6612_shutdown
1054 /* ------------------------------------------------------------------------- */
1055 /* AMD AM79C874 phy */
1057 /* register definitions for the 874 */
1059 #define MII_AM79C874_MFR 16 /* Miscellaneous Feature Register */
1060 #define MII_AM79C874_ICSR 17 /* Interrupt/Status Register */
1061 #define MII_AM79C874_DR 18 /* Diagnostic Register */
1062 #define MII_AM79C874_PMLR 19 /* Power and Loopback Register */
1063 #define MII_AM79C874_MCR 21 /* ModeControl Register */
1064 #define MII_AM79C874_DC 23 /* Disconnect Counter */
1065 #define MII_AM79C874_REC 24 /* Recieve Error Counter */
1067 static void mii_parse_am79c874_dr(uint mii_reg, struct net_device *dev)
1069 struct fec_enet_private *fep = netdev_priv(dev);
1070 volatile uint *s = &(fep->phy_status);
1073 status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_ANC);
1075 if (mii_reg & 0x0080)
1076 status |= PHY_STAT_ANC;
1077 if (mii_reg & 0x0400)
1078 status |= ((mii_reg & 0x0800) ? PHY_STAT_100FDX : PHY_STAT_100HDX);
1080 status |= ((mii_reg & 0x0800) ? PHY_STAT_10FDX : PHY_STAT_10HDX);
1085 static phy_cmd_t const phy_cmd_am79c874_config[] = {
1086 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1087 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1088 { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr },
1091 static phy_cmd_t const phy_cmd_am79c874_startup[] = { /* enable interrupts */
1092 { mk_mii_write(MII_AM79C874_ICSR, 0xff00), NULL },
1093 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1094 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1097 static phy_cmd_t const phy_cmd_am79c874_ack_int[] = {
1098 /* find out the current status */
1099 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1100 { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr },
1101 /* we only need to read ISR to acknowledge */
1102 { mk_mii_read(MII_AM79C874_ICSR), NULL },
1105 static phy_cmd_t const phy_cmd_am79c874_shutdown[] = { /* disable interrupts */
1106 { mk_mii_write(MII_AM79C874_ICSR, 0x0000), NULL },
1109 static phy_info_t const phy_info_am79c874 = {
1112 .config = phy_cmd_am79c874_config,
1113 .startup = phy_cmd_am79c874_startup,
1114 .ack_int = phy_cmd_am79c874_ack_int,
1115 .shutdown = phy_cmd_am79c874_shutdown
1119 /* ------------------------------------------------------------------------- */
1120 /* Kendin KS8721BL phy */
1122 /* register definitions for the 8721 */
1124 #define MII_KS8721BL_RXERCR 21
1125 #define MII_KS8721BL_ICSR 22
1126 #define MII_KS8721BL_PHYCR 31
1128 static phy_cmd_t const phy_cmd_ks8721bl_config[] = {
1129 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1130 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1133 static phy_cmd_t const phy_cmd_ks8721bl_startup[] = { /* enable interrupts */
1134 { mk_mii_write(MII_KS8721BL_ICSR, 0xff00), NULL },
1135 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1136 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1139 static phy_cmd_t const phy_cmd_ks8721bl_ack_int[] = {
1140 /* find out the current status */
1141 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1142 /* we only need to read ISR to acknowledge */
1143 { mk_mii_read(MII_KS8721BL_ICSR), NULL },
1146 static phy_cmd_t const phy_cmd_ks8721bl_shutdown[] = { /* disable interrupts */
1147 { mk_mii_write(MII_KS8721BL_ICSR, 0x0000), NULL },
1150 static phy_info_t const phy_info_ks8721bl = {
1153 .config = phy_cmd_ks8721bl_config,
1154 .startup = phy_cmd_ks8721bl_startup,
1155 .ack_int = phy_cmd_ks8721bl_ack_int,
1156 .shutdown = phy_cmd_ks8721bl_shutdown
1159 /* ------------------------------------------------------------------------- */
1160 /* register definitions for the DP83848 */
1162 #define MII_DP8384X_PHYSTST 16 /* PHY Status Register */
1164 static void mii_parse_dp8384x_sr2(uint mii_reg, struct net_device *dev)
1166 struct fec_enet_private *fep = dev->priv;
1167 volatile uint *s = &(fep->phy_status);
1169 *s &= ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC);
1172 if (mii_reg & 0x0001) {
1174 *s |= PHY_STAT_LINK;
1177 /* Status of link */
1178 if (mii_reg & 0x0010) /* Autonegotioation complete */
1180 if (mii_reg & 0x0002) { /* 10MBps? */
1181 if (mii_reg & 0x0004) /* Full Duplex? */
1182 *s |= PHY_STAT_10FDX;
1184 *s |= PHY_STAT_10HDX;
1185 } else { /* 100 Mbps? */
1186 if (mii_reg & 0x0004) /* Full Duplex? */
1187 *s |= PHY_STAT_100FDX;
1189 *s |= PHY_STAT_100HDX;
1191 if (mii_reg & 0x0008)
1192 *s |= PHY_STAT_FAULT;
1195 static phy_info_t phy_info_dp83848= {
1199 (const phy_cmd_t []) { /* config */
1200 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1201 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1202 { mk_mii_read(MII_DP8384X_PHYSTST), mii_parse_dp8384x_sr2 },
1205 (const phy_cmd_t []) { /* startup - enable interrupts */
1206 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1207 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1210 (const phy_cmd_t []) { /* ack_int - never happens, no interrupt */
1213 (const phy_cmd_t []) { /* shutdown */
1218 /* ------------------------------------------------------------------------- */
1220 static phy_info_t const * const phy_info[] = {
1230 /* ------------------------------------------------------------------------- */
1231 #ifdef HAVE_mii_link_interrupt
1232 #ifdef CONFIG_RPXCLASSIC
1234 mii_link_interrupt(void *dev_id);
1237 mii_link_interrupt(int irq, void * dev_id);
1241 #if defined(CONFIG_M5272)
1243 * Code specific to Coldfire 5272 setup.
1245 static void __inline__ fec_request_intrs(struct net_device *dev)
1247 volatile unsigned long *icrp;
1248 static const struct idesc {
1251 irq_handler_t handler;
1253 { "fec(RX)", 86, fec_enet_interrupt },
1254 { "fec(TX)", 87, fec_enet_interrupt },
1255 { "fec(OTHER)", 88, fec_enet_interrupt },
1256 { "fec(MII)", 66, mii_link_interrupt },
1260 /* Setup interrupt handlers. */
1261 for (idp = id; idp->name; idp++) {
1262 if (request_irq(idp->irq, idp->handler, IRQF_DISABLED, idp->name, dev) != 0)
1263 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, idp->irq);
1266 /* Unmask interrupt at ColdFire 5272 SIM */
1267 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR3);
1269 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1273 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1275 volatile fec_t *fecp;
1278 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1279 fecp->fec_x_cntrl = 0x00;
1282 * Set MII speed to 2.5 MHz
1283 * See 5272 manual section 11.5.8: MSCR
1285 fep->phy_speed = ((((MCF_CLK / 4) / (2500000 / 10)) + 5) / 10) * 2;
1286 fecp->fec_mii_speed = fep->phy_speed;
1288 fec_restart(dev, 0);
1291 static void __inline__ fec_get_mac(struct net_device *dev)
1293 struct fec_enet_private *fep = netdev_priv(dev);
1294 volatile fec_t *fecp;
1295 unsigned char *iap, tmpaddr[ETH_ALEN];
1301 * Get MAC address from FLASH.
1302 * If it is all 1's or 0's, use the default.
1304 iap = (unsigned char *)FEC_FLASHMAC;
1305 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1306 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1307 iap = fec_mac_default;
1308 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1309 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1310 iap = fec_mac_default;
1312 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1313 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1317 memcpy(dev->dev_addr, iap, ETH_ALEN);
1319 /* Adjust MAC if using default MAC address */
1320 if (iap == fec_mac_default)
1321 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1324 static void __inline__ fec_enable_phy_intr(void)
1328 static void __inline__ fec_disable_phy_intr(void)
1330 volatile unsigned long *icrp;
1331 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1335 static void __inline__ fec_phy_ack_intr(void)
1337 volatile unsigned long *icrp;
1338 /* Acknowledge the interrupt */
1339 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1343 static void __inline__ fec_localhw_setup(void)
1348 * Do not need to make region uncached on 5272.
1350 static void __inline__ fec_uncache(unsigned long addr)
1354 /* ------------------------------------------------------------------------- */
1356 #elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
1359 * Code specific to Coldfire 5230/5231/5232/5234/5235,
1360 * the 5270/5271/5274/5275 and 5280/5282 setups.
1362 static void __inline__ fec_request_intrs(struct net_device *dev)
1364 struct fec_enet_private *fep;
1366 static const struct idesc {
1376 fep = netdev_priv(dev);
1377 b = (fep->index) ? 128 : 64;
1379 /* Setup interrupt handlers. */
1380 for (idp = id; idp->name; idp++) {
1381 if (request_irq(b+idp->irq, fec_enet_interrupt, IRQF_DISABLED, idp->name, dev) != 0)
1382 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq);
1385 /* Unmask interrupts at ColdFire 5280/5282 interrupt controller */
1387 volatile unsigned char *icrp;
1388 volatile unsigned long *imrp;
1391 b = (fep->index) ? MCFICM_INTC1 : MCFICM_INTC0;
1392 icrp = (volatile unsigned char *) (MCF_IPSBAR + b +
1394 for (i = 23, ilip = 0x28; (i < 36); i++)
1397 imrp = (volatile unsigned long *) (MCF_IPSBAR + b +
1399 *imrp &= ~0x0000000f;
1400 imrp = (volatile unsigned long *) (MCF_IPSBAR + b +
1402 *imrp &= ~0xff800001;
1405 #if defined(CONFIG_M528x)
1406 /* Set up gpio outputs for MII lines */
1408 volatile u16 *gpio_paspar;
1409 volatile u8 *gpio_pehlpar;
1411 gpio_paspar = (volatile u16 *) (MCF_IPSBAR + 0x100056);
1412 gpio_pehlpar = (volatile u16 *) (MCF_IPSBAR + 0x100058);
1413 *gpio_paspar |= 0x0f00;
1414 *gpio_pehlpar = 0xc0;
1418 #if defined(CONFIG_M527x)
1419 /* Set up gpio outputs for MII lines */
1421 volatile u8 *gpio_par_fec;
1422 volatile u16 *gpio_par_feci2c;
1424 gpio_par_feci2c = (volatile u16 *)(MCF_IPSBAR + 0x100082);
1425 /* Set up gpio outputs for FEC0 MII lines */
1426 gpio_par_fec = (volatile u8 *)(MCF_IPSBAR + 0x100078);
1428 *gpio_par_feci2c |= 0x0f00;
1429 *gpio_par_fec |= 0xc0;
1431 #if defined(CONFIG_FEC2)
1432 /* Set up gpio outputs for FEC1 MII lines */
1433 gpio_par_fec = (volatile u8 *)(MCF_IPSBAR + 0x100079);
1435 *gpio_par_feci2c |= 0x00a0;
1436 *gpio_par_fec |= 0xc0;
1437 #endif /* CONFIG_FEC2 */
1439 #endif /* CONFIG_M527x */
1442 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1444 volatile fec_t *fecp;
1447 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1448 fecp->fec_x_cntrl = 0x00;
1451 * Set MII speed to 2.5 MHz
1452 * See 5282 manual section 17.5.4.7: MSCR
1454 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
1455 fecp->fec_mii_speed = fep->phy_speed;
1457 fec_restart(dev, 0);
1460 static void __inline__ fec_get_mac(struct net_device *dev)
1462 struct fec_enet_private *fep = netdev_priv(dev);
1463 volatile fec_t *fecp;
1464 unsigned char *iap, tmpaddr[ETH_ALEN];
1470 * Get MAC address from FLASH.
1471 * If it is all 1's or 0's, use the default.
1474 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1475 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1476 iap = fec_mac_default;
1477 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1478 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1479 iap = fec_mac_default;
1481 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1482 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1486 memcpy(dev->dev_addr, iap, ETH_ALEN);
1488 /* Adjust MAC if using default MAC address */
1489 if (iap == fec_mac_default)
1490 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1493 static void __inline__ fec_enable_phy_intr(void)
1497 static void __inline__ fec_disable_phy_intr(void)
1501 static void __inline__ fec_phy_ack_intr(void)
1505 static void __inline__ fec_localhw_setup(void)
1510 * Do not need to make region uncached on 5272.
1512 static void __inline__ fec_uncache(unsigned long addr)
1516 /* ------------------------------------------------------------------------- */
1518 #elif defined(CONFIG_M520x)
1521 * Code specific to Coldfire 520x
1523 static void __inline__ fec_request_intrs(struct net_device *dev)
1525 struct fec_enet_private *fep;
1527 static const struct idesc {
1537 fep = netdev_priv(dev);
1540 /* Setup interrupt handlers. */
1541 for (idp = id; idp->name; idp++) {
1542 if (request_irq(b+idp->irq, fec_enet_interrupt, IRQF_DISABLED, idp->name,dev) != 0)
1543 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq);
1546 /* Unmask interrupts at ColdFire interrupt controller */
1548 volatile unsigned char *icrp;
1549 volatile unsigned long *imrp;
1551 icrp = (volatile unsigned char *) (MCF_IPSBAR + MCFICM_INTC0 +
1553 for (b = 36; (b < 49); b++)
1555 imrp = (volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 +
1557 *imrp &= ~0x0001FFF0;
1559 *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FEC) |= 0xf0;
1560 *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FECI2C) |= 0x0f;
1563 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1565 volatile fec_t *fecp;
1568 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1569 fecp->fec_x_cntrl = 0x00;
1572 * Set MII speed to 2.5 MHz
1573 * See 5282 manual section 17.5.4.7: MSCR
1575 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
1576 fecp->fec_mii_speed = fep->phy_speed;
1578 fec_restart(dev, 0);
1581 static void __inline__ fec_get_mac(struct net_device *dev)
1583 struct fec_enet_private *fep = netdev_priv(dev);
1584 volatile fec_t *fecp;
1585 unsigned char *iap, tmpaddr[ETH_ALEN];
1591 * Get MAC address from FLASH.
1592 * If it is all 1's or 0's, use the default.
1595 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1596 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1597 iap = fec_mac_default;
1598 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1599 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1600 iap = fec_mac_default;
1602 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1603 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1607 memcpy(dev->dev_addr, iap, ETH_ALEN);
1609 /* Adjust MAC if using default MAC address */
1610 if (iap == fec_mac_default)
1611 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1614 static void __inline__ fec_enable_phy_intr(void)
1618 static void __inline__ fec_disable_phy_intr(void)
1622 static void __inline__ fec_phy_ack_intr(void)
1626 static void __inline__ fec_localhw_setup(void)
1630 static void __inline__ fec_uncache(unsigned long addr)
1634 /* ------------------------------------------------------------------------- */
1636 #elif defined(CONFIG_M532x)
1638 * Code specific for M532x
1640 static void __inline__ fec_request_intrs(struct net_device *dev)
1642 struct fec_enet_private *fep;
1644 static const struct idesc {
1654 fep = netdev_priv(dev);
1655 b = (fep->index) ? 128 : 64;
1657 /* Setup interrupt handlers. */
1658 for (idp = id; idp->name; idp++) {
1659 if (request_irq(b+idp->irq, fec_enet_interrupt, IRQF_DISABLED, idp->name,dev) != 0)
1660 printk("FEC: Could not allocate %s IRQ(%d)!\n",
1661 idp->name, b+idp->irq);
1664 /* Unmask interrupts */
1665 MCF_INTC0_ICR36 = 0x2;
1666 MCF_INTC0_ICR37 = 0x2;
1667 MCF_INTC0_ICR38 = 0x2;
1668 MCF_INTC0_ICR39 = 0x2;
1669 MCF_INTC0_ICR40 = 0x2;
1670 MCF_INTC0_ICR41 = 0x2;
1671 MCF_INTC0_ICR42 = 0x2;
1672 MCF_INTC0_ICR43 = 0x2;
1673 MCF_INTC0_ICR44 = 0x2;
1674 MCF_INTC0_ICR45 = 0x2;
1675 MCF_INTC0_ICR46 = 0x2;
1676 MCF_INTC0_ICR47 = 0x2;
1677 MCF_INTC0_ICR48 = 0x2;
1679 MCF_INTC0_IMRH &= ~(
1680 MCF_INTC_IMRH_INT_MASK36 |
1681 MCF_INTC_IMRH_INT_MASK37 |
1682 MCF_INTC_IMRH_INT_MASK38 |
1683 MCF_INTC_IMRH_INT_MASK39 |
1684 MCF_INTC_IMRH_INT_MASK40 |
1685 MCF_INTC_IMRH_INT_MASK41 |
1686 MCF_INTC_IMRH_INT_MASK42 |
1687 MCF_INTC_IMRH_INT_MASK43 |
1688 MCF_INTC_IMRH_INT_MASK44 |
1689 MCF_INTC_IMRH_INT_MASK45 |
1690 MCF_INTC_IMRH_INT_MASK46 |
1691 MCF_INTC_IMRH_INT_MASK47 |
1692 MCF_INTC_IMRH_INT_MASK48 );
1694 /* Set up gpio outputs for MII lines */
1695 MCF_GPIO_PAR_FECI2C |= (0 |
1696 MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC |
1697 MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO);
1698 MCF_GPIO_PAR_FEC = (0 |
1699 MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC |
1700 MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC);
1703 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1705 volatile fec_t *fecp;
1708 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1709 fecp->fec_x_cntrl = 0x00;
1712 * Set MII speed to 2.5 MHz
1714 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
1715 fecp->fec_mii_speed = fep->phy_speed;
1717 fec_restart(dev, 0);
1720 static void __inline__ fec_get_mac(struct net_device *dev)
1722 struct fec_enet_private *fep = netdev_priv(dev);
1723 volatile fec_t *fecp;
1724 unsigned char *iap, tmpaddr[ETH_ALEN];
1730 * Get MAC address from FLASH.
1731 * If it is all 1's or 0's, use the default.
1734 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1735 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1736 iap = fec_mac_default;
1737 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1738 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1739 iap = fec_mac_default;
1741 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1742 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1746 memcpy(dev->dev_addr, iap, ETH_ALEN);
1748 /* Adjust MAC if using default MAC address */
1749 if (iap == fec_mac_default)
1750 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1753 static void __inline__ fec_enable_phy_intr(void)
1757 static void __inline__ fec_disable_phy_intr(void)
1761 static void __inline__ fec_phy_ack_intr(void)
1765 static void __inline__ fec_localhw_setup(void)
1770 * Do not need to make region uncached on 532x.
1772 static void __inline__ fec_uncache(unsigned long addr)
1776 /* ------------------------------------------------------------------------- */
1782 * Code specific to the MPC860T setup.
1784 static void __inline__ fec_request_intrs(struct net_device *dev)
1786 volatile immap_t *immap;
1788 immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */
1790 if (request_8xxirq(FEC_INTERRUPT, fec_enet_interrupt, 0, "fec", dev) != 0)
1791 panic("Could not allocate FEC IRQ!");
1793 #ifdef CONFIG_RPXCLASSIC
1794 /* Make Port C, bit 15 an input that causes interrupts.
1796 immap->im_ioport.iop_pcpar &= ~0x0001;
1797 immap->im_ioport.iop_pcdir &= ~0x0001;
1798 immap->im_ioport.iop_pcso &= ~0x0001;
1799 immap->im_ioport.iop_pcint |= 0x0001;
1800 cpm_install_handler(CPMVEC_PIO_PC15, mii_link_interrupt, dev);
1802 /* Make LEDS reflect Link status.
1804 *((uint *) RPX_CSR_ADDR) &= ~BCSR2_FETHLEDMODE;
1808 static void __inline__ fec_get_mac(struct net_device *dev)
1813 memcpy(dev->dev_addr, bd->bi_enetaddr, ETH_ALEN);
1815 #ifdef CONFIG_RPXCLASSIC
1816 /* The Embedded Planet boards have only one MAC address in
1817 * the EEPROM, but can have two Ethernet ports. For the
1818 * FEC port, we create another address by setting one of
1819 * the address bits above something that would have (up to
1820 * now) been allocated.
1822 dev->dev_adrd[3] |= 0x80;
1826 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1828 extern uint _get_IMMR(void);
1829 volatile immap_t *immap;
1830 volatile fec_t *fecp;
1833 immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */
1835 /* Configure all of port D for MII.
1837 immap->im_ioport.iop_pdpar = 0x1fff;
1839 /* Bits moved from Rev. D onward.
1841 if ((_get_IMMR() & 0xffff) < 0x0501)
1842 immap->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */
1844 immap->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */
1846 /* Set MII speed to 2.5 MHz
1848 fecp->fec_mii_speed = fep->phy_speed =
1849 ((bd->bi_busfreq * 1000000) / 2500000) & 0x7e;
1852 static void __inline__ fec_enable_phy_intr(void)
1854 volatile fec_t *fecp;
1858 /* Enable MII command finished interrupt
1860 fecp->fec_ivec = (FEC_INTERRUPT/2) << 29;
1863 static void __inline__ fec_disable_phy_intr(void)
1867 static void __inline__ fec_phy_ack_intr(void)
1871 static void __inline__ fec_localhw_setup(void)
1873 volatile fec_t *fecp;
1876 fecp->fec_r_hash = PKT_MAXBUF_SIZE;
1877 /* Enable big endian and don't care about SDMA FC.
1879 fecp->fec_fun_code = 0x78000000;
1882 static void __inline__ fec_uncache(unsigned long addr)
1885 pte = va_to_pte(mem_addr);
1886 pte_val(*pte) |= _PAGE_NO_CACHE;
1887 flush_tlb_page(init_mm.mmap, mem_addr);
1892 /* ------------------------------------------------------------------------- */
1894 static void mii_display_status(struct net_device *dev)
1896 struct fec_enet_private *fep = netdev_priv(dev);
1897 volatile uint *s = &(fep->phy_status);
1899 if (!fep->link && !fep->old_link) {
1900 /* Link is still down - don't print anything */
1904 printk("%s: status: ", dev->name);
1907 printk("link down");
1911 switch(*s & PHY_STAT_SPMASK) {
1912 case PHY_STAT_100FDX: printk(", 100MBit Full Duplex"); break;
1913 case PHY_STAT_100HDX: printk(", 100MBit Half Duplex"); break;
1914 case PHY_STAT_10FDX: printk(", 10MBit Full Duplex"); break;
1915 case PHY_STAT_10HDX: printk(", 10MBit Half Duplex"); break;
1917 printk(", Unknown speed/duplex");
1920 if (*s & PHY_STAT_ANC)
1921 printk(", auto-negotiation complete");
1924 if (*s & PHY_STAT_FAULT)
1925 printk(", remote fault");
1930 static void mii_display_config(struct work_struct *work)
1932 struct fec_enet_private *fep = container_of(work, struct fec_enet_private, phy_task);
1933 struct net_device *dev = fep->netdev;
1934 uint status = fep->phy_status;
1937 ** When we get here, phy_task is already removed from
1938 ** the workqueue. It is thus safe to allow to reuse it.
1940 fep->mii_phy_task_queued = 0;
1941 printk("%s: config: auto-negotiation ", dev->name);
1943 if (status & PHY_CONF_ANE)
1948 if (status & PHY_CONF_100FDX)
1950 if (status & PHY_CONF_100HDX)
1952 if (status & PHY_CONF_10FDX)
1954 if (status & PHY_CONF_10HDX)
1956 if (!(status & PHY_CONF_SPMASK))
1957 printk(", No speed/duplex selected?");
1959 if (status & PHY_CONF_LOOP)
1960 printk(", loopback enabled");
1964 fep->sequence_done = 1;
1967 static void mii_relink(struct work_struct *work)
1969 struct fec_enet_private *fep = container_of(work, struct fec_enet_private, phy_task);
1970 struct net_device *dev = fep->netdev;
1974 ** When we get here, phy_task is already removed from
1975 ** the workqueue. It is thus safe to allow to reuse it.
1977 fep->mii_phy_task_queued = 0;
1978 fep->link = (fep->phy_status & PHY_STAT_LINK) ? 1 : 0;
1979 mii_display_status(dev);
1980 fep->old_link = fep->link;
1985 & (PHY_STAT_100FDX | PHY_STAT_10FDX))
1987 fec_restart(dev, duplex);
1992 enable_irq(fep->mii_irq);
1997 /* mii_queue_relink is called in interrupt context from mii_link_interrupt */
1998 static void mii_queue_relink(uint mii_reg, struct net_device *dev)
2000 struct fec_enet_private *fep = netdev_priv(dev);
2003 ** We cannot queue phy_task twice in the workqueue. It
2004 ** would cause an endless loop in the workqueue.
2005 ** Fortunately, if the last mii_relink entry has not yet been
2006 ** executed now, it will do the job for the current interrupt,
2007 ** which is just what we want.
2009 if (fep->mii_phy_task_queued)
2012 fep->mii_phy_task_queued = 1;
2013 INIT_WORK(&fep->phy_task, mii_relink);
2014 schedule_work(&fep->phy_task);
2017 /* mii_queue_config is called in interrupt context from fec_enet_mii */
2018 static void mii_queue_config(uint mii_reg, struct net_device *dev)
2020 struct fec_enet_private *fep = netdev_priv(dev);
2022 if (fep->mii_phy_task_queued)
2025 fep->mii_phy_task_queued = 1;
2026 INIT_WORK(&fep->phy_task, mii_display_config);
2027 schedule_work(&fep->phy_task);
2030 phy_cmd_t const phy_cmd_relink[] = {
2031 { mk_mii_read(MII_REG_CR), mii_queue_relink },
2034 phy_cmd_t const phy_cmd_config[] = {
2035 { mk_mii_read(MII_REG_CR), mii_queue_config },
2039 /* Read remainder of PHY ID.
2042 mii_discover_phy3(uint mii_reg, struct net_device *dev)
2044 struct fec_enet_private *fep;
2047 fep = netdev_priv(dev);
2048 fep->phy_id |= (mii_reg & 0xffff);
2049 printk("fec: PHY @ 0x%x, ID 0x%08x", fep->phy_addr, fep->phy_id);
2051 for(i = 0; phy_info[i]; i++) {
2052 if(phy_info[i]->id == (fep->phy_id >> 4))
2057 printk(" -- %s\n", phy_info[i]->name);
2059 printk(" -- unknown PHY!\n");
2061 fep->phy = phy_info[i];
2062 fep->phy_id_done = 1;
2065 /* Scan all of the MII PHY addresses looking for someone to respond
2066 * with a valid ID. This usually happens quickly.
2069 mii_discover_phy(uint mii_reg, struct net_device *dev)
2071 struct fec_enet_private *fep;
2072 volatile fec_t *fecp;
2075 fep = netdev_priv(dev);
2078 if (fep->phy_addr < 32) {
2079 if ((phytype = (mii_reg & 0xffff)) != 0xffff && phytype != 0) {
2081 /* Got first part of ID, now get remainder.
2083 fep->phy_id = phytype << 16;
2084 mii_queue(dev, mk_mii_read(MII_REG_PHYIR2),
2088 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1),
2092 printk("FEC: No PHY device found.\n");
2093 /* Disable external MII interface */
2094 fecp->fec_mii_speed = fep->phy_speed = 0;
2095 fec_disable_phy_intr();
2099 /* This interrupt occurs when the PHY detects a link change.
2101 #ifdef HAVE_mii_link_interrupt
2102 #ifdef CONFIG_RPXCLASSIC
2104 mii_link_interrupt(void *dev_id)
2107 mii_link_interrupt(int irq, void * dev_id)
2110 struct net_device *dev = dev_id;
2111 struct fec_enet_private *fep = netdev_priv(dev);
2116 disable_irq(fep->mii_irq); /* disable now, enable later */
2119 mii_do_cmd(dev, fep->phy->ack_int);
2120 mii_do_cmd(dev, phy_cmd_relink); /* restart and display status */
2127 fec_enet_open(struct net_device *dev)
2129 struct fec_enet_private *fep = netdev_priv(dev);
2131 /* I should reset the ring buffers here, but I don't yet know
2132 * a simple way to do that.
2134 fec_set_mac_address(dev);
2136 fep->sequence_done = 0;
2140 mii_do_cmd(dev, fep->phy->ack_int);
2141 mii_do_cmd(dev, fep->phy->config);
2142 mii_do_cmd(dev, phy_cmd_config); /* display configuration */
2144 /* Poll until the PHY tells us its configuration
2146 * Request is initiated by mii_do_cmd above, but answer
2147 * comes by interrupt.
2148 * This should take about 25 usec per register at 2.5 MHz,
2149 * and we read approximately 5 registers.
2151 while(!fep->sequence_done)
2154 mii_do_cmd(dev, fep->phy->startup);
2156 /* Set the initial link state to true. A lot of hardware
2157 * based on this device does not implement a PHY interrupt,
2158 * so we are never notified of link change.
2162 fep->link = 1; /* lets just try it and see */
2163 /* no phy, go full duplex, it's most likely a hub chip */
2164 fec_restart(dev, 1);
2167 netif_start_queue(dev);
2169 return 0; /* Success */
2173 fec_enet_close(struct net_device *dev)
2175 struct fec_enet_private *fep = netdev_priv(dev);
2177 /* Don't know what to do yet.
2180 netif_stop_queue(dev);
2186 /* Set or clear the multicast filter for this adaptor.
2187 * Skeleton taken from sunlance driver.
2188 * The CPM Ethernet implementation allows Multicast as well as individual
2189 * MAC address filtering. Some of the drivers check to make sure it is
2190 * a group multicast address, and discard those that are not. I guess I
2191 * will do the same for now, but just remove the test if you want
2192 * individual filtering as well (do the upper net layers want or support
2193 * this kind of feature?).
2196 #define HASH_BITS 6 /* #bits in hash */
2197 #define CRC32_POLY 0xEDB88320
2199 static void set_multicast_list(struct net_device *dev)
2201 struct fec_enet_private *fep;
2203 struct dev_mc_list *dmi;
2204 unsigned int i, j, bit, data, crc;
2207 fep = netdev_priv(dev);
2210 if (dev->flags&IFF_PROMISC) {
2211 ep->fec_r_cntrl |= 0x0008;
2214 ep->fec_r_cntrl &= ~0x0008;
2216 if (dev->flags & IFF_ALLMULTI) {
2217 /* Catch all multicast addresses, so set the
2218 * filter to all 1's.
2220 ep->fec_grp_hash_table_high = 0xffffffff;
2221 ep->fec_grp_hash_table_low = 0xffffffff;
2223 /* Clear filter and add the addresses in hash register.
2225 ep->fec_grp_hash_table_high = 0;
2226 ep->fec_grp_hash_table_low = 0;
2230 for (j = 0; j < dev->mc_count; j++, dmi = dmi->next)
2232 /* Only support group multicast for now.
2234 if (!(dmi->dmi_addr[0] & 1))
2237 /* calculate crc32 value of mac address
2241 for (i = 0; i < dmi->dmi_addrlen; i++)
2243 data = dmi->dmi_addr[i];
2244 for (bit = 0; bit < 8; bit++, data >>= 1)
2247 (((crc ^ data) & 1) ? CRC32_POLY : 0);
2251 /* only upper 6 bits (HASH_BITS) are used
2252 which point to specific bit in he hash registers
2254 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
2257 ep->fec_grp_hash_table_high |= 1 << (hash - 32);
2259 ep->fec_grp_hash_table_low |= 1 << hash;
2265 /* Set a MAC change in hardware.
2268 fec_set_mac_address(struct net_device *dev)
2270 volatile fec_t *fecp;
2272 fecp = ((struct fec_enet_private *)netdev_priv(dev))->hwp;
2274 /* Set station address. */
2275 fecp->fec_addr_low = dev->dev_addr[3] | (dev->dev_addr[2] << 8) |
2276 (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24);
2277 fecp->fec_addr_high = (dev->dev_addr[5] << 16) |
2278 (dev->dev_addr[4] << 24);
2282 /* Initialize the FEC Ethernet on 860T (or ColdFire 5272).
2285 * XXX: We need to clean up on failure exits here.
2287 int __init fec_enet_init(struct net_device *dev)
2289 struct fec_enet_private *fep = netdev_priv(dev);
2290 unsigned long mem_addr;
2291 volatile cbd_t *bdp;
2293 volatile fec_t *fecp;
2295 static int index = 0;
2297 /* Only allow us to be probed once. */
2298 if (index >= FEC_MAX_PORTS)
2301 /* Allocate memory for buffer descriptors.
2303 mem_addr = __get_free_page(GFP_KERNEL);
2304 if (mem_addr == 0) {
2305 printk("FEC: allocate descriptor memory failed?\n");
2309 spin_lock_init(&fep->hw_lock);
2310 spin_lock_init(&fep->mii_lock);
2312 /* Create an Ethernet device instance.
2314 fecp = (volatile fec_t *) fec_hw[index];
2320 /* Whack a reset. We should wait for this.
2322 fecp->fec_ecntrl = 1;
2325 /* Set the Ethernet address. If using multiple Enets on the 8xx,
2326 * this needs some work to get unique addresses.
2328 * This is our default MAC address unless the user changes
2329 * it via eth_mac_addr (our dev->set_mac_addr handler).
2333 cbd_base = (cbd_t *)mem_addr;
2334 /* XXX: missing check for allocation failure */
2336 fec_uncache(mem_addr);
2338 /* Set receive and transmit descriptor base.
2340 fep->rx_bd_base = cbd_base;
2341 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
2343 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
2344 fep->cur_rx = fep->rx_bd_base;
2346 fep->skb_cur = fep->skb_dirty = 0;
2348 /* Initialize the receive buffer descriptors.
2350 bdp = fep->rx_bd_base;
2351 for (i=0; i<FEC_ENET_RX_PAGES; i++) {
2355 mem_addr = __get_free_page(GFP_KERNEL);
2356 /* XXX: missing check for allocation failure */
2358 fec_uncache(mem_addr);
2360 /* Initialize the BD for every fragment in the page.
2362 for (j=0; j<FEC_ENET_RX_FRPPG; j++) {
2363 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2364 bdp->cbd_bufaddr = __pa(mem_addr);
2365 mem_addr += FEC_ENET_RX_FRSIZE;
2370 /* Set the last buffer to wrap.
2373 bdp->cbd_sc |= BD_SC_WRAP;
2375 /* ...and the same for transmmit.
2377 bdp = fep->tx_bd_base;
2378 for (i=0, j=FEC_ENET_TX_FRPPG; i<TX_RING_SIZE; i++) {
2379 if (j >= FEC_ENET_TX_FRPPG) {
2380 mem_addr = __get_free_page(GFP_KERNEL);
2383 mem_addr += FEC_ENET_TX_FRSIZE;
2386 fep->tx_bounce[i] = (unsigned char *) mem_addr;
2388 /* Initialize the BD for every fragment in the page.
2391 bdp->cbd_bufaddr = 0;
2395 /* Set the last buffer to wrap.
2398 bdp->cbd_sc |= BD_SC_WRAP;
2400 /* Set receive and transmit descriptor base.
2402 fecp->fec_r_des_start = __pa((uint)(fep->rx_bd_base));
2403 fecp->fec_x_des_start = __pa((uint)(fep->tx_bd_base));
2405 /* Install our interrupt handlers. This varies depending on
2408 fec_request_intrs(dev);
2410 fecp->fec_grp_hash_table_high = 0;
2411 fecp->fec_grp_hash_table_low = 0;
2412 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
2413 fecp->fec_ecntrl = 2;
2414 fecp->fec_r_des_active = 0;
2415 #ifndef CONFIG_M5272
2416 fecp->fec_hash_table_high = 0;
2417 fecp->fec_hash_table_low = 0;
2420 dev->base_addr = (unsigned long)fecp;
2422 /* The FEC Ethernet specific entries in the device structure. */
2423 dev->open = fec_enet_open;
2424 dev->hard_start_xmit = fec_enet_start_xmit;
2425 dev->tx_timeout = fec_timeout;
2426 dev->watchdog_timeo = TX_TIMEOUT;
2427 dev->stop = fec_enet_close;
2428 dev->set_multicast_list = set_multicast_list;
2430 for (i=0; i<NMII-1; i++)
2431 mii_cmds[i].mii_next = &mii_cmds[i+1];
2432 mii_free = mii_cmds;
2434 /* setup MII interface */
2435 fec_set_mii(dev, fep);
2437 /* Clear and enable interrupts */
2438 fecp->fec_ievent = 0xffc00000;
2439 fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII);
2441 /* Queue up command to detect the PHY and initialize the
2442 * remainder of the interface.
2444 fep->phy_id_done = 0;
2446 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), mii_discover_phy);
2452 /* This function is called to start or restart the FEC during a link
2453 * change. This only happens when switching between half and full
2457 fec_restart(struct net_device *dev, int duplex)
2459 struct fec_enet_private *fep;
2460 volatile cbd_t *bdp;
2461 volatile fec_t *fecp;
2464 fep = netdev_priv(dev);
2467 /* Whack a reset. We should wait for this.
2469 fecp->fec_ecntrl = 1;
2472 /* Clear any outstanding interrupt.
2474 fecp->fec_ievent = 0xffc00000;
2475 fec_enable_phy_intr();
2477 /* Set station address.
2479 fec_set_mac_address(dev);
2481 /* Reset all multicast.
2483 fecp->fec_grp_hash_table_high = 0;
2484 fecp->fec_grp_hash_table_low = 0;
2486 /* Set maximum receive buffer size.
2488 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
2490 fec_localhw_setup();
2492 /* Set receive and transmit descriptor base.
2494 fecp->fec_r_des_start = __pa((uint)(fep->rx_bd_base));
2495 fecp->fec_x_des_start = __pa((uint)(fep->tx_bd_base));
2497 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
2498 fep->cur_rx = fep->rx_bd_base;
2500 /* Reset SKB transmit buffers.
2502 fep->skb_cur = fep->skb_dirty = 0;
2503 for (i=0; i<=TX_RING_MOD_MASK; i++) {
2504 if (fep->tx_skbuff[i] != NULL) {
2505 dev_kfree_skb_any(fep->tx_skbuff[i]);
2506 fep->tx_skbuff[i] = NULL;
2510 /* Initialize the receive buffer descriptors.
2512 bdp = fep->rx_bd_base;
2513 for (i=0; i<RX_RING_SIZE; i++) {
2515 /* Initialize the BD for every fragment in the page.
2517 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2521 /* Set the last buffer to wrap.
2524 bdp->cbd_sc |= BD_SC_WRAP;
2526 /* ...and the same for transmmit.
2528 bdp = fep->tx_bd_base;
2529 for (i=0; i<TX_RING_SIZE; i++) {
2531 /* Initialize the BD for every fragment in the page.
2534 bdp->cbd_bufaddr = 0;
2538 /* Set the last buffer to wrap.
2541 bdp->cbd_sc |= BD_SC_WRAP;
2546 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;/* MII enable */
2547 fecp->fec_x_cntrl = 0x04; /* FD enable */
2549 /* MII enable|No Rcv on Xmit */
2550 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x06;
2551 fecp->fec_x_cntrl = 0x00;
2553 fep->full_duplex = duplex;
2557 fecp->fec_mii_speed = fep->phy_speed;
2559 /* And last, enable the transmit and receive processing.
2561 fecp->fec_ecntrl = 2;
2562 fecp->fec_r_des_active = 0;
2564 /* Enable interrupts we wish to service.
2566 fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII);
2570 fec_stop(struct net_device *dev)
2572 volatile fec_t *fecp;
2573 struct fec_enet_private *fep;
2575 fep = netdev_priv(dev);
2579 ** We cannot expect a graceful transmit stop without link !!!
2583 fecp->fec_x_cntrl = 0x01; /* Graceful transmit stop */
2585 if (!(fecp->fec_ievent & FEC_ENET_GRA))
2586 printk("fec_stop : Graceful transmit stop did not complete !\n");
2589 /* Whack a reset. We should wait for this.
2591 fecp->fec_ecntrl = 1;
2594 /* Clear outstanding MII command interrupts.
2596 fecp->fec_ievent = FEC_ENET_MII;
2597 fec_enable_phy_intr();
2599 fecp->fec_imask = FEC_ENET_MII;
2600 fecp->fec_mii_speed = fep->phy_speed;
2603 static int __init fec_enet_module_init(void)
2605 struct net_device *dev;
2607 DECLARE_MAC_BUF(mac);
2609 printk("FEC ENET Version 0.2\n");
2611 for (i = 0; (i < FEC_MAX_PORTS); i++) {
2612 dev = alloc_etherdev(sizeof(struct fec_enet_private));
2615 err = fec_enet_init(dev);
2620 if (register_netdev(dev) != 0) {
2621 /* XXX: missing cleanup here */
2626 printk("%s: ethernet %s\n",
2627 dev->name, print_mac(mac, dev->dev_addr));
2632 module_init(fec_enet_module_init);
2634 MODULE_LICENSE("GPL");