2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
21 * Copyright (C) 2010 Freescale Semiconductor, Inc.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/pci.h>
33 #include <linux/init.h>
34 #include <linux/delay.h>
35 #include <linux/netdevice.h>
36 #include <linux/etherdevice.h>
37 #include <linux/skbuff.h>
38 #include <linux/spinlock.h>
39 #include <linux/workqueue.h>
40 #include <linux/bitops.h>
42 #include <linux/irq.h>
43 #include <linux/clk.h>
44 #include <linux/platform_device.h>
45 #include <linux/phy.h>
46 #include <linux/fec.h>
48 #include <asm/cacheflush.h>
51 #include <asm/coldfire.h>
52 #include <asm/mcfsim.h>
57 #if defined(CONFIG_ARM)
58 #define FEC_ALIGNMENT 0xf
60 #define FEC_ALIGNMENT 0x3
63 #define DRIVER_NAME "fec"
65 /* Controller is ENET-MAC */
66 #define FEC_QUIRK_ENET_MAC (1 << 0)
67 /* Controller needs driver to swap frame */
68 #define FEC_QUIRK_SWAP_FRAME (1 << 1)
70 static struct platform_device_id fec_devtype[] = {
76 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
80 static unsigned char macaddr[ETH_ALEN];
81 module_param_array(macaddr, byte, NULL, 0);
82 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
84 #if defined(CONFIG_M5272)
86 * Some hardware gets it MAC address out of local flash memory.
87 * if this is non-zero then assume it is the address to get MAC from.
89 #if defined(CONFIG_NETtel)
90 #define FEC_FLASHMAC 0xf0006006
91 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
92 #define FEC_FLASHMAC 0xf0006000
93 #elif defined(CONFIG_CANCam)
94 #define FEC_FLASHMAC 0xf0020000
95 #elif defined (CONFIG_M5272C3)
96 #define FEC_FLASHMAC (0xffe04000 + 4)
97 #elif defined(CONFIG_MOD5272)
98 #define FEC_FLASHMAC 0xffc0406b
100 #define FEC_FLASHMAC 0
102 #endif /* CONFIG_M5272 */
104 /* The number of Tx and Rx buffers. These are allocated from the page
105 * pool. The code may assume these are power of two, so it it best
106 * to keep them that size.
107 * We don't need to allocate pages for the transmitter. We just use
108 * the skbuffer directly.
110 #define FEC_ENET_RX_PAGES 8
111 #define FEC_ENET_RX_FRSIZE 2048
112 #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
113 #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
114 #define FEC_ENET_TX_FRSIZE 2048
115 #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
116 #define TX_RING_SIZE 16 /* Must be power of two */
117 #define TX_RING_MOD_MASK 15 /* for this to work */
119 #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
120 #error "FEC: descriptor ring size constants too large"
123 /* Interrupt events/masks. */
124 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
125 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
126 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
127 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
128 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
129 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
130 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
131 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
132 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
133 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
135 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
137 /* The FEC stores dest/src/type, data, and checksum for receive packets.
139 #define PKT_MAXBUF_SIZE 1518
140 #define PKT_MINBUF_SIZE 64
141 #define PKT_MAXBLR_SIZE 1520
145 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
146 * size bits. Other FEC hardware does not, so we need to take that into
147 * account when setting it.
149 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
150 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
151 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
153 #define OPT_FRAME_SIZE 0
156 /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
157 * tx_bd_base always point to the base of the buffer descriptors. The
158 * cur_rx and cur_tx point to the currently available buffer.
159 * The dirty_tx tracks the current buffer that is being sent by the
160 * controller. The cur_tx and dirty_tx are equal under both completely
161 * empty and completely full conditions. The empty/ready indicator in
162 * the buffer descriptor determines the actual condition.
164 struct fec_enet_private {
165 /* Hardware registers of the FEC device */
168 struct net_device *netdev;
172 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
173 unsigned char *tx_bounce[TX_RING_SIZE];
174 struct sk_buff* tx_skbuff[TX_RING_SIZE];
175 struct sk_buff* rx_skbuff[RX_RING_SIZE];
179 /* CPM dual port RAM relative addresses */
181 /* Address of Rx and Tx buffers */
182 struct bufdesc *rx_bd_base;
183 struct bufdesc *tx_bd_base;
184 /* The next free ring entry */
185 struct bufdesc *cur_rx, *cur_tx;
186 /* The ring entries to be free()ed */
187 struct bufdesc *dirty_tx;
190 /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */
193 struct platform_device *pdev;
197 /* Phylib and MDIO interface */
198 struct mii_bus *mii_bus;
199 struct phy_device *phy_dev;
202 phy_interface_t phy_interface;
205 struct completion mdio_done;
208 static irqreturn_t fec_enet_interrupt(int irq, void * dev_id);
209 static void fec_enet_tx(struct net_device *ndev);
210 static void fec_enet_rx(struct net_device *ndev);
211 static int fec_enet_close(struct net_device *ndev);
212 static void fec_restart(struct net_device *ndev, int duplex);
213 static void fec_stop(struct net_device *ndev);
215 /* FEC MII MMFR bits definition */
216 #define FEC_MMFR_ST (1 << 30)
217 #define FEC_MMFR_OP_READ (2 << 28)
218 #define FEC_MMFR_OP_WRITE (1 << 28)
219 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
220 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
221 #define FEC_MMFR_TA (2 << 16)
222 #define FEC_MMFR_DATA(v) (v & 0xffff)
224 #define FEC_MII_TIMEOUT 1000 /* us */
226 /* Transmitter timeout */
227 #define TX_TIMEOUT (2 * HZ)
229 static void *swap_buffer(void *bufaddr, int len)
232 unsigned int *buf = bufaddr;
234 for (i = 0; i < (len + 3) / 4; i++, buf++)
235 *buf = cpu_to_be32(*buf);
241 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
243 struct fec_enet_private *fep = netdev_priv(ndev);
244 const struct platform_device_id *id_entry =
245 platform_get_device_id(fep->pdev);
248 unsigned short status;
252 /* Link is down or autonegotiation is in progress. */
253 return NETDEV_TX_BUSY;
256 spin_lock_irqsave(&fep->hw_lock, flags);
257 /* Fill in a Tx ring entry */
260 status = bdp->cbd_sc;
262 if (status & BD_ENET_TX_READY) {
263 /* Ooops. All transmit buffers are full. Bail out.
264 * This should not happen, since ndev->tbusy should be set.
266 printk("%s: tx queue full!.\n", ndev->name);
267 spin_unlock_irqrestore(&fep->hw_lock, flags);
268 return NETDEV_TX_BUSY;
271 /* Clear all of the status flags */
272 status &= ~BD_ENET_TX_STATS;
274 /* Set buffer length and buffer pointer */
276 bdp->cbd_datlen = skb->len;
279 * On some FEC implementations data must be aligned on
280 * 4-byte boundaries. Use bounce buffers to copy data
281 * and get it aligned. Ugh.
283 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
285 index = bdp - fep->tx_bd_base;
286 memcpy(fep->tx_bounce[index], skb->data, skb->len);
287 bufaddr = fep->tx_bounce[index];
291 * Some design made an incorrect assumption on endian mode of
292 * the system that it's running on. As the result, driver has to
293 * swap every frame going to and coming from the controller.
295 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
296 swap_buffer(bufaddr, skb->len);
298 /* Save skb pointer */
299 fep->tx_skbuff[fep->skb_cur] = skb;
301 ndev->stats.tx_bytes += skb->len;
302 fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
304 /* Push the data cache so the CPM does not get stale memory
307 bdp->cbd_bufaddr = dma_map_single(&ndev->dev, bufaddr,
308 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
310 /* Send it on its way. Tell FEC it's ready, interrupt when done,
311 * it's the last BD of the frame, and to put the CRC on the end.
313 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
314 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
315 bdp->cbd_sc = status;
317 /* Trigger transmission start */
318 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
320 /* If this was the last BD in the ring, start at the beginning again. */
321 if (status & BD_ENET_TX_WRAP)
322 bdp = fep->tx_bd_base;
326 if (bdp == fep->dirty_tx) {
328 netif_stop_queue(ndev);
333 spin_unlock_irqrestore(&fep->hw_lock, flags);
339 fec_timeout(struct net_device *ndev)
341 struct fec_enet_private *fep = netdev_priv(ndev);
343 ndev->stats.tx_errors++;
345 fec_restart(ndev, fep->full_duplex);
346 netif_wake_queue(ndev);
350 fec_enet_interrupt(int irq, void *dev_id)
352 struct net_device *ndev = dev_id;
353 struct fec_enet_private *fep = netdev_priv(ndev);
355 irqreturn_t ret = IRQ_NONE;
358 int_events = readl(fep->hwp + FEC_IEVENT);
359 writel(int_events, fep->hwp + FEC_IEVENT);
361 if (int_events & FEC_ENET_RXF) {
366 /* Transmit OK, or non-fatal error. Update the buffer
367 * descriptors. FEC handles all errors, we just discover
368 * them as part of the transmit process.
370 if (int_events & FEC_ENET_TXF) {
375 if (int_events & FEC_ENET_MII) {
377 complete(&fep->mdio_done);
379 } while (int_events);
386 fec_enet_tx(struct net_device *ndev)
388 struct fec_enet_private *fep;
390 unsigned short status;
393 fep = netdev_priv(ndev);
394 spin_lock(&fep->hw_lock);
397 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
398 if (bdp == fep->cur_tx && fep->tx_full == 0)
401 dma_unmap_single(&ndev->dev, bdp->cbd_bufaddr, FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
402 bdp->cbd_bufaddr = 0;
404 skb = fep->tx_skbuff[fep->skb_dirty];
405 /* Check for errors. */
406 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
407 BD_ENET_TX_RL | BD_ENET_TX_UN |
409 ndev->stats.tx_errors++;
410 if (status & BD_ENET_TX_HB) /* No heartbeat */
411 ndev->stats.tx_heartbeat_errors++;
412 if (status & BD_ENET_TX_LC) /* Late collision */
413 ndev->stats.tx_window_errors++;
414 if (status & BD_ENET_TX_RL) /* Retrans limit */
415 ndev->stats.tx_aborted_errors++;
416 if (status & BD_ENET_TX_UN) /* Underrun */
417 ndev->stats.tx_fifo_errors++;
418 if (status & BD_ENET_TX_CSL) /* Carrier lost */
419 ndev->stats.tx_carrier_errors++;
421 ndev->stats.tx_packets++;
424 if (status & BD_ENET_TX_READY)
425 printk("HEY! Enet xmit interrupt and TX_READY.\n");
427 /* Deferred means some collisions occurred during transmit,
428 * but we eventually sent the packet OK.
430 if (status & BD_ENET_TX_DEF)
431 ndev->stats.collisions++;
433 /* Free the sk buffer associated with this last transmit */
434 dev_kfree_skb_any(skb);
435 fep->tx_skbuff[fep->skb_dirty] = NULL;
436 fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
438 /* Update pointer to next buffer descriptor to be transmitted */
439 if (status & BD_ENET_TX_WRAP)
440 bdp = fep->tx_bd_base;
444 /* Since we have freed up a buffer, the ring is no longer full
448 if (netif_queue_stopped(ndev))
449 netif_wake_queue(ndev);
453 spin_unlock(&fep->hw_lock);
457 /* During a receive, the cur_rx points to the current incoming buffer.
458 * When we update through the ring, if the next incoming buffer has
459 * not been given to the system, we just set the empty indicator,
460 * effectively tossing the packet.
463 fec_enet_rx(struct net_device *ndev)
465 struct fec_enet_private *fep = netdev_priv(ndev);
466 const struct platform_device_id *id_entry =
467 platform_get_device_id(fep->pdev);
469 unsigned short status;
478 spin_lock(&fep->hw_lock);
480 /* First, grab all of the stats for the incoming packet.
481 * These get messed up if we get called due to a busy condition.
485 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
487 /* Since we have allocated space to hold a complete frame,
488 * the last indicator should be set.
490 if ((status & BD_ENET_RX_LAST) == 0)
491 printk("FEC ENET: rcv is not +last\n");
494 goto rx_processing_done;
496 /* Check for errors. */
497 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
498 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
499 ndev->stats.rx_errors++;
500 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
501 /* Frame too long or too short. */
502 ndev->stats.rx_length_errors++;
504 if (status & BD_ENET_RX_NO) /* Frame alignment */
505 ndev->stats.rx_frame_errors++;
506 if (status & BD_ENET_RX_CR) /* CRC Error */
507 ndev->stats.rx_crc_errors++;
508 if (status & BD_ENET_RX_OV) /* FIFO overrun */
509 ndev->stats.rx_fifo_errors++;
512 /* Report late collisions as a frame error.
513 * On this error, the BD is closed, but we don't know what we
514 * have in the buffer. So, just drop this frame on the floor.
516 if (status & BD_ENET_RX_CL) {
517 ndev->stats.rx_errors++;
518 ndev->stats.rx_frame_errors++;
519 goto rx_processing_done;
522 /* Process the incoming frame. */
523 ndev->stats.rx_packets++;
524 pkt_len = bdp->cbd_datlen;
525 ndev->stats.rx_bytes += pkt_len;
526 data = (__u8*)__va(bdp->cbd_bufaddr);
528 dma_unmap_single(NULL, bdp->cbd_bufaddr, bdp->cbd_datlen,
531 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
532 swap_buffer(data, pkt_len);
534 /* This does 16 byte alignment, exactly what we need.
535 * The packet length includes FCS, but we don't want to
536 * include that when passing upstream as it messes up
537 * bridging applications.
539 skb = dev_alloc_skb(pkt_len - 4 + NET_IP_ALIGN);
541 if (unlikely(!skb)) {
542 printk("%s: Memory squeeze, dropping packet.\n",
544 ndev->stats.rx_dropped++;
546 skb_reserve(skb, NET_IP_ALIGN);
547 skb_put(skb, pkt_len - 4); /* Make room */
548 skb_copy_to_linear_data(skb, data, pkt_len - 4);
549 skb->protocol = eth_type_trans(skb, ndev);
553 bdp->cbd_bufaddr = dma_map_single(NULL, data, bdp->cbd_datlen,
556 /* Clear the status flags for this buffer */
557 status &= ~BD_ENET_RX_STATS;
559 /* Mark the buffer empty */
560 status |= BD_ENET_RX_EMPTY;
561 bdp->cbd_sc = status;
563 /* Update BD pointer to next entry */
564 if (status & BD_ENET_RX_WRAP)
565 bdp = fep->rx_bd_base;
568 /* Doing this here will keep the FEC running while we process
569 * incoming frames. On a heavily loaded network, we should be
570 * able to keep up at the expense of system resources.
572 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
576 spin_unlock(&fep->hw_lock);
579 /* ------------------------------------------------------------------------- */
580 static void __inline__ fec_get_mac(struct net_device *ndev)
582 struct fec_enet_private *fep = netdev_priv(ndev);
583 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
584 unsigned char *iap, tmpaddr[ETH_ALEN];
587 * try to get mac address in following order:
589 * 1) module parameter via kernel command line in form
590 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
595 * 2) from flash or fuse (via platform data)
597 if (!is_valid_ether_addr(iap)) {
600 iap = (unsigned char *)FEC_FLASHMAC;
603 memcpy(iap, pdata->mac, ETH_ALEN);
608 * 3) FEC mac registers set by bootloader
610 if (!is_valid_ether_addr(iap)) {
611 *((unsigned long *) &tmpaddr[0]) =
612 be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW));
613 *((unsigned short *) &tmpaddr[4]) =
614 be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
618 memcpy(ndev->dev_addr, iap, ETH_ALEN);
620 /* Adjust MAC if using macaddr */
622 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->pdev->id;
625 /* ------------------------------------------------------------------------- */
630 static void fec_enet_adjust_link(struct net_device *ndev)
632 struct fec_enet_private *fep = netdev_priv(ndev);
633 struct phy_device *phy_dev = fep->phy_dev;
636 int status_change = 0;
638 spin_lock_irqsave(&fep->hw_lock, flags);
640 /* Prevent a state halted on mii error */
641 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
642 phy_dev->state = PHY_RESUMING;
646 /* Duplex link change */
648 if (fep->full_duplex != phy_dev->duplex) {
649 fec_restart(ndev, phy_dev->duplex);
654 /* Link on or off change */
655 if (phy_dev->link != fep->link) {
656 fep->link = phy_dev->link;
658 fec_restart(ndev, phy_dev->duplex);
665 spin_unlock_irqrestore(&fep->hw_lock, flags);
668 phy_print_status(phy_dev);
671 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
673 struct fec_enet_private *fep = bus->priv;
674 unsigned long time_left;
676 fep->mii_timeout = 0;
677 init_completion(&fep->mdio_done);
679 /* start a read op */
680 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
681 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
682 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
684 /* wait for end of transfer */
685 time_left = wait_for_completion_timeout(&fep->mdio_done,
686 usecs_to_jiffies(FEC_MII_TIMEOUT));
687 if (time_left == 0) {
688 fep->mii_timeout = 1;
689 printk(KERN_ERR "FEC: MDIO read timeout\n");
694 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
697 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
700 struct fec_enet_private *fep = bus->priv;
701 unsigned long time_left;
703 fep->mii_timeout = 0;
704 init_completion(&fep->mdio_done);
706 /* start a write op */
707 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
708 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
709 FEC_MMFR_TA | FEC_MMFR_DATA(value),
710 fep->hwp + FEC_MII_DATA);
712 /* wait for end of transfer */
713 time_left = wait_for_completion_timeout(&fep->mdio_done,
714 usecs_to_jiffies(FEC_MII_TIMEOUT));
715 if (time_left == 0) {
716 fep->mii_timeout = 1;
717 printk(KERN_ERR "FEC: MDIO write timeout\n");
724 static int fec_enet_mdio_reset(struct mii_bus *bus)
729 static int fec_enet_mii_probe(struct net_device *ndev)
731 struct fec_enet_private *fep = netdev_priv(ndev);
732 struct phy_device *phy_dev = NULL;
733 char mdio_bus_id[MII_BUS_ID_SIZE];
734 char phy_name[MII_BUS_ID_SIZE + 3];
736 int dev_id = fep->pdev->id;
740 /* check for attached phy */
741 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
742 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
744 if (fep->mii_bus->phy_map[phy_id] == NULL)
746 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
750 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
754 if (phy_id >= PHY_MAX_ADDR) {
755 printk(KERN_INFO "%s: no PHY, assuming direct connection "
756 "to switch\n", ndev->name);
757 strncpy(mdio_bus_id, "0", MII_BUS_ID_SIZE);
761 snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT, mdio_bus_id, phy_id);
762 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 0,
763 PHY_INTERFACE_MODE_MII);
764 if (IS_ERR(phy_dev)) {
765 printk(KERN_ERR "%s: could not attach to PHY\n", ndev->name);
766 return PTR_ERR(phy_dev);
769 /* mask with MAC supported features */
770 phy_dev->supported &= PHY_BASIC_FEATURES;
771 phy_dev->advertising = phy_dev->supported;
773 fep->phy_dev = phy_dev;
775 fep->full_duplex = 0;
777 printk(KERN_INFO "%s: Freescale FEC PHY driver [%s] "
778 "(mii_bus:phy_addr=%s, irq=%d)\n", ndev->name,
779 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
785 static int fec_enet_mii_init(struct platform_device *pdev)
787 static struct mii_bus *fec0_mii_bus;
788 struct net_device *ndev = platform_get_drvdata(pdev);
789 struct fec_enet_private *fep = netdev_priv(ndev);
790 const struct platform_device_id *id_entry =
791 platform_get_device_id(fep->pdev);
795 * The dual fec interfaces are not equivalent with enet-mac.
796 * Here are the differences:
798 * - fec0 supports MII & RMII modes while fec1 only supports RMII
799 * - fec0 acts as the 1588 time master while fec1 is slave
800 * - external phys can only be configured by fec0
802 * That is to say fec1 can not work independently. It only works
803 * when fec0 is working. The reason behind this design is that the
804 * second interface is added primarily for Switch mode.
806 * Because of the last point above, both phys are attached on fec0
807 * mdio interface in board design, and need to be configured by
810 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && pdev->id) {
811 /* fec1 uses fec0 mii_bus */
812 fep->mii_bus = fec0_mii_bus;
816 fep->mii_timeout = 0;
819 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
821 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000) << 1;
822 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
824 fep->mii_bus = mdiobus_alloc();
825 if (fep->mii_bus == NULL) {
830 fep->mii_bus->name = "fec_enet_mii_bus";
831 fep->mii_bus->read = fec_enet_mdio_read;
832 fep->mii_bus->write = fec_enet_mdio_write;
833 fep->mii_bus->reset = fec_enet_mdio_reset;
834 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id + 1);
835 fep->mii_bus->priv = fep;
836 fep->mii_bus->parent = &pdev->dev;
838 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
839 if (!fep->mii_bus->irq) {
841 goto err_out_free_mdiobus;
844 for (i = 0; i < PHY_MAX_ADDR; i++)
845 fep->mii_bus->irq[i] = PHY_POLL;
847 platform_set_drvdata(ndev, fep->mii_bus);
849 if (mdiobus_register(fep->mii_bus))
850 goto err_out_free_mdio_irq;
852 /* save fec0 mii_bus */
853 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
854 fec0_mii_bus = fep->mii_bus;
858 err_out_free_mdio_irq:
859 kfree(fep->mii_bus->irq);
860 err_out_free_mdiobus:
861 mdiobus_free(fep->mii_bus);
866 static void fec_enet_mii_remove(struct fec_enet_private *fep)
869 phy_disconnect(fep->phy_dev);
870 mdiobus_unregister(fep->mii_bus);
871 kfree(fep->mii_bus->irq);
872 mdiobus_free(fep->mii_bus);
875 static int fec_enet_get_settings(struct net_device *ndev,
876 struct ethtool_cmd *cmd)
878 struct fec_enet_private *fep = netdev_priv(ndev);
879 struct phy_device *phydev = fep->phy_dev;
884 return phy_ethtool_gset(phydev, cmd);
887 static int fec_enet_set_settings(struct net_device *ndev,
888 struct ethtool_cmd *cmd)
890 struct fec_enet_private *fep = netdev_priv(ndev);
891 struct phy_device *phydev = fep->phy_dev;
896 return phy_ethtool_sset(phydev, cmd);
899 static void fec_enet_get_drvinfo(struct net_device *ndev,
900 struct ethtool_drvinfo *info)
902 struct fec_enet_private *fep = netdev_priv(ndev);
904 strcpy(info->driver, fep->pdev->dev.driver->name);
905 strcpy(info->version, "Revision: 1.0");
906 strcpy(info->bus_info, dev_name(&ndev->dev));
909 static struct ethtool_ops fec_enet_ethtool_ops = {
910 .get_settings = fec_enet_get_settings,
911 .set_settings = fec_enet_set_settings,
912 .get_drvinfo = fec_enet_get_drvinfo,
913 .get_link = ethtool_op_get_link,
916 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
918 struct fec_enet_private *fep = netdev_priv(ndev);
919 struct phy_device *phydev = fep->phy_dev;
921 if (!netif_running(ndev))
927 return phy_mii_ioctl(phydev, rq, cmd);
930 static void fec_enet_free_buffers(struct net_device *ndev)
932 struct fec_enet_private *fep = netdev_priv(ndev);
937 bdp = fep->rx_bd_base;
938 for (i = 0; i < RX_RING_SIZE; i++) {
939 skb = fep->rx_skbuff[i];
941 if (bdp->cbd_bufaddr)
942 dma_unmap_single(&ndev->dev, bdp->cbd_bufaddr,
943 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
949 bdp = fep->tx_bd_base;
950 for (i = 0; i < TX_RING_SIZE; i++)
951 kfree(fep->tx_bounce[i]);
954 static int fec_enet_alloc_buffers(struct net_device *ndev)
956 struct fec_enet_private *fep = netdev_priv(ndev);
961 bdp = fep->rx_bd_base;
962 for (i = 0; i < RX_RING_SIZE; i++) {
963 skb = dev_alloc_skb(FEC_ENET_RX_FRSIZE);
965 fec_enet_free_buffers(ndev);
968 fep->rx_skbuff[i] = skb;
970 bdp->cbd_bufaddr = dma_map_single(&ndev->dev, skb->data,
971 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
972 bdp->cbd_sc = BD_ENET_RX_EMPTY;
976 /* Set the last buffer to wrap. */
978 bdp->cbd_sc |= BD_SC_WRAP;
980 bdp = fep->tx_bd_base;
981 for (i = 0; i < TX_RING_SIZE; i++) {
982 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
985 bdp->cbd_bufaddr = 0;
989 /* Set the last buffer to wrap. */
991 bdp->cbd_sc |= BD_SC_WRAP;
997 fec_enet_open(struct net_device *ndev)
999 struct fec_enet_private *fep = netdev_priv(ndev);
1002 /* I should reset the ring buffers here, but I don't yet know
1003 * a simple way to do that.
1006 ret = fec_enet_alloc_buffers(ndev);
1010 /* Probe and connect to PHY when open the interface */
1011 ret = fec_enet_mii_probe(ndev);
1013 fec_enet_free_buffers(ndev);
1016 phy_start(fep->phy_dev);
1017 netif_start_queue(ndev);
1023 fec_enet_close(struct net_device *ndev)
1025 struct fec_enet_private *fep = netdev_priv(ndev);
1027 /* Don't know what to do yet. */
1029 netif_stop_queue(ndev);
1033 phy_stop(fep->phy_dev);
1034 phy_disconnect(fep->phy_dev);
1037 fec_enet_free_buffers(ndev);
1042 /* Set or clear the multicast filter for this adaptor.
1043 * Skeleton taken from sunlance driver.
1044 * The CPM Ethernet implementation allows Multicast as well as individual
1045 * MAC address filtering. Some of the drivers check to make sure it is
1046 * a group multicast address, and discard those that are not. I guess I
1047 * will do the same for now, but just remove the test if you want
1048 * individual filtering as well (do the upper net layers want or support
1049 * this kind of feature?).
1052 #define HASH_BITS 6 /* #bits in hash */
1053 #define CRC32_POLY 0xEDB88320
1055 static void set_multicast_list(struct net_device *ndev)
1057 struct fec_enet_private *fep = netdev_priv(ndev);
1058 struct netdev_hw_addr *ha;
1059 unsigned int i, bit, data, crc, tmp;
1062 if (ndev->flags & IFF_PROMISC) {
1063 tmp = readl(fep->hwp + FEC_R_CNTRL);
1065 writel(tmp, fep->hwp + FEC_R_CNTRL);
1069 tmp = readl(fep->hwp + FEC_R_CNTRL);
1071 writel(tmp, fep->hwp + FEC_R_CNTRL);
1073 if (ndev->flags & IFF_ALLMULTI) {
1074 /* Catch all multicast addresses, so set the
1077 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1078 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1083 /* Clear filter and add the addresses in hash register
1085 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1086 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1088 netdev_for_each_mc_addr(ha, ndev) {
1089 /* Only support group multicast for now */
1090 if (!(ha->addr[0] & 1))
1093 /* calculate crc32 value of mac address */
1096 for (i = 0; i < ndev->addr_len; i++) {
1098 for (bit = 0; bit < 8; bit++, data >>= 1) {
1100 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1104 /* only upper 6 bits (HASH_BITS) are used
1105 * which point to specific bit in he hash registers
1107 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
1110 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1111 tmp |= 1 << (hash - 32);
1112 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1114 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1116 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1121 /* Set a MAC change in hardware. */
1123 fec_set_mac_address(struct net_device *ndev, void *p)
1125 struct fec_enet_private *fep = netdev_priv(ndev);
1126 struct sockaddr *addr = p;
1128 if (!is_valid_ether_addr(addr->sa_data))
1129 return -EADDRNOTAVAIL;
1131 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
1133 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
1134 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
1135 fep->hwp + FEC_ADDR_LOW);
1136 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
1137 fep->hwp + FEC_ADDR_HIGH);
1141 static const struct net_device_ops fec_netdev_ops = {
1142 .ndo_open = fec_enet_open,
1143 .ndo_stop = fec_enet_close,
1144 .ndo_start_xmit = fec_enet_start_xmit,
1145 .ndo_set_multicast_list = set_multicast_list,
1146 .ndo_change_mtu = eth_change_mtu,
1147 .ndo_validate_addr = eth_validate_addr,
1148 .ndo_tx_timeout = fec_timeout,
1149 .ndo_set_mac_address = fec_set_mac_address,
1150 .ndo_do_ioctl = fec_enet_ioctl,
1154 * XXX: We need to clean up on failure exits here.
1157 static int fec_enet_init(struct net_device *ndev)
1159 struct fec_enet_private *fep = netdev_priv(ndev);
1160 struct bufdesc *cbd_base;
1161 struct bufdesc *bdp;
1164 /* Allocate memory for buffer descriptors. */
1165 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
1168 printk("FEC: allocate descriptor memory failed?\n");
1172 spin_lock_init(&fep->hw_lock);
1176 /* Get the Ethernet address */
1179 /* Set receive and transmit descriptor base. */
1180 fep->rx_bd_base = cbd_base;
1181 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
1183 /* The FEC Ethernet specific entries in the device structure */
1184 ndev->watchdog_timeo = TX_TIMEOUT;
1185 ndev->netdev_ops = &fec_netdev_ops;
1186 ndev->ethtool_ops = &fec_enet_ethtool_ops;
1188 /* Initialize the receive buffer descriptors. */
1189 bdp = fep->rx_bd_base;
1190 for (i = 0; i < RX_RING_SIZE; i++) {
1192 /* Initialize the BD for every fragment in the page. */
1197 /* Set the last buffer to wrap */
1199 bdp->cbd_sc |= BD_SC_WRAP;
1201 /* ...and the same for transmit */
1202 bdp = fep->tx_bd_base;
1203 for (i = 0; i < TX_RING_SIZE; i++) {
1205 /* Initialize the BD for every fragment in the page. */
1207 bdp->cbd_bufaddr = 0;
1211 /* Set the last buffer to wrap */
1213 bdp->cbd_sc |= BD_SC_WRAP;
1215 fec_restart(ndev, 0);
1220 /* This function is called to start or restart the FEC during a link
1221 * change. This only happens when switching between half and full
1225 fec_restart(struct net_device *ndev, int duplex)
1227 struct fec_enet_private *fep = netdev_priv(ndev);
1228 const struct platform_device_id *id_entry =
1229 platform_get_device_id(fep->pdev);
1231 u32 val, temp_mac[2];
1233 /* Whack a reset. We should wait for this. */
1234 writel(1, fep->hwp + FEC_ECNTRL);
1238 * enet-mac reset will reset mac address registers too,
1239 * so need to reconfigure it.
1241 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
1242 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
1243 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
1244 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
1247 /* Clear any outstanding interrupt. */
1248 writel(0xffc00000, fep->hwp + FEC_IEVENT);
1250 /* Reset all multicast. */
1251 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1252 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1253 #ifndef CONFIG_M5272
1254 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1255 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1258 /* Set maximum receive buffer size. */
1259 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
1261 /* Set receive and transmit descriptor base. */
1262 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
1263 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE,
1264 fep->hwp + FEC_X_DES_START);
1266 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
1267 fep->cur_rx = fep->rx_bd_base;
1269 /* Reset SKB transmit buffers. */
1270 fep->skb_cur = fep->skb_dirty = 0;
1271 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
1272 if (fep->tx_skbuff[i]) {
1273 dev_kfree_skb_any(fep->tx_skbuff[i]);
1274 fep->tx_skbuff[i] = NULL;
1278 /* Enable MII mode */
1280 /* MII enable / FD enable */
1281 writel(OPT_FRAME_SIZE | 0x04, fep->hwp + FEC_R_CNTRL);
1282 writel(0x04, fep->hwp + FEC_X_CNTRL);
1284 /* MII enable / No Rcv on Xmit */
1285 writel(OPT_FRAME_SIZE | 0x06, fep->hwp + FEC_R_CNTRL);
1286 writel(0x0, fep->hwp + FEC_X_CNTRL);
1288 fep->full_duplex = duplex;
1291 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1294 * The phy interface and speed need to get configured
1295 * differently on enet-mac.
1297 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
1298 val = readl(fep->hwp + FEC_R_CNTRL);
1301 if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1307 if (fep->phy_dev && fep->phy_dev->speed == SPEED_100)
1312 writel(val, fep->hwp + FEC_R_CNTRL);
1314 #ifdef FEC_MIIGSK_ENR
1315 if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) {
1316 /* disable the gasket and wait */
1317 writel(0, fep->hwp + FEC_MIIGSK_ENR);
1318 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1322 * configure the gasket:
1323 * RMII, 50 MHz, no loopback, no echo
1325 writel(1, fep->hwp + FEC_MIIGSK_CFGR);
1327 /* re-enable the gasket */
1328 writel(2, fep->hwp + FEC_MIIGSK_ENR);
1333 /* And last, enable the transmit and receive processing */
1334 writel(2, fep->hwp + FEC_ECNTRL);
1335 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
1337 /* Enable interrupts we wish to service */
1338 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1342 fec_stop(struct net_device *ndev)
1344 struct fec_enet_private *fep = netdev_priv(ndev);
1346 /* We cannot expect a graceful transmit stop without link !!! */
1348 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1350 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1351 printk("fec_stop : Graceful transmit stop did not complete !\n");
1354 /* Whack a reset. We should wait for this. */
1355 writel(1, fep->hwp + FEC_ECNTRL);
1357 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1358 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1361 static int __devinit
1362 fec_probe(struct platform_device *pdev)
1364 struct fec_enet_private *fep;
1365 struct fec_platform_data *pdata;
1366 struct net_device *ndev;
1367 int i, irq, ret = 0;
1370 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1374 r = request_mem_region(r->start, resource_size(r), pdev->name);
1378 /* Init network device */
1379 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
1382 goto failed_alloc_etherdev;
1385 SET_NETDEV_DEV(ndev, &pdev->dev);
1387 /* setup board info structure */
1388 fep = netdev_priv(ndev);
1390 fep->hwp = ioremap(r->start, resource_size(r));
1395 goto failed_ioremap;
1398 platform_set_drvdata(pdev, ndev);
1400 pdata = pdev->dev.platform_data;
1402 fep->phy_interface = pdata->phy;
1404 /* This device has up to three irqs on some platforms */
1405 for (i = 0; i < 3; i++) {
1406 irq = platform_get_irq(pdev, i);
1409 ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev);
1412 irq = platform_get_irq(pdev, i);
1413 free_irq(irq, ndev);
1419 fep->clk = clk_get(&pdev->dev, "fec_clk");
1420 if (IS_ERR(fep->clk)) {
1421 ret = PTR_ERR(fep->clk);
1424 clk_enable(fep->clk);
1426 ret = fec_enet_init(ndev);
1430 ret = fec_enet_mii_init(pdev);
1432 goto failed_mii_init;
1434 /* Carrier starts down, phylib will bring it up */
1435 netif_carrier_off(ndev);
1437 ret = register_netdev(ndev);
1439 goto failed_register;
1444 fec_enet_mii_remove(fep);
1447 clk_disable(fep->clk);
1450 for (i = 0; i < 3; i++) {
1451 irq = platform_get_irq(pdev, i);
1453 free_irq(irq, ndev);
1459 failed_alloc_etherdev:
1460 release_mem_region(r->start, resource_size(r));
1465 static int __devexit
1466 fec_drv_remove(struct platform_device *pdev)
1468 struct net_device *ndev = platform_get_drvdata(pdev);
1469 struct fec_enet_private *fep = netdev_priv(ndev);
1472 platform_set_drvdata(pdev, NULL);
1475 fec_enet_mii_remove(fep);
1476 clk_disable(fep->clk);
1479 unregister_netdev(ndev);
1482 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1484 release_mem_region(r->start, resource_size(r));
1491 fec_suspend(struct device *dev)
1493 struct net_device *ndev = dev_get_drvdata(dev);
1494 struct fec_enet_private *fep = netdev_priv(ndev);
1496 if (netif_running(ndev)) {
1498 netif_device_detach(ndev);
1500 clk_disable(fep->clk);
1506 fec_resume(struct device *dev)
1508 struct net_device *ndev = dev_get_drvdata(dev);
1509 struct fec_enet_private *fep = netdev_priv(ndev);
1511 clk_enable(fep->clk);
1512 if (netif_running(ndev)) {
1513 fec_restart(ndev, fep->full_duplex);
1514 netif_device_attach(ndev);
1520 static const struct dev_pm_ops fec_pm_ops = {
1521 .suspend = fec_suspend,
1522 .resume = fec_resume,
1523 .freeze = fec_suspend,
1525 .poweroff = fec_suspend,
1526 .restore = fec_resume,
1530 static struct platform_driver fec_driver = {
1532 .name = DRIVER_NAME,
1533 .owner = THIS_MODULE,
1538 .id_table = fec_devtype,
1540 .remove = __devexit_p(fec_drv_remove),
1544 fec_enet_module_init(void)
1546 printk(KERN_INFO "FEC Ethernet Driver\n");
1548 return platform_driver_register(&fec_driver);
1552 fec_enet_cleanup(void)
1554 platform_driver_unregister(&fec_driver);
1557 module_exit(fec_enet_cleanup);
1558 module_init(fec_enet_module_init);
1560 MODULE_LICENSE("GPL");