drivers/net/forcedeth.c

   1 /*
   2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
   3  *
   4  * Note: This driver is a cleanroom reimplementation based on reverse
   5  *      engineered documentation written by Carl-Daniel Hailfinger
   6  *      and Andrew de Quincey.
   7  *
   8  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
   9  * trademarks of NVIDIA Corporation in the United States and other
  10  * countries.
  11  *
  12  * Copyright (C) 2003,4,5 Manfred Spraul
  13  * Copyright (C) 2004 Andrew de Quincey (wol support)
  14  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  15  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
  16  * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License as published by
  20  * the Free Software Foundation; either version 2 of the License, or
  21  * (at your option) any later version.
  22  *
  23  * This program is distributed in the hope that it will be useful,
  24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  26  * GNU General Public License for more details.
  27  *
  28  * You should have received a copy of the GNU General Public License
  29  * along with this program; if not, write to the Free Software
  30  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  31  *
  32  * Known bugs:
  33  * We suspect that on some hardware no TX done interrupts are generated.
  34  * This means recovery from netif_stop_queue only happens if the hw timer
  35  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
  36  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
  37  * If your hardware reliably generates tx done interrupts, then you can remove
  38  * DEV_NEED_TIMERIRQ from the driver_data flags.
  39  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
  40  * superfluous timer interrupts from the nic.
  41  */
  42 #define FORCEDETH_VERSION               "0.64"
  43 #define DRV_NAME                        "forcedeth"
  44
  45 #include <linux/module.h>
  46 #include <linux/types.h>
  47 #include <linux/pci.h>
  48 #include <linux/interrupt.h>
  49 #include <linux/netdevice.h>
  50 #include <linux/etherdevice.h>
  51 #include <linux/delay.h>
  52 #include <linux/sched.h>
  53 #include <linux/spinlock.h>
  54 #include <linux/ethtool.h>
  55 #include <linux/timer.h>
  56 #include <linux/skbuff.h>
  57 #include <linux/mii.h>
  58 #include <linux/random.h>
  59 #include <linux/init.h>
  60 #include <linux/if_vlan.h>
  61 #include <linux/dma-mapping.h>
  62 #include <linux/slab.h>
  63
  64 #include <asm/irq.h>
  65 #include <asm/io.h>
  66 #include <asm/uaccess.h>
  67 #include <asm/system.h>
  68
  69 #if 0
  70 #define dprintk                 printk
  71 #else
  72 #define dprintk(x...)           do { } while (0)
  73 #endif
  74
  75 #define TX_WORK_PER_LOOP  64
  76 #define RX_WORK_PER_LOOP  64
  77
  78 /*
  79  * Hardware access:
  80  */
  81
  82 #define DEV_NEED_TIMERIRQ          0x0000001  /* set the timer irq flag in the irq mask */
  83 #define DEV_NEED_LINKTIMER         0x0000002  /* poll link settings. Relies on the timer irq */
  84 #define DEV_HAS_LARGEDESC          0x0000004  /* device supports jumbo frames and needs packet format 2 */
  85 #define DEV_HAS_HIGH_DMA           0x0000008  /* device supports 64bit dma */
  86 #define DEV_HAS_CHECKSUM           0x0000010  /* device supports tx and rx checksum offloads */
  87 #define DEV_HAS_VLAN               0x0000020  /* device supports vlan tagging and striping */
  88 #define DEV_HAS_MSI                0x0000040  /* device supports MSI */
  89 #define DEV_HAS_MSI_X              0x0000080  /* device supports MSI-X */
  90 #define DEV_HAS_POWER_CNTRL        0x0000100  /* device supports power savings */
  91 #define DEV_HAS_STATISTICS_V1      0x0000200  /* device supports hw statistics version 1 */
  92 #define DEV_HAS_STATISTICS_V2      0x0000400  /* device supports hw statistics version 2 */
  93 #define DEV_HAS_STATISTICS_V3      0x0000800  /* device supports hw statistics version 3 */
  94 #define DEV_HAS_STATISTICS_V12     0x0000600  /* device supports hw statistics version 1 and 2 */
  95 #define DEV_HAS_STATISTICS_V123    0x0000e00  /* device supports hw statistics version 1, 2, and 3 */
  96 #define DEV_HAS_TEST_EXTENDED      0x0001000  /* device supports extended diagnostic test */
  97 #define DEV_HAS_MGMT_UNIT          0x0002000  /* device supports management unit */
  98 #define DEV_HAS_CORRECT_MACADDR    0x0004000  /* device supports correct mac address order */
  99 #define DEV_HAS_COLLISION_FIX      0x0008000  /* device supports tx collision fix */
 100 #define DEV_HAS_PAUSEFRAME_TX_V1   0x0010000  /* device supports tx pause frames version 1 */
 101 #define DEV_HAS_PAUSEFRAME_TX_V2   0x0020000  /* device supports tx pause frames version 2 */
 102 #define DEV_HAS_PAUSEFRAME_TX_V3   0x0040000  /* device supports tx pause frames version 3 */
 103 #define DEV_NEED_TX_LIMIT          0x0080000  /* device needs to limit tx */
 104 #define DEV_NEED_TX_LIMIT2         0x0180000  /* device needs to limit tx, expect for some revs */
 105 #define DEV_HAS_GEAR_MODE          0x0200000  /* device supports gear mode */
 106 #define DEV_NEED_PHY_INIT_FIX      0x0400000  /* device needs specific phy workaround */
 107 #define DEV_NEED_LOW_POWER_FIX     0x0800000  /* device needs special power up workaround */
 108 #define DEV_NEED_MSI_FIX           0x1000000  /* device needs msi workaround */
 109
 110 enum {
 111         NvRegIrqStatus = 0x000,
 112 #define NVREG_IRQSTAT_MIIEVENT  0x040
 113 #define NVREG_IRQSTAT_MASK              0x83ff
 114         NvRegIrqMask = 0x004,
 115 #define NVREG_IRQ_RX_ERROR              0x0001
 116 #define NVREG_IRQ_RX                    0x0002
 117 #define NVREG_IRQ_RX_NOBUF              0x0004
 118 #define NVREG_IRQ_TX_ERR                0x0008
 119 #define NVREG_IRQ_TX_OK                 0x0010
 120 #define NVREG_IRQ_TIMER                 0x0020
 121 #define NVREG_IRQ_LINK                  0x0040
 122 #define NVREG_IRQ_RX_FORCED             0x0080
 123 #define NVREG_IRQ_TX_FORCED             0x0100
 124 #define NVREG_IRQ_RECOVER_ERROR         0x8200
 125 #define NVREG_IRQMASK_THROUGHPUT        0x00df
 126 #define NVREG_IRQMASK_CPU               0x0060
 127 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
 128 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
 129 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
 130
 131         NvRegUnknownSetupReg6 = 0x008,
 132 #define NVREG_UNKSETUP6_VAL             3
 133
 134 /*
 135  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
 136  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
 137  */
 138         NvRegPollingInterval = 0x00c,
 139 #define NVREG_POLL_DEFAULT_THROUGHPUT   65535 /* backup tx cleanup if loop max reached */
 140 #define NVREG_POLL_DEFAULT_CPU  13
 141         NvRegMSIMap0 = 0x020,
 142         NvRegMSIMap1 = 0x024,
 143         NvRegMSIIrqMask = 0x030,
 144 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
 145         NvRegMisc1 = 0x080,
 146 #define NVREG_MISC1_PAUSE_TX    0x01
 147 #define NVREG_MISC1_HD          0x02
 148 #define NVREG_MISC1_FORCE       0x3b0f3c
 149
 150         NvRegMacReset = 0x34,
 151 #define NVREG_MAC_RESET_ASSERT  0x0F3
 152         NvRegTransmitterControl = 0x084,
 153 #define NVREG_XMITCTL_START     0x01
 154 #define NVREG_XMITCTL_MGMT_ST   0x40000000
 155 #define NVREG_XMITCTL_SYNC_MASK         0x000f0000
 156 #define NVREG_XMITCTL_SYNC_NOT_READY    0x0
 157 #define NVREG_XMITCTL_SYNC_PHY_INIT     0x00040000
 158 #define NVREG_XMITCTL_MGMT_SEMA_MASK    0x00000f00
 159 #define NVREG_XMITCTL_MGMT_SEMA_FREE    0x0
 160 #define NVREG_XMITCTL_HOST_SEMA_MASK    0x0000f000
 161 #define NVREG_XMITCTL_HOST_SEMA_ACQ     0x0000f000
 162 #define NVREG_XMITCTL_HOST_LOADED       0x00004000
 163 #define NVREG_XMITCTL_TX_PATH_EN        0x01000000
 164 #define NVREG_XMITCTL_DATA_START        0x00100000
 165 #define NVREG_XMITCTL_DATA_READY        0x00010000
 166 #define NVREG_XMITCTL_DATA_ERROR        0x00020000
 167         NvRegTransmitterStatus = 0x088,
 168 #define NVREG_XMITSTAT_BUSY     0x01
 169
 170         NvRegPacketFilterFlags = 0x8c,
 171 #define NVREG_PFF_PAUSE_RX      0x08
 172 #define NVREG_PFF_ALWAYS        0x7F0000
 173 #define NVREG_PFF_PROMISC       0x80
 174 #define NVREG_PFF_MYADDR        0x20
 175 #define NVREG_PFF_LOOPBACK      0x10
 176
 177         NvRegOffloadConfig = 0x90,
 178 #define NVREG_OFFLOAD_HOMEPHY   0x601
 179 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
 180         NvRegReceiverControl = 0x094,
 181 #define NVREG_RCVCTL_START      0x01
 182 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
 183         NvRegReceiverStatus = 0x98,
 184 #define NVREG_RCVSTAT_BUSY      0x01
 185
 186         NvRegSlotTime = 0x9c,
 187 #define NVREG_SLOTTIME_LEGBF_ENABLED    0x80000000
 188 #define NVREG_SLOTTIME_10_100_FULL      0x00007f00
 189 #define NVREG_SLOTTIME_1000_FULL        0x0003ff00
 190 #define NVREG_SLOTTIME_HALF             0x0000ff00
 191 #define NVREG_SLOTTIME_DEFAULT          0x00007f00
 192 #define NVREG_SLOTTIME_MASK             0x000000ff
 193
 194         NvRegTxDeferral = 0xA0,
 195 #define NVREG_TX_DEFERRAL_DEFAULT               0x15050f
 196 #define NVREG_TX_DEFERRAL_RGMII_10_100          0x16070f
 197 #define NVREG_TX_DEFERRAL_RGMII_1000            0x14050f
 198 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10      0x16190f
 199 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100     0x16300f
 200 #define NVREG_TX_DEFERRAL_MII_STRETCH           0x152000
 201         NvRegRxDeferral = 0xA4,
 202 #define NVREG_RX_DEFERRAL_DEFAULT       0x16
 203         NvRegMacAddrA = 0xA8,
 204         NvRegMacAddrB = 0xAC,
 205         NvRegMulticastAddrA = 0xB0,
 206 #define NVREG_MCASTADDRA_FORCE  0x01
 207         NvRegMulticastAddrB = 0xB4,
 208         NvRegMulticastMaskA = 0xB8,
 209 #define NVREG_MCASTMASKA_NONE           0xffffffff
 210         NvRegMulticastMaskB = 0xBC,
 211 #define NVREG_MCASTMASKB_NONE           0xffff
 212
 213         NvRegPhyInterface = 0xC0,
 214 #define PHY_RGMII               0x10000000
 215         NvRegBackOffControl = 0xC4,
 216 #define NVREG_BKOFFCTRL_DEFAULT                 0x70000000
 217 #define NVREG_BKOFFCTRL_SEED_MASK               0x000003ff
 218 #define NVREG_BKOFFCTRL_SELECT                  24
 219 #define NVREG_BKOFFCTRL_GEAR                    12
 220
 221         NvRegTxRingPhysAddr = 0x100,
 222         NvRegRxRingPhysAddr = 0x104,
 223         NvRegRingSizes = 0x108,
 224 #define NVREG_RINGSZ_TXSHIFT 0
 225 #define NVREG_RINGSZ_RXSHIFT 16
 226         NvRegTransmitPoll = 0x10c,
 227 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
 228         NvRegLinkSpeed = 0x110,
 229 #define NVREG_LINKSPEED_FORCE 0x10000
 230 #define NVREG_LINKSPEED_10      1000
 231 #define NVREG_LINKSPEED_100     100
 232 #define NVREG_LINKSPEED_1000    50
 233 #define NVREG_LINKSPEED_MASK    (0xFFF)
 234         NvRegUnknownSetupReg5 = 0x130,
 235 #define NVREG_UNKSETUP5_BIT31   (1<<31)
 236         NvRegTxWatermark = 0x13c,
 237 #define NVREG_TX_WM_DESC1_DEFAULT       0x0200010
 238 #define NVREG_TX_WM_DESC2_3_DEFAULT     0x1e08000
 239 #define NVREG_TX_WM_DESC2_3_1000        0xfe08000
 240         NvRegTxRxControl = 0x144,
 241 #define NVREG_TXRXCTL_KICK      0x0001
 242 #define NVREG_TXRXCTL_BIT1      0x0002
 243 #define NVREG_TXRXCTL_BIT2      0x0004
 244 #define NVREG_TXRXCTL_IDLE      0x0008
 245 #define NVREG_TXRXCTL_RESET     0x0010
 246 #define NVREG_TXRXCTL_RXCHECK   0x0400
 247 #define NVREG_TXRXCTL_DESC_1    0
 248 #define NVREG_TXRXCTL_DESC_2    0x002100
 249 #define NVREG_TXRXCTL_DESC_3    0xc02200
 250 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
 251 #define NVREG_TXRXCTL_VLANINS   0x00080
 252         NvRegTxRingPhysAddrHigh = 0x148,
 253         NvRegRxRingPhysAddrHigh = 0x14C,
 254         NvRegTxPauseFrame = 0x170,
 255 #define NVREG_TX_PAUSEFRAME_DISABLE     0x0fff0080
 256 #define NVREG_TX_PAUSEFRAME_ENABLE_V1   0x01800010
 257 #define NVREG_TX_PAUSEFRAME_ENABLE_V2   0x056003f0
 258 #define NVREG_TX_PAUSEFRAME_ENABLE_V3   0x09f00880
 259         NvRegTxPauseFrameLimit = 0x174,
 260 #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
 261         NvRegMIIStatus = 0x180,
 262 #define NVREG_MIISTAT_ERROR             0x0001
 263 #define NVREG_MIISTAT_LINKCHANGE        0x0008
 264 #define NVREG_MIISTAT_MASK_RW           0x0007
 265 #define NVREG_MIISTAT_MASK_ALL          0x000f
 266         NvRegMIIMask = 0x184,
 267 #define NVREG_MII_LINKCHANGE            0x0008
 268
 269         NvRegAdapterControl = 0x188,
 270 #define NVREG_ADAPTCTL_START    0x02
 271 #define NVREG_ADAPTCTL_LINKUP   0x04
 272 #define NVREG_ADAPTCTL_PHYVALID 0x40000
 273 #define NVREG_ADAPTCTL_RUNNING  0x100000
 274 #define NVREG_ADAPTCTL_PHYSHIFT 24
 275         NvRegMIISpeed = 0x18c,
 276 #define NVREG_MIISPEED_BIT8     (1<<8)
 277 #define NVREG_MIIDELAY  5
 278         NvRegMIIControl = 0x190,
 279 #define NVREG_MIICTL_INUSE      0x08000
 280 #define NVREG_MIICTL_WRITE      0x00400
 281 #define NVREG_MIICTL_ADDRSHIFT  5
 282         NvRegMIIData = 0x194,
 283         NvRegTxUnicast = 0x1a0,
 284         NvRegTxMulticast = 0x1a4,
 285         NvRegTxBroadcast = 0x1a8,
 286         NvRegWakeUpFlags = 0x200,
 287 #define NVREG_WAKEUPFLAGS_VAL           0x7770
 288 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
 289 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
 290 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
 291 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
 292 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
 293 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
 294 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
 295 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
 296 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
 297 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
 298
 299         NvRegMgmtUnitGetVersion = 0x204,
 300 #define NVREG_MGMTUNITGETVERSION        0x01
 301         NvRegMgmtUnitVersion = 0x208,
 302 #define NVREG_MGMTUNITVERSION           0x08
 303         NvRegPowerCap = 0x268,
 304 #define NVREG_POWERCAP_D3SUPP   (1<<30)
 305 #define NVREG_POWERCAP_D2SUPP   (1<<26)
 306 #define NVREG_POWERCAP_D1SUPP   (1<<25)
 307         NvRegPowerState = 0x26c,
 308 #define NVREG_POWERSTATE_POWEREDUP      0x8000
 309 #define NVREG_POWERSTATE_VALID          0x0100
 310 #define NVREG_POWERSTATE_MASK           0x0003
 311 #define NVREG_POWERSTATE_D0             0x0000
 312 #define NVREG_POWERSTATE_D1             0x0001
 313 #define NVREG_POWERSTATE_D2             0x0002
 314 #define NVREG_POWERSTATE_D3             0x0003
 315         NvRegMgmtUnitControl = 0x278,
 316 #define NVREG_MGMTUNITCONTROL_INUSE     0x20000
 317         NvRegTxCnt = 0x280,
 318         NvRegTxZeroReXmt = 0x284,
 319         NvRegTxOneReXmt = 0x288,
 320         NvRegTxManyReXmt = 0x28c,
 321         NvRegTxLateCol = 0x290,
 322         NvRegTxUnderflow = 0x294,
 323         NvRegTxLossCarrier = 0x298,
 324         NvRegTxExcessDef = 0x29c,
 325         NvRegTxRetryErr = 0x2a0,
 326         NvRegRxFrameErr = 0x2a4,
 327         NvRegRxExtraByte = 0x2a8,
 328         NvRegRxLateCol = 0x2ac,
 329         NvRegRxRunt = 0x2b0,
 330         NvRegRxFrameTooLong = 0x2b4,
 331         NvRegRxOverflow = 0x2b8,
 332         NvRegRxFCSErr = 0x2bc,
 333         NvRegRxFrameAlignErr = 0x2c0,
 334         NvRegRxLenErr = 0x2c4,
 335         NvRegRxUnicast = 0x2c8,
 336         NvRegRxMulticast = 0x2cc,
 337         NvRegRxBroadcast = 0x2d0,
 338         NvRegTxDef = 0x2d4,
 339         NvRegTxFrame = 0x2d8,
 340         NvRegRxCnt = 0x2dc,
 341         NvRegTxPause = 0x2e0,
 342         NvRegRxPause = 0x2e4,
 343         NvRegRxDropFrame = 0x2e8,
 344         NvRegVlanControl = 0x300,
 345 #define NVREG_VLANCONTROL_ENABLE        0x2000
 346         NvRegMSIXMap0 = 0x3e0,
 347         NvRegMSIXMap1 = 0x3e4,
 348         NvRegMSIXIrqStatus = 0x3f0,
 349
 350         NvRegPowerState2 = 0x600,
 351 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F15
 352 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
 353 #define NVREG_POWERSTATE2_PHY_RESET             0x0004
 354 #define NVREG_POWERSTATE2_GATE_CLOCKS           0x0F00
 355 };
 356
 357 /* Big endian: should work, but is untested */
 358 struct ring_desc {
 359         __le32 buf;
 360         __le32 flaglen;
 361 };
 362
 363 struct ring_desc_ex {
 364         __le32 bufhigh;
 365         __le32 buflow;
 366         __le32 txvlan;
 367         __le32 flaglen;
 368 };
 369
 370 union ring_type {
 371         struct ring_desc* orig;
 372         struct ring_desc_ex* ex;
 373 };
 374
 375 #define FLAG_MASK_V1 0xffff0000
 376 #define FLAG_MASK_V2 0xffffc000
 377 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
 378 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
 379
 380 #define NV_TX_LASTPACKET        (1<<16)
 381 #define NV_TX_RETRYERROR        (1<<19)
 382 #define NV_TX_RETRYCOUNT_MASK   (0xF<<20)
 383 #define NV_TX_FORCED_INTERRUPT  (1<<24)
 384 #define NV_TX_DEFERRED          (1<<26)
 385 #define NV_TX_CARRIERLOST       (1<<27)
 386 #define NV_TX_LATECOLLISION     (1<<28)
 387 #define NV_TX_UNDERFLOW         (1<<29)
 388 #define NV_TX_ERROR             (1<<30)
 389 #define NV_TX_VALID             (1<<31)
 390
 391 #define NV_TX2_LASTPACKET       (1<<29)
 392 #define NV_TX2_RETRYERROR       (1<<18)
 393 #define NV_TX2_RETRYCOUNT_MASK  (0xF<<19)
 394 #define NV_TX2_FORCED_INTERRUPT (1<<30)
 395 #define NV_TX2_DEFERRED         (1<<25)
 396 #define NV_TX2_CARRIERLOST      (1<<26)
 397 #define NV_TX2_LATECOLLISION    (1<<27)
 398 #define NV_TX2_UNDERFLOW        (1<<28)
 399 /* error and valid are the same for both */
 400 #define NV_TX2_ERROR            (1<<30)
 401 #define NV_TX2_VALID            (1<<31)
 402 #define NV_TX2_TSO              (1<<28)
 403 #define NV_TX2_TSO_SHIFT        14
 404 #define NV_TX2_TSO_MAX_SHIFT    14
 405 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
 406 #define NV_TX2_CHECKSUM_L3      (1<<27)
 407 #define NV_TX2_CHECKSUM_L4      (1<<26)
 408
 409 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
 410
 411 #define NV_RX_DESCRIPTORVALID   (1<<16)
 412 #define NV_RX_MISSEDFRAME       (1<<17)
 413 #define NV_RX_SUBSTRACT1        (1<<18)
 414 #define NV_RX_ERROR1            (1<<23)
 415 #define NV_RX_ERROR2            (1<<24)
 416 #define NV_RX_ERROR3            (1<<25)
 417 #define NV_RX_ERROR4            (1<<26)
 418 #define NV_RX_CRCERR            (1<<27)
 419 #define NV_RX_OVERFLOW          (1<<28)
 420 #define NV_RX_FRAMINGERR        (1<<29)
 421 #define NV_RX_ERROR             (1<<30)
 422 #define NV_RX_AVAIL             (1<<31)
 423 #define NV_RX_ERROR_MASK        (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
 424
 425 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
 426 #define NV_RX2_CHECKSUM_IP      (0x10000000)
 427 #define NV_RX2_CHECKSUM_IP_TCP  (0x14000000)
 428 #define NV_RX2_CHECKSUM_IP_UDP  (0x18000000)
 429 #define NV_RX2_DESCRIPTORVALID  (1<<29)
 430 #define NV_RX2_SUBSTRACT1       (1<<25)
 431 #define NV_RX2_ERROR1           (1<<18)
 432 #define NV_RX2_ERROR2           (1<<19)
 433 #define NV_RX2_ERROR3           (1<<20)
 434 #define NV_RX2_ERROR4           (1<<21)
 435 #define NV_RX2_CRCERR           (1<<22)
 436 #define NV_RX2_OVERFLOW         (1<<23)
 437 #define NV_RX2_FRAMINGERR       (1<<24)
 438 /* error and avail are the same for both */
 439 #define NV_RX2_ERROR            (1<<30)
 440 #define NV_RX2_AVAIL            (1<<31)
 441 #define NV_RX2_ERROR_MASK       (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
 442
 443 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
 444 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
 445
 446 /* Miscelaneous hardware related defines: */
 447 #define NV_PCI_REGSZ_VER1       0x270
 448 #define NV_PCI_REGSZ_VER2       0x2d4
 449 #define NV_PCI_REGSZ_VER3       0x604
 450 #define NV_PCI_REGSZ_MAX        0x604
 451
 452 /* various timeout delays: all in usec */
 453 #define NV_TXRX_RESET_DELAY     4
 454 #define NV_TXSTOP_DELAY1        10
 455 #define NV_TXSTOP_DELAY1MAX     500000
 456 #define NV_TXSTOP_DELAY2        100
 457 #define NV_RXSTOP_DELAY1        10
 458 #define NV_RXSTOP_DELAY1MAX     500000
 459 #define NV_RXSTOP_DELAY2        100
 460 #define NV_SETUP5_DELAY         5
 461 #define NV_SETUP5_DELAYMAX      50000
 462 #define NV_POWERUP_DELAY        5
 463 #define NV_POWERUP_DELAYMAX     5000
 464 #define NV_MIIBUSY_DELAY        50
 465 #define NV_MIIPHY_DELAY 10
 466 #define NV_MIIPHY_DELAYMAX      10000
 467 #define NV_MAC_RESET_DELAY      64
 468
 469 #define NV_WAKEUPPATTERNS       5
 470 #define NV_WAKEUPMASKENTRIES    4
 471
 472 /* General driver defaults */
 473 #define NV_WATCHDOG_TIMEO       (5*HZ)
 474
 475 #define RX_RING_DEFAULT         512
 476 #define TX_RING_DEFAULT         256
 477 #define RX_RING_MIN             128
 478 #define TX_RING_MIN             64
 479 #define RING_MAX_DESC_VER_1     1024
 480 #define RING_MAX_DESC_VER_2_3   16384
 481
 482 /* rx/tx mac addr + type + vlan + align + slack*/
 483 #define NV_RX_HEADERS           (64)
 484 /* even more slack. */
 485 #define NV_RX_ALLOC_PAD         (64)
 486
 487 /* maximum mtu size */
 488 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
 489 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
 490
 491 #define OOM_REFILL      (1+HZ/20)
 492 #define POLL_WAIT       (1+HZ/100)
 493 #define LINK_TIMEOUT    (3*HZ)
 494 #define STATS_INTERVAL  (10*HZ)
 495
 496 /*
 497  * desc_ver values:
 498  * The nic supports three different descriptor types:
 499  * - DESC_VER_1: Original
 500  * - DESC_VER_2: support for jumbo frames.
 501  * - DESC_VER_3: 64-bit format.
 502  */
 503 #define DESC_VER_1      1
 504 #define DESC_VER_2      2
 505 #define DESC_VER_3      3
 506
 507 /* PHY defines */
 508 #define PHY_OUI_MARVELL         0x5043
 509 #define PHY_OUI_CICADA          0x03f1
 510 #define PHY_OUI_VITESSE         0x01c1
 511 #define PHY_OUI_REALTEK         0x0732
 512 #define PHY_OUI_REALTEK2        0x0020
 513 #define PHYID1_OUI_MASK 0x03ff
 514 #define PHYID1_OUI_SHFT 6
 515 #define PHYID2_OUI_MASK 0xfc00
 516 #define PHYID2_OUI_SHFT 10
 517 #define PHYID2_MODEL_MASK               0x03f0
 518 #define PHY_MODEL_REALTEK_8211          0x0110
 519 #define PHY_REV_MASK                    0x0001
 520 #define PHY_REV_REALTEK_8211B           0x0000
 521 #define PHY_REV_REALTEK_8211C           0x0001
 522 #define PHY_MODEL_REALTEK_8201          0x0200
 523 #define PHY_MODEL_MARVELL_E3016         0x0220
 524 #define PHY_MARVELL_E3016_INITMASK      0x0300
 525 #define PHY_CICADA_INIT1        0x0f000
 526 #define PHY_CICADA_INIT2        0x0e00
 527 #define PHY_CICADA_INIT3        0x01000
 528 #define PHY_CICADA_INIT4        0x0200
 529 #define PHY_CICADA_INIT5        0x0004
 530 #define PHY_CICADA_INIT6        0x02000
 531 #define PHY_VITESSE_INIT_REG1   0x1f
 532 #define PHY_VITESSE_INIT_REG2   0x10
 533 #define PHY_VITESSE_INIT_REG3   0x11
 534 #define PHY_VITESSE_INIT_REG4   0x12
 535 #define PHY_VITESSE_INIT_MSK1   0xc
 536 #define PHY_VITESSE_INIT_MSK2   0x0180
 537 #define PHY_VITESSE_INIT1       0x52b5
 538 #define PHY_VITESSE_INIT2       0xaf8a
 539 #define PHY_VITESSE_INIT3       0x8
 540 #define PHY_VITESSE_INIT4       0x8f8a
 541 #define PHY_VITESSE_INIT5       0xaf86
 542 #define PHY_VITESSE_INIT6       0x8f86
 543 #define PHY_VITESSE_INIT7       0xaf82
 544 #define PHY_VITESSE_INIT8       0x0100
 545 #define PHY_VITESSE_INIT9       0x8f82
 546 #define PHY_VITESSE_INIT10      0x0
 547 #define PHY_REALTEK_INIT_REG1   0x1f
 548 #define PHY_REALTEK_INIT_REG2   0x19
 549 #define PHY_REALTEK_INIT_REG3   0x13
 550 #define PHY_REALTEK_INIT_REG4   0x14
 551 #define PHY_REALTEK_INIT_REG5   0x18
 552 #define PHY_REALTEK_INIT_REG6   0x11
 553 #define PHY_REALTEK_INIT_REG7   0x01
 554 #define PHY_REALTEK_INIT1       0x0000
 555 #define PHY_REALTEK_INIT2       0x8e00
 556 #define PHY_REALTEK_INIT3       0x0001
 557 #define PHY_REALTEK_INIT4       0xad17
 558 #define PHY_REALTEK_INIT5       0xfb54
 559 #define PHY_REALTEK_INIT6       0xf5c7
 560 #define PHY_REALTEK_INIT7       0x1000
 561 #define PHY_REALTEK_INIT8       0x0003
 562 #define PHY_REALTEK_INIT9       0x0008
 563 #define PHY_REALTEK_INIT10      0x0005
 564 #define PHY_REALTEK_INIT11      0x0200
 565 #define PHY_REALTEK_INIT_MSK1   0x0003
 566
 567 #define PHY_GIGABIT     0x0100
 568
 569 #define PHY_TIMEOUT     0x1
 570 #define PHY_ERROR       0x2
 571
 572 #define PHY_100 0x1
 573 #define PHY_1000        0x2
 574 #define PHY_HALF        0x100
 575
 576 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
 577 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
 578 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
 579 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
 580 #define NV_PAUSEFRAME_RX_REQ     0x0010
 581 #define NV_PAUSEFRAME_TX_REQ     0x0020
 582 #define NV_PAUSEFRAME_AUTONEG    0x0040
 583
 584 /* MSI/MSI-X defines */
 585 #define NV_MSI_X_MAX_VECTORS  8
 586 #define NV_MSI_X_VECTORS_MASK 0x000f
 587 #define NV_MSI_CAPABLE        0x0010
 588 #define NV_MSI_X_CAPABLE      0x0020
 589 #define NV_MSI_ENABLED        0x0040
 590 #define NV_MSI_X_ENABLED      0x0080
 591
 592 #define NV_MSI_X_VECTOR_ALL   0x0
 593 #define NV_MSI_X_VECTOR_RX    0x0
 594 #define NV_MSI_X_VECTOR_TX    0x1
 595 #define NV_MSI_X_VECTOR_OTHER 0x2
 596
 597 #define NV_MSI_PRIV_OFFSET 0x68
 598 #define NV_MSI_PRIV_VALUE  0xffffffff
 599
 600 #define NV_RESTART_TX         0x1
 601 #define NV_RESTART_RX         0x2
 602
 603 #define NV_TX_LIMIT_COUNT     16
 604
 605 #define NV_DYNAMIC_THRESHOLD        4
 606 #define NV_DYNAMIC_MAX_QUIET_COUNT  2048
 607
 608 /* statistics */
 609 struct nv_ethtool_str {
 610         char name[ETH_GSTRING_LEN];
 611 };
 612
 613 static const struct nv_ethtool_str nv_estats_str[] = {
 614         { "tx_bytes" },
 615         { "tx_zero_rexmt" },
 616         { "tx_one_rexmt" },
 617         { "tx_many_rexmt" },
 618         { "tx_late_collision" },
 619         { "tx_fifo_errors" },
 620         { "tx_carrier_errors" },
 621         { "tx_excess_deferral" },
 622         { "tx_retry_error" },
 623         { "rx_frame_error" },
 624         { "rx_extra_byte" },
 625         { "rx_late_collision" },
 626         { "rx_runt" },
 627         { "rx_frame_too_long" },
 628         { "rx_over_errors" },
 629         { "rx_crc_errors" },
 630         { "rx_frame_align_error" },
 631         { "rx_length_error" },
 632         { "rx_unicast" },
 633         { "rx_multicast" },
 634         { "rx_broadcast" },
 635         { "rx_packets" },
 636         { "rx_errors_total" },
 637         { "tx_errors_total" },
 638
 639         /* version 2 stats */
 640         { "tx_deferral" },
 641         { "tx_packets" },
 642         { "rx_bytes" },
 643         { "tx_pause" },
 644         { "rx_pause" },
 645         { "rx_drop_frame" },
 646
 647         /* version 3 stats */
 648         { "tx_unicast" },
 649         { "tx_multicast" },
 650         { "tx_broadcast" }
 651 };
 652
 653 struct nv_ethtool_stats {
 654         u64 tx_bytes;
 655         u64 tx_zero_rexmt;
 656         u64 tx_one_rexmt;
 657         u64 tx_many_rexmt;
 658         u64 tx_late_collision;
 659         u64 tx_fifo_errors;
 660         u64 tx_carrier_errors;
 661         u64 tx_excess_deferral;
 662         u64 tx_retry_error;
 663         u64 rx_frame_error;
 664         u64 rx_extra_byte;
 665         u64 rx_late_collision;
 666         u64 rx_runt;
 667         u64 rx_frame_too_long;
 668         u64 rx_over_errors;
 669         u64 rx_crc_errors;
 670         u64 rx_frame_align_error;
 671         u64 rx_length_error;
 672         u64 rx_unicast;
 673         u64 rx_multicast;
 674         u64 rx_broadcast;
 675         u64 rx_packets;
 676         u64 rx_errors_total;
 677         u64 tx_errors_total;
 678
 679         /* version 2 stats */
 680         u64 tx_deferral;
 681         u64 tx_packets;
 682         u64 rx_bytes;
 683         u64 tx_pause;
 684         u64 rx_pause;
 685         u64 rx_drop_frame;
 686
 687         /* version 3 stats */
 688         u64 tx_unicast;
 689         u64 tx_multicast;
 690         u64 tx_broadcast;
 691 };
 692
 693 #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
 694 #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
 695 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
 696
 697 /* diagnostics */
 698 #define NV_TEST_COUNT_BASE 3
 699 #define NV_TEST_COUNT_EXTENDED 4
 700
 701 static const struct nv_ethtool_str nv_etests_str[] = {
 702         { "link      (online/offline)" },
 703         { "register  (offline)       " },
 704         { "interrupt (offline)       " },
 705         { "loopback  (offline)       " }
 706 };
 707
 708 struct register_test {
 709         __u32 reg;
 710         __u32 mask;
 711 };
 712
 713 static const struct register_test nv_registers_test[] = {
 714         { NvRegUnknownSetupReg6, 0x01 },
 715         { NvRegMisc1, 0x03c },
 716         { NvRegOffloadConfig, 0x03ff },
 717         { NvRegMulticastAddrA, 0xffffffff },
 718         { NvRegTxWatermark, 0x0ff },
 719         { NvRegWakeUpFlags, 0x07777 },
 720         { 0,0 }
 721 };
 722
 723 struct nv_skb_map {
 724         struct sk_buff *skb;
 725         dma_addr_t dma;
 726         unsigned int dma_len:31;
 727         unsigned int dma_single:1;
 728         struct ring_desc_ex *first_tx_desc;
 729         struct nv_skb_map *next_tx_ctx;
 730 };
 731
 732 /*
 733  * SMP locking:
 734  * All hardware access under netdev_priv(dev)->lock, except the performance
 735  * critical parts:
 736  * - rx is (pseudo-) lockless: it relies on the single-threading provided
 737  *      by the arch code for interrupts.
 738  * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
 739  *      needs netdev_priv(dev)->lock :-(
 740  * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
 741  */
 742
 743 /* in dev: base, irq */
 744 struct fe_priv {
 745         spinlock_t lock;
 746
 747         struct net_device *dev;
 748         struct napi_struct napi;
 749
 750         /* General data:
 751          * Locking: spin_lock(&np->lock); */
 752         struct nv_ethtool_stats estats;
 753         int in_shutdown;
 754         u32 linkspeed;
 755         int duplex;
 756         int autoneg;
 757         int fixed_mode;
 758         int phyaddr;
 759         int wolenabled;
 760         unsigned int phy_oui;
 761         unsigned int phy_model;
 762         unsigned int phy_rev;
 763         u16 gigabit;
 764         int intr_test;
 765         int recover_error;
 766         int quiet_count;
 767
 768         /* General data: RO fields */
 769         dma_addr_t ring_addr;
 770         struct pci_dev *pci_dev;
 771         u32 orig_mac[2];
 772         u32 events;
 773         u32 irqmask;
 774         u32 desc_ver;
 775         u32 txrxctl_bits;
 776         u32 vlanctl_bits;
 777         u32 driver_data;
 778         u32 device_id;
 779         u32 register_size;
 780         int rx_csum;
 781         u32 mac_in_use;
 782         int mgmt_version;
 783         int mgmt_sema;
 784
 785         void __iomem *base;
 786
 787         /* rx specific fields.
 788          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 789          */
 790         union ring_type get_rx, put_rx, first_rx, last_rx;
 791         struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
 792         struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
 793         struct nv_skb_map *rx_skb;
 794
 795         union ring_type rx_ring;
 796         unsigned int rx_buf_sz;
 797         unsigned int pkt_limit;
 798         struct timer_list oom_kick;
 799         struct timer_list nic_poll;
 800         struct timer_list stats_poll;
 801         u32 nic_poll_irq;
 802         int rx_ring_size;
 803
 804         /* media detection workaround.
 805          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 806          */
 807         int need_linktimer;
 808         unsigned long link_timeout;
 809         /*
 810          * tx specific fields.
 811          */
 812         union ring_type get_tx, put_tx, first_tx, last_tx;
 813         struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
 814         struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
 815         struct nv_skb_map *tx_skb;
 816
 817         union ring_type tx_ring;
 818         u32 tx_flags;
 819         int tx_ring_size;
 820         int tx_limit;
 821         u32 tx_pkts_in_progress;
 822         struct nv_skb_map *tx_change_owner;
 823         struct nv_skb_map *tx_end_flip;
 824         int tx_stop;
 825
 826         /* vlan fields */
 827         struct vlan_group *vlangrp;
 828
 829         /* msi/msi-x fields */
 830         u32 msi_flags;
 831         struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
 832
 833         /* flow control */
 834         u32 pause_flags;
 835
 836         /* power saved state */
 837         u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
 838
 839         /* for different msi-x irq type */
 840         char name_rx[IFNAMSIZ + 3];       /* -rx    */
 841         char name_tx[IFNAMSIZ + 3];       /* -tx    */
 842         char name_other[IFNAMSIZ + 6];    /* -other */
 843 };
 844
 845 /*
 846  * Maximum number of loops until we assume that a bit in the irq mask
 847  * is stuck. Overridable with module param.
 848  */
 849 static int max_interrupt_work = 4;
 850
 851 /*
 852  * Optimization can be either throuput mode or cpu mode
 853  *
 854  * Throughput Mode: Every tx and rx packet will generate an interrupt.
 855  * CPU Mode: Interrupts are controlled by a timer.
 856  */
 857 enum {
 858         NV_OPTIMIZATION_MODE_THROUGHPUT,
 859         NV_OPTIMIZATION_MODE_CPU,
 860         NV_OPTIMIZATION_MODE_DYNAMIC
 861 };
 862 static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC;
 863
 864 /*
 865  * Poll interval for timer irq
 866  *
 867  * This interval determines how frequent an interrupt is generated.
 868  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
 869  * Min = 0, and Max = 65535
 870  */
 871 static int poll_interval = -1;
 872
 873 /*
 874  * MSI interrupts
 875  */
 876 enum {
 877         NV_MSI_INT_DISABLED,
 878         NV_MSI_INT_ENABLED
 879 };
 880 static int msi = NV_MSI_INT_ENABLED;
 881
 882 /*
 883  * MSIX interrupts
 884  */
 885 enum {
 886         NV_MSIX_INT_DISABLED,
 887         NV_MSIX_INT_ENABLED
 888 };
 889 static int msix = NV_MSIX_INT_ENABLED;
 890
 891 /*
 892  * DMA 64bit
 893  */
 894 enum {
 895         NV_DMA_64BIT_DISABLED,
 896         NV_DMA_64BIT_ENABLED
 897 };
 898 static int dma_64bit = NV_DMA_64BIT_ENABLED;
 899
 900 /*
 901  * Crossover Detection
 902  * Realtek 8201 phy + some OEM boards do not work properly.
 903  */
 904 enum {
 905         NV_CROSSOVER_DETECTION_DISABLED,
 906         NV_CROSSOVER_DETECTION_ENABLED
 907 };
 908 static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
 909
 910 /*
 911  * Power down phy when interface is down (persists through reboot;
 912  * older Linux and other OSes may not power it up again)
 913  */
 914 static int phy_power_down = 0;
 915
 916 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
 917 {
 918         return netdev_priv(dev);
 919 }
 920
 921 static inline u8 __iomem *get_hwbase(struct net_device *dev)
 922 {
 923         return ((struct fe_priv *)netdev_priv(dev))->base;
 924 }
 925
 926 static inline void pci_push(u8 __iomem *base)
 927 {
 928         /* force out pending posted writes */
 929         readl(base);
 930 }
 931
 932 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
 933 {
 934         return le32_to_cpu(prd->flaglen)
 935                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
 936 }
 937
 938 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
 939 {
 940         return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
 941 }
 942
 943 static bool nv_optimized(struct fe_priv *np)
 944 {
 945         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 946                 return false;
 947         return true;
 948 }
 949
 950 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
 951                                 int delay, int delaymax, const char *msg)
 952 {
 953         u8 __iomem *base = get_hwbase(dev);
 954
 955         pci_push(base);
 956         do {
 957                 udelay(delay);
 958                 delaymax -= delay;
 959                 if (delaymax < 0) {
 960                         if (msg)
 961                                 printk("%s", msg);
 962                         return 1;
 963                 }
 964         } while ((readl(base + offset) & mask) != target);
 965         return 0;
 966 }
 967
 968 #define NV_SETUP_RX_RING 0x01
 969 #define NV_SETUP_TX_RING 0x02
 970
 971 static inline u32 dma_low(dma_addr_t addr)
 972 {
 973         return addr;
 974 }
 975
 976 static inline u32 dma_high(dma_addr_t addr)
 977 {
 978         return addr>>31>>1;     /* 0 if 32bit, shift down by 32 if 64bit */
 979 }
 980
 981 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
 982 {
 983         struct fe_priv *np = get_nvpriv(dev);
 984         u8 __iomem *base = get_hwbase(dev);
 985
 986         if (!nv_optimized(np)) {
 987                 if (rxtx_flags & NV_SETUP_RX_RING) {
 988                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
 989                 }
 990                 if (rxtx_flags & NV_SETUP_TX_RING) {
 991                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
 992                 }
 993         } else {
 994                 if (rxtx_flags & NV_SETUP_RX_RING) {
 995                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
 996                         writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
 997                 }
 998                 if (rxtx_flags & NV_SETUP_TX_RING) {
 999                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
1000                         writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
1001                 }
1002         }
1003 }
1004
1005 static void free_rings(struct net_device *dev)
1006 {
1007         struct fe_priv *np = get_nvpriv(dev);
1008
1009         if (!nv_optimized(np)) {
1010                 if (np->rx_ring.orig)
1011                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
1012                                             np->rx_ring.orig, np->ring_addr);
1013         } else {
1014                 if (np->rx_ring.ex)
1015                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
1016                                             np->rx_ring.ex, np->ring_addr);
1017         }
1018         if (np->rx_skb)
1019                 kfree(np->rx_skb);
1020         if (np->tx_skb)
1021                 kfree(np->tx_skb);
1022 }
1023
1024 static int using_multi_irqs(struct net_device *dev)
1025 {
1026         struct fe_priv *np = get_nvpriv(dev);
1027
1028         if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
1029             ((np->msi_flags & NV_MSI_X_ENABLED) &&
1030              ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
1031                 return 0;
1032         else
1033                 return 1;
1034 }
1035
1036 static void nv_txrx_gate(struct net_device *dev, bool gate)
1037 {
1038         struct fe_priv *np = get_nvpriv(dev);
1039         u8 __iomem *base = get_hwbase(dev);
1040         u32 powerstate;
1041
1042         if (!np->mac_in_use &&
1043             (np->driver_data & DEV_HAS_POWER_CNTRL)) {
1044                 powerstate = readl(base + NvRegPowerState2);
1045                 if (gate)
1046                         powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS;
1047                 else
1048                         powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS;
1049                 writel(powerstate, base + NvRegPowerState2);
1050         }
1051 }
1052
1053 static void nv_enable_irq(struct net_device *dev)
1054 {
1055         struct fe_priv *np = get_nvpriv(dev);
1056
1057         if (!using_multi_irqs(dev)) {
1058                 if (np->msi_flags & NV_MSI_X_ENABLED)
1059                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1060                 else
1061                         enable_irq(np->pci_dev->irq);
1062         } else {
1063                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1064                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1065                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1066         }
1067 }
1068
1069 static void nv_disable_irq(struct net_device *dev)
1070 {
1071         struct fe_priv *np = get_nvpriv(dev);
1072
1073         if (!using_multi_irqs(dev)) {
1074                 if (np->msi_flags & NV_MSI_X_ENABLED)
1075                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1076                 else
1077                         disable_irq(np->pci_dev->irq);
1078         } else {
1079                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1080                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1081                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1082         }
1083 }
1084
1085 /* In MSIX mode, a write to irqmask behaves as XOR */
1086 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1087 {
1088         u8 __iomem *base = get_hwbase(dev);
1089
1090         writel(mask, base + NvRegIrqMask);
1091 }
1092
1093 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1094 {
1095         struct fe_priv *np = get_nvpriv(dev);
1096         u8 __iomem *base = get_hwbase(dev);
1097
1098         if (np->msi_flags & NV_MSI_X_ENABLED) {
1099                 writel(mask, base + NvRegIrqMask);
1100         } else {
1101                 if (np->msi_flags & NV_MSI_ENABLED)
1102                         writel(0, base + NvRegMSIIrqMask);
1103                 writel(0, base + NvRegIrqMask);
1104         }
1105 }
1106
1107 static void nv_napi_enable(struct net_device *dev)
1108 {
1109         struct fe_priv *np = get_nvpriv(dev);
1110
1111         napi_enable(&np->napi);
1112 }
1113
1114 static void nv_napi_disable(struct net_device *dev)
1115 {
1116         struct fe_priv *np = get_nvpriv(dev);
1117
1118         napi_disable(&np->napi);
1119 }
1120
1121 #define MII_READ        (-1)
1122 /* mii_rw: read/write a register on the PHY.
1123  *
1124  * Caller must guarantee serialization
1125  */
1126 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1127 {
1128         u8 __iomem *base = get_hwbase(dev);
1129         u32 reg;
1130         int retval;
1131
1132         writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1133
1134         reg = readl(base + NvRegMIIControl);
1135         if (reg & NVREG_MIICTL_INUSE) {
1136                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1137                 udelay(NV_MIIBUSY_DELAY);
1138         }
1139
1140         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1141         if (value != MII_READ) {
1142                 writel(value, base + NvRegMIIData);
1143                 reg |= NVREG_MIICTL_WRITE;
1144         }
1145         writel(reg, base + NvRegMIIControl);
1146
1147         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1148                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1149                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1150                                 dev->name, miireg, addr);
1151                 retval = -1;
1152         } else if (value != MII_READ) {
1153                 /* it was a write operation - fewer failures are detectable */
1154                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1155                                 dev->name, value, miireg, addr);
1156                 retval = 0;
1157         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1158                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1159                                 dev->name, miireg, addr);
1160                 retval = -1;
1161         } else {
1162                 retval = readl(base + NvRegMIIData);
1163                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1164                                 dev->name, miireg, addr, retval);
1165         }
1166
1167         return retval;
1168 }
1169
1170 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1171 {
1172         struct fe_priv *np = netdev_priv(dev);
1173         u32 miicontrol;
1174         unsigned int tries = 0;
1175
1176         miicontrol = BMCR_RESET | bmcr_setup;
1177         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1178                 return -1;
1179         }
1180
1181         /* wait for 500ms */
1182         msleep(500);
1183
1184         /* must wait till reset is deasserted */
1185         while (miicontrol & BMCR_RESET) {
1186                 msleep(10);
1187                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1188                 /* FIXME: 100 tries seem excessive */
1189                 if (tries++ > 100)
1190                         return -1;
1191         }
1192         return 0;
1193 }
1194
1195 static int phy_init(struct net_device *dev)
1196 {
1197         struct fe_priv *np = get_nvpriv(dev);
1198         u8 __iomem *base = get_hwbase(dev);
1199         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1200
1201         /* phy errata for E3016 phy */
1202         if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1203                 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1204                 reg &= ~PHY_MARVELL_E3016_INITMASK;
1205                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1206                         printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1207                         return PHY_ERROR;
1208                 }
1209         }
1210         if (np->phy_oui == PHY_OUI_REALTEK) {
1211                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1212                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1213                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1214                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1215                                 return PHY_ERROR;
1216                         }
1217                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1218                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1219                                 return PHY_ERROR;
1220                         }
1221                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1222                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1223                                 return PHY_ERROR;
1224                         }
1225                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1226                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1227                                 return PHY_ERROR;
1228                         }
1229                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1230                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1231                                 return PHY_ERROR;
1232                         }
1233                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1234                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1235                                 return PHY_ERROR;
1236                         }
1237                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1238                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1239                                 return PHY_ERROR;
1240                         }
1241                 }
1242                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1243                     np->phy_rev == PHY_REV_REALTEK_8211C) {
1244                         u32 powerstate = readl(base + NvRegPowerState2);
1245
1246                         /* need to perform hw phy reset */
1247                         powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1248                         writel(powerstate, base + NvRegPowerState2);
1249                         msleep(25);
1250
1251                         powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1252                         writel(powerstate, base + NvRegPowerState2);
1253                         msleep(25);
1254
1255                         reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1256                         reg |= PHY_REALTEK_INIT9;
1257                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) {
1258                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1259                                 return PHY_ERROR;
1260                         }
1261                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10)) {
1262                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1263                                 return PHY_ERROR;
1264                         }
1265                         reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1266                         if (!(reg & PHY_REALTEK_INIT11)) {
1267                                 reg |= PHY_REALTEK_INIT11;
1268                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) {
1269                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1270                                         return PHY_ERROR;
1271                                 }
1272                         }
1273                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1274                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1275                                 return PHY_ERROR;
1276                         }
1277                 }
1278                 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1279                         if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1280                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1281                                 phy_reserved |= PHY_REALTEK_INIT7;
1282                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1283                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1284                                         return PHY_ERROR;
1285                                 }
1286                         }
1287                 }
1288         }
1289
1290         /* set advertise register */
1291         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1292         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1293         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1294                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1295                 return PHY_ERROR;
1296         }
1297
1298         /* get phy interface type */
1299         phyinterface = readl(base + NvRegPhyInterface);
1300
1301         /* see if gigabit phy */
1302         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1303         if (mii_status & PHY_GIGABIT) {
1304                 np->gigabit = PHY_GIGABIT;
1305                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1306                 mii_control_1000 &= ~ADVERTISE_1000HALF;
1307                 if (phyinterface & PHY_RGMII)
1308                         mii_control_1000 |= ADVERTISE_1000FULL;
1309                 else
1310                         mii_control_1000 &= ~ADVERTISE_1000FULL;
1311
1312                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1313                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1314                         return PHY_ERROR;
1315                 }
1316         }
1317         else
1318                 np->gigabit = 0;
1319
1320         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1321         mii_control |= BMCR_ANENABLE;
1322
1323         if (np->phy_oui == PHY_OUI_REALTEK &&
1324             np->phy_model == PHY_MODEL_REALTEK_8211 &&
1325             np->phy_rev == PHY_REV_REALTEK_8211C) {
1326                 /* start autoneg since we already performed hw reset above */
1327                 mii_control |= BMCR_ANRESTART;
1328                 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1329                         printk(KERN_INFO "%s: phy init failed\n", pci_name(np->pci_dev));
1330                         return PHY_ERROR;
1331                 }
1332         } else {
1333                 /* reset the phy
1334                  * (certain phys need bmcr to be setup with reset)
1335                  */
1336                 if (phy_reset(dev, mii_control)) {
1337                         printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1338                         return PHY_ERROR;
1339                 }
1340         }
1341
1342         /* phy vendor specific configuration */
1343         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1344                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1345                 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1346                 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1347                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1348                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1349                         return PHY_ERROR;
1350                 }
1351                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1352                 phy_reserved |= PHY_CICADA_INIT5;
1353                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1354                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1355                         return PHY_ERROR;
1356                 }
1357         }
1358         if (np->phy_oui == PHY_OUI_CICADA) {
1359                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1360                 phy_reserved |= PHY_CICADA_INIT6;
1361                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1362                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1363                         return PHY_ERROR;
1364                 }
1365         }
1366         if (np->phy_oui == PHY_OUI_VITESSE) {
1367                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) {
1368                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1369                         return PHY_ERROR;
1370                 }
1371                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) {
1372                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1373                         return PHY_ERROR;
1374                 }
1375                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1376                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1377                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1378                         return PHY_ERROR;
1379                 }
1380                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1381                 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1382                 phy_reserved |= PHY_VITESSE_INIT3;
1383                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1384                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1385                         return PHY_ERROR;
1386                 }
1387                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) {
1388                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1389                         return PHY_ERROR;
1390                 }
1391                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) {
1392                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1393                         return PHY_ERROR;
1394                 }
1395                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1396                 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1397                 phy_reserved |= PHY_VITESSE_INIT3;
1398                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1399                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1400                         return PHY_ERROR;
1401                 }
1402                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1403                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1404                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1405                         return PHY_ERROR;
1406                 }
1407                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) {
1408                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1409                         return PHY_ERROR;
1410                 }
1411                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) {
1412                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1413                         return PHY_ERROR;
1414                 }
1415                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1416                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1417                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1418                         return PHY_ERROR;
1419                 }
1420                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1421                 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1422                 phy_reserved |= PHY_VITESSE_INIT8;
1423                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1424                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1425                         return PHY_ERROR;
1426                 }
1427                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) {
1428                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1429                         return PHY_ERROR;
1430                 }
1431                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) {
1432                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1433                         return PHY_ERROR;
1434                 }
1435         }
1436         if (np->phy_oui == PHY_OUI_REALTEK) {
1437                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1438                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1439                         /* reset could have cleared these out, set them back */
1440                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1441                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1442                                 return PHY_ERROR;
1443                         }
1444                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1445                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1446                                 return PHY_ERROR;
1447                         }
1448                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1449                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1450                                 return PHY_ERROR;
1451                         }
1452                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1453                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1454                                 return PHY_ERROR;
1455                         }
1456                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1457                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1458                                 return PHY_ERROR;
1459                         }
1460                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1461                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1462                                 return PHY_ERROR;
1463                         }
1464                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1465                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1466                                 return PHY_ERROR;
1467                         }
1468                 }
1469                 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1470                         if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1471                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1472                                 phy_reserved |= PHY_REALTEK_INIT7;
1473                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1474                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1475                                         return PHY_ERROR;
1476                                 }
1477                         }
1478                         if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1479                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1480                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1481                                         return PHY_ERROR;
1482                                 }
1483                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
1484                                 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1485                                 phy_reserved |= PHY_REALTEK_INIT3;
1486                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved)) {
1487                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1488                                         return PHY_ERROR;
1489                                 }
1490                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1491                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1492                                         return PHY_ERROR;
1493                                 }
1494                         }
1495                 }
1496         }
1497
1498         /* some phys clear out pause advertisment on reset, set it back */
1499         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1500
1501         /* restart auto negotiation, power down phy */
1502         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1503         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1504         if (phy_power_down) {
1505                 mii_control |= BMCR_PDOWN;
1506         }
1507         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1508                 return PHY_ERROR;
1509         }
1510
1511         return 0;
1512 }
1513
1514 static void nv_start_rx(struct net_device *dev)
1515 {
1516         struct fe_priv *np = netdev_priv(dev);
1517         u8 __iomem *base = get_hwbase(dev);
1518         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1519
1520         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1521         /* Already running? Stop it. */
1522         if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1523                 rx_ctrl &= ~NVREG_RCVCTL_START;
1524                 writel(rx_ctrl, base + NvRegReceiverControl);
1525                 pci_push(base);
1526         }
1527         writel(np->linkspeed, base + NvRegLinkSpeed);
1528         pci_push(base);
1529         rx_ctrl |= NVREG_RCVCTL_START;
1530         if (np->mac_in_use)
1531                 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1532         writel(rx_ctrl, base + NvRegReceiverControl);
1533         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1534                                 dev->name, np->duplex, np->linkspeed);
1535         pci_push(base);
1536 }
1537
1538 static void nv_stop_rx(struct net_device *dev)
1539 {
1540         struct fe_priv *np = netdev_priv(dev);
1541         u8 __iomem *base = get_hwbase(dev);
1542         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1543
1544         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1545         if (!np->mac_in_use)
1546                 rx_ctrl &= ~NVREG_RCVCTL_START;
1547         else
1548                 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1549         writel(rx_ctrl, base + NvRegReceiverControl);
1550         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1551                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1552                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1553
1554         udelay(NV_RXSTOP_DELAY2);
1555         if (!np->mac_in_use)
1556                 writel(0, base + NvRegLinkSpeed);
1557 }
1558
1559 static void nv_start_tx(struct net_device *dev)
1560 {
1561         struct fe_priv *np = netdev_priv(dev);
1562         u8 __iomem *base = get_hwbase(dev);
1563         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1564
1565         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1566         tx_ctrl |= NVREG_XMITCTL_START;
1567         if (np->mac_in_use)
1568                 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1569         writel(tx_ctrl, base + NvRegTransmitterControl);
1570         pci_push(base);
1571 }
1572
1573 static void nv_stop_tx(struct net_device *dev)
1574 {
1575         struct fe_priv *np = netdev_priv(dev);
1576         u8 __iomem *base = get_hwbase(dev);
1577         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1578
1579         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1580         if (!np->mac_in_use)
1581                 tx_ctrl &= ~NVREG_XMITCTL_START;
1582         else
1583                 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1584         writel(tx_ctrl, base + NvRegTransmitterControl);
1585         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1586                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1587                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1588
1589         udelay(NV_TXSTOP_DELAY2);
1590         if (!np->mac_in_use)
1591                 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1592                        base + NvRegTransmitPoll);
1593 }
1594
1595 static void nv_start_rxtx(struct net_device *dev)
1596 {
1597         nv_start_rx(dev);
1598         nv_start_tx(dev);
1599 }
1600
1601 static void nv_stop_rxtx(struct net_device *dev)
1602 {
1603         nv_stop_rx(dev);
1604         nv_stop_tx(dev);
1605 }
1606
1607 static void nv_txrx_reset(struct net_device *dev)
1608 {
1609         struct fe_priv *np = netdev_priv(dev);
1610         u8 __iomem *base = get_hwbase(dev);
1611
1612         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1613         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1614         pci_push(base);
1615         udelay(NV_TXRX_RESET_DELAY);
1616         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1617         pci_push(base);
1618 }
1619
1620 static void nv_mac_reset(struct net_device *dev)
1621 {
1622         struct fe_priv *np = netdev_priv(dev);
1623         u8 __iomem *base = get_hwbase(dev);
1624         u32 temp1, temp2, temp3;
1625
1626         dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1627
1628         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1629         pci_push(base);
1630
1631         /* save registers since they will be cleared on reset */
1632         temp1 = readl(base + NvRegMacAddrA);
1633         temp2 = readl(base + NvRegMacAddrB);
1634         temp3 = readl(base + NvRegTransmitPoll);
1635
1636         writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1637         pci_push(base);
1638         udelay(NV_MAC_RESET_DELAY);
1639         writel(0, base + NvRegMacReset);
1640         pci_push(base);
1641         udelay(NV_MAC_RESET_DELAY);
1642
1643         /* restore saved registers */
1644         writel(temp1, base + NvRegMacAddrA);
1645         writel(temp2, base + NvRegMacAddrB);
1646         writel(temp3, base + NvRegTransmitPoll);
1647
1648         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1649         pci_push(base);
1650 }
1651
1652 static void nv_get_hw_stats(struct net_device *dev)
1653 {
1654         struct fe_priv *np = netdev_priv(dev);
1655         u8 __iomem *base = get_hwbase(dev);
1656
1657         np->estats.tx_bytes += readl(base + NvRegTxCnt);
1658         np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1659         np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1660         np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1661         np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1662         np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1663         np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1664         np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1665         np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1666         np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1667         np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1668         np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1669         np->estats.rx_runt += readl(base + NvRegRxRunt);
1670         np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1671         np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1672         np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1673         np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1674         np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1675         np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1676         np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1677         np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1678         np->estats.rx_packets =
1679                 np->estats.rx_unicast +
1680                 np->estats.rx_multicast +
1681                 np->estats.rx_broadcast;
1682         np->estats.rx_errors_total =
1683                 np->estats.rx_crc_errors +
1684                 np->estats.rx_over_errors +
1685                 np->estats.rx_frame_error +
1686                 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1687                 np->estats.rx_late_collision +
1688                 np->estats.rx_runt +
1689                 np->estats.rx_frame_too_long;
1690         np->estats.tx_errors_total =
1691                 np->estats.tx_late_collision +
1692                 np->estats.tx_fifo_errors +
1693                 np->estats.tx_carrier_errors +
1694                 np->estats.tx_excess_deferral +
1695                 np->estats.tx_retry_error;
1696
1697         if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1698                 np->estats.tx_deferral += readl(base + NvRegTxDef);
1699                 np->estats.tx_packets += readl(base + NvRegTxFrame);
1700                 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1701                 np->estats.tx_pause += readl(base + NvRegTxPause);
1702                 np->estats.rx_pause += readl(base + NvRegRxPause);
1703                 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1704         }
1705
1706         if (np->driver_data & DEV_HAS_STATISTICS_V3) {
1707                 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1708                 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1709                 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
1710         }
1711 }
1712
1713 /*
1714  * nv_get_stats: dev->get_stats function
1715  * Get latest stats value from the nic.
1716  * Called with read_lock(&dev_base_lock) held for read -
1717  * only synchronized against unregister_netdevice.
1718  */
1719 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1720 {
1721         struct fe_priv *np = netdev_priv(dev);
1722
1723         /* If the nic supports hw counters then retrieve latest values */
1724         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) {
1725                 nv_get_hw_stats(dev);
1726
1727                 /* copy to net_device stats */
1728                 dev->stats.tx_bytes = np->estats.tx_bytes;
1729                 dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1730                 dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1731                 dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
1732                 dev->stats.rx_over_errors = np->estats.rx_over_errors;
1733                 dev->stats.rx_errors = np->estats.rx_errors_total;
1734                 dev->stats.tx_errors = np->estats.tx_errors_total;
1735         }
1736
1737         return &dev->stats;
1738 }
1739
1740 /*
1741  * nv_alloc_rx: fill rx ring entries.
1742  * Return 1 if the allocations for the skbs failed and the
1743  * rx engine is without Available descriptors
1744  */
1745 static int nv_alloc_rx(struct net_device *dev)
1746 {
1747         struct fe_priv *np = netdev_priv(dev);
1748         struct ring_desc* less_rx;
1749
1750         less_rx = np->get_rx.orig;
1751         if (less_rx-- == np->first_rx.orig)
1752                 less_rx = np->last_rx.orig;
1753
1754         while (np->put_rx.orig != less_rx) {
1755                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1756                 if (skb) {
1757                         np->put_rx_ctx->skb = skb;
1758                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1759                                                              skb->data,
1760                                                              skb_tailroom(skb),
1761                                                              PCI_DMA_FROMDEVICE);
1762                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1763                         np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1764                         wmb();
1765                         np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1766                         if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1767                                 np->put_rx.orig = np->first_rx.orig;
1768                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1769                                 np->put_rx_ctx = np->first_rx_ctx;
1770                 } else {
1771                         return 1;
1772                 }
1773         }
1774         return 0;
1775 }
1776
1777 static int nv_alloc_rx_optimized(struct net_device *dev)
1778 {
1779         struct fe_priv *np = netdev_priv(dev);
1780         struct ring_desc_ex* less_rx;
1781
1782         less_rx = np->get_rx.ex;
1783         if (less_rx-- == np->first_rx.ex)
1784                 less_rx = np->last_rx.ex;
1785
1786         while (np->put_rx.ex != less_rx) {
1787                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1788                 if (skb) {
1789                         np->put_rx_ctx->skb = skb;
1790                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1791                                                              skb->data,
1792                                                              skb_tailroom(skb),
1793                                                              PCI_DMA_FROMDEVICE);
1794                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1795                         np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1796                         np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
1797                         wmb();
1798                         np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1799                         if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1800                                 np->put_rx.ex = np->first_rx.ex;
1801                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1802                                 np->put_rx_ctx = np->first_rx_ctx;
1803                 } else {
1804                         return 1;
1805                 }
1806         }
1807         return 0;
1808 }
1809
1810 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1811 static void nv_do_rx_refill(unsigned long data)
1812 {
1813         struct net_device *dev = (struct net_device *) data;
1814         struct fe_priv *np = netdev_priv(dev);
1815
1816         /* Just reschedule NAPI rx processing */
1817         napi_schedule(&np->napi);
1818 }
1819
1820 static void nv_init_rx(struct net_device *dev)
1821 {
1822         struct fe_priv *np = netdev_priv(dev);
1823         int i;
1824
1825         np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1826
1827         if (!nv_optimized(np))
1828                 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1829         else
1830                 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1831         np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1832         np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1833
1834         for (i = 0; i < np->rx_ring_size; i++) {
1835                 if (!nv_optimized(np)) {
1836                         np->rx_ring.orig[i].flaglen = 0;
1837                         np->rx_ring.orig[i].buf = 0;
1838                 } else {
1839                         np->rx_ring.ex[i].flaglen = 0;
1840                         np->rx_ring.ex[i].txvlan = 0;
1841                         np->rx_ring.ex[i].bufhigh = 0;
1842                         np->rx_ring.ex[i].buflow = 0;
1843                 }
1844                 np->rx_skb[i].skb = NULL;
1845                 np->rx_skb[i].dma = 0;
1846         }
1847 }
1848
1849 static void nv_init_tx(struct net_device *dev)
1850 {
1851         struct fe_priv *np = netdev_priv(dev);
1852         int i;
1853
1854         np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1855
1856         if (!nv_optimized(np))
1857                 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1858         else
1859                 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1860         np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1861         np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1862         np->tx_pkts_in_progress = 0;
1863         np->tx_change_owner = NULL;
1864         np->tx_end_flip = NULL;
1865         np->tx_stop = 0;
1866
1867         for (i = 0; i < np->tx_ring_size; i++) {
1868                 if (!nv_optimized(np)) {
1869                         np->tx_ring.orig[i].flaglen = 0;
1870                         np->tx_ring.orig[i].buf = 0;
1871                 } else {
1872                         np->tx_ring.ex[i].flaglen = 0;
1873                         np->tx_ring.ex[i].txvlan = 0;
1874                         np->tx_ring.ex[i].bufhigh = 0;
1875                         np->tx_ring.ex[i].buflow = 0;
1876                 }
1877                 np->tx_skb[i].skb = NULL;
1878                 np->tx_skb[i].dma = 0;
1879                 np->tx_skb[i].dma_len = 0;
1880                 np->tx_skb[i].dma_single = 0;
1881                 np->tx_skb[i].first_tx_desc = NULL;
1882                 np->tx_skb[i].next_tx_ctx = NULL;
1883         }
1884 }
1885
1886 static int nv_init_ring(struct net_device *dev)
1887 {
1888         struct fe_priv *np = netdev_priv(dev);
1889
1890         nv_init_tx(dev);
1891         nv_init_rx(dev);
1892
1893         if (!nv_optimized(np))
1894                 return nv_alloc_rx(dev);
1895         else
1896                 return nv_alloc_rx_optimized(dev);
1897 }
1898
1899 static void nv_unmap_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1900 {
1901         if (tx_skb->dma) {
1902                 if (tx_skb->dma_single)
1903                         pci_unmap_single(np->pci_dev, tx_skb->dma,
1904                                          tx_skb->dma_len,
1905                                          PCI_DMA_TODEVICE);
1906                 else
1907                         pci_unmap_page(np->pci_dev, tx_skb->dma,
1908                                        tx_skb->dma_len,
1909                                        PCI_DMA_TODEVICE);
1910                 tx_skb->dma = 0;
1911         }
1912 }
1913
1914 static int nv_release_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1915 {
1916         nv_unmap_txskb(np, tx_skb);
1917         if (tx_skb->skb) {
1918                 dev_kfree_skb_any(tx_skb->skb);
1919                 tx_skb->skb = NULL;
1920                 return 1;
1921         }
1922         return 0;
1923 }
1924
1925 static void nv_drain_tx(struct net_device *dev)
1926 {
1927         struct fe_priv *np = netdev_priv(dev);
1928         unsigned int i;
1929
1930         for (i = 0; i < np->tx_ring_size; i++) {
1931                 if (!nv_optimized(np)) {
1932                         np->tx_ring.orig[i].flaglen = 0;
1933                         np->tx_ring.orig[i].buf = 0;
1934                 } else {
1935                         np->tx_ring.ex[i].flaglen = 0;
1936                         np->tx_ring.ex[i].txvlan = 0;
1937                         np->tx_ring.ex[i].bufhigh = 0;
1938                         np->tx_ring.ex[i].buflow = 0;
1939                 }
1940                 if (nv_release_txskb(np, &np->tx_skb[i]))
1941                         dev->stats.tx_dropped++;
1942                 np->tx_skb[i].dma = 0;
1943                 np->tx_skb[i].dma_len = 0;
1944                 np->tx_skb[i].dma_single = 0;
1945                 np->tx_skb[i].first_tx_desc = NULL;
1946                 np->tx_skb[i].next_tx_ctx = NULL;
1947         }
1948         np->tx_pkts_in_progress = 0;
1949         np->tx_change_owner = NULL;
1950         np->tx_end_flip = NULL;
1951 }
1952
1953 static void nv_drain_rx(struct net_device *dev)
1954 {
1955         struct fe_priv *np = netdev_priv(dev);
1956         int i;
1957
1958         for (i = 0; i < np->rx_ring_size; i++) {
1959                 if (!nv_optimized(np)) {
1960                         np->rx_ring.orig[i].flaglen = 0;
1961                         np->rx_ring.orig[i].buf = 0;
1962                 } else {
1963                         np->rx_ring.ex[i].flaglen = 0;
1964                         np->rx_ring.ex[i].txvlan = 0;
1965                         np->rx_ring.ex[i].bufhigh = 0;
1966                         np->rx_ring.ex[i].buflow = 0;
1967                 }
1968                 wmb();
1969                 if (np->rx_skb[i].skb) {
1970                         pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
1971                                          (skb_end_pointer(np->rx_skb[i].skb) -
1972                                           np->rx_skb[i].skb->data),
1973                                          PCI_DMA_FROMDEVICE);
1974                         dev_kfree_skb(np->rx_skb[i].skb);
1975                         np->rx_skb[i].skb = NULL;
1976                 }
1977         }
1978 }
1979
1980 static void nv_drain_rxtx(struct net_device *dev)
1981 {
1982         nv_drain_tx(dev);
1983         nv_drain_rx(dev);
1984 }
1985
1986 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1987 {
1988         return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1989 }
1990
1991 static void nv_legacybackoff_reseed(struct net_device *dev)
1992 {
1993         u8 __iomem *base = get_hwbase(dev);
1994         u32 reg;
1995         u32 low;
1996         int tx_status = 0;
1997
1998         reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
1999         get_random_bytes(&low, sizeof(low));
2000         reg |= low & NVREG_SLOTTIME_MASK;
2001
2002         /* Need to stop tx before change takes effect.
2003          * Caller has already gained np->lock.
2004          */
2005         tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
2006         if (tx_status)
2007                 nv_stop_tx(dev);
2008         nv_stop_rx(dev);
2009         writel(reg, base + NvRegSlotTime);
2010         if (tx_status)
2011                 nv_start_tx(dev);
2012         nv_start_rx(dev);
2013 }
2014
2015 /* Gear Backoff Seeds */
2016 #define BACKOFF_SEEDSET_ROWS    8
2017 #define BACKOFF_SEEDSET_LFSRS   15
2018
2019 /* Known Good seed sets */
2020 static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2021     {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2022     {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
2023     {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2024     {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2025     {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2026     {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2027     {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800,  84},
2028     {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184}};
2029
2030 static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2031     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2032     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2033     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2034     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2035     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2036     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2037     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2038     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}};
2039
2040 static void nv_gear_backoff_reseed(struct net_device *dev)
2041 {
2042         u8 __iomem *base = get_hwbase(dev);
2043         u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
2044         u32 temp, seedset, combinedSeed;
2045         int i;
2046
2047         /* Setup seed for free running LFSR */
2048         /* We are going to read the time stamp counter 3 times
2049            and swizzle bits around to increase randomness */
2050         get_random_bytes(&miniseed1, sizeof(miniseed1));
2051         miniseed1 &= 0x0fff;
2052         if (miniseed1 == 0)
2053                 miniseed1 = 0xabc;
2054
2055         get_random_bytes(&miniseed2, sizeof(miniseed2));
2056         miniseed2 &= 0x0fff;
2057         if (miniseed2 == 0)
2058                 miniseed2 = 0xabc;
2059         miniseed2_reversed =
2060                 ((miniseed2 & 0xF00) >> 8) |
2061                  (miniseed2 & 0x0F0) |
2062                  ((miniseed2 & 0x00F) << 8);
2063
2064         get_random_bytes(&miniseed3, sizeof(miniseed3));
2065         miniseed3 &= 0x0fff;
2066         if (miniseed3 == 0)
2067                 miniseed3 = 0xabc;
2068         miniseed3_reversed =
2069                 ((miniseed3 & 0xF00) >> 8) |
2070                  (miniseed3 & 0x0F0) |
2071                  ((miniseed3 & 0x00F) << 8);
2072
2073         combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
2074                        (miniseed2 ^ miniseed3_reversed);
2075
2076         /* Seeds can not be zero */
2077         if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
2078                 combinedSeed |= 0x08;
2079         if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
2080                 combinedSeed |= 0x8000;
2081
2082         /* No need to disable tx here */
2083         temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
2084         temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
2085         temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
2086         writel(temp,base + NvRegBackOffControl);
2087
2088         /* Setup seeds for all gear LFSRs. */
2089         get_random_bytes(&seedset, sizeof(seedset));
2090         seedset = seedset % BACKOFF_SEEDSET_ROWS;
2091         for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++)
2092         {
2093                 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
2094                 temp |= main_seedset[seedset][i-1] & 0x3ff;
2095                 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
2096                 writel(temp, base + NvRegBackOffControl);
2097         }
2098 }
2099
2100 /*
2101  * nv_start_xmit: dev->hard_start_xmit function
2102  * Called with netif_tx_lock held.
2103  */
2104 static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
2105 {
2106         struct fe_priv *np = netdev_priv(dev);
2107         u32 tx_flags = 0;
2108         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2109         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2110         unsigned int i;
2111         u32 offset = 0;
2112         u32 bcnt;
2113         u32 size = skb_headlen(skb);
2114         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2115         u32 empty_slots;
2116         struct ring_desc* put_tx;
2117         struct ring_desc* start_tx;
2118         struct ring_desc* prev_tx;
2119         struct nv_skb_map* prev_tx_ctx;
2120         unsigned long flags;
2121
2122         /* add fragments to entries count */
2123         for (i = 0; i < fragments; i++) {
2124                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2125                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2126         }
2127
2128         spin_lock_irqsave(&np->lock, flags);
2129         empty_slots = nv_get_empty_tx_slots(np);
2130         if (unlikely(empty_slots <= entries)) {
2131                 netif_stop_queue(dev);
2132                 np->tx_stop = 1;
2133                 spin_unlock_irqrestore(&np->lock, flags);
2134                 return NETDEV_TX_BUSY;
2135         }
2136         spin_unlock_irqrestore(&np->lock, flags);
2137
2138         start_tx = put_tx = np->put_tx.orig;
2139
2140         /* setup the header buffer */
2141         do {
2142                 prev_tx = put_tx;
2143                 prev_tx_ctx = np->put_tx_ctx;
2144                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2145                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2146                                                 PCI_DMA_TODEVICE);
2147                 np->put_tx_ctx->dma_len = bcnt;
2148                 np->put_tx_ctx->dma_single = 1;
2149                 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2150                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2151
2152                 tx_flags = np->tx_flags;
2153                 offset += bcnt;
2154                 size -= bcnt;
2155                 if (unlikely(put_tx++ == np->last_tx.orig))
2156                         put_tx = np->first_tx.orig;
2157                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2158                         np->put_tx_ctx = np->first_tx_ctx;
2159         } while (size);
2160
2161         /* setup the fragments */
2162         for (i = 0; i < fragments; i++) {
2163                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2164                 u32 size = frag->size;
2165                 offset = 0;
2166
2167                 do {
2168                         prev_tx = put_tx;
2169                         prev_tx_ctx = np->put_tx_ctx;
2170                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2171                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2172                                                            PCI_DMA_TODEVICE);
2173                         np->put_tx_ctx->dma_len = bcnt;
2174                         np->put_tx_ctx->dma_single = 0;
2175                         put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2176                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2177
2178                         offset += bcnt;
2179                         size -= bcnt;
2180                         if (unlikely(put_tx++ == np->last_tx.orig))
2181                                 put_tx = np->first_tx.orig;
2182                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2183                                 np->put_tx_ctx = np->first_tx_ctx;
2184                 } while (size);
2185         }
2186
2187         /* set last fragment flag  */
2188         prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
2189
2190         /* save skb in this slot's context area */
2191         prev_tx_ctx->skb = skb;
2192
2193         if (skb_is_gso(skb))
2194                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2195         else
2196                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2197                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2198
2199         spin_lock_irqsave(&np->lock, flags);
2200
2201         /* set tx flags */
2202         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2203         np->put_tx.orig = put_tx;
2204
2205         spin_unlock_irqrestore(&np->lock, flags);
2206
2207         dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
2208                 dev->name, entries, tx_flags_extra);
2209         {
2210                 int j;
2211                 for (j=0; j<64; j++) {
2212                         if ((j%16) == 0)
2213                                 dprintk("\n%03x:", j);
2214                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2215                 }
2216                 dprintk("\n");
2217         }
2218
2219         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2220         return NETDEV_TX_OK;
2221 }
2222
2223 static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb,
2224                                            struct net_device *dev)
2225 {
2226         struct fe_priv *np = netdev_priv(dev);
2227         u32 tx_flags = 0;
2228         u32 tx_flags_extra;
2229         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2230         unsigned int i;
2231         u32 offset = 0;
2232         u32 bcnt;
2233         u32 size = skb_headlen(skb);
2234         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2235         u32 empty_slots;
2236         struct ring_desc_ex* put_tx;
2237         struct ring_desc_ex* start_tx;
2238         struct ring_desc_ex* prev_tx;
2239         struct nv_skb_map* prev_tx_ctx;
2240         struct nv_skb_map* start_tx_ctx;
2241         unsigned long flags;
2242
2243         /* add fragments to entries count */
2244         for (i = 0; i < fragments; i++) {
2245                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2246                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2247         }
2248
2249         spin_lock_irqsave(&np->lock, flags);
2250         empty_slots = nv_get_empty_tx_slots(np);
2251         if (unlikely(empty_slots <= entries)) {
2252                 netif_stop_queue(dev);
2253                 np->tx_stop = 1;
2254                 spin_unlock_irqrestore(&np->lock, flags);
2255                 return NETDEV_TX_BUSY;
2256         }
2257         spin_unlock_irqrestore(&np->lock, flags);
2258
2259         start_tx = put_tx = np->put_tx.ex;
2260         start_tx_ctx = np->put_tx_ctx;
2261
2262         /* setup the header buffer */
2263         do {
2264                 prev_tx = put_tx;
2265                 prev_tx_ctx = np->put_tx_ctx;
2266                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2267                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2268                                                 PCI_DMA_TODEVICE);
2269                 np->put_tx_ctx->dma_len = bcnt;
2270                 np->put_tx_ctx->dma_single = 1;
2271                 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2272                 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2273                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2274
2275                 tx_flags = NV_TX2_VALID;
2276                 offset += bcnt;
2277                 size -= bcnt;
2278                 if (unlikely(put_tx++ == np->last_tx.ex))
2279                         put_tx = np->first_tx.ex;
2280                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2281                         np->put_tx_ctx = np->first_tx_ctx;
2282         } while (size);
2283
2284         /* setup the fragments */
2285         for (i = 0; i < fragments; i++) {
2286                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2287                 u32 size = frag->size;
2288                 offset = 0;
2289
2290                 do {
2291                         prev_tx = put_tx;
2292                         prev_tx_ctx = np->put_tx_ctx;
2293                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2294                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2295                                                            PCI_DMA_TODEVICE);
2296                         np->put_tx_ctx->dma_len = bcnt;
2297                         np->put_tx_ctx->dma_single = 0;
2298                         put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2299                         put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2300                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2301
2302                         offset += bcnt;
2303                         size -= bcnt;
2304                         if (unlikely(put_tx++ == np->last_tx.ex))
2305                                 put_tx = np->first_tx.ex;
2306                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2307                                 np->put_tx_ctx = np->first_tx_ctx;
2308                 } while (size);
2309         }
2310
2311         /* set last fragment flag  */
2312         prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
2313
2314         /* save skb in this slot's context area */
2315         prev_tx_ctx->skb = skb;
2316
2317         if (skb_is_gso(skb))
2318                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2319         else
2320                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2321                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2322
2323         /* vlan tag */
2324         if (likely(!np->vlangrp)) {
2325                 start_tx->txvlan = 0;
2326         } else {
2327                 if (vlan_tx_tag_present(skb))
2328                         start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb));
2329                 else
2330                         start_tx->txvlan = 0;
2331         }
2332
2333         spin_lock_irqsave(&np->lock, flags);
2334
2335         if (np->tx_limit) {
2336                 /* Limit the number of outstanding tx. Setup all fragments, but
2337                  * do not set the VALID bit on the first descriptor. Save a pointer
2338                  * to that descriptor and also for next skb_map element.
2339                  */
2340
2341                 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2342                         if (!np->tx_change_owner)
2343                                 np->tx_change_owner = start_tx_ctx;
2344
2345                         /* remove VALID bit */
2346                         tx_flags &= ~NV_TX2_VALID;
2347                         start_tx_ctx->first_tx_desc = start_tx;
2348                         start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2349                         np->tx_end_flip = np->put_tx_ctx;
2350                 } else {
2351                         np->tx_pkts_in_progress++;
2352                 }
2353         }
2354
2355         /* set tx flags */
2356         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2357         np->put_tx.ex = put_tx;
2358
2359         spin_unlock_irqrestore(&np->lock, flags);
2360
2361         dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
2362                 dev->name, entries, tx_flags_extra);
2363         {
2364                 int j;
2365                 for (j=0; j<64; j++) {
2366                         if ((j%16) == 0)
2367                                 dprintk("\n%03x:", j);
2368                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2369                 }
2370                 dprintk("\n");
2371         }
2372
2373         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2374         return NETDEV_TX_OK;
2375 }
2376
2377 static inline void nv_tx_flip_ownership(struct net_device *dev)
2378 {
2379         struct fe_priv *np = netdev_priv(dev);
2380
2381         np->tx_pkts_in_progress--;
2382         if (np->tx_change_owner) {
2383                 np->tx_change_owner->first_tx_desc->flaglen |=
2384                         cpu_to_le32(NV_TX2_VALID);
2385                 np->tx_pkts_in_progress++;
2386
2387                 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2388                 if (np->tx_change_owner == np->tx_end_flip)
2389                         np->tx_change_owner = NULL;
2390
2391                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2392         }
2393 }
2394
2395 /*
2396  * nv_tx_done: check for completed packets, release the skbs.
2397  *
2398  * Caller must own np->lock.
2399  */
2400 static int nv_tx_done(struct net_device *dev, int limit)
2401 {
2402         struct fe_priv *np = netdev_priv(dev);
2403         u32 flags;
2404         int tx_work = 0;
2405         struct ring_desc* orig_get_tx = np->get_tx.orig;
2406
2407         while ((np->get_tx.orig != np->put_tx.orig) &&
2408                !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) &&
2409                (tx_work < limit)) {
2410
2411                 dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
2412                                         dev->name, flags);
2413
2414                 nv_unmap_txskb(np, np->get_tx_ctx);
2415
2416                 if (np->desc_ver == DESC_VER_1) {
2417                         if (flags & NV_TX_LASTPACKET) {
2418                                 if (flags & NV_TX_ERROR) {
2419                                         if (flags & NV_TX_UNDERFLOW)
2420                                                 dev->stats.tx_fifo_errors++;
2421                                         if (flags & NV_TX_CARRIERLOST)
2422                                                 dev->stats.tx_carrier_errors++;
2423                                         if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK))
2424                                                 nv_legacybackoff_reseed(dev);
2425                                         dev->stats.tx_errors++;
2426                                 } else {
2427                                         dev->stats.tx_packets++;
2428                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2429                                 }
2430                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2431                                 np->get_tx_ctx->skb = NULL;
2432                                 tx_work++;
2433                         }
2434                 } else {
2435                         if (flags & NV_TX2_LASTPACKET) {
2436                                 if (flags & NV_TX2_ERROR) {
2437                                         if (flags & NV_TX2_UNDERFLOW)
2438                                                 dev->stats.tx_fifo_errors++;
2439                                         if (flags & NV_TX2_CARRIERLOST)
2440                                                 dev->stats.tx_carrier_errors++;
2441                                         if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK))
2442                                                 nv_legacybackoff_reseed(dev);
2443                                         dev->stats.tx_errors++;
2444                                 } else {
2445                                         dev->stats.tx_packets++;
2446                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2447                                 }
2448                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2449                                 np->get_tx_ctx->skb = NULL;
2450                                 tx_work++;
2451                         }
2452                 }
2453                 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2454                         np->get_tx.orig = np->first_tx.orig;
2455                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2456                         np->get_tx_ctx = np->first_tx_ctx;
2457         }
2458         if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2459                 np->tx_stop = 0;
2460                 netif_wake_queue(dev);
2461         }
2462         return tx_work;
2463 }
2464
2465 static int nv_tx_done_optimized(struct net_device *dev, int limit)
2466 {
2467         struct fe_priv *np = netdev_priv(dev);
2468         u32 flags;
2469         int tx_work = 0;
2470         struct ring_desc_ex* orig_get_tx = np->get_tx.ex;
2471
2472         while ((np->get_tx.ex != np->put_tx.ex) &&
2473                !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX2_VALID) &&
2474                (tx_work < limit)) {
2475
2476                 dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n",
2477                                         dev->name, flags);
2478
2479                 nv_unmap_txskb(np, np->get_tx_ctx);
2480
2481                 if (flags & NV_TX2_LASTPACKET) {
2482                         if (!(flags & NV_TX2_ERROR))
2483                                 dev->stats.tx_packets++;
2484                         else {
2485                                 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2486                                         if (np->driver_data & DEV_HAS_GEAR_MODE)
2487                                                 nv_gear_backoff_reseed(dev);
2488                                         else
2489                                                 nv_legacybackoff_reseed(dev);
2490                                 }
2491                         }
2492
2493                         dev_kfree_skb_any(np->get_tx_ctx->skb);
2494                         np->get_tx_ctx->skb = NULL;
2495                         tx_work++;
2496
2497                         if (np->tx_limit) {
2498                                 nv_tx_flip_ownership(dev);
2499                         }
2500                 }
2501                 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2502                         np->get_tx.ex = np->first_tx.ex;
2503                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2504                         np->get_tx_ctx = np->first_tx_ctx;
2505         }
2506         if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2507                 np->tx_stop = 0;
2508                 netif_wake_queue(dev);
2509         }
2510         return tx_work;
2511 }
2512
2513 /*
2514  * nv_tx_timeout: dev->tx_timeout function
2515  * Called with netif_tx_lock held.
2516  */
2517 static void nv_tx_timeout(struct net_device *dev)
2518 {
2519         struct fe_priv *np = netdev_priv(dev);
2520         u8 __iomem *base = get_hwbase(dev);
2521         u32 status;
2522         union ring_type put_tx;
2523         int saved_tx_limit;
2524
2525         if (np->msi_flags & NV_MSI_X_ENABLED)
2526                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2527         else
2528                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2529
2530         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
2531
2532         {
2533                 int i;
2534
2535                 printk(KERN_INFO "%s: Ring at %lx\n",
2536                        dev->name, (unsigned long)np->ring_addr);
2537                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
2538                 for (i=0;i<=np->register_size;i+= 32) {
2539                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2540                                         i,
2541                                         readl(base + i + 0), readl(base + i + 4),
2542                                         readl(base + i + 8), readl(base + i + 12),
2543                                         readl(base + i + 16), readl(base + i + 20),
2544                                         readl(base + i + 24), readl(base + i + 28));
2545                 }
2546                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
2547                 for (i=0;i<np->tx_ring_size;i+= 4) {
2548                         if (!nv_optimized(np)) {
2549                                 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2550                                        i,
2551                                        le32_to_cpu(np->tx_ring.orig[i].buf),
2552                                        le32_to_cpu(np->tx_ring.orig[i].flaglen),
2553                                        le32_to_cpu(np->tx_ring.orig[i+1].buf),
2554                                        le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2555                                        le32_to_cpu(np->tx_ring.orig[i+2].buf),
2556                                        le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2557                                        le32_to_cpu(np->tx_ring.orig[i+3].buf),
2558                                        le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2559                         } else {
2560                                 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2561                                        i,
2562                                        le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2563                                        le32_to_cpu(np->tx_ring.ex[i].buflow),
2564                                        le32_to_cpu(np->tx_ring.ex[i].flaglen),
2565                                        le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2566                                        le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2567                                        le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2568                                        le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2569                                        le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2570                                        le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2571                                        le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2572                                        le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2573                                        le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2574                         }
2575                 }
2576         }
2577
2578         spin_lock_irq(&np->lock);
2579
2580         /* 1) stop tx engine */
2581         nv_stop_tx(dev);
2582
2583         /* 2) complete any outstanding tx and do not give HW any limited tx pkts */
2584         saved_tx_limit = np->tx_limit;
2585         np->tx_limit = 0; /* prevent giving HW any limited pkts */
2586         np->tx_stop = 0;  /* prevent waking tx queue */
2587         if (!nv_optimized(np))
2588                 nv_tx_done(dev, np->tx_ring_size);
2589         else
2590                 nv_tx_done_optimized(dev, np->tx_ring_size);
2591
2592         /* save current HW postion */
2593         if (np->tx_change_owner)
2594                 put_tx.ex = np->tx_change_owner->first_tx_desc;
2595         else
2596                 put_tx = np->put_tx;
2597
2598         /* 3) clear all tx state */
2599         nv_drain_tx(dev);
2600         nv_init_tx(dev);
2601
2602         /* 4) restore state to current HW position */
2603         np->get_tx = np->put_tx = put_tx;
2604         np->tx_limit = saved_tx_limit;
2605
2606         /* 5) restart tx engine */
2607         nv_start_tx(dev);
2608         netif_wake_queue(dev);
2609         spin_unlock_irq(&np->lock);
2610 }
2611
2612 /*
2613  * Called when the nic notices a mismatch between the actual data len on the
2614  * wire and the len indicated in the 802 header
2615  */
2616 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2617 {
2618         int hdrlen;     /* length of the 802 header */
2619         int protolen;   /* length as stored in the proto field */
2620
2621         /* 1) calculate len according to header */
2622         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2623                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
2624                 hdrlen = VLAN_HLEN;
2625         } else {
2626                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
2627                 hdrlen = ETH_HLEN;
2628         }
2629         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
2630                                 dev->name, datalen, protolen, hdrlen);
2631         if (protolen > ETH_DATA_LEN)
2632                 return datalen; /* Value in proto field not a len, no checks possible */
2633
2634         protolen += hdrlen;
2635         /* consistency checks: */
2636         if (datalen > ETH_ZLEN) {
2637                 if (datalen >= protolen) {
2638                         /* more data on wire than in 802 header, trim of
2639                          * additional data.
2640                          */
2641                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2642                                         dev->name, protolen);
2643                         return protolen;
2644                 } else {
2645                         /* less data on wire than mentioned in header.
2646                          * Discard the packet.
2647                          */
2648                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
2649                                         dev->name);
2650                         return -1;
2651                 }
2652         } else {
2653                 /* short packet. Accept only if 802 values are also short */
2654                 if (protolen > ETH_ZLEN) {
2655                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
2656                                         dev->name);
2657                         return -1;
2658                 }
2659                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2660                                 dev->name, datalen);
2661                 return datalen;
2662         }
2663 }
2664
2665 static int nv_rx_process(struct net_device *dev, int limit)
2666 {
2667         struct fe_priv *np = netdev_priv(dev);
2668         u32 flags;
2669         int rx_work = 0;
2670         struct sk_buff *skb;
2671         int len;
2672
2673         while((np->get_rx.orig != np->put_rx.orig) &&
2674               !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2675                 (rx_work < limit)) {
2676
2677                 dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
2678                                         dev->name, flags);
2679
2680                 /*
2681                  * the packet is for us - immediately tear down the pci mapping.
2682                  * TODO: check if a prefetch of the first cacheline improves
2683                  * the performance.
2684                  */
2685                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2686                                 np->get_rx_ctx->dma_len,
2687                                 PCI_DMA_FROMDEVICE);
2688                 skb = np->get_rx_ctx->skb;
2689                 np->get_rx_ctx->skb = NULL;
2690
2691                 {
2692                         int j;
2693                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2694                         for (j=0; j<64; j++) {
2695                                 if ((j%16) == 0)
2696                                         dprintk("\n%03x:", j);
2697                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2698                         }
2699                         dprintk("\n");
2700                 }
2701                 /* look at what we actually got: */
2702                 if (np->desc_ver == DESC_VER_1) {
2703                         if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2704                                 len = flags & LEN_MASK_V1;
2705                                 if (unlikely(flags & NV_RX_ERROR)) {
2706                                         if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
2707                                                 len = nv_getlen(dev, skb->data, len);
2708                                                 if (len < 0) {
2709                                                         dev->stats.rx_errors++;
2710                                                         dev_kfree_skb(skb);
2711                                                         goto next_pkt;
2712                                                 }
2713                                         }
2714                                         /* framing errors are soft errors */
2715                                         else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
2716                                                 if (flags & NV_RX_SUBSTRACT1) {
2717                                                         len--;
2718                                                 }
2719                                         }
2720                                         /* the rest are hard errors */
2721                                         else {
2722                                                 if (flags & NV_RX_MISSEDFRAME)
2723                                                         dev->stats.rx_missed_errors++;
2724                                                 if (flags & NV_RX_CRCERR)
2725                                                         dev->stats.rx_crc_errors++;
2726                                                 if (flags & NV_RX_OVERFLOW)
2727                                                         dev->stats.rx_over_errors++;
2728                                                 dev->stats.rx_errors++;
2729                                                 dev_kfree_skb(skb);
2730                                                 goto next_pkt;
2731                                         }
2732                                 }
2733                         } else {
2734                                 dev_kfree_skb(skb);
2735                                 goto next_pkt;
2736                         }
2737                 } else {
2738                         if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2739                                 len = flags & LEN_MASK_V2;
2740                                 if (unlikely(flags & NV_RX2_ERROR)) {
2741                                         if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2742                                                 len = nv_getlen(dev, skb->data, len);
2743                                                 if (len < 0) {
2744                                                         dev->stats.rx_errors++;
2745                                                         dev_kfree_skb(skb);
2746                                                         goto next_pkt;
2747                                                 }
2748                                         }
2749                                         /* framing errors are soft errors */
2750                                         else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2751                                                 if (flags & NV_RX2_SUBSTRACT1) {
2752                                                         len--;
2753                                                 }
2754                                         }
2755                                         /* the rest are hard errors */
2756                                         else {
2757                                                 if (flags & NV_RX2_CRCERR)
2758                                                         dev->stats.rx_crc_errors++;
2759                                                 if (flags & NV_RX2_OVERFLOW)
2760                                                         dev->stats.rx_over_errors++;
2761                                                 dev->stats.rx_errors++;
2762                                                 dev_kfree_skb(skb);
2763                                                 goto next_pkt;
2764                                         }
2765                                 }
2766                                 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2767                                     ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2768                                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2769                         } else {
2770                                 dev_kfree_skb(skb);
2771                                 goto next_pkt;
2772                         }
2773                 }
2774                 /* got a valid packet - forward it to the network core */
2775                 skb_put(skb, len);
2776                 skb->protocol = eth_type_trans(skb, dev);
2777                 dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2778                                         dev->name, len, skb->protocol);
2779                 napi_gro_receive(&np->napi, skb);
2780                 dev->stats.rx_packets++;
2781                 dev->stats.rx_bytes += len;
2782 next_pkt:
2783                 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2784                         np->get_rx.orig = np->first_rx.orig;
2785                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2786                         np->get_rx_ctx = np->first_rx_ctx;
2787
2788                 rx_work++;
2789         }
2790
2791         return rx_work;
2792 }
2793
2794 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2795 {
2796         struct fe_priv *np = netdev_priv(dev);
2797         u32 flags;
2798         u32 vlanflags = 0;
2799         int rx_work = 0;
2800         struct sk_buff *skb;
2801         int len;
2802
2803         while((np->get_rx.ex != np->put_rx.ex) &&
2804               !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2805               (rx_work < limit)) {
2806
2807                 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n",
2808                                         dev->name, flags);
2809
2810                 /*
2811                  * the packet is for us - immediately tear down the pci mapping.
2812                  * TODO: check if a prefetch of the first cacheline improves
2813                  * the performance.
2814                  */
2815                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2816                                 np->get_rx_ctx->dma_len,
2817                                 PCI_DMA_FROMDEVICE);
2818                 skb = np->get_rx_ctx->skb;
2819                 np->get_rx_ctx->skb = NULL;
2820
2821                 {
2822                         int j;
2823                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2824                         for (j=0; j<64; j++) {
2825                                 if ((j%16) == 0)
2826                                         dprintk("\n%03x:", j);
2827                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2828                         }
2829                         dprintk("\n");
2830                 }
2831                 /* look at what we actually got: */
2832                 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2833                         len = flags & LEN_MASK_V2;
2834                         if (unlikely(flags & NV_RX2_ERROR)) {
2835                                 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2836                                         len = nv_getlen(dev, skb->data, len);
2837                                         if (len < 0) {
2838                                                 dev_kfree_skb(skb);
2839                                                 goto next_pkt;
2840                                         }
2841                                 }
2842                                 /* framing errors are soft errors */
2843                                 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2844                                         if (flags & NV_RX2_SUBSTRACT1) {
2845                                                 len--;
2846                                         }
2847                                 }
2848                                 /* the rest are hard errors */
2849                                 else {
2850                                         dev_kfree_skb(skb);
2851                                         goto next_pkt;
2852                                 }
2853                         }
2854
2855                         if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2856                             ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2857                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2858
2859                         /* got a valid packet - forward it to the network core */
2860                         skb_put(skb, len);
2861                         skb->protocol = eth_type_trans(skb, dev);
2862                         prefetch(skb->data);
2863
2864                         dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
2865                                 dev->name, len, skb->protocol);
2866
2867                         if (likely(!np->vlangrp)) {
2868                                 napi_gro_receive(&np->napi, skb);
2869                         } else {
2870                                 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2871                                 if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2872                                         vlan_gro_receive(&np->napi, np->vlangrp,
2873                                                          vlanflags & NV_RX3_VLAN_TAG_MASK, skb);
2874                                 } else {
2875                                         napi_gro_receive(&np->napi, skb);
2876                                 }
2877                         }
2878
2879                         dev->stats.rx_packets++;
2880                         dev->stats.rx_bytes += len;
2881                 } else {
2882                         dev_kfree_skb(skb);
2883                 }
2884 next_pkt:
2885                 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2886                         np->get_rx.ex = np->first_rx.ex;
2887                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2888                         np->get_rx_ctx = np->first_rx_ctx;
2889
2890                 rx_work++;
2891         }
2892
2893         return rx_work;
2894 }
2895
2896 static void set_bufsize(struct net_device *dev)
2897 {
2898         struct fe_priv *np = netdev_priv(dev);
2899
2900         if (dev->mtu <= ETH_DATA_LEN)
2901                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2902         else
2903                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2904 }
2905
2906 /*
2907  * nv_change_mtu: dev->change_mtu function
2908  * Called with dev_base_lock held for read.
2909  */
2910 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2911 {
2912         struct fe_priv *np = netdev_priv(dev);
2913         int old_mtu;
2914
2915         if (new_mtu < 64 || new_mtu > np->pkt_limit)
2916                 return -EINVAL;
2917
2918         old_mtu = dev->mtu;
2919         dev->mtu = new_mtu;
2920
2921         /* return early if the buffer sizes will not change */
2922         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2923                 return 0;
2924         if (old_mtu == new_mtu)
2925                 return 0;
2926
2927         /* synchronized against open : rtnl_lock() held by caller */
2928         if (netif_running(dev)) {
2929                 u8 __iomem *base = get_hwbase(dev);
2930                 /*
2931                  * It seems that the nic preloads valid ring entries into an
2932                  * internal buffer. The procedure for flushing everything is
2933                  * guessed, there is probably a simpler approach.
2934                  * Changing the MTU is a rare event, it shouldn't matter.
2935                  */
2936                 nv_disable_irq(dev);
2937                 nv_napi_disable(dev);
2938                 netif_tx_lock_bh(dev);
2939                 netif_addr_lock(dev);
2940                 spin_lock(&np->lock);
2941                 /* stop engines */
2942                 nv_stop_rxtx(dev);
2943                 nv_txrx_reset(dev);
2944                 /* drain rx queue */
2945                 nv_drain_rxtx(dev);
2946                 /* reinit driver view of the rx queue */
2947                 set_bufsize(dev);
2948                 if (nv_init_ring(dev)) {
2949                         if (!np->in_shutdown)
2950                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2951                 }
2952                 /* reinit nic view of the rx queue */
2953                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2954                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2955                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2956                         base + NvRegRingSizes);
2957                 pci_push(base);
2958                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2959                 pci_push(base);
2960
2961                 /* restart rx engine */
2962                 nv_start_rxtx(dev);
2963                 spin_unlock(&np->lock);
2964                 netif_addr_unlock(dev);
2965                 netif_tx_unlock_bh(dev);
2966                 nv_napi_enable(dev);
2967                 nv_enable_irq(dev);
2968         }
2969         return 0;
2970 }
2971
2972 static void nv_copy_mac_to_hw(struct net_device *dev)
2973 {
2974         u8 __iomem *base = get_hwbase(dev);
2975         u32 mac[2];
2976
2977         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2978                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2979         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2980
2981         writel(mac[0], base + NvRegMacAddrA);
2982         writel(mac[1], base + NvRegMacAddrB);
2983 }
2984
2985 /*
2986  * nv_set_mac_address: dev->set_mac_address function
2987  * Called with rtnl_lock() held.
2988  */
2989 static int nv_set_mac_address(struct net_device *dev, void *addr)
2990 {
2991         struct fe_priv *np = netdev_priv(dev);
2992         struct sockaddr *macaddr = (struct sockaddr*)addr;
2993
2994         if (!is_valid_ether_addr(macaddr->sa_data))
2995                 return -EADDRNOTAVAIL;
2996
2997         /* synchronized against open : rtnl_lock() held by caller */
2998         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2999
3000         if (netif_running(dev)) {
3001                 netif_tx_lock_bh(dev);
3002                 netif_addr_lock(dev);
3003                 spin_lock_irq(&np->lock);
3004
3005                 /* stop rx engine */
3006                 nv_stop_rx(dev);
3007
3008                 /* set mac address */
3009                 nv_copy_mac_to_hw(dev);
3010
3011                 /* restart rx engine */
3012                 nv_start_rx(dev);
3013                 spin_unlock_irq(&np->lock);
3014                 netif_addr_unlock(dev);
3015                 netif_tx_unlock_bh(dev);
3016         } else {
3017                 nv_copy_mac_to_hw(dev);
3018         }
3019         return 0;
3020 }
3021
3022 /*
3023  * nv_set_multicast: dev->set_multicast function
3024  * Called with netif_tx_lock held.
3025  */
3026 static void nv_set_multicast(struct net_device *dev)
3027 {
3028         struct fe_priv *np = netdev_priv(dev);
3029         u8 __iomem *base = get_hwbase(dev);
3030         u32 addr[2];
3031         u32 mask[2];
3032         u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
3033
3034         memset(addr, 0, sizeof(addr));
3035         memset(mask, 0, sizeof(mask));
3036
3037         if (dev->flags & IFF_PROMISC) {
3038                 pff |= NVREG_PFF_PROMISC;
3039         } else {
3040                 pff |= NVREG_PFF_MYADDR;
3041
3042                 if (dev->flags & IFF_ALLMULTI || !netdev_mc_empty(dev)) {
3043                         u32 alwaysOff[2];
3044                         u32 alwaysOn[2];
3045
3046                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
3047                         if (dev->flags & IFF_ALLMULTI) {
3048                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
3049                         } else {
3050                                 struct netdev_hw_addr *ha;
3051
3052                                 netdev_for_each_mc_addr(ha, dev) {
3053                                         unsigned char *addr = ha->addr;
3054                                         u32 a, b;
3055
3056                                         a = le32_to_cpu(*(__le32 *) addr);
3057                                         b = le16_to_cpu(*(__le16 *) (&addr[4]));
3058                                         alwaysOn[0] &= a;
3059                                         alwaysOff[0] &= ~a;
3060                                         alwaysOn[1] &= b;
3061                                         alwaysOff[1] &= ~b;
3062                                 }
3063                         }
3064                         addr[0] = alwaysOn[0];
3065                         addr[1] = alwaysOn[1];
3066                         mask[0] = alwaysOn[0] | alwaysOff[0];
3067                         mask[1] = alwaysOn[1] | alwaysOff[1];
3068                 } else {
3069                         mask[0] = NVREG_MCASTMASKA_NONE;
3070                         mask[1] = NVREG_MCASTMASKB_NONE;
3071                 }
3072         }
3073         addr[0] |= NVREG_MCASTADDRA_FORCE;
3074         pff |= NVREG_PFF_ALWAYS;
3075         spin_lock_irq(&np->lock);
3076         nv_stop_rx(dev);
3077         writel(addr[0], base + NvRegMulticastAddrA);
3078         writel(addr[1], base + NvRegMulticastAddrB);
3079         writel(mask[0], base + NvRegMulticastMaskA);
3080         writel(mask[1], base + NvRegMulticastMaskB);
3081         writel(pff, base + NvRegPacketFilterFlags);
3082         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
3083                 dev->name);
3084         nv_start_rx(dev);
3085         spin_unlock_irq(&np->lock);
3086 }
3087
3088 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
3089 {
3090         struct fe_priv *np = netdev_priv(dev);
3091         u8 __iomem *base = get_hwbase(dev);
3092
3093         np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
3094
3095         if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
3096                 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
3097                 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
3098                         writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
3099                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3100                 } else {
3101                         writel(pff, base + NvRegPacketFilterFlags);
3102                 }
3103         }
3104         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
3105                 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
3106                 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
3107                         u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
3108                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
3109                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
3110                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
3111                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
3112                                 /* limit the number of tx pause frames to a default of 8 */
3113                                 writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
3114                         }
3115                         writel(pause_enable,  base + NvRegTxPauseFrame);
3116                         writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3117                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3118                 } else {
3119                         writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
3120                         writel(regmisc, base + NvRegMisc1);
3121                 }
3122         }
3123 }
3124
3125 /**
3126  * nv_update_linkspeed: Setup the MAC according to the link partner
3127  * @dev: Network device to be configured
3128  *
3129  * The function queries the PHY and checks if there is a link partner.
3130  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3131  * set to 10 MBit HD.
3132  *
3133  * The function returns 0 if there is no link partner and 1 if there is
3134  * a good link partner.
3135  */
3136 static int nv_update_linkspeed(struct net_device *dev)
3137 {
3138         struct fe_priv *np = netdev_priv(dev);
3139         u8 __iomem *base = get_hwbase(dev);
3140         int adv = 0;
3141         int lpa = 0;
3142         int adv_lpa, adv_pause, lpa_pause;
3143         int newls = np->linkspeed;
3144         int newdup = np->duplex;
3145         int mii_status;
3146         int retval = 0;
3147         u32 control_1000, status_1000, phyreg, pause_flags, txreg;
3148         u32 txrxFlags = 0;
3149         u32 phy_exp;
3150
3151         /* BMSR_LSTATUS is latched, read it twice:
3152          * we want the current value.
3153          */
3154         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3155         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3156
3157         if (!(mii_status & BMSR_LSTATUS)) {
3158                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
3159                                 dev->name);
3160                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3161                 newdup = 0;
3162                 retval = 0;
3163                 goto set_speed;
3164         }
3165
3166         if (np->autoneg == 0) {
3167                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
3168                                 dev->name, np->fixed_mode);
3169                 if (np->fixed_mode & LPA_100FULL) {
3170                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3171                         newdup = 1;
3172                 } else if (np->fixed_mode & LPA_100HALF) {
3173                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3174                         newdup = 0;
3175                 } else if (np->fixed_mode & LPA_10FULL) {
3176                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3177                         newdup = 1;
3178                 } else {
3179                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3180                         newdup = 0;
3181                 }
3182                 retval = 1;
3183                 goto set_speed;
3184         }
3185         /* check auto negotiation is complete */
3186         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3187                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3188                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3189                 newdup = 0;
3190                 retval = 0;
3191                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
3192                 goto set_speed;
3193         }
3194
3195         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3196         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3197         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
3198                                 dev->name, adv, lpa);
3199
3200         retval = 1;
3201         if (np->gigabit == PHY_GIGABIT) {
3202                 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3203                 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
3204
3205                 if ((control_1000 & ADVERTISE_1000FULL) &&
3206                         (status_1000 & LPA_1000FULL)) {
3207                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
3208                                 dev->name);
3209                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3210                         newdup = 1;
3211                         goto set_speed;
3212                 }
3213         }
3214
3215         /* FIXME: handle parallel detection properly */
3216         adv_lpa = lpa & adv;
3217         if (adv_lpa & LPA_100FULL) {
3218                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3219                 newdup = 1;
3220         } else if (adv_lpa & LPA_100HALF) {
3221                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3222                 newdup = 0;
3223         } else if (adv_lpa & LPA_10FULL) {
3224                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3225                 newdup = 1;
3226         } else if (adv_lpa & LPA_10HALF) {
3227                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3228                 newdup = 0;
3229         } else {
3230                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
3231                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3232                 newdup = 0;
3233         }
3234
3235 set_speed:
3236         if (np->duplex == newdup && np->linkspeed == newls)
3237                 return retval;
3238
3239         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
3240                         dev->name, np->linkspeed, np->duplex, newls, newdup);
3241
3242         np->duplex = newdup;
3243         np->linkspeed = newls;
3244
3245         /* The transmitter and receiver must be restarted for safe update */
3246         if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3247                 txrxFlags |= NV_RESTART_TX;
3248                 nv_stop_tx(dev);
3249         }
3250         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3251                 txrxFlags |= NV_RESTART_RX;
3252                 nv_stop_rx(dev);
3253         }
3254
3255         if (np->gigabit == PHY_GIGABIT) {
3256                 phyreg = readl(base + NvRegSlotTime);
3257                 phyreg &= ~(0x3FF00);
3258                 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3259                     ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3260                         phyreg |= NVREG_SLOTTIME_10_100_FULL;
3261                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3262                         phyreg |= NVREG_SLOTTIME_1000_FULL;
3263                 writel(phyreg, base + NvRegSlotTime);
3264         }
3265
3266         phyreg = readl(base + NvRegPhyInterface);
3267         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3268         if (np->duplex == 0)
3269                 phyreg |= PHY_HALF;
3270         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3271                 phyreg |= PHY_100;
3272         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3273                 phyreg |= PHY_1000;
3274         writel(phyreg, base + NvRegPhyInterface);
3275
3276         phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
3277         if (phyreg & PHY_RGMII) {
3278                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
3279                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3280                 } else {
3281                         if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3282                                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3283                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3284                                 else
3285                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3286                         } else {
3287                                 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3288                         }
3289                 }
3290         } else {
3291                 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3292                         txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3293                 else
3294                         txreg = NVREG_TX_DEFERRAL_DEFAULT;
3295         }
3296         writel(txreg, base + NvRegTxDeferral);
3297
3298         if (np->desc_ver == DESC_VER_1) {
3299                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3300         } else {
3301                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3302                         txreg = NVREG_TX_WM_DESC2_3_1000;
3303                 else
3304                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3305         }
3306         writel(txreg, base + NvRegTxWatermark);
3307
3308         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
3309                 base + NvRegMisc1);
3310         pci_push(base);
3311         writel(np->linkspeed, base + NvRegLinkSpeed);
3312         pci_push(base);
3313
3314         pause_flags = 0;
3315         /* setup pause frame */
3316         if (np->duplex != 0) {
3317                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3318                         adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
3319                         lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
3320
3321                         switch (adv_pause) {
3322                         case ADVERTISE_PAUSE_CAP:
3323                                 if (lpa_pause & LPA_PAUSE_CAP) {
3324                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3325                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3326                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3327                                 }
3328                                 break;
3329                         case ADVERTISE_PAUSE_ASYM:
3330                                 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
3331                                 {
3332                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3333                                 }
3334                                 break;
3335                         case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
3336                                 if (lpa_pause & LPA_PAUSE_CAP)
3337                                 {
3338                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
3339                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3340                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3341                                 }
3342                                 if (lpa_pause == LPA_PAUSE_ASYM)
3343                                 {
3344                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3345                                 }
3346                                 break;
3347                         }
3348                 } else {
3349                         pause_flags = np->pause_flags;
3350                 }
3351         }
3352         nv_update_pause(dev, pause_flags);
3353
3354         if (txrxFlags & NV_RESTART_TX)
3355                 nv_start_tx(dev);
3356         if (txrxFlags & NV_RESTART_RX)
3357                 nv_start_rx(dev);
3358
3359         return retval;
3360 }
3361
3362 static void nv_linkchange(struct net_device *dev)
3363 {
3364         if (nv_update_linkspeed(dev)) {
3365                 if (!netif_carrier_ok(dev)) {
3366                         netif_carrier_on(dev);
3367                         printk(KERN_INFO "%s: link up.\n", dev->name);
3368                         nv_txrx_gate(dev, false);
3369                         nv_start_rx(dev);
3370                 }
3371         } else {
3372                 if (netif_carrier_ok(dev)) {
3373                         netif_carrier_off(dev);
3374                         printk(KERN_INFO "%s: link down.\n", dev->name);
3375                         nv_txrx_gate(dev, true);
3376                         nv_stop_rx(dev);
3377                 }
3378         }
3379 }
3380
3381 static void nv_link_irq(struct net_device *dev)
3382 {
3383         u8 __iomem *base = get_hwbase(dev);
3384         u32 miistat;
3385
3386         miistat = readl(base + NvRegMIIStatus);
3387         writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3388         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
3389
3390         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3391                 nv_linkchange(dev);
3392         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
3393 }
3394
3395 static void nv_msi_workaround(struct fe_priv *np)
3396 {
3397
3398         /* Need to toggle the msi irq mask within the ethernet device,
3399          * otherwise, future interrupts will not be detected.
3400          */
3401         if (np->msi_flags & NV_MSI_ENABLED) {
3402                 u8 __iomem *base = np->base;
3403
3404                 writel(0, base + NvRegMSIIrqMask);
3405                 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3406         }
3407 }
3408
3409 static inline int nv_change_interrupt_mode(struct net_device *dev, int total_work)
3410 {
3411         struct fe_priv *np = netdev_priv(dev);
3412
3413         if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC) {
3414                 if (total_work > NV_DYNAMIC_THRESHOLD) {
3415                         /* transition to poll based interrupts */
3416                         np->quiet_count = 0;
3417                         if (np->irqmask != NVREG_IRQMASK_CPU) {
3418                                 np->irqmask = NVREG_IRQMASK_CPU;
3419                                 return 1;
3420                         }
3421                 } else {
3422                         if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) {
3423                                 np->quiet_count++;
3424                         } else {
3425                                 /* reached a period of low activity, switch
3426                                    to per tx/rx packet interrupts */
3427                                 if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) {
3428                                         np->irqmask = NVREG_IRQMASK_THROUGHPUT;
3429                                         return 1;
3430                                 }
3431                         }
3432                 }
3433         }
3434         return 0;
3435 }
3436
3437 static irqreturn_t nv_nic_irq(int foo, void *data)
3438 {
3439         struct net_device *dev = (struct net_device *) data;
3440         struct fe_priv *np = netdev_priv(dev);
3441         u8 __iomem *base = get_hwbase(dev);
3442
3443         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
3444
3445         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3446                 np->events = readl(base + NvRegIrqStatus);
3447                 writel(np->events, base + NvRegIrqStatus);
3448         } else {
3449                 np->events = readl(base + NvRegMSIXIrqStatus);
3450                 writel(np->events, base + NvRegMSIXIrqStatus);
3451         }
3452         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, np->events);
3453         if (!(np->events & np->irqmask))
3454                 return IRQ_NONE;
3455
3456         nv_msi_workaround(np);
3457
3458         if (napi_schedule_prep(&np->napi)) {
3459                 /*
3460                  * Disable further irq's (msix not enabled with napi)
3461                  */
3462                 writel(0, base + NvRegIrqMask);
3463                 __napi_schedule(&np->napi);
3464         }
3465
3466         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
3467
3468         return IRQ_HANDLED;
3469 }
3470
3471 /**
3472  * All _optimized functions are used to help increase performance
3473  * (reduce CPU and increase throughput). They use descripter version 3,
3474  * compiler directives, and reduce memory accesses.
3475  */
3476 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3477 {
3478         struct net_device *dev = (struct net_device *) data;
3479         struct fe_priv *np = netdev_priv(dev);
3480         u8 __iomem *base = get_hwbase(dev);
3481
3482         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name);
3483
3484         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3485                 np->events = readl(base + NvRegIrqStatus);
3486                 writel(np->events, base + NvRegIrqStatus);
3487         } else {
3488                 np->events = readl(base + NvRegMSIXIrqStatus);
3489                 writel(np->events, base + NvRegMSIXIrqStatus);
3490         }
3491         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, np->events);
3492         if (!(np->events & np->irqmask))
3493                 return IRQ_NONE;
3494
3495         nv_msi_workaround(np);
3496
3497         if (napi_schedule_prep(&np->napi)) {
3498                 /*
3499                  * Disable further irq's (msix not enabled with napi)
3500                  */
3501                 writel(0, base + NvRegIrqMask);
3502                 __napi_schedule(&np->napi);
3503         }
3504         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name);
3505
3506         return IRQ_HANDLED;
3507 }
3508
3509 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3510 {
3511         struct net_device *dev = (struct net_device *) data;
3512         struct fe_priv *np = netdev_priv(dev);
3513         u8 __iomem *base = get_hwbase(dev);
3514         u32 events;
3515         int i;
3516         unsigned long flags;
3517
3518         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
3519
3520         for (i=0; ; i++) {
3521                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3522                 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
3523                 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
3524                 if (!(events & np->irqmask))
3525                         break;
3526
3527                 spin_lock_irqsave(&np->lock, flags);
3528                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3529                 spin_unlock_irqrestore(&np->lock, flags);
3530
3531                 if (unlikely(i > max_interrupt_work)) {
3532                         spin_lock_irqsave(&np->lock, flags);
3533                         /* disable interrupts on the nic */
3534                         writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3535                         pci_push(base);
3536
3537                         if (!np->in_shutdown) {
3538                                 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3539                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3540                         }
3541                         spin_unlock_irqrestore(&np->lock, flags);
3542                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
3543                         break;
3544                 }
3545
3546         }
3547         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
3548
3549         return IRQ_RETVAL(i);
3550 }
3551
3552 static int nv_napi_poll(struct napi_struct *napi, int budget)
3553 {
3554         struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3555         struct net_device *dev = np->dev;
3556         u8 __iomem *base = get_hwbase(dev);
3557         unsigned long flags;
3558         int retcode;
3559         int rx_count, tx_work=0, rx_work=0;
3560
3561         do {
3562                 if (!nv_optimized(np)) {
3563                         spin_lock_irqsave(&np->lock, flags);
3564                         tx_work += nv_tx_done(dev, np->tx_ring_size);
3565                         spin_unlock_irqrestore(&np->lock, flags);
3566
3567                         rx_count = nv_rx_process(dev, budget - rx_work);
3568                         retcode = nv_alloc_rx(dev);
3569                 } else {
3570                         spin_lock_irqsave(&np->lock, flags);
3571                         tx_work += nv_tx_done_optimized(dev, np->tx_ring_size);
3572                         spin_unlock_irqrestore(&np->lock, flags);
3573
3574                         rx_count = nv_rx_process_optimized(dev,
3575                             budget - rx_work);
3576                         retcode = nv_alloc_rx_optimized(dev);
3577                 }
3578         } while (retcode == 0 &&
3579                  rx_count > 0 && (rx_work += rx_count) < budget);
3580
3581         if (retcode) {
3582                 spin_lock_irqsave(&np->lock, flags);
3583                 if (!np->in_shutdown)
3584                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3585                 spin_unlock_irqrestore(&np->lock, flags);
3586         }
3587
3588         nv_change_interrupt_mode(dev, tx_work + rx_work);
3589
3590         if (unlikely(np->events & NVREG_IRQ_LINK)) {
3591                 spin_lock_irqsave(&np->lock, flags);
3592                 nv_link_irq(dev);
3593                 spin_unlock_irqrestore(&np->lock, flags);
3594         }
3595         if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3596                 spin_lock_irqsave(&np->lock, flags);
3597                 nv_linkchange(dev);
3598                 spin_unlock_irqrestore(&np->lock, flags);
3599                 np->link_timeout = jiffies + LINK_TIMEOUT;
3600         }
3601         if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3602                 spin_lock_irqsave(&np->lock, flags);
3603                 if (!np->in_shutdown) {
3604                         np->nic_poll_irq = np->irqmask;
3605                         np->recover_error = 1;
3606                         mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3607                 }
3608                 spin_unlock_irqrestore(&np->lock, flags);
3609                 napi_complete(napi);
3610                 return rx_work;
3611         }
3612
3613         if (rx_work < budget) {
3614                 /* re-enable interrupts
3615                    (msix not enabled in napi) */
3616                 napi_complete(napi);
3617
3618                 writel(np->irqmask, base + NvRegIrqMask);
3619         }
3620         return rx_work;
3621 }
3622
3623 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3624 {
3625         struct net_device *dev = (struct net_device *) data;
3626         struct fe_priv *np = netdev_priv(dev);
3627         u8 __iomem *base = get_hwbase(dev);
3628         u32 events;
3629         int i;
3630         unsigned long flags;
3631
3632         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
3633
3634         for (i=0; ; i++) {
3635                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3636                 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3637                 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
3638                 if (!(events & np->irqmask))
3639                         break;
3640
3641                 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3642                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3643                                 spin_lock_irqsave(&np->lock, flags);
3644                                 if (!np->in_shutdown)
3645                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3646                                 spin_unlock_irqrestore(&np->lock, flags);
3647                         }
3648                 }
3649
3650                 if (unlikely(i > max_interrupt_work)) {
3651                         spin_lock_irqsave(&np->lock, flags);
3652                         /* disable interrupts on the nic */
3653                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3654                         pci_push(base);
3655
3656                         if (!np->in_shutdown) {
3657                                 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3658                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3659                         }
3660                         spin_unlock_irqrestore(&np->lock, flags);
3661                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
3662                         break;
3663                 }
3664         }
3665         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
3666
3667         return IRQ_RETVAL(i);
3668 }
3669
3670 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3671 {
3672         struct net_device *dev = (struct net_device *) data;
3673         struct fe_priv *np = netdev_priv(dev);
3674         u8 __iomem *base = get_hwbase(dev);
3675         u32 events;
3676         int i;
3677         unsigned long flags;
3678
3679         dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
3680
3681         for (i=0; ; i++) {
3682                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3683                 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
3684                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3685                 if (!(events & np->irqmask))
3686                         break;
3687
3688                 /* check tx in case we reached max loop limit in tx isr */
3689                 spin_lock_irqsave(&np->lock, flags);
3690                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3691                 spin_unlock_irqrestore(&np->lock, flags);
3692
3693                 if (events & NVREG_IRQ_LINK) {
3694                         spin_lock_irqsave(&np->lock, flags);
3695                         nv_link_irq(dev);
3696                         spin_unlock_irqrestore(&np->lock, flags);
3697                 }
3698                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3699                         spin_lock_irqsave(&np->lock, flags);
3700                         nv_linkchange(dev);
3701                         spin_unlock_irqrestore(&np->lock, flags);
3702                         np->link_timeout = jiffies + LINK_TIMEOUT;
3703                 }
3704                 if (events & NVREG_IRQ_RECOVER_ERROR) {
3705                         spin_lock_irq(&np->lock);
3706                         /* disable interrupts on the nic */
3707                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3708                         pci_push(base);
3709
3710                         if (!np->in_shutdown) {
3711                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3712                                 np->recover_error = 1;
3713                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3714                         }
3715                         spin_unlock_irq(&np->lock);
3716                         break;
3717                 }
3718                 if (unlikely(i > max_interrupt_work)) {
3719                         spin_lock_irqsave(&np->lock, flags);
3720                         /* disable interrupts on the nic */
3721                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3722                         pci_push(base);
3723
3724                         if (!np->in_shutdown) {
3725                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3726                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3727                         }
3728                         spin_unlock_irqrestore(&np->lock, flags);
3729                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
3730                         break;
3731                 }
3732
3733         }
3734         dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
3735
3736         return IRQ_RETVAL(i);
3737 }
3738
3739 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3740 {
3741         struct net_device *dev = (struct net_device *) data;
3742         struct fe_priv *np = netdev_priv(dev);
3743         u8 __iomem *base = get_hwbase(dev);
3744         u32 events;
3745
3746         dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
3747
3748         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3749                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3750                 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3751         } else {
3752                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3753                 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3754         }
3755         pci_push(base);
3756         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3757         if (!(events & NVREG_IRQ_TIMER))
3758                 return IRQ_RETVAL(0);
3759
3760         nv_msi_workaround(np);
3761
3762         spin_lock(&np->lock);
3763         np->intr_test = 1;
3764         spin_unlock(&np->lock);
3765
3766         dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
3767
3768         return IRQ_RETVAL(1);
3769 }
3770
3771 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3772 {
3773         u8 __iomem *base = get_hwbase(dev);
3774         int i;
3775         u32 msixmap = 0;
3776
3777         /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3778          * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3779          * the remaining 8 interrupts.
3780          */
3781         for (i = 0; i < 8; i++) {
3782                 if ((irqmask >> i) & 0x1) {
3783                         msixmap |= vector << (i << 2);
3784                 }
3785         }
3786         writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3787
3788         msixmap = 0;
3789         for (i = 0; i < 8; i++) {
3790                 if ((irqmask >> (i + 8)) & 0x1) {
3791                         msixmap |= vector << (i << 2);
3792                 }
3793         }
3794         writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3795 }
3796
3797 static int nv_request_irq(struct net_device *dev, int intr_test)
3798 {
3799         struct fe_priv *np = get_nvpriv(dev);
3800         u8 __iomem *base = get_hwbase(dev);
3801         int ret = 1;
3802         int i;
3803         irqreturn_t (*handler)(int foo, void *data);
3804
3805         if (intr_test) {
3806                 handler = nv_nic_irq_test;
3807         } else {
3808                 if (nv_optimized(np))
3809                         handler = nv_nic_irq_optimized;
3810                 else
3811                         handler = nv_nic_irq;
3812         }
3813
3814         if (np->msi_flags & NV_MSI_X_CAPABLE) {
3815                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3816                         np->msi_x_entry[i].entry = i;
3817                 }
3818                 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
3819                         np->msi_flags |= NV_MSI_X_ENABLED;
3820                         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3821                                 /* Request irq for rx handling */
3822                                 sprintf(np->name_rx, "%s-rx", dev->name);
3823                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
3824                                                 nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) {
3825                                         printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
3826                                         pci_disable_msix(np->pci_dev);
3827                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3828                                         goto out_err;
3829                                 }
3830                                 /* Request irq for tx handling */
3831                                 sprintf(np->name_tx, "%s-tx", dev->name);
3832                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
3833                                                 nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) {
3834                                         printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
3835                                         pci_disable_msix(np->pci_dev);
3836                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3837                                         goto out_free_rx;
3838                                 }
3839                                 /* Request irq for link and timer handling */
3840                                 sprintf(np->name_other, "%s-other", dev->name);
3841                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
3842                                                 nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) {
3843                                         printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
3844                                         pci_disable_msix(np->pci_dev);
3845                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3846                                         goto out_free_tx;
3847                                 }
3848                                 /* map interrupts to their respective vector */
3849                                 writel(0, base + NvRegMSIXMap0);
3850                                 writel(0, base + NvRegMSIXMap1);
3851                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3852                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3853                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3854                         } else {
3855                                 /* Request irq for all interrupts */
3856                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
3857                                         printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3858                                         pci_disable_msix(np->pci_dev);
3859                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3860                                         goto out_err;
3861                                 }
3862
3863                                 /* map interrupts to vector 0 */
3864                                 writel(0, base + NvRegMSIXMap0);
3865                                 writel(0, base + NvRegMSIXMap1);
3866                         }
3867                 }
3868         }
3869         if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
3870                 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
3871                         np->msi_flags |= NV_MSI_ENABLED;
3872                         dev->irq = np->pci_dev->irq;
3873                         if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
3874                                 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3875                                 pci_disable_msi(np->pci_dev);
3876                                 np->msi_flags &= ~NV_MSI_ENABLED;
3877                                 dev->irq = np->pci_dev->irq;
3878                                 goto out_err;
3879                         }
3880
3881                         /* map interrupts to vector 0 */
3882                         writel(0, base + NvRegMSIMap0);
3883                         writel(0, base + NvRegMSIMap1);
3884                         /* enable msi vector 0 */
3885                         writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3886                 }
3887         }
3888         if (ret != 0) {
3889                 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
3890                         goto out_err;
3891
3892         }
3893
3894         return 0;
3895 out_free_tx:
3896         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3897 out_free_rx:
3898         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3899 out_err:
3900         return 1;
3901 }
3902
3903 static void nv_free_irq(struct net_device *dev)
3904 {
3905         struct fe_priv *np = get_nvpriv(dev);
3906         int i;
3907
3908         if (np->msi_flags & NV_MSI_X_ENABLED) {
3909                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3910                         free_irq(np->msi_x_entry[i].vector, dev);
3911                 }
3912                 pci_disable_msix(np->pci_dev);
3913                 np->msi_flags &= ~NV_MSI_X_ENABLED;
3914         } else {
3915                 free_irq(np->pci_dev->irq, dev);
3916                 if (np->msi_flags & NV_MSI_ENABLED) {
3917                         pci_disable_msi(np->pci_dev);
3918                         np->msi_flags &= ~NV_MSI_ENABLED;
3919                 }
3920         }
3921 }
3922
3923 static void nv_do_nic_poll(unsigned long data)
3924 {
3925         struct net_device *dev = (struct net_device *) data;
3926         struct fe_priv *np = netdev_priv(dev);
3927         u8 __iomem *base = get_hwbase(dev);
3928         u32 mask = 0;
3929
3930         /*
3931          * First disable irq(s) and then
3932          * reenable interrupts on the nic, we have to do this before calling
3933          * nv_nic_irq because that may decide to do otherwise
3934          */
3935
3936         if (!using_multi_irqs(dev)) {
3937                 if (np->msi_flags & NV_MSI_X_ENABLED)
3938                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3939                 else
3940                         disable_irq_lockdep(np->pci_dev->irq);
3941                 mask = np->irqmask;
3942         } else {
3943                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3944                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3945                         mask |= NVREG_IRQ_RX_ALL;
3946                 }
3947                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3948                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3949                         mask |= NVREG_IRQ_TX_ALL;
3950                 }
3951                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3952                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3953                         mask |= NVREG_IRQ_OTHER;
3954                 }
3955         }
3956         /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
3957
3958         if (np->recover_error) {
3959                 np->recover_error = 0;
3960                 printk(KERN_INFO "%s: MAC in recoverable error state\n", dev->name);
3961                 if (netif_running(dev)) {
3962                         netif_tx_lock_bh(dev);
3963                         netif_addr_lock(dev);
3964                         spin_lock(&np->lock);
3965                         /* stop engines */
3966                         nv_stop_rxtx(dev);
3967                         if (np->driver_data & DEV_HAS_POWER_CNTRL)
3968                                 nv_mac_reset(dev);
3969                         nv_txrx_reset(dev);
3970                         /* drain rx queue */
3971                         nv_drain_rxtx(dev);
3972                         /* reinit driver view of the rx queue */
3973                         set_bufsize(dev);
3974                         if (nv_init_ring(dev)) {
3975                                 if (!np->in_shutdown)
3976                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3977                         }
3978                         /* reinit nic view of the rx queue */
3979                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3980                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3981                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3982                                 base + NvRegRingSizes);
3983                         pci_push(base);
3984                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3985                         pci_push(base);
3986                         /* clear interrupts */
3987                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3988                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3989                         else
3990                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3991
3992                         /* restart rx engine */
3993                         nv_start_rxtx(dev);
3994                         spin_unlock(&np->lock);
3995                         netif_addr_unlock(dev);
3996                         netif_tx_unlock_bh(dev);
3997                 }
3998         }
3999
4000         writel(mask, base + NvRegIrqMask);
4001         pci_push(base);
4002
4003         if (!using_multi_irqs(dev)) {
4004                 np->nic_poll_irq = 0;
4005                 if (nv_optimized(np))
4006                         nv_nic_irq_optimized(0, dev);
4007                 else
4008                         nv_nic_irq(0, dev);
4009                 if (np->msi_flags & NV_MSI_X_ENABLED)
4010                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
4011                 else
4012                         enable_irq_lockdep(np->pci_dev->irq);
4013         } else {
4014                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4015                         np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL;
4016                         nv_nic_irq_rx(0, dev);
4017                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4018                 }
4019                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4020                         np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL;
4021                         nv_nic_irq_tx(0, dev);
4022                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4023                 }
4024                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4025                         np->nic_poll_irq &= ~NVREG_IRQ_OTHER;
4026                         nv_nic_irq_other(0, dev);
4027                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4028                 }
4029         }
4030
4031 }
4032
4033 #ifdef CONFIG_NET_POLL_CONTROLLER
4034 static void nv_poll_controller(struct net_device *dev)
4035 {
4036         nv_do_nic_poll((unsigned long) dev);
4037 }
4038 #endif
4039
4040 static void nv_do_stats_poll(unsigned long data)
4041 {
4042         struct net_device *dev = (struct net_device *) data;
4043         struct fe_priv *np = netdev_priv(dev);
4044
4045         nv_get_hw_stats(dev);
4046
4047         if (!np->in_shutdown)
4048                 mod_timer(&np->stats_poll,
4049                         round_jiffies(jiffies + STATS_INTERVAL));
4050 }
4051
4052 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4053 {
4054         struct fe_priv *np = netdev_priv(dev);
4055         strcpy(info->driver, DRV_NAME);
4056         strcpy(info->version, FORCEDETH_VERSION);
4057         strcpy(info->bus_info, pci_name(np->pci_dev));
4058 }
4059
4060 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4061 {
4062         struct fe_priv *np = netdev_priv(dev);
4063         wolinfo->supported = WAKE_MAGIC;
4064
4065         spin_lock_irq(&np->lock);
4066         if (np->wolenabled)
4067                 wolinfo->wolopts = WAKE_MAGIC;
4068         spin_unlock_irq(&np->lock);
4069 }
4070
4071 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4072 {
4073         struct fe_priv *np = netdev_priv(dev);
4074         u8 __iomem *base = get_hwbase(dev);
4075         u32 flags = 0;
4076
4077         if (wolinfo->wolopts == 0) {
4078                 np->wolenabled = 0;
4079         } else if (wolinfo->wolopts & WAKE_MAGIC) {
4080                 np->wolenabled = 1;
4081                 flags = NVREG_WAKEUPFLAGS_ENABLE;
4082         }
4083         if (netif_running(dev)) {
4084                 spin_lock_irq(&np->lock);
4085                 writel(flags, base + NvRegWakeUpFlags);
4086                 spin_unlock_irq(&np->lock);
4087         }
4088         return 0;
4089 }
4090
4091 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4092 {
4093         struct fe_priv *np = netdev_priv(dev);
4094         int adv;
4095
4096         spin_lock_irq(&np->lock);
4097         ecmd->port = PORT_MII;
4098         if (!netif_running(dev)) {
4099                 /* We do not track link speed / duplex setting if the
4100                  * interface is disabled. Force a link check */
4101                 if (nv_update_linkspeed(dev)) {
4102                         if (!netif_carrier_ok(dev))
4103                                 netif_carrier_on(dev);
4104                 } else {
4105                         if (netif_carrier_ok(dev))
4106                                 netif_carrier_off(dev);
4107                 }
4108         }
4109
4110         if (netif_carrier_ok(dev)) {
4111                 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
4112                 case NVREG_LINKSPEED_10:
4113                         ecmd->speed = SPEED_10;
4114                         break;
4115                 case NVREG_LINKSPEED_100:
4116                         ecmd->speed = SPEED_100;
4117                         break;
4118                 case NVREG_LINKSPEED_1000:
4119                         ecmd->speed = SPEED_1000;
4120                         break;
4121                 }
4122                 ecmd->duplex = DUPLEX_HALF;
4123                 if (np->duplex)
4124                         ecmd->duplex = DUPLEX_FULL;
4125         } else {
4126                 ecmd->speed = -1;
4127                 ecmd->duplex = -1;
4128         }
4129
4130         ecmd->autoneg = np->autoneg;
4131
4132         ecmd->advertising = ADVERTISED_MII;
4133         if (np->autoneg) {
4134                 ecmd->advertising |= ADVERTISED_Autoneg;
4135                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4136                 if (adv & ADVERTISE_10HALF)
4137                         ecmd->advertising |= ADVERTISED_10baseT_Half;
4138                 if (adv & ADVERTISE_10FULL)
4139                         ecmd->advertising |= ADVERTISED_10baseT_Full;
4140                 if (adv & ADVERTISE_100HALF)
4141                         ecmd->advertising |= ADVERTISED_100baseT_Half;
4142                 if (adv & ADVERTISE_100FULL)
4143                         ecmd->advertising |= ADVERTISED_100baseT_Full;
4144                 if (np->gigabit == PHY_GIGABIT) {
4145                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4146                         if (adv & ADVERTISE_1000FULL)
4147                                 ecmd->advertising |= ADVERTISED_1000baseT_Full;
4148                 }
4149         }
4150         ecmd->supported = (SUPPORTED_Autoneg |
4151                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4152                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4153                 SUPPORTED_MII);
4154         if (np->gigabit == PHY_GIGABIT)
4155                 ecmd->supported |= SUPPORTED_1000baseT_Full;
4156
4157         ecmd->phy_address = np->phyaddr;
4158         ecmd->transceiver = XCVR_EXTERNAL;
4159
4160         /* ignore maxtxpkt, maxrxpkt for now */
4161         spin_unlock_irq(&np->lock);
4162         return 0;
4163 }
4164
4165 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4166 {
4167         struct fe_priv *np = netdev_priv(dev);
4168
4169         if (ecmd->port != PORT_MII)
4170                 return -EINVAL;
4171         if (ecmd->transceiver != XCVR_EXTERNAL)
4172                 return -EINVAL;
4173         if (ecmd->phy_address != np->phyaddr) {
4174                 /* TODO: support switching between multiple phys. Should be
4175                  * trivial, but not enabled due to lack of test hardware. */
4176                 return -EINVAL;
4177         }
4178         if (ecmd->autoneg == AUTONEG_ENABLE) {
4179                 u32 mask;
4180
4181                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4182                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4183                 if (np->gigabit == PHY_GIGABIT)
4184                         mask |= ADVERTISED_1000baseT_Full;
4185
4186                 if ((ecmd->advertising & mask) == 0)
4187                         return -EINVAL;
4188
4189         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4190                 /* Note: autonegotiation disable, speed 1000 intentionally
4191                  * forbidden - noone should need that. */
4192
4193                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
4194                         return -EINVAL;
4195                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4196                         return -EINVAL;
4197         } else {
4198                 return -EINVAL;
4199         }
4200
4201         netif_carrier_off(dev);
4202         if (netif_running(dev)) {
4203                 unsigned long flags;
4204
4205                 nv_disable_irq(dev);
4206                 netif_tx_lock_bh(dev);
4207                 netif_addr_lock(dev);
4208                 /* with plain spinlock lockdep complains */
4209                 spin_lock_irqsave(&np->lock, flags);
4210                 /* stop engines */
4211                 /* FIXME:
4212                  * this can take some time, and interrupts are disabled
4213                  * due to spin_lock_irqsave, but let's hope no daemon
4214                  * is going to change the settings very often...
4215                  * Worst case:
4216                  * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4217                  * + some minor delays, which is up to a second approximately
4218                  */
4219                 nv_stop_rxtx(dev);
4220                 spin_unlock_irqrestore(&np->lock, flags);
4221                 netif_addr_unlock(dev);
4222                 netif_tx_unlock_bh(dev);
4223         }
4224
4225         if (ecmd->autoneg == AUTONEG_ENABLE) {
4226                 int adv, bmcr;
4227
4228                 np->autoneg = 1;
4229
4230                 /* advertise only what has been requested */
4231                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4232                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4233                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4234                         adv |= ADVERTISE_10HALF;
4235                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
4236                         adv |= ADVERTISE_10FULL;
4237                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4238                         adv |= ADVERTISE_100HALF;
4239                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
4240                         adv |= ADVERTISE_100FULL;
4241                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)  /* for rx we set both advertisments but disable tx pause */
4242                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4243                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4244                         adv |=  ADVERTISE_PAUSE_ASYM;
4245                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4246
4247                 if (np->gigabit == PHY_GIGABIT) {
4248                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4249                         adv &= ~ADVERTISE_1000FULL;
4250                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4251                                 adv |= ADVERTISE_1000FULL;
4252                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4253                 }
4254
4255                 if (netif_running(dev))
4256                         printk(KERN_INFO "%s: link down.\n", dev->name);
4257                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4258                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4259                         bmcr |= BMCR_ANENABLE;
4260                         /* reset the phy in order for settings to stick,
4261                          * and cause autoneg to start */
4262                         if (phy_reset(dev, bmcr)) {
4263                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4264                                 return -EINVAL;
4265                         }
4266                 } else {
4267                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4268                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4269                 }
4270         } else {
4271                 int adv, bmcr;
4272
4273                 np->autoneg = 0;
4274
4275                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4276                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4277                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4278                         adv |= ADVERTISE_10HALF;
4279                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
4280                         adv |= ADVERTISE_10FULL;
4281                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4282                         adv |= ADVERTISE_100HALF;
4283                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
4284                         adv |= ADVERTISE_100FULL;
4285                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4286                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
4287                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4288                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4289                 }
4290                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4291                         adv |=  ADVERTISE_PAUSE_ASYM;
4292                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4293                 }
4294                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4295                 np->fixed_mode = adv;
4296
4297                 if (np->gigabit == PHY_GIGABIT) {
4298                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4299                         adv &= ~ADVERTISE_1000FULL;
4300                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4301                 }
4302
4303                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4304                 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4305                 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
4306                         bmcr |= BMCR_FULLDPLX;
4307                 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
4308                         bmcr |= BMCR_SPEED100;
4309                 if (np->phy_oui == PHY_OUI_MARVELL) {
4310                         /* reset the phy in order for forced mode settings to stick */
4311                         if (phy_reset(dev, bmcr)) {
4312                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4313                                 return -EINVAL;
4314                         }
4315                 } else {
4316                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4317                         if (netif_running(dev)) {
4318                                 /* Wait a bit and then reconfigure the nic. */
4319                                 udelay(10);
4320                                 nv_linkchange(dev);
4321                         }
4322                 }
4323         }
4324
4325         if (netif_running(dev)) {
4326                 nv_start_rxtx(dev);
4327                 nv_enable_irq(dev);
4328         }
4329
4330         return 0;
4331 }
4332
4333 #define FORCEDETH_REGS_VER      1
4334
4335 static int nv_get_regs_len(struct net_device *dev)
4336 {
4337         struct fe_priv *np = netdev_priv(dev);
4338         return np->register_size;
4339 }
4340
4341 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4342 {
4343         struct fe_priv *np = netdev_priv(dev);
4344         u8 __iomem *base = get_hwbase(dev);
4345         u32 *rbuf = buf;
4346         int i;
4347
4348         regs->version = FORCEDETH_REGS_VER;
4349         spin_lock_irq(&np->lock);
4350         for (i = 0;i <= np->register_size/sizeof(u32); i++)
4351                 rbuf[i] = readl(base + i*sizeof(u32));
4352         spin_unlock_irq(&np->lock);
4353 }
4354
4355 static int nv_nway_reset(struct net_device *dev)
4356 {
4357         struct fe_priv *np = netdev_priv(dev);
4358         int ret;
4359
4360         if (np->autoneg) {
4361                 int bmcr;
4362
4363                 netif_carrier_off(dev);
4364                 if (netif_running(dev)) {
4365                         nv_disable_irq(dev);
4366                         netif_tx_lock_bh(dev);
4367                         netif_addr_lock(dev);
4368                         spin_lock(&np->lock);
4369                         /* stop engines */
4370                         nv_stop_rxtx(dev);
4371                         spin_unlock(&np->lock);
4372                         netif_addr_unlock(dev);
4373                         netif_tx_unlock_bh(dev);
4374                         printk(KERN_INFO "%s: link down.\n", dev->name);
4375                 }
4376
4377                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4378                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4379                         bmcr |= BMCR_ANENABLE;
4380                         /* reset the phy in order for settings to stick*/
4381                         if (phy_reset(dev, bmcr)) {
4382                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4383                                 return -EINVAL;
4384                         }
4385                 } else {
4386                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4387                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4388                 }
4389
4390                 if (netif_running(dev)) {
4391                         nv_start_rxtx(dev);
4392                         nv_enable_irq(dev);
4393                 }
4394                 ret = 0;
4395         } else {
4396                 ret = -EINVAL;
4397         }
4398
4399         return ret;
4400 }
4401
4402 static int nv_set_tso(struct net_device *dev, u32 value)
4403 {
4404         struct fe_priv *np = netdev_priv(dev);
4405
4406         if ((np->driver_data & DEV_HAS_CHECKSUM))
4407                 return ethtool_op_set_tso(dev, value);
4408         else
4409                 return -EOPNOTSUPP;
4410 }
4411
4412 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4413 {
4414         struct fe_priv *np = netdev_priv(dev);
4415
4416         ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4417         ring->rx_mini_max_pending = 0;
4418         ring->rx_jumbo_max_pending = 0;
4419         ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4420
4421         ring->rx_pending = np->rx_ring_size;
4422         ring->rx_mini_pending = 0;
4423         ring->rx_jumbo_pending = 0;
4424         ring->tx_pending = np->tx_ring_size;
4425 }
4426
4427 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4428 {
4429         struct fe_priv *np = netdev_priv(dev);
4430         u8 __iomem *base = get_hwbase(dev);
4431         u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4432         dma_addr_t ring_addr;
4433
4434         if (ring->rx_pending < RX_RING_MIN ||
4435             ring->tx_pending < TX_RING_MIN ||
4436             ring->rx_mini_pending != 0 ||
4437             ring->rx_jumbo_pending != 0 ||
4438             (np->desc_ver == DESC_VER_1 &&
4439              (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4440               ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4441             (np->desc_ver != DESC_VER_1 &&
4442              (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4443               ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4444                 return -EINVAL;
4445         }
4446
4447         /* allocate new rings */
4448         if (!nv_optimized(np)) {
4449                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4450                                             sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4451                                             &ring_addr);
4452         } else {
4453                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4454                                             sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4455                                             &ring_addr);
4456         }
4457         rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4458         tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4459         if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4460                 /* fall back to old rings */
4461                 if (!nv_optimized(np)) {
4462                         if (rxtx_ring)
4463                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4464                                                     rxtx_ring, ring_addr);
4465                 } else {
4466                         if (rxtx_ring)
4467                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4468                                                     rxtx_ring, ring_addr);
4469                 }
4470                 if (rx_skbuff)
4471                         kfree(rx_skbuff);
4472                 if (tx_skbuff)
4473                         kfree(tx_skbuff);
4474                 goto exit;
4475         }
4476
4477         if (netif_running(dev)) {
4478                 nv_disable_irq(dev);
4479                 nv_napi_disable(dev);
4480                 netif_tx_lock_bh(dev);
4481                 netif_addr_lock(dev);
4482                 spin_lock(&np->lock);
4483                 /* stop engines */
4484                 nv_stop_rxtx(dev);
4485                 nv_txrx_reset(dev);
4486                 /* drain queues */
4487                 nv_drain_rxtx(dev);
4488                 /* delete queues */
4489                 free_rings(dev);
4490         }
4491
4492         /* set new values */
4493         np->rx_ring_size = ring->rx_pending;
4494         np->tx_ring_size = ring->tx_pending;
4495
4496         if (!nv_optimized(np)) {
4497                 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
4498                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4499         } else {
4500                 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
4501                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4502         }
4503         np->rx_skb = (struct nv_skb_map*)rx_skbuff;
4504         np->tx_skb = (struct nv_skb_map*)tx_skbuff;
4505         np->ring_addr = ring_addr;
4506
4507         memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4508         memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4509
4510         if (netif_running(dev)) {
4511                 /* reinit driver view of the queues */
4512                 set_bufsize(dev);
4513                 if (nv_init_ring(dev)) {
4514                         if (!np->in_shutdown)
4515                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4516                 }
4517
4518                 /* reinit nic view of the queues */
4519                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4520                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4521                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4522                         base + NvRegRingSizes);
4523                 pci_push(base);
4524                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4525                 pci_push(base);
4526
4527                 /* restart engines */
4528                 nv_start_rxtx(dev);
4529                 spin_unlock(&np->lock);
4530                 netif_addr_unlock(dev);
4531                 netif_tx_unlock_bh(dev);
4532                 nv_napi_enable(dev);
4533                 nv_enable_irq(dev);
4534         }
4535         return 0;
4536 exit:
4537         return -ENOMEM;
4538 }
4539
4540 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4541 {
4542         struct fe_priv *np = netdev_priv(dev);
4543
4544         pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4545         pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4546         pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4547 }
4548
4549 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4550 {
4551         struct fe_priv *np = netdev_priv(dev);
4552         int adv, bmcr;
4553
4554         if ((!np->autoneg && np->duplex == 0) ||
4555             (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4556                 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
4557                        dev->name);
4558                 return -EINVAL;
4559         }
4560         if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4561                 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
4562                 return -EINVAL;
4563         }
4564
4565         netif_carrier_off(dev);
4566         if (netif_running(dev)) {
4567                 nv_disable_irq(dev);
4568                 netif_tx_lock_bh(dev);
4569                 netif_addr_lock(dev);
4570                 spin_lock(&np->lock);
4571                 /* stop engines */
4572                 nv_stop_rxtx(dev);
4573                 spin_unlock(&np->lock);
4574                 netif_addr_unlock(dev);
4575                 netif_tx_unlock_bh(dev);
4576         }
4577
4578         np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4579         if (pause->rx_pause)
4580                 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4581         if (pause->tx_pause)
4582                 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4583
4584         if (np->autoneg && pause->autoneg) {
4585                 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4586
4587                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4588                 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4589                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4590                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4591                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4592                         adv |=  ADVERTISE_PAUSE_ASYM;
4593                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4594
4595                 if (netif_running(dev))
4596                         printk(KERN_INFO "%s: link down.\n", dev->name);
4597                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4598                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4599                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4600         } else {
4601                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4602                 if (pause->rx_pause)
4603                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4604                 if (pause->tx_pause)
4605                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4606
4607                 if (!netif_running(dev))
4608                         nv_update_linkspeed(dev);
4609                 else
4610                         nv_update_pause(dev, np->pause_flags);
4611         }
4612
4613         if (netif_running(dev)) {
4614                 nv_start_rxtx(dev);
4615                 nv_enable_irq(dev);
4616         }
4617         return 0;
4618 }
4619
4620 static u32 nv_get_rx_csum(struct net_device *dev)
4621 {
4622         struct fe_priv *np = netdev_priv(dev);
4623         return (np->rx_csum) != 0;
4624 }
4625
4626 static int nv_set_rx_csum(struct net_device *dev, u32 data)
4627 {
4628         struct fe_priv *np = netdev_priv(dev);
4629         u8 __iomem *base = get_hwbase(dev);
4630         int retcode = 0;
4631
4632         if (np->driver_data & DEV_HAS_CHECKSUM) {
4633                 if (data) {
4634                         np->rx_csum = 1;
4635                         np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4636                 } else {
4637                         np->rx_csum = 0;
4638                         /* vlan is dependent on rx checksum offload */
4639                         if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
4640                                 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4641                 }
4642                 if (netif_running(dev)) {
4643                         spin_lock_irq(&np->lock);
4644                         writel(np->txrxctl_bits, base + NvRegTxRxControl);
4645                         spin_unlock_irq(&np->lock);
4646                 }
4647         } else {
4648                 return -EINVAL;
4649         }
4650
4651         return retcode;
4652 }
4653
4654 static int nv_set_tx_csum(struct net_device *dev, u32 data)
4655 {
4656         struct fe_priv *np = netdev_priv(dev);
4657
4658         if (np->driver_data & DEV_HAS_CHECKSUM)
4659                 return ethtool_op_set_tx_csum(dev, data);
4660         else
4661                 return -EOPNOTSUPP;
4662 }
4663
4664 static int nv_set_sg(struct net_device *dev, u32 data)
4665 {
4666         struct fe_priv *np = netdev_priv(dev);
4667
4668         if (np->driver_data & DEV_HAS_CHECKSUM)
4669                 return ethtool_op_set_sg(dev, data);
4670         else
4671                 return -EOPNOTSUPP;
4672 }
4673
4674 static int nv_get_sset_count(struct net_device *dev, int sset)
4675 {
4676         struct fe_priv *np = netdev_priv(dev);
4677
4678         switch (sset) {
4679         case ETH_SS_TEST:
4680                 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4681                         return NV_TEST_COUNT_EXTENDED;
4682                 else
4683                         return NV_TEST_COUNT_BASE;
4684         case ETH_SS_STATS:
4685                 if (np->driver_data & DEV_HAS_STATISTICS_V3)
4686                         return NV_DEV_STATISTICS_V3_COUNT;
4687                 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4688                         return NV_DEV_STATISTICS_V2_COUNT;
4689                 else if (np->driver_data & DEV_HAS_STATISTICS_V1)
4690                         return NV_DEV_STATISTICS_V1_COUNT;
4691                 else
4692                         return 0;
4693         default:
4694                 return -EOPNOTSUPP;
4695         }
4696 }
4697
4698 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4699 {
4700         struct fe_priv *np = netdev_priv(dev);
4701
4702         /* update stats */
4703         nv_do_stats_poll((unsigned long)dev);
4704
4705         memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
4706 }
4707
4708 static int nv_link_test(struct net_device *dev)
4709 {
4710         struct fe_priv *np = netdev_priv(dev);
4711         int mii_status;
4712
4713         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4714         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4715
4716         /* check phy link status */
4717         if (!(mii_status & BMSR_LSTATUS))
4718                 return 0;
4719         else
4720                 return 1;
4721 }
4722
4723 static int nv_register_test(struct net_device *dev)
4724 {
4725         u8 __iomem *base = get_hwbase(dev);
4726         int i = 0;
4727         u32 orig_read, new_read;
4728
4729         do {
4730                 orig_read = readl(base + nv_registers_test[i].reg);
4731
4732                 /* xor with mask to toggle bits */
4733                 orig_read ^= nv_registers_test[i].mask;
4734
4735                 writel(orig_read, base + nv_registers_test[i].reg);
4736
4737                 new_read = readl(base + nv_registers_test[i].reg);
4738
4739                 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4740                         return 0;
4741
4742                 /* restore original value */
4743                 orig_read ^= nv_registers_test[i].mask;
4744                 writel(orig_read, base + nv_registers_test[i].reg);
4745
4746         } while (nv_registers_test[++i].reg != 0);
4747
4748         return 1;
4749 }
4750
4751 static int nv_interrupt_test(struct net_device *dev)
4752 {
4753         struct fe_priv *np = netdev_priv(dev);
4754         u8 __iomem *base = get_hwbase(dev);
4755         int ret = 1;
4756         int testcnt;
4757         u32 save_msi_flags, save_poll_interval = 0;
4758
4759         if (netif_running(dev)) {
4760                 /* free current irq */
4761                 nv_free_irq(dev);
4762                 save_poll_interval = readl(base+NvRegPollingInterval);
4763         }
4764
4765         /* flag to test interrupt handler */
4766         np->intr_test = 0;
4767
4768         /* setup test irq */
4769         save_msi_flags = np->msi_flags;
4770         np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4771         np->msi_flags |= 0x001; /* setup 1 vector */
4772         if (nv_request_irq(dev, 1))
4773                 return 0;
4774
4775         /* setup timer interrupt */
4776         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4777         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4778
4779         nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4780
4781         /* wait for at least one interrupt */
4782         msleep(100);
4783
4784         spin_lock_irq(&np->lock);
4785
4786         /* flag should be set within ISR */
4787         testcnt = np->intr_test;
4788         if (!testcnt)
4789                 ret = 2;
4790
4791         nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4792         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4793                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4794         else
4795                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4796
4797         spin_unlock_irq(&np->lock);
4798
4799         nv_free_irq(dev);
4800
4801         np->msi_flags = save_msi_flags;
4802
4803         if (netif_running(dev)) {
4804                 writel(save_poll_interval, base + NvRegPollingInterval);
4805                 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4806                 /* restore original irq */
4807                 if (nv_request_irq(dev, 0))
4808                         return 0;
4809         }
4810
4811         return ret;
4812 }
4813
4814 static int nv_loopback_test(struct net_device *dev)
4815 {
4816         struct fe_priv *np = netdev_priv(dev);
4817         u8 __iomem *base = get_hwbase(dev);
4818         struct sk_buff *tx_skb, *rx_skb;
4819         dma_addr_t test_dma_addr;
4820         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
4821         u32 flags;
4822         int len, i, pkt_len;
4823         u8 *pkt_data;
4824         u32 filter_flags = 0;
4825         u32 misc1_flags = 0;
4826         int ret = 1;
4827
4828         if (netif_running(dev)) {
4829                 nv_disable_irq(dev);
4830                 filter_flags = readl(base + NvRegPacketFilterFlags);
4831                 misc1_flags = readl(base + NvRegMisc1);
4832         } else {
4833                 nv_txrx_reset(dev);
4834         }
4835
4836         /* reinit driver view of the rx queue */
4837         set_bufsize(dev);
4838         nv_init_ring(dev);
4839
4840         /* setup hardware for loopback */
4841         writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
4842         writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
4843
4844         /* reinit nic view of the rx queue */
4845         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4846         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4847         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4848                 base + NvRegRingSizes);
4849         pci_push(base);
4850
4851         /* restart rx engine */
4852         nv_start_rxtx(dev);
4853
4854         /* setup packet for tx */
4855         pkt_len = ETH_DATA_LEN;
4856         tx_skb = dev_alloc_skb(pkt_len);
4857         if (!tx_skb) {
4858                 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
4859                          " of %s\n", dev->name);
4860                 ret = 0;
4861                 goto out;
4862         }
4863         test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
4864                                        skb_tailroom(tx_skb),
4865                                        PCI_DMA_FROMDEVICE);
4866         pkt_data = skb_put(tx_skb, pkt_len);
4867         for (i = 0; i < pkt_len; i++)
4868                 pkt_data[i] = (u8)(i & 0xff);
4869
4870         if (!nv_optimized(np)) {
4871                 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
4872                 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4873         } else {
4874                 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
4875                 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
4876                 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4877         }
4878         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4879         pci_push(get_hwbase(dev));
4880
4881         msleep(500);
4882
4883         /* check for rx of the packet */
4884         if (!nv_optimized(np)) {
4885                 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
4886                 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
4887
4888         } else {
4889                 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
4890                 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
4891         }
4892
4893         if (flags & NV_RX_AVAIL) {
4894                 ret = 0;
4895         } else if (np->desc_ver == DESC_VER_1) {
4896                 if (flags & NV_RX_ERROR)
4897                         ret = 0;
4898         } else {
4899                 if (flags & NV_RX2_ERROR) {
4900                         ret = 0;
4901                 }
4902         }
4903
4904         if (ret) {
4905                 if (len != pkt_len) {
4906                         ret = 0;
4907                         dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
4908                                 dev->name, len, pkt_len);
4909                 } else {
4910                         rx_skb = np->rx_skb[0].skb;
4911                         for (i = 0; i < pkt_len; i++) {
4912                                 if (rx_skb->data[i] != (u8)(i & 0xff)) {
4913                                         ret = 0;
4914                                         dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
4915                                                 dev->name, i);
4916                                         break;
4917                                 }
4918                         }
4919                 }
4920         } else {
4921                 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
4922         }
4923
4924         pci_unmap_single(np->pci_dev, test_dma_addr,
4925                        (skb_end_pointer(tx_skb) - tx_skb->data),
4926                        PCI_DMA_TODEVICE);
4927         dev_kfree_skb_any(tx_skb);
4928  out:
4929         /* stop engines */
4930         nv_stop_rxtx(dev);
4931         nv_txrx_reset(dev);
4932         /* drain rx queue */
4933         nv_drain_rxtx(dev);
4934
4935         if (netif_running(dev)) {
4936                 writel(misc1_flags, base + NvRegMisc1);
4937                 writel(filter_flags, base + NvRegPacketFilterFlags);
4938                 nv_enable_irq(dev);
4939         }
4940
4941         return ret;
4942 }
4943
4944 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
4945 {
4946         struct fe_priv *np = netdev_priv(dev);
4947         u8 __iomem *base = get_hwbase(dev);
4948         int result;
4949         memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
4950
4951         if (!nv_link_test(dev)) {
4952                 test->flags |= ETH_TEST_FL_FAILED;
4953                 buffer[0] = 1;
4954         }
4955
4956         if (test->flags & ETH_TEST_FL_OFFLINE) {
4957                 if (netif_running(dev)) {
4958                         netif_stop_queue(dev);
4959                         nv_napi_disable(dev);
4960                         netif_tx_lock_bh(dev);
4961                         netif_addr_lock(dev);
4962                         spin_lock_irq(&np->lock);
4963                         nv_disable_hw_interrupts(dev, np->irqmask);
4964                         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
4965                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4966                         } else {
4967                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4968                         }
4969                         /* stop engines */
4970                         nv_stop_rxtx(dev);
4971                         nv_txrx_reset(dev);
4972                         /* drain rx queue */
4973                         nv_drain_rxtx(dev);
4974                         spin_unlock_irq(&np->lock);
4975                         netif_addr_unlock(dev);
4976                         netif_tx_unlock_bh(dev);
4977                 }
4978
4979                 if (!nv_register_test(dev)) {
4980                         test->flags |= ETH_TEST_FL_FAILED;
4981                         buffer[1] = 1;
4982                 }
4983
4984                 result = nv_interrupt_test(dev);
4985                 if (result != 1) {
4986                         test->flags |= ETH_TEST_FL_FAILED;
4987                         buffer[2] = 1;
4988                 }
4989                 if (result == 0) {
4990                         /* bail out */
4991                         return;
4992                 }
4993
4994                 if (!nv_loopback_test(dev)) {
4995                         test->flags |= ETH_TEST_FL_FAILED;
4996                         buffer[3] = 1;
4997                 }
4998
4999                 if (netif_running(dev)) {
5000                         /* reinit driver view of the rx queue */
5001                         set_bufsize(dev);
5002                         if (nv_init_ring(dev)) {
5003                                 if (!np->in_shutdown)
5004                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5005                         }
5006                         /* reinit nic view of the rx queue */
5007                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5008                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5009                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5010                                 base + NvRegRingSizes);
5011                         pci_push(base);
5012                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5013                         pci_push(base);
5014                         /* restart rx engine */
5015                         nv_start_rxtx(dev);
5016                         netif_start_queue(dev);
5017                         nv_napi_enable(dev);
5018                         nv_enable_hw_interrupts(dev, np->irqmask);
5019                 }
5020         }
5021 }
5022
5023 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
5024 {
5025         switch (stringset) {
5026         case ETH_SS_STATS:
5027                 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
5028                 break;
5029         case ETH_SS_TEST:
5030                 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
5031                 break;
5032         }
5033 }
5034
5035 static const struct ethtool_ops ops = {
5036         .get_drvinfo = nv_get_drvinfo,
5037         .get_link = ethtool_op_get_link,
5038         .get_wol = nv_get_wol,
5039         .set_wol = nv_set_wol,
5040         .get_settings = nv_get_settings,
5041         .set_settings = nv_set_settings,
5042         .get_regs_len = nv_get_regs_len,
5043         .get_regs = nv_get_regs,
5044         .nway_reset = nv_nway_reset,
5045         .set_tso = nv_set_tso,
5046         .get_ringparam = nv_get_ringparam,
5047         .set_ringparam = nv_set_ringparam,
5048         .get_pauseparam = nv_get_pauseparam,
5049         .set_pauseparam = nv_set_pauseparam,
5050         .get_rx_csum = nv_get_rx_csum,
5051         .set_rx_csum = nv_set_rx_csum,
5052         .set_tx_csum = nv_set_tx_csum,
5053         .set_sg = nv_set_sg,
5054         .get_strings = nv_get_strings,
5055         .get_ethtool_stats = nv_get_ethtool_stats,
5056         .get_sset_count = nv_get_sset_count,
5057         .self_test = nv_self_test,
5058 };
5059
5060 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
5061 {
5062         struct fe_priv *np = get_nvpriv(dev);
5063
5064         spin_lock_irq(&np->lock);
5065
5066         /* save vlan group */
5067         np->vlangrp = grp;
5068
5069         if (grp) {
5070                 /* enable vlan on MAC */
5071                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
5072         } else {
5073                 /* disable vlan on MAC */
5074                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
5075                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
5076         }
5077
5078         writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5079
5080         spin_unlock_irq(&np->lock);
5081 }
5082
5083 /* The mgmt unit and driver use a semaphore to access the phy during init */
5084 static int nv_mgmt_acquire_sema(struct net_device *dev)
5085 {
5086         struct fe_priv *np = netdev_priv(dev);
5087         u8 __iomem *base = get_hwbase(dev);
5088         int i;
5089         u32 tx_ctrl, mgmt_sema;
5090
5091         for (i = 0; i < 10; i++) {
5092                 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
5093                 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
5094                         break;
5095                 msleep(500);
5096         }
5097
5098         if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
5099                 return 0;
5100
5101         for (i = 0; i < 2; i++) {
5102                 tx_ctrl = readl(base + NvRegTransmitterControl);
5103                 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
5104                 writel(tx_ctrl, base + NvRegTransmitterControl);
5105
5106                 /* verify that semaphore was acquired */
5107                 tx_ctrl = readl(base + NvRegTransmitterControl);
5108                 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
5109                     ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
5110                         np->mgmt_sema = 1;
5111                         return 1;
5112                 }
5113                 else
5114                         udelay(50);
5115         }
5116
5117         return 0;
5118 }
5119
5120 static void nv_mgmt_release_sema(struct net_device *dev)
5121 {
5122         struct fe_priv *np = netdev_priv(dev);
5123         u8 __iomem *base = get_hwbase(dev);
5124         u32 tx_ctrl;
5125
5126         if (np->driver_data & DEV_HAS_MGMT_UNIT) {
5127                 if (np->mgmt_sema) {
5128                         tx_ctrl = readl(base + NvRegTransmitterControl);
5129                         tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
5130                         writel(tx_ctrl, base + NvRegTransmitterControl);
5131                 }
5132         }
5133 }
5134
5135
5136 static int nv_mgmt_get_version(struct net_device *dev)
5137 {
5138         struct fe_priv *np = netdev_priv(dev);
5139         u8 __iomem *base = get_hwbase(dev);
5140         u32 data_ready = readl(base + NvRegTransmitterControl);
5141         u32 data_ready2 = 0;
5142         unsigned long start;
5143         int ready = 0;
5144
5145         writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
5146         writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
5147         start = jiffies;
5148         while (time_before(jiffies, start + 5*HZ)) {
5149                 data_ready2 = readl(base + NvRegTransmitterControl);
5150                 if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) {
5151                         ready = 1;
5152                         break;
5153                 }
5154                 schedule_timeout_uninterruptible(1);
5155         }
5156
5157         if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR))
5158                 return 0;
5159
5160         np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;
5161
5162         return 1;
5163 }
5164
5165 static int nv_open(struct net_device *dev)
5166 {
5167         struct fe_priv *np = netdev_priv(dev);
5168         u8 __iomem *base = get_hwbase(dev);
5169         int ret = 1;
5170         int oom, i;
5171         u32 low;
5172
5173         dprintk(KERN_DEBUG "nv_open: begin\n");
5174
5175         /* power up phy */
5176         mii_rw(dev, np->phyaddr, MII_BMCR,
5177                mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
5178
5179         nv_txrx_gate(dev, false);
5180         /* erase previous misconfiguration */
5181         if (np->driver_data & DEV_HAS_POWER_CNTRL)
5182                 nv_mac_reset(dev);
5183         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5184         writel(0, base + NvRegMulticastAddrB);
5185         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5186         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5187         writel(0, base + NvRegPacketFilterFlags);
5188
5189         writel(0, base + NvRegTransmitterControl);
5190         writel(0, base + NvRegReceiverControl);
5191
5192         writel(0, base + NvRegAdapterControl);
5193
5194         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5195                 writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
5196
5197         /* initialize descriptor rings */
5198         set_bufsize(dev);
5199         oom = nv_init_ring(dev);
5200
5201         writel(0, base + NvRegLinkSpeed);
5202         writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5203         nv_txrx_reset(dev);
5204         writel(0, base + NvRegUnknownSetupReg6);
5205
5206         np->in_shutdown = 0;
5207
5208         /* give hw rings */
5209         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5210         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5211                 base + NvRegRingSizes);
5212
5213         writel(np->linkspeed, base + NvRegLinkSpeed);
5214         if (np->desc_ver == DESC_VER_1)
5215                 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5216         else
5217                 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
5218         writel(np->txrxctl_bits, base + NvRegTxRxControl);
5219         writel(np->vlanctl_bits, base + NvRegVlanControl);
5220         pci_push(base);
5221         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
5222         reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5223                         NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
5224                         KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
5225
5226         writel(0, base + NvRegMIIMask);
5227         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5228         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5229
5230         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5231         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5232         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
5233         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5234
5235         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
5236
5237         get_random_bytes(&low, sizeof(low));
5238         low &= NVREG_SLOTTIME_MASK;
5239         if (np->desc_ver == DESC_VER_1) {
5240                 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5241         } else {
5242                 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5243                         /* setup legacy backoff */
5244                         writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5245                 } else {
5246                         writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5247                         nv_gear_backoff_reseed(dev);
5248                 }
5249         }
5250         writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5251         writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
5252         if (poll_interval == -1) {
5253                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5254                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5255                 else
5256                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5257         }
5258         else
5259                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5260         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5261         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5262                         base + NvRegAdapterControl);
5263         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
5264         writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
5265         if (np->wolenabled)
5266                 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5267
5268         i = readl(base + NvRegPowerState);
5269         if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
5270                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5271
5272         pci_push(base);
5273         udelay(10);
5274         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5275
5276         nv_disable_hw_interrupts(dev, np->irqmask);
5277         pci_push(base);
5278         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5279         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5280         pci_push(base);
5281
5282         if (nv_request_irq(dev, 0)) {
5283                 goto out_drain;
5284         }
5285
5286         /* ask for interrupts */
5287         nv_enable_hw_interrupts(dev, np->irqmask);
5288
5289         spin_lock_irq(&np->lock);
5290         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5291         writel(0, base + NvRegMulticastAddrB);
5292         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5293         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5294         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5295         /* One manual link speed update: Interrupts are enabled, future link
5296          * speed changes cause interrupts and are handled by nv_link_irq().
5297          */
5298         {
5299                 u32 miistat;
5300                 miistat = readl(base + NvRegMIIStatus);
5301                 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5302                 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
5303         }
5304         /* set linkspeed to invalid value, thus force nv_update_linkspeed
5305          * to init hw */
5306         np->linkspeed = 0;
5307         ret = nv_update_linkspeed(dev);
5308         nv_start_rxtx(dev);
5309         netif_start_queue(dev);
5310         nv_napi_enable(dev);
5311
5312         if (ret) {
5313                 netif_carrier_on(dev);
5314         } else {
5315                 printk(KERN_INFO "%s: no link during initialization.\n", dev->name);
5316                 netif_carrier_off(dev);
5317         }
5318         if (oom)
5319                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5320
5321         /* start statistics timer */
5322         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5323                 mod_timer(&np->stats_poll,
5324                         round_jiffies(jiffies + STATS_INTERVAL));
5325
5326         spin_unlock_irq(&np->lock);
5327
5328         return 0;
5329 out_drain:
5330         nv_drain_rxtx(dev);
5331         return ret;
5332 }
5333
5334 static int nv_close(struct net_device *dev)
5335 {
5336         struct fe_priv *np = netdev_priv(dev);
5337         u8 __iomem *base;
5338
5339         spin_lock_irq(&np->lock);
5340         np->in_shutdown = 1;
5341         spin_unlock_irq(&np->lock);
5342         nv_napi_disable(dev);
5343         synchronize_irq(np->pci_dev->irq);
5344
5345         del_timer_sync(&np->oom_kick);
5346         del_timer_sync(&np->nic_poll);
5347         del_timer_sync(&np->stats_poll);
5348
5349         netif_stop_queue(dev);
5350         spin_lock_irq(&np->lock);
5351         nv_stop_rxtx(dev);
5352         nv_txrx_reset(dev);
5353
5354         /* disable interrupts on the nic or we will lock up */
5355         base = get_hwbase(dev);
5356         nv_disable_hw_interrupts(dev, np->irqmask);
5357         pci_push(base);
5358         dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
5359
5360         spin_unlock_irq(&np->lock);
5361
5362         nv_free_irq(dev);
5363
5364         nv_drain_rxtx(dev);
5365
5366         if (np->wolenabled || !phy_power_down) {
5367                 nv_txrx_gate(dev, false);
5368                 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5369                 nv_start_rx(dev);
5370         } else {
5371                 /* power down phy */
5372                 mii_rw(dev, np->phyaddr, MII_BMCR,
5373                        mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
5374                 nv_txrx_gate(dev, true);
5375         }
5376
5377         /* FIXME: power down nic */
5378
5379         return 0;
5380 }
5381
5382 static const struct net_device_ops nv_netdev_ops = {
5383         .ndo_open               = nv_open,
5384         .ndo_stop               = nv_close,
5385         .ndo_get_stats          = nv_get_stats,
5386         .ndo_start_xmit         = nv_start_xmit,
5387         .ndo_tx_timeout         = nv_tx_timeout,
5388         .ndo_change_mtu         = nv_change_mtu,
5389         .ndo_validate_addr      = eth_validate_addr,
5390         .ndo_set_mac_address    = nv_set_mac_address,
5391         .ndo_set_multicast_list = nv_set_multicast,
5392         .ndo_vlan_rx_register   = nv_vlan_rx_register,
5393 #ifdef CONFIG_NET_POLL_CONTROLLER
5394         .ndo_poll_controller    = nv_poll_controller,
5395 #endif
5396 };
5397
5398 static const struct net_device_ops nv_netdev_ops_optimized = {
5399         .ndo_open               = nv_open,
5400         .ndo_stop               = nv_close,
5401         .ndo_get_stats          = nv_get_stats,
5402         .ndo_start_xmit         = nv_start_xmit_optimized,
5403         .ndo_tx_timeout         = nv_tx_timeout,
5404         .ndo_change_mtu         = nv_change_mtu,
5405         .ndo_validate_addr      = eth_validate_addr,
5406         .ndo_set_mac_address    = nv_set_mac_address,
5407         .ndo_set_multicast_list = nv_set_multicast,
5408         .ndo_vlan_rx_register   = nv_vlan_rx_register,
5409 #ifdef CONFIG_NET_POLL_CONTROLLER
5410         .ndo_poll_controller    = nv_poll_controller,
5411 #endif
5412 };
5413
5414 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5415 {
5416         struct net_device *dev;
5417         struct fe_priv *np;
5418         unsigned long addr;
5419         u8 __iomem *base;
5420         int err, i;
5421         u32 powerstate, txreg;
5422         u32 phystate_orig = 0, phystate;
5423         int phyinitialized = 0;
5424         static int printed_version;
5425
5426         if (!printed_version++)
5427                 printk(KERN_INFO "%s: Reverse Engineered nForce ethernet"
5428                        " driver. Version %s.\n", DRV_NAME, FORCEDETH_VERSION);
5429
5430         dev = alloc_etherdev(sizeof(struct fe_priv));
5431         err = -ENOMEM;
5432         if (!dev)
5433                 goto out;
5434
5435         np = netdev_priv(dev);
5436         np->dev = dev;
5437         np->pci_dev = pci_dev;
5438         spin_lock_init(&np->lock);
5439         SET_NETDEV_DEV(dev, &pci_dev->dev);
5440
5441         init_timer(&np->oom_kick);
5442         np->oom_kick.data = (unsigned long) dev;
5443         np->oom_kick.function = &nv_do_rx_refill;       /* timer handler */
5444         init_timer(&np->nic_poll);
5445         np->nic_poll.data = (unsigned long) dev;
5446         np->nic_poll.function = &nv_do_nic_poll;        /* timer handler */
5447         init_timer(&np->stats_poll);
5448         np->stats_poll.data = (unsigned long) dev;
5449         np->stats_poll.function = &nv_do_stats_poll;    /* timer handler */
5450
5451         err = pci_enable_device(pci_dev);
5452         if (err)
5453                 goto out_free;
5454
5455         pci_set_master(pci_dev);
5456
5457         err = pci_request_regions(pci_dev, DRV_NAME);
5458         if (err < 0)
5459                 goto out_disable;
5460
5461         if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5462                 np->register_size = NV_PCI_REGSZ_VER3;
5463         else if (id->driver_data & DEV_HAS_STATISTICS_V1)
5464                 np->register_size = NV_PCI_REGSZ_VER2;
5465         else
5466                 np->register_size = NV_PCI_REGSZ_VER1;
5467
5468         err = -EINVAL;
5469         addr = 0;
5470         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5471                 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
5472                                 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
5473                                 pci_resource_len(pci_dev, i),
5474                                 pci_resource_flags(pci_dev, i));
5475                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
5476                                 pci_resource_len(pci_dev, i) >= np->register_size) {
5477                         addr = pci_resource_start(pci_dev, i);
5478                         break;
5479                 }
5480         }
5481         if (i == DEVICE_COUNT_RESOURCE) {
5482                 dev_printk(KERN_INFO, &pci_dev->dev,
5483                            "Couldn't find register window\n");
5484                 goto out_relreg;
5485         }
5486
5487         /* copy of driver data */
5488         np->driver_data = id->driver_data;
5489         /* copy of device id */
5490         np->device_id = id->device;
5491
5492         /* handle different descriptor versions */
5493         if (id->driver_data & DEV_HAS_HIGH_DMA) {
5494                 /* packet format 3: supports 40-bit addressing */
5495                 np->desc_ver = DESC_VER_3;
5496                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
5497                 if (dma_64bit) {
5498                         if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39)))
5499                                 dev_printk(KERN_INFO, &pci_dev->dev,
5500                                         "64-bit DMA failed, using 32-bit addressing\n");
5501                         else
5502                                 dev->features |= NETIF_F_HIGHDMA;
5503                         if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) {
5504                                 dev_printk(KERN_INFO, &pci_dev->dev,
5505                                         "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5506                         }
5507                 }
5508         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5509                 /* packet format 2: supports jumbo frames */
5510                 np->desc_ver = DESC_VER_2;
5511                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
5512         } else {
5513                 /* original packet format */
5514                 np->desc_ver = DESC_VER_1;
5515                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
5516         }
5517
5518         np->pkt_limit = NV_PKTLIMIT_1;
5519         if (id->driver_data & DEV_HAS_LARGEDESC)
5520                 np->pkt_limit = NV_PKTLIMIT_2;
5521
5522         if (id->driver_data & DEV_HAS_CHECKSUM) {
5523                 np->rx_csum = 1;
5524                 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
5525                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
5526                 dev->features |= NETIF_F_TSO;
5527                 dev->features |= NETIF_F_GRO;
5528         }
5529
5530         np->vlanctl_bits = 0;
5531         if (id->driver_data & DEV_HAS_VLAN) {
5532                 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5533                 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
5534         }
5535
5536         np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
5537         if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5538             (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5539             (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
5540                 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
5541         }
5542
5543
5544         err = -ENOMEM;
5545         np->base = ioremap(addr, np->register_size);
5546         if (!np->base)
5547                 goto out_relreg;
5548         dev->base_addr = (unsigned long)np->base;
5549
5550         dev->irq = pci_dev->irq;
5551
5552         np->rx_ring_size = RX_RING_DEFAULT;
5553         np->tx_ring_size = TX_RING_DEFAULT;
5554
5555         if (!nv_optimized(np)) {
5556                 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
5557                                         sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
5558                                         &np->ring_addr);
5559                 if (!np->rx_ring.orig)
5560                         goto out_unmap;
5561                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
5562         } else {
5563                 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
5564                                         sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
5565                                         &np->ring_addr);
5566                 if (!np->rx_ring.ex)
5567                         goto out_unmap;
5568                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
5569         }
5570         np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5571         np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5572         if (!np->rx_skb || !np->tx_skb)
5573                 goto out_freering;
5574
5575         if (!nv_optimized(np))
5576                 dev->netdev_ops = &nv_netdev_ops;
5577         else
5578                 dev->netdev_ops = &nv_netdev_ops_optimized;
5579
5580         netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
5581         SET_ETHTOOL_OPS(dev, &ops);
5582         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5583
5584         pci_set_drvdata(pci_dev, dev);
5585
5586         /* read the mac address */
5587         base = get_hwbase(dev);
5588         np->orig_mac[0] = readl(base + NvRegMacAddrA);
5589         np->orig_mac[1] = readl(base + NvRegMacAddrB);
5590
5591         /* check the workaround bit for correct mac address order */
5592         txreg = readl(base + NvRegTransmitPoll);
5593         if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
5594                 /* mac address is already in correct order */
5595                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5596                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5597                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5598                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5599                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5600                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5601         } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5602                 /* mac address is already in correct order */
5603                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5604                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5605                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5606                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5607                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5608                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5609                 /*
5610                  * Set orig mac address back to the reversed version.
5611                  * This flag will be cleared during low power transition.
5612                  * Therefore, we should always put back the reversed address.
5613                  */
5614                 np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
5615                         (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
5616                 np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
5617         } else {
5618                 /* need to reverse mac address to correct order */
5619                 dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
5620                 dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
5621                 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5622                 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5623                 dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
5624                 dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
5625                 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5626                 printk(KERN_DEBUG "nv_probe: set workaround bit for reversed mac addr\n");
5627         }
5628         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
5629
5630         if (!is_valid_ether_addr(dev->perm_addr)) {
5631                 /*
5632                  * Bad mac address. At least one bios sets the mac address
5633                  * to 01:23:45:67:89:ab
5634                  */
5635                 dev_printk(KERN_ERR, &pci_dev->dev,
5636                         "Invalid Mac address detected: %pM\n",
5637                         dev->dev_addr);
5638                 dev_printk(KERN_ERR, &pci_dev->dev,
5639                         "Please complain to your hardware vendor. Switching to a random MAC.\n");
5640                 random_ether_addr(dev->dev_addr);
5641         }
5642
5643         dprintk(KERN_DEBUG "%s: MAC Address %pM\n",
5644                 pci_name(pci_dev), dev->dev_addr);
5645
5646         /* set mac address */
5647         nv_copy_mac_to_hw(dev);
5648
5649         /* Workaround current PCI init glitch:  wakeup bits aren't
5650          * being set from PCI PM capability.
5651          */
5652         device_init_wakeup(&pci_dev->dev, 1);
5653
5654         /* disable WOL */
5655         writel(0, base + NvRegWakeUpFlags);
5656         np->wolenabled = 0;
5657
5658         if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5659
5660                 /* take phy and nic out of low power mode */
5661                 powerstate = readl(base + NvRegPowerState2);
5662                 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5663                 if ((id->driver_data & DEV_NEED_LOW_POWER_FIX) &&
5664                     pci_dev->revision >= 0xA3)
5665                         powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5666                 writel(powerstate, base + NvRegPowerState2);
5667         }
5668
5669         if (np->desc_ver == DESC_VER_1) {
5670                 np->tx_flags = NV_TX_VALID;
5671         } else {
5672                 np->tx_flags = NV_TX2_VALID;
5673         }
5674
5675         np->msi_flags = 0;
5676         if ((id->driver_data & DEV_HAS_MSI) && msi) {
5677                 np->msi_flags |= NV_MSI_CAPABLE;
5678         }
5679         if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5680                 /* msix has had reported issues when modifying irqmask
5681                    as in the case of napi, therefore, disable for now
5682                 */
5683 #if 0
5684                 np->msi_flags |= NV_MSI_X_CAPABLE;
5685 #endif
5686         }
5687
5688         if (optimization_mode == NV_OPTIMIZATION_MODE_CPU) {
5689                 np->irqmask = NVREG_IRQMASK_CPU;
5690                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5691                         np->msi_flags |= 0x0001;
5692         } else if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC &&
5693                    !(id->driver_data & DEV_NEED_TIMERIRQ)) {
5694                 /* start off in throughput mode */
5695                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5696                 /* remove support for msix mode */
5697                 np->msi_flags &= ~NV_MSI_X_CAPABLE;
5698         } else {
5699                 optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
5700                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5701                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5702                         np->msi_flags |= 0x0003;
5703         }
5704
5705         if (id->driver_data & DEV_NEED_TIMERIRQ)
5706                 np->irqmask |= NVREG_IRQ_TIMER;
5707         if (id->driver_data & DEV_NEED_LINKTIMER) {
5708                 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
5709                 np->need_linktimer = 1;
5710                 np->link_timeout = jiffies + LINK_TIMEOUT;
5711         } else {
5712                 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
5713                 np->need_linktimer = 0;
5714         }
5715
5716         /* Limit the number of tx's outstanding for hw bug */
5717         if (id->driver_data & DEV_NEED_TX_LIMIT) {
5718                 np->tx_limit = 1;
5719                 if (((id->driver_data & DEV_NEED_TX_LIMIT2) == DEV_NEED_TX_LIMIT2) &&
5720                     pci_dev->revision >= 0xA2)
5721                         np->tx_limit = 0;
5722         }
5723
5724         /* clear phy state and temporarily halt phy interrupts */
5725         writel(0, base + NvRegMIIMask);
5726         phystate = readl(base + NvRegAdapterControl);
5727         if (phystate & NVREG_ADAPTCTL_RUNNING) {
5728                 phystate_orig = 1;
5729                 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5730                 writel(phystate, base + NvRegAdapterControl);
5731         }
5732         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5733
5734         if (id->driver_data & DEV_HAS_MGMT_UNIT) {
5735                 /* management unit running on the mac? */
5736                 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) &&
5737                     (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) &&
5738                     nv_mgmt_acquire_sema(dev) &&
5739                     nv_mgmt_get_version(dev)) {
5740                         np->mac_in_use = 1;
5741                         if (np->mgmt_version > 0) {
5742                                 np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE;
5743                         }
5744                         dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n",
5745                                 pci_name(pci_dev), np->mac_in_use);
5746                         /* management unit setup the phy already? */
5747                         if (np->mac_in_use &&
5748                             ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5749                              NVREG_XMITCTL_SYNC_PHY_INIT)) {
5750                                 /* phy is inited by mgmt unit */
5751                                 phyinitialized = 1;
5752                                 dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n",
5753                                         pci_name(pci_dev));
5754                         } else {
5755                                 /* we need to init the phy */
5756                         }
5757                 }
5758         }
5759
5760         /* find a suitable phy */
5761         for (i = 1; i <= 32; i++) {
5762                 int id1, id2;
5763                 int phyaddr = i & 0x1F;
5764
5765                 spin_lock_irq(&np->lock);
5766                 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5767                 spin_unlock_irq(&np->lock);
5768                 if (id1 < 0 || id1 == 0xffff)
5769                         continue;
5770                 spin_lock_irq(&np->lock);
5771                 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5772                 spin_unlock_irq(&np->lock);
5773                 if (id2 < 0 || id2 == 0xffff)
5774                         continue;
5775
5776                 np->phy_model = id2 & PHYID2_MODEL_MASK;
5777                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5778                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5779                 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
5780                         pci_name(pci_dev), id1, id2, phyaddr);
5781                 np->phyaddr = phyaddr;
5782                 np->phy_oui = id1 | id2;
5783
5784                 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5785                 if (np->phy_oui == PHY_OUI_REALTEK2)
5786                         np->phy_oui = PHY_OUI_REALTEK;
5787                 /* Setup phy revision for Realtek */
5788                 if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211)
5789                         np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
5790
5791                 break;
5792         }
5793         if (i == 33) {
5794                 dev_printk(KERN_INFO, &pci_dev->dev,
5795                         "open: Could not find a valid PHY.\n");
5796                 goto out_error;
5797         }
5798
5799         if (!phyinitialized) {
5800                 /* reset it */
5801                 phy_init(dev);
5802         } else {
5803                 /* see if it is a gigabit phy */
5804                 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5805                 if (mii_status & PHY_GIGABIT) {
5806                         np->gigabit = PHY_GIGABIT;
5807                 }
5808         }
5809
5810         /* set default link speed settings */
5811         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5812         np->duplex = 0;
5813         np->autoneg = 1;
5814
5815         err = register_netdev(dev);
5816         if (err) {
5817                 dev_printk(KERN_INFO, &pci_dev->dev,
5818                            "unable to register netdev: %d\n", err);
5819                 goto out_error;
5820         }
5821
5822         dev_printk(KERN_INFO, &pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, "
5823                    "addr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
5824                    dev->name,
5825                    np->phy_oui,
5826                    np->phyaddr,
5827                    dev->dev_addr[0],
5828                    dev->dev_addr[1],
5829                    dev->dev_addr[2],
5830                    dev->dev_addr[3],
5831                    dev->dev_addr[4],
5832                    dev->dev_addr[5]);
5833
5834         dev_printk(KERN_INFO, &pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
5835                    dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
5836                    dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ?
5837                         "csum " : "",
5838                    dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
5839                         "vlan " : "",
5840                    id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
5841                    id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
5842                    id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
5843                    np->gigabit == PHY_GIGABIT ? "gbit " : "",
5844                    np->need_linktimer ? "lnktim " : "",
5845                    np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
5846                    np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
5847                    np->desc_ver);
5848
5849         return 0;
5850
5851 out_error:
5852         if (phystate_orig)
5853                 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
5854         pci_set_drvdata(pci_dev, NULL);
5855 out_freering:
5856         free_rings(dev);
5857 out_unmap:
5858         iounmap(get_hwbase(dev));
5859 out_relreg:
5860         pci_release_regions(pci_dev);
5861 out_disable:
5862         pci_disable_device(pci_dev);
5863 out_free:
5864         free_netdev(dev);
5865 out:
5866         return err;
5867 }
5868
5869 static void nv_restore_phy(struct net_device *dev)
5870 {
5871         struct fe_priv *np = netdev_priv(dev);
5872         u16 phy_reserved, mii_control;
5873
5874         if (np->phy_oui == PHY_OUI_REALTEK &&
5875             np->phy_model == PHY_MODEL_REALTEK_8201 &&
5876             phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
5877                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
5878                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
5879                 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
5880                 phy_reserved |= PHY_REALTEK_INIT8;
5881                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
5882                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
5883
5884                 /* restart auto negotiation */
5885                 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
5886                 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
5887                 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);
5888         }
5889 }
5890
5891 static void nv_restore_mac_addr(struct pci_dev *pci_dev)
5892 {
5893         struct net_device *dev = pci_get_drvdata(pci_dev);
5894         struct fe_priv *np = netdev_priv(dev);
5895         u8 __iomem *base = get_hwbase(dev);
5896
5897         /* special op: write back the misordered MAC address - otherwise
5898          * the next nv_probe would see a wrong address.
5899          */
5900         writel(np->orig_mac[0], base + NvRegMacAddrA);
5901         writel(np->orig_mac[1], base + NvRegMacAddrB);
5902         writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
5903                base + NvRegTransmitPoll);
5904 }
5905
5906 static void __devexit nv_remove(struct pci_dev *pci_dev)
5907 {
5908         struct net_device *dev = pci_get_drvdata(pci_dev);
5909
5910         unregister_netdev(dev);
5911
5912         nv_restore_mac_addr(pci_dev);
5913
5914         /* restore any phy related changes */
5915         nv_restore_phy(dev);
5916
5917         nv_mgmt_release_sema(dev);
5918
5919         /* free all structures */
5920         free_rings(dev);
5921         iounmap(get_hwbase(dev));
5922         pci_release_regions(pci_dev);
5923         pci_disable_device(pci_dev);
5924         free_netdev(dev);
5925         pci_set_drvdata(pci_dev, NULL);
5926 }
5927
5928 #ifdef CONFIG_PM
5929 static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
5930 {
5931         struct net_device *dev = pci_get_drvdata(pdev);
5932         struct fe_priv *np = netdev_priv(dev);
5933         u8 __iomem *base = get_hwbase(dev);
5934         int i;
5935
5936         if (netif_running(dev)) {
5937                 // Gross.
5938                 nv_close(dev);
5939         }
5940         netif_device_detach(dev);
5941
5942         /* save non-pci configuration space */
5943         for (i = 0;i <= np->register_size/sizeof(u32); i++)
5944                 np->saved_config_space[i] = readl(base + i*sizeof(u32));
5945
5946         pci_save_state(pdev);
5947         pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
5948         pci_disable_device(pdev);
5949         pci_set_power_state(pdev, pci_choose_state(pdev, state));
5950         return 0;
5951 }
5952
5953 static int nv_resume(struct pci_dev *pdev)
5954 {
5955         struct net_device *dev = pci_get_drvdata(pdev);
5956         struct fe_priv *np = netdev_priv(dev);
5957         u8 __iomem *base = get_hwbase(dev);
5958         int i, rc = 0;
5959
5960         pci_set_power_state(pdev, PCI_D0);
5961         pci_restore_state(pdev);
5962         /* ack any pending wake events, disable PME */
5963         pci_enable_wake(pdev, PCI_D0, 0);
5964
5965         /* restore non-pci configuration space */
5966         for (i = 0;i <= np->register_size/sizeof(u32); i++)
5967                 writel(np->saved_config_space[i], base+i*sizeof(u32));
5968
5969         if (np->driver_data & DEV_NEED_MSI_FIX)
5970                 pci_write_config_dword(pdev, NV_MSI_PRIV_OFFSET, NV_MSI_PRIV_VALUE);
5971
5972         /* restore phy state, including autoneg */
5973         phy_init(dev);
5974
5975         netif_device_attach(dev);
5976         if (netif_running(dev)) {
5977                 rc = nv_open(dev);
5978                 nv_set_multicast(dev);
5979         }
5980         return rc;
5981 }
5982
5983 static void nv_shutdown(struct pci_dev *pdev)
5984 {
5985         struct net_device *dev = pci_get_drvdata(pdev);
5986         struct fe_priv *np = netdev_priv(dev);
5987
5988         if (netif_running(dev))
5989                 nv_close(dev);
5990
5991         /*
5992          * Restore the MAC so a kernel started by kexec won't get confused.
5993          * If we really go for poweroff, we must not restore the MAC,
5994          * otherwise the MAC for WOL will be reversed at least on some boards.
5995          */
5996         if (system_state != SYSTEM_POWER_OFF) {
5997                 nv_restore_mac_addr(pdev);
5998         }
5999
6000         pci_disable_device(pdev);
6001         /*
6002          * Apparently it is not possible to reinitialise from D3 hot,
6003          * only put the device into D3 if we really go for poweroff.
6004          */
6005         if (system_state == SYSTEM_POWER_OFF) {
6006                 if (pci_enable_wake(pdev, PCI_D3cold, np->wolenabled))
6007                         pci_enable_wake(pdev, PCI_D3hot, np->wolenabled);
6008                 pci_set_power_state(pdev, PCI_D3hot);
6009         }
6010 }
6011 #else
6012 #define nv_suspend NULL
6013 #define nv_shutdown NULL
6014 #define nv_resume NULL
6015 #endif /* CONFIG_PM */
6016
6017 static DEFINE_PCI_DEVICE_TABLE(pci_tbl) = {
6018         {       /* nForce Ethernet Controller */
6019                 PCI_DEVICE(0x10DE, 0x01C3),
6020                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6021         },
6022         {       /* nForce2 Ethernet Controller */
6023                 PCI_DEVICE(0x10DE, 0x0066),
6024                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6025         },
6026         {       /* nForce3 Ethernet Controller */
6027                 PCI_DEVICE(0x10DE, 0x00D6),
6028                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6029         },
6030         {       /* nForce3 Ethernet Controller */
6031                 PCI_DEVICE(0x10DE, 0x0086),
6032                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6033         },
6034         {       /* nForce3 Ethernet Controller */
6035                 PCI_DEVICE(0x10DE, 0x008C),
6036                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6037         },
6038         {       /* nForce3 Ethernet Controller */
6039                 PCI_DEVICE(0x10DE, 0x00E6),
6040                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6041         },
6042         {       /* nForce3 Ethernet Controller */
6043                 PCI_DEVICE(0x10DE, 0x00DF),
6044                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6045         },
6046         {       /* CK804 Ethernet Controller */
6047                 PCI_DEVICE(0x10DE, 0x0056),
6048                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6049         },
6050         {       /* CK804 Ethernet Controller */
6051                 PCI_DEVICE(0x10DE, 0x0057),
6052                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6053         },
6054         {       /* MCP04 Ethernet Controller */
6055                 PCI_DEVICE(0x10DE, 0x0037),
6056                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6057         },
6058         {       /* MCP04 Ethernet Controller */
6059                 PCI_DEVICE(0x10DE, 0x0038),
6060                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6061         },
6062         {       /* MCP51 Ethernet Controller */
6063                 PCI_DEVICE(0x10DE, 0x0268),
6064                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
6065         },
6066         {       /* MCP51 Ethernet Controller */
6067                 PCI_DEVICE(0x10DE, 0x0269),
6068                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
6069         },
6070         {       /* MCP55 Ethernet Controller */
6071                 PCI_DEVICE(0x10DE, 0x0372),
6072                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
6073         },
6074         {       /* MCP55 Ethernet Controller */
6075                 PCI_DEVICE(0x10DE, 0x0373),
6076                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
6077         },
6078         {       /* MCP61 Ethernet Controller */
6079                 PCI_DEVICE(0x10DE, 0x03E5),
6080                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6081         },
6082         {       /* MCP61 Ethernet Controller */
6083                 PCI_DEVICE(0x10DE, 0x03E6),
6084                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6085         },
6086         {       /* MCP61 Ethernet Controller */
6087                 PCI_DEVICE(0x10DE, 0x03EE),
6088                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6089         },
6090         {       /* MCP61 Ethernet Controller */
6091                 PCI_DEVICE(0x10DE, 0x03EF),
6092                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6093         },
6094         {       /* MCP65 Ethernet Controller */
6095                 PCI_DEVICE(0x10DE, 0x0450),
6096                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6097         },
6098         {       /* MCP65 Ethernet Controller */
6099                 PCI_DEVICE(0x10DE, 0x0451),
6100                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6101         },
6102         {       /* MCP65 Ethernet Controller */
6103                 PCI_DEVICE(0x10DE, 0x0452),
6104                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6105         },
6106         {       /* MCP65 Ethernet Controller */
6107                 PCI_DEVICE(0x10DE, 0x0453),
6108                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6109         },
6110         {       /* MCP67 Ethernet Controller */
6111                 PCI_DEVICE(0x10DE, 0x054C),
6112                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6113         },
6114         {       /* MCP67 Ethernet Controller */
6115                 PCI_DEVICE(0x10DE, 0x054D),
6116                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6117         },
6118         {       /* MCP67 Ethernet Controller */
6119                 PCI_DEVICE(0x10DE, 0x054E),
6120                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6121         },
6122         {       /* MCP67 Ethernet Controller */
6123                 PCI_DEVICE(0x10DE, 0x054F),
6124                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6125         },
6126         {       /* MCP73 Ethernet Controller */
6127                 PCI_DEVICE(0x10DE, 0x07DC),
6128                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6129         },
6130         {       /* MCP73 Ethernet Controller */
6131                 PCI_DEVICE(0x10DE, 0x07DD),
6132                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6133         },
6134         {       /* MCP73 Ethernet Controller */
6135                 PCI_DEVICE(0x10DE, 0x07DE),
6136                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6137         },
6138         {       /* MCP73 Ethernet Controller */
6139                 PCI_DEVICE(0x10DE, 0x07DF),
6140                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6141         },
6142         {       /* MCP77 Ethernet Controller */
6143                 PCI_DEVICE(0x10DE, 0x0760),
6144                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6145         },
6146         {       /* MCP77 Ethernet Controller */
6147                 PCI_DEVICE(0x10DE, 0x0761),
6148                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6149         },
6150         {       /* MCP77 Ethernet Controller */
6151                 PCI_DEVICE(0x10DE, 0x0762),
6152                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6153         },
6154         {       /* MCP77 Ethernet Controller */
6155                 PCI_DEVICE(0x10DE, 0x0763),
6156                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6157         },
6158         {       /* MCP79 Ethernet Controller */
6159                 PCI_DEVICE(0x10DE, 0x0AB0),
6160                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6161         },
6162         {       /* MCP79 Ethernet Controller */
6163                 PCI_DEVICE(0x10DE, 0x0AB1),
6164                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6165         },
6166         {       /* MCP79 Ethernet Controller */
6167                 PCI_DEVICE(0x10DE, 0x0AB2),
6168                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6169         },
6170         {       /* MCP79 Ethernet Controller */
6171                 PCI_DEVICE(0x10DE, 0x0AB3),
6172                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6173         },
6174         {       /* MCP89 Ethernet Controller */
6175                 PCI_DEVICE(0x10DE, 0x0D7D),
6176                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX,
6177         },
6178         {0,},
6179 };
6180
6181 static struct pci_driver driver = {
6182         .name           = DRV_NAME,
6183         .id_table       = pci_tbl,
6184         .probe          = nv_probe,
6185         .remove         = __devexit_p(nv_remove),
6186         .suspend        = nv_suspend,
6187         .resume         = nv_resume,
6188         .shutdown       = nv_shutdown,
6189 };
6190
6191 static int __init init_nic(void)
6192 {
6193         return pci_register_driver(&driver);
6194 }
6195
6196 static void __exit exit_nic(void)
6197 {
6198         pci_unregister_driver(&driver);
6199 }
6200
6201 module_param(max_interrupt_work, int, 0);
6202 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
6203 module_param(optimization_mode, int, 0);
6204 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer. In dynamic mode (2), the mode toggles between throughput and CPU mode based on network load.");
6205 module_param(poll_interval, int, 0);
6206 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
6207 module_param(msi, int, 0);
6208 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
6209 module_param(msix, int, 0);
6210 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
6211 module_param(dma_64bit, int, 0);
6212 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
6213 module_param(phy_cross, int, 0);
6214 MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
6215 module_param(phy_power_down, int, 0);
6216 MODULE_PARM_DESC(phy_power_down, "Power down phy and disable link when interface is down (1), or leave phy powered up (0).");
6217
6218 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6219 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6220 MODULE_LICENSE("GPL");
6221
6222 MODULE_DEVICE_TABLE(pci, pci_tbl);
6223
6224 module_init(init_nic);
6225 module_exit(exit_nic);