2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey. It's neither supported nor endorsed
7 * by NVIDIA Corp. Use at your own risk.
9 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
10 * trademarks of NVIDIA Corporation in the United States and other
13 * Copyright (C) 2003,4,5 Manfred Spraul
14 * Copyright (C) 2004 Andrew de Quincey (wol support)
15 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
16 * IRQ rate fixes, bigendian fixes, cleanups, verification)
17 * Copyright (c) 2004 NVIDIA Corporation
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License as published by
21 * the Free Software Foundation; either version 2 of the License, or
22 * (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
34 * 0.01: 05 Oct 2003: First release that compiles without warnings.
35 * 0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
36 * Check all PCI BARs for the register window.
37 * udelay added to mii_rw.
38 * 0.03: 06 Oct 2003: Initialize dev->irq.
39 * 0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
40 * 0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
41 * 0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
43 * 0.07: 14 Oct 2003: Further irq mask updates.
44 * 0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
45 * added into irq handler, NULL check for drain_ring.
46 * 0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
47 * requested interrupt sources.
48 * 0.10: 20 Oct 2003: First cleanup for release.
49 * 0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
50 * MAC Address init fix, set_multicast cleanup.
51 * 0.12: 23 Oct 2003: Cleanups for release.
52 * 0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
53 * Set link speed correctly. start rx before starting
54 * tx (nv_start_rx sets the link speed).
55 * 0.14: 25 Oct 2003: Nic dependant irq mask.
56 * 0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
58 * 0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
59 * increased to 1628 bytes.
60 * 0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
62 * 0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
63 * 0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
64 * addresses, really stop rx if already running
65 * in nv_start_rx, clean up a bit.
66 * 0.20: 07 Dec 2003: alloc fixes
67 * 0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
68 * 0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
70 * 0.23: 26 Jan 2004: various small cleanups
71 * 0.24: 27 Feb 2004: make driver even less anonymous in backtraces
72 * 0.25: 09 Mar 2004: wol support
73 * 0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
74 * 0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
75 * added CK804/MCP04 device IDs, code fixes
76 * for registers, link status and other minor fixes.
77 * 0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
78 * 0.29: 31 Aug 2004: Add backup timer for link change notification.
79 * 0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
80 * into nv_close, otherwise reenabling for wol can
81 * cause DMA to kfree'd memory.
82 * 0.31: 14 Nov 2004: ethtool support for getting/setting link
84 * 0.32: 16 Apr 2005: RX_ERROR4 handling added.
85 * 0.33: 16 May 2005: Support for MCP51 added.
86 * 0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
87 * 0.35: 26 Jun 2005: Support for MCP55 added.
88 * 0.36: 28 Jun 2005: Add jumbo frame support.
89 * 0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
90 * 0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
92 * 0.39: 18 Jul 2005: Add 64bit descriptor support.
93 * 0.40: 19 Jul 2005: Add support for mac address change.
94 * 0.41: 30 Jul 2005: Write back original MAC in nv_close instead
96 * 0.42: 06 Aug 2005: Fix lack of link speed initialization
97 * in the second (and later) nv_open call
98 * 0.43: 10 Aug 2005: Add support for tx checksum.
99 * 0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
100 * 0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
101 * 0.46: 20 Oct 2005: Add irq optimization modes.
102 * 0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
103 * 0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
104 * 0.49: 10 Dec 2005: Fix tso for large buffers.
105 * 0.50: 20 Jan 2006: Add 8021pq tagging support.
106 * 0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
109 * We suspect that on some hardware no TX done interrupts are generated.
110 * This means recovery from netif_stop_queue only happens if the hw timer
111 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
112 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
113 * If your hardware reliably generates tx done interrupts, then you can remove
114 * DEV_NEED_TIMERIRQ from the driver_data flags.
115 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
116 * superfluous timer interrupts from the nic.
118 #define FORCEDETH_VERSION "0.51"
119 #define DRV_NAME "forcedeth"
121 #include <linux/module.h>
122 #include <linux/types.h>
123 #include <linux/pci.h>
124 #include <linux/interrupt.h>
125 #include <linux/netdevice.h>
126 #include <linux/etherdevice.h>
127 #include <linux/delay.h>
128 #include <linux/spinlock.h>
129 #include <linux/ethtool.h>
130 #include <linux/timer.h>
131 #include <linux/skbuff.h>
132 #include <linux/mii.h>
133 #include <linux/random.h>
134 #include <linux/init.h>
135 #include <linux/if_vlan.h>
139 #include <asm/uaccess.h>
140 #include <asm/system.h>
143 #define dprintk printk
145 #define dprintk(x...) do { } while (0)
153 #define DEV_NEED_TIMERIRQ 0x0001 /* set the timer irq flag in the irq mask */
154 #define DEV_NEED_LINKTIMER 0x0002 /* poll link settings. Relies on the timer irq */
155 #define DEV_HAS_LARGEDESC 0x0004 /* device supports jumbo frames and needs packet format 2 */
156 #define DEV_HAS_HIGH_DMA 0x0008 /* device supports 64bit dma */
157 #define DEV_HAS_CHECKSUM 0x0010 /* device supports tx and rx checksum offloads */
158 #define DEV_HAS_VLAN 0x0020 /* device supports vlan tagging and striping */
161 NvRegIrqStatus = 0x000,
162 #define NVREG_IRQSTAT_MIIEVENT 0x040
163 #define NVREG_IRQSTAT_MASK 0x1ff
164 NvRegIrqMask = 0x004,
165 #define NVREG_IRQ_RX_ERROR 0x0001
166 #define NVREG_IRQ_RX 0x0002
167 #define NVREG_IRQ_RX_NOBUF 0x0004
168 #define NVREG_IRQ_TX_ERR 0x0008
169 #define NVREG_IRQ_TX_OK 0x0010
170 #define NVREG_IRQ_TIMER 0x0020
171 #define NVREG_IRQ_LINK 0x0040
172 #define NVREG_IRQ_TX_ERROR 0x0080
173 #define NVREG_IRQ_TX1 0x0100
174 #define NVREG_IRQMASK_THROUGHPUT 0x00df
175 #define NVREG_IRQMASK_CPU 0x0040
177 #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
178 NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_TX_ERROR| \
181 NvRegUnknownSetupReg6 = 0x008,
182 #define NVREG_UNKSETUP6_VAL 3
185 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
186 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
188 NvRegPollingInterval = 0x00c,
189 #define NVREG_POLL_DEFAULT_THROUGHPUT 970
190 #define NVREG_POLL_DEFAULT_CPU 13
192 #define NVREG_MISC1_HD 0x02
193 #define NVREG_MISC1_FORCE 0x3b0f3c
195 NvRegTransmitterControl = 0x084,
196 #define NVREG_XMITCTL_START 0x01
197 NvRegTransmitterStatus = 0x088,
198 #define NVREG_XMITSTAT_BUSY 0x01
200 NvRegPacketFilterFlags = 0x8c,
201 #define NVREG_PFF_ALWAYS 0x7F0008
202 #define NVREG_PFF_PROMISC 0x80
203 #define NVREG_PFF_MYADDR 0x20
205 NvRegOffloadConfig = 0x90,
206 #define NVREG_OFFLOAD_HOMEPHY 0x601
207 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
208 NvRegReceiverControl = 0x094,
209 #define NVREG_RCVCTL_START 0x01
210 NvRegReceiverStatus = 0x98,
211 #define NVREG_RCVSTAT_BUSY 0x01
213 NvRegRandomSeed = 0x9c,
214 #define NVREG_RNDSEED_MASK 0x00ff
215 #define NVREG_RNDSEED_FORCE 0x7f00
216 #define NVREG_RNDSEED_FORCE2 0x2d00
217 #define NVREG_RNDSEED_FORCE3 0x7400
219 NvRegUnknownSetupReg1 = 0xA0,
220 #define NVREG_UNKSETUP1_VAL 0x16070f
221 NvRegUnknownSetupReg2 = 0xA4,
222 #define NVREG_UNKSETUP2_VAL 0x16
223 NvRegMacAddrA = 0xA8,
224 NvRegMacAddrB = 0xAC,
225 NvRegMulticastAddrA = 0xB0,
226 #define NVREG_MCASTADDRA_FORCE 0x01
227 NvRegMulticastAddrB = 0xB4,
228 NvRegMulticastMaskA = 0xB8,
229 NvRegMulticastMaskB = 0xBC,
231 NvRegPhyInterface = 0xC0,
232 #define PHY_RGMII 0x10000000
234 NvRegTxRingPhysAddr = 0x100,
235 NvRegRxRingPhysAddr = 0x104,
236 NvRegRingSizes = 0x108,
237 #define NVREG_RINGSZ_TXSHIFT 0
238 #define NVREG_RINGSZ_RXSHIFT 16
239 NvRegUnknownTransmitterReg = 0x10c,
240 NvRegLinkSpeed = 0x110,
241 #define NVREG_LINKSPEED_FORCE 0x10000
242 #define NVREG_LINKSPEED_10 1000
243 #define NVREG_LINKSPEED_100 100
244 #define NVREG_LINKSPEED_1000 50
245 #define NVREG_LINKSPEED_MASK (0xFFF)
246 NvRegUnknownSetupReg5 = 0x130,
247 #define NVREG_UNKSETUP5_BIT31 (1<<31)
248 NvRegUnknownSetupReg3 = 0x13c,
249 #define NVREG_UNKSETUP3_VAL1 0x200010
250 NvRegTxRxControl = 0x144,
251 #define NVREG_TXRXCTL_KICK 0x0001
252 #define NVREG_TXRXCTL_BIT1 0x0002
253 #define NVREG_TXRXCTL_BIT2 0x0004
254 #define NVREG_TXRXCTL_IDLE 0x0008
255 #define NVREG_TXRXCTL_RESET 0x0010
256 #define NVREG_TXRXCTL_RXCHECK 0x0400
257 #define NVREG_TXRXCTL_DESC_1 0
258 #define NVREG_TXRXCTL_DESC_2 0x02100
259 #define NVREG_TXRXCTL_DESC_3 0x02200
260 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
261 #define NVREG_TXRXCTL_VLANINS 0x00080
262 NvRegTxRingPhysAddrHigh = 0x148,
263 NvRegRxRingPhysAddrHigh = 0x14C,
264 NvRegMIIStatus = 0x180,
265 #define NVREG_MIISTAT_ERROR 0x0001
266 #define NVREG_MIISTAT_LINKCHANGE 0x0008
267 #define NVREG_MIISTAT_MASK 0x000f
268 #define NVREG_MIISTAT_MASK2 0x000f
269 NvRegUnknownSetupReg4 = 0x184,
270 #define NVREG_UNKSETUP4_VAL 8
272 NvRegAdapterControl = 0x188,
273 #define NVREG_ADAPTCTL_START 0x02
274 #define NVREG_ADAPTCTL_LINKUP 0x04
275 #define NVREG_ADAPTCTL_PHYVALID 0x40000
276 #define NVREG_ADAPTCTL_RUNNING 0x100000
277 #define NVREG_ADAPTCTL_PHYSHIFT 24
278 NvRegMIISpeed = 0x18c,
279 #define NVREG_MIISPEED_BIT8 (1<<8)
280 #define NVREG_MIIDELAY 5
281 NvRegMIIControl = 0x190,
282 #define NVREG_MIICTL_INUSE 0x08000
283 #define NVREG_MIICTL_WRITE 0x00400
284 #define NVREG_MIICTL_ADDRSHIFT 5
285 NvRegMIIData = 0x194,
286 NvRegWakeUpFlags = 0x200,
287 #define NVREG_WAKEUPFLAGS_VAL 0x7770
288 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
289 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
290 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
291 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
292 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
293 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
294 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
295 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
296 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
297 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
299 NvRegPatternCRC = 0x204,
300 NvRegPatternMask = 0x208,
301 NvRegPowerCap = 0x268,
302 #define NVREG_POWERCAP_D3SUPP (1<<30)
303 #define NVREG_POWERCAP_D2SUPP (1<<26)
304 #define NVREG_POWERCAP_D1SUPP (1<<25)
305 NvRegPowerState = 0x26c,
306 #define NVREG_POWERSTATE_POWEREDUP 0x8000
307 #define NVREG_POWERSTATE_VALID 0x0100
308 #define NVREG_POWERSTATE_MASK 0x0003
309 #define NVREG_POWERSTATE_D0 0x0000
310 #define NVREG_POWERSTATE_D1 0x0001
311 #define NVREG_POWERSTATE_D2 0x0002
312 #define NVREG_POWERSTATE_D3 0x0003
313 NvRegVlanControl = 0x300,
314 #define NVREG_VLANCONTROL_ENABLE 0x2000
317 /* Big endian: should work, but is untested */
323 struct ring_desc_ex {
324 u32 PacketBufferHigh;
330 typedef union _ring_type {
331 struct ring_desc* orig;
332 struct ring_desc_ex* ex;
335 #define FLAG_MASK_V1 0xffff0000
336 #define FLAG_MASK_V2 0xffffc000
337 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
338 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
340 #define NV_TX_LASTPACKET (1<<16)
341 #define NV_TX_RETRYERROR (1<<19)
342 #define NV_TX_FORCED_INTERRUPT (1<<24)
343 #define NV_TX_DEFERRED (1<<26)
344 #define NV_TX_CARRIERLOST (1<<27)
345 #define NV_TX_LATECOLLISION (1<<28)
346 #define NV_TX_UNDERFLOW (1<<29)
347 #define NV_TX_ERROR (1<<30)
348 #define NV_TX_VALID (1<<31)
350 #define NV_TX2_LASTPACKET (1<<29)
351 #define NV_TX2_RETRYERROR (1<<18)
352 #define NV_TX2_FORCED_INTERRUPT (1<<30)
353 #define NV_TX2_DEFERRED (1<<25)
354 #define NV_TX2_CARRIERLOST (1<<26)
355 #define NV_TX2_LATECOLLISION (1<<27)
356 #define NV_TX2_UNDERFLOW (1<<28)
357 /* error and valid are the same for both */
358 #define NV_TX2_ERROR (1<<30)
359 #define NV_TX2_VALID (1<<31)
360 #define NV_TX2_TSO (1<<28)
361 #define NV_TX2_TSO_SHIFT 14
362 #define NV_TX2_TSO_MAX_SHIFT 14
363 #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
364 #define NV_TX2_CHECKSUM_L3 (1<<27)
365 #define NV_TX2_CHECKSUM_L4 (1<<26)
367 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
369 #define NV_RX_DESCRIPTORVALID (1<<16)
370 #define NV_RX_MISSEDFRAME (1<<17)
371 #define NV_RX_SUBSTRACT1 (1<<18)
372 #define NV_RX_ERROR1 (1<<23)
373 #define NV_RX_ERROR2 (1<<24)
374 #define NV_RX_ERROR3 (1<<25)
375 #define NV_RX_ERROR4 (1<<26)
376 #define NV_RX_CRCERR (1<<27)
377 #define NV_RX_OVERFLOW (1<<28)
378 #define NV_RX_FRAMINGERR (1<<29)
379 #define NV_RX_ERROR (1<<30)
380 #define NV_RX_AVAIL (1<<31)
382 #define NV_RX2_CHECKSUMMASK (0x1C000000)
383 #define NV_RX2_CHECKSUMOK1 (0x10000000)
384 #define NV_RX2_CHECKSUMOK2 (0x14000000)
385 #define NV_RX2_CHECKSUMOK3 (0x18000000)
386 #define NV_RX2_DESCRIPTORVALID (1<<29)
387 #define NV_RX2_SUBSTRACT1 (1<<25)
388 #define NV_RX2_ERROR1 (1<<18)
389 #define NV_RX2_ERROR2 (1<<19)
390 #define NV_RX2_ERROR3 (1<<20)
391 #define NV_RX2_ERROR4 (1<<21)
392 #define NV_RX2_CRCERR (1<<22)
393 #define NV_RX2_OVERFLOW (1<<23)
394 #define NV_RX2_FRAMINGERR (1<<24)
395 /* error and avail are the same for both */
396 #define NV_RX2_ERROR (1<<30)
397 #define NV_RX2_AVAIL (1<<31)
399 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
400 #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
402 /* Miscelaneous hardware related defines: */
403 #define NV_PCI_REGSZ 0x270
405 /* various timeout delays: all in usec */
406 #define NV_TXRX_RESET_DELAY 4
407 #define NV_TXSTOP_DELAY1 10
408 #define NV_TXSTOP_DELAY1MAX 500000
409 #define NV_TXSTOP_DELAY2 100
410 #define NV_RXSTOP_DELAY1 10
411 #define NV_RXSTOP_DELAY1MAX 500000
412 #define NV_RXSTOP_DELAY2 100
413 #define NV_SETUP5_DELAY 5
414 #define NV_SETUP5_DELAYMAX 50000
415 #define NV_POWERUP_DELAY 5
416 #define NV_POWERUP_DELAYMAX 5000
417 #define NV_MIIBUSY_DELAY 50
418 #define NV_MIIPHY_DELAY 10
419 #define NV_MIIPHY_DELAYMAX 10000
421 #define NV_WAKEUPPATTERNS 5
422 #define NV_WAKEUPMASKENTRIES 4
424 /* General driver defaults */
425 #define NV_WATCHDOG_TIMEO (5*HZ)
430 * If your nic mysteriously hangs then try to reduce the limits
431 * to 1/0: It might be required to set NV_TX_LASTPACKET in the
432 * last valid ring entry. But this would be impossible to
433 * implement - probably a disassembly error.
435 #define TX_LIMIT_STOP 255
436 #define TX_LIMIT_START 254
438 /* rx/tx mac addr + type + vlan + align + slack*/
439 #define NV_RX_HEADERS (64)
440 /* even more slack. */
441 #define NV_RX_ALLOC_PAD (64)
443 /* maximum mtu size */
444 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
445 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
447 #define OOM_REFILL (1+HZ/20)
448 #define POLL_WAIT (1+HZ/100)
449 #define LINK_TIMEOUT (3*HZ)
453 * The nic supports three different descriptor types:
454 * - DESC_VER_1: Original
455 * - DESC_VER_2: support for jumbo frames.
456 * - DESC_VER_3: 64-bit format.
463 #define PHY_OUI_MARVELL 0x5043
464 #define PHY_OUI_CICADA 0x03f1
465 #define PHYID1_OUI_MASK 0x03ff
466 #define PHYID1_OUI_SHFT 6
467 #define PHYID2_OUI_MASK 0xfc00
468 #define PHYID2_OUI_SHFT 10
469 #define PHY_INIT1 0x0f000
470 #define PHY_INIT2 0x0e00
471 #define PHY_INIT3 0x01000
472 #define PHY_INIT4 0x0200
473 #define PHY_INIT5 0x0004
474 #define PHY_INIT6 0x02000
475 #define PHY_GIGABIT 0x0100
477 #define PHY_TIMEOUT 0x1
478 #define PHY_ERROR 0x2
482 #define PHY_HALF 0x100
484 /* FIXME: MII defines that should be added to <linux/mii.h> */
485 #define MII_1000BT_CR 0x09
486 #define MII_1000BT_SR 0x0a
487 #define ADVERTISE_1000FULL 0x0200
488 #define ADVERTISE_1000HALF 0x0100
489 #define LPA_1000FULL 0x0800
490 #define LPA_1000HALF 0x0400
495 * All hardware access under dev->priv->lock, except the performance
497 * - rx is (pseudo-) lockless: it relies on the single-threading provided
498 * by the arch code for interrupts.
499 * - tx setup is lockless: it relies on dev->xmit_lock. Actual submission
500 * needs dev->priv->lock :-(
501 * - set_multicast_list: preparation lockless, relies on dev->xmit_lock.
504 /* in dev: base, irq */
509 * Locking: spin_lock(&np->lock); */
510 struct net_device_stats stats;
518 unsigned int phy_oui;
521 /* General data: RO fields */
522 dma_addr_t ring_addr;
523 struct pci_dev *pci_dev;
532 /* rx specific fields.
533 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
536 unsigned int cur_rx, refill_rx;
537 struct sk_buff *rx_skbuff[RX_RING];
538 dma_addr_t rx_dma[RX_RING];
539 unsigned int rx_buf_sz;
540 unsigned int pkt_limit;
541 struct timer_list oom_kick;
542 struct timer_list nic_poll;
544 /* media detection workaround.
545 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
548 unsigned long link_timeout;
550 * tx specific fields.
553 unsigned int next_tx, nic_tx;
554 struct sk_buff *tx_skbuff[TX_RING];
555 dma_addr_t tx_dma[TX_RING];
556 unsigned int tx_dma_len[TX_RING];
560 struct vlan_group *vlangrp;
564 * Maximum number of loops until we assume that a bit in the irq mask
565 * is stuck. Overridable with module param.
567 static int max_interrupt_work = 5;
570 * Optimization can be either throuput mode or cpu mode
572 * Throughput Mode: Every tx and rx packet will generate an interrupt.
573 * CPU Mode: Interrupts are controlled by a timer.
575 #define NV_OPTIMIZATION_MODE_THROUGHPUT 0
576 #define NV_OPTIMIZATION_MODE_CPU 1
577 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
580 * Poll interval for timer irq
582 * This interval determines how frequent an interrupt is generated.
583 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
584 * Min = 0, and Max = 65535
586 static int poll_interval = -1;
588 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
590 return netdev_priv(dev);
593 static inline u8 __iomem *get_hwbase(struct net_device *dev)
595 return ((struct fe_priv *)netdev_priv(dev))->base;
598 static inline void pci_push(u8 __iomem *base)
600 /* force out pending posted writes */
604 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
606 return le32_to_cpu(prd->FlagLen)
607 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
610 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
612 return le32_to_cpu(prd->FlagLen) & LEN_MASK_V2;
615 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
616 int delay, int delaymax, const char *msg)
618 u8 __iomem *base = get_hwbase(dev);
629 } while ((readl(base + offset) & mask) != target);
633 #define NV_SETUP_RX_RING 0x01
634 #define NV_SETUP_TX_RING 0x02
636 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
638 struct fe_priv *np = get_nvpriv(dev);
639 u8 __iomem *base = get_hwbase(dev);
641 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
642 if (rxtx_flags & NV_SETUP_RX_RING) {
643 writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
645 if (rxtx_flags & NV_SETUP_TX_RING) {
646 writel((u32) cpu_to_le64(np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
649 if (rxtx_flags & NV_SETUP_RX_RING) {
650 writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
651 writel((u32) (cpu_to_le64(np->ring_addr) >> 32), base + NvRegRxRingPhysAddrHigh);
653 if (rxtx_flags & NV_SETUP_TX_RING) {
654 writel((u32) cpu_to_le64(np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
655 writel((u32) (cpu_to_le64(np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)) >> 32), base + NvRegTxRingPhysAddrHigh);
660 #define MII_READ (-1)
661 /* mii_rw: read/write a register on the PHY.
663 * Caller must guarantee serialization
665 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
667 u8 __iomem *base = get_hwbase(dev);
671 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
673 reg = readl(base + NvRegMIIControl);
674 if (reg & NVREG_MIICTL_INUSE) {
675 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
676 udelay(NV_MIIBUSY_DELAY);
679 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
680 if (value != MII_READ) {
681 writel(value, base + NvRegMIIData);
682 reg |= NVREG_MIICTL_WRITE;
684 writel(reg, base + NvRegMIIControl);
686 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
687 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
688 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
689 dev->name, miireg, addr);
691 } else if (value != MII_READ) {
692 /* it was a write operation - fewer failures are detectable */
693 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
694 dev->name, value, miireg, addr);
696 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
697 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
698 dev->name, miireg, addr);
701 retval = readl(base + NvRegMIIData);
702 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
703 dev->name, miireg, addr, retval);
709 static int phy_reset(struct net_device *dev)
711 struct fe_priv *np = netdev_priv(dev);
713 unsigned int tries = 0;
715 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
716 miicontrol |= BMCR_RESET;
717 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
724 /* must wait till reset is deasserted */
725 while (miicontrol & BMCR_RESET) {
727 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
728 /* FIXME: 100 tries seem excessive */
735 static int phy_init(struct net_device *dev)
737 struct fe_priv *np = get_nvpriv(dev);
738 u8 __iomem *base = get_hwbase(dev);
739 u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
741 /* set advertise register */
742 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
743 reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|0x800|0x400);
744 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
745 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
749 /* get phy interface type */
750 phyinterface = readl(base + NvRegPhyInterface);
752 /* see if gigabit phy */
753 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
754 if (mii_status & PHY_GIGABIT) {
755 np->gigabit = PHY_GIGABIT;
756 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
757 mii_control_1000 &= ~ADVERTISE_1000HALF;
758 if (phyinterface & PHY_RGMII)
759 mii_control_1000 |= ADVERTISE_1000FULL;
761 mii_control_1000 &= ~ADVERTISE_1000FULL;
763 if (mii_rw(dev, np->phyaddr, MII_1000BT_CR, mii_control_1000)) {
764 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
772 if (phy_reset(dev)) {
773 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
777 /* phy vendor specific configuration */
778 if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
779 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
780 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
781 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
782 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
783 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
786 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
787 phy_reserved |= PHY_INIT5;
788 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
789 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
793 if (np->phy_oui == PHY_OUI_CICADA) {
794 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
795 phy_reserved |= PHY_INIT6;
796 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
797 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
802 /* restart auto negotiation */
803 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
804 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
805 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
812 static void nv_start_rx(struct net_device *dev)
814 struct fe_priv *np = netdev_priv(dev);
815 u8 __iomem *base = get_hwbase(dev);
817 dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
818 /* Already running? Stop it. */
819 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
820 writel(0, base + NvRegReceiverControl);
823 writel(np->linkspeed, base + NvRegLinkSpeed);
825 writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
826 dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
827 dev->name, np->duplex, np->linkspeed);
831 static void nv_stop_rx(struct net_device *dev)
833 u8 __iomem *base = get_hwbase(dev);
835 dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
836 writel(0, base + NvRegReceiverControl);
837 reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
838 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
839 KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
841 udelay(NV_RXSTOP_DELAY2);
842 writel(0, base + NvRegLinkSpeed);
845 static void nv_start_tx(struct net_device *dev)
847 u8 __iomem *base = get_hwbase(dev);
849 dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
850 writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
854 static void nv_stop_tx(struct net_device *dev)
856 u8 __iomem *base = get_hwbase(dev);
858 dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
859 writel(0, base + NvRegTransmitterControl);
860 reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
861 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
862 KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
864 udelay(NV_TXSTOP_DELAY2);
865 writel(0, base + NvRegUnknownTransmitterReg);
868 static void nv_txrx_reset(struct net_device *dev)
870 struct fe_priv *np = netdev_priv(dev);
871 u8 __iomem *base = get_hwbase(dev);
873 dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
874 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
876 udelay(NV_TXRX_RESET_DELAY);
877 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
882 * nv_get_stats: dev->get_stats function
883 * Get latest stats value from the nic.
884 * Called with read_lock(&dev_base_lock) held for read -
885 * only synchronized against unregister_netdevice.
887 static struct net_device_stats *nv_get_stats(struct net_device *dev)
889 struct fe_priv *np = netdev_priv(dev);
891 /* It seems that the nic always generates interrupts and doesn't
892 * accumulate errors internally. Thus the current values in np->stats
893 * are already up to date.
899 * nv_alloc_rx: fill rx ring entries.
900 * Return 1 if the allocations for the skbs failed and the
901 * rx engine is without Available descriptors
903 static int nv_alloc_rx(struct net_device *dev)
905 struct fe_priv *np = netdev_priv(dev);
906 unsigned int refill_rx = np->refill_rx;
909 while (np->cur_rx != refill_rx) {
912 nr = refill_rx % RX_RING;
913 if (np->rx_skbuff[nr] == NULL) {
915 skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
920 np->rx_skbuff[nr] = skb;
922 skb = np->rx_skbuff[nr];
924 np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data,
925 skb->end-skb->data, PCI_DMA_FROMDEVICE);
926 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
927 np->rx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->rx_dma[nr]);
929 np->rx_ring.orig[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
931 np->rx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->rx_dma[nr]) >> 32;
932 np->rx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->rx_dma[nr]) & 0x0FFFFFFFF;
934 np->rx_ring.ex[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
936 dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n",
937 dev->name, refill_rx);
940 np->refill_rx = refill_rx;
941 if (np->cur_rx - refill_rx == RX_RING)
946 static void nv_do_rx_refill(unsigned long data)
948 struct net_device *dev = (struct net_device *) data;
949 struct fe_priv *np = netdev_priv(dev);
951 disable_irq(dev->irq);
952 if (nv_alloc_rx(dev)) {
953 spin_lock(&np->lock);
954 if (!np->in_shutdown)
955 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
956 spin_unlock(&np->lock);
958 enable_irq(dev->irq);
961 static void nv_init_rx(struct net_device *dev)
963 struct fe_priv *np = netdev_priv(dev);
966 np->cur_rx = RX_RING;
968 for (i = 0; i < RX_RING; i++)
969 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
970 np->rx_ring.orig[i].FlagLen = 0;
972 np->rx_ring.ex[i].FlagLen = 0;
975 static void nv_init_tx(struct net_device *dev)
977 struct fe_priv *np = netdev_priv(dev);
980 np->next_tx = np->nic_tx = 0;
981 for (i = 0; i < TX_RING; i++) {
982 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
983 np->tx_ring.orig[i].FlagLen = 0;
985 np->tx_ring.ex[i].FlagLen = 0;
986 np->tx_skbuff[i] = NULL;
991 static int nv_init_ring(struct net_device *dev)
995 return nv_alloc_rx(dev);
998 static int nv_release_txskb(struct net_device *dev, unsigned int skbnr)
1000 struct fe_priv *np = netdev_priv(dev);
1002 dprintk(KERN_INFO "%s: nv_release_txskb for skbnr %d\n",
1005 if (np->tx_dma[skbnr]) {
1006 pci_unmap_page(np->pci_dev, np->tx_dma[skbnr],
1007 np->tx_dma_len[skbnr],
1009 np->tx_dma[skbnr] = 0;
1012 if (np->tx_skbuff[skbnr]) {
1013 dev_kfree_skb_irq(np->tx_skbuff[skbnr]);
1014 np->tx_skbuff[skbnr] = NULL;
1021 static void nv_drain_tx(struct net_device *dev)
1023 struct fe_priv *np = netdev_priv(dev);
1026 for (i = 0; i < TX_RING; i++) {
1027 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1028 np->tx_ring.orig[i].FlagLen = 0;
1030 np->tx_ring.ex[i].FlagLen = 0;
1031 if (nv_release_txskb(dev, i))
1032 np->stats.tx_dropped++;
1036 static void nv_drain_rx(struct net_device *dev)
1038 struct fe_priv *np = netdev_priv(dev);
1040 for (i = 0; i < RX_RING; i++) {
1041 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1042 np->rx_ring.orig[i].FlagLen = 0;
1044 np->rx_ring.ex[i].FlagLen = 0;
1046 if (np->rx_skbuff[i]) {
1047 pci_unmap_single(np->pci_dev, np->rx_dma[i],
1048 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
1049 PCI_DMA_FROMDEVICE);
1050 dev_kfree_skb(np->rx_skbuff[i]);
1051 np->rx_skbuff[i] = NULL;
1056 static void drain_ring(struct net_device *dev)
1063 * nv_start_xmit: dev->hard_start_xmit function
1064 * Called with dev->xmit_lock held.
1066 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1068 struct fe_priv *np = netdev_priv(dev);
1070 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
1071 unsigned int fragments = skb_shinfo(skb)->nr_frags;
1072 unsigned int nr = (np->next_tx - 1) % TX_RING;
1073 unsigned int start_nr = np->next_tx % TX_RING;
1077 u32 size = skb->len-skb->data_len;
1078 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1079 u32 tx_flags_vlan = 0;
1081 /* add fragments to entries count */
1082 for (i = 0; i < fragments; i++) {
1083 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1084 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1087 spin_lock_irq(&np->lock);
1089 if ((np->next_tx - np->nic_tx + entries - 1) > TX_LIMIT_STOP) {
1090 spin_unlock_irq(&np->lock);
1091 netif_stop_queue(dev);
1092 return NETDEV_TX_BUSY;
1095 /* setup the header buffer */
1097 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1098 nr = (nr + 1) % TX_RING;
1100 np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1102 np->tx_dma_len[nr] = bcnt;
1104 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1105 np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
1106 np->tx_ring.orig[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
1108 np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1109 np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1110 np->tx_ring.ex[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
1112 tx_flags = np->tx_flags;
1117 /* setup the fragments */
1118 for (i = 0; i < fragments; i++) {
1119 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1120 u32 size = frag->size;
1124 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1125 nr = (nr + 1) % TX_RING;
1127 np->tx_dma[nr] = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1129 np->tx_dma_len[nr] = bcnt;
1131 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1132 np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
1133 np->tx_ring.orig[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
1135 np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1136 np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1137 np->tx_ring.ex[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
1144 /* set last fragment flag */
1145 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1146 np->tx_ring.orig[nr].FlagLen |= cpu_to_le32(tx_flags_extra);
1148 np->tx_ring.ex[nr].FlagLen |= cpu_to_le32(tx_flags_extra);
1151 np->tx_skbuff[nr] = skb;
1154 if (skb_shinfo(skb)->tso_size)
1155 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->tso_size << NV_TX2_TSO_SHIFT);
1158 tx_flags_extra = (skb->ip_summed == CHECKSUM_HW ? (NV_TX2_CHECKSUM_L3|NV_TX2_CHECKSUM_L4) : 0);
1161 if (np->vlangrp && vlan_tx_tag_present(skb)) {
1162 tx_flags_vlan = NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb);
1166 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1167 np->tx_ring.orig[start_nr].FlagLen |= cpu_to_le32(tx_flags | tx_flags_extra);
1169 np->tx_ring.ex[start_nr].TxVlan = cpu_to_le32(tx_flags_vlan);
1170 np->tx_ring.ex[start_nr].FlagLen |= cpu_to_le32(tx_flags | tx_flags_extra);
1173 dprintk(KERN_DEBUG "%s: nv_start_xmit: packet %d (entries %d) queued for transmission. tx_flags_extra: %x\n",
1174 dev->name, np->next_tx, entries, tx_flags_extra);
1177 for (j=0; j<64; j++) {
1179 dprintk("\n%03x:", j);
1180 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1185 np->next_tx += entries;
1187 dev->trans_start = jiffies;
1188 spin_unlock_irq(&np->lock);
1189 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1190 pci_push(get_hwbase(dev));
1191 return NETDEV_TX_OK;
1195 * nv_tx_done: check for completed packets, release the skbs.
1197 * Caller must own np->lock.
1199 static void nv_tx_done(struct net_device *dev)
1201 struct fe_priv *np = netdev_priv(dev);
1204 struct sk_buff *skb;
1206 while (np->nic_tx != np->next_tx) {
1207 i = np->nic_tx % TX_RING;
1209 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1210 Flags = le32_to_cpu(np->tx_ring.orig[i].FlagLen);
1212 Flags = le32_to_cpu(np->tx_ring.ex[i].FlagLen);
1214 dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, Flags 0x%x.\n",
1215 dev->name, np->nic_tx, Flags);
1216 if (Flags & NV_TX_VALID)
1218 if (np->desc_ver == DESC_VER_1) {
1219 if (Flags & NV_TX_LASTPACKET) {
1220 skb = np->tx_skbuff[i];
1221 if (Flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION|
1222 NV_TX_UNDERFLOW|NV_TX_ERROR)) {
1223 if (Flags & NV_TX_UNDERFLOW)
1224 np->stats.tx_fifo_errors++;
1225 if (Flags & NV_TX_CARRIERLOST)
1226 np->stats.tx_carrier_errors++;
1227 np->stats.tx_errors++;
1229 np->stats.tx_packets++;
1230 np->stats.tx_bytes += skb->len;
1234 if (Flags & NV_TX2_LASTPACKET) {
1235 skb = np->tx_skbuff[i];
1236 if (Flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION|
1237 NV_TX2_UNDERFLOW|NV_TX2_ERROR)) {
1238 if (Flags & NV_TX2_UNDERFLOW)
1239 np->stats.tx_fifo_errors++;
1240 if (Flags & NV_TX2_CARRIERLOST)
1241 np->stats.tx_carrier_errors++;
1242 np->stats.tx_errors++;
1244 np->stats.tx_packets++;
1245 np->stats.tx_bytes += skb->len;
1249 nv_release_txskb(dev, i);
1252 if (np->next_tx - np->nic_tx < TX_LIMIT_START)
1253 netif_wake_queue(dev);
1257 * nv_tx_timeout: dev->tx_timeout function
1258 * Called with dev->xmit_lock held.
1260 static void nv_tx_timeout(struct net_device *dev)
1262 struct fe_priv *np = netdev_priv(dev);
1263 u8 __iomem *base = get_hwbase(dev);
1265 printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name,
1266 readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK);
1271 printk(KERN_INFO "%s: Ring at %lx: next %d nic %d\n",
1272 dev->name, (unsigned long)np->ring_addr,
1273 np->next_tx, np->nic_tx);
1274 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
1275 for (i=0;i<0x400;i+= 32) {
1276 printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1278 readl(base + i + 0), readl(base + i + 4),
1279 readl(base + i + 8), readl(base + i + 12),
1280 readl(base + i + 16), readl(base + i + 20),
1281 readl(base + i + 24), readl(base + i + 28));
1283 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
1284 for (i=0;i<TX_RING;i+= 4) {
1285 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1286 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
1288 le32_to_cpu(np->tx_ring.orig[i].PacketBuffer),
1289 le32_to_cpu(np->tx_ring.orig[i].FlagLen),
1290 le32_to_cpu(np->tx_ring.orig[i+1].PacketBuffer),
1291 le32_to_cpu(np->tx_ring.orig[i+1].FlagLen),
1292 le32_to_cpu(np->tx_ring.orig[i+2].PacketBuffer),
1293 le32_to_cpu(np->tx_ring.orig[i+2].FlagLen),
1294 le32_to_cpu(np->tx_ring.orig[i+3].PacketBuffer),
1295 le32_to_cpu(np->tx_ring.orig[i+3].FlagLen));
1297 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
1299 le32_to_cpu(np->tx_ring.ex[i].PacketBufferHigh),
1300 le32_to_cpu(np->tx_ring.ex[i].PacketBufferLow),
1301 le32_to_cpu(np->tx_ring.ex[i].FlagLen),
1302 le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferHigh),
1303 le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferLow),
1304 le32_to_cpu(np->tx_ring.ex[i+1].FlagLen),
1305 le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferHigh),
1306 le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferLow),
1307 le32_to_cpu(np->tx_ring.ex[i+2].FlagLen),
1308 le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferHigh),
1309 le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferLow),
1310 le32_to_cpu(np->tx_ring.ex[i+3].FlagLen));
1315 spin_lock_irq(&np->lock);
1317 /* 1) stop tx engine */
1320 /* 2) check that the packets were not sent already: */
1323 /* 3) if there are dead entries: clear everything */
1324 if (np->next_tx != np->nic_tx) {
1325 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
1327 np->next_tx = np->nic_tx = 0;
1328 setup_hw_rings(dev, NV_SETUP_TX_RING);
1329 netif_wake_queue(dev);
1332 /* 4) restart tx engine */
1334 spin_unlock_irq(&np->lock);
1338 * Called when the nic notices a mismatch between the actual data len on the
1339 * wire and the len indicated in the 802 header
1341 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
1343 int hdrlen; /* length of the 802 header */
1344 int protolen; /* length as stored in the proto field */
1346 /* 1) calculate len according to header */
1347 if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == __constant_htons(ETH_P_8021Q)) {
1348 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
1351 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
1354 dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
1355 dev->name, datalen, protolen, hdrlen);
1356 if (protolen > ETH_DATA_LEN)
1357 return datalen; /* Value in proto field not a len, no checks possible */
1360 /* consistency checks: */
1361 if (datalen > ETH_ZLEN) {
1362 if (datalen >= protolen) {
1363 /* more data on wire than in 802 header, trim of
1366 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1367 dev->name, protolen);
1370 /* less data on wire than mentioned in header.
1371 * Discard the packet.
1373 dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
1378 /* short packet. Accept only if 802 values are also short */
1379 if (protolen > ETH_ZLEN) {
1380 dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
1384 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1385 dev->name, datalen);
1390 static void nv_rx_process(struct net_device *dev)
1392 struct fe_priv *np = netdev_priv(dev);
1398 struct sk_buff *skb;
1401 if (np->cur_rx - np->refill_rx >= RX_RING)
1402 break; /* we scanned the whole ring - do not continue */
1404 i = np->cur_rx % RX_RING;
1405 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1406 Flags = le32_to_cpu(np->rx_ring.orig[i].FlagLen);
1407 len = nv_descr_getlength(&np->rx_ring.orig[i], np->desc_ver);
1409 Flags = le32_to_cpu(np->rx_ring.ex[i].FlagLen);
1410 len = nv_descr_getlength_ex(&np->rx_ring.ex[i], np->desc_ver);
1411 vlanflags = le32_to_cpu(np->rx_ring.ex[i].PacketBufferLow);
1414 dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, Flags 0x%x.\n",
1415 dev->name, np->cur_rx, Flags);
1417 if (Flags & NV_RX_AVAIL)
1418 break; /* still owned by hardware, */
1421 * the packet is for us - immediately tear down the pci mapping.
1422 * TODO: check if a prefetch of the first cacheline improves
1425 pci_unmap_single(np->pci_dev, np->rx_dma[i],
1426 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
1427 PCI_DMA_FROMDEVICE);
1431 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",Flags);
1432 for (j=0; j<64; j++) {
1434 dprintk("\n%03x:", j);
1435 dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]);
1439 /* look at what we actually got: */
1440 if (np->desc_ver == DESC_VER_1) {
1441 if (!(Flags & NV_RX_DESCRIPTORVALID))
1444 if (Flags & NV_RX_ERROR) {
1445 if (Flags & NV_RX_MISSEDFRAME) {
1446 np->stats.rx_missed_errors++;
1447 np->stats.rx_errors++;
1450 if (Flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) {
1451 np->stats.rx_errors++;
1454 if (Flags & NV_RX_CRCERR) {
1455 np->stats.rx_crc_errors++;
1456 np->stats.rx_errors++;
1459 if (Flags & NV_RX_OVERFLOW) {
1460 np->stats.rx_over_errors++;
1461 np->stats.rx_errors++;
1464 if (Flags & NV_RX_ERROR4) {
1465 len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1467 np->stats.rx_errors++;
1471 /* framing errors are soft errors. */
1472 if (Flags & NV_RX_FRAMINGERR) {
1473 if (Flags & NV_RX_SUBSTRACT1) {
1479 if (!(Flags & NV_RX2_DESCRIPTORVALID))
1482 if (Flags & NV_RX2_ERROR) {
1483 if (Flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) {
1484 np->stats.rx_errors++;
1487 if (Flags & NV_RX2_CRCERR) {
1488 np->stats.rx_crc_errors++;
1489 np->stats.rx_errors++;
1492 if (Flags & NV_RX2_OVERFLOW) {
1493 np->stats.rx_over_errors++;
1494 np->stats.rx_errors++;
1497 if (Flags & NV_RX2_ERROR4) {
1498 len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1500 np->stats.rx_errors++;
1504 /* framing errors are soft errors */
1505 if (Flags & NV_RX2_FRAMINGERR) {
1506 if (Flags & NV_RX2_SUBSTRACT1) {
1511 Flags &= NV_RX2_CHECKSUMMASK;
1512 if (Flags == NV_RX2_CHECKSUMOK1 ||
1513 Flags == NV_RX2_CHECKSUMOK2 ||
1514 Flags == NV_RX2_CHECKSUMOK3) {
1515 dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name);
1516 np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY;
1518 dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name);
1521 /* got a valid packet - forward it to the network core */
1522 skb = np->rx_skbuff[i];
1523 np->rx_skbuff[i] = NULL;
1526 skb->protocol = eth_type_trans(skb, dev);
1527 dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
1528 dev->name, np->cur_rx, len, skb->protocol);
1529 if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT)) {
1530 vlan_hwaccel_rx(skb, np->vlangrp, vlanflags & NV_RX3_VLAN_TAG_MASK);
1534 dev->last_rx = jiffies;
1535 np->stats.rx_packets++;
1536 np->stats.rx_bytes += len;
1542 static void set_bufsize(struct net_device *dev)
1544 struct fe_priv *np = netdev_priv(dev);
1546 if (dev->mtu <= ETH_DATA_LEN)
1547 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
1549 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
1553 * nv_change_mtu: dev->change_mtu function
1554 * Called with dev_base_lock held for read.
1556 static int nv_change_mtu(struct net_device *dev, int new_mtu)
1558 struct fe_priv *np = netdev_priv(dev);
1561 if (new_mtu < 64 || new_mtu > np->pkt_limit)
1567 /* return early if the buffer sizes will not change */
1568 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1570 if (old_mtu == new_mtu)
1573 /* synchronized against open : rtnl_lock() held by caller */
1574 if (netif_running(dev)) {
1575 u8 __iomem *base = get_hwbase(dev);
1577 * It seems that the nic preloads valid ring entries into an
1578 * internal buffer. The procedure for flushing everything is
1579 * guessed, there is probably a simpler approach.
1580 * Changing the MTU is a rare event, it shouldn't matter.
1582 disable_irq(dev->irq);
1583 spin_lock_bh(&dev->xmit_lock);
1584 spin_lock(&np->lock);
1589 /* drain rx queue */
1592 /* reinit driver view of the rx queue */
1595 /* alloc new rx buffers */
1597 if (nv_alloc_rx(dev)) {
1598 if (!np->in_shutdown)
1599 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1601 /* reinit nic view of the rx queue */
1602 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
1603 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
1604 writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),
1605 base + NvRegRingSizes);
1607 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1610 /* restart rx engine */
1613 spin_unlock(&np->lock);
1614 spin_unlock_bh(&dev->xmit_lock);
1615 enable_irq(dev->irq);
1620 static void nv_copy_mac_to_hw(struct net_device *dev)
1622 u8 __iomem *base = get_hwbase(dev);
1625 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
1626 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
1627 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
1629 writel(mac[0], base + NvRegMacAddrA);
1630 writel(mac[1], base + NvRegMacAddrB);
1634 * nv_set_mac_address: dev->set_mac_address function
1635 * Called with rtnl_lock() held.
1637 static int nv_set_mac_address(struct net_device *dev, void *addr)
1639 struct fe_priv *np = netdev_priv(dev);
1640 struct sockaddr *macaddr = (struct sockaddr*)addr;
1642 if(!is_valid_ether_addr(macaddr->sa_data))
1643 return -EADDRNOTAVAIL;
1645 /* synchronized against open : rtnl_lock() held by caller */
1646 memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
1648 if (netif_running(dev)) {
1649 spin_lock_bh(&dev->xmit_lock);
1650 spin_lock_irq(&np->lock);
1652 /* stop rx engine */
1655 /* set mac address */
1656 nv_copy_mac_to_hw(dev);
1658 /* restart rx engine */
1660 spin_unlock_irq(&np->lock);
1661 spin_unlock_bh(&dev->xmit_lock);
1663 nv_copy_mac_to_hw(dev);
1669 * nv_set_multicast: dev->set_multicast function
1670 * Called with dev->xmit_lock held.
1672 static void nv_set_multicast(struct net_device *dev)
1674 struct fe_priv *np = netdev_priv(dev);
1675 u8 __iomem *base = get_hwbase(dev);
1680 memset(addr, 0, sizeof(addr));
1681 memset(mask, 0, sizeof(mask));
1683 if (dev->flags & IFF_PROMISC) {
1684 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
1685 pff = NVREG_PFF_PROMISC;
1687 pff = NVREG_PFF_MYADDR;
1689 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
1693 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
1694 if (dev->flags & IFF_ALLMULTI) {
1695 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
1697 struct dev_mc_list *walk;
1699 walk = dev->mc_list;
1700 while (walk != NULL) {
1702 a = le32_to_cpu(*(u32 *) walk->dmi_addr);
1703 b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
1711 addr[0] = alwaysOn[0];
1712 addr[1] = alwaysOn[1];
1713 mask[0] = alwaysOn[0] | alwaysOff[0];
1714 mask[1] = alwaysOn[1] | alwaysOff[1];
1717 addr[0] |= NVREG_MCASTADDRA_FORCE;
1718 pff |= NVREG_PFF_ALWAYS;
1719 spin_lock_irq(&np->lock);
1721 writel(addr[0], base + NvRegMulticastAddrA);
1722 writel(addr[1], base + NvRegMulticastAddrB);
1723 writel(mask[0], base + NvRegMulticastMaskA);
1724 writel(mask[1], base + NvRegMulticastMaskB);
1725 writel(pff, base + NvRegPacketFilterFlags);
1726 dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
1729 spin_unlock_irq(&np->lock);
1733 * nv_update_linkspeed: Setup the MAC according to the link partner
1734 * @dev: Network device to be configured
1736 * The function queries the PHY and checks if there is a link partner.
1737 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
1738 * set to 10 MBit HD.
1740 * The function returns 0 if there is no link partner and 1 if there is
1741 * a good link partner.
1743 static int nv_update_linkspeed(struct net_device *dev)
1745 struct fe_priv *np = netdev_priv(dev);
1746 u8 __iomem *base = get_hwbase(dev);
1748 int newls = np->linkspeed;
1749 int newdup = np->duplex;
1752 u32 control_1000, status_1000, phyreg;
1754 /* BMSR_LSTATUS is latched, read it twice:
1755 * we want the current value.
1757 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1758 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1760 if (!(mii_status & BMSR_LSTATUS)) {
1761 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
1763 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1769 if (np->autoneg == 0) {
1770 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
1771 dev->name, np->fixed_mode);
1772 if (np->fixed_mode & LPA_100FULL) {
1773 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1775 } else if (np->fixed_mode & LPA_100HALF) {
1776 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1778 } else if (np->fixed_mode & LPA_10FULL) {
1779 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1782 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1788 /* check auto negotiation is complete */
1789 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
1790 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
1791 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1794 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
1799 if (np->gigabit == PHY_GIGABIT) {
1800 control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1801 status_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_SR, MII_READ);
1803 if ((control_1000 & ADVERTISE_1000FULL) &&
1804 (status_1000 & LPA_1000FULL)) {
1805 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
1807 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
1813 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1814 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
1815 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
1816 dev->name, adv, lpa);
1818 /* FIXME: handle parallel detection properly */
1820 if (lpa & LPA_100FULL) {
1821 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1823 } else if (lpa & LPA_100HALF) {
1824 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1826 } else if (lpa & LPA_10FULL) {
1827 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1829 } else if (lpa & LPA_10HALF) {
1830 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1833 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, lpa);
1834 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1839 if (np->duplex == newdup && np->linkspeed == newls)
1842 dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
1843 dev->name, np->linkspeed, np->duplex, newls, newdup);
1845 np->duplex = newdup;
1846 np->linkspeed = newls;
1848 if (np->gigabit == PHY_GIGABIT) {
1849 phyreg = readl(base + NvRegRandomSeed);
1850 phyreg &= ~(0x3FF00);
1851 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
1852 phyreg |= NVREG_RNDSEED_FORCE3;
1853 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
1854 phyreg |= NVREG_RNDSEED_FORCE2;
1855 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
1856 phyreg |= NVREG_RNDSEED_FORCE;
1857 writel(phyreg, base + NvRegRandomSeed);
1860 phyreg = readl(base + NvRegPhyInterface);
1861 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
1862 if (np->duplex == 0)
1864 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
1866 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
1868 writel(phyreg, base + NvRegPhyInterface);
1870 writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
1873 writel(np->linkspeed, base + NvRegLinkSpeed);
1879 static void nv_linkchange(struct net_device *dev)
1881 if (nv_update_linkspeed(dev)) {
1882 if (!netif_carrier_ok(dev)) {
1883 netif_carrier_on(dev);
1884 printk(KERN_INFO "%s: link up.\n", dev->name);
1888 if (netif_carrier_ok(dev)) {
1889 netif_carrier_off(dev);
1890 printk(KERN_INFO "%s: link down.\n", dev->name);
1896 static void nv_link_irq(struct net_device *dev)
1898 u8 __iomem *base = get_hwbase(dev);
1901 miistat = readl(base + NvRegMIIStatus);
1902 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1903 dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
1905 if (miistat & (NVREG_MIISTAT_LINKCHANGE))
1907 dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
1910 static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs)
1912 struct net_device *dev = (struct net_device *) data;
1913 struct fe_priv *np = netdev_priv(dev);
1914 u8 __iomem *base = get_hwbase(dev);
1918 dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
1921 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1922 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1924 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
1925 if (!(events & np->irqmask))
1928 spin_lock(&np->lock);
1930 spin_unlock(&np->lock);
1933 if (nv_alloc_rx(dev)) {
1934 spin_lock(&np->lock);
1935 if (!np->in_shutdown)
1936 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1937 spin_unlock(&np->lock);
1940 if (events & NVREG_IRQ_LINK) {
1941 spin_lock(&np->lock);
1943 spin_unlock(&np->lock);
1945 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
1946 spin_lock(&np->lock);
1948 spin_unlock(&np->lock);
1949 np->link_timeout = jiffies + LINK_TIMEOUT;
1951 if (events & (NVREG_IRQ_TX_ERR)) {
1952 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
1955 if (events & (NVREG_IRQ_UNKNOWN)) {
1956 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
1959 if (i > max_interrupt_work) {
1960 spin_lock(&np->lock);
1961 /* disable interrupts on the nic */
1962 writel(0, base + NvRegIrqMask);
1965 if (!np->in_shutdown)
1966 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
1967 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
1968 spin_unlock(&np->lock);
1973 dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
1975 return IRQ_RETVAL(i);
1978 static void nv_do_nic_poll(unsigned long data)
1980 struct net_device *dev = (struct net_device *) data;
1981 struct fe_priv *np = netdev_priv(dev);
1982 u8 __iomem *base = get_hwbase(dev);
1984 disable_irq(dev->irq);
1985 /* FIXME: Do we need synchronize_irq(dev->irq) here? */
1987 * reenable interrupts on the nic, we have to do this before calling
1988 * nv_nic_irq because that may decide to do otherwise
1990 writel(np->irqmask, base + NvRegIrqMask);
1992 nv_nic_irq((int) 0, (void *) data, (struct pt_regs *) NULL);
1993 enable_irq(dev->irq);
1996 #ifdef CONFIG_NET_POLL_CONTROLLER
1997 static void nv_poll_controller(struct net_device *dev)
1999 nv_do_nic_poll((unsigned long) dev);
2003 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2005 struct fe_priv *np = netdev_priv(dev);
2006 strcpy(info->driver, "forcedeth");
2007 strcpy(info->version, FORCEDETH_VERSION);
2008 strcpy(info->bus_info, pci_name(np->pci_dev));
2011 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
2013 struct fe_priv *np = netdev_priv(dev);
2014 wolinfo->supported = WAKE_MAGIC;
2016 spin_lock_irq(&np->lock);
2018 wolinfo->wolopts = WAKE_MAGIC;
2019 spin_unlock_irq(&np->lock);
2022 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
2024 struct fe_priv *np = netdev_priv(dev);
2025 u8 __iomem *base = get_hwbase(dev);
2027 spin_lock_irq(&np->lock);
2028 if (wolinfo->wolopts == 0) {
2029 writel(0, base + NvRegWakeUpFlags);
2032 if (wolinfo->wolopts & WAKE_MAGIC) {
2033 writel(NVREG_WAKEUPFLAGS_ENABLE, base + NvRegWakeUpFlags);
2036 spin_unlock_irq(&np->lock);
2040 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2042 struct fe_priv *np = netdev_priv(dev);
2045 spin_lock_irq(&np->lock);
2046 ecmd->port = PORT_MII;
2047 if (!netif_running(dev)) {
2048 /* We do not track link speed / duplex setting if the
2049 * interface is disabled. Force a link check */
2050 nv_update_linkspeed(dev);
2052 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
2053 case NVREG_LINKSPEED_10:
2054 ecmd->speed = SPEED_10;
2056 case NVREG_LINKSPEED_100:
2057 ecmd->speed = SPEED_100;
2059 case NVREG_LINKSPEED_1000:
2060 ecmd->speed = SPEED_1000;
2063 ecmd->duplex = DUPLEX_HALF;
2065 ecmd->duplex = DUPLEX_FULL;
2067 ecmd->autoneg = np->autoneg;
2069 ecmd->advertising = ADVERTISED_MII;
2071 ecmd->advertising |= ADVERTISED_Autoneg;
2072 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2074 adv = np->fixed_mode;
2076 if (adv & ADVERTISE_10HALF)
2077 ecmd->advertising |= ADVERTISED_10baseT_Half;
2078 if (adv & ADVERTISE_10FULL)
2079 ecmd->advertising |= ADVERTISED_10baseT_Full;
2080 if (adv & ADVERTISE_100HALF)
2081 ecmd->advertising |= ADVERTISED_100baseT_Half;
2082 if (adv & ADVERTISE_100FULL)
2083 ecmd->advertising |= ADVERTISED_100baseT_Full;
2084 if (np->autoneg && np->gigabit == PHY_GIGABIT) {
2085 adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
2086 if (adv & ADVERTISE_1000FULL)
2087 ecmd->advertising |= ADVERTISED_1000baseT_Full;
2090 ecmd->supported = (SUPPORTED_Autoneg |
2091 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2092 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2094 if (np->gigabit == PHY_GIGABIT)
2095 ecmd->supported |= SUPPORTED_1000baseT_Full;
2097 ecmd->phy_address = np->phyaddr;
2098 ecmd->transceiver = XCVR_EXTERNAL;
2100 /* ignore maxtxpkt, maxrxpkt for now */
2101 spin_unlock_irq(&np->lock);
2105 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2107 struct fe_priv *np = netdev_priv(dev);
2109 if (ecmd->port != PORT_MII)
2111 if (ecmd->transceiver != XCVR_EXTERNAL)
2113 if (ecmd->phy_address != np->phyaddr) {
2114 /* TODO: support switching between multiple phys. Should be
2115 * trivial, but not enabled due to lack of test hardware. */
2118 if (ecmd->autoneg == AUTONEG_ENABLE) {
2121 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2122 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
2123 if (np->gigabit == PHY_GIGABIT)
2124 mask |= ADVERTISED_1000baseT_Full;
2126 if ((ecmd->advertising & mask) == 0)
2129 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
2130 /* Note: autonegotiation disable, speed 1000 intentionally
2131 * forbidden - noone should need that. */
2133 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
2135 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
2141 spin_lock_irq(&np->lock);
2142 if (ecmd->autoneg == AUTONEG_ENABLE) {
2147 /* advertise only what has been requested */
2148 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2149 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
2150 if (ecmd->advertising & ADVERTISED_10baseT_Half)
2151 adv |= ADVERTISE_10HALF;
2152 if (ecmd->advertising & ADVERTISED_10baseT_Full)
2153 adv |= ADVERTISE_10FULL;
2154 if (ecmd->advertising & ADVERTISED_100baseT_Half)
2155 adv |= ADVERTISE_100HALF;
2156 if (ecmd->advertising & ADVERTISED_100baseT_Full)
2157 adv |= ADVERTISE_100FULL;
2158 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
2160 if (np->gigabit == PHY_GIGABIT) {
2161 adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
2162 adv &= ~ADVERTISE_1000FULL;
2163 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
2164 adv |= ADVERTISE_1000FULL;
2165 mii_rw(dev, np->phyaddr, MII_1000BT_CR, adv);
2168 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
2169 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
2170 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
2177 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2178 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
2179 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
2180 adv |= ADVERTISE_10HALF;
2181 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
2182 adv |= ADVERTISE_10FULL;
2183 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
2184 adv |= ADVERTISE_100HALF;
2185 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
2186 adv |= ADVERTISE_100FULL;
2187 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
2188 np->fixed_mode = adv;
2190 if (np->gigabit == PHY_GIGABIT) {
2191 adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
2192 adv &= ~ADVERTISE_1000FULL;
2193 mii_rw(dev, np->phyaddr, MII_1000BT_CR, adv);
2196 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
2197 bmcr |= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_FULLDPLX);
2198 if (adv & (ADVERTISE_10FULL|ADVERTISE_100FULL))
2199 bmcr |= BMCR_FULLDPLX;
2200 if (adv & (ADVERTISE_100HALF|ADVERTISE_100FULL))
2201 bmcr |= BMCR_SPEED100;
2202 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
2204 if (netif_running(dev)) {
2205 /* Wait a bit and then reconfigure the nic. */
2210 spin_unlock_irq(&np->lock);
2215 #define FORCEDETH_REGS_VER 1
2216 #define FORCEDETH_REGS_SIZE 0x400 /* 256 32-bit registers */
2218 static int nv_get_regs_len(struct net_device *dev)
2220 return FORCEDETH_REGS_SIZE;
2223 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
2225 struct fe_priv *np = netdev_priv(dev);
2226 u8 __iomem *base = get_hwbase(dev);
2230 regs->version = FORCEDETH_REGS_VER;
2231 spin_lock_irq(&np->lock);
2232 for (i=0;i<FORCEDETH_REGS_SIZE/sizeof(u32);i++)
2233 rbuf[i] = readl(base + i*sizeof(u32));
2234 spin_unlock_irq(&np->lock);
2237 static int nv_nway_reset(struct net_device *dev)
2239 struct fe_priv *np = netdev_priv(dev);
2242 spin_lock_irq(&np->lock);
2246 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
2247 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
2248 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
2254 spin_unlock_irq(&np->lock);
2259 static struct ethtool_ops ops = {
2260 .get_drvinfo = nv_get_drvinfo,
2261 .get_link = ethtool_op_get_link,
2262 .get_wol = nv_get_wol,
2263 .set_wol = nv_set_wol,
2264 .get_settings = nv_get_settings,
2265 .set_settings = nv_set_settings,
2266 .get_regs_len = nv_get_regs_len,
2267 .get_regs = nv_get_regs,
2268 .nway_reset = nv_nway_reset,
2269 .get_perm_addr = ethtool_op_get_perm_addr,
2272 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
2274 struct fe_priv *np = get_nvpriv(dev);
2276 spin_lock_irq(&np->lock);
2278 /* save vlan group */
2282 /* enable vlan on MAC */
2283 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
2285 /* disable vlan on MAC */
2286 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
2287 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
2290 writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2292 spin_unlock_irq(&np->lock);
2295 static void nv_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
2300 static int nv_open(struct net_device *dev)
2302 struct fe_priv *np = netdev_priv(dev);
2303 u8 __iomem *base = get_hwbase(dev);
2306 dprintk(KERN_DEBUG "nv_open: begin\n");
2308 /* 1) erase previous misconfiguration */
2309 /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */
2310 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
2311 writel(0, base + NvRegMulticastAddrB);
2312 writel(0, base + NvRegMulticastMaskA);
2313 writel(0, base + NvRegMulticastMaskB);
2314 writel(0, base + NvRegPacketFilterFlags);
2316 writel(0, base + NvRegTransmitterControl);
2317 writel(0, base + NvRegReceiverControl);
2319 writel(0, base + NvRegAdapterControl);
2321 /* 2) initialize descriptor rings */
2323 oom = nv_init_ring(dev);
2325 writel(0, base + NvRegLinkSpeed);
2326 writel(0, base + NvRegUnknownTransmitterReg);
2328 writel(0, base + NvRegUnknownSetupReg6);
2330 np->in_shutdown = 0;
2332 /* 3) set mac address */
2333 nv_copy_mac_to_hw(dev);
2335 /* 4) give hw rings */
2336 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2337 writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),
2338 base + NvRegRingSizes);
2340 /* 5) continue setup */
2341 writel(np->linkspeed, base + NvRegLinkSpeed);
2342 writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3);
2343 writel(np->txrxctl_bits, base + NvRegTxRxControl);
2344 writel(np->vlanctl_bits, base + NvRegVlanControl);
2346 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
2347 reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
2348 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
2349 KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
2351 writel(0, base + NvRegUnknownSetupReg4);
2352 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2353 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
2355 /* 6) continue setup */
2356 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
2357 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
2358 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
2359 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2361 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
2362 get_random_bytes(&i, sizeof(i));
2363 writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
2364 writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1);
2365 writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2);
2366 if (poll_interval == -1) {
2367 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
2368 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
2370 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
2373 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
2374 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
2375 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
2376 base + NvRegAdapterControl);
2377 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
2378 writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);
2379 writel(NVREG_WAKEUPFLAGS_VAL, base + NvRegWakeUpFlags);
2381 i = readl(base + NvRegPowerState);
2382 if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
2383 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
2387 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
2389 writel(0, base + NvRegIrqMask);
2391 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
2392 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2395 ret = request_irq(dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev);
2399 /* ask for interrupts */
2400 writel(np->irqmask, base + NvRegIrqMask);
2402 spin_lock_irq(&np->lock);
2403 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
2404 writel(0, base + NvRegMulticastAddrB);
2405 writel(0, base + NvRegMulticastMaskA);
2406 writel(0, base + NvRegMulticastMaskB);
2407 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
2408 /* One manual link speed update: Interrupts are enabled, future link
2409 * speed changes cause interrupts and are handled by nv_link_irq().
2413 miistat = readl(base + NvRegMIIStatus);
2414 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
2415 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
2417 /* set linkspeed to invalid value, thus force nv_update_linkspeed
2420 ret = nv_update_linkspeed(dev);
2423 netif_start_queue(dev);
2425 netif_carrier_on(dev);
2427 printk("%s: no link during initialization.\n", dev->name);
2428 netif_carrier_off(dev);
2431 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2432 spin_unlock_irq(&np->lock);
2440 static int nv_close(struct net_device *dev)
2442 struct fe_priv *np = netdev_priv(dev);
2445 spin_lock_irq(&np->lock);
2446 np->in_shutdown = 1;
2447 spin_unlock_irq(&np->lock);
2448 synchronize_irq(dev->irq);
2450 del_timer_sync(&np->oom_kick);
2451 del_timer_sync(&np->nic_poll);
2453 netif_stop_queue(dev);
2454 spin_lock_irq(&np->lock);
2459 /* disable interrupts on the nic or we will lock up */
2460 base = get_hwbase(dev);
2461 writel(0, base + NvRegIrqMask);
2463 dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
2465 spin_unlock_irq(&np->lock);
2467 free_irq(dev->irq, dev);
2474 /* special op: write back the misordered MAC address - otherwise
2475 * the next nv_probe would see a wrong address.
2477 writel(np->orig_mac[0], base + NvRegMacAddrA);
2478 writel(np->orig_mac[1], base + NvRegMacAddrB);
2480 /* FIXME: power down nic */
2485 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
2487 struct net_device *dev;
2493 dev = alloc_etherdev(sizeof(struct fe_priv));
2498 np = netdev_priv(dev);
2499 np->pci_dev = pci_dev;
2500 spin_lock_init(&np->lock);
2501 SET_MODULE_OWNER(dev);
2502 SET_NETDEV_DEV(dev, &pci_dev->dev);
2504 init_timer(&np->oom_kick);
2505 np->oom_kick.data = (unsigned long) dev;
2506 np->oom_kick.function = &nv_do_rx_refill; /* timer handler */
2507 init_timer(&np->nic_poll);
2508 np->nic_poll.data = (unsigned long) dev;
2509 np->nic_poll.function = &nv_do_nic_poll; /* timer handler */
2511 err = pci_enable_device(pci_dev);
2513 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
2514 err, pci_name(pci_dev));
2518 pci_set_master(pci_dev);
2520 err = pci_request_regions(pci_dev, DRV_NAME);
2526 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
2527 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
2528 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
2529 pci_resource_len(pci_dev, i),
2530 pci_resource_flags(pci_dev, i));
2531 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
2532 pci_resource_len(pci_dev, i) >= NV_PCI_REGSZ) {
2533 addr = pci_resource_start(pci_dev, i);
2537 if (i == DEVICE_COUNT_RESOURCE) {
2538 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
2543 /* handle different descriptor versions */
2544 if (id->driver_data & DEV_HAS_HIGH_DMA) {
2545 /* packet format 3: supports 40-bit addressing */
2546 np->desc_ver = DESC_VER_3;
2547 if (pci_set_dma_mask(pci_dev, 0x0000007fffffffffULL)) {
2548 printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
2551 if (pci_set_consistent_dma_mask(pci_dev, 0x0000007fffffffffULL)) {
2552 printk(KERN_INFO "forcedeth: 64-bit DMA (consistent) failed for device %s.\n",
2556 dev->features |= NETIF_F_HIGHDMA;
2557 printk(KERN_INFO "forcedeth: using HIGHDMA\n");
2560 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
2561 } else if (id->driver_data & DEV_HAS_LARGEDESC) {
2562 /* packet format 2: supports jumbo frames */
2563 np->desc_ver = DESC_VER_2;
2564 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
2566 /* original packet format */
2567 np->desc_ver = DESC_VER_1;
2568 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
2571 np->pkt_limit = NV_PKTLIMIT_1;
2572 if (id->driver_data & DEV_HAS_LARGEDESC)
2573 np->pkt_limit = NV_PKTLIMIT_2;
2575 if (id->driver_data & DEV_HAS_CHECKSUM) {
2576 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
2577 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
2579 dev->features |= NETIF_F_TSO;
2583 np->vlanctl_bits = 0;
2584 if (id->driver_data & DEV_HAS_VLAN) {
2585 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
2586 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
2587 dev->vlan_rx_register = nv_vlan_rx_register;
2588 dev->vlan_rx_kill_vid = nv_vlan_rx_kill_vid;
2592 np->base = ioremap(addr, NV_PCI_REGSZ);
2595 dev->base_addr = (unsigned long)np->base;
2597 dev->irq = pci_dev->irq;
2599 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
2600 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
2601 sizeof(struct ring_desc) * (RX_RING + TX_RING),
2603 if (!np->rx_ring.orig)
2605 np->tx_ring.orig = &np->rx_ring.orig[RX_RING];
2607 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
2608 sizeof(struct ring_desc_ex) * (RX_RING + TX_RING),
2610 if (!np->rx_ring.ex)
2612 np->tx_ring.ex = &np->rx_ring.ex[RX_RING];
2615 dev->open = nv_open;
2616 dev->stop = nv_close;
2617 dev->hard_start_xmit = nv_start_xmit;
2618 dev->get_stats = nv_get_stats;
2619 dev->change_mtu = nv_change_mtu;
2620 dev->set_mac_address = nv_set_mac_address;
2621 dev->set_multicast_list = nv_set_multicast;
2622 #ifdef CONFIG_NET_POLL_CONTROLLER
2623 dev->poll_controller = nv_poll_controller;
2625 SET_ETHTOOL_OPS(dev, &ops);
2626 dev->tx_timeout = nv_tx_timeout;
2627 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
2629 pci_set_drvdata(pci_dev, dev);
2631 /* read the mac address */
2632 base = get_hwbase(dev);
2633 np->orig_mac[0] = readl(base + NvRegMacAddrA);
2634 np->orig_mac[1] = readl(base + NvRegMacAddrB);
2636 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
2637 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
2638 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
2639 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
2640 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
2641 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
2642 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
2644 if (!is_valid_ether_addr(dev->perm_addr)) {
2646 * Bad mac address. At least one bios sets the mac address
2647 * to 01:23:45:67:89:ab
2649 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
2651 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2652 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2653 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
2654 dev->dev_addr[0] = 0x00;
2655 dev->dev_addr[1] = 0x00;
2656 dev->dev_addr[2] = 0x6c;
2657 get_random_bytes(&dev->dev_addr[3], 3);
2660 dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
2661 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2662 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2665 writel(0, base + NvRegWakeUpFlags);
2668 if (np->desc_ver == DESC_VER_1) {
2669 np->tx_flags = NV_TX_VALID;
2671 np->tx_flags = NV_TX2_VALID;
2673 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
2674 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
2676 np->irqmask = NVREG_IRQMASK_CPU;
2678 if (id->driver_data & DEV_NEED_TIMERIRQ)
2679 np->irqmask |= NVREG_IRQ_TIMER;
2680 if (id->driver_data & DEV_NEED_LINKTIMER) {
2681 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
2682 np->need_linktimer = 1;
2683 np->link_timeout = jiffies + LINK_TIMEOUT;
2685 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
2686 np->need_linktimer = 0;
2689 /* find a suitable phy */
2690 for (i = 1; i <= 32; i++) {
2692 int phyaddr = i & 0x1F;
2694 spin_lock_irq(&np->lock);
2695 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
2696 spin_unlock_irq(&np->lock);
2697 if (id1 < 0 || id1 == 0xffff)
2699 spin_lock_irq(&np->lock);
2700 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
2701 spin_unlock_irq(&np->lock);
2702 if (id2 < 0 || id2 == 0xffff)
2705 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
2706 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
2707 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
2708 pci_name(pci_dev), id1, id2, phyaddr);
2709 np->phyaddr = phyaddr;
2710 np->phy_oui = id1 | id2;
2714 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
2722 /* set default link speed settings */
2723 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2727 err = register_netdev(dev);
2729 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
2732 printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
2733 dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
2739 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2740 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING),
2741 np->rx_ring.orig, np->ring_addr);
2743 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (RX_RING + TX_RING),
2744 np->rx_ring.ex, np->ring_addr);
2745 pci_set_drvdata(pci_dev, NULL);
2747 iounmap(get_hwbase(dev));
2749 pci_release_regions(pci_dev);
2751 pci_disable_device(pci_dev);
2758 static void __devexit nv_remove(struct pci_dev *pci_dev)
2760 struct net_device *dev = pci_get_drvdata(pci_dev);
2761 struct fe_priv *np = netdev_priv(dev);
2763 unregister_netdev(dev);
2765 /* free all structures */
2766 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2767 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING), np->rx_ring.orig, np->ring_addr);
2769 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (RX_RING + TX_RING), np->rx_ring.ex, np->ring_addr);
2770 iounmap(get_hwbase(dev));
2771 pci_release_regions(pci_dev);
2772 pci_disable_device(pci_dev);
2774 pci_set_drvdata(pci_dev, NULL);
2777 static struct pci_device_id pci_tbl[] = {
2778 { /* nForce Ethernet Controller */
2779 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
2780 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2782 { /* nForce2 Ethernet Controller */
2783 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
2784 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2786 { /* nForce3 Ethernet Controller */
2787 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
2788 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2790 { /* nForce3 Ethernet Controller */
2791 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
2792 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
2794 { /* nForce3 Ethernet Controller */
2795 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
2796 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
2798 { /* nForce3 Ethernet Controller */
2799 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
2800 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
2802 { /* nForce3 Ethernet Controller */
2803 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
2804 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
2806 { /* CK804 Ethernet Controller */
2807 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
2808 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2810 { /* CK804 Ethernet Controller */
2811 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
2812 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2814 { /* MCP04 Ethernet Controller */
2815 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
2816 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2818 { /* MCP04 Ethernet Controller */
2819 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
2820 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2822 { /* MCP51 Ethernet Controller */
2823 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
2824 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA,
2826 { /* MCP51 Ethernet Controller */
2827 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
2828 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA,
2830 { /* MCP55 Ethernet Controller */
2831 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
2832 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN,
2834 { /* MCP55 Ethernet Controller */
2835 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
2836 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN,
2841 static struct pci_driver driver = {
2842 .name = "forcedeth",
2843 .id_table = pci_tbl,
2845 .remove = __devexit_p(nv_remove),
2849 static int __init init_nic(void)
2851 printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
2852 return pci_module_init(&driver);
2855 static void __exit exit_nic(void)
2857 pci_unregister_driver(&driver);
2860 module_param(max_interrupt_work, int, 0);
2861 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
2862 module_param(optimization_mode, int, 0);
2863 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
2864 module_param(poll_interval, int, 0);
2865 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
2867 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
2868 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
2869 MODULE_LICENSE("GPL");
2871 MODULE_DEVICE_TABLE(pci, pci_tbl);
2873 module_init(init_nic);
2874 module_exit(exit_nic);