drivers/net/forcedeth.c

   1 /*
   2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
   3  *
   4  * Note: This driver is a cleanroom reimplementation based on reverse
   5  *      engineered documentation written by Carl-Daniel Hailfinger
   6  *      and Andrew de Quincey.
   7  *
   8  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
   9  * trademarks of NVIDIA Corporation in the United States and other
  10  * countries.
  11  *
  12  * Copyright (C) 2003,4,5 Manfred Spraul
  13  * Copyright (C) 2004 Andrew de Quincey (wol support)
  14  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  15  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
  16  * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License as published by
  20  * the Free Software Foundation; either version 2 of the License, or
  21  * (at your option) any later version.
  22  *
  23  * This program is distributed in the hope that it will be useful,
  24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  26  * GNU General Public License for more details.
  27  *
  28  * You should have received a copy of the GNU General Public License
  29  * along with this program; if not, write to the Free Software
  30  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  31  *
  32  * Known bugs:
  33  * We suspect that on some hardware no TX done interrupts are generated.
  34  * This means recovery from netif_stop_queue only happens if the hw timer
  35  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
  36  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
  37  * If your hardware reliably generates tx done interrupts, then you can remove
  38  * DEV_NEED_TIMERIRQ from the driver_data flags.
  39  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
  40  * superfluous timer interrupts from the nic.
  41  */
  42 #define FORCEDETH_VERSION               "0.64"
  43 #define DRV_NAME                        "forcedeth"
  44
  45 #include <linux/module.h>
  46 #include <linux/types.h>
  47 #include <linux/pci.h>
  48 #include <linux/interrupt.h>
  49 #include <linux/netdevice.h>
  50 #include <linux/etherdevice.h>
  51 #include <linux/delay.h>
  52 #include <linux/sched.h>
  53 #include <linux/spinlock.h>
  54 #include <linux/ethtool.h>
  55 #include <linux/timer.h>
  56 #include <linux/skbuff.h>
  57 #include <linux/mii.h>
  58 #include <linux/random.h>
  59 #include <linux/init.h>
  60 #include <linux/if_vlan.h>
  61 #include <linux/dma-mapping.h>
  62 #include <linux/slab.h>
  63 #include <linux/uaccess.h>
  64 #include  <linux/io.h>
  65
  66 #include <asm/irq.h>
  67 #include <asm/system.h>
  68
  69 #if 0
  70 #define dprintk                 printk
  71 #else
  72 #define dprintk(x...)           do { } while (0)
  73 #endif
  74
  75 #define TX_WORK_PER_LOOP  64
  76 #define RX_WORK_PER_LOOP  64
  77
  78 /*
  79  * Hardware access:
  80  */
  81
  82 #define DEV_NEED_TIMERIRQ          0x0000001  /* set the timer irq flag in the irq mask */
  83 #define DEV_NEED_LINKTIMER         0x0000002  /* poll link settings. Relies on the timer irq */
  84 #define DEV_HAS_LARGEDESC          0x0000004  /* device supports jumbo frames and needs packet format 2 */
  85 #define DEV_HAS_HIGH_DMA           0x0000008  /* device supports 64bit dma */
  86 #define DEV_HAS_CHECKSUM           0x0000010  /* device supports tx and rx checksum offloads */
  87 #define DEV_HAS_VLAN               0x0000020  /* device supports vlan tagging and striping */
  88 #define DEV_HAS_MSI                0x0000040  /* device supports MSI */
  89 #define DEV_HAS_MSI_X              0x0000080  /* device supports MSI-X */
  90 #define DEV_HAS_POWER_CNTRL        0x0000100  /* device supports power savings */
  91 #define DEV_HAS_STATISTICS_V1      0x0000200  /* device supports hw statistics version 1 */
  92 #define DEV_HAS_STATISTICS_V2      0x0000400  /* device supports hw statistics version 2 */
  93 #define DEV_HAS_STATISTICS_V3      0x0000800  /* device supports hw statistics version 3 */
  94 #define DEV_HAS_STATISTICS_V12     0x0000600  /* device supports hw statistics version 1 and 2 */
  95 #define DEV_HAS_STATISTICS_V123    0x0000e00  /* device supports hw statistics version 1, 2, and 3 */
  96 #define DEV_HAS_TEST_EXTENDED      0x0001000  /* device supports extended diagnostic test */
  97 #define DEV_HAS_MGMT_UNIT          0x0002000  /* device supports management unit */
  98 #define DEV_HAS_CORRECT_MACADDR    0x0004000  /* device supports correct mac address order */
  99 #define DEV_HAS_COLLISION_FIX      0x0008000  /* device supports tx collision fix */
 100 #define DEV_HAS_PAUSEFRAME_TX_V1   0x0010000  /* device supports tx pause frames version 1 */
 101 #define DEV_HAS_PAUSEFRAME_TX_V2   0x0020000  /* device supports tx pause frames version 2 */
 102 #define DEV_HAS_PAUSEFRAME_TX_V3   0x0040000  /* device supports tx pause frames version 3 */
 103 #define DEV_NEED_TX_LIMIT          0x0080000  /* device needs to limit tx */
 104 #define DEV_NEED_TX_LIMIT2         0x0180000  /* device needs to limit tx, expect for some revs */
 105 #define DEV_HAS_GEAR_MODE          0x0200000  /* device supports gear mode */
 106 #define DEV_NEED_PHY_INIT_FIX      0x0400000  /* device needs specific phy workaround */
 107 #define DEV_NEED_LOW_POWER_FIX     0x0800000  /* device needs special power up workaround */
 108 #define DEV_NEED_MSI_FIX           0x1000000  /* device needs msi workaround */
 109
 110 enum {
 111         NvRegIrqStatus = 0x000,
 112 #define NVREG_IRQSTAT_MIIEVENT  0x040
 113 #define NVREG_IRQSTAT_MASK              0x83ff
 114         NvRegIrqMask = 0x004,
 115 #define NVREG_IRQ_RX_ERROR              0x0001
 116 #define NVREG_IRQ_RX                    0x0002
 117 #define NVREG_IRQ_RX_NOBUF              0x0004
 118 #define NVREG_IRQ_TX_ERR                0x0008
 119 #define NVREG_IRQ_TX_OK                 0x0010
 120 #define NVREG_IRQ_TIMER                 0x0020
 121 #define NVREG_IRQ_LINK                  0x0040
 122 #define NVREG_IRQ_RX_FORCED             0x0080
 123 #define NVREG_IRQ_TX_FORCED             0x0100
 124 #define NVREG_IRQ_RECOVER_ERROR         0x8200
 125 #define NVREG_IRQMASK_THROUGHPUT        0x00df
 126 #define NVREG_IRQMASK_CPU               0x0060
 127 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
 128 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
 129 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
 130
 131         NvRegUnknownSetupReg6 = 0x008,
 132 #define NVREG_UNKSETUP6_VAL             3
 133
 134 /*
 135  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
 136  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
 137  */
 138         NvRegPollingInterval = 0x00c,
 139 #define NVREG_POLL_DEFAULT_THROUGHPUT   65535 /* backup tx cleanup if loop max reached */
 140 #define NVREG_POLL_DEFAULT_CPU  13
 141         NvRegMSIMap0 = 0x020,
 142         NvRegMSIMap1 = 0x024,
 143         NvRegMSIIrqMask = 0x030,
 144 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
 145         NvRegMisc1 = 0x080,
 146 #define NVREG_MISC1_PAUSE_TX    0x01
 147 #define NVREG_MISC1_HD          0x02
 148 #define NVREG_MISC1_FORCE       0x3b0f3c
 149
 150         NvRegMacReset = 0x34,
 151 #define NVREG_MAC_RESET_ASSERT  0x0F3
 152         NvRegTransmitterControl = 0x084,
 153 #define NVREG_XMITCTL_START     0x01
 154 #define NVREG_XMITCTL_MGMT_ST   0x40000000
 155 #define NVREG_XMITCTL_SYNC_MASK         0x000f0000
 156 #define NVREG_XMITCTL_SYNC_NOT_READY    0x0
 157 #define NVREG_XMITCTL_SYNC_PHY_INIT     0x00040000
 158 #define NVREG_XMITCTL_MGMT_SEMA_MASK    0x00000f00
 159 #define NVREG_XMITCTL_MGMT_SEMA_FREE    0x0
 160 #define NVREG_XMITCTL_HOST_SEMA_MASK    0x0000f000
 161 #define NVREG_XMITCTL_HOST_SEMA_ACQ     0x0000f000
 162 #define NVREG_XMITCTL_HOST_LOADED       0x00004000
 163 #define NVREG_XMITCTL_TX_PATH_EN        0x01000000
 164 #define NVREG_XMITCTL_DATA_START        0x00100000
 165 #define NVREG_XMITCTL_DATA_READY        0x00010000
 166 #define NVREG_XMITCTL_DATA_ERROR        0x00020000
 167         NvRegTransmitterStatus = 0x088,
 168 #define NVREG_XMITSTAT_BUSY     0x01
 169
 170         NvRegPacketFilterFlags = 0x8c,
 171 #define NVREG_PFF_PAUSE_RX      0x08
 172 #define NVREG_PFF_ALWAYS        0x7F0000
 173 #define NVREG_PFF_PROMISC       0x80
 174 #define NVREG_PFF_MYADDR        0x20
 175 #define NVREG_PFF_LOOPBACK      0x10
 176
 177         NvRegOffloadConfig = 0x90,
 178 #define NVREG_OFFLOAD_HOMEPHY   0x601
 179 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
 180         NvRegReceiverControl = 0x094,
 181 #define NVREG_RCVCTL_START      0x01
 182 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
 183         NvRegReceiverStatus = 0x98,
 184 #define NVREG_RCVSTAT_BUSY      0x01
 185
 186         NvRegSlotTime = 0x9c,
 187 #define NVREG_SLOTTIME_LEGBF_ENABLED    0x80000000
 188 #define NVREG_SLOTTIME_10_100_FULL      0x00007f00
 189 #define NVREG_SLOTTIME_1000_FULL        0x0003ff00
 190 #define NVREG_SLOTTIME_HALF             0x0000ff00
 191 #define NVREG_SLOTTIME_DEFAULT          0x00007f00
 192 #define NVREG_SLOTTIME_MASK             0x000000ff
 193
 194         NvRegTxDeferral = 0xA0,
 195 #define NVREG_TX_DEFERRAL_DEFAULT               0x15050f
 196 #define NVREG_TX_DEFERRAL_RGMII_10_100          0x16070f
 197 #define NVREG_TX_DEFERRAL_RGMII_1000            0x14050f
 198 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10      0x16190f
 199 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100     0x16300f
 200 #define NVREG_TX_DEFERRAL_MII_STRETCH           0x152000
 201         NvRegRxDeferral = 0xA4,
 202 #define NVREG_RX_DEFERRAL_DEFAULT       0x16
 203         NvRegMacAddrA = 0xA8,
 204         NvRegMacAddrB = 0xAC,
 205         NvRegMulticastAddrA = 0xB0,
 206 #define NVREG_MCASTADDRA_FORCE  0x01
 207         NvRegMulticastAddrB = 0xB4,
 208         NvRegMulticastMaskA = 0xB8,
 209 #define NVREG_MCASTMASKA_NONE           0xffffffff
 210         NvRegMulticastMaskB = 0xBC,
 211 #define NVREG_MCASTMASKB_NONE           0xffff
 212
 213         NvRegPhyInterface = 0xC0,
 214 #define PHY_RGMII               0x10000000
 215         NvRegBackOffControl = 0xC4,
 216 #define NVREG_BKOFFCTRL_DEFAULT                 0x70000000
 217 #define NVREG_BKOFFCTRL_SEED_MASK               0x000003ff
 218 #define NVREG_BKOFFCTRL_SELECT                  24
 219 #define NVREG_BKOFFCTRL_GEAR                    12
 220
 221         NvRegTxRingPhysAddr = 0x100,
 222         NvRegRxRingPhysAddr = 0x104,
 223         NvRegRingSizes = 0x108,
 224 #define NVREG_RINGSZ_TXSHIFT 0
 225 #define NVREG_RINGSZ_RXSHIFT 16
 226         NvRegTransmitPoll = 0x10c,
 227 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
 228         NvRegLinkSpeed = 0x110,
 229 #define NVREG_LINKSPEED_FORCE 0x10000
 230 #define NVREG_LINKSPEED_10      1000
 231 #define NVREG_LINKSPEED_100     100
 232 #define NVREG_LINKSPEED_1000    50
 233 #define NVREG_LINKSPEED_MASK    (0xFFF)
 234         NvRegUnknownSetupReg5 = 0x130,
 235 #define NVREG_UNKSETUP5_BIT31   (1<<31)
 236         NvRegTxWatermark = 0x13c,
 237 #define NVREG_TX_WM_DESC1_DEFAULT       0x0200010
 238 #define NVREG_TX_WM_DESC2_3_DEFAULT     0x1e08000
 239 #define NVREG_TX_WM_DESC2_3_1000        0xfe08000
 240         NvRegTxRxControl = 0x144,
 241 #define NVREG_TXRXCTL_KICK      0x0001
 242 #define NVREG_TXRXCTL_BIT1      0x0002
 243 #define NVREG_TXRXCTL_BIT2      0x0004
 244 #define NVREG_TXRXCTL_IDLE      0x0008
 245 #define NVREG_TXRXCTL_RESET     0x0010
 246 #define NVREG_TXRXCTL_RXCHECK   0x0400
 247 #define NVREG_TXRXCTL_DESC_1    0
 248 #define NVREG_TXRXCTL_DESC_2    0x002100
 249 #define NVREG_TXRXCTL_DESC_3    0xc02200
 250 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
 251 #define NVREG_TXRXCTL_VLANINS   0x00080
 252         NvRegTxRingPhysAddrHigh = 0x148,
 253         NvRegRxRingPhysAddrHigh = 0x14C,
 254         NvRegTxPauseFrame = 0x170,
 255 #define NVREG_TX_PAUSEFRAME_DISABLE     0x0fff0080
 256 #define NVREG_TX_PAUSEFRAME_ENABLE_V1   0x01800010
 257 #define NVREG_TX_PAUSEFRAME_ENABLE_V2   0x056003f0
 258 #define NVREG_TX_PAUSEFRAME_ENABLE_V3   0x09f00880
 259         NvRegTxPauseFrameLimit = 0x174,
 260 #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
 261         NvRegMIIStatus = 0x180,
 262 #define NVREG_MIISTAT_ERROR             0x0001
 263 #define NVREG_MIISTAT_LINKCHANGE        0x0008
 264 #define NVREG_MIISTAT_MASK_RW           0x0007
 265 #define NVREG_MIISTAT_MASK_ALL          0x000f
 266         NvRegMIIMask = 0x184,
 267 #define NVREG_MII_LINKCHANGE            0x0008
 268
 269         NvRegAdapterControl = 0x188,
 270 #define NVREG_ADAPTCTL_START    0x02
 271 #define NVREG_ADAPTCTL_LINKUP   0x04
 272 #define NVREG_ADAPTCTL_PHYVALID 0x40000
 273 #define NVREG_ADAPTCTL_RUNNING  0x100000
 274 #define NVREG_ADAPTCTL_PHYSHIFT 24
 275         NvRegMIISpeed = 0x18c,
 276 #define NVREG_MIISPEED_BIT8     (1<<8)
 277 #define NVREG_MIIDELAY  5
 278         NvRegMIIControl = 0x190,
 279 #define NVREG_MIICTL_INUSE      0x08000
 280 #define NVREG_MIICTL_WRITE      0x00400
 281 #define NVREG_MIICTL_ADDRSHIFT  5
 282         NvRegMIIData = 0x194,
 283         NvRegTxUnicast = 0x1a0,
 284         NvRegTxMulticast = 0x1a4,
 285         NvRegTxBroadcast = 0x1a8,
 286         NvRegWakeUpFlags = 0x200,
 287 #define NVREG_WAKEUPFLAGS_VAL           0x7770
 288 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
 289 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
 290 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
 291 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
 292 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
 293 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
 294 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
 295 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
 296 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
 297 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
 298
 299         NvRegMgmtUnitGetVersion = 0x204,
 300 #define NVREG_MGMTUNITGETVERSION        0x01
 301         NvRegMgmtUnitVersion = 0x208,
 302 #define NVREG_MGMTUNITVERSION           0x08
 303         NvRegPowerCap = 0x268,
 304 #define NVREG_POWERCAP_D3SUPP   (1<<30)
 305 #define NVREG_POWERCAP_D2SUPP   (1<<26)
 306 #define NVREG_POWERCAP_D1SUPP   (1<<25)
 307         NvRegPowerState = 0x26c,
 308 #define NVREG_POWERSTATE_POWEREDUP      0x8000
 309 #define NVREG_POWERSTATE_VALID          0x0100
 310 #define NVREG_POWERSTATE_MASK           0x0003
 311 #define NVREG_POWERSTATE_D0             0x0000
 312 #define NVREG_POWERSTATE_D1             0x0001
 313 #define NVREG_POWERSTATE_D2             0x0002
 314 #define NVREG_POWERSTATE_D3             0x0003
 315         NvRegMgmtUnitControl = 0x278,
 316 #define NVREG_MGMTUNITCONTROL_INUSE     0x20000
 317         NvRegTxCnt = 0x280,
 318         NvRegTxZeroReXmt = 0x284,
 319         NvRegTxOneReXmt = 0x288,
 320         NvRegTxManyReXmt = 0x28c,
 321         NvRegTxLateCol = 0x290,
 322         NvRegTxUnderflow = 0x294,
 323         NvRegTxLossCarrier = 0x298,
 324         NvRegTxExcessDef = 0x29c,
 325         NvRegTxRetryErr = 0x2a0,
 326         NvRegRxFrameErr = 0x2a4,
 327         NvRegRxExtraByte = 0x2a8,
 328         NvRegRxLateCol = 0x2ac,
 329         NvRegRxRunt = 0x2b0,
 330         NvRegRxFrameTooLong = 0x2b4,
 331         NvRegRxOverflow = 0x2b8,
 332         NvRegRxFCSErr = 0x2bc,
 333         NvRegRxFrameAlignErr = 0x2c0,
 334         NvRegRxLenErr = 0x2c4,
 335         NvRegRxUnicast = 0x2c8,
 336         NvRegRxMulticast = 0x2cc,
 337         NvRegRxBroadcast = 0x2d0,
 338         NvRegTxDef = 0x2d4,
 339         NvRegTxFrame = 0x2d8,
 340         NvRegRxCnt = 0x2dc,
 341         NvRegTxPause = 0x2e0,
 342         NvRegRxPause = 0x2e4,
 343         NvRegRxDropFrame = 0x2e8,
 344         NvRegVlanControl = 0x300,
 345 #define NVREG_VLANCONTROL_ENABLE        0x2000
 346         NvRegMSIXMap0 = 0x3e0,
 347         NvRegMSIXMap1 = 0x3e4,
 348         NvRegMSIXIrqStatus = 0x3f0,
 349
 350         NvRegPowerState2 = 0x600,
 351 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F15
 352 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
 353 #define NVREG_POWERSTATE2_PHY_RESET             0x0004
 354 #define NVREG_POWERSTATE2_GATE_CLOCKS           0x0F00
 355 };
 356
 357 /* Big endian: should work, but is untested */
 358 struct ring_desc {
 359         __le32 buf;
 360         __le32 flaglen;
 361 };
 362
 363 struct ring_desc_ex {
 364         __le32 bufhigh;
 365         __le32 buflow;
 366         __le32 txvlan;
 367         __le32 flaglen;
 368 };
 369
 370 union ring_type {
 371         struct ring_desc *orig;
 372         struct ring_desc_ex *ex;
 373 };
 374
 375 #define FLAG_MASK_V1 0xffff0000
 376 #define FLAG_MASK_V2 0xffffc000
 377 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
 378 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
 379
 380 #define NV_TX_LASTPACKET        (1<<16)
 381 #define NV_TX_RETRYERROR        (1<<19)
 382 #define NV_TX_RETRYCOUNT_MASK   (0xF<<20)
 383 #define NV_TX_FORCED_INTERRUPT  (1<<24)
 384 #define NV_TX_DEFERRED          (1<<26)
 385 #define NV_TX_CARRIERLOST       (1<<27)
 386 #define NV_TX_LATECOLLISION     (1<<28)
 387 #define NV_TX_UNDERFLOW         (1<<29)
 388 #define NV_TX_ERROR             (1<<30)
 389 #define NV_TX_VALID             (1<<31)
 390
 391 #define NV_TX2_LASTPACKET       (1<<29)
 392 #define NV_TX2_RETRYERROR       (1<<18)
 393 #define NV_TX2_RETRYCOUNT_MASK  (0xF<<19)
 394 #define NV_TX2_FORCED_INTERRUPT (1<<30)
 395 #define NV_TX2_DEFERRED         (1<<25)
 396 #define NV_TX2_CARRIERLOST      (1<<26)
 397 #define NV_TX2_LATECOLLISION    (1<<27)
 398 #define NV_TX2_UNDERFLOW        (1<<28)
 399 /* error and valid are the same for both */
 400 #define NV_TX2_ERROR            (1<<30)
 401 #define NV_TX2_VALID            (1<<31)
 402 #define NV_TX2_TSO              (1<<28)
 403 #define NV_TX2_TSO_SHIFT        14
 404 #define NV_TX2_TSO_MAX_SHIFT    14
 405 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
 406 #define NV_TX2_CHECKSUM_L3      (1<<27)
 407 #define NV_TX2_CHECKSUM_L4      (1<<26)
 408
 409 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
 410
 411 #define NV_RX_DESCRIPTORVALID   (1<<16)
 412 #define NV_RX_MISSEDFRAME       (1<<17)
 413 #define NV_RX_SUBSTRACT1        (1<<18)
 414 #define NV_RX_ERROR1            (1<<23)
 415 #define NV_RX_ERROR2            (1<<24)
 416 #define NV_RX_ERROR3            (1<<25)
 417 #define NV_RX_ERROR4            (1<<26)
 418 #define NV_RX_CRCERR            (1<<27)
 419 #define NV_RX_OVERFLOW          (1<<28)
 420 #define NV_RX_FRAMINGERR        (1<<29)
 421 #define NV_RX_ERROR             (1<<30)
 422 #define NV_RX_AVAIL             (1<<31)
 423 #define NV_RX_ERROR_MASK        (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
 424
 425 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
 426 #define NV_RX2_CHECKSUM_IP      (0x10000000)
 427 #define NV_RX2_CHECKSUM_IP_TCP  (0x14000000)
 428 #define NV_RX2_CHECKSUM_IP_UDP  (0x18000000)
 429 #define NV_RX2_DESCRIPTORVALID  (1<<29)
 430 #define NV_RX2_SUBSTRACT1       (1<<25)
 431 #define NV_RX2_ERROR1           (1<<18)
 432 #define NV_RX2_ERROR2           (1<<19)
 433 #define NV_RX2_ERROR3           (1<<20)
 434 #define NV_RX2_ERROR4           (1<<21)
 435 #define NV_RX2_CRCERR           (1<<22)
 436 #define NV_RX2_OVERFLOW         (1<<23)
 437 #define NV_RX2_FRAMINGERR       (1<<24)
 438 /* error and avail are the same for both */
 439 #define NV_RX2_ERROR            (1<<30)
 440 #define NV_RX2_AVAIL            (1<<31)
 441 #define NV_RX2_ERROR_MASK       (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
 442
 443 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
 444 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
 445
 446 /* Miscelaneous hardware related defines: */
 447 #define NV_PCI_REGSZ_VER1       0x270
 448 #define NV_PCI_REGSZ_VER2       0x2d4
 449 #define NV_PCI_REGSZ_VER3       0x604
 450 #define NV_PCI_REGSZ_MAX        0x604
 451
 452 /* various timeout delays: all in usec */
 453 #define NV_TXRX_RESET_DELAY     4
 454 #define NV_TXSTOP_DELAY1        10
 455 #define NV_TXSTOP_DELAY1MAX     500000
 456 #define NV_TXSTOP_DELAY2        100
 457 #define NV_RXSTOP_DELAY1        10
 458 #define NV_RXSTOP_DELAY1MAX     500000
 459 #define NV_RXSTOP_DELAY2        100
 460 #define NV_SETUP5_DELAY         5
 461 #define NV_SETUP5_DELAYMAX      50000
 462 #define NV_POWERUP_DELAY        5
 463 #define NV_POWERUP_DELAYMAX     5000
 464 #define NV_MIIBUSY_DELAY        50
 465 #define NV_MIIPHY_DELAY 10
 466 #define NV_MIIPHY_DELAYMAX      10000
 467 #define NV_MAC_RESET_DELAY      64
 468
 469 #define NV_WAKEUPPATTERNS       5
 470 #define NV_WAKEUPMASKENTRIES    4
 471
 472 /* General driver defaults */
 473 #define NV_WATCHDOG_TIMEO       (5*HZ)
 474
 475 #define RX_RING_DEFAULT         512
 476 #define TX_RING_DEFAULT         256
 477 #define RX_RING_MIN             128
 478 #define TX_RING_MIN             64
 479 #define RING_MAX_DESC_VER_1     1024
 480 #define RING_MAX_DESC_VER_2_3   16384
 481
 482 /* rx/tx mac addr + type + vlan + align + slack*/
 483 #define NV_RX_HEADERS           (64)
 484 /* even more slack. */
 485 #define NV_RX_ALLOC_PAD         (64)
 486
 487 /* maximum mtu size */
 488 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
 489 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
 490
 491 #define OOM_REFILL      (1+HZ/20)
 492 #define POLL_WAIT       (1+HZ/100)
 493 #define LINK_TIMEOUT    (3*HZ)
 494 #define STATS_INTERVAL  (10*HZ)
 495
 496 /*
 497  * desc_ver values:
 498  * The nic supports three different descriptor types:
 499  * - DESC_VER_1: Original
 500  * - DESC_VER_2: support for jumbo frames.
 501  * - DESC_VER_3: 64-bit format.
 502  */
 503 #define DESC_VER_1      1
 504 #define DESC_VER_2      2
 505 #define DESC_VER_3      3
 506
 507 /* PHY defines */
 508 #define PHY_OUI_MARVELL         0x5043
 509 #define PHY_OUI_CICADA          0x03f1
 510 #define PHY_OUI_VITESSE         0x01c1
 511 #define PHY_OUI_REALTEK         0x0732
 512 #define PHY_OUI_REALTEK2        0x0020
 513 #define PHYID1_OUI_MASK 0x03ff
 514 #define PHYID1_OUI_SHFT 6
 515 #define PHYID2_OUI_MASK 0xfc00
 516 #define PHYID2_OUI_SHFT 10
 517 #define PHYID2_MODEL_MASK               0x03f0
 518 #define PHY_MODEL_REALTEK_8211          0x0110
 519 #define PHY_REV_MASK                    0x0001
 520 #define PHY_REV_REALTEK_8211B           0x0000
 521 #define PHY_REV_REALTEK_8211C           0x0001
 522 #define PHY_MODEL_REALTEK_8201          0x0200
 523 #define PHY_MODEL_MARVELL_E3016         0x0220
 524 #define PHY_MARVELL_E3016_INITMASK      0x0300
 525 #define PHY_CICADA_INIT1        0x0f000
 526 #define PHY_CICADA_INIT2        0x0e00
 527 #define PHY_CICADA_INIT3        0x01000
 528 #define PHY_CICADA_INIT4        0x0200
 529 #define PHY_CICADA_INIT5        0x0004
 530 #define PHY_CICADA_INIT6        0x02000
 531 #define PHY_VITESSE_INIT_REG1   0x1f
 532 #define PHY_VITESSE_INIT_REG2   0x10
 533 #define PHY_VITESSE_INIT_REG3   0x11
 534 #define PHY_VITESSE_INIT_REG4   0x12
 535 #define PHY_VITESSE_INIT_MSK1   0xc
 536 #define PHY_VITESSE_INIT_MSK2   0x0180
 537 #define PHY_VITESSE_INIT1       0x52b5
 538 #define PHY_VITESSE_INIT2       0xaf8a
 539 #define PHY_VITESSE_INIT3       0x8
 540 #define PHY_VITESSE_INIT4       0x8f8a
 541 #define PHY_VITESSE_INIT5       0xaf86
 542 #define PHY_VITESSE_INIT6       0x8f86
 543 #define PHY_VITESSE_INIT7       0xaf82
 544 #define PHY_VITESSE_INIT8       0x0100
 545 #define PHY_VITESSE_INIT9       0x8f82
 546 #define PHY_VITESSE_INIT10      0x0
 547 #define PHY_REALTEK_INIT_REG1   0x1f
 548 #define PHY_REALTEK_INIT_REG2   0x19
 549 #define PHY_REALTEK_INIT_REG3   0x13
 550 #define PHY_REALTEK_INIT_REG4   0x14
 551 #define PHY_REALTEK_INIT_REG5   0x18
 552 #define PHY_REALTEK_INIT_REG6   0x11
 553 #define PHY_REALTEK_INIT_REG7   0x01
 554 #define PHY_REALTEK_INIT1       0x0000
 555 #define PHY_REALTEK_INIT2       0x8e00
 556 #define PHY_REALTEK_INIT3       0x0001
 557 #define PHY_REALTEK_INIT4       0xad17
 558 #define PHY_REALTEK_INIT5       0xfb54
 559 #define PHY_REALTEK_INIT6       0xf5c7
 560 #define PHY_REALTEK_INIT7       0x1000
 561 #define PHY_REALTEK_INIT8       0x0003
 562 #define PHY_REALTEK_INIT9       0x0008
 563 #define PHY_REALTEK_INIT10      0x0005
 564 #define PHY_REALTEK_INIT11      0x0200
 565 #define PHY_REALTEK_INIT_MSK1   0x0003
 566
 567 #define PHY_GIGABIT     0x0100
 568
 569 #define PHY_TIMEOUT     0x1
 570 #define PHY_ERROR       0x2
 571
 572 #define PHY_100 0x1
 573 #define PHY_1000        0x2
 574 #define PHY_HALF        0x100
 575
 576 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
 577 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
 578 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
 579 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
 580 #define NV_PAUSEFRAME_RX_REQ     0x0010
 581 #define NV_PAUSEFRAME_TX_REQ     0x0020
 582 #define NV_PAUSEFRAME_AUTONEG    0x0040
 583
 584 /* MSI/MSI-X defines */
 585 #define NV_MSI_X_MAX_VECTORS  8
 586 #define NV_MSI_X_VECTORS_MASK 0x000f
 587 #define NV_MSI_CAPABLE        0x0010
 588 #define NV_MSI_X_CAPABLE      0x0020
 589 #define NV_MSI_ENABLED        0x0040
 590 #define NV_MSI_X_ENABLED      0x0080
 591
 592 #define NV_MSI_X_VECTOR_ALL   0x0
 593 #define NV_MSI_X_VECTOR_RX    0x0
 594 #define NV_MSI_X_VECTOR_TX    0x1
 595 #define NV_MSI_X_VECTOR_OTHER 0x2
 596
 597 #define NV_MSI_PRIV_OFFSET 0x68
 598 #define NV_MSI_PRIV_VALUE  0xffffffff
 599
 600 #define NV_RESTART_TX         0x1
 601 #define NV_RESTART_RX         0x2
 602
 603 #define NV_TX_LIMIT_COUNT     16
 604
 605 #define NV_DYNAMIC_THRESHOLD        4
 606 #define NV_DYNAMIC_MAX_QUIET_COUNT  2048
 607
 608 /* statistics */
 609 struct nv_ethtool_str {
 610         char name[ETH_GSTRING_LEN];
 611 };
 612
 613 static const struct nv_ethtool_str nv_estats_str[] = {
 614         { "tx_bytes" },
 615         { "tx_zero_rexmt" },
 616         { "tx_one_rexmt" },
 617         { "tx_many_rexmt" },
 618         { "tx_late_collision" },
 619         { "tx_fifo_errors" },
 620         { "tx_carrier_errors" },
 621         { "tx_excess_deferral" },
 622         { "tx_retry_error" },
 623         { "rx_frame_error" },
 624         { "rx_extra_byte" },
 625         { "rx_late_collision" },
 626         { "rx_runt" },
 627         { "rx_frame_too_long" },
 628         { "rx_over_errors" },
 629         { "rx_crc_errors" },
 630         { "rx_frame_align_error" },
 631         { "rx_length_error" },
 632         { "rx_unicast" },
 633         { "rx_multicast" },
 634         { "rx_broadcast" },
 635         { "rx_packets" },
 636         { "rx_errors_total" },
 637         { "tx_errors_total" },
 638
 639         /* version 2 stats */
 640         { "tx_deferral" },
 641         { "tx_packets" },
 642         { "rx_bytes" },
 643         { "tx_pause" },
 644         { "rx_pause" },
 645         { "rx_drop_frame" },
 646
 647         /* version 3 stats */
 648         { "tx_unicast" },
 649         { "tx_multicast" },
 650         { "tx_broadcast" }
 651 };
 652
 653 struct nv_ethtool_stats {
 654         u64 tx_bytes;
 655         u64 tx_zero_rexmt;
 656         u64 tx_one_rexmt;
 657         u64 tx_many_rexmt;
 658         u64 tx_late_collision;
 659         u64 tx_fifo_errors;
 660         u64 tx_carrier_errors;
 661         u64 tx_excess_deferral;
 662         u64 tx_retry_error;
 663         u64 rx_frame_error;
 664         u64 rx_extra_byte;
 665         u64 rx_late_collision;
 666         u64 rx_runt;
 667         u64 rx_frame_too_long;
 668         u64 rx_over_errors;
 669         u64 rx_crc_errors;
 670         u64 rx_frame_align_error;
 671         u64 rx_length_error;
 672         u64 rx_unicast;
 673         u64 rx_multicast;
 674         u64 rx_broadcast;
 675         u64 rx_packets;
 676         u64 rx_errors_total;
 677         u64 tx_errors_total;
 678
 679         /* version 2 stats */
 680         u64 tx_deferral;
 681         u64 tx_packets;
 682         u64 rx_bytes;
 683         u64 tx_pause;
 684         u64 rx_pause;
 685         u64 rx_drop_frame;
 686
 687         /* version 3 stats */
 688         u64 tx_unicast;
 689         u64 tx_multicast;
 690         u64 tx_broadcast;
 691 };
 692
 693 #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
 694 #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
 695 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
 696
 697 /* diagnostics */
 698 #define NV_TEST_COUNT_BASE 3
 699 #define NV_TEST_COUNT_EXTENDED 4
 700
 701 static const struct nv_ethtool_str nv_etests_str[] = {
 702         { "link      (online/offline)" },
 703         { "register  (offline)       " },
 704         { "interrupt (offline)       " },
 705         { "loopback  (offline)       " }
 706 };
 707
 708 struct register_test {
 709         __u32 reg;
 710         __u32 mask;
 711 };
 712
 713 static const struct register_test nv_registers_test[] = {
 714         { NvRegUnknownSetupReg6, 0x01 },
 715         { NvRegMisc1, 0x03c },
 716         { NvRegOffloadConfig, 0x03ff },
 717         { NvRegMulticastAddrA, 0xffffffff },
 718         { NvRegTxWatermark, 0x0ff },
 719         { NvRegWakeUpFlags, 0x07777 },
 720         { 0, 0 }
 721 };
 722
 723 struct nv_skb_map {
 724         struct sk_buff *skb;
 725         dma_addr_t dma;
 726         unsigned int dma_len:31;
 727         unsigned int dma_single:1;
 728         struct ring_desc_ex *first_tx_desc;
 729         struct nv_skb_map *next_tx_ctx;
 730 };
 731
 732 /*
 733  * SMP locking:
 734  * All hardware access under netdev_priv(dev)->lock, except the performance
 735  * critical parts:
 736  * - rx is (pseudo-) lockless: it relies on the single-threading provided
 737  *      by the arch code for interrupts.
 738  * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
 739  *      needs netdev_priv(dev)->lock :-(
 740  * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
 741  */
 742
 743 /* in dev: base, irq */
 744 struct fe_priv {
 745         spinlock_t lock;
 746
 747         struct net_device *dev;
 748         struct napi_struct napi;
 749
 750         /* General data:
 751          * Locking: spin_lock(&np->lock); */
 752         struct nv_ethtool_stats estats;
 753         int in_shutdown;
 754         u32 linkspeed;
 755         int duplex;
 756         int autoneg;
 757         int fixed_mode;
 758         int phyaddr;
 759         int wolenabled;
 760         unsigned int phy_oui;
 761         unsigned int phy_model;
 762         unsigned int phy_rev;
 763         u16 gigabit;
 764         int intr_test;
 765         int recover_error;
 766         int quiet_count;
 767
 768         /* General data: RO fields */
 769         dma_addr_t ring_addr;
 770         struct pci_dev *pci_dev;
 771         u32 orig_mac[2];
 772         u32 events;
 773         u32 irqmask;
 774         u32 desc_ver;
 775         u32 txrxctl_bits;
 776         u32 vlanctl_bits;
 777         u32 driver_data;
 778         u32 device_id;
 779         u32 register_size;
 780         int rx_csum;
 781         u32 mac_in_use;
 782         int mgmt_version;
 783         int mgmt_sema;
 784
 785         void __iomem *base;
 786
 787         /* rx specific fields.
 788          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 789          */
 790         union ring_type get_rx, put_rx, first_rx, last_rx;
 791         struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
 792         struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
 793         struct nv_skb_map *rx_skb;
 794
 795         union ring_type rx_ring;
 796         unsigned int rx_buf_sz;
 797         unsigned int pkt_limit;
 798         struct timer_list oom_kick;
 799         struct timer_list nic_poll;
 800         struct timer_list stats_poll;
 801         u32 nic_poll_irq;
 802         int rx_ring_size;
 803
 804         /* media detection workaround.
 805          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 806          */
 807         int need_linktimer;
 808         unsigned long link_timeout;
 809         /*
 810          * tx specific fields.
 811          */
 812         union ring_type get_tx, put_tx, first_tx, last_tx;
 813         struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
 814         struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
 815         struct nv_skb_map *tx_skb;
 816
 817         union ring_type tx_ring;
 818         u32 tx_flags;
 819         int tx_ring_size;
 820         int tx_limit;
 821         u32 tx_pkts_in_progress;
 822         struct nv_skb_map *tx_change_owner;
 823         struct nv_skb_map *tx_end_flip;
 824         int tx_stop;
 825
 826         /* vlan fields */
 827         struct vlan_group *vlangrp;
 828
 829         /* msi/msi-x fields */
 830         u32 msi_flags;
 831         struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
 832
 833         /* flow control */
 834         u32 pause_flags;
 835
 836         /* power saved state */
 837         u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
 838
 839         /* for different msi-x irq type */
 840         char name_rx[IFNAMSIZ + 3];       /* -rx    */
 841         char name_tx[IFNAMSIZ + 3];       /* -tx    */
 842         char name_other[IFNAMSIZ + 6];    /* -other */
 843 };
 844
 845 /*
 846  * Maximum number of loops until we assume that a bit in the irq mask
 847  * is stuck. Overridable with module param.
 848  */
 849 static int max_interrupt_work = 4;
 850
 851 /*
 852  * Optimization can be either throuput mode or cpu mode
 853  *
 854  * Throughput Mode: Every tx and rx packet will generate an interrupt.
 855  * CPU Mode: Interrupts are controlled by a timer.
 856  */
 857 enum {
 858         NV_OPTIMIZATION_MODE_THROUGHPUT,
 859         NV_OPTIMIZATION_MODE_CPU,
 860         NV_OPTIMIZATION_MODE_DYNAMIC
 861 };
 862 static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC;
 863
 864 /*
 865  * Poll interval for timer irq
 866  *
 867  * This interval determines how frequent an interrupt is generated.
 868  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
 869  * Min = 0, and Max = 65535
 870  */
 871 static int poll_interval = -1;
 872
 873 /*
 874  * MSI interrupts
 875  */
 876 enum {
 877         NV_MSI_INT_DISABLED,
 878         NV_MSI_INT_ENABLED
 879 };
 880 static int msi = NV_MSI_INT_ENABLED;
 881
 882 /*
 883  * MSIX interrupts
 884  */
 885 enum {
 886         NV_MSIX_INT_DISABLED,
 887         NV_MSIX_INT_ENABLED
 888 };
 889 static int msix = NV_MSIX_INT_ENABLED;
 890
 891 /*
 892  * DMA 64bit
 893  */
 894 enum {
 895         NV_DMA_64BIT_DISABLED,
 896         NV_DMA_64BIT_ENABLED
 897 };
 898 static int dma_64bit = NV_DMA_64BIT_ENABLED;
 899
 900 /*
 901  * Crossover Detection
 902  * Realtek 8201 phy + some OEM boards do not work properly.
 903  */
 904 enum {
 905         NV_CROSSOVER_DETECTION_DISABLED,
 906         NV_CROSSOVER_DETECTION_ENABLED
 907 };
 908 static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
 909
 910 /*
 911  * Power down phy when interface is down (persists through reboot;
 912  * older Linux and other OSes may not power it up again)
 913  */
 914 static int phy_power_down;
 915
 916 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
 917 {
 918         return netdev_priv(dev);
 919 }
 920
 921 static inline u8 __iomem *get_hwbase(struct net_device *dev)
 922 {
 923         return ((struct fe_priv *)netdev_priv(dev))->base;
 924 }
 925
 926 static inline void pci_push(u8 __iomem *base)
 927 {
 928         /* force out pending posted writes */
 929         readl(base);
 930 }
 931
 932 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
 933 {
 934         return le32_to_cpu(prd->flaglen)
 935                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
 936 }
 937
 938 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
 939 {
 940         return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
 941 }
 942
 943 static bool nv_optimized(struct fe_priv *np)
 944 {
 945         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 946                 return false;
 947         return true;
 948 }
 949
 950 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
 951                                 int delay, int delaymax, const char *msg)
 952 {
 953         u8 __iomem *base = get_hwbase(dev);
 954
 955         pci_push(base);
 956         do {
 957                 udelay(delay);
 958                 delaymax -= delay;
 959                 if (delaymax < 0) {
 960                         if (msg)
 961                                 printk("%s", msg);
 962                         return 1;
 963                 }
 964         } while ((readl(base + offset) & mask) != target);
 965         return 0;
 966 }
 967
 968 #define NV_SETUP_RX_RING 0x01
 969 #define NV_SETUP_TX_RING 0x02
 970
 971 static inline u32 dma_low(dma_addr_t addr)
 972 {
 973         return addr;
 974 }
 975
 976 static inline u32 dma_high(dma_addr_t addr)
 977 {
 978         return addr>>31>>1;     /* 0 if 32bit, shift down by 32 if 64bit */
 979 }
 980
 981 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
 982 {
 983         struct fe_priv *np = get_nvpriv(dev);
 984         u8 __iomem *base = get_hwbase(dev);
 985
 986         if (!nv_optimized(np)) {
 987                 if (rxtx_flags & NV_SETUP_RX_RING)
 988                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
 989                 if (rxtx_flags & NV_SETUP_TX_RING)
 990                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
 991         } else {
 992                 if (rxtx_flags & NV_SETUP_RX_RING) {
 993                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
 994                         writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
 995                 }
 996                 if (rxtx_flags & NV_SETUP_TX_RING) {
 997                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
 998                         writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
 999                 }
1000         }
1001 }
1002
1003 static void free_rings(struct net_device *dev)
1004 {
1005         struct fe_priv *np = get_nvpriv(dev);
1006
1007         if (!nv_optimized(np)) {
1008                 if (np->rx_ring.orig)
1009                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
1010                                             np->rx_ring.orig, np->ring_addr);
1011         } else {
1012                 if (np->rx_ring.ex)
1013                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
1014                                             np->rx_ring.ex, np->ring_addr);
1015         }
1016         kfree(np->rx_skb);
1017         kfree(np->tx_skb);
1018 }
1019
1020 static int using_multi_irqs(struct net_device *dev)
1021 {
1022         struct fe_priv *np = get_nvpriv(dev);
1023
1024         if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
1025             ((np->msi_flags & NV_MSI_X_ENABLED) &&
1026              ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
1027                 return 0;
1028         else
1029                 return 1;
1030 }
1031
1032 static void nv_txrx_gate(struct net_device *dev, bool gate)
1033 {
1034         struct fe_priv *np = get_nvpriv(dev);
1035         u8 __iomem *base = get_hwbase(dev);
1036         u32 powerstate;
1037
1038         if (!np->mac_in_use &&
1039             (np->driver_data & DEV_HAS_POWER_CNTRL)) {
1040                 powerstate = readl(base + NvRegPowerState2);
1041                 if (gate)
1042                         powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS;
1043                 else
1044                         powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS;
1045                 writel(powerstate, base + NvRegPowerState2);
1046         }
1047 }
1048
1049 static void nv_enable_irq(struct net_device *dev)
1050 {
1051         struct fe_priv *np = get_nvpriv(dev);
1052
1053         if (!using_multi_irqs(dev)) {
1054                 if (np->msi_flags & NV_MSI_X_ENABLED)
1055                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1056                 else
1057                         enable_irq(np->pci_dev->irq);
1058         } else {
1059                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1060                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1061                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1062         }
1063 }
1064
1065 static void nv_disable_irq(struct net_device *dev)
1066 {
1067         struct fe_priv *np = get_nvpriv(dev);
1068
1069         if (!using_multi_irqs(dev)) {
1070                 if (np->msi_flags & NV_MSI_X_ENABLED)
1071                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1072                 else
1073                         disable_irq(np->pci_dev->irq);
1074         } else {
1075                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1076                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1077                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1078         }
1079 }
1080
1081 /* In MSIX mode, a write to irqmask behaves as XOR */
1082 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1083 {
1084         u8 __iomem *base = get_hwbase(dev);
1085
1086         writel(mask, base + NvRegIrqMask);
1087 }
1088
1089 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1090 {
1091         struct fe_priv *np = get_nvpriv(dev);
1092         u8 __iomem *base = get_hwbase(dev);
1093
1094         if (np->msi_flags & NV_MSI_X_ENABLED) {
1095                 writel(mask, base + NvRegIrqMask);
1096         } else {
1097                 if (np->msi_flags & NV_MSI_ENABLED)
1098                         writel(0, base + NvRegMSIIrqMask);
1099                 writel(0, base + NvRegIrqMask);
1100         }
1101 }
1102
1103 static void nv_napi_enable(struct net_device *dev)
1104 {
1105         struct fe_priv *np = get_nvpriv(dev);
1106
1107         napi_enable(&np->napi);
1108 }
1109
1110 static void nv_napi_disable(struct net_device *dev)
1111 {
1112         struct fe_priv *np = get_nvpriv(dev);
1113
1114         napi_disable(&np->napi);
1115 }
1116
1117 #define MII_READ        (-1)
1118 /* mii_rw: read/write a register on the PHY.
1119  *
1120  * Caller must guarantee serialization
1121  */
1122 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1123 {
1124         u8 __iomem *base = get_hwbase(dev);
1125         u32 reg;
1126         int retval;
1127
1128         writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1129
1130         reg = readl(base + NvRegMIIControl);
1131         if (reg & NVREG_MIICTL_INUSE) {
1132                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1133                 udelay(NV_MIIBUSY_DELAY);
1134         }
1135
1136         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1137         if (value != MII_READ) {
1138                 writel(value, base + NvRegMIIData);
1139                 reg |= NVREG_MIICTL_WRITE;
1140         }
1141         writel(reg, base + NvRegMIIControl);
1142
1143         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1144                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1145                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1146                                 dev->name, miireg, addr);
1147                 retval = -1;
1148         } else if (value != MII_READ) {
1149                 /* it was a write operation - fewer failures are detectable */
1150                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1151                                 dev->name, value, miireg, addr);
1152                 retval = 0;
1153         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1154                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1155                                 dev->name, miireg, addr);
1156                 retval = -1;
1157         } else {
1158                 retval = readl(base + NvRegMIIData);
1159                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1160                                 dev->name, miireg, addr, retval);
1161         }
1162
1163         return retval;
1164 }
1165
1166 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1167 {
1168         struct fe_priv *np = netdev_priv(dev);
1169         u32 miicontrol;
1170         unsigned int tries = 0;
1171
1172         miicontrol = BMCR_RESET | bmcr_setup;
1173         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol))
1174                 return -1;
1175
1176         /* wait for 500ms */
1177         msleep(500);
1178
1179         /* must wait till reset is deasserted */
1180         while (miicontrol & BMCR_RESET) {
1181                 msleep(10);
1182                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1183                 /* FIXME: 100 tries seem excessive */
1184                 if (tries++ > 100)
1185                         return -1;
1186         }
1187         return 0;
1188 }
1189
1190 static int phy_init(struct net_device *dev)
1191 {
1192         struct fe_priv *np = get_nvpriv(dev);
1193         u8 __iomem *base = get_hwbase(dev);
1194         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000, reg;
1195
1196         /* phy errata for E3016 phy */
1197         if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1198                 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1199                 reg &= ~PHY_MARVELL_E3016_INITMASK;
1200                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1201                         printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1202                         return PHY_ERROR;
1203                 }
1204         }
1205         if (np->phy_oui == PHY_OUI_REALTEK) {
1206                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1207                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1208                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1209                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1210                                 return PHY_ERROR;
1211                         }
1212                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1213                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1214                                 return PHY_ERROR;
1215                         }
1216                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1217                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1218                                 return PHY_ERROR;
1219                         }
1220                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1221                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1222                                 return PHY_ERROR;
1223                         }
1224                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1225                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1226                                 return PHY_ERROR;
1227                         }
1228                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1229                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1230                                 return PHY_ERROR;
1231                         }
1232                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1233                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1234                                 return PHY_ERROR;
1235                         }
1236                 }
1237                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1238                     np->phy_rev == PHY_REV_REALTEK_8211C) {
1239                         u32 powerstate = readl(base + NvRegPowerState2);
1240
1241                         /* need to perform hw phy reset */
1242                         powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1243                         writel(powerstate, base + NvRegPowerState2);
1244                         msleep(25);
1245
1246                         powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1247                         writel(powerstate, base + NvRegPowerState2);
1248                         msleep(25);
1249
1250                         reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1251                         reg |= PHY_REALTEK_INIT9;
1252                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) {
1253                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1254                                 return PHY_ERROR;
1255                         }
1256                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10)) {
1257                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1258                                 return PHY_ERROR;
1259                         }
1260                         reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1261                         if (!(reg & PHY_REALTEK_INIT11)) {
1262                                 reg |= PHY_REALTEK_INIT11;
1263                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) {
1264                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1265                                         return PHY_ERROR;
1266                                 }
1267                         }
1268                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1269                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1270                                 return PHY_ERROR;
1271                         }
1272                 }
1273                 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1274                         if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1275                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1276                                 phy_reserved |= PHY_REALTEK_INIT7;
1277                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1278                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1279                                         return PHY_ERROR;
1280                                 }
1281                         }
1282                 }
1283         }
1284
1285         /* set advertise register */
1286         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1287         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1288         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1289                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1290                 return PHY_ERROR;
1291         }
1292
1293         /* get phy interface type */
1294         phyinterface = readl(base + NvRegPhyInterface);
1295
1296         /* see if gigabit phy */
1297         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1298         if (mii_status & PHY_GIGABIT) {
1299                 np->gigabit = PHY_GIGABIT;
1300                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1301                 mii_control_1000 &= ~ADVERTISE_1000HALF;
1302                 if (phyinterface & PHY_RGMII)
1303                         mii_control_1000 |= ADVERTISE_1000FULL;
1304                 else
1305                         mii_control_1000 &= ~ADVERTISE_1000FULL;
1306
1307                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1308                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1309                         return PHY_ERROR;
1310                 }
1311         } else
1312                 np->gigabit = 0;
1313
1314         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1315         mii_control |= BMCR_ANENABLE;
1316
1317         if (np->phy_oui == PHY_OUI_REALTEK &&
1318             np->phy_model == PHY_MODEL_REALTEK_8211 &&
1319             np->phy_rev == PHY_REV_REALTEK_8211C) {
1320                 /* start autoneg since we already performed hw reset above */
1321                 mii_control |= BMCR_ANRESTART;
1322                 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1323                         printk(KERN_INFO "%s: phy init failed\n", pci_name(np->pci_dev));
1324                         return PHY_ERROR;
1325                 }
1326         } else {
1327                 /* reset the phy
1328                  * (certain phys need bmcr to be setup with reset)
1329                  */
1330                 if (phy_reset(dev, mii_control)) {
1331                         printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1332                         return PHY_ERROR;
1333                 }
1334         }
1335
1336         /* phy vendor specific configuration */
1337         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII)) {
1338                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1339                 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1340                 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1341                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1342                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1343                         return PHY_ERROR;
1344                 }
1345                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1346                 phy_reserved |= PHY_CICADA_INIT5;
1347                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1348                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1349                         return PHY_ERROR;
1350                 }
1351         }
1352         if (np->phy_oui == PHY_OUI_CICADA) {
1353                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1354                 phy_reserved |= PHY_CICADA_INIT6;
1355                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1356                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1357                         return PHY_ERROR;
1358                 }
1359         }
1360         if (np->phy_oui == PHY_OUI_VITESSE) {
1361                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) {
1362                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1363                         return PHY_ERROR;
1364                 }
1365                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) {
1366                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1367                         return PHY_ERROR;
1368                 }
1369                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1370                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1371                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1372                         return PHY_ERROR;
1373                 }
1374                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1375                 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1376                 phy_reserved |= PHY_VITESSE_INIT3;
1377                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1378                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1379                         return PHY_ERROR;
1380                 }
1381                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) {
1382                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1383                         return PHY_ERROR;
1384                 }
1385                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) {
1386                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1387                         return PHY_ERROR;
1388                 }
1389                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1390                 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1391                 phy_reserved |= PHY_VITESSE_INIT3;
1392                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1393                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1394                         return PHY_ERROR;
1395                 }
1396                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1397                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1398                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1399                         return PHY_ERROR;
1400                 }
1401                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) {
1402                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1403                         return PHY_ERROR;
1404                 }
1405                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) {
1406                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1407                         return PHY_ERROR;
1408                 }
1409                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1410                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1411                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1412                         return PHY_ERROR;
1413                 }
1414                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1415                 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1416                 phy_reserved |= PHY_VITESSE_INIT8;
1417                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1418                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1419                         return PHY_ERROR;
1420                 }
1421                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) {
1422                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1423                         return PHY_ERROR;
1424                 }
1425                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) {
1426                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1427                         return PHY_ERROR;
1428                 }
1429         }
1430         if (np->phy_oui == PHY_OUI_REALTEK) {
1431                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1432                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1433                         /* reset could have cleared these out, set them back */
1434                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1435                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1436                                 return PHY_ERROR;
1437                         }
1438                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1439                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1440                                 return PHY_ERROR;
1441                         }
1442                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1443                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1444                                 return PHY_ERROR;
1445                         }
1446                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1447                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1448                                 return PHY_ERROR;
1449                         }
1450                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1451                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1452                                 return PHY_ERROR;
1453                         }
1454                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1455                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1456                                 return PHY_ERROR;
1457                         }
1458                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1459                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1460                                 return PHY_ERROR;
1461                         }
1462                 }
1463                 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1464                         if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1465                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1466                                 phy_reserved |= PHY_REALTEK_INIT7;
1467                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1468                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1469                                         return PHY_ERROR;
1470                                 }
1471                         }
1472                         if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1473                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1474                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1475                                         return PHY_ERROR;
1476                                 }
1477                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
1478                                 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1479                                 phy_reserved |= PHY_REALTEK_INIT3;
1480                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved)) {
1481                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1482                                         return PHY_ERROR;
1483                                 }
1484                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1485                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1486                                         return PHY_ERROR;
1487                                 }
1488                         }
1489                 }
1490         }
1491
1492         /* some phys clear out pause advertisment on reset, set it back */
1493         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1494
1495         /* restart auto negotiation, power down phy */
1496         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1497         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1498         if (phy_power_down)
1499                 mii_control |= BMCR_PDOWN;
1500         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control))
1501                 return PHY_ERROR;
1502
1503         return 0;
1504 }
1505
1506 static void nv_start_rx(struct net_device *dev)
1507 {
1508         struct fe_priv *np = netdev_priv(dev);
1509         u8 __iomem *base = get_hwbase(dev);
1510         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1511
1512         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1513         /* Already running? Stop it. */
1514         if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1515                 rx_ctrl &= ~NVREG_RCVCTL_START;
1516                 writel(rx_ctrl, base + NvRegReceiverControl);
1517                 pci_push(base);
1518         }
1519         writel(np->linkspeed, base + NvRegLinkSpeed);
1520         pci_push(base);
1521         rx_ctrl |= NVREG_RCVCTL_START;
1522         if (np->mac_in_use)
1523                 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1524         writel(rx_ctrl, base + NvRegReceiverControl);
1525         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1526                                 dev->name, np->duplex, np->linkspeed);
1527         pci_push(base);
1528 }
1529
1530 static void nv_stop_rx(struct net_device *dev)
1531 {
1532         struct fe_priv *np = netdev_priv(dev);
1533         u8 __iomem *base = get_hwbase(dev);
1534         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1535
1536         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1537         if (!np->mac_in_use)
1538                 rx_ctrl &= ~NVREG_RCVCTL_START;
1539         else
1540                 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1541         writel(rx_ctrl, base + NvRegReceiverControl);
1542         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1543                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1544                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1545
1546         udelay(NV_RXSTOP_DELAY2);
1547         if (!np->mac_in_use)
1548                 writel(0, base + NvRegLinkSpeed);
1549 }
1550
1551 static void nv_start_tx(struct net_device *dev)
1552 {
1553         struct fe_priv *np = netdev_priv(dev);
1554         u8 __iomem *base = get_hwbase(dev);
1555         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1556
1557         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1558         tx_ctrl |= NVREG_XMITCTL_START;
1559         if (np->mac_in_use)
1560                 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1561         writel(tx_ctrl, base + NvRegTransmitterControl);
1562         pci_push(base);
1563 }
1564
1565 static void nv_stop_tx(struct net_device *dev)
1566 {
1567         struct fe_priv *np = netdev_priv(dev);
1568         u8 __iomem *base = get_hwbase(dev);
1569         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1570
1571         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1572         if (!np->mac_in_use)
1573                 tx_ctrl &= ~NVREG_XMITCTL_START;
1574         else
1575                 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1576         writel(tx_ctrl, base + NvRegTransmitterControl);
1577         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1578                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1579                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1580
1581         udelay(NV_TXSTOP_DELAY2);
1582         if (!np->mac_in_use)
1583                 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1584                        base + NvRegTransmitPoll);
1585 }
1586
1587 static void nv_start_rxtx(struct net_device *dev)
1588 {
1589         nv_start_rx(dev);
1590         nv_start_tx(dev);
1591 }
1592
1593 static void nv_stop_rxtx(struct net_device *dev)
1594 {
1595         nv_stop_rx(dev);
1596         nv_stop_tx(dev);
1597 }
1598
1599 static void nv_txrx_reset(struct net_device *dev)
1600 {
1601         struct fe_priv *np = netdev_priv(dev);
1602         u8 __iomem *base = get_hwbase(dev);
1603
1604         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1605         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1606         pci_push(base);
1607         udelay(NV_TXRX_RESET_DELAY);
1608         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1609         pci_push(base);
1610 }
1611
1612 static void nv_mac_reset(struct net_device *dev)
1613 {
1614         struct fe_priv *np = netdev_priv(dev);
1615         u8 __iomem *base = get_hwbase(dev);
1616         u32 temp1, temp2, temp3;
1617
1618         dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1619
1620         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1621         pci_push(base);
1622
1623         /* save registers since they will be cleared on reset */
1624         temp1 = readl(base + NvRegMacAddrA);
1625         temp2 = readl(base + NvRegMacAddrB);
1626         temp3 = readl(base + NvRegTransmitPoll);
1627
1628         writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1629         pci_push(base);
1630         udelay(NV_MAC_RESET_DELAY);
1631         writel(0, base + NvRegMacReset);
1632         pci_push(base);
1633         udelay(NV_MAC_RESET_DELAY);
1634
1635         /* restore saved registers */
1636         writel(temp1, base + NvRegMacAddrA);
1637         writel(temp2, base + NvRegMacAddrB);
1638         writel(temp3, base + NvRegTransmitPoll);
1639
1640         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1641         pci_push(base);
1642 }
1643
1644 static void nv_get_hw_stats(struct net_device *dev)
1645 {
1646         struct fe_priv *np = netdev_priv(dev);
1647         u8 __iomem *base = get_hwbase(dev);
1648
1649         np->estats.tx_bytes += readl(base + NvRegTxCnt);
1650         np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1651         np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1652         np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1653         np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1654         np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1655         np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1656         np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1657         np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1658         np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1659         np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1660         np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1661         np->estats.rx_runt += readl(base + NvRegRxRunt);
1662         np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1663         np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1664         np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1665         np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1666         np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1667         np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1668         np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1669         np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1670         np->estats.rx_packets =
1671                 np->estats.rx_unicast +
1672                 np->estats.rx_multicast +
1673                 np->estats.rx_broadcast;
1674         np->estats.rx_errors_total =
1675                 np->estats.rx_crc_errors +
1676                 np->estats.rx_over_errors +
1677                 np->estats.rx_frame_error +
1678                 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1679                 np->estats.rx_late_collision +
1680                 np->estats.rx_runt +
1681                 np->estats.rx_frame_too_long;
1682         np->estats.tx_errors_total =
1683                 np->estats.tx_late_collision +
1684                 np->estats.tx_fifo_errors +
1685                 np->estats.tx_carrier_errors +
1686                 np->estats.tx_excess_deferral +
1687                 np->estats.tx_retry_error;
1688
1689         if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1690                 np->estats.tx_deferral += readl(base + NvRegTxDef);
1691                 np->estats.tx_packets += readl(base + NvRegTxFrame);
1692                 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1693                 np->estats.tx_pause += readl(base + NvRegTxPause);
1694                 np->estats.rx_pause += readl(base + NvRegRxPause);
1695                 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1696         }
1697
1698         if (np->driver_data & DEV_HAS_STATISTICS_V3) {
1699                 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1700                 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1701                 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
1702         }
1703 }
1704
1705 /*
1706  * nv_get_stats: dev->get_stats function
1707  * Get latest stats value from the nic.
1708  * Called with read_lock(&dev_base_lock) held for read -
1709  * only synchronized against unregister_netdevice.
1710  */
1711 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1712 {
1713         struct fe_priv *np = netdev_priv(dev);
1714
1715         /* If the nic supports hw counters then retrieve latest values */
1716         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) {
1717                 nv_get_hw_stats(dev);
1718
1719                 /* copy to net_device stats */
1720                 dev->stats.tx_bytes = np->estats.tx_bytes;
1721                 dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1722                 dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1723                 dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
1724                 dev->stats.rx_over_errors = np->estats.rx_over_errors;
1725                 dev->stats.rx_errors = np->estats.rx_errors_total;
1726                 dev->stats.tx_errors = np->estats.tx_errors_total;
1727         }
1728
1729         return &dev->stats;
1730 }
1731
1732 /*
1733  * nv_alloc_rx: fill rx ring entries.
1734  * Return 1 if the allocations for the skbs failed and the
1735  * rx engine is without Available descriptors
1736  */
1737 static int nv_alloc_rx(struct net_device *dev)
1738 {
1739         struct fe_priv *np = netdev_priv(dev);
1740         struct ring_desc *less_rx;
1741
1742         less_rx = np->get_rx.orig;
1743         if (less_rx-- == np->first_rx.orig)
1744                 less_rx = np->last_rx.orig;
1745
1746         while (np->put_rx.orig != less_rx) {
1747                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1748                 if (skb) {
1749                         np->put_rx_ctx->skb = skb;
1750                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1751                                                              skb->data,
1752                                                              skb_tailroom(skb),
1753                                                              PCI_DMA_FROMDEVICE);
1754                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1755                         np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1756                         wmb();
1757                         np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1758                         if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1759                                 np->put_rx.orig = np->first_rx.orig;
1760                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1761                                 np->put_rx_ctx = np->first_rx_ctx;
1762                 } else
1763                         return 1;
1764         }
1765         return 0;
1766 }
1767
1768 static int nv_alloc_rx_optimized(struct net_device *dev)
1769 {
1770         struct fe_priv *np = netdev_priv(dev);
1771         struct ring_desc_ex *less_rx;
1772
1773         less_rx = np->get_rx.ex;
1774         if (less_rx-- == np->first_rx.ex)
1775                 less_rx = np->last_rx.ex;
1776
1777         while (np->put_rx.ex != less_rx) {
1778                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1779                 if (skb) {
1780                         np->put_rx_ctx->skb = skb;
1781                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1782                                                              skb->data,
1783                                                              skb_tailroom(skb),
1784                                                              PCI_DMA_FROMDEVICE);
1785                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1786                         np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1787                         np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
1788                         wmb();
1789                         np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1790                         if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1791                                 np->put_rx.ex = np->first_rx.ex;
1792                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1793                                 np->put_rx_ctx = np->first_rx_ctx;
1794                 } else
1795                         return 1;
1796         }
1797         return 0;
1798 }
1799
1800 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1801 static void nv_do_rx_refill(unsigned long data)
1802 {
1803         struct net_device *dev = (struct net_device *) data;
1804         struct fe_priv *np = netdev_priv(dev);
1805
1806         /* Just reschedule NAPI rx processing */
1807         napi_schedule(&np->napi);
1808 }
1809
1810 static void nv_init_rx(struct net_device *dev)
1811 {
1812         struct fe_priv *np = netdev_priv(dev);
1813         int i;
1814
1815         np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1816
1817         if (!nv_optimized(np))
1818                 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1819         else
1820                 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1821         np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1822         np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1823
1824         for (i = 0; i < np->rx_ring_size; i++) {
1825                 if (!nv_optimized(np)) {
1826                         np->rx_ring.orig[i].flaglen = 0;
1827                         np->rx_ring.orig[i].buf = 0;
1828                 } else {
1829                         np->rx_ring.ex[i].flaglen = 0;
1830                         np->rx_ring.ex[i].txvlan = 0;
1831                         np->rx_ring.ex[i].bufhigh = 0;
1832                         np->rx_ring.ex[i].buflow = 0;
1833                 }
1834                 np->rx_skb[i].skb = NULL;
1835                 np->rx_skb[i].dma = 0;
1836         }
1837 }
1838
1839 static void nv_init_tx(struct net_device *dev)
1840 {
1841         struct fe_priv *np = netdev_priv(dev);
1842         int i;
1843
1844         np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1845
1846         if (!nv_optimized(np))
1847                 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1848         else
1849                 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1850         np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1851         np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1852         np->tx_pkts_in_progress = 0;
1853         np->tx_change_owner = NULL;
1854         np->tx_end_flip = NULL;
1855         np->tx_stop = 0;
1856
1857         for (i = 0; i < np->tx_ring_size; i++) {
1858                 if (!nv_optimized(np)) {
1859                         np->tx_ring.orig[i].flaglen = 0;
1860                         np->tx_ring.orig[i].buf = 0;
1861                 } else {
1862                         np->tx_ring.ex[i].flaglen = 0;
1863                         np->tx_ring.ex[i].txvlan = 0;
1864                         np->tx_ring.ex[i].bufhigh = 0;
1865                         np->tx_ring.ex[i].buflow = 0;
1866                 }
1867                 np->tx_skb[i].skb = NULL;
1868                 np->tx_skb[i].dma = 0;
1869                 np->tx_skb[i].dma_len = 0;
1870                 np->tx_skb[i].dma_single = 0;
1871                 np->tx_skb[i].first_tx_desc = NULL;
1872                 np->tx_skb[i].next_tx_ctx = NULL;
1873         }
1874 }
1875
1876 static int nv_init_ring(struct net_device *dev)
1877 {
1878         struct fe_priv *np = netdev_priv(dev);
1879
1880         nv_init_tx(dev);
1881         nv_init_rx(dev);
1882
1883         if (!nv_optimized(np))
1884                 return nv_alloc_rx(dev);
1885         else
1886                 return nv_alloc_rx_optimized(dev);
1887 }
1888
1889 static void nv_unmap_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1890 {
1891         if (tx_skb->dma) {
1892                 if (tx_skb->dma_single)
1893                         pci_unmap_single(np->pci_dev, tx_skb->dma,
1894                                          tx_skb->dma_len,
1895                                          PCI_DMA_TODEVICE);
1896                 else
1897                         pci_unmap_page(np->pci_dev, tx_skb->dma,
1898                                        tx_skb->dma_len,
1899                                        PCI_DMA_TODEVICE);
1900                 tx_skb->dma = 0;
1901         }
1902 }
1903
1904 static int nv_release_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1905 {
1906         nv_unmap_txskb(np, tx_skb);
1907         if (tx_skb->skb) {
1908                 dev_kfree_skb_any(tx_skb->skb);
1909                 tx_skb->skb = NULL;
1910                 return 1;
1911         }
1912         return 0;
1913 }
1914
1915 static void nv_drain_tx(struct net_device *dev)
1916 {
1917         struct fe_priv *np = netdev_priv(dev);
1918         unsigned int i;
1919
1920         for (i = 0; i < np->tx_ring_size; i++) {
1921                 if (!nv_optimized(np)) {
1922                         np->tx_ring.orig[i].flaglen = 0;
1923                         np->tx_ring.orig[i].buf = 0;
1924                 } else {
1925                         np->tx_ring.ex[i].flaglen = 0;
1926                         np->tx_ring.ex[i].txvlan = 0;
1927                         np->tx_ring.ex[i].bufhigh = 0;
1928                         np->tx_ring.ex[i].buflow = 0;
1929                 }
1930                 if (nv_release_txskb(np, &np->tx_skb[i]))
1931                         dev->stats.tx_dropped++;
1932                 np->tx_skb[i].dma = 0;
1933                 np->tx_skb[i].dma_len = 0;
1934                 np->tx_skb[i].dma_single = 0;
1935                 np->tx_skb[i].first_tx_desc = NULL;
1936                 np->tx_skb[i].next_tx_ctx = NULL;
1937         }
1938         np->tx_pkts_in_progress = 0;
1939         np->tx_change_owner = NULL;
1940         np->tx_end_flip = NULL;
1941 }
1942
1943 static void nv_drain_rx(struct net_device *dev)
1944 {
1945         struct fe_priv *np = netdev_priv(dev);
1946         int i;
1947
1948         for (i = 0; i < np->rx_ring_size; i++) {
1949                 if (!nv_optimized(np)) {
1950                         np->rx_ring.orig[i].flaglen = 0;
1951                         np->rx_ring.orig[i].buf = 0;
1952                 } else {
1953                         np->rx_ring.ex[i].flaglen = 0;
1954                         np->rx_ring.ex[i].txvlan = 0;
1955                         np->rx_ring.ex[i].bufhigh = 0;
1956                         np->rx_ring.ex[i].buflow = 0;
1957                 }
1958                 wmb();
1959                 if (np->rx_skb[i].skb) {
1960                         pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
1961                                          (skb_end_pointer(np->rx_skb[i].skb) -
1962                                           np->rx_skb[i].skb->data),
1963                                          PCI_DMA_FROMDEVICE);
1964                         dev_kfree_skb(np->rx_skb[i].skb);
1965                         np->rx_skb[i].skb = NULL;
1966                 }
1967         }
1968 }
1969
1970 static void nv_drain_rxtx(struct net_device *dev)
1971 {
1972         nv_drain_tx(dev);
1973         nv_drain_rx(dev);
1974 }
1975
1976 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1977 {
1978         return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1979 }
1980
1981 static void nv_legacybackoff_reseed(struct net_device *dev)
1982 {
1983         u8 __iomem *base = get_hwbase(dev);
1984         u32 reg;
1985         u32 low;
1986         int tx_status = 0;
1987
1988         reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
1989         get_random_bytes(&low, sizeof(low));
1990         reg |= low & NVREG_SLOTTIME_MASK;
1991
1992         /* Need to stop tx before change takes effect.
1993          * Caller has already gained np->lock.
1994          */
1995         tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
1996         if (tx_status)
1997                 nv_stop_tx(dev);
1998         nv_stop_rx(dev);
1999         writel(reg, base + NvRegSlotTime);
2000         if (tx_status)
2001                 nv_start_tx(dev);
2002         nv_start_rx(dev);
2003 }
2004
2005 /* Gear Backoff Seeds */
2006 #define BACKOFF_SEEDSET_ROWS    8
2007 #define BACKOFF_SEEDSET_LFSRS   15
2008
2009 /* Known Good seed sets */
2010 static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2011         {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2012         {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
2013         {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2014         {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2015         {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2016         {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2017         {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800,  84},
2018         {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184} };
2019
2020 static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2021         {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2022         {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2023         {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2024         {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2025         {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2026         {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2027         {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2028         {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395} };
2029
2030 static void nv_gear_backoff_reseed(struct net_device *dev)
2031 {
2032         u8 __iomem *base = get_hwbase(dev);
2033         u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
2034         u32 temp, seedset, combinedSeed;
2035         int i;
2036
2037         /* Setup seed for free running LFSR */
2038         /* We are going to read the time stamp counter 3 times
2039            and swizzle bits around to increase randomness */
2040         get_random_bytes(&miniseed1, sizeof(miniseed1));
2041         miniseed1 &= 0x0fff;
2042         if (miniseed1 == 0)
2043                 miniseed1 = 0xabc;
2044
2045         get_random_bytes(&miniseed2, sizeof(miniseed2));
2046         miniseed2 &= 0x0fff;
2047         if (miniseed2 == 0)
2048                 miniseed2 = 0xabc;
2049         miniseed2_reversed =
2050                 ((miniseed2 & 0xF00) >> 8) |
2051                  (miniseed2 & 0x0F0) |
2052                  ((miniseed2 & 0x00F) << 8);
2053
2054         get_random_bytes(&miniseed3, sizeof(miniseed3));
2055         miniseed3 &= 0x0fff;
2056         if (miniseed3 == 0)
2057                 miniseed3 = 0xabc;
2058         miniseed3_reversed =
2059                 ((miniseed3 & 0xF00) >> 8) |
2060                  (miniseed3 & 0x0F0) |
2061                  ((miniseed3 & 0x00F) << 8);
2062
2063         combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
2064                        (miniseed2 ^ miniseed3_reversed);
2065
2066         /* Seeds can not be zero */
2067         if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
2068                 combinedSeed |= 0x08;
2069         if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
2070                 combinedSeed |= 0x8000;
2071
2072         /* No need to disable tx here */
2073         temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
2074         temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
2075         temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
2076         writel(temp, base + NvRegBackOffControl);
2077
2078         /* Setup seeds for all gear LFSRs. */
2079         get_random_bytes(&seedset, sizeof(seedset));
2080         seedset = seedset % BACKOFF_SEEDSET_ROWS;
2081         for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++) {
2082                 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
2083                 temp |= main_seedset[seedset][i-1] & 0x3ff;
2084                 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
2085                 writel(temp, base + NvRegBackOffControl);
2086         }
2087 }
2088
2089 /*
2090  * nv_start_xmit: dev->hard_start_xmit function
2091  * Called with netif_tx_lock held.
2092  */
2093 static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
2094 {
2095         struct fe_priv *np = netdev_priv(dev);
2096         u32 tx_flags = 0;
2097         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2098         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2099         unsigned int i;
2100         u32 offset = 0;
2101         u32 bcnt;
2102         u32 size = skb_headlen(skb);
2103         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2104         u32 empty_slots;
2105         struct ring_desc *put_tx;
2106         struct ring_desc *start_tx;
2107         struct ring_desc *prev_tx;
2108         struct nv_skb_map *prev_tx_ctx;
2109         unsigned long flags;
2110
2111         /* add fragments to entries count */
2112         for (i = 0; i < fragments; i++) {
2113                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2114                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2115         }
2116
2117         spin_lock_irqsave(&np->lock, flags);
2118         empty_slots = nv_get_empty_tx_slots(np);
2119         if (unlikely(empty_slots <= entries)) {
2120                 netif_stop_queue(dev);
2121                 np->tx_stop = 1;
2122                 spin_unlock_irqrestore(&np->lock, flags);
2123                 return NETDEV_TX_BUSY;
2124         }
2125         spin_unlock_irqrestore(&np->lock, flags);
2126
2127         start_tx = put_tx = np->put_tx.orig;
2128
2129         /* setup the header buffer */
2130         do {
2131                 prev_tx = put_tx;
2132                 prev_tx_ctx = np->put_tx_ctx;
2133                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2134                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2135                                                 PCI_DMA_TODEVICE);
2136                 np->put_tx_ctx->dma_len = bcnt;
2137                 np->put_tx_ctx->dma_single = 1;
2138                 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2139                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2140
2141                 tx_flags = np->tx_flags;
2142                 offset += bcnt;
2143                 size -= bcnt;
2144                 if (unlikely(put_tx++ == np->last_tx.orig))
2145                         put_tx = np->first_tx.orig;
2146                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2147                         np->put_tx_ctx = np->first_tx_ctx;
2148         } while (size);
2149
2150         /* setup the fragments */
2151         for (i = 0; i < fragments; i++) {
2152                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2153                 u32 size = frag->size;
2154                 offset = 0;
2155
2156                 do {
2157                         prev_tx = put_tx;
2158                         prev_tx_ctx = np->put_tx_ctx;
2159                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2160                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2161                                                            PCI_DMA_TODEVICE);
2162                         np->put_tx_ctx->dma_len = bcnt;
2163                         np->put_tx_ctx->dma_single = 0;
2164                         put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2165                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2166
2167                         offset += bcnt;
2168                         size -= bcnt;
2169                         if (unlikely(put_tx++ == np->last_tx.orig))
2170                                 put_tx = np->first_tx.orig;
2171                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2172                                 np->put_tx_ctx = np->first_tx_ctx;
2173                 } while (size);
2174         }
2175
2176         /* set last fragment flag  */
2177         prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
2178
2179         /* save skb in this slot's context area */
2180         prev_tx_ctx->skb = skb;
2181
2182         if (skb_is_gso(skb))
2183                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2184         else
2185                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2186                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2187
2188         spin_lock_irqsave(&np->lock, flags);
2189
2190         /* set tx flags */
2191         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2192         np->put_tx.orig = put_tx;
2193
2194         spin_unlock_irqrestore(&np->lock, flags);
2195
2196         dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
2197                 dev->name, entries, tx_flags_extra);
2198         {
2199                 int j;
2200                 for (j = 0; j < 64; j++) {
2201                         if ((j%16) == 0)
2202                                 dprintk("\n%03x:", j);
2203                         dprintk(" %02x", ((unsigned char *)skb->data)[j]);
2204                 }
2205                 dprintk("\n");
2206         }
2207
2208         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2209         return NETDEV_TX_OK;
2210 }
2211
2212 static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb,
2213                                            struct net_device *dev)
2214 {
2215         struct fe_priv *np = netdev_priv(dev);
2216         u32 tx_flags = 0;
2217         u32 tx_flags_extra;
2218         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2219         unsigned int i;
2220         u32 offset = 0;
2221         u32 bcnt;
2222         u32 size = skb_headlen(skb);
2223         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2224         u32 empty_slots;
2225         struct ring_desc_ex *put_tx;
2226         struct ring_desc_ex *start_tx;
2227         struct ring_desc_ex *prev_tx;
2228         struct nv_skb_map *prev_tx_ctx;
2229         struct nv_skb_map *start_tx_ctx;
2230         unsigned long flags;
2231
2232         /* add fragments to entries count */
2233         for (i = 0; i < fragments; i++) {
2234                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2235                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2236         }
2237
2238         spin_lock_irqsave(&np->lock, flags);
2239         empty_slots = nv_get_empty_tx_slots(np);
2240         if (unlikely(empty_slots <= entries)) {
2241                 netif_stop_queue(dev);
2242                 np->tx_stop = 1;
2243                 spin_unlock_irqrestore(&np->lock, flags);
2244                 return NETDEV_TX_BUSY;
2245         }
2246         spin_unlock_irqrestore(&np->lock, flags);
2247
2248         start_tx = put_tx = np->put_tx.ex;
2249         start_tx_ctx = np->put_tx_ctx;
2250
2251         /* setup the header buffer */
2252         do {
2253                 prev_tx = put_tx;
2254                 prev_tx_ctx = np->put_tx_ctx;
2255                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2256                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2257                                                 PCI_DMA_TODEVICE);
2258                 np->put_tx_ctx->dma_len = bcnt;
2259                 np->put_tx_ctx->dma_single = 1;
2260                 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2261                 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2262                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2263
2264                 tx_flags = NV_TX2_VALID;
2265                 offset += bcnt;
2266                 size -= bcnt;
2267                 if (unlikely(put_tx++ == np->last_tx.ex))
2268                         put_tx = np->first_tx.ex;
2269                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2270                         np->put_tx_ctx = np->first_tx_ctx;
2271         } while (size);
2272
2273         /* setup the fragments */
2274         for (i = 0; i < fragments; i++) {
2275                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2276                 u32 size = frag->size;
2277                 offset = 0;
2278
2279                 do {
2280                         prev_tx = put_tx;
2281                         prev_tx_ctx = np->put_tx_ctx;
2282                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2283                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2284                                                            PCI_DMA_TODEVICE);
2285                         np->put_tx_ctx->dma_len = bcnt;
2286                         np->put_tx_ctx->dma_single = 0;
2287                         put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2288                         put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2289                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2290
2291                         offset += bcnt;
2292                         size -= bcnt;
2293                         if (unlikely(put_tx++ == np->last_tx.ex))
2294                                 put_tx = np->first_tx.ex;
2295                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2296                                 np->put_tx_ctx = np->first_tx_ctx;
2297                 } while (size);
2298         }
2299
2300         /* set last fragment flag  */
2301         prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
2302
2303         /* save skb in this slot's context area */
2304         prev_tx_ctx->skb = skb;
2305
2306         if (skb_is_gso(skb))
2307                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2308         else
2309                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2310                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2311
2312         /* vlan tag */
2313         if (vlan_tx_tag_present(skb))
2314                 start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT |
2315                                         vlan_tx_tag_get(skb));
2316         else
2317                 start_tx->txvlan = 0;
2318
2319         spin_lock_irqsave(&np->lock, flags);
2320
2321         if (np->tx_limit) {
2322                 /* Limit the number of outstanding tx. Setup all fragments, but
2323                  * do not set the VALID bit on the first descriptor. Save a pointer
2324                  * to that descriptor and also for next skb_map element.
2325                  */
2326
2327                 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2328                         if (!np->tx_change_owner)
2329                                 np->tx_change_owner = start_tx_ctx;
2330
2331                         /* remove VALID bit */
2332                         tx_flags &= ~NV_TX2_VALID;
2333                         start_tx_ctx->first_tx_desc = start_tx;
2334                         start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2335                         np->tx_end_flip = np->put_tx_ctx;
2336                 } else {
2337                         np->tx_pkts_in_progress++;
2338                 }
2339         }
2340
2341         /* set tx flags */
2342         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2343         np->put_tx.ex = put_tx;
2344
2345         spin_unlock_irqrestore(&np->lock, flags);
2346
2347         dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
2348                 dev->name, entries, tx_flags_extra);
2349         {
2350                 int j;
2351                 for (j = 0; j < 64; j++) {
2352                         if ((j%16) == 0)
2353                                 dprintk("\n%03x:", j);
2354                         dprintk(" %02x", ((unsigned char *)skb->data)[j]);
2355                 }
2356                 dprintk("\n");
2357         }
2358
2359         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2360         return NETDEV_TX_OK;
2361 }
2362
2363 static inline void nv_tx_flip_ownership(struct net_device *dev)
2364 {
2365         struct fe_priv *np = netdev_priv(dev);
2366
2367         np->tx_pkts_in_progress--;
2368         if (np->tx_change_owner) {
2369                 np->tx_change_owner->first_tx_desc->flaglen |=
2370                         cpu_to_le32(NV_TX2_VALID);
2371                 np->tx_pkts_in_progress++;
2372
2373                 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2374                 if (np->tx_change_owner == np->tx_end_flip)
2375                         np->tx_change_owner = NULL;
2376
2377                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2378         }
2379 }
2380
2381 /*
2382  * nv_tx_done: check for completed packets, release the skbs.
2383  *
2384  * Caller must own np->lock.
2385  */
2386 static int nv_tx_done(struct net_device *dev, int limit)
2387 {
2388         struct fe_priv *np = netdev_priv(dev);
2389         u32 flags;
2390         int tx_work = 0;
2391         struct ring_desc *orig_get_tx = np->get_tx.orig;
2392
2393         while ((np->get_tx.orig != np->put_tx.orig) &&
2394                !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) &&
2395                (tx_work < limit)) {
2396
2397                 dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
2398                                         dev->name, flags);
2399
2400                 nv_unmap_txskb(np, np->get_tx_ctx);
2401
2402                 if (np->desc_ver == DESC_VER_1) {
2403                         if (flags & NV_TX_LASTPACKET) {
2404                                 if (flags & NV_TX_ERROR) {
2405                                         if (flags & NV_TX_UNDERFLOW)
2406                                                 dev->stats.tx_fifo_errors++;
2407                                         if (flags & NV_TX_CARRIERLOST)
2408                                                 dev->stats.tx_carrier_errors++;
2409                                         if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK))
2410                                                 nv_legacybackoff_reseed(dev);
2411                                         dev->stats.tx_errors++;
2412                                 } else {
2413                                         dev->stats.tx_packets++;
2414                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2415                                 }
2416                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2417                                 np->get_tx_ctx->skb = NULL;
2418                                 tx_work++;
2419                         }
2420                 } else {
2421                         if (flags & NV_TX2_LASTPACKET) {
2422                                 if (flags & NV_TX2_ERROR) {
2423                                         if (flags & NV_TX2_UNDERFLOW)
2424                                                 dev->stats.tx_fifo_errors++;
2425                                         if (flags & NV_TX2_CARRIERLOST)
2426                                                 dev->stats.tx_carrier_errors++;
2427                                         if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK))
2428                                                 nv_legacybackoff_reseed(dev);
2429                                         dev->stats.tx_errors++;
2430                                 } else {
2431                                         dev->stats.tx_packets++;
2432                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2433                                 }
2434                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2435                                 np->get_tx_ctx->skb = NULL;
2436                                 tx_work++;
2437                         }
2438                 }
2439                 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2440                         np->get_tx.orig = np->first_tx.orig;
2441                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2442                         np->get_tx_ctx = np->first_tx_ctx;
2443         }
2444         if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2445                 np->tx_stop = 0;
2446                 netif_wake_queue(dev);
2447         }
2448         return tx_work;
2449 }
2450
2451 static int nv_tx_done_optimized(struct net_device *dev, int limit)
2452 {
2453         struct fe_priv *np = netdev_priv(dev);
2454         u32 flags;
2455         int tx_work = 0;
2456         struct ring_desc_ex *orig_get_tx = np->get_tx.ex;
2457
2458         while ((np->get_tx.ex != np->put_tx.ex) &&
2459                !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX2_VALID) &&
2460                (tx_work < limit)) {
2461
2462                 dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n",
2463                                         dev->name, flags);
2464
2465                 nv_unmap_txskb(np, np->get_tx_ctx);
2466
2467                 if (flags & NV_TX2_LASTPACKET) {
2468                         if (!(flags & NV_TX2_ERROR))
2469                                 dev->stats.tx_packets++;
2470                         else {
2471                                 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2472                                         if (np->driver_data & DEV_HAS_GEAR_MODE)
2473                                                 nv_gear_backoff_reseed(dev);
2474                                         else
2475                                                 nv_legacybackoff_reseed(dev);
2476                                 }
2477                         }
2478
2479                         dev_kfree_skb_any(np->get_tx_ctx->skb);
2480                         np->get_tx_ctx->skb = NULL;
2481                         tx_work++;
2482
2483                         if (np->tx_limit)
2484                                 nv_tx_flip_ownership(dev);
2485                 }
2486                 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2487                         np->get_tx.ex = np->first_tx.ex;
2488                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2489                         np->get_tx_ctx = np->first_tx_ctx;
2490         }
2491         if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2492                 np->tx_stop = 0;
2493                 netif_wake_queue(dev);
2494         }
2495         return tx_work;
2496 }
2497
2498 /*
2499  * nv_tx_timeout: dev->tx_timeout function
2500  * Called with netif_tx_lock held.
2501  */
2502 static void nv_tx_timeout(struct net_device *dev)
2503 {
2504         struct fe_priv *np = netdev_priv(dev);
2505         u8 __iomem *base = get_hwbase(dev);
2506         u32 status;
2507         union ring_type put_tx;
2508         int saved_tx_limit;
2509
2510         if (np->msi_flags & NV_MSI_X_ENABLED)
2511                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2512         else
2513                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2514
2515         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
2516
2517         {
2518                 int i;
2519
2520                 printk(KERN_INFO "%s: Ring at %lx\n",
2521                        dev->name, (unsigned long)np->ring_addr);
2522                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
2523                 for (i = 0; i <= np->register_size; i += 32) {
2524                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2525                                         i,
2526                                         readl(base + i + 0), readl(base + i + 4),
2527                                         readl(base + i + 8), readl(base + i + 12),
2528                                         readl(base + i + 16), readl(base + i + 20),
2529                                         readl(base + i + 24), readl(base + i + 28));
2530                 }
2531                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
2532                 for (i = 0; i < np->tx_ring_size; i += 4) {
2533                         if (!nv_optimized(np)) {
2534                                 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2535                                        i,
2536                                        le32_to_cpu(np->tx_ring.orig[i].buf),
2537                                        le32_to_cpu(np->tx_ring.orig[i].flaglen),
2538                                        le32_to_cpu(np->tx_ring.orig[i+1].buf),
2539                                        le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2540                                        le32_to_cpu(np->tx_ring.orig[i+2].buf),
2541                                        le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2542                                        le32_to_cpu(np->tx_ring.orig[i+3].buf),
2543                                        le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2544                         } else {
2545                                 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2546                                        i,
2547                                        le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2548                                        le32_to_cpu(np->tx_ring.ex[i].buflow),
2549                                        le32_to_cpu(np->tx_ring.ex[i].flaglen),
2550                                        le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2551                                        le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2552                                        le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2553                                        le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2554                                        le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2555                                        le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2556                                        le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2557                                        le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2558                                        le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2559                         }
2560                 }
2561         }
2562
2563         spin_lock_irq(&np->lock);
2564
2565         /* 1) stop tx engine */
2566         nv_stop_tx(dev);
2567
2568         /* 2) complete any outstanding tx and do not give HW any limited tx pkts */
2569         saved_tx_limit = np->tx_limit;
2570         np->tx_limit = 0; /* prevent giving HW any limited pkts */
2571         np->tx_stop = 0;  /* prevent waking tx queue */
2572         if (!nv_optimized(np))
2573                 nv_tx_done(dev, np->tx_ring_size);
2574         else
2575                 nv_tx_done_optimized(dev, np->tx_ring_size);
2576
2577         /* save current HW postion */
2578         if (np->tx_change_owner)
2579                 put_tx.ex = np->tx_change_owner->first_tx_desc;
2580         else
2581                 put_tx = np->put_tx;
2582
2583         /* 3) clear all tx state */
2584         nv_drain_tx(dev);
2585         nv_init_tx(dev);
2586
2587         /* 4) restore state to current HW position */
2588         np->get_tx = np->put_tx = put_tx;
2589         np->tx_limit = saved_tx_limit;
2590
2591         /* 5) restart tx engine */
2592         nv_start_tx(dev);
2593         netif_wake_queue(dev);
2594         spin_unlock_irq(&np->lock);
2595 }
2596
2597 /*
2598  * Called when the nic notices a mismatch between the actual data len on the
2599  * wire and the len indicated in the 802 header
2600  */
2601 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2602 {
2603         int hdrlen;     /* length of the 802 header */
2604         int protolen;   /* length as stored in the proto field */
2605
2606         /* 1) calculate len according to header */
2607         if (((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2608                 protolen = ntohs(((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto);
2609                 hdrlen = VLAN_HLEN;
2610         } else {
2611                 protolen = ntohs(((struct ethhdr *)packet)->h_proto);
2612                 hdrlen = ETH_HLEN;
2613         }
2614         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
2615                                 dev->name, datalen, protolen, hdrlen);
2616         if (protolen > ETH_DATA_LEN)
2617                 return datalen; /* Value in proto field not a len, no checks possible */
2618
2619         protolen += hdrlen;
2620         /* consistency checks: */
2621         if (datalen > ETH_ZLEN) {
2622                 if (datalen >= protolen) {
2623                         /* more data on wire than in 802 header, trim of
2624                          * additional data.
2625                          */
2626                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2627                                         dev->name, protolen);
2628                         return protolen;
2629                 } else {
2630                         /* less data on wire than mentioned in header.
2631                          * Discard the packet.
2632                          */
2633                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
2634                                         dev->name);
2635                         return -1;
2636                 }
2637         } else {
2638                 /* short packet. Accept only if 802 values are also short */
2639                 if (protolen > ETH_ZLEN) {
2640                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
2641                                         dev->name);
2642                         return -1;
2643                 }
2644                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2645                                 dev->name, datalen);
2646                 return datalen;
2647         }
2648 }
2649
2650 static int nv_rx_process(struct net_device *dev, int limit)
2651 {
2652         struct fe_priv *np = netdev_priv(dev);
2653         u32 flags;
2654         int rx_work = 0;
2655         struct sk_buff *skb;
2656         int len;
2657
2658         while ((np->get_rx.orig != np->put_rx.orig) &&
2659               !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2660                 (rx_work < limit)) {
2661
2662                 dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
2663                                         dev->name, flags);
2664
2665                 /*
2666                  * the packet is for us - immediately tear down the pci mapping.
2667                  * TODO: check if a prefetch of the first cacheline improves
2668                  * the performance.
2669                  */
2670                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2671                                 np->get_rx_ctx->dma_len,
2672                                 PCI_DMA_FROMDEVICE);
2673                 skb = np->get_rx_ctx->skb;
2674                 np->get_rx_ctx->skb = NULL;
2675
2676                 {
2677                         int j;
2678                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).", flags);
2679                         for (j = 0; j < 64; j++) {
2680                                 if ((j%16) == 0)
2681                                         dprintk("\n%03x:", j);
2682                                 dprintk(" %02x", ((unsigned char *)skb->data)[j]);
2683                         }
2684                         dprintk("\n");
2685                 }
2686                 /* look at what we actually got: */
2687                 if (np->desc_ver == DESC_VER_1) {
2688                         if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2689                                 len = flags & LEN_MASK_V1;
2690                                 if (unlikely(flags & NV_RX_ERROR)) {
2691                                         if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
2692                                                 len = nv_getlen(dev, skb->data, len);
2693                                                 if (len < 0) {
2694                                                         dev->stats.rx_errors++;
2695                                                         dev_kfree_skb(skb);
2696                                                         goto next_pkt;
2697                                                 }
2698                                         }
2699                                         /* framing errors are soft errors */
2700                                         else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
2701                                                 if (flags & NV_RX_SUBSTRACT1)
2702                                                         len--;
2703                                         }
2704                                         /* the rest are hard errors */
2705                                         else {
2706                                                 if (flags & NV_RX_MISSEDFRAME)
2707                                                         dev->stats.rx_missed_errors++;
2708                                                 if (flags & NV_RX_CRCERR)
2709                                                         dev->stats.rx_crc_errors++;
2710                                                 if (flags & NV_RX_OVERFLOW)
2711                                                         dev->stats.rx_over_errors++;
2712                                                 dev->stats.rx_errors++;
2713                                                 dev_kfree_skb(skb);
2714                                                 goto next_pkt;
2715                                         }
2716                                 }
2717                         } else {
2718                                 dev_kfree_skb(skb);
2719                                 goto next_pkt;
2720                         }
2721                 } else {
2722                         if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2723                                 len = flags & LEN_MASK_V2;
2724                                 if (unlikely(flags & NV_RX2_ERROR)) {
2725                                         if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2726                                                 len = nv_getlen(dev, skb->data, len);
2727                                                 if (len < 0) {
2728                                                         dev->stats.rx_errors++;
2729                                                         dev_kfree_skb(skb);
2730                                                         goto next_pkt;
2731                                                 }
2732                                         }
2733                                         /* framing errors are soft errors */
2734                                         else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2735                                                 if (flags & NV_RX2_SUBSTRACT1)
2736                                                         len--;
2737                                         }
2738                                         /* the rest are hard errors */
2739                                         else {
2740                                                 if (flags & NV_RX2_CRCERR)
2741                                                         dev->stats.rx_crc_errors++;
2742                                                 if (flags & NV_RX2_OVERFLOW)
2743                                                         dev->stats.rx_over_errors++;
2744                                                 dev->stats.rx_errors++;
2745                                                 dev_kfree_skb(skb);
2746                                                 goto next_pkt;
2747                                         }
2748                                 }
2749                                 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2750                                     ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2751                                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2752                         } else {
2753                                 dev_kfree_skb(skb);
2754                                 goto next_pkt;
2755                         }
2756                 }
2757                 /* got a valid packet - forward it to the network core */
2758                 skb_put(skb, len);
2759                 skb->protocol = eth_type_trans(skb, dev);
2760                 dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2761                                         dev->name, len, skb->protocol);
2762                 napi_gro_receive(&np->napi, skb);
2763                 dev->stats.rx_packets++;
2764                 dev->stats.rx_bytes += len;
2765 next_pkt:
2766                 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2767                         np->get_rx.orig = np->first_rx.orig;
2768                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2769                         np->get_rx_ctx = np->first_rx_ctx;
2770
2771                 rx_work++;
2772         }
2773
2774         return rx_work;
2775 }
2776
2777 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2778 {
2779         struct fe_priv *np = netdev_priv(dev);
2780         u32 flags;
2781         u32 vlanflags = 0;
2782         int rx_work = 0;
2783         struct sk_buff *skb;
2784         int len;
2785
2786         while ((np->get_rx.ex != np->put_rx.ex) &&
2787               !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2788               (rx_work < limit)) {
2789
2790                 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n",
2791                                         dev->name, flags);
2792
2793                 /*
2794                  * the packet is for us - immediately tear down the pci mapping.
2795                  * TODO: check if a prefetch of the first cacheline improves
2796                  * the performance.
2797                  */
2798                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2799                                 np->get_rx_ctx->dma_len,
2800                                 PCI_DMA_FROMDEVICE);
2801                 skb = np->get_rx_ctx->skb;
2802                 np->get_rx_ctx->skb = NULL;
2803
2804                 {
2805                         int j;
2806                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).", flags);
2807                         for (j = 0; j < 64; j++) {
2808                                 if ((j%16) == 0)
2809                                         dprintk("\n%03x:", j);
2810                                 dprintk(" %02x", ((unsigned char *)skb->data)[j]);
2811                         }
2812                         dprintk("\n");
2813                 }
2814                 /* look at what we actually got: */
2815                 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2816                         len = flags & LEN_MASK_V2;
2817                         if (unlikely(flags & NV_RX2_ERROR)) {
2818                                 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2819                                         len = nv_getlen(dev, skb->data, len);
2820                                         if (len < 0) {
2821                                                 dev_kfree_skb(skb);
2822                                                 goto next_pkt;
2823                                         }
2824                                 }
2825                                 /* framing errors are soft errors */
2826                                 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2827                                         if (flags & NV_RX2_SUBSTRACT1)
2828                                                 len--;
2829                                 }
2830                                 /* the rest are hard errors */
2831                                 else {
2832                                         dev_kfree_skb(skb);
2833                                         goto next_pkt;
2834                                 }
2835                         }
2836
2837                         if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2838                             ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2839                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2840
2841                         /* got a valid packet - forward it to the network core */
2842                         skb_put(skb, len);
2843                         skb->protocol = eth_type_trans(skb, dev);
2844                         prefetch(skb->data);
2845
2846                         dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
2847                                 dev->name, len, skb->protocol);
2848
2849                         if (likely(!np->vlangrp)) {
2850                                 napi_gro_receive(&np->napi, skb);
2851                         } else {
2852                                 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2853                                 if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2854                                         vlan_gro_receive(&np->napi, np->vlangrp,
2855                                                          vlanflags & NV_RX3_VLAN_TAG_MASK, skb);
2856                                 } else {
2857                                         napi_gro_receive(&np->napi, skb);
2858                                 }
2859                         }
2860
2861                         dev->stats.rx_packets++;
2862                         dev->stats.rx_bytes += len;
2863                 } else {
2864                         dev_kfree_skb(skb);
2865                 }
2866 next_pkt:
2867                 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2868                         np->get_rx.ex = np->first_rx.ex;
2869                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2870                         np->get_rx_ctx = np->first_rx_ctx;
2871
2872                 rx_work++;
2873         }
2874
2875         return rx_work;
2876 }
2877
2878 static void set_bufsize(struct net_device *dev)
2879 {
2880         struct fe_priv *np = netdev_priv(dev);
2881
2882         if (dev->mtu <= ETH_DATA_LEN)
2883                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2884         else
2885                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2886 }
2887
2888 /*
2889  * nv_change_mtu: dev->change_mtu function
2890  * Called with dev_base_lock held for read.
2891  */
2892 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2893 {
2894         struct fe_priv *np = netdev_priv(dev);
2895         int old_mtu;
2896
2897         if (new_mtu < 64 || new_mtu > np->pkt_limit)
2898                 return -EINVAL;
2899
2900         old_mtu = dev->mtu;
2901         dev->mtu = new_mtu;
2902
2903         /* return early if the buffer sizes will not change */
2904         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2905                 return 0;
2906         if (old_mtu == new_mtu)
2907                 return 0;
2908
2909         /* synchronized against open : rtnl_lock() held by caller */
2910         if (netif_running(dev)) {
2911                 u8 __iomem *base = get_hwbase(dev);
2912                 /*
2913                  * It seems that the nic preloads valid ring entries into an
2914                  * internal buffer. The procedure for flushing everything is
2915                  * guessed, there is probably a simpler approach.
2916                  * Changing the MTU is a rare event, it shouldn't matter.
2917                  */
2918                 nv_disable_irq(dev);
2919                 nv_napi_disable(dev);
2920                 netif_tx_lock_bh(dev);
2921                 netif_addr_lock(dev);
2922                 spin_lock(&np->lock);
2923                 /* stop engines */
2924                 nv_stop_rxtx(dev);
2925                 nv_txrx_reset(dev);
2926                 /* drain rx queue */
2927                 nv_drain_rxtx(dev);
2928                 /* reinit driver view of the rx queue */
2929                 set_bufsize(dev);
2930                 if (nv_init_ring(dev)) {
2931                         if (!np->in_shutdown)
2932                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2933                 }
2934                 /* reinit nic view of the rx queue */
2935                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2936                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2937                 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2938                         base + NvRegRingSizes);
2939                 pci_push(base);
2940                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2941                 pci_push(base);
2942
2943                 /* restart rx engine */
2944                 nv_start_rxtx(dev);
2945                 spin_unlock(&np->lock);
2946                 netif_addr_unlock(dev);
2947                 netif_tx_unlock_bh(dev);
2948                 nv_napi_enable(dev);
2949                 nv_enable_irq(dev);
2950         }
2951         return 0;
2952 }
2953
2954 static void nv_copy_mac_to_hw(struct net_device *dev)
2955 {
2956         u8 __iomem *base = get_hwbase(dev);
2957         u32 mac[2];
2958
2959         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2960                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2961         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2962
2963         writel(mac[0], base + NvRegMacAddrA);
2964         writel(mac[1], base + NvRegMacAddrB);
2965 }
2966
2967 /*
2968  * nv_set_mac_address: dev->set_mac_address function
2969  * Called with rtnl_lock() held.
2970  */
2971 static int nv_set_mac_address(struct net_device *dev, void *addr)
2972 {
2973         struct fe_priv *np = netdev_priv(dev);
2974         struct sockaddr *macaddr = (struct sockaddr *)addr;
2975
2976         if (!is_valid_ether_addr(macaddr->sa_data))
2977                 return -EADDRNOTAVAIL;
2978
2979         /* synchronized against open : rtnl_lock() held by caller */
2980         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2981
2982         if (netif_running(dev)) {
2983                 netif_tx_lock_bh(dev);
2984                 netif_addr_lock(dev);
2985                 spin_lock_irq(&np->lock);
2986
2987                 /* stop rx engine */
2988                 nv_stop_rx(dev);
2989
2990                 /* set mac address */
2991                 nv_copy_mac_to_hw(dev);
2992
2993                 /* restart rx engine */
2994                 nv_start_rx(dev);
2995                 spin_unlock_irq(&np->lock);
2996                 netif_addr_unlock(dev);
2997                 netif_tx_unlock_bh(dev);
2998         } else {
2999                 nv_copy_mac_to_hw(dev);
3000         }
3001         return 0;
3002 }
3003
3004 /*
3005  * nv_set_multicast: dev->set_multicast function
3006  * Called with netif_tx_lock held.
3007  */
3008 static void nv_set_multicast(struct net_device *dev)
3009 {
3010         struct fe_priv *np = netdev_priv(dev);
3011         u8 __iomem *base = get_hwbase(dev);
3012         u32 addr[2];
3013         u32 mask[2];
3014         u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
3015
3016         memset(addr, 0, sizeof(addr));
3017         memset(mask, 0, sizeof(mask));
3018
3019         if (dev->flags & IFF_PROMISC) {
3020                 pff |= NVREG_PFF_PROMISC;
3021         } else {
3022                 pff |= NVREG_PFF_MYADDR;
3023
3024                 if (dev->flags & IFF_ALLMULTI || !netdev_mc_empty(dev)) {
3025                         u32 alwaysOff[2];
3026                         u32 alwaysOn[2];
3027
3028                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
3029                         if (dev->flags & IFF_ALLMULTI) {
3030                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
3031                         } else {
3032                                 struct netdev_hw_addr *ha;
3033
3034                                 netdev_for_each_mc_addr(ha, dev) {
3035                                         unsigned char *addr = ha->addr;
3036                                         u32 a, b;
3037
3038                                         a = le32_to_cpu(*(__le32 *) addr);
3039                                         b = le16_to_cpu(*(__le16 *) (&addr[4]));
3040                                         alwaysOn[0] &= a;
3041                                         alwaysOff[0] &= ~a;
3042                                         alwaysOn[1] &= b;
3043                                         alwaysOff[1] &= ~b;
3044                                 }
3045                         }
3046                         addr[0] = alwaysOn[0];
3047                         addr[1] = alwaysOn[1];
3048                         mask[0] = alwaysOn[0] | alwaysOff[0];
3049                         mask[1] = alwaysOn[1] | alwaysOff[1];
3050                 } else {
3051                         mask[0] = NVREG_MCASTMASKA_NONE;
3052                         mask[1] = NVREG_MCASTMASKB_NONE;
3053                 }
3054         }
3055         addr[0] |= NVREG_MCASTADDRA_FORCE;
3056         pff |= NVREG_PFF_ALWAYS;
3057         spin_lock_irq(&np->lock);
3058         nv_stop_rx(dev);
3059         writel(addr[0], base + NvRegMulticastAddrA);
3060         writel(addr[1], base + NvRegMulticastAddrB);
3061         writel(mask[0], base + NvRegMulticastMaskA);
3062         writel(mask[1], base + NvRegMulticastMaskB);
3063         writel(pff, base + NvRegPacketFilterFlags);
3064         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
3065                 dev->name);
3066         nv_start_rx(dev);
3067         spin_unlock_irq(&np->lock);
3068 }
3069
3070 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
3071 {
3072         struct fe_priv *np = netdev_priv(dev);
3073         u8 __iomem *base = get_hwbase(dev);
3074
3075         np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
3076
3077         if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
3078                 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
3079                 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
3080                         writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
3081                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3082                 } else {
3083                         writel(pff, base + NvRegPacketFilterFlags);
3084                 }
3085         }
3086         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
3087                 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
3088                 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
3089                         u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
3090                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
3091                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
3092                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
3093                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
3094                                 /* limit the number of tx pause frames to a default of 8 */
3095                                 writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
3096                         }
3097                         writel(pause_enable,  base + NvRegTxPauseFrame);
3098                         writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3099                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3100                 } else {
3101                         writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
3102                         writel(regmisc, base + NvRegMisc1);
3103                 }
3104         }
3105 }
3106
3107 /**
3108  * nv_update_linkspeed: Setup the MAC according to the link partner
3109  * @dev: Network device to be configured
3110  *
3111  * The function queries the PHY and checks if there is a link partner.
3112  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3113  * set to 10 MBit HD.
3114  *
3115  * The function returns 0 if there is no link partner and 1 if there is
3116  * a good link partner.
3117  */
3118 static int nv_update_linkspeed(struct net_device *dev)
3119 {
3120         struct fe_priv *np = netdev_priv(dev);
3121         u8 __iomem *base = get_hwbase(dev);
3122         int adv = 0;
3123         int lpa = 0;
3124         int adv_lpa, adv_pause, lpa_pause;
3125         int newls = np->linkspeed;
3126         int newdup = np->duplex;
3127         int mii_status;
3128         int retval = 0;
3129         u32 control_1000, status_1000, phyreg, pause_flags, txreg;
3130         u32 txrxFlags = 0;
3131         u32 phy_exp;
3132
3133         /* BMSR_LSTATUS is latched, read it twice:
3134          * we want the current value.
3135          */
3136         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3137         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3138
3139         if (!(mii_status & BMSR_LSTATUS)) {
3140                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
3141                                 dev->name);
3142                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3143                 newdup = 0;
3144                 retval = 0;
3145                 goto set_speed;
3146         }
3147
3148         if (np->autoneg == 0) {
3149                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
3150                                 dev->name, np->fixed_mode);
3151                 if (np->fixed_mode & LPA_100FULL) {
3152                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3153                         newdup = 1;
3154                 } else if (np->fixed_mode & LPA_100HALF) {
3155                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3156                         newdup = 0;
3157                 } else if (np->fixed_mode & LPA_10FULL) {
3158                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3159                         newdup = 1;
3160                 } else {
3161                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3162                         newdup = 0;
3163                 }
3164                 retval = 1;
3165                 goto set_speed;
3166         }
3167         /* check auto negotiation is complete */
3168         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3169                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3170                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3171                 newdup = 0;
3172                 retval = 0;
3173                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
3174                 goto set_speed;
3175         }
3176
3177         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3178         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3179         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
3180                                 dev->name, adv, lpa);
3181
3182         retval = 1;
3183         if (np->gigabit == PHY_GIGABIT) {
3184                 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3185                 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
3186
3187                 if ((control_1000 & ADVERTISE_1000FULL) &&
3188                         (status_1000 & LPA_1000FULL)) {
3189                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
3190                                 dev->name);
3191                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3192                         newdup = 1;
3193                         goto set_speed;
3194                 }
3195         }
3196
3197         /* FIXME: handle parallel detection properly */
3198         adv_lpa = lpa & adv;
3199         if (adv_lpa & LPA_100FULL) {
3200                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3201                 newdup = 1;
3202         } else if (adv_lpa & LPA_100HALF) {
3203                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3204                 newdup = 0;
3205         } else if (adv_lpa & LPA_10FULL) {
3206                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3207                 newdup = 1;
3208         } else if (adv_lpa & LPA_10HALF) {
3209                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3210                 newdup = 0;
3211         } else {
3212                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
3213                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3214                 newdup = 0;
3215         }
3216
3217 set_speed:
3218         if (np->duplex == newdup && np->linkspeed == newls)
3219                 return retval;
3220
3221         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
3222                         dev->name, np->linkspeed, np->duplex, newls, newdup);
3223
3224         np->duplex = newdup;
3225         np->linkspeed = newls;
3226
3227         /* The transmitter and receiver must be restarted for safe update */
3228         if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3229                 txrxFlags |= NV_RESTART_TX;
3230                 nv_stop_tx(dev);
3231         }
3232         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3233                 txrxFlags |= NV_RESTART_RX;
3234                 nv_stop_rx(dev);
3235         }
3236
3237         if (np->gigabit == PHY_GIGABIT) {
3238                 phyreg = readl(base + NvRegSlotTime);
3239                 phyreg &= ~(0x3FF00);
3240                 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3241                     ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3242                         phyreg |= NVREG_SLOTTIME_10_100_FULL;
3243                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3244                         phyreg |= NVREG_SLOTTIME_1000_FULL;
3245                 writel(phyreg, base + NvRegSlotTime);
3246         }
3247
3248         phyreg = readl(base + NvRegPhyInterface);
3249         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3250         if (np->duplex == 0)
3251                 phyreg |= PHY_HALF;
3252         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3253                 phyreg |= PHY_100;
3254         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3255                 phyreg |= PHY_1000;
3256         writel(phyreg, base + NvRegPhyInterface);
3257
3258         phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
3259         if (phyreg & PHY_RGMII) {
3260                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
3261                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3262                 } else {
3263                         if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3264                                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3265                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3266                                 else
3267                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3268                         } else {
3269                                 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3270                         }
3271                 }
3272         } else {
3273                 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3274                         txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3275                 else
3276                         txreg = NVREG_TX_DEFERRAL_DEFAULT;
3277         }
3278         writel(txreg, base + NvRegTxDeferral);
3279
3280         if (np->desc_ver == DESC_VER_1) {
3281                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3282         } else {
3283                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3284                         txreg = NVREG_TX_WM_DESC2_3_1000;
3285                 else
3286                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3287         }
3288         writel(txreg, base + NvRegTxWatermark);
3289
3290         writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
3291                 base + NvRegMisc1);
3292         pci_push(base);
3293         writel(np->linkspeed, base + NvRegLinkSpeed);
3294         pci_push(base);
3295
3296         pause_flags = 0;
3297         /* setup pause frame */
3298         if (np->duplex != 0) {
3299                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3300                         adv_pause = adv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3301                         lpa_pause = lpa & (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
3302
3303                         switch (adv_pause) {
3304                         case ADVERTISE_PAUSE_CAP:
3305                                 if (lpa_pause & LPA_PAUSE_CAP) {
3306                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3307                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3308                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3309                                 }
3310                                 break;
3311                         case ADVERTISE_PAUSE_ASYM:
3312                                 if (lpa_pause == (LPA_PAUSE_CAP | LPA_PAUSE_ASYM))
3313                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3314                                 break;
3315                         case ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM:
3316                                 if (lpa_pause & LPA_PAUSE_CAP) {
3317                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
3318                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3319                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3320                                 }
3321                                 if (lpa_pause == LPA_PAUSE_ASYM)
3322                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3323                                 break;
3324                         }
3325                 } else {
3326                         pause_flags = np->pause_flags;
3327                 }
3328         }
3329         nv_update_pause(dev, pause_flags);
3330
3331         if (txrxFlags & NV_RESTART_TX)
3332                 nv_start_tx(dev);
3333         if (txrxFlags & NV_RESTART_RX)
3334                 nv_start_rx(dev);
3335
3336         return retval;
3337 }
3338
3339 static void nv_linkchange(struct net_device *dev)
3340 {
3341         if (nv_update_linkspeed(dev)) {
3342                 if (!netif_carrier_ok(dev)) {
3343                         netif_carrier_on(dev);
3344                         printk(KERN_INFO "%s: link up.\n", dev->name);
3345                         nv_txrx_gate(dev, false);
3346                         nv_start_rx(dev);
3347                 }
3348         } else {
3349                 if (netif_carrier_ok(dev)) {
3350                         netif_carrier_off(dev);
3351                         printk(KERN_INFO "%s: link down.\n", dev->name);
3352                         nv_txrx_gate(dev, true);
3353                         nv_stop_rx(dev);
3354                 }
3355         }
3356 }
3357
3358 static void nv_link_irq(struct net_device *dev)
3359 {
3360         u8 __iomem *base = get_hwbase(dev);
3361         u32 miistat;
3362
3363         miistat = readl(base + NvRegMIIStatus);
3364         writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3365         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
3366
3367         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3368                 nv_linkchange(dev);
3369         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
3370 }
3371
3372 static void nv_msi_workaround(struct fe_priv *np)
3373 {
3374
3375         /* Need to toggle the msi irq mask within the ethernet device,
3376          * otherwise, future interrupts will not be detected.
3377          */
3378         if (np->msi_flags & NV_MSI_ENABLED) {
3379                 u8 __iomem *base = np->base;
3380
3381                 writel(0, base + NvRegMSIIrqMask);
3382                 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3383         }
3384 }
3385
3386 static inline int nv_change_interrupt_mode(struct net_device *dev, int total_work)
3387 {
3388         struct fe_priv *np = netdev_priv(dev);
3389
3390         if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC) {
3391                 if (total_work > NV_DYNAMIC_THRESHOLD) {
3392                         /* transition to poll based interrupts */
3393                         np->quiet_count = 0;
3394                         if (np->irqmask != NVREG_IRQMASK_CPU) {
3395                                 np->irqmask = NVREG_IRQMASK_CPU;
3396                                 return 1;
3397                         }
3398                 } else {
3399                         if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) {
3400                                 np->quiet_count++;
3401                         } else {
3402                                 /* reached a period of low activity, switch
3403                                    to per tx/rx packet interrupts */
3404                                 if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) {
3405                                         np->irqmask = NVREG_IRQMASK_THROUGHPUT;
3406                                         return 1;
3407                                 }
3408                         }
3409                 }
3410         }
3411         return 0;
3412 }
3413
3414 static irqreturn_t nv_nic_irq(int foo, void *data)
3415 {
3416         struct net_device *dev = (struct net_device *) data;
3417         struct fe_priv *np = netdev_priv(dev);
3418         u8 __iomem *base = get_hwbase(dev);
3419
3420         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
3421
3422         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3423                 np->events = readl(base + NvRegIrqStatus);
3424                 writel(np->events, base + NvRegIrqStatus);
3425         } else {
3426                 np->events = readl(base + NvRegMSIXIrqStatus);
3427                 writel(np->events, base + NvRegMSIXIrqStatus);
3428         }
3429         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, np->events);
3430         if (!(np->events & np->irqmask))
3431                 return IRQ_NONE;
3432
3433         nv_msi_workaround(np);
3434
3435         if (napi_schedule_prep(&np->napi)) {
3436                 /*
3437                  * Disable further irq's (msix not enabled with napi)
3438                  */
3439                 writel(0, base + NvRegIrqMask);
3440                 __napi_schedule(&np->napi);
3441         }
3442
3443         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
3444
3445         return IRQ_HANDLED;
3446 }
3447
3448 /**
3449  * All _optimized functions are used to help increase performance
3450  * (reduce CPU and increase throughput). They use descripter version 3,
3451  * compiler directives, and reduce memory accesses.
3452  */
3453 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3454 {
3455         struct net_device *dev = (struct net_device *) data;
3456         struct fe_priv *np = netdev_priv(dev);
3457         u8 __iomem *base = get_hwbase(dev);
3458
3459         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name);
3460
3461         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3462                 np->events = readl(base + NvRegIrqStatus);
3463                 writel(np->events, base + NvRegIrqStatus);
3464         } else {
3465                 np->events = readl(base + NvRegMSIXIrqStatus);
3466                 writel(np->events, base + NvRegMSIXIrqStatus);
3467         }
3468         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, np->events);
3469         if (!(np->events & np->irqmask))
3470                 return IRQ_NONE;
3471
3472         nv_msi_workaround(np);
3473
3474         if (napi_schedule_prep(&np->napi)) {
3475                 /*
3476                  * Disable further irq's (msix not enabled with napi)
3477                  */
3478                 writel(0, base + NvRegIrqMask);
3479                 __napi_schedule(&np->napi);
3480         }
3481         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name);
3482
3483         return IRQ_HANDLED;
3484 }
3485
3486 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3487 {
3488         struct net_device *dev = (struct net_device *) data;
3489         struct fe_priv *np = netdev_priv(dev);
3490         u8 __iomem *base = get_hwbase(dev);
3491         u32 events;
3492         int i;
3493         unsigned long flags;
3494
3495         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
3496
3497         for (i = 0;; i++) {
3498                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3499                 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
3500                 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
3501                 if (!(events & np->irqmask))
3502                         break;
3503
3504                 spin_lock_irqsave(&np->lock, flags);
3505                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3506                 spin_unlock_irqrestore(&np->lock, flags);
3507
3508                 if (unlikely(i > max_interrupt_work)) {
3509                         spin_lock_irqsave(&np->lock, flags);
3510                         /* disable interrupts on the nic */
3511                         writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3512                         pci_push(base);
3513
3514                         if (!np->in_shutdown) {
3515                                 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3516                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3517                         }
3518                         spin_unlock_irqrestore(&np->lock, flags);
3519                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
3520                         break;
3521                 }
3522
3523         }
3524         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
3525
3526         return IRQ_RETVAL(i);
3527 }
3528
3529 static int nv_napi_poll(struct napi_struct *napi, int budget)
3530 {
3531         struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3532         struct net_device *dev = np->dev;
3533         u8 __iomem *base = get_hwbase(dev);
3534         unsigned long flags;
3535         int retcode;
3536         int rx_count, tx_work = 0, rx_work = 0;
3537
3538         do {
3539                 if (!nv_optimized(np)) {
3540                         spin_lock_irqsave(&np->lock, flags);
3541                         tx_work += nv_tx_done(dev, np->tx_ring_size);
3542                         spin_unlock_irqrestore(&np->lock, flags);
3543
3544                         rx_count = nv_rx_process(dev, budget - rx_work);
3545                         retcode = nv_alloc_rx(dev);
3546                 } else {
3547                         spin_lock_irqsave(&np->lock, flags);
3548                         tx_work += nv_tx_done_optimized(dev, np->tx_ring_size);
3549                         spin_unlock_irqrestore(&np->lock, flags);
3550
3551                         rx_count = nv_rx_process_optimized(dev,
3552                             budget - rx_work);
3553                         retcode = nv_alloc_rx_optimized(dev);
3554                 }
3555         } while (retcode == 0 &&
3556                  rx_count > 0 && (rx_work += rx_count) < budget);
3557
3558         if (retcode) {
3559                 spin_lock_irqsave(&np->lock, flags);
3560                 if (!np->in_shutdown)
3561                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3562                 spin_unlock_irqrestore(&np->lock, flags);
3563         }
3564
3565         nv_change_interrupt_mode(dev, tx_work + rx_work);
3566
3567         if (unlikely(np->events & NVREG_IRQ_LINK)) {
3568                 spin_lock_irqsave(&np->lock, flags);
3569                 nv_link_irq(dev);
3570                 spin_unlock_irqrestore(&np->lock, flags);
3571         }
3572         if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3573                 spin_lock_irqsave(&np->lock, flags);
3574                 nv_linkchange(dev);
3575                 spin_unlock_irqrestore(&np->lock, flags);
3576                 np->link_timeout = jiffies + LINK_TIMEOUT;
3577         }
3578         if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3579                 spin_lock_irqsave(&np->lock, flags);
3580                 if (!np->in_shutdown) {
3581                         np->nic_poll_irq = np->irqmask;
3582                         np->recover_error = 1;
3583                         mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3584                 }
3585                 spin_unlock_irqrestore(&np->lock, flags);
3586                 napi_complete(napi);
3587                 return rx_work;
3588         }
3589
3590         if (rx_work < budget) {
3591                 /* re-enable interrupts
3592                    (msix not enabled in napi) */
3593                 napi_complete(napi);
3594
3595                 writel(np->irqmask, base + NvRegIrqMask);
3596         }
3597         return rx_work;
3598 }
3599
3600 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3601 {
3602         struct net_device *dev = (struct net_device *) data;
3603         struct fe_priv *np = netdev_priv(dev);
3604         u8 __iomem *base = get_hwbase(dev);
3605         u32 events;
3606         int i;
3607         unsigned long flags;
3608
3609         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
3610
3611         for (i = 0;; i++) {
3612                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3613                 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3614                 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
3615                 if (!(events & np->irqmask))
3616                         break;
3617
3618                 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3619                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3620                                 spin_lock_irqsave(&np->lock, flags);
3621                                 if (!np->in_shutdown)
3622                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3623                                 spin_unlock_irqrestore(&np->lock, flags);
3624                         }
3625                 }
3626
3627                 if (unlikely(i > max_interrupt_work)) {
3628                         spin_lock_irqsave(&np->lock, flags);
3629                         /* disable interrupts on the nic */
3630                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3631                         pci_push(base);
3632
3633                         if (!np->in_shutdown) {
3634                                 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3635                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3636                         }
3637                         spin_unlock_irqrestore(&np->lock, flags);
3638                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
3639                         break;
3640                 }
3641         }
3642         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
3643
3644         return IRQ_RETVAL(i);
3645 }
3646
3647 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3648 {
3649         struct net_device *dev = (struct net_device *) data;
3650         struct fe_priv *np = netdev_priv(dev);
3651         u8 __iomem *base = get_hwbase(dev);
3652         u32 events;
3653         int i;
3654         unsigned long flags;
3655
3656         dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
3657
3658         for (i = 0;; i++) {
3659                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3660                 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
3661                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3662                 if (!(events & np->irqmask))
3663                         break;
3664
3665                 /* check tx in case we reached max loop limit in tx isr */
3666                 spin_lock_irqsave(&np->lock, flags);
3667                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3668                 spin_unlock_irqrestore(&np->lock, flags);
3669
3670                 if (events & NVREG_IRQ_LINK) {
3671                         spin_lock_irqsave(&np->lock, flags);
3672                         nv_link_irq(dev);
3673                         spin_unlock_irqrestore(&np->lock, flags);
3674                 }
3675                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3676                         spin_lock_irqsave(&np->lock, flags);
3677                         nv_linkchange(dev);
3678                         spin_unlock_irqrestore(&np->lock, flags);
3679                         np->link_timeout = jiffies + LINK_TIMEOUT;
3680                 }
3681                 if (events & NVREG_IRQ_RECOVER_ERROR) {
3682                         spin_lock_irq(&np->lock);
3683                         /* disable interrupts on the nic */
3684                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3685                         pci_push(base);
3686
3687                         if (!np->in_shutdown) {
3688                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3689                                 np->recover_error = 1;
3690                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3691                         }
3692                         spin_unlock_irq(&np->lock);
3693                         break;
3694                 }
3695                 if (unlikely(i > max_interrupt_work)) {
3696                         spin_lock_irqsave(&np->lock, flags);
3697                         /* disable interrupts on the nic */
3698                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3699                         pci_push(base);
3700
3701                         if (!np->in_shutdown) {
3702                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3703                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3704                         }
3705                         spin_unlock_irqrestore(&np->lock, flags);
3706                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
3707                         break;
3708                 }
3709
3710         }
3711         dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
3712
3713         return IRQ_RETVAL(i);
3714 }
3715
3716 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3717 {
3718         struct net_device *dev = (struct net_device *) data;
3719         struct fe_priv *np = netdev_priv(dev);
3720         u8 __iomem *base = get_hwbase(dev);
3721         u32 events;
3722
3723         dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
3724
3725         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3726                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3727                 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3728         } else {
3729                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3730                 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3731         }
3732         pci_push(base);
3733         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3734         if (!(events & NVREG_IRQ_TIMER))
3735                 return IRQ_RETVAL(0);
3736
3737         nv_msi_workaround(np);
3738
3739         spin_lock(&np->lock);
3740         np->intr_test = 1;
3741         spin_unlock(&np->lock);
3742
3743         dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
3744
3745         return IRQ_RETVAL(1);
3746 }
3747
3748 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3749 {
3750         u8 __iomem *base = get_hwbase(dev);
3751         int i;
3752         u32 msixmap = 0;
3753
3754         /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3755          * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3756          * the remaining 8 interrupts.
3757          */
3758         for (i = 0; i < 8; i++) {
3759                 if ((irqmask >> i) & 0x1)
3760                         msixmap |= vector << (i << 2);
3761         }
3762         writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3763
3764         msixmap = 0;
3765         for (i = 0; i < 8; i++) {
3766                 if ((irqmask >> (i + 8)) & 0x1)
3767                         msixmap |= vector << (i << 2);
3768         }
3769         writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3770 }
3771
3772 static int nv_request_irq(struct net_device *dev, int intr_test)
3773 {
3774         struct fe_priv *np = get_nvpriv(dev);
3775         u8 __iomem *base = get_hwbase(dev);
3776         int ret = 1;
3777         int i;
3778         irqreturn_t (*handler)(int foo, void *data);
3779
3780         if (intr_test) {
3781                 handler = nv_nic_irq_test;
3782         } else {
3783                 if (nv_optimized(np))
3784                         handler = nv_nic_irq_optimized;
3785                 else
3786                         handler = nv_nic_irq;
3787         }
3788
3789         if (np->msi_flags & NV_MSI_X_CAPABLE) {
3790                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
3791                         np->msi_x_entry[i].entry = i;
3792                 ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK));
3793                 if (ret == 0) {
3794                         np->msi_flags |= NV_MSI_X_ENABLED;
3795                         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3796                                 /* Request irq for rx handling */
3797                                 sprintf(np->name_rx, "%s-rx", dev->name);
3798                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
3799                                                 nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) {
3800                                         printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
3801                                         pci_disable_msix(np->pci_dev);
3802                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3803                                         goto out_err;
3804                                 }
3805                                 /* Request irq for tx handling */
3806                                 sprintf(np->name_tx, "%s-tx", dev->name);
3807                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
3808                                                 nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) {
3809                                         printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
3810                                         pci_disable_msix(np->pci_dev);
3811                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3812                                         goto out_free_rx;
3813                                 }
3814                                 /* Request irq for link and timer handling */
3815                                 sprintf(np->name_other, "%s-other", dev->name);
3816                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
3817                                                 nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) {
3818                                         printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
3819                                         pci_disable_msix(np->pci_dev);
3820                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3821                                         goto out_free_tx;
3822                                 }
3823                                 /* map interrupts to their respective vector */
3824                                 writel(0, base + NvRegMSIXMap0);
3825                                 writel(0, base + NvRegMSIXMap1);
3826                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3827                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3828                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3829                         } else {
3830                                 /* Request irq for all interrupts */
3831                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
3832                                         printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3833                                         pci_disable_msix(np->pci_dev);
3834                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3835                                         goto out_err;
3836                                 }
3837
3838                                 /* map interrupts to vector 0 */
3839                                 writel(0, base + NvRegMSIXMap0);
3840                                 writel(0, base + NvRegMSIXMap1);
3841                         }
3842                 }
3843         }
3844         if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
3845                 ret = pci_enable_msi(np->pci_dev);
3846                 if (ret == 0) {
3847                         np->msi_flags |= NV_MSI_ENABLED;
3848                         dev->irq = np->pci_dev->irq;
3849                         if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
3850                                 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3851                                 pci_disable_msi(np->pci_dev);
3852                                 np->msi_flags &= ~NV_MSI_ENABLED;
3853                                 dev->irq = np->pci_dev->irq;
3854                                 goto out_err;
3855                         }
3856
3857                         /* map interrupts to vector 0 */
3858                         writel(0, base + NvRegMSIMap0);
3859                         writel(0, base + NvRegMSIMap1);
3860                         /* enable msi vector 0 */
3861                         writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3862                 }
3863         }
3864         if (ret != 0) {
3865                 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
3866                         goto out_err;
3867
3868         }
3869
3870         return 0;
3871 out_free_tx:
3872         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3873 out_free_rx:
3874         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3875 out_err:
3876         return 1;
3877 }
3878
3879 static void nv_free_irq(struct net_device *dev)
3880 {
3881         struct fe_priv *np = get_nvpriv(dev);
3882         int i;
3883
3884         if (np->msi_flags & NV_MSI_X_ENABLED) {
3885                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
3886                         free_irq(np->msi_x_entry[i].vector, dev);
3887                 pci_disable_msix(np->pci_dev);
3888                 np->msi_flags &= ~NV_MSI_X_ENABLED;
3889         } else {
3890                 free_irq(np->pci_dev->irq, dev);
3891                 if (np->msi_flags & NV_MSI_ENABLED) {
3892                         pci_disable_msi(np->pci_dev);
3893                         np->msi_flags &= ~NV_MSI_ENABLED;
3894                 }
3895         }
3896 }
3897
3898 static void nv_do_nic_poll(unsigned long data)
3899 {
3900         struct net_device *dev = (struct net_device *) data;
3901         struct fe_priv *np = netdev_priv(dev);
3902         u8 __iomem *base = get_hwbase(dev);
3903         u32 mask = 0;
3904
3905         /*
3906          * First disable irq(s) and then
3907          * reenable interrupts on the nic, we have to do this before calling
3908          * nv_nic_irq because that may decide to do otherwise
3909          */
3910
3911         if (!using_multi_irqs(dev)) {
3912                 if (np->msi_flags & NV_MSI_X_ENABLED)
3913                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3914                 else
3915                         disable_irq_lockdep(np->pci_dev->irq);
3916                 mask = np->irqmask;
3917         } else {
3918                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3919                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3920                         mask |= NVREG_IRQ_RX_ALL;
3921                 }
3922                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3923                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3924                         mask |= NVREG_IRQ_TX_ALL;
3925                 }
3926                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3927                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3928                         mask |= NVREG_IRQ_OTHER;
3929                 }
3930         }
3931         /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
3932
3933         if (np->recover_error) {
3934                 np->recover_error = 0;
3935                 printk(KERN_INFO "%s: MAC in recoverable error state\n", dev->name);
3936                 if (netif_running(dev)) {
3937                         netif_tx_lock_bh(dev);
3938                         netif_addr_lock(dev);
3939                         spin_lock(&np->lock);
3940                         /* stop engines */
3941                         nv_stop_rxtx(dev);
3942                         if (np->driver_data & DEV_HAS_POWER_CNTRL)
3943                                 nv_mac_reset(dev);
3944                         nv_txrx_reset(dev);
3945                         /* drain rx queue */
3946                         nv_drain_rxtx(dev);
3947                         /* reinit driver view of the rx queue */
3948                         set_bufsize(dev);
3949                         if (nv_init_ring(dev)) {
3950                                 if (!np->in_shutdown)
3951                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3952                         }
3953                         /* reinit nic view of the rx queue */
3954                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3955                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3956                         writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3957                                 base + NvRegRingSizes);
3958                         pci_push(base);
3959                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3960                         pci_push(base);
3961                         /* clear interrupts */
3962                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3963                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3964                         else
3965                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3966
3967                         /* restart rx engine */
3968                         nv_start_rxtx(dev);
3969                         spin_unlock(&np->lock);
3970                         netif_addr_unlock(dev);
3971                         netif_tx_unlock_bh(dev);
3972                 }
3973         }
3974
3975         writel(mask, base + NvRegIrqMask);
3976         pci_push(base);
3977
3978         if (!using_multi_irqs(dev)) {
3979                 np->nic_poll_irq = 0;
3980                 if (nv_optimized(np))
3981                         nv_nic_irq_optimized(0, dev);
3982                 else
3983                         nv_nic_irq(0, dev);
3984                 if (np->msi_flags & NV_MSI_X_ENABLED)
3985                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3986                 else
3987                         enable_irq_lockdep(np->pci_dev->irq);
3988         } else {
3989                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3990                         np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL;
3991                         nv_nic_irq_rx(0, dev);
3992                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3993                 }
3994                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3995                         np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL;
3996                         nv_nic_irq_tx(0, dev);
3997                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3998                 }
3999                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4000                         np->nic_poll_irq &= ~NVREG_IRQ_OTHER;
4001                         nv_nic_irq_other(0, dev);
4002                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4003                 }
4004         }
4005
4006 }
4007
4008 #ifdef CONFIG_NET_POLL_CONTROLLER
4009 static void nv_poll_controller(struct net_device *dev)
4010 {
4011         nv_do_nic_poll((unsigned long) dev);
4012 }
4013 #endif
4014
4015 static void nv_do_stats_poll(unsigned long data)
4016 {
4017         struct net_device *dev = (struct net_device *) data;
4018         struct fe_priv *np = netdev_priv(dev);
4019
4020         nv_get_hw_stats(dev);
4021
4022         if (!np->in_shutdown)
4023                 mod_timer(&np->stats_poll,
4024                         round_jiffies(jiffies + STATS_INTERVAL));
4025 }
4026
4027 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4028 {
4029         struct fe_priv *np = netdev_priv(dev);
4030         strcpy(info->driver, DRV_NAME);
4031         strcpy(info->version, FORCEDETH_VERSION);
4032         strcpy(info->bus_info, pci_name(np->pci_dev));
4033 }
4034
4035 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4036 {
4037         struct fe_priv *np = netdev_priv(dev);
4038         wolinfo->supported = WAKE_MAGIC;
4039
4040         spin_lock_irq(&np->lock);
4041         if (np->wolenabled)
4042                 wolinfo->wolopts = WAKE_MAGIC;
4043         spin_unlock_irq(&np->lock);
4044 }
4045
4046 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4047 {
4048         struct fe_priv *np = netdev_priv(dev);
4049         u8 __iomem *base = get_hwbase(dev);
4050         u32 flags = 0;
4051
4052         if (wolinfo->wolopts == 0) {
4053                 np->wolenabled = 0;
4054         } else if (wolinfo->wolopts & WAKE_MAGIC) {
4055                 np->wolenabled = 1;
4056                 flags = NVREG_WAKEUPFLAGS_ENABLE;
4057         }
4058         if (netif_running(dev)) {
4059                 spin_lock_irq(&np->lock);
4060                 writel(flags, base + NvRegWakeUpFlags);
4061                 spin_unlock_irq(&np->lock);
4062         }
4063         return 0;
4064 }
4065
4066 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4067 {
4068         struct fe_priv *np = netdev_priv(dev);
4069         int adv;
4070
4071         spin_lock_irq(&np->lock);
4072         ecmd->port = PORT_MII;
4073         if (!netif_running(dev)) {
4074                 /* We do not track link speed / duplex setting if the
4075                  * interface is disabled. Force a link check */
4076                 if (nv_update_linkspeed(dev)) {
4077                         if (!netif_carrier_ok(dev))
4078                                 netif_carrier_on(dev);
4079                 } else {
4080                         if (netif_carrier_ok(dev))
4081                                 netif_carrier_off(dev);
4082                 }
4083         }
4084
4085         if (netif_carrier_ok(dev)) {
4086                 switch (np->linkspeed & (NVREG_LINKSPEED_MASK)) {
4087                 case NVREG_LINKSPEED_10:
4088                         ecmd->speed = SPEED_10;
4089                         break;
4090                 case NVREG_LINKSPEED_100:
4091                         ecmd->speed = SPEED_100;
4092                         break;
4093                 case NVREG_LINKSPEED_1000:
4094                         ecmd->speed = SPEED_1000;
4095                         break;
4096                 }
4097                 ecmd->duplex = DUPLEX_HALF;
4098                 if (np->duplex)
4099                         ecmd->duplex = DUPLEX_FULL;
4100         } else {
4101                 ecmd->speed = -1;
4102                 ecmd->duplex = -1;
4103         }
4104
4105         ecmd->autoneg = np->autoneg;
4106
4107         ecmd->advertising = ADVERTISED_MII;
4108         if (np->autoneg) {
4109                 ecmd->advertising |= ADVERTISED_Autoneg;
4110                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4111                 if (adv & ADVERTISE_10HALF)
4112                         ecmd->advertising |= ADVERTISED_10baseT_Half;
4113                 if (adv & ADVERTISE_10FULL)
4114                         ecmd->advertising |= ADVERTISED_10baseT_Full;
4115                 if (adv & ADVERTISE_100HALF)
4116                         ecmd->advertising |= ADVERTISED_100baseT_Half;
4117                 if (adv & ADVERTISE_100FULL)
4118                         ecmd->advertising |= ADVERTISED_100baseT_Full;
4119                 if (np->gigabit == PHY_GIGABIT) {
4120                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4121                         if (adv & ADVERTISE_1000FULL)
4122                                 ecmd->advertising |= ADVERTISED_1000baseT_Full;
4123                 }
4124         }
4125         ecmd->supported = (SUPPORTED_Autoneg |
4126                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4127                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4128                 SUPPORTED_MII);
4129         if (np->gigabit == PHY_GIGABIT)
4130                 ecmd->supported |= SUPPORTED_1000baseT_Full;
4131
4132         ecmd->phy_address = np->phyaddr;
4133         ecmd->transceiver = XCVR_EXTERNAL;
4134
4135         /* ignore maxtxpkt, maxrxpkt for now */
4136         spin_unlock_irq(&np->lock);
4137         return 0;
4138 }
4139
4140 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4141 {
4142         struct fe_priv *np = netdev_priv(dev);
4143
4144         if (ecmd->port != PORT_MII)
4145                 return -EINVAL;
4146         if (ecmd->transceiver != XCVR_EXTERNAL)
4147                 return -EINVAL;
4148         if (ecmd->phy_address != np->phyaddr) {
4149                 /* TODO: support switching between multiple phys. Should be
4150                  * trivial, but not enabled due to lack of test hardware. */
4151                 return -EINVAL;
4152         }
4153         if (ecmd->autoneg == AUTONEG_ENABLE) {
4154                 u32 mask;
4155
4156                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4157                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4158                 if (np->gigabit == PHY_GIGABIT)
4159                         mask |= ADVERTISED_1000baseT_Full;
4160
4161                 if ((ecmd->advertising & mask) == 0)
4162                         return -EINVAL;
4163
4164         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4165                 /* Note: autonegotiation disable, speed 1000 intentionally
4166                  * forbidden - noone should need that. */
4167
4168                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
4169                         return -EINVAL;
4170                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4171                         return -EINVAL;
4172         } else {
4173                 return -EINVAL;
4174         }
4175
4176         netif_carrier_off(dev);
4177         if (netif_running(dev)) {
4178                 unsigned long flags;
4179
4180                 nv_disable_irq(dev);
4181                 netif_tx_lock_bh(dev);
4182                 netif_addr_lock(dev);
4183                 /* with plain spinlock lockdep complains */
4184                 spin_lock_irqsave(&np->lock, flags);
4185                 /* stop engines */
4186                 /* FIXME:
4187                  * this can take some time, and interrupts are disabled
4188                  * due to spin_lock_irqsave, but let's hope no daemon
4189                  * is going to change the settings very often...
4190                  * Worst case:
4191                  * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4192                  * + some minor delays, which is up to a second approximately
4193                  */
4194                 nv_stop_rxtx(dev);
4195                 spin_unlock_irqrestore(&np->lock, flags);
4196                 netif_addr_unlock(dev);
4197                 netif_tx_unlock_bh(dev);
4198         }
4199
4200         if (ecmd->autoneg == AUTONEG_ENABLE) {
4201                 int adv, bmcr;
4202
4203                 np->autoneg = 1;
4204
4205                 /* advertise only what has been requested */
4206                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4207                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4208                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4209                         adv |= ADVERTISE_10HALF;
4210                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
4211                         adv |= ADVERTISE_10FULL;
4212                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4213                         adv |= ADVERTISE_100HALF;
4214                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
4215                         adv |= ADVERTISE_100FULL;
4216                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)  /* for rx we set both advertisments but disable tx pause */
4217                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4218                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4219                         adv |=  ADVERTISE_PAUSE_ASYM;
4220                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4221
4222                 if (np->gigabit == PHY_GIGABIT) {
4223                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4224                         adv &= ~ADVERTISE_1000FULL;
4225                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4226                                 adv |= ADVERTISE_1000FULL;
4227                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4228                 }
4229
4230                 if (netif_running(dev))
4231                         printk(KERN_INFO "%s: link down.\n", dev->name);
4232                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4233                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4234                         bmcr |= BMCR_ANENABLE;
4235                         /* reset the phy in order for settings to stick,
4236                          * and cause autoneg to start */
4237                         if (phy_reset(dev, bmcr)) {
4238                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4239                                 return -EINVAL;
4240                         }
4241                 } else {
4242                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4243                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4244                 }
4245         } else {
4246                 int adv, bmcr;
4247
4248                 np->autoneg = 0;
4249
4250                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4251                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4252                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4253                         adv |= ADVERTISE_10HALF;
4254                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
4255                         adv |= ADVERTISE_10FULL;
4256                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4257                         adv |= ADVERTISE_100HALF;
4258                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
4259                         adv |= ADVERTISE_100FULL;
4260                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4261                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
4262                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4263                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4264                 }
4265                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4266                         adv |=  ADVERTISE_PAUSE_ASYM;
4267                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4268                 }
4269                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4270                 np->fixed_mode = adv;
4271
4272                 if (np->gigabit == PHY_GIGABIT) {
4273                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4274                         adv &= ~ADVERTISE_1000FULL;
4275                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4276                 }
4277
4278                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4279                 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4280                 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
4281                         bmcr |= BMCR_FULLDPLX;
4282                 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
4283                         bmcr |= BMCR_SPEED100;
4284                 if (np->phy_oui == PHY_OUI_MARVELL) {
4285                         /* reset the phy in order for forced mode settings to stick */
4286                         if (phy_reset(dev, bmcr)) {
4287                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4288                                 return -EINVAL;
4289                         }
4290                 } else {
4291                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4292                         if (netif_running(dev)) {
4293                                 /* Wait a bit and then reconfigure the nic. */
4294                                 udelay(10);
4295                                 nv_linkchange(dev);
4296                         }
4297                 }
4298         }
4299
4300         if (netif_running(dev)) {
4301                 nv_start_rxtx(dev);
4302                 nv_enable_irq(dev);
4303         }
4304
4305         return 0;
4306 }
4307
4308 #define FORCEDETH_REGS_VER      1
4309
4310 static int nv_get_regs_len(struct net_device *dev)
4311 {
4312         struct fe_priv *np = netdev_priv(dev);
4313         return np->register_size;
4314 }
4315
4316 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4317 {
4318         struct fe_priv *np = netdev_priv(dev);
4319         u8 __iomem *base = get_hwbase(dev);
4320         u32 *rbuf = buf;
4321         int i;
4322
4323         regs->version = FORCEDETH_REGS_VER;
4324         spin_lock_irq(&np->lock);
4325         for (i = 0; i <= np->register_size/sizeof(u32); i++)
4326                 rbuf[i] = readl(base + i*sizeof(u32));
4327         spin_unlock_irq(&np->lock);
4328 }
4329
4330 static int nv_nway_reset(struct net_device *dev)
4331 {
4332         struct fe_priv *np = netdev_priv(dev);
4333         int ret;
4334
4335         if (np->autoneg) {
4336                 int bmcr;
4337
4338                 netif_carrier_off(dev);
4339                 if (netif_running(dev)) {
4340                         nv_disable_irq(dev);
4341                         netif_tx_lock_bh(dev);
4342                         netif_addr_lock(dev);
4343                         spin_lock(&np->lock);
4344                         /* stop engines */
4345                         nv_stop_rxtx(dev);
4346                         spin_unlock(&np->lock);
4347                         netif_addr_unlock(dev);
4348                         netif_tx_unlock_bh(dev);
4349                         printk(KERN_INFO "%s: link down.\n", dev->name);
4350                 }
4351
4352                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4353                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4354                         bmcr |= BMCR_ANENABLE;
4355                         /* reset the phy in order for settings to stick*/
4356                         if (phy_reset(dev, bmcr)) {
4357                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4358                                 return -EINVAL;
4359                         }
4360                 } else {
4361                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4362                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4363                 }
4364
4365                 if (netif_running(dev)) {
4366                         nv_start_rxtx(dev);
4367                         nv_enable_irq(dev);
4368                 }
4369                 ret = 0;
4370         } else {
4371                 ret = -EINVAL;
4372         }
4373
4374         return ret;
4375 }
4376
4377 static int nv_set_tso(struct net_device *dev, u32 value)
4378 {
4379         struct fe_priv *np = netdev_priv(dev);
4380
4381         if ((np->driver_data & DEV_HAS_CHECKSUM))
4382                 return ethtool_op_set_tso(dev, value);
4383         else
4384                 return -EOPNOTSUPP;
4385 }
4386
4387 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4388 {
4389         struct fe_priv *np = netdev_priv(dev);
4390
4391         ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4392         ring->rx_mini_max_pending = 0;
4393         ring->rx_jumbo_max_pending = 0;
4394         ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4395
4396         ring->rx_pending = np->rx_ring_size;
4397         ring->rx_mini_pending = 0;
4398         ring->rx_jumbo_pending = 0;
4399         ring->tx_pending = np->tx_ring_size;
4400 }
4401
4402 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4403 {
4404         struct fe_priv *np = netdev_priv(dev);
4405         u8 __iomem *base = get_hwbase(dev);
4406         u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4407         dma_addr_t ring_addr;
4408
4409         if (ring->rx_pending < RX_RING_MIN ||
4410             ring->tx_pending < TX_RING_MIN ||
4411             ring->rx_mini_pending != 0 ||
4412             ring->rx_jumbo_pending != 0 ||
4413             (np->desc_ver == DESC_VER_1 &&
4414              (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4415               ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4416             (np->desc_ver != DESC_VER_1 &&
4417              (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4418               ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4419                 return -EINVAL;
4420         }
4421
4422         /* allocate new rings */
4423         if (!nv_optimized(np)) {
4424                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4425                                             sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4426                                             &ring_addr);
4427         } else {
4428                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4429                                             sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4430                                             &ring_addr);
4431         }
4432         rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4433         tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4434         if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4435                 /* fall back to old rings */
4436                 if (!nv_optimized(np)) {
4437                         if (rxtx_ring)
4438                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4439                                                     rxtx_ring, ring_addr);
4440                 } else {
4441                         if (rxtx_ring)
4442                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4443                                                     rxtx_ring, ring_addr);
4444                 }
4445
4446                 kfree(rx_skbuff);
4447                 kfree(tx_skbuff);
4448                 goto exit;
4449         }
4450
4451         if (netif_running(dev)) {
4452                 nv_disable_irq(dev);
4453                 nv_napi_disable(dev);
4454                 netif_tx_lock_bh(dev);
4455                 netif_addr_lock(dev);
4456                 spin_lock(&np->lock);
4457                 /* stop engines */
4458                 nv_stop_rxtx(dev);
4459                 nv_txrx_reset(dev);
4460                 /* drain queues */
4461                 nv_drain_rxtx(dev);
4462                 /* delete queues */
4463                 free_rings(dev);
4464         }
4465
4466         /* set new values */
4467         np->rx_ring_size = ring->rx_pending;
4468         np->tx_ring_size = ring->tx_pending;
4469
4470         if (!nv_optimized(np)) {
4471                 np->rx_ring.orig = (struct ring_desc *)rxtx_ring;
4472                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4473         } else {
4474                 np->rx_ring.ex = (struct ring_desc_ex *)rxtx_ring;
4475                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4476         }
4477         np->rx_skb = (struct nv_skb_map *)rx_skbuff;
4478         np->tx_skb = (struct nv_skb_map *)tx_skbuff;
4479         np->ring_addr = ring_addr;
4480
4481         memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4482         memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4483
4484         if (netif_running(dev)) {
4485                 /* reinit driver view of the queues */
4486                 set_bufsize(dev);
4487                 if (nv_init_ring(dev)) {
4488                         if (!np->in_shutdown)
4489                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4490                 }
4491
4492                 /* reinit nic view of the queues */
4493                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4494                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4495                 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4496                         base + NvRegRingSizes);
4497                 pci_push(base);
4498                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4499                 pci_push(base);
4500
4501                 /* restart engines */
4502                 nv_start_rxtx(dev);
4503                 spin_unlock(&np->lock);
4504                 netif_addr_unlock(dev);
4505                 netif_tx_unlock_bh(dev);
4506                 nv_napi_enable(dev);
4507                 nv_enable_irq(dev);
4508         }
4509         return 0;
4510 exit:
4511         return -ENOMEM;
4512 }
4513
4514 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4515 {
4516         struct fe_priv *np = netdev_priv(dev);
4517
4518         pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4519         pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4520         pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4521 }
4522
4523 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4524 {
4525         struct fe_priv *np = netdev_priv(dev);
4526         int adv, bmcr;
4527
4528         if ((!np->autoneg && np->duplex == 0) ||
4529             (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4530                 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
4531                        dev->name);
4532                 return -EINVAL;
4533         }
4534         if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4535                 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
4536                 return -EINVAL;
4537         }
4538
4539         netif_carrier_off(dev);
4540         if (netif_running(dev)) {
4541                 nv_disable_irq(dev);
4542                 netif_tx_lock_bh(dev);
4543                 netif_addr_lock(dev);
4544                 spin_lock(&np->lock);
4545                 /* stop engines */
4546                 nv_stop_rxtx(dev);
4547                 spin_unlock(&np->lock);
4548                 netif_addr_unlock(dev);
4549                 netif_tx_unlock_bh(dev);
4550         }
4551
4552         np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4553         if (pause->rx_pause)
4554                 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4555         if (pause->tx_pause)
4556                 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4557
4558         if (np->autoneg && pause->autoneg) {
4559                 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4560
4561                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4562                 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4563                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4564                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4565                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4566                         adv |=  ADVERTISE_PAUSE_ASYM;
4567                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4568
4569                 if (netif_running(dev))
4570                         printk(KERN_INFO "%s: link down.\n", dev->name);
4571                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4572                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4573                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4574         } else {
4575                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4576                 if (pause->rx_pause)
4577                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4578                 if (pause->tx_pause)
4579                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4580
4581                 if (!netif_running(dev))
4582                         nv_update_linkspeed(dev);
4583                 else
4584                         nv_update_pause(dev, np->pause_flags);
4585         }
4586
4587         if (netif_running(dev)) {
4588                 nv_start_rxtx(dev);
4589                 nv_enable_irq(dev);
4590         }
4591         return 0;
4592 }
4593
4594 static u32 nv_get_rx_csum(struct net_device *dev)
4595 {
4596         struct fe_priv *np = netdev_priv(dev);
4597         return np->rx_csum != 0;
4598 }
4599
4600 static int nv_set_rx_csum(struct net_device *dev, u32 data)
4601 {
4602         struct fe_priv *np = netdev_priv(dev);
4603         u8 __iomem *base = get_hwbase(dev);
4604         int retcode = 0;
4605
4606         if (np->driver_data & DEV_HAS_CHECKSUM) {
4607                 if (data) {
4608                         np->rx_csum = 1;
4609                         np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4610                 } else {
4611                         np->rx_csum = 0;
4612                         /* vlan is dependent on rx checksum offload */
4613                         if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
4614                                 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4615                 }
4616                 if (netif_running(dev)) {
4617                         spin_lock_irq(&np->lock);
4618                         writel(np->txrxctl_bits, base + NvRegTxRxControl);
4619                         spin_unlock_irq(&np->lock);
4620                 }
4621         } else {
4622                 return -EINVAL;
4623         }
4624
4625         return retcode;
4626 }
4627
4628 static int nv_set_tx_csum(struct net_device *dev, u32 data)
4629 {
4630         struct fe_priv *np = netdev_priv(dev);
4631
4632         if (np->driver_data & DEV_HAS_CHECKSUM)
4633                 return ethtool_op_set_tx_csum(dev, data);
4634         else
4635                 return -EOPNOTSUPP;
4636 }
4637
4638 static int nv_set_sg(struct net_device *dev, u32 data)
4639 {
4640         struct fe_priv *np = netdev_priv(dev);
4641
4642         if (np->driver_data & DEV_HAS_CHECKSUM)
4643                 return ethtool_op_set_sg(dev, data);
4644         else
4645                 return -EOPNOTSUPP;
4646 }
4647
4648 static int nv_get_sset_count(struct net_device *dev, int sset)
4649 {
4650         struct fe_priv *np = netdev_priv(dev);
4651
4652         switch (sset) {
4653         case ETH_SS_TEST:
4654                 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4655                         return NV_TEST_COUNT_EXTENDED;
4656                 else
4657                         return NV_TEST_COUNT_BASE;
4658         case ETH_SS_STATS:
4659                 if (np->driver_data & DEV_HAS_STATISTICS_V3)
4660                         return NV_DEV_STATISTICS_V3_COUNT;
4661                 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4662                         return NV_DEV_STATISTICS_V2_COUNT;
4663                 else if (np->driver_data & DEV_HAS_STATISTICS_V1)
4664                         return NV_DEV_STATISTICS_V1_COUNT;
4665                 else
4666                         return 0;
4667         default:
4668                 return -EOPNOTSUPP;
4669         }
4670 }
4671
4672 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4673 {
4674         struct fe_priv *np = netdev_priv(dev);
4675
4676         /* update stats */
4677         nv_do_stats_poll((unsigned long)dev);
4678
4679         memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
4680 }
4681
4682 static int nv_link_test(struct net_device *dev)
4683 {
4684         struct fe_priv *np = netdev_priv(dev);
4685         int mii_status;
4686
4687         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4688         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4689
4690         /* check phy link status */
4691         if (!(mii_status & BMSR_LSTATUS))
4692                 return 0;
4693         else
4694                 return 1;
4695 }
4696
4697 static int nv_register_test(struct net_device *dev)
4698 {
4699         u8 __iomem *base = get_hwbase(dev);
4700         int i = 0;
4701         u32 orig_read, new_read;
4702
4703         do {
4704                 orig_read = readl(base + nv_registers_test[i].reg);
4705
4706                 /* xor with mask to toggle bits */
4707                 orig_read ^= nv_registers_test[i].mask;
4708
4709                 writel(orig_read, base + nv_registers_test[i].reg);
4710
4711                 new_read = readl(base + nv_registers_test[i].reg);
4712
4713                 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4714                         return 0;
4715
4716                 /* restore original value */
4717                 orig_read ^= nv_registers_test[i].mask;
4718                 writel(orig_read, base + nv_registers_test[i].reg);
4719
4720         } while (nv_registers_test[++i].reg != 0);
4721
4722         return 1;
4723 }
4724
4725 static int nv_interrupt_test(struct net_device *dev)
4726 {
4727         struct fe_priv *np = netdev_priv(dev);
4728         u8 __iomem *base = get_hwbase(dev);
4729         int ret = 1;
4730         int testcnt;
4731         u32 save_msi_flags, save_poll_interval = 0;
4732
4733         if (netif_running(dev)) {
4734                 /* free current irq */
4735                 nv_free_irq(dev);
4736                 save_poll_interval = readl(base+NvRegPollingInterval);
4737         }
4738
4739         /* flag to test interrupt handler */
4740         np->intr_test = 0;
4741
4742         /* setup test irq */
4743         save_msi_flags = np->msi_flags;
4744         np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4745         np->msi_flags |= 0x001; /* setup 1 vector */
4746         if (nv_request_irq(dev, 1))
4747                 return 0;
4748
4749         /* setup timer interrupt */
4750         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4751         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4752
4753         nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4754
4755         /* wait for at least one interrupt */
4756         msleep(100);
4757
4758         spin_lock_irq(&np->lock);
4759
4760         /* flag should be set within ISR */
4761         testcnt = np->intr_test;
4762         if (!testcnt)
4763                 ret = 2;
4764
4765         nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4766         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4767                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4768         else
4769                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4770
4771         spin_unlock_irq(&np->lock);
4772
4773         nv_free_irq(dev);
4774
4775         np->msi_flags = save_msi_flags;
4776
4777         if (netif_running(dev)) {
4778                 writel(save_poll_interval, base + NvRegPollingInterval);
4779                 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4780                 /* restore original irq */
4781                 if (nv_request_irq(dev, 0))
4782                         return 0;
4783         }
4784
4785         return ret;
4786 }
4787
4788 static int nv_loopback_test(struct net_device *dev)
4789 {
4790         struct fe_priv *np = netdev_priv(dev);
4791         u8 __iomem *base = get_hwbase(dev);
4792         struct sk_buff *tx_skb, *rx_skb;
4793         dma_addr_t test_dma_addr;
4794         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
4795         u32 flags;
4796         int len, i, pkt_len;
4797         u8 *pkt_data;
4798         u32 filter_flags = 0;
4799         u32 misc1_flags = 0;
4800         int ret = 1;
4801
4802         if (netif_running(dev)) {
4803                 nv_disable_irq(dev);
4804                 filter_flags = readl(base + NvRegPacketFilterFlags);
4805                 misc1_flags = readl(base + NvRegMisc1);
4806         } else {
4807                 nv_txrx_reset(dev);
4808         }
4809
4810         /* reinit driver view of the rx queue */
4811         set_bufsize(dev);
4812         nv_init_ring(dev);
4813
4814         /* setup hardware for loopback */
4815         writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
4816         writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
4817
4818         /* reinit nic view of the rx queue */
4819         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4820         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4821         writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4822                 base + NvRegRingSizes);
4823         pci_push(base);
4824
4825         /* restart rx engine */
4826         nv_start_rxtx(dev);
4827
4828         /* setup packet for tx */
4829         pkt_len = ETH_DATA_LEN;
4830         tx_skb = dev_alloc_skb(pkt_len);
4831         if (!tx_skb) {
4832                 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
4833                          " of %s\n", dev->name);
4834                 ret = 0;
4835                 goto out;
4836         }
4837         test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
4838                                        skb_tailroom(tx_skb),
4839                                        PCI_DMA_FROMDEVICE);
4840         pkt_data = skb_put(tx_skb, pkt_len);
4841         for (i = 0; i < pkt_len; i++)
4842                 pkt_data[i] = (u8)(i & 0xff);
4843
4844         if (!nv_optimized(np)) {
4845                 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
4846                 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4847         } else {
4848                 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
4849                 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
4850                 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4851         }
4852         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4853         pci_push(get_hwbase(dev));
4854
4855         msleep(500);
4856
4857         /* check for rx of the packet */
4858         if (!nv_optimized(np)) {
4859                 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
4860                 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
4861
4862         } else {
4863                 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
4864                 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
4865         }
4866
4867         if (flags & NV_RX_AVAIL) {
4868                 ret = 0;
4869         } else if (np->desc_ver == DESC_VER_1) {
4870                 if (flags & NV_RX_ERROR)
4871                         ret = 0;
4872         } else {
4873                 if (flags & NV_RX2_ERROR)
4874                         ret = 0;
4875         }
4876
4877         if (ret) {
4878                 if (len != pkt_len) {
4879                         ret = 0;
4880                         dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
4881                                 dev->name, len, pkt_len);
4882                 } else {
4883                         rx_skb = np->rx_skb[0].skb;
4884                         for (i = 0; i < pkt_len; i++) {
4885                                 if (rx_skb->data[i] != (u8)(i & 0xff)) {
4886                                         ret = 0;
4887                                         dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
4888                                                 dev->name, i);
4889                                         break;
4890                                 }
4891                         }
4892                 }
4893         } else {
4894                 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
4895         }
4896
4897         pci_unmap_single(np->pci_dev, test_dma_addr,
4898                        (skb_end_pointer(tx_skb) - tx_skb->data),
4899                        PCI_DMA_TODEVICE);
4900         dev_kfree_skb_any(tx_skb);
4901  out:
4902         /* stop engines */
4903         nv_stop_rxtx(dev);
4904         nv_txrx_reset(dev);
4905         /* drain rx queue */
4906         nv_drain_rxtx(dev);
4907
4908         if (netif_running(dev)) {
4909                 writel(misc1_flags, base + NvRegMisc1);
4910                 writel(filter_flags, base + NvRegPacketFilterFlags);
4911                 nv_enable_irq(dev);
4912         }
4913
4914         return ret;
4915 }
4916
4917 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
4918 {
4919         struct fe_priv *np = netdev_priv(dev);
4920         u8 __iomem *base = get_hwbase(dev);
4921         int result;
4922         memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
4923
4924         if (!nv_link_test(dev)) {
4925                 test->flags |= ETH_TEST_FL_FAILED;
4926                 buffer[0] = 1;
4927         }
4928
4929         if (test->flags & ETH_TEST_FL_OFFLINE) {
4930                 if (netif_running(dev)) {
4931                         netif_stop_queue(dev);
4932                         nv_napi_disable(dev);
4933                         netif_tx_lock_bh(dev);
4934                         netif_addr_lock(dev);
4935                         spin_lock_irq(&np->lock);
4936                         nv_disable_hw_interrupts(dev, np->irqmask);
4937                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4938                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4939                         else
4940                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4941                         /* stop engines */
4942                         nv_stop_rxtx(dev);
4943                         nv_txrx_reset(dev);
4944                         /* drain rx queue */
4945                         nv_drain_rxtx(dev);
4946                         spin_unlock_irq(&np->lock);
4947                         netif_addr_unlock(dev);
4948                         netif_tx_unlock_bh(dev);
4949                 }
4950
4951                 if (!nv_register_test(dev)) {
4952                         test->flags |= ETH_TEST_FL_FAILED;
4953                         buffer[1] = 1;
4954                 }
4955
4956                 result = nv_interrupt_test(dev);
4957                 if (result != 1) {
4958                         test->flags |= ETH_TEST_FL_FAILED;
4959                         buffer[2] = 1;
4960                 }
4961                 if (result == 0) {
4962                         /* bail out */
4963                         return;
4964                 }
4965
4966                 if (!nv_loopback_test(dev)) {
4967                         test->flags |= ETH_TEST_FL_FAILED;
4968                         buffer[3] = 1;
4969                 }
4970
4971                 if (netif_running(dev)) {
4972                         /* reinit driver view of the rx queue */
4973                         set_bufsize(dev);
4974                         if (nv_init_ring(dev)) {
4975                                 if (!np->in_shutdown)
4976                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4977                         }
4978                         /* reinit nic view of the rx queue */
4979                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4980                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4981                         writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4982                                 base + NvRegRingSizes);
4983                         pci_push(base);
4984                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4985                         pci_push(base);
4986                         /* restart rx engine */
4987                         nv_start_rxtx(dev);
4988                         netif_start_queue(dev);
4989                         nv_napi_enable(dev);
4990                         nv_enable_hw_interrupts(dev, np->irqmask);
4991                 }
4992         }
4993 }
4994
4995 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
4996 {
4997         switch (stringset) {
4998         case ETH_SS_STATS:
4999                 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
5000                 break;
5001         case ETH_SS_TEST:
5002                 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
5003                 break;
5004         }
5005 }
5006
5007 static const struct ethtool_ops ops = {
5008         .get_drvinfo = nv_get_drvinfo,
5009         .get_link = ethtool_op_get_link,
5010         .get_wol = nv_get_wol,
5011         .set_wol = nv_set_wol,
5012         .get_settings = nv_get_settings,
5013         .set_settings = nv_set_settings,
5014         .get_regs_len = nv_get_regs_len,
5015         .get_regs = nv_get_regs,
5016         .nway_reset = nv_nway_reset,
5017         .set_tso = nv_set_tso,
5018         .get_ringparam = nv_get_ringparam,
5019         .set_ringparam = nv_set_ringparam,
5020         .get_pauseparam = nv_get_pauseparam,
5021         .set_pauseparam = nv_set_pauseparam,
5022         .get_rx_csum = nv_get_rx_csum,
5023         .set_rx_csum = nv_set_rx_csum,
5024         .set_tx_csum = nv_set_tx_csum,
5025         .set_sg = nv_set_sg,
5026         .get_strings = nv_get_strings,
5027         .get_ethtool_stats = nv_get_ethtool_stats,
5028         .get_sset_count = nv_get_sset_count,
5029         .self_test = nv_self_test,
5030 };
5031
5032 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
5033 {
5034         struct fe_priv *np = get_nvpriv(dev);
5035
5036         spin_lock_irq(&np->lock);
5037
5038         /* save vlan group */
5039         np->vlangrp = grp;
5040
5041         if (grp) {
5042                 /* enable vlan on MAC */
5043                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
5044         } else {
5045                 /* disable vlan on MAC */
5046                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
5047                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
5048         }
5049
5050         writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5051
5052         spin_unlock_irq(&np->lock);
5053 }
5054
5055 /* The mgmt unit and driver use a semaphore to access the phy during init */
5056 static int nv_mgmt_acquire_sema(struct net_device *dev)
5057 {
5058         struct fe_priv *np = netdev_priv(dev);
5059         u8 __iomem *base = get_hwbase(dev);
5060         int i;
5061         u32 tx_ctrl, mgmt_sema;
5062
5063         for (i = 0; i < 10; i++) {
5064                 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
5065                 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
5066                         break;
5067                 msleep(500);
5068         }
5069
5070         if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
5071                 return 0;
5072
5073         for (i = 0; i < 2; i++) {
5074                 tx_ctrl = readl(base + NvRegTransmitterControl);
5075                 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
5076                 writel(tx_ctrl, base + NvRegTransmitterControl);
5077
5078                 /* verify that semaphore was acquired */
5079                 tx_ctrl = readl(base + NvRegTransmitterControl);
5080                 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
5081                     ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
5082                         np->mgmt_sema = 1;
5083                         return 1;
5084                 } else
5085                         udelay(50);
5086         }
5087
5088         return 0;
5089 }
5090
5091 static void nv_mgmt_release_sema(struct net_device *dev)
5092 {
5093         struct fe_priv *np = netdev_priv(dev);
5094         u8 __iomem *base = get_hwbase(dev);
5095         u32 tx_ctrl;
5096
5097         if (np->driver_data & DEV_HAS_MGMT_UNIT) {
5098                 if (np->mgmt_sema) {
5099                         tx_ctrl = readl(base + NvRegTransmitterControl);
5100                         tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
5101                         writel(tx_ctrl, base + NvRegTransmitterControl);
5102                 }
5103         }
5104 }
5105
5106
5107 static int nv_mgmt_get_version(struct net_device *dev)
5108 {
5109         struct fe_priv *np = netdev_priv(dev);
5110         u8 __iomem *base = get_hwbase(dev);
5111         u32 data_ready = readl(base + NvRegTransmitterControl);
5112         u32 data_ready2 = 0;
5113         unsigned long start;
5114         int ready = 0;
5115
5116         writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
5117         writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
5118         start = jiffies;
5119         while (time_before(jiffies, start + 5*HZ)) {
5120                 data_ready2 = readl(base + NvRegTransmitterControl);
5121                 if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) {
5122                         ready = 1;
5123                         break;
5124                 }
5125                 schedule_timeout_uninterruptible(1);
5126         }
5127
5128         if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR))
5129                 return 0;
5130
5131         np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;
5132
5133         return 1;
5134 }
5135
5136 static int nv_open(struct net_device *dev)
5137 {
5138         struct fe_priv *np = netdev_priv(dev);
5139         u8 __iomem *base = get_hwbase(dev);
5140         int ret = 1;
5141         int oom, i;
5142         u32 low;
5143
5144         dprintk(KERN_DEBUG "nv_open: begin\n");
5145
5146         /* power up phy */
5147         mii_rw(dev, np->phyaddr, MII_BMCR,
5148                mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
5149
5150         nv_txrx_gate(dev, false);
5151         /* erase previous misconfiguration */
5152         if (np->driver_data & DEV_HAS_POWER_CNTRL)
5153                 nv_mac_reset(dev);
5154         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5155         writel(0, base + NvRegMulticastAddrB);
5156         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5157         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5158         writel(0, base + NvRegPacketFilterFlags);
5159
5160         writel(0, base + NvRegTransmitterControl);
5161         writel(0, base + NvRegReceiverControl);
5162
5163         writel(0, base + NvRegAdapterControl);
5164
5165         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5166                 writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
5167
5168         /* initialize descriptor rings */
5169         set_bufsize(dev);
5170         oom = nv_init_ring(dev);
5171
5172         writel(0, base + NvRegLinkSpeed);
5173         writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5174         nv_txrx_reset(dev);
5175         writel(0, base + NvRegUnknownSetupReg6);
5176
5177         np->in_shutdown = 0;
5178
5179         /* give hw rings */
5180         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5181         writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5182                 base + NvRegRingSizes);
5183
5184         writel(np->linkspeed, base + NvRegLinkSpeed);
5185         if (np->desc_ver == DESC_VER_1)
5186                 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5187         else
5188                 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
5189         writel(np->txrxctl_bits, base + NvRegTxRxControl);
5190         writel(np->vlanctl_bits, base + NvRegVlanControl);
5191         pci_push(base);
5192         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
5193         reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5194                         NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
5195                         KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
5196
5197         writel(0, base + NvRegMIIMask);
5198         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5199         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5200
5201         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5202         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5203         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
5204         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5205
5206         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
5207
5208         get_random_bytes(&low, sizeof(low));
5209         low &= NVREG_SLOTTIME_MASK;
5210         if (np->desc_ver == DESC_VER_1) {
5211                 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5212         } else {
5213                 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5214                         /* setup legacy backoff */
5215                         writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5216                 } else {
5217                         writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5218                         nv_gear_backoff_reseed(dev);
5219                 }
5220         }
5221         writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5222         writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
5223         if (poll_interval == -1) {
5224                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5225                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5226                 else
5227                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5228         } else
5229                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5230         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5231         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5232                         base + NvRegAdapterControl);
5233         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
5234         writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
5235         if (np->wolenabled)
5236                 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5237
5238         i = readl(base + NvRegPowerState);
5239         if ((i & NVREG_POWERSTATE_POWEREDUP) == 0)
5240                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5241
5242         pci_push(base);
5243         udelay(10);
5244         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5245
5246         nv_disable_hw_interrupts(dev, np->irqmask);
5247         pci_push(base);
5248         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5249         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5250         pci_push(base);
5251
5252         if (nv_request_irq(dev, 0))
5253                 goto out_drain;
5254
5255         /* ask for interrupts */
5256         nv_enable_hw_interrupts(dev, np->irqmask);
5257
5258         spin_lock_irq(&np->lock);
5259         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5260         writel(0, base + NvRegMulticastAddrB);
5261         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5262         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5263         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5264         /* One manual link speed update: Interrupts are enabled, future link
5265          * speed changes cause interrupts and are handled by nv_link_irq().
5266          */
5267         {
5268                 u32 miistat;
5269                 miistat = readl(base + NvRegMIIStatus);
5270                 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5271                 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
5272         }
5273         /* set linkspeed to invalid value, thus force nv_update_linkspeed
5274          * to init hw */
5275         np->linkspeed = 0;
5276         ret = nv_update_linkspeed(dev);
5277         nv_start_rxtx(dev);
5278         netif_start_queue(dev);
5279         nv_napi_enable(dev);
5280
5281         if (ret) {
5282                 netif_carrier_on(dev);
5283         } else {
5284                 printk(KERN_INFO "%s: no link during initialization.\n", dev->name);
5285                 netif_carrier_off(dev);
5286         }
5287         if (oom)
5288                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5289
5290         /* start statistics timer */
5291         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5292                 mod_timer(&np->stats_poll,
5293                         round_jiffies(jiffies + STATS_INTERVAL));
5294
5295         spin_unlock_irq(&np->lock);
5296
5297         return 0;
5298 out_drain:
5299         nv_drain_rxtx(dev);
5300         return ret;
5301 }
5302
5303 static int nv_close(struct net_device *dev)
5304 {
5305         struct fe_priv *np = netdev_priv(dev);
5306         u8 __iomem *base;
5307
5308         spin_lock_irq(&np->lock);
5309         np->in_shutdown = 1;
5310         spin_unlock_irq(&np->lock);
5311         nv_napi_disable(dev);
5312         synchronize_irq(np->pci_dev->irq);
5313
5314         del_timer_sync(&np->oom_kick);
5315         del_timer_sync(&np->nic_poll);
5316         del_timer_sync(&np->stats_poll);
5317
5318         netif_stop_queue(dev);
5319         spin_lock_irq(&np->lock);
5320         nv_stop_rxtx(dev);
5321         nv_txrx_reset(dev);
5322
5323         /* disable interrupts on the nic or we will lock up */
5324         base = get_hwbase(dev);
5325         nv_disable_hw_interrupts(dev, np->irqmask);
5326         pci_push(base);
5327         dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
5328
5329         spin_unlock_irq(&np->lock);
5330
5331         nv_free_irq(dev);
5332
5333         nv_drain_rxtx(dev);
5334
5335         if (np->wolenabled || !phy_power_down) {
5336                 nv_txrx_gate(dev, false);
5337                 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5338                 nv_start_rx(dev);
5339         } else {
5340                 /* power down phy */
5341                 mii_rw(dev, np->phyaddr, MII_BMCR,
5342                        mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
5343                 nv_txrx_gate(dev, true);
5344         }
5345
5346         /* FIXME: power down nic */
5347
5348         return 0;
5349 }
5350
5351 static const struct net_device_ops nv_netdev_ops = {
5352         .ndo_open               = nv_open,
5353         .ndo_stop               = nv_close,
5354         .ndo_get_stats          = nv_get_stats,
5355         .ndo_start_xmit         = nv_start_xmit,
5356         .ndo_tx_timeout         = nv_tx_timeout,
5357         .ndo_change_mtu         = nv_change_mtu,
5358         .ndo_validate_addr      = eth_validate_addr,
5359         .ndo_set_mac_address    = nv_set_mac_address,
5360         .ndo_set_multicast_list = nv_set_multicast,
5361         .ndo_vlan_rx_register   = nv_vlan_rx_register,
5362 #ifdef CONFIG_NET_POLL_CONTROLLER
5363         .ndo_poll_controller    = nv_poll_controller,
5364 #endif
5365 };
5366
5367 static const struct net_device_ops nv_netdev_ops_optimized = {
5368         .ndo_open               = nv_open,
5369         .ndo_stop               = nv_close,
5370         .ndo_get_stats          = nv_get_stats,
5371         .ndo_start_xmit         = nv_start_xmit_optimized,
5372         .ndo_tx_timeout         = nv_tx_timeout,
5373         .ndo_change_mtu         = nv_change_mtu,
5374         .ndo_validate_addr      = eth_validate_addr,
5375         .ndo_set_mac_address    = nv_set_mac_address,
5376         .ndo_set_multicast_list = nv_set_multicast,
5377         .ndo_vlan_rx_register   = nv_vlan_rx_register,
5378 #ifdef CONFIG_NET_POLL_CONTROLLER
5379         .ndo_poll_controller    = nv_poll_controller,
5380 #endif
5381 };
5382
5383 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5384 {
5385         struct net_device *dev;
5386         struct fe_priv *np;
5387         unsigned long addr;
5388         u8 __iomem *base;
5389         int err, i;
5390         u32 powerstate, txreg;
5391         u32 phystate_orig = 0, phystate;
5392         int phyinitialized = 0;
5393         static int printed_version;
5394
5395         if (!printed_version++)
5396                 printk(KERN_INFO "%s: Reverse Engineered nForce ethernet"
5397                        " driver. Version %s.\n", DRV_NAME, FORCEDETH_VERSION);
5398
5399         dev = alloc_etherdev(sizeof(struct fe_priv));
5400         err = -ENOMEM;
5401         if (!dev)
5402                 goto out;
5403
5404         np = netdev_priv(dev);
5405         np->dev = dev;
5406         np->pci_dev = pci_dev;
5407         spin_lock_init(&np->lock);
5408         SET_NETDEV_DEV(dev, &pci_dev->dev);
5409
5410         init_timer(&np->oom_kick);
5411         np->oom_kick.data = (unsigned long) dev;
5412         np->oom_kick.function = nv_do_rx_refill;        /* timer handler */
5413         init_timer(&np->nic_poll);
5414         np->nic_poll.data = (unsigned long) dev;
5415         np->nic_poll.function = nv_do_nic_poll; /* timer handler */
5416         init_timer(&np->stats_poll);
5417         np->stats_poll.data = (unsigned long) dev;
5418         np->stats_poll.function = nv_do_stats_poll;     /* timer handler */
5419
5420         err = pci_enable_device(pci_dev);
5421         if (err)
5422                 goto out_free;
5423
5424         pci_set_master(pci_dev);
5425
5426         err = pci_request_regions(pci_dev, DRV_NAME);
5427         if (err < 0)
5428                 goto out_disable;
5429
5430         if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5431                 np->register_size = NV_PCI_REGSZ_VER3;
5432         else if (id->driver_data & DEV_HAS_STATISTICS_V1)
5433                 np->register_size = NV_PCI_REGSZ_VER2;
5434         else
5435                 np->register_size = NV_PCI_REGSZ_VER1;
5436
5437         err = -EINVAL;
5438         addr = 0;
5439         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5440                 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
5441                                 pci_name(pci_dev), i, (void *)pci_resource_start(pci_dev, i),
5442                                 pci_resource_len(pci_dev, i),
5443                                 pci_resource_flags(pci_dev, i));
5444                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
5445                                 pci_resource_len(pci_dev, i) >= np->register_size) {
5446                         addr = pci_resource_start(pci_dev, i);
5447                         break;
5448                 }
5449         }
5450         if (i == DEVICE_COUNT_RESOURCE) {
5451                 dev_printk(KERN_INFO, &pci_dev->dev,
5452                            "Couldn't find register window\n");
5453                 goto out_relreg;
5454         }
5455
5456         /* copy of driver data */
5457         np->driver_data = id->driver_data;
5458         /* copy of device id */
5459         np->device_id = id->device;
5460
5461         /* handle different descriptor versions */
5462         if (id->driver_data & DEV_HAS_HIGH_DMA) {
5463                 /* packet format 3: supports 40-bit addressing */
5464                 np->desc_ver = DESC_VER_3;
5465                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
5466                 if (dma_64bit) {
5467                         if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39)))
5468                                 dev_printk(KERN_INFO, &pci_dev->dev,
5469                                         "64-bit DMA failed, using 32-bit addressing\n");
5470                         else
5471                                 dev->features |= NETIF_F_HIGHDMA;
5472                         if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) {
5473                                 dev_printk(KERN_INFO, &pci_dev->dev,
5474                                         "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5475                         }
5476                 }
5477         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5478                 /* packet format 2: supports jumbo frames */
5479                 np->desc_ver = DESC_VER_2;
5480                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
5481         } else {
5482                 /* original packet format */
5483                 np->desc_ver = DESC_VER_1;
5484                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
5485         }
5486
5487         np->pkt_limit = NV_PKTLIMIT_1;
5488         if (id->driver_data & DEV_HAS_LARGEDESC)
5489                 np->pkt_limit = NV_PKTLIMIT_2;
5490
5491         if (id->driver_data & DEV_HAS_CHECKSUM) {
5492                 np->rx_csum = 1;
5493                 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
5494                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
5495                 dev->features |= NETIF_F_TSO;
5496                 dev->features |= NETIF_F_GRO;
5497         }
5498
5499         np->vlanctl_bits = 0;
5500         if (id->driver_data & DEV_HAS_VLAN) {
5501                 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5502                 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
5503         }
5504
5505         np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
5506         if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5507             (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5508             (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
5509                 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
5510         }
5511
5512
5513         err = -ENOMEM;
5514         np->base = ioremap(addr, np->register_size);
5515         if (!np->base)
5516                 goto out_relreg;
5517         dev->base_addr = (unsigned long)np->base;
5518
5519         dev->irq = pci_dev->irq;
5520
5521         np->rx_ring_size = RX_RING_DEFAULT;
5522         np->tx_ring_size = TX_RING_DEFAULT;
5523
5524         if (!nv_optimized(np)) {
5525                 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
5526                                         sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
5527                                         &np->ring_addr);
5528                 if (!np->rx_ring.orig)
5529                         goto out_unmap;
5530                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
5531         } else {
5532                 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
5533                                         sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
5534                                         &np->ring_addr);
5535                 if (!np->rx_ring.ex)
5536                         goto out_unmap;
5537                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
5538         }
5539         np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5540         np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5541         if (!np->rx_skb || !np->tx_skb)
5542                 goto out_freering;
5543
5544         if (!nv_optimized(np))
5545                 dev->netdev_ops = &nv_netdev_ops;
5546         else
5547                 dev->netdev_ops = &nv_netdev_ops_optimized;
5548
5549         netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
5550         SET_ETHTOOL_OPS(dev, &ops);
5551         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5552
5553         pci_set_drvdata(pci_dev, dev);
5554
5555         /* read the mac address */
5556         base = get_hwbase(dev);
5557         np->orig_mac[0] = readl(base + NvRegMacAddrA);
5558         np->orig_mac[1] = readl(base + NvRegMacAddrB);
5559
5560         /* check the workaround bit for correct mac address order */
5561         txreg = readl(base + NvRegTransmitPoll);
5562         if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
5563                 /* mac address is already in correct order */
5564                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5565                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5566                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5567                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5568                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5569                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5570         } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5571                 /* mac address is already in correct order */
5572                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5573                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5574                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5575                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5576                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5577                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5578                 /*
5579                  * Set orig mac address back to the reversed version.
5580                  * This flag will be cleared during low power transition.
5581                  * Therefore, we should always put back the reversed address.
5582                  */
5583                 np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
5584                         (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
5585                 np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
5586         } else {
5587                 /* need to reverse mac address to correct order */
5588                 dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
5589                 dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
5590                 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5591                 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5592                 dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
5593                 dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
5594                 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5595                 printk(KERN_DEBUG "nv_probe: set workaround bit for reversed mac addr\n");
5596         }
5597         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
5598
5599         if (!is_valid_ether_addr(dev->perm_addr)) {
5600                 /*
5601                  * Bad mac address. At least one bios sets the mac address
5602                  * to 01:23:45:67:89:ab
5603                  */
5604                 dev_printk(KERN_ERR, &pci_dev->dev,
5605                         "Invalid Mac address detected: %pM\n",
5606                         dev->dev_addr);
5607                 dev_printk(KERN_ERR, &pci_dev->dev,
5608                         "Please complain to your hardware vendor. Switching to a random MAC.\n");
5609                 random_ether_addr(dev->dev_addr);
5610         }
5611
5612         dprintk(KERN_DEBUG "%s: MAC Address %pM\n",
5613                 pci_name(pci_dev), dev->dev_addr);
5614
5615         /* set mac address */
5616         nv_copy_mac_to_hw(dev);
5617
5618         /* Workaround current PCI init glitch:  wakeup bits aren't
5619          * being set from PCI PM capability.
5620          */
5621         device_init_wakeup(&pci_dev->dev, 1);
5622
5623         /* disable WOL */
5624         writel(0, base + NvRegWakeUpFlags);
5625         np->wolenabled = 0;
5626
5627         if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5628
5629                 /* take phy and nic out of low power mode */
5630                 powerstate = readl(base + NvRegPowerState2);
5631                 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5632                 if ((id->driver_data & DEV_NEED_LOW_POWER_FIX) &&
5633                     pci_dev->revision >= 0xA3)
5634                         powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5635                 writel(powerstate, base + NvRegPowerState2);
5636         }
5637
5638         if (np->desc_ver == DESC_VER_1)
5639                 np->tx_flags = NV_TX_VALID;
5640         else
5641                 np->tx_flags = NV_TX2_VALID;
5642
5643         np->msi_flags = 0;
5644         if ((id->driver_data & DEV_HAS_MSI) && msi)
5645                 np->msi_flags |= NV_MSI_CAPABLE;
5646
5647         if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5648                 /* msix has had reported issues when modifying irqmask
5649                    as in the case of napi, therefore, disable for now
5650                 */
5651 #if 0
5652                 np->msi_flags |= NV_MSI_X_CAPABLE;
5653 #endif
5654         }
5655
5656         if (optimization_mode == NV_OPTIMIZATION_MODE_CPU) {
5657                 np->irqmask = NVREG_IRQMASK_CPU;
5658                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5659                         np->msi_flags |= 0x0001;
5660         } else if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC &&
5661                    !(id->driver_data & DEV_NEED_TIMERIRQ)) {
5662                 /* start off in throughput mode */
5663                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5664                 /* remove support for msix mode */
5665                 np->msi_flags &= ~NV_MSI_X_CAPABLE;
5666         } else {
5667                 optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
5668                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5669                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5670                         np->msi_flags |= 0x0003;
5671         }
5672
5673         if (id->driver_data & DEV_NEED_TIMERIRQ)
5674                 np->irqmask |= NVREG_IRQ_TIMER;
5675         if (id->driver_data & DEV_NEED_LINKTIMER) {
5676                 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
5677                 np->need_linktimer = 1;
5678                 np->link_timeout = jiffies + LINK_TIMEOUT;
5679         } else {
5680                 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
5681                 np->need_linktimer = 0;
5682         }
5683
5684         /* Limit the number of tx's outstanding for hw bug */
5685         if (id->driver_data & DEV_NEED_TX_LIMIT) {
5686                 np->tx_limit = 1;
5687                 if (((id->driver_data & DEV_NEED_TX_LIMIT2) == DEV_NEED_TX_LIMIT2) &&
5688                     pci_dev->revision >= 0xA2)
5689                         np->tx_limit = 0;
5690         }
5691
5692         /* clear phy state and temporarily halt phy interrupts */
5693         writel(0, base + NvRegMIIMask);
5694         phystate = readl(base + NvRegAdapterControl);
5695         if (phystate & NVREG_ADAPTCTL_RUNNING) {
5696                 phystate_orig = 1;
5697                 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5698                 writel(phystate, base + NvRegAdapterControl);
5699         }
5700         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5701
5702         if (id->driver_data & DEV_HAS_MGMT_UNIT) {
5703                 /* management unit running on the mac? */
5704                 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) &&
5705                     (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) &&
5706                     nv_mgmt_acquire_sema(dev) &&
5707                     nv_mgmt_get_version(dev)) {
5708                         np->mac_in_use = 1;
5709                         if (np->mgmt_version > 0)
5710                                 np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE;
5711                         dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n",
5712                                 pci_name(pci_dev), np->mac_in_use);
5713                         /* management unit setup the phy already? */
5714                         if (np->mac_in_use &&
5715                             ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5716                              NVREG_XMITCTL_SYNC_PHY_INIT)) {
5717                                 /* phy is inited by mgmt unit */
5718                                 phyinitialized = 1;
5719                                 dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n",
5720                                         pci_name(pci_dev));
5721                         } else {
5722                                 /* we need to init the phy */
5723                         }
5724                 }
5725         }
5726
5727         /* find a suitable phy */
5728         for (i = 1; i <= 32; i++) {
5729                 int id1, id2;
5730                 int phyaddr = i & 0x1F;
5731
5732                 spin_lock_irq(&np->lock);
5733                 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5734                 spin_unlock_irq(&np->lock);
5735                 if (id1 < 0 || id1 == 0xffff)
5736                         continue;
5737                 spin_lock_irq(&np->lock);
5738                 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5739                 spin_unlock_irq(&np->lock);
5740                 if (id2 < 0 || id2 == 0xffff)
5741                         continue;
5742
5743                 np->phy_model = id2 & PHYID2_MODEL_MASK;
5744                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5745                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5746                 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
5747                         pci_name(pci_dev), id1, id2, phyaddr);
5748                 np->phyaddr = phyaddr;
5749                 np->phy_oui = id1 | id2;
5750
5751                 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5752                 if (np->phy_oui == PHY_OUI_REALTEK2)
5753                         np->phy_oui = PHY_OUI_REALTEK;
5754                 /* Setup phy revision for Realtek */
5755                 if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211)
5756                         np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
5757
5758                 break;
5759         }
5760         if (i == 33) {
5761                 dev_printk(KERN_INFO, &pci_dev->dev,
5762                         "open: Could not find a valid PHY.\n");
5763                 goto out_error;
5764         }
5765
5766         if (!phyinitialized) {
5767                 /* reset it */
5768                 phy_init(dev);
5769         } else {
5770                 /* see if it is a gigabit phy */
5771                 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5772                 if (mii_status & PHY_GIGABIT)
5773                         np->gigabit = PHY_GIGABIT;
5774         }
5775
5776         /* set default link speed settings */
5777         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5778         np->duplex = 0;
5779         np->autoneg = 1;
5780
5781         err = register_netdev(dev);
5782         if (err) {
5783                 dev_printk(KERN_INFO, &pci_dev->dev,
5784                            "unable to register netdev: %d\n", err);
5785                 goto out_error;
5786         }
5787
5788         dev_printk(KERN_INFO, &pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, "
5789                    "addr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
5790                    dev->name,
5791                    np->phy_oui,
5792                    np->phyaddr,
5793                    dev->dev_addr[0],
5794                    dev->dev_addr[1],
5795                    dev->dev_addr[2],
5796                    dev->dev_addr[3],
5797                    dev->dev_addr[4],
5798                    dev->dev_addr[5]);
5799
5800         dev_printk(KERN_INFO, &pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
5801                 dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
5802                 dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ?
5803                         "csum " : "",
5804                 dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
5805                         "vlan " : "",
5806                 id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
5807                 id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
5808                 id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
5809                 np->gigabit == PHY_GIGABIT ? "gbit " : "",
5810                 np->need_linktimer ? "lnktim " : "",
5811                 np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
5812                 np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
5813                 np->desc_ver);
5814
5815         return 0;
5816
5817 out_error:
5818         if (phystate_orig)
5819                 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
5820         pci_set_drvdata(pci_dev, NULL);
5821 out_freering:
5822         free_rings(dev);
5823 out_unmap:
5824         iounmap(get_hwbase(dev));
5825 out_relreg:
5826         pci_release_regions(pci_dev);
5827 out_disable:
5828         pci_disable_device(pci_dev);
5829 out_free:
5830         free_netdev(dev);
5831 out:
5832         return err;
5833 }
5834
5835 static void nv_restore_phy(struct net_device *dev)
5836 {
5837         struct fe_priv *np = netdev_priv(dev);
5838         u16 phy_reserved, mii_control;
5839
5840         if (np->phy_oui == PHY_OUI_REALTEK &&
5841             np->phy_model == PHY_MODEL_REALTEK_8201 &&
5842             phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
5843                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
5844                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
5845                 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
5846                 phy_reserved |= PHY_REALTEK_INIT8;
5847                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
5848                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
5849
5850                 /* restart auto negotiation */
5851                 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
5852                 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
5853                 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);
5854         }
5855 }
5856
5857 static void nv_restore_mac_addr(struct pci_dev *pci_dev)
5858 {
5859         struct net_device *dev = pci_get_drvdata(pci_dev);
5860         struct fe_priv *np = netdev_priv(dev);
5861         u8 __iomem *base = get_hwbase(dev);
5862
5863         /* special op: write back the misordered MAC address - otherwise
5864          * the next nv_probe would see a wrong address.
5865          */
5866         writel(np->orig_mac[0], base + NvRegMacAddrA);
5867         writel(np->orig_mac[1], base + NvRegMacAddrB);
5868         writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
5869                base + NvRegTransmitPoll);
5870 }
5871
5872 static void __devexit nv_remove(struct pci_dev *pci_dev)
5873 {
5874         struct net_device *dev = pci_get_drvdata(pci_dev);
5875
5876         unregister_netdev(dev);
5877
5878         nv_restore_mac_addr(pci_dev);
5879
5880         /* restore any phy related changes */
5881         nv_restore_phy(dev);
5882
5883         nv_mgmt_release_sema(dev);
5884
5885         /* free all structures */
5886         free_rings(dev);
5887         iounmap(get_hwbase(dev));
5888         pci_release_regions(pci_dev);
5889         pci_disable_device(pci_dev);
5890         free_netdev(dev);
5891         pci_set_drvdata(pci_dev, NULL);
5892 }
5893
5894 #ifdef CONFIG_PM
5895 static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
5896 {
5897         struct net_device *dev = pci_get_drvdata(pdev);
5898         struct fe_priv *np = netdev_priv(dev);
5899         u8 __iomem *base = get_hwbase(dev);
5900         int i;
5901
5902         if (netif_running(dev)) {
5903                 /* Gross. */
5904                 nv_close(dev);
5905         }
5906         netif_device_detach(dev);
5907
5908         /* save non-pci configuration space */
5909         for (i = 0; i <= np->register_size/sizeof(u32); i++)
5910                 np->saved_config_space[i] = readl(base + i*sizeof(u32));
5911
5912         pci_save_state(pdev);
5913         pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
5914         pci_disable_device(pdev);
5915         pci_set_power_state(pdev, pci_choose_state(pdev, state));
5916         return 0;
5917 }
5918
5919 static int nv_resume(struct pci_dev *pdev)
5920 {
5921         struct net_device *dev = pci_get_drvdata(pdev);
5922         struct fe_priv *np = netdev_priv(dev);
5923         u8 __iomem *base = get_hwbase(dev);
5924         int i, rc = 0;
5925
5926         pci_set_power_state(pdev, PCI_D0);
5927         pci_restore_state(pdev);
5928         /* ack any pending wake events, disable PME */
5929         pci_enable_wake(pdev, PCI_D0, 0);
5930
5931         /* restore non-pci configuration space */
5932         for (i = 0; i <= np->register_size/sizeof(u32); i++)
5933                 writel(np->saved_config_space[i], base+i*sizeof(u32));
5934
5935         if (np->driver_data & DEV_NEED_MSI_FIX)
5936                 pci_write_config_dword(pdev, NV_MSI_PRIV_OFFSET, NV_MSI_PRIV_VALUE);
5937
5938         /* restore phy state, including autoneg */
5939         phy_init(dev);
5940
5941         netif_device_attach(dev);
5942         if (netif_running(dev)) {
5943                 rc = nv_open(dev);
5944                 nv_set_multicast(dev);
5945         }
5946         return rc;
5947 }
5948
5949 static void nv_shutdown(struct pci_dev *pdev)
5950 {
5951         struct net_device *dev = pci_get_drvdata(pdev);
5952         struct fe_priv *np = netdev_priv(dev);
5953
5954         if (netif_running(dev))
5955                 nv_close(dev);
5956
5957         /*
5958          * Restore the MAC so a kernel started by kexec won't get confused.
5959          * If we really go for poweroff, we must not restore the MAC,
5960          * otherwise the MAC for WOL will be reversed at least on some boards.
5961          */
5962         if (system_state != SYSTEM_POWER_OFF)
5963                 nv_restore_mac_addr(pdev);
5964
5965         pci_disable_device(pdev);
5966         /*
5967          * Apparently it is not possible to reinitialise from D3 hot,
5968          * only put the device into D3 if we really go for poweroff.
5969          */
5970         if (system_state == SYSTEM_POWER_OFF) {
5971                 if (pci_enable_wake(pdev, PCI_D3cold, np->wolenabled))
5972                         pci_enable_wake(pdev, PCI_D3hot, np->wolenabled);
5973                 pci_set_power_state(pdev, PCI_D3hot);
5974         }
5975 }
5976 #else
5977 #define nv_suspend NULL
5978 #define nv_shutdown NULL
5979 #define nv_resume NULL
5980 #endif /* CONFIG_PM */
5981
5982 static DEFINE_PCI_DEVICE_TABLE(pci_tbl) = {
5983         {       /* nForce Ethernet Controller */
5984                 PCI_DEVICE(0x10DE, 0x01C3),
5985                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5986         },
5987         {       /* nForce2 Ethernet Controller */
5988                 PCI_DEVICE(0x10DE, 0x0066),
5989                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5990         },
5991         {       /* nForce3 Ethernet Controller */
5992                 PCI_DEVICE(0x10DE, 0x00D6),
5993                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5994         },
5995         {       /* nForce3 Ethernet Controller */
5996                 PCI_DEVICE(0x10DE, 0x0086),
5997                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5998         },
5999         {       /* nForce3 Ethernet Controller */
6000                 PCI_DEVICE(0x10DE, 0x008C),
6001                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6002         },
6003         {       /* nForce3 Ethernet Controller */
6004                 PCI_DEVICE(0x10DE, 0x00E6),
6005                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6006         },
6007         {       /* nForce3 Ethernet Controller */
6008                 PCI_DEVICE(0x10DE, 0x00DF),
6009                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6010         },
6011         {       /* CK804 Ethernet Controller */
6012                 PCI_DEVICE(0x10DE, 0x0056),
6013                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6014         },
6015         {       /* CK804 Ethernet Controller */
6016                 PCI_DEVICE(0x10DE, 0x0057),
6017                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6018         },
6019         {       /* MCP04 Ethernet Controller */
6020                 PCI_DEVICE(0x10DE, 0x0037),
6021                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6022         },
6023         {       /* MCP04 Ethernet Controller */
6024                 PCI_DEVICE(0x10DE, 0x0038),
6025                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6026         },
6027         {       /* MCP51 Ethernet Controller */
6028                 PCI_DEVICE(0x10DE, 0x0268),
6029                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
6030         },
6031         {       /* MCP51 Ethernet Controller */
6032                 PCI_DEVICE(0x10DE, 0x0269),
6033                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
6034         },
6035         {       /* MCP55 Ethernet Controller */
6036                 PCI_DEVICE(0x10DE, 0x0372),
6037                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
6038         },
6039         {       /* MCP55 Ethernet Controller */
6040                 PCI_DEVICE(0x10DE, 0x0373),
6041                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
6042         },
6043         {       /* MCP61 Ethernet Controller */
6044                 PCI_DEVICE(0x10DE, 0x03E5),
6045                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6046         },
6047         {       /* MCP61 Ethernet Controller */
6048                 PCI_DEVICE(0x10DE, 0x03E6),
6049                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6050         },
6051         {       /* MCP61 Ethernet Controller */
6052                 PCI_DEVICE(0x10DE, 0x03EE),
6053                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6054         },
6055         {       /* MCP61 Ethernet Controller */
6056                 PCI_DEVICE(0x10DE, 0x03EF),
6057                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6058         },
6059         {       /* MCP65 Ethernet Controller */
6060                 PCI_DEVICE(0x10DE, 0x0450),
6061                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6062         },
6063         {       /* MCP65 Ethernet Controller */
6064                 PCI_DEVICE(0x10DE, 0x0451),
6065                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6066         },
6067         {       /* MCP65 Ethernet Controller */
6068                 PCI_DEVICE(0x10DE, 0x0452),
6069                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6070         },
6071         {       /* MCP65 Ethernet Controller */
6072                 PCI_DEVICE(0x10DE, 0x0453),
6073                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6074         },
6075         {       /* MCP67 Ethernet Controller */
6076                 PCI_DEVICE(0x10DE, 0x054C),
6077                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6078         },
6079         {       /* MCP67 Ethernet Controller */
6080                 PCI_DEVICE(0x10DE, 0x054D),
6081                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6082         },
6083         {       /* MCP67 Ethernet Controller */
6084                 PCI_DEVICE(0x10DE, 0x054E),
6085                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6086         },
6087         {       /* MCP67 Ethernet Controller */
6088                 PCI_DEVICE(0x10DE, 0x054F),
6089                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6090         },
6091         {       /* MCP73 Ethernet Controller */
6092                 PCI_DEVICE(0x10DE, 0x07DC),
6093                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6094         },
6095         {       /* MCP73 Ethernet Controller */
6096                 PCI_DEVICE(0x10DE, 0x07DD),
6097                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6098         },
6099         {       /* MCP73 Ethernet Controller */
6100                 PCI_DEVICE(0x10DE, 0x07DE),
6101                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6102         },
6103         {       /* MCP73 Ethernet Controller */
6104                 PCI_DEVICE(0x10DE, 0x07DF),
6105                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6106         },
6107         {       /* MCP77 Ethernet Controller */
6108                 PCI_DEVICE(0x10DE, 0x0760),
6109                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6110         },
6111         {       /* MCP77 Ethernet Controller */
6112                 PCI_DEVICE(0x10DE, 0x0761),
6113                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6114         },
6115         {       /* MCP77 Ethernet Controller */
6116                 PCI_DEVICE(0x10DE, 0x0762),
6117                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6118         },
6119         {       /* MCP77 Ethernet Controller */
6120                 PCI_DEVICE(0x10DE, 0x0763),
6121                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6122         },
6123         {       /* MCP79 Ethernet Controller */
6124                 PCI_DEVICE(0x10DE, 0x0AB0),
6125                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6126         },
6127         {       /* MCP79 Ethernet Controller */
6128                 PCI_DEVICE(0x10DE, 0x0AB1),
6129                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6130         },
6131         {       /* MCP79 Ethernet Controller */
6132                 PCI_DEVICE(0x10DE, 0x0AB2),
6133                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6134         },
6135         {       /* MCP79 Ethernet Controller */
6136                 PCI_DEVICE(0x10DE, 0x0AB3),
6137                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6138         },
6139         {       /* MCP89 Ethernet Controller */
6140                 PCI_DEVICE(0x10DE, 0x0D7D),
6141                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX,
6142         },
6143         {0,},
6144 };
6145
6146 static struct pci_driver driver = {
6147         .name           = DRV_NAME,
6148         .id_table       = pci_tbl,
6149         .probe          = nv_probe,
6150         .remove         = __devexit_p(nv_remove),
6151         .suspend        = nv_suspend,
6152         .resume         = nv_resume,
6153         .shutdown       = nv_shutdown,
6154 };
6155
6156 static int __init init_nic(void)
6157 {
6158         return pci_register_driver(&driver);
6159 }
6160
6161 static void __exit exit_nic(void)
6162 {
6163         pci_unregister_driver(&driver);
6164 }
6165
6166 module_param(max_interrupt_work, int, 0);
6167 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
6168 module_param(optimization_mode, int, 0);
6169 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer. In dynamic mode (2), the mode toggles between throughput and CPU mode based on network load.");
6170 module_param(poll_interval, int, 0);
6171 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
6172 module_param(msi, int, 0);
6173 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
6174 module_param(msix, int, 0);
6175 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
6176 module_param(dma_64bit, int, 0);
6177 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
6178 module_param(phy_cross, int, 0);
6179 MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
6180 module_param(phy_power_down, int, 0);
6181 MODULE_PARM_DESC(phy_power_down, "Power down phy and disable link when interface is down (1), or leave phy powered up (0).");
6182
6183 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6184 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6185 MODULE_LICENSE("GPL");
6186
6187 MODULE_DEVICE_TABLE(pci, pci_tbl);
6188
6189 module_init(init_nic);
6190 module_exit(exit_nic);