2 * Freescale PowerQUICC Ethernet Driver -- MIIM bus implementation
3 * Provides Bus interface for MIIM regs
5 * Author: Andy Fleming <afleming@freescale.com>
6 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
8 * Copyright 2002-2004, 2008-2009 Freescale Semiconductor, Inc.
10 * Based on gianfar_mii.c and ucc_geth_mii.c (Li Yang, Kim Phillips)
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/string.h>
21 #include <linux/errno.h>
22 #include <linux/unistd.h>
23 #include <linux/slab.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/netdevice.h>
28 #include <linux/etherdevice.h>
29 #include <linux/skbuff.h>
30 #include <linux/spinlock.h>
32 #include <linux/module.h>
33 #include <linux/platform_device.h>
34 #include <linux/crc32.h>
35 #include <linux/mii.h>
36 #include <linux/phy.h>
38 #include <linux/of_address.h>
39 #include <linux/of_mdio.h>
40 #include <linux/of_platform.h>
44 #include <asm/uaccess.h>
48 #include "fsl_pq_mdio.h"
50 struct fsl_pq_mdio_priv {
52 struct fsl_pq_mdio __iomem *regs;
56 * Write value to the PHY at mii_id at register regnum,
57 * on the bus attached to the local interface, which may be different from the
58 * generic mdio bus (tied to a single interface), waiting until the write is
59 * done before returning. This is helpful in programming interfaces like
60 * the TBI which control interfaces like onchip SERDES and are always tied to
61 * the local mdio pins, which may not be the same as system mdio bus, used for
62 * controlling the external PHYs, for example.
64 int fsl_pq_local_mdio_write(struct fsl_pq_mdio __iomem *regs, int mii_id,
65 int regnum, u16 value)
67 /* Set the PHY address and the register address we want to write */
68 out_be32(®s->miimadd, (mii_id << 8) | regnum);
70 /* Write out the value we want */
71 out_be32(®s->miimcon, value);
73 /* Wait for the transaction to finish */
74 while (in_be32(®s->miimind) & MIIMIND_BUSY)
81 * Read the bus for PHY at addr mii_id, register regnum, and
82 * return the value. Clears miimcom first. All PHY operation
83 * done on the bus attached to the local interface,
84 * which may be different from the generic mdio bus
85 * This is helpful in programming interfaces like
86 * the TBI which, in turn, control interfaces like onchip SERDES
87 * and are always tied to the local mdio pins, which may not be the
88 * same as system mdio bus, used for controlling the external PHYs, for eg.
90 int fsl_pq_local_mdio_read(struct fsl_pq_mdio __iomem *regs,
91 int mii_id, int regnum)
95 /* Set the PHY address and the register address we want to read */
96 out_be32(®s->miimadd, (mii_id << 8) | regnum);
98 /* Clear miimcom, and then initiate a read */
99 out_be32(®s->miimcom, 0);
100 out_be32(®s->miimcom, MII_READ_COMMAND);
102 /* Wait for the transaction to finish */
103 while (in_be32(®s->miimind) & (MIIMIND_NOTVALID | MIIMIND_BUSY))
106 /* Grab the value of the register from miimstat */
107 value = in_be32(®s->miimstat);
112 static struct fsl_pq_mdio __iomem *fsl_pq_mdio_get_regs(struct mii_bus *bus)
114 struct fsl_pq_mdio_priv *priv = bus->priv;
120 * Write value to the PHY at mii_id at register regnum,
121 * on the bus, waiting until the write is done before returning.
123 int fsl_pq_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 value)
125 struct fsl_pq_mdio __iomem *regs = fsl_pq_mdio_get_regs(bus);
127 /* Write to the local MII regs */
128 return fsl_pq_local_mdio_write(regs, mii_id, regnum, value);
132 * Read the bus for PHY at addr mii_id, register regnum, and
133 * return the value. Clears miimcom first.
135 int fsl_pq_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
137 struct fsl_pq_mdio __iomem *regs = fsl_pq_mdio_get_regs(bus);
139 /* Read the local MII regs */
140 return fsl_pq_local_mdio_read(regs, mii_id, regnum);
143 /* Reset the MIIM registers, and wait for the bus to free */
144 static int fsl_pq_mdio_reset(struct mii_bus *bus)
146 struct fsl_pq_mdio __iomem *regs = fsl_pq_mdio_get_regs(bus);
147 int timeout = PHY_INIT_TIMEOUT;
149 mutex_lock(&bus->mdio_lock);
151 /* Reset the management interface */
152 out_be32(®s->miimcfg, MIIMCFG_RESET);
154 /* Setup the MII Mgmt clock speed */
155 out_be32(®s->miimcfg, MIIMCFG_INIT_VALUE);
157 /* Wait until the bus is free */
158 while ((in_be32(®s->miimind) & MIIMIND_BUSY) && timeout--)
161 mutex_unlock(&bus->mdio_lock);
164 printk(KERN_ERR "%s: The MII Bus is stuck!\n",
172 void fsl_pq_mdio_bus_name(char *name, struct device_node *np)
175 u64 taddr = OF_BAD_ADDR;
177 addr = of_get_address(np, 0, NULL, NULL);
179 taddr = of_translate_address(np, addr);
181 snprintf(name, MII_BUS_ID_SIZE, "%s@%llx", np->name,
182 (unsigned long long)taddr);
184 EXPORT_SYMBOL_GPL(fsl_pq_mdio_bus_name);
186 /* Scan the bus in reverse, looking for an empty spot */
187 static int fsl_pq_mdio_find_free(struct mii_bus *new_bus)
191 for (i = PHY_MAX_ADDR; i > 0; i--) {
194 if (get_phy_id(new_bus, i, &phy_id))
197 if (phy_id == 0xffffffff)
205 #if defined(CONFIG_GIANFAR) || defined(CONFIG_GIANFAR_MODULE)
206 static u32 __iomem *get_gfar_tbipa(struct fsl_pq_mdio __iomem *regs, struct device_node *np)
208 struct gfar __iomem *enet_regs;
211 * This is mildly evil, but so is our hardware for doing this.
212 * Also, we have to cast back to struct gfar because of
213 * definition weirdness done in gianfar.h.
215 if(of_device_is_compatible(np, "fsl,gianfar-mdio") ||
216 of_device_is_compatible(np, "fsl,gianfar-tbi") ||
217 of_device_is_compatible(np, "gianfar")) {
218 enet_regs = (struct gfar __iomem *)regs;
219 return &enet_regs->tbipa;
220 } else if (of_device_is_compatible(np, "fsl,etsec2-mdio") ||
221 of_device_is_compatible(np, "fsl,etsec2-tbi")) {
222 return of_iomap(np, 1);
229 #if defined(CONFIG_UCC_GETH) || defined(CONFIG_UCC_GETH_MODULE)
230 static int get_ucc_id_for_range(u64 start, u64 end, u32 *ucc_id)
232 struct device_node *np = NULL;
235 for_each_compatible_node(np, NULL, "ucc_geth") {
236 struct resource tempres;
238 err = of_address_to_resource(np, 0, &tempres);
242 /* if our mdio regs fall within this UCC regs range */
243 if ((start >= tempres.start) && (end <= tempres.end)) {
244 /* Find the id of the UCC */
247 id = of_get_property(np, "cell-index", NULL);
249 id = of_get_property(np, "device-id", NULL);
268 static int fsl_pq_mdio_probe(struct platform_device *ofdev)
270 struct device_node *np = ofdev->dev.of_node;
271 struct device_node *tbi;
272 struct fsl_pq_mdio_priv *priv;
273 struct fsl_pq_mdio __iomem *regs = NULL;
276 struct mii_bus *new_bus;
279 u64 addr = 0, size = 0;
282 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
286 new_bus = mdiobus_alloc();
292 new_bus->name = "Freescale PowerQUICC MII Bus",
293 new_bus->read = &fsl_pq_mdio_read,
294 new_bus->write = &fsl_pq_mdio_write,
295 new_bus->reset = &fsl_pq_mdio_reset,
296 new_bus->priv = priv;
297 fsl_pq_mdio_bus_name(new_bus->id, np);
299 addrp = of_get_address(np, 0, &size, NULL);
305 /* Set the PHY base address */
306 addr = of_translate_address(np, addrp);
307 if (addr == OF_BAD_ADDR) {
312 map = ioremap(addr, size);
319 if (of_device_is_compatible(np, "fsl,gianfar-mdio") ||
320 of_device_is_compatible(np, "fsl,gianfar-tbi") ||
321 of_device_is_compatible(np, "fsl,ucc-mdio") ||
322 of_device_is_compatible(np, "ucc_geth_phy"))
323 map -= offsetof(struct fsl_pq_mdio, miimcfg);
327 new_bus->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
329 if (NULL == new_bus->irq) {
334 new_bus->parent = &ofdev->dev;
335 dev_set_drvdata(&ofdev->dev, new_bus);
337 if (of_device_is_compatible(np, "fsl,gianfar-mdio") ||
338 of_device_is_compatible(np, "fsl,gianfar-tbi") ||
339 of_device_is_compatible(np, "fsl,etsec2-mdio") ||
340 of_device_is_compatible(np, "fsl,etsec2-tbi") ||
341 of_device_is_compatible(np, "gianfar")) {
342 #if defined(CONFIG_GIANFAR) || defined(CONFIG_GIANFAR_MODULE)
343 tbipa = get_gfar_tbipa(regs, np);
352 } else if (of_device_is_compatible(np, "fsl,ucc-mdio") ||
353 of_device_is_compatible(np, "ucc_geth_phy")) {
354 #if defined(CONFIG_UCC_GETH) || defined(CONFIG_UCC_GETH_MODULE)
356 static u32 mii_mng_master;
358 tbipa = ®s->utbipar;
360 if ((err = get_ucc_id_for_range(addr, addr + size, &id)))
363 if (!mii_mng_master) {
365 ucc_set_qe_mux_mii_mng(id - 1);
376 for_each_child_of_node(np, tbi) {
377 if (!strncmp(tbi->type, "tbi-phy", 8))
382 const u32 *prop = of_get_property(tbi, "reg", NULL);
391 tbiaddr = fsl_pq_mdio_find_free(new_bus);
395 * We define TBIPA at 0 to be illegal, opting to fail for boards that
396 * have PHYs at 1-31, rather than change tbipa and rescan.
404 out_be32(tbipa, tbiaddr);
406 err = of_mdiobus_register(new_bus, np);
408 printk (KERN_ERR "%s: Cannot register as MDIO bus\n",
427 static int fsl_pq_mdio_remove(struct platform_device *ofdev)
429 struct device *device = &ofdev->dev;
430 struct mii_bus *bus = dev_get_drvdata(device);
431 struct fsl_pq_mdio_priv *priv = bus->priv;
433 mdiobus_unregister(bus);
435 dev_set_drvdata(device, NULL);
445 static struct of_device_id fsl_pq_mdio_match[] = {
448 .compatible = "ucc_geth_phy",
452 .compatible = "gianfar",
455 .compatible = "fsl,ucc-mdio",
458 .compatible = "fsl,gianfar-tbi",
461 .compatible = "fsl,gianfar-mdio",
464 .compatible = "fsl,etsec2-tbi",
467 .compatible = "fsl,etsec2-mdio",
471 MODULE_DEVICE_TABLE(of, fsl_pq_mdio_match);
473 static struct platform_driver fsl_pq_mdio_driver = {
475 .name = "fsl-pq_mdio",
476 .owner = THIS_MODULE,
477 .of_match_table = fsl_pq_mdio_match,
479 .probe = fsl_pq_mdio_probe,
480 .remove = fsl_pq_mdio_remove,
483 int __init fsl_pq_mdio_init(void)
485 return platform_driver_register(&fsl_pq_mdio_driver);
487 module_init(fsl_pq_mdio_init);
489 void fsl_pq_mdio_exit(void)
491 platform_driver_unregister(&fsl_pq_mdio_driver);
493 module_exit(fsl_pq_mdio_exit);
494 MODULE_LICENSE("GPL");