2 * drivers/net/gianfar.c
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
10 * Maintainer: Kumar Gala
12 * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
13 * Copyright (c) 2007 MontaVista Software, Inc.
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * Gianfar: AKA Lambda Draconis, "Dragon"
28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
35 * last descriptor of the ring.
37 * When a packet is received, the RXF bit in the
38 * IEVENT register is set, triggering an interrupt when the
39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
42 * of frames or amount of time have passed). In NAPI, the
43 * interrupt handler will signal there is work to be done, and
44 * exit. This method will start at the last known empty
45 * descriptor, and process every subsequent descriptor until there
46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
64 #include <linux/kernel.h>
65 #include <linux/string.h>
66 #include <linux/errno.h>
67 #include <linux/unistd.h>
68 #include <linux/slab.h>
69 #include <linux/interrupt.h>
70 #include <linux/init.h>
71 #include <linux/delay.h>
72 #include <linux/netdevice.h>
73 #include <linux/etherdevice.h>
74 #include <linux/skbuff.h>
75 #include <linux/if_vlan.h>
76 #include <linux/spinlock.h>
78 #include <linux/of_mdio.h>
79 #include <linux/of_platform.h>
81 #include <linux/tcp.h>
82 #include <linux/udp.h>
87 #include <asm/uaccess.h>
88 #include <linux/module.h>
89 #include <linux/dma-mapping.h>
90 #include <linux/crc32.h>
91 #include <linux/mii.h>
92 #include <linux/phy.h>
93 #include <linux/phy_fixed.h>
97 #include "fsl_pq_mdio.h"
99 #define TX_TIMEOUT (1*HZ)
100 #undef BRIEF_GFAR_ERRORS
101 #undef VERBOSE_GFAR_ERRORS
103 const char gfar_driver_name[] = "Gianfar Ethernet";
104 const char gfar_driver_version[] = "1.3";
106 static int gfar_enet_open(struct net_device *dev);
107 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
108 static void gfar_reset_task(struct work_struct *work);
109 static void gfar_timeout(struct net_device *dev);
110 static int gfar_close(struct net_device *dev);
111 struct sk_buff *gfar_new_skb(struct net_device *dev);
112 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
113 struct sk_buff *skb);
114 static int gfar_set_mac_address(struct net_device *dev);
115 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
116 static irqreturn_t gfar_error(int irq, void *dev_id);
117 static irqreturn_t gfar_transmit(int irq, void *dev_id);
118 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
119 static void adjust_link(struct net_device *dev);
120 static void init_registers(struct net_device *dev);
121 static int init_phy(struct net_device *dev);
122 static int gfar_probe(struct of_device *ofdev,
123 const struct of_device_id *match);
124 static int gfar_remove(struct of_device *ofdev);
125 static void free_skb_resources(struct gfar_private *priv);
126 static void gfar_set_multi(struct net_device *dev);
127 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
128 static void gfar_configure_serdes(struct net_device *dev);
129 static int gfar_poll(struct napi_struct *napi, int budget);
130 #ifdef CONFIG_NET_POLL_CONTROLLER
131 static void gfar_netpoll(struct net_device *dev);
133 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
134 static int gfar_clean_tx_ring(struct net_device *dev);
135 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
137 static void gfar_vlan_rx_register(struct net_device *netdev,
138 struct vlan_group *grp);
139 void gfar_halt(struct net_device *dev);
140 static void gfar_halt_nodisable(struct net_device *dev);
141 void gfar_start(struct net_device *dev);
142 static void gfar_clear_exact_match(struct net_device *dev);
143 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
144 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
146 MODULE_AUTHOR("Freescale Semiconductor, Inc");
147 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
148 MODULE_LICENSE("GPL");
150 static const struct net_device_ops gfar_netdev_ops = {
151 .ndo_open = gfar_enet_open,
152 .ndo_start_xmit = gfar_start_xmit,
153 .ndo_stop = gfar_close,
154 .ndo_change_mtu = gfar_change_mtu,
155 .ndo_set_multicast_list = gfar_set_multi,
156 .ndo_tx_timeout = gfar_timeout,
157 .ndo_do_ioctl = gfar_ioctl,
158 .ndo_vlan_rx_register = gfar_vlan_rx_register,
159 .ndo_set_mac_address = eth_mac_addr,
160 .ndo_validate_addr = eth_validate_addr,
161 #ifdef CONFIG_NET_POLL_CONTROLLER
162 .ndo_poll_controller = gfar_netpoll,
166 /* Returns 1 if incoming frames use an FCB */
167 static inline int gfar_uses_fcb(struct gfar_private *priv)
169 return priv->vlgrp || priv->rx_csum_enable;
172 static int gfar_of_init(struct net_device *dev)
176 const void *mac_addr;
179 struct gfar_private *priv = netdev_priv(dev);
180 struct device_node *np = priv->node;
182 const u32 *stash_len;
183 const u32 *stash_idx;
185 if (!np || !of_device_is_available(np))
188 /* get a pointer to the register memory */
189 addr = of_translate_address(np, of_get_address(np, 0, &size, NULL));
190 priv->regs = ioremap(addr, size);
192 if (priv->regs == NULL)
195 priv->interruptTransmit = irq_of_parse_and_map(np, 0);
197 model = of_get_property(np, "model", NULL);
199 /* If we aren't the FEC we have multiple interrupts */
200 if (model && strcasecmp(model, "FEC")) {
201 priv->interruptReceive = irq_of_parse_and_map(np, 1);
203 priv->interruptError = irq_of_parse_and_map(np, 2);
205 if (priv->interruptTransmit < 0 ||
206 priv->interruptReceive < 0 ||
207 priv->interruptError < 0) {
213 stash = of_get_property(np, "bd-stash", NULL);
216 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
217 priv->bd_stash_en = 1;
220 stash_len = of_get_property(np, "rx-stash-len", NULL);
223 priv->rx_stash_size = *stash_len;
225 stash_idx = of_get_property(np, "rx-stash-idx", NULL);
228 priv->rx_stash_index = *stash_idx;
230 if (stash_len || stash_idx)
231 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
233 mac_addr = of_get_mac_address(np);
235 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
237 if (model && !strcasecmp(model, "TSEC"))
239 FSL_GIANFAR_DEV_HAS_GIGABIT |
240 FSL_GIANFAR_DEV_HAS_COALESCE |
241 FSL_GIANFAR_DEV_HAS_RMON |
242 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
243 if (model && !strcasecmp(model, "eTSEC"))
245 FSL_GIANFAR_DEV_HAS_GIGABIT |
246 FSL_GIANFAR_DEV_HAS_COALESCE |
247 FSL_GIANFAR_DEV_HAS_RMON |
248 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
249 FSL_GIANFAR_DEV_HAS_PADDING |
250 FSL_GIANFAR_DEV_HAS_CSUM |
251 FSL_GIANFAR_DEV_HAS_VLAN |
252 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
253 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH;
255 ctype = of_get_property(np, "phy-connection-type", NULL);
257 /* We only care about rgmii-id. The rest are autodetected */
258 if (ctype && !strcmp(ctype, "rgmii-id"))
259 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
261 priv->interface = PHY_INTERFACE_MODE_MII;
263 if (of_get_property(np, "fsl,magic-packet", NULL))
264 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
266 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
268 /* Find the TBI PHY. If it's not there, we don't support SGMII */
269 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
278 /* Ioctl MII Interface */
279 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
281 struct gfar_private *priv = netdev_priv(dev);
283 if (!netif_running(dev))
289 return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
292 /* Set up the ethernet device structure, private data,
293 * and anything else we need before we start */
294 static int gfar_probe(struct of_device *ofdev,
295 const struct of_device_id *match)
298 struct net_device *dev = NULL;
299 struct gfar_private *priv = NULL;
303 /* Create an ethernet device instance */
304 dev = alloc_etherdev(sizeof (*priv));
309 priv = netdev_priv(dev);
312 priv->node = ofdev->node;
313 SET_NETDEV_DEV(dev, &ofdev->dev);
315 err = gfar_of_init(dev);
320 spin_lock_init(&priv->txlock);
321 spin_lock_init(&priv->rxlock);
322 spin_lock_init(&priv->bflock);
323 INIT_WORK(&priv->reset_task, gfar_reset_task);
325 dev_set_drvdata(&ofdev->dev, priv);
327 /* Stop the DMA engine now, in case it was running before */
328 /* (The firmware could have used it, and left it running). */
331 /* Reset MAC layer */
332 gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
334 /* We need to delay at least 3 TX clocks */
337 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
338 gfar_write(&priv->regs->maccfg1, tempval);
340 /* Initialize MACCFG2. */
341 gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
343 /* Initialize ECNTRL */
344 gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
346 /* Set the dev->base_addr to the gfar reg region */
347 dev->base_addr = (unsigned long) (priv->regs);
349 SET_NETDEV_DEV(dev, &ofdev->dev);
351 /* Fill in the dev structure */
352 dev->watchdog_timeo = TX_TIMEOUT;
353 netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT);
356 dev->netdev_ops = &gfar_netdev_ops;
357 dev->ethtool_ops = &gfar_ethtool_ops;
359 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
360 priv->rx_csum_enable = 1;
361 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;
363 priv->rx_csum_enable = 0;
367 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)
368 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
370 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
371 priv->extended_hash = 1;
372 priv->hash_width = 9;
374 priv->hash_regs[0] = &priv->regs->igaddr0;
375 priv->hash_regs[1] = &priv->regs->igaddr1;
376 priv->hash_regs[2] = &priv->regs->igaddr2;
377 priv->hash_regs[3] = &priv->regs->igaddr3;
378 priv->hash_regs[4] = &priv->regs->igaddr4;
379 priv->hash_regs[5] = &priv->regs->igaddr5;
380 priv->hash_regs[6] = &priv->regs->igaddr6;
381 priv->hash_regs[7] = &priv->regs->igaddr7;
382 priv->hash_regs[8] = &priv->regs->gaddr0;
383 priv->hash_regs[9] = &priv->regs->gaddr1;
384 priv->hash_regs[10] = &priv->regs->gaddr2;
385 priv->hash_regs[11] = &priv->regs->gaddr3;
386 priv->hash_regs[12] = &priv->regs->gaddr4;
387 priv->hash_regs[13] = &priv->regs->gaddr5;
388 priv->hash_regs[14] = &priv->regs->gaddr6;
389 priv->hash_regs[15] = &priv->regs->gaddr7;
392 priv->extended_hash = 0;
393 priv->hash_width = 8;
395 priv->hash_regs[0] = &priv->regs->gaddr0;
396 priv->hash_regs[1] = &priv->regs->gaddr1;
397 priv->hash_regs[2] = &priv->regs->gaddr2;
398 priv->hash_regs[3] = &priv->regs->gaddr3;
399 priv->hash_regs[4] = &priv->regs->gaddr4;
400 priv->hash_regs[5] = &priv->regs->gaddr5;
401 priv->hash_regs[6] = &priv->regs->gaddr6;
402 priv->hash_regs[7] = &priv->regs->gaddr7;
405 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
406 priv->padding = DEFAULT_PADDING;
410 if (dev->features & NETIF_F_IP_CSUM)
411 dev->hard_header_len += GMAC_FCB_LEN;
413 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
414 priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
415 priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
416 priv->num_txbdfree = DEFAULT_TX_RING_SIZE;
418 priv->txcoalescing = DEFAULT_TX_COALESCE;
419 priv->txic = DEFAULT_TXIC;
420 priv->rxcoalescing = DEFAULT_RX_COALESCE;
421 priv->rxic = DEFAULT_RXIC;
423 /* Enable most messages by default */
424 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
426 /* Carrier starts down, phylib will bring it up */
427 netif_carrier_off(dev);
429 err = register_netdev(dev);
432 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
437 device_init_wakeup(&dev->dev,
438 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
440 /* fill out IRQ number and name fields */
441 len_devname = strlen(dev->name);
442 strncpy(&priv->int_name_tx[0], dev->name, len_devname);
443 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
444 strncpy(&priv->int_name_tx[len_devname],
445 "_tx", sizeof("_tx") + 1);
447 strncpy(&priv->int_name_rx[0], dev->name, len_devname);
448 strncpy(&priv->int_name_rx[len_devname],
449 "_rx", sizeof("_rx") + 1);
451 strncpy(&priv->int_name_er[0], dev->name, len_devname);
452 strncpy(&priv->int_name_er[len_devname],
453 "_er", sizeof("_er") + 1);
455 priv->int_name_tx[len_devname] = '\0';
457 /* Create all the sysfs files */
458 gfar_init_sysfs(dev);
460 /* Print out the device info */
461 printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
463 /* Even more device info helps when determining which kernel */
464 /* provided which set of benchmarks. */
465 printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
466 printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
467 dev->name, priv->rx_ring_size, priv->tx_ring_size);
475 of_node_put(priv->phy_node);
477 of_node_put(priv->tbi_node);
482 static int gfar_remove(struct of_device *ofdev)
484 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
487 of_node_put(priv->phy_node);
489 of_node_put(priv->tbi_node);
491 dev_set_drvdata(&ofdev->dev, NULL);
494 free_netdev(priv->ndev);
500 static int gfar_suspend(struct of_device *ofdev, pm_message_t state)
502 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
503 struct net_device *dev = priv->ndev;
507 int magic_packet = priv->wol_en &&
508 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
510 netif_device_detach(dev);
512 if (netif_running(dev)) {
513 spin_lock_irqsave(&priv->txlock, flags);
514 spin_lock(&priv->rxlock);
516 gfar_halt_nodisable(dev);
518 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
519 tempval = gfar_read(&priv->regs->maccfg1);
521 tempval &= ~MACCFG1_TX_EN;
524 tempval &= ~MACCFG1_RX_EN;
526 gfar_write(&priv->regs->maccfg1, tempval);
528 spin_unlock(&priv->rxlock);
529 spin_unlock_irqrestore(&priv->txlock, flags);
531 napi_disable(&priv->napi);
534 /* Enable interrupt on Magic Packet */
535 gfar_write(&priv->regs->imask, IMASK_MAG);
537 /* Enable Magic Packet mode */
538 tempval = gfar_read(&priv->regs->maccfg2);
539 tempval |= MACCFG2_MPEN;
540 gfar_write(&priv->regs->maccfg2, tempval);
542 phy_stop(priv->phydev);
549 static int gfar_resume(struct of_device *ofdev)
551 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
552 struct net_device *dev = priv->ndev;
555 int magic_packet = priv->wol_en &&
556 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
558 if (!netif_running(dev)) {
559 netif_device_attach(dev);
563 if (!magic_packet && priv->phydev)
564 phy_start(priv->phydev);
566 /* Disable Magic Packet mode, in case something
570 spin_lock_irqsave(&priv->txlock, flags);
571 spin_lock(&priv->rxlock);
573 tempval = gfar_read(&priv->regs->maccfg2);
574 tempval &= ~MACCFG2_MPEN;
575 gfar_write(&priv->regs->maccfg2, tempval);
579 spin_unlock(&priv->rxlock);
580 spin_unlock_irqrestore(&priv->txlock, flags);
582 netif_device_attach(dev);
584 napi_enable(&priv->napi);
589 #define gfar_suspend NULL
590 #define gfar_resume NULL
593 /* Reads the controller's registers to determine what interface
594 * connects it to the PHY.
596 static phy_interface_t gfar_get_interface(struct net_device *dev)
598 struct gfar_private *priv = netdev_priv(dev);
599 u32 ecntrl = gfar_read(&priv->regs->ecntrl);
601 if (ecntrl & ECNTRL_SGMII_MODE)
602 return PHY_INTERFACE_MODE_SGMII;
604 if (ecntrl & ECNTRL_TBI_MODE) {
605 if (ecntrl & ECNTRL_REDUCED_MODE)
606 return PHY_INTERFACE_MODE_RTBI;
608 return PHY_INTERFACE_MODE_TBI;
611 if (ecntrl & ECNTRL_REDUCED_MODE) {
612 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
613 return PHY_INTERFACE_MODE_RMII;
615 phy_interface_t interface = priv->interface;
618 * This isn't autodetected right now, so it must
619 * be set by the device tree or platform code.
621 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
622 return PHY_INTERFACE_MODE_RGMII_ID;
624 return PHY_INTERFACE_MODE_RGMII;
628 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
629 return PHY_INTERFACE_MODE_GMII;
631 return PHY_INTERFACE_MODE_MII;
635 /* Initializes driver's PHY state, and attaches to the PHY.
636 * Returns 0 on success.
638 static int init_phy(struct net_device *dev)
640 struct gfar_private *priv = netdev_priv(dev);
641 uint gigabit_support =
642 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
643 SUPPORTED_1000baseT_Full : 0;
644 phy_interface_t interface;
648 priv->oldduplex = -1;
650 interface = gfar_get_interface(dev);
652 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
655 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
658 dev_err(&dev->dev, "could not attach to PHY\n");
662 if (interface == PHY_INTERFACE_MODE_SGMII)
663 gfar_configure_serdes(dev);
665 /* Remove any features not supported by the controller */
666 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
667 priv->phydev->advertising = priv->phydev->supported;
673 * Initialize TBI PHY interface for communicating with the
674 * SERDES lynx PHY on the chip. We communicate with this PHY
675 * through the MDIO bus on each controller, treating it as a
676 * "normal" PHY at the address found in the TBIPA register. We assume
677 * that the TBIPA register is valid. Either the MDIO bus code will set
678 * it to a value that doesn't conflict with other PHYs on the bus, or the
679 * value doesn't matter, as there are no other PHYs on the bus.
681 static void gfar_configure_serdes(struct net_device *dev)
683 struct gfar_private *priv = netdev_priv(dev);
684 struct phy_device *tbiphy;
686 if (!priv->tbi_node) {
687 dev_warn(&dev->dev, "error: SGMII mode requires that the "
688 "device tree specify a tbi-handle\n");
692 tbiphy = of_phy_find_device(priv->tbi_node);
694 dev_err(&dev->dev, "error: Could not get TBI device\n");
699 * If the link is already up, we must already be ok, and don't need to
700 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
701 * everything for us? Resetting it takes the link down and requires
702 * several seconds for it to come back.
704 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
707 /* Single clk mode, mii mode off(for serdes communication) */
708 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
710 phy_write(tbiphy, MII_ADVERTISE,
711 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
712 ADVERTISE_1000XPSE_ASYM);
714 phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE |
715 BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
718 static void init_registers(struct net_device *dev)
720 struct gfar_private *priv = netdev_priv(dev);
723 gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
725 /* Initialize IMASK */
726 gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
728 /* Init hash registers to zero */
729 gfar_write(&priv->regs->igaddr0, 0);
730 gfar_write(&priv->regs->igaddr1, 0);
731 gfar_write(&priv->regs->igaddr2, 0);
732 gfar_write(&priv->regs->igaddr3, 0);
733 gfar_write(&priv->regs->igaddr4, 0);
734 gfar_write(&priv->regs->igaddr5, 0);
735 gfar_write(&priv->regs->igaddr6, 0);
736 gfar_write(&priv->regs->igaddr7, 0);
738 gfar_write(&priv->regs->gaddr0, 0);
739 gfar_write(&priv->regs->gaddr1, 0);
740 gfar_write(&priv->regs->gaddr2, 0);
741 gfar_write(&priv->regs->gaddr3, 0);
742 gfar_write(&priv->regs->gaddr4, 0);
743 gfar_write(&priv->regs->gaddr5, 0);
744 gfar_write(&priv->regs->gaddr6, 0);
745 gfar_write(&priv->regs->gaddr7, 0);
747 /* Zero out the rmon mib registers if it has them */
748 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
749 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
751 /* Mask off the CAM interrupts */
752 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
753 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
756 /* Initialize the max receive buffer length */
757 gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
759 /* Initialize the Minimum Frame Length Register */
760 gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
764 /* Halt the receive and transmit queues */
765 static void gfar_halt_nodisable(struct net_device *dev)
767 struct gfar_private *priv = netdev_priv(dev);
768 struct gfar __iomem *regs = priv->regs;
771 /* Mask all interrupts */
772 gfar_write(®s->imask, IMASK_INIT_CLEAR);
774 /* Clear all interrupts */
775 gfar_write(®s->ievent, IEVENT_INIT_CLEAR);
777 /* Stop the DMA, and wait for it to stop */
778 tempval = gfar_read(&priv->regs->dmactrl);
779 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
780 != (DMACTRL_GRS | DMACTRL_GTS)) {
781 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
782 gfar_write(&priv->regs->dmactrl, tempval);
784 while (!(gfar_read(&priv->regs->ievent) &
785 (IEVENT_GRSC | IEVENT_GTSC)))
790 /* Halt the receive and transmit queues */
791 void gfar_halt(struct net_device *dev)
793 struct gfar_private *priv = netdev_priv(dev);
794 struct gfar __iomem *regs = priv->regs;
797 gfar_halt_nodisable(dev);
799 /* Disable Rx and Tx */
800 tempval = gfar_read(®s->maccfg1);
801 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
802 gfar_write(®s->maccfg1, tempval);
805 void stop_gfar(struct net_device *dev)
807 struct gfar_private *priv = netdev_priv(dev);
808 struct gfar __iomem *regs = priv->regs;
811 phy_stop(priv->phydev);
814 spin_lock_irqsave(&priv->txlock, flags);
815 spin_lock(&priv->rxlock);
819 spin_unlock(&priv->rxlock);
820 spin_unlock_irqrestore(&priv->txlock, flags);
823 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
824 free_irq(priv->interruptError, dev);
825 free_irq(priv->interruptTransmit, dev);
826 free_irq(priv->interruptReceive, dev);
828 free_irq(priv->interruptTransmit, dev);
831 free_skb_resources(priv);
833 dma_free_coherent(&priv->ofdev->dev,
834 sizeof(struct txbd8)*priv->tx_ring_size
835 + sizeof(struct rxbd8)*priv->rx_ring_size,
837 gfar_read(®s->tbase0));
840 /* If there are any tx skbs or rx skbs still around, free them.
841 * Then free tx_skbuff and rx_skbuff */
842 static void free_skb_resources(struct gfar_private *priv)
848 /* Go through all the buffer descriptors and free their data buffers */
849 txbdp = priv->tx_bd_base;
851 for (i = 0; i < priv->tx_ring_size; i++) {
852 if (!priv->tx_skbuff[i])
855 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
856 txbdp->length, DMA_TO_DEVICE);
858 for (j = 0; j < skb_shinfo(priv->tx_skbuff[i])->nr_frags; j++) {
860 dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
861 txbdp->length, DMA_TO_DEVICE);
864 dev_kfree_skb_any(priv->tx_skbuff[i]);
865 priv->tx_skbuff[i] = NULL;
868 kfree(priv->tx_skbuff);
870 rxbdp = priv->rx_bd_base;
872 /* rx_skbuff is not guaranteed to be allocated, so only
873 * free it and its contents if it is allocated */
874 if(priv->rx_skbuff != NULL) {
875 for (i = 0; i < priv->rx_ring_size; i++) {
876 if (priv->rx_skbuff[i]) {
877 dma_unmap_single(&priv->ofdev->dev, rxbdp->bufPtr,
878 priv->rx_buffer_size,
881 dev_kfree_skb_any(priv->rx_skbuff[i]);
882 priv->rx_skbuff[i] = NULL;
891 kfree(priv->rx_skbuff);
895 void gfar_start(struct net_device *dev)
897 struct gfar_private *priv = netdev_priv(dev);
898 struct gfar __iomem *regs = priv->regs;
901 /* Enable Rx and Tx in MACCFG1 */
902 tempval = gfar_read(®s->maccfg1);
903 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
904 gfar_write(®s->maccfg1, tempval);
906 /* Initialize DMACTRL to have WWR and WOP */
907 tempval = gfar_read(&priv->regs->dmactrl);
908 tempval |= DMACTRL_INIT_SETTINGS;
909 gfar_write(&priv->regs->dmactrl, tempval);
911 /* Make sure we aren't stopped */
912 tempval = gfar_read(&priv->regs->dmactrl);
913 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
914 gfar_write(&priv->regs->dmactrl, tempval);
916 /* Clear THLT/RHLT, so that the DMA starts polling now */
917 gfar_write(®s->tstat, TSTAT_CLEAR_THALT);
918 gfar_write(®s->rstat, RSTAT_CLEAR_RHALT);
920 /* Unmask the interrupts we look for */
921 gfar_write(®s->imask, IMASK_DEFAULT);
923 dev->trans_start = jiffies;
926 /* Bring the controller up and running */
927 int startup_gfar(struct net_device *dev)
934 struct gfar_private *priv = netdev_priv(dev);
935 struct gfar __iomem *regs = priv->regs;
940 gfar_write(®s->imask, IMASK_INIT_CLEAR);
942 /* Allocate memory for the buffer descriptors */
943 vaddr = (unsigned long) dma_alloc_coherent(&priv->ofdev->dev,
944 sizeof (struct txbd8) * priv->tx_ring_size +
945 sizeof (struct rxbd8) * priv->rx_ring_size,
949 if (netif_msg_ifup(priv))
950 printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
955 priv->tx_bd_base = (struct txbd8 *) vaddr;
957 /* enet DMA only understands physical addresses */
958 gfar_write(®s->tbase0, addr);
960 /* Start the rx descriptor ring where the tx ring leaves off */
961 addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
962 vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
963 priv->rx_bd_base = (struct rxbd8 *) vaddr;
964 gfar_write(®s->rbase0, addr);
966 /* Setup the skbuff rings */
968 (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
969 priv->tx_ring_size, GFP_KERNEL);
971 if (NULL == priv->tx_skbuff) {
972 if (netif_msg_ifup(priv))
973 printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
979 for (i = 0; i < priv->tx_ring_size; i++)
980 priv->tx_skbuff[i] = NULL;
983 (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
984 priv->rx_ring_size, GFP_KERNEL);
986 if (NULL == priv->rx_skbuff) {
987 if (netif_msg_ifup(priv))
988 printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
994 for (i = 0; i < priv->rx_ring_size; i++)
995 priv->rx_skbuff[i] = NULL;
997 /* Initialize some variables in our dev structure */
998 priv->num_txbdfree = priv->tx_ring_size;
999 priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
1000 priv->cur_rx = priv->rx_bd_base;
1001 priv->skb_curtx = priv->skb_dirtytx = 0;
1002 priv->skb_currx = 0;
1004 /* Initialize Transmit Descriptor Ring */
1005 txbdp = priv->tx_bd_base;
1006 for (i = 0; i < priv->tx_ring_size; i++) {
1012 /* Set the last descriptor in the ring to indicate wrap */
1014 txbdp->status |= TXBD_WRAP;
1016 rxbdp = priv->rx_bd_base;
1017 for (i = 0; i < priv->rx_ring_size; i++) {
1018 struct sk_buff *skb;
1020 skb = gfar_new_skb(dev);
1023 printk(KERN_ERR "%s: Can't allocate RX buffers\n",
1026 goto err_rxalloc_fail;
1029 priv->rx_skbuff[i] = skb;
1031 gfar_new_rxbdp(dev, rxbdp, skb);
1036 /* Set the last descriptor in the ring to wrap */
1038 rxbdp->status |= RXBD_WRAP;
1040 /* If the device has multiple interrupts, register for
1041 * them. Otherwise, only register for the one */
1042 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1043 /* Install our interrupt handlers for Error,
1044 * Transmit, and Receive */
1045 if (request_irq(priv->interruptError, gfar_error,
1046 0, priv->int_name_er, dev) < 0) {
1047 if (netif_msg_intr(priv))
1048 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1049 dev->name, priv->interruptError);
1055 if (request_irq(priv->interruptTransmit, gfar_transmit,
1056 0, priv->int_name_tx, dev) < 0) {
1057 if (netif_msg_intr(priv))
1058 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1059 dev->name, priv->interruptTransmit);
1066 if (request_irq(priv->interruptReceive, gfar_receive,
1067 0, priv->int_name_rx, dev) < 0) {
1068 if (netif_msg_intr(priv))
1069 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
1070 dev->name, priv->interruptReceive);
1076 if (request_irq(priv->interruptTransmit, gfar_interrupt,
1077 0, priv->int_name_tx, dev) < 0) {
1078 if (netif_msg_intr(priv))
1079 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1080 dev->name, priv->interruptTransmit);
1087 phy_start(priv->phydev);
1089 /* Configure the coalescing support */
1090 gfar_write(®s->txic, 0);
1091 if (priv->txcoalescing)
1092 gfar_write(®s->txic, priv->txic);
1094 gfar_write(®s->rxic, 0);
1095 if (priv->rxcoalescing)
1096 gfar_write(®s->rxic, priv->rxic);
1098 if (priv->rx_csum_enable)
1099 rctrl |= RCTRL_CHECKSUMMING;
1101 if (priv->extended_hash) {
1102 rctrl |= RCTRL_EXTHASH;
1104 gfar_clear_exact_match(dev);
1105 rctrl |= RCTRL_EMEN;
1108 if (priv->padding) {
1109 rctrl &= ~RCTRL_PAL_MASK;
1110 rctrl |= RCTRL_PADDING(priv->padding);
1113 /* Init rctrl based on our settings */
1114 gfar_write(&priv->regs->rctrl, rctrl);
1116 if (dev->features & NETIF_F_IP_CSUM)
1117 gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
1119 /* Set the extraction length and index */
1120 attrs = ATTRELI_EL(priv->rx_stash_size) |
1121 ATTRELI_EI(priv->rx_stash_index);
1123 gfar_write(&priv->regs->attreli, attrs);
1125 /* Start with defaults, and add stashing or locking
1126 * depending on the approprate variables */
1127 attrs = ATTR_INIT_SETTINGS;
1129 if (priv->bd_stash_en)
1130 attrs |= ATTR_BDSTASH;
1132 if (priv->rx_stash_size != 0)
1133 attrs |= ATTR_BUFSTASH;
1135 gfar_write(&priv->regs->attr, attrs);
1137 gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
1138 gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
1139 gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
1141 /* Start the controller */
1147 free_irq(priv->interruptTransmit, dev);
1149 free_irq(priv->interruptError, dev);
1153 free_skb_resources(priv);
1155 dma_free_coherent(&priv->ofdev->dev,
1156 sizeof(struct txbd8)*priv->tx_ring_size
1157 + sizeof(struct rxbd8)*priv->rx_ring_size,
1159 gfar_read(®s->tbase0));
1164 /* Called when something needs to use the ethernet device */
1165 /* Returns 0 for success. */
1166 static int gfar_enet_open(struct net_device *dev)
1168 struct gfar_private *priv = netdev_priv(dev);
1171 napi_enable(&priv->napi);
1173 skb_queue_head_init(&priv->rx_recycle);
1175 /* Initialize a bunch of registers */
1176 init_registers(dev);
1178 gfar_set_mac_address(dev);
1180 err = init_phy(dev);
1183 napi_disable(&priv->napi);
1187 err = startup_gfar(dev);
1189 napi_disable(&priv->napi);
1193 netif_start_queue(dev);
1195 device_set_wakeup_enable(&dev->dev, priv->wol_en);
1200 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1202 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1204 memset(fcb, 0, GMAC_FCB_LEN);
1209 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1213 /* If we're here, it's a IP packet with a TCP or UDP
1214 * payload. We set it to checksum, using a pseudo-header
1217 flags = TXFCB_DEFAULT;
1219 /* Tell the controller what the protocol is */
1220 /* And provide the already calculated phcs */
1221 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1223 fcb->phcs = udp_hdr(skb)->check;
1225 fcb->phcs = tcp_hdr(skb)->check;
1227 /* l3os is the distance between the start of the
1228 * frame (skb->data) and the start of the IP hdr.
1229 * l4os is the distance between the start of the
1230 * l3 hdr and the l4 hdr */
1231 fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
1232 fcb->l4os = skb_network_header_len(skb);
1237 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1239 fcb->flags |= TXFCB_VLN;
1240 fcb->vlctl = vlan_tx_tag_get(skb);
1243 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
1244 struct txbd8 *base, int ring_size)
1246 struct txbd8 *new_bd = bdp + stride;
1248 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
1251 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
1254 return skip_txbd(bdp, 1, base, ring_size);
1257 /* This is called by the kernel when a frame is ready for transmission. */
1258 /* It is pointed to by the dev->hard_start_xmit function pointer */
1259 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1261 struct gfar_private *priv = netdev_priv(dev);
1262 struct txfcb *fcb = NULL;
1263 struct txbd8 *txbdp, *txbdp_start, *base;
1267 unsigned long flags;
1268 unsigned int nr_frags, length;
1270 base = priv->tx_bd_base;
1272 /* make space for additional header when fcb is needed */
1273 if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
1274 (priv->vlgrp && vlan_tx_tag_present(skb))) &&
1275 (skb_headroom(skb) < GMAC_FCB_LEN)) {
1276 struct sk_buff *skb_new;
1278 skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN);
1280 dev->stats.tx_errors++;
1282 return NETDEV_TX_OK;
1288 /* total number of fragments in the SKB */
1289 nr_frags = skb_shinfo(skb)->nr_frags;
1291 spin_lock_irqsave(&priv->txlock, flags);
1293 /* check if there is space to queue this packet */
1294 if ((nr_frags+1) > priv->num_txbdfree) {
1295 /* no space, stop the queue */
1296 netif_stop_queue(dev);
1297 dev->stats.tx_fifo_errors++;
1298 spin_unlock_irqrestore(&priv->txlock, flags);
1299 return NETDEV_TX_BUSY;
1302 /* Update transmit stats */
1303 dev->stats.tx_bytes += skb->len;
1305 txbdp = txbdp_start = priv->cur_tx;
1307 if (nr_frags == 0) {
1308 lstatus = txbdp->lstatus | BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1310 /* Place the fragment addresses and lengths into the TxBDs */
1311 for (i = 0; i < nr_frags; i++) {
1312 /* Point at the next BD, wrapping as needed */
1313 txbdp = next_txbd(txbdp, base, priv->tx_ring_size);
1315 length = skb_shinfo(skb)->frags[i].size;
1317 lstatus = txbdp->lstatus | length |
1318 BD_LFLAG(TXBD_READY);
1320 /* Handle the last BD specially */
1321 if (i == nr_frags - 1)
1322 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1324 bufaddr = dma_map_page(&priv->ofdev->dev,
1325 skb_shinfo(skb)->frags[i].page,
1326 skb_shinfo(skb)->frags[i].page_offset,
1330 /* set the TxBD length and buffer pointer */
1331 txbdp->bufPtr = bufaddr;
1332 txbdp->lstatus = lstatus;
1335 lstatus = txbdp_start->lstatus;
1338 /* Set up checksumming */
1339 if (CHECKSUM_PARTIAL == skb->ip_summed) {
1340 fcb = gfar_add_fcb(skb);
1341 lstatus |= BD_LFLAG(TXBD_TOE);
1342 gfar_tx_checksum(skb, fcb);
1345 if (priv->vlgrp && vlan_tx_tag_present(skb)) {
1346 if (unlikely(NULL == fcb)) {
1347 fcb = gfar_add_fcb(skb);
1348 lstatus |= BD_LFLAG(TXBD_TOE);
1351 gfar_tx_vlan(skb, fcb);
1354 /* setup the TxBD length and buffer pointer for the first BD */
1355 priv->tx_skbuff[priv->skb_curtx] = skb;
1356 txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
1357 skb_headlen(skb), DMA_TO_DEVICE);
1359 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
1362 * The powerpc-specific eieio() is used, as wmb() has too strong
1363 * semantics (it requires synchronization between cacheable and
1364 * uncacheable mappings, which eieio doesn't provide and which we
1365 * don't need), thus requiring a more expensive sync instruction. At
1366 * some point, the set of architecture-independent barrier functions
1367 * should be expanded to include weaker barriers.
1371 txbdp_start->lstatus = lstatus;
1373 /* Update the current skb pointer to the next entry we will use
1374 * (wrapping if necessary) */
1375 priv->skb_curtx = (priv->skb_curtx + 1) &
1376 TX_RING_MOD_MASK(priv->tx_ring_size);
1378 priv->cur_tx = next_txbd(txbdp, base, priv->tx_ring_size);
1380 /* reduce TxBD free count */
1381 priv->num_txbdfree -= (nr_frags + 1);
1383 dev->trans_start = jiffies;
1385 /* If the next BD still needs to be cleaned up, then the bds
1386 are full. We need to tell the kernel to stop sending us stuff. */
1387 if (!priv->num_txbdfree) {
1388 netif_stop_queue(dev);
1390 dev->stats.tx_fifo_errors++;
1393 /* Tell the DMA to go go go */
1394 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1397 spin_unlock_irqrestore(&priv->txlock, flags);
1399 return NETDEV_TX_OK;
1402 /* Stops the kernel queue, and halts the controller */
1403 static int gfar_close(struct net_device *dev)
1405 struct gfar_private *priv = netdev_priv(dev);
1407 napi_disable(&priv->napi);
1409 skb_queue_purge(&priv->rx_recycle);
1410 cancel_work_sync(&priv->reset_task);
1413 /* Disconnect from the PHY */
1414 phy_disconnect(priv->phydev);
1415 priv->phydev = NULL;
1417 netif_stop_queue(dev);
1422 /* Changes the mac address if the controller is not running. */
1423 static int gfar_set_mac_address(struct net_device *dev)
1425 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1431 /* Enables and disables VLAN insertion/extraction */
1432 static void gfar_vlan_rx_register(struct net_device *dev,
1433 struct vlan_group *grp)
1435 struct gfar_private *priv = netdev_priv(dev);
1436 unsigned long flags;
1439 spin_lock_irqsave(&priv->rxlock, flags);
1444 /* Enable VLAN tag insertion */
1445 tempval = gfar_read(&priv->regs->tctrl);
1446 tempval |= TCTRL_VLINS;
1448 gfar_write(&priv->regs->tctrl, tempval);
1450 /* Enable VLAN tag extraction */
1451 tempval = gfar_read(&priv->regs->rctrl);
1452 tempval |= RCTRL_VLEX;
1453 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
1454 gfar_write(&priv->regs->rctrl, tempval);
1456 /* Disable VLAN tag insertion */
1457 tempval = gfar_read(&priv->regs->tctrl);
1458 tempval &= ~TCTRL_VLINS;
1459 gfar_write(&priv->regs->tctrl, tempval);
1461 /* Disable VLAN tag extraction */
1462 tempval = gfar_read(&priv->regs->rctrl);
1463 tempval &= ~RCTRL_VLEX;
1464 /* If parse is no longer required, then disable parser */
1465 if (tempval & RCTRL_REQ_PARSER)
1466 tempval |= RCTRL_PRSDEP_INIT;
1468 tempval &= ~RCTRL_PRSDEP_INIT;
1469 gfar_write(&priv->regs->rctrl, tempval);
1472 gfar_change_mtu(dev, dev->mtu);
1474 spin_unlock_irqrestore(&priv->rxlock, flags);
1477 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1479 int tempsize, tempval;
1480 struct gfar_private *priv = netdev_priv(dev);
1481 int oldsize = priv->rx_buffer_size;
1482 int frame_size = new_mtu + ETH_HLEN;
1485 frame_size += VLAN_HLEN;
1487 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1488 if (netif_msg_drv(priv))
1489 printk(KERN_ERR "%s: Invalid MTU setting\n",
1494 if (gfar_uses_fcb(priv))
1495 frame_size += GMAC_FCB_LEN;
1497 frame_size += priv->padding;
1500 (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1501 INCREMENTAL_BUFFER_SIZE;
1503 /* Only stop and start the controller if it isn't already
1504 * stopped, and we changed something */
1505 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1508 priv->rx_buffer_size = tempsize;
1512 gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1513 gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1515 /* If the mtu is larger than the max size for standard
1516 * ethernet frames (ie, a jumbo frame), then set maccfg2
1517 * to allow huge frames, and to check the length */
1518 tempval = gfar_read(&priv->regs->maccfg2);
1520 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1521 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1523 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1525 gfar_write(&priv->regs->maccfg2, tempval);
1527 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1533 /* gfar_reset_task gets scheduled when a packet has not been
1534 * transmitted after a set amount of time.
1535 * For now, assume that clearing out all the structures, and
1536 * starting over will fix the problem.
1538 static void gfar_reset_task(struct work_struct *work)
1540 struct gfar_private *priv = container_of(work, struct gfar_private,
1542 struct net_device *dev = priv->ndev;
1544 if (dev->flags & IFF_UP) {
1545 netif_stop_queue(dev);
1548 netif_start_queue(dev);
1551 netif_tx_schedule_all(dev);
1554 static void gfar_timeout(struct net_device *dev)
1556 struct gfar_private *priv = netdev_priv(dev);
1558 dev->stats.tx_errors++;
1559 schedule_work(&priv->reset_task);
1562 /* Interrupt Handler for Transmit complete */
1563 static int gfar_clean_tx_ring(struct net_device *dev)
1565 struct gfar_private *priv = netdev_priv(dev);
1567 struct txbd8 *lbdp = NULL;
1568 struct txbd8 *base = priv->tx_bd_base;
1569 struct sk_buff *skb;
1571 int tx_ring_size = priv->tx_ring_size;
1577 bdp = priv->dirty_tx;
1578 skb_dirtytx = priv->skb_dirtytx;
1580 while ((skb = priv->tx_skbuff[skb_dirtytx])) {
1581 frags = skb_shinfo(skb)->nr_frags;
1582 lbdp = skip_txbd(bdp, frags, base, tx_ring_size);
1584 lstatus = lbdp->lstatus;
1586 /* Only clean completed frames */
1587 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
1588 (lstatus & BD_LENGTH_MASK))
1591 dma_unmap_single(&priv->ofdev->dev,
1596 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1597 bdp = next_txbd(bdp, base, tx_ring_size);
1599 for (i = 0; i < frags; i++) {
1600 dma_unmap_page(&priv->ofdev->dev,
1604 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1605 bdp = next_txbd(bdp, base, tx_ring_size);
1609 * If there's room in the queue (limit it to rx_buffer_size)
1610 * we add this skb back into the pool, if it's the right size
1612 if (skb_queue_len(&priv->rx_recycle) < priv->rx_ring_size &&
1613 skb_recycle_check(skb, priv->rx_buffer_size +
1615 __skb_queue_head(&priv->rx_recycle, skb);
1617 dev_kfree_skb_any(skb);
1619 priv->tx_skbuff[skb_dirtytx] = NULL;
1621 skb_dirtytx = (skb_dirtytx + 1) &
1622 TX_RING_MOD_MASK(tx_ring_size);
1625 priv->num_txbdfree += frags + 1;
1628 /* If we freed a buffer, we can restart transmission, if necessary */
1629 if (netif_queue_stopped(dev) && priv->num_txbdfree)
1630 netif_wake_queue(dev);
1632 /* Update dirty indicators */
1633 priv->skb_dirtytx = skb_dirtytx;
1634 priv->dirty_tx = bdp;
1636 dev->stats.tx_packets += howmany;
1641 static void gfar_schedule_cleanup(struct net_device *dev)
1643 struct gfar_private *priv = netdev_priv(dev);
1644 unsigned long flags;
1646 spin_lock_irqsave(&priv->txlock, flags);
1647 spin_lock(&priv->rxlock);
1649 if (napi_schedule_prep(&priv->napi)) {
1650 gfar_write(&priv->regs->imask, IMASK_RTX_DISABLED);
1651 __napi_schedule(&priv->napi);
1654 * Clear IEVENT, so interrupts aren't called again
1655 * because of the packets that have already arrived.
1657 gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1660 spin_unlock(&priv->rxlock);
1661 spin_unlock_irqrestore(&priv->txlock, flags);
1664 /* Interrupt Handler for Transmit complete */
1665 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1667 gfar_schedule_cleanup((struct net_device *)dev_id);
1671 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
1672 struct sk_buff *skb)
1674 struct gfar_private *priv = netdev_priv(dev);
1677 bdp->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
1678 priv->rx_buffer_size, DMA_FROM_DEVICE);
1680 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
1682 if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1)
1683 lstatus |= BD_LFLAG(RXBD_WRAP);
1687 bdp->lstatus = lstatus;
1691 struct sk_buff * gfar_new_skb(struct net_device *dev)
1693 unsigned int alignamount;
1694 struct gfar_private *priv = netdev_priv(dev);
1695 struct sk_buff *skb = NULL;
1697 skb = __skb_dequeue(&priv->rx_recycle);
1699 skb = netdev_alloc_skb(dev,
1700 priv->rx_buffer_size + RXBUF_ALIGNMENT);
1705 alignamount = RXBUF_ALIGNMENT -
1706 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
1708 /* We need the data buffer to be aligned properly. We will reserve
1709 * as many bytes as needed to align the data properly
1711 skb_reserve(skb, alignamount);
1716 static inline void count_errors(unsigned short status, struct net_device *dev)
1718 struct gfar_private *priv = netdev_priv(dev);
1719 struct net_device_stats *stats = &dev->stats;
1720 struct gfar_extra_stats *estats = &priv->extra_stats;
1722 /* If the packet was truncated, none of the other errors
1724 if (status & RXBD_TRUNCATED) {
1725 stats->rx_length_errors++;
1731 /* Count the errors, if there were any */
1732 if (status & (RXBD_LARGE | RXBD_SHORT)) {
1733 stats->rx_length_errors++;
1735 if (status & RXBD_LARGE)
1740 if (status & RXBD_NONOCTET) {
1741 stats->rx_frame_errors++;
1742 estats->rx_nonoctet++;
1744 if (status & RXBD_CRCERR) {
1745 estats->rx_crcerr++;
1746 stats->rx_crc_errors++;
1748 if (status & RXBD_OVERRUN) {
1749 estats->rx_overrun++;
1750 stats->rx_crc_errors++;
1754 irqreturn_t gfar_receive(int irq, void *dev_id)
1756 gfar_schedule_cleanup((struct net_device *)dev_id);
1760 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1762 /* If valid headers were found, and valid sums
1763 * were verified, then we tell the kernel that no
1764 * checksumming is necessary. Otherwise, it is */
1765 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1766 skb->ip_summed = CHECKSUM_UNNECESSARY;
1768 skb->ip_summed = CHECKSUM_NONE;
1772 /* gfar_process_frame() -- handle one incoming packet if skb
1774 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1777 struct gfar_private *priv = netdev_priv(dev);
1778 struct rxfcb *fcb = NULL;
1782 /* fcb is at the beginning if exists */
1783 fcb = (struct rxfcb *)skb->data;
1785 /* Remove the FCB from the skb */
1786 /* Remove the padded bytes, if there are any */
1788 skb_pull(skb, amount_pull);
1790 if (priv->rx_csum_enable)
1791 gfar_rx_checksum(skb, fcb);
1793 /* Tell the skb what kind of packet this is */
1794 skb->protocol = eth_type_trans(skb, dev);
1796 /* Send the packet up the stack */
1797 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
1798 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
1800 ret = netif_receive_skb(skb);
1802 if (NET_RX_DROP == ret)
1803 priv->extra_stats.kernel_dropped++;
1808 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1809 * until the budget/quota has been reached. Returns the number
1812 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1814 struct rxbd8 *bdp, *base;
1815 struct sk_buff *skb;
1819 struct gfar_private *priv = netdev_priv(dev);
1821 /* Get the first full descriptor */
1823 base = priv->rx_bd_base;
1825 amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0) +
1828 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1829 struct sk_buff *newskb;
1832 /* Add another skb for the future */
1833 newskb = gfar_new_skb(dev);
1835 skb = priv->rx_skbuff[priv->skb_currx];
1837 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
1838 priv->rx_buffer_size, DMA_FROM_DEVICE);
1840 /* We drop the frame if we failed to allocate a new buffer */
1841 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
1842 bdp->status & RXBD_ERR)) {
1843 count_errors(bdp->status, dev);
1845 if (unlikely(!newskb))
1849 * We need to reset ->data to what it
1850 * was before gfar_new_skb() re-aligned
1851 * it to an RXBUF_ALIGNMENT boundary
1852 * before we put the skb back on the
1855 skb->data = skb->head + NET_SKB_PAD;
1856 __skb_queue_head(&priv->rx_recycle, skb);
1859 /* Increment the number of packets */
1860 dev->stats.rx_packets++;
1864 pkt_len = bdp->length - ETH_FCS_LEN;
1865 /* Remove the FCS from the packet length */
1866 skb_put(skb, pkt_len);
1867 dev->stats.rx_bytes += pkt_len;
1869 if (in_irq() || irqs_disabled())
1870 printk("Interrupt problem!\n");
1871 gfar_process_frame(dev, skb, amount_pull);
1874 if (netif_msg_rx_err(priv))
1876 "%s: Missing skb!\n", dev->name);
1877 dev->stats.rx_dropped++;
1878 priv->extra_stats.rx_skbmissing++;
1883 priv->rx_skbuff[priv->skb_currx] = newskb;
1885 /* Setup the new bdp */
1886 gfar_new_rxbdp(dev, bdp, newskb);
1888 /* Update to the next pointer */
1889 bdp = next_bd(bdp, base, priv->rx_ring_size);
1891 /* update to point at the next skb */
1893 (priv->skb_currx + 1) &
1894 RX_RING_MOD_MASK(priv->rx_ring_size);
1897 /* Update the current rxbd pointer to be the next one */
1903 static int gfar_poll(struct napi_struct *napi, int budget)
1905 struct gfar_private *priv = container_of(napi, struct gfar_private, napi);
1906 struct net_device *dev = priv->ndev;
1909 unsigned long flags;
1911 /* Clear IEVENT, so interrupts aren't called again
1912 * because of the packets that have already arrived */
1913 gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1915 /* If we fail to get the lock, don't bother with the TX BDs */
1916 if (spin_trylock_irqsave(&priv->txlock, flags)) {
1917 tx_cleaned = gfar_clean_tx_ring(dev);
1918 spin_unlock_irqrestore(&priv->txlock, flags);
1921 rx_cleaned = gfar_clean_rx_ring(dev, budget);
1926 if (rx_cleaned < budget) {
1927 napi_complete(napi);
1929 /* Clear the halt bit in RSTAT */
1930 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1932 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1934 /* If we are coalescing interrupts, update the timer */
1935 /* Otherwise, clear it */
1936 if (likely(priv->rxcoalescing)) {
1937 gfar_write(&priv->regs->rxic, 0);
1938 gfar_write(&priv->regs->rxic, priv->rxic);
1940 if (likely(priv->txcoalescing)) {
1941 gfar_write(&priv->regs->txic, 0);
1942 gfar_write(&priv->regs->txic, priv->txic);
1949 #ifdef CONFIG_NET_POLL_CONTROLLER
1951 * Polling 'interrupt' - used by things like netconsole to send skbs
1952 * without having to re-enable interrupts. It's not called while
1953 * the interrupt routine is executing.
1955 static void gfar_netpoll(struct net_device *dev)
1957 struct gfar_private *priv = netdev_priv(dev);
1959 /* If the device has multiple interrupts, run tx/rx */
1960 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1961 disable_irq(priv->interruptTransmit);
1962 disable_irq(priv->interruptReceive);
1963 disable_irq(priv->interruptError);
1964 gfar_interrupt(priv->interruptTransmit, dev);
1965 enable_irq(priv->interruptError);
1966 enable_irq(priv->interruptReceive);
1967 enable_irq(priv->interruptTransmit);
1969 disable_irq(priv->interruptTransmit);
1970 gfar_interrupt(priv->interruptTransmit, dev);
1971 enable_irq(priv->interruptTransmit);
1976 /* The interrupt handler for devices with one interrupt */
1977 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
1979 struct net_device *dev = dev_id;
1980 struct gfar_private *priv = netdev_priv(dev);
1982 /* Save ievent for future reference */
1983 u32 events = gfar_read(&priv->regs->ievent);
1985 /* Check for reception */
1986 if (events & IEVENT_RX_MASK)
1987 gfar_receive(irq, dev_id);
1989 /* Check for transmit completion */
1990 if (events & IEVENT_TX_MASK)
1991 gfar_transmit(irq, dev_id);
1993 /* Check for errors */
1994 if (events & IEVENT_ERR_MASK)
1995 gfar_error(irq, dev_id);
2000 /* Called every time the controller might need to be made
2001 * aware of new link state. The PHY code conveys this
2002 * information through variables in the phydev structure, and this
2003 * function converts those variables into the appropriate
2004 * register values, and can bring down the device if needed.
2006 static void adjust_link(struct net_device *dev)
2008 struct gfar_private *priv = netdev_priv(dev);
2009 struct gfar __iomem *regs = priv->regs;
2010 unsigned long flags;
2011 struct phy_device *phydev = priv->phydev;
2014 spin_lock_irqsave(&priv->txlock, flags);
2016 u32 tempval = gfar_read(®s->maccfg2);
2017 u32 ecntrl = gfar_read(®s->ecntrl);
2019 /* Now we make sure that we can be in full duplex mode.
2020 * If not, we operate in half-duplex mode. */
2021 if (phydev->duplex != priv->oldduplex) {
2023 if (!(phydev->duplex))
2024 tempval &= ~(MACCFG2_FULL_DUPLEX);
2026 tempval |= MACCFG2_FULL_DUPLEX;
2028 priv->oldduplex = phydev->duplex;
2031 if (phydev->speed != priv->oldspeed) {
2033 switch (phydev->speed) {
2036 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2038 ecntrl &= ~(ECNTRL_R100);
2043 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
2045 /* Reduced mode distinguishes
2046 * between 10 and 100 */
2047 if (phydev->speed == SPEED_100)
2048 ecntrl |= ECNTRL_R100;
2050 ecntrl &= ~(ECNTRL_R100);
2053 if (netif_msg_link(priv))
2055 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
2056 dev->name, phydev->speed);
2060 priv->oldspeed = phydev->speed;
2063 gfar_write(®s->maccfg2, tempval);
2064 gfar_write(®s->ecntrl, ecntrl);
2066 if (!priv->oldlink) {
2070 } else if (priv->oldlink) {
2074 priv->oldduplex = -1;
2077 if (new_state && netif_msg_link(priv))
2078 phy_print_status(phydev);
2080 spin_unlock_irqrestore(&priv->txlock, flags);
2083 /* Update the hash table based on the current list of multicast
2084 * addresses we subscribe to. Also, change the promiscuity of
2085 * the device based on the flags (this function is called
2086 * whenever dev->flags is changed */
2087 static void gfar_set_multi(struct net_device *dev)
2089 struct dev_mc_list *mc_ptr;
2090 struct gfar_private *priv = netdev_priv(dev);
2091 struct gfar __iomem *regs = priv->regs;
2094 if(dev->flags & IFF_PROMISC) {
2095 /* Set RCTRL to PROM */
2096 tempval = gfar_read(®s->rctrl);
2097 tempval |= RCTRL_PROM;
2098 gfar_write(®s->rctrl, tempval);
2100 /* Set RCTRL to not PROM */
2101 tempval = gfar_read(®s->rctrl);
2102 tempval &= ~(RCTRL_PROM);
2103 gfar_write(®s->rctrl, tempval);
2106 if(dev->flags & IFF_ALLMULTI) {
2107 /* Set the hash to rx all multicast frames */
2108 gfar_write(®s->igaddr0, 0xffffffff);
2109 gfar_write(®s->igaddr1, 0xffffffff);
2110 gfar_write(®s->igaddr2, 0xffffffff);
2111 gfar_write(®s->igaddr3, 0xffffffff);
2112 gfar_write(®s->igaddr4, 0xffffffff);
2113 gfar_write(®s->igaddr5, 0xffffffff);
2114 gfar_write(®s->igaddr6, 0xffffffff);
2115 gfar_write(®s->igaddr7, 0xffffffff);
2116 gfar_write(®s->gaddr0, 0xffffffff);
2117 gfar_write(®s->gaddr1, 0xffffffff);
2118 gfar_write(®s->gaddr2, 0xffffffff);
2119 gfar_write(®s->gaddr3, 0xffffffff);
2120 gfar_write(®s->gaddr4, 0xffffffff);
2121 gfar_write(®s->gaddr5, 0xffffffff);
2122 gfar_write(®s->gaddr6, 0xffffffff);
2123 gfar_write(®s->gaddr7, 0xffffffff);
2128 /* zero out the hash */
2129 gfar_write(®s->igaddr0, 0x0);
2130 gfar_write(®s->igaddr1, 0x0);
2131 gfar_write(®s->igaddr2, 0x0);
2132 gfar_write(®s->igaddr3, 0x0);
2133 gfar_write(®s->igaddr4, 0x0);
2134 gfar_write(®s->igaddr5, 0x0);
2135 gfar_write(®s->igaddr6, 0x0);
2136 gfar_write(®s->igaddr7, 0x0);
2137 gfar_write(®s->gaddr0, 0x0);
2138 gfar_write(®s->gaddr1, 0x0);
2139 gfar_write(®s->gaddr2, 0x0);
2140 gfar_write(®s->gaddr3, 0x0);
2141 gfar_write(®s->gaddr4, 0x0);
2142 gfar_write(®s->gaddr5, 0x0);
2143 gfar_write(®s->gaddr6, 0x0);
2144 gfar_write(®s->gaddr7, 0x0);
2146 /* If we have extended hash tables, we need to
2147 * clear the exact match registers to prepare for
2149 if (priv->extended_hash) {
2150 em_num = GFAR_EM_NUM + 1;
2151 gfar_clear_exact_match(dev);
2158 if(dev->mc_count == 0)
2161 /* Parse the list, and set the appropriate bits */
2162 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
2164 gfar_set_mac_for_addr(dev, idx,
2168 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
2176 /* Clears each of the exact match registers to zero, so they
2177 * don't interfere with normal reception */
2178 static void gfar_clear_exact_match(struct net_device *dev)
2181 u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
2183 for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
2184 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
2187 /* Set the appropriate hash bit for the given addr */
2188 /* The algorithm works like so:
2189 * 1) Take the Destination Address (ie the multicast address), and
2190 * do a CRC on it (little endian), and reverse the bits of the
2192 * 2) Use the 8 most significant bits as a hash into a 256-entry
2193 * table. The table is controlled through 8 32-bit registers:
2194 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
2195 * gaddr7. This means that the 3 most significant bits in the
2196 * hash index which gaddr register to use, and the 5 other bits
2197 * indicate which bit (assuming an IBM numbering scheme, which
2198 * for PowerPC (tm) is usually the case) in the register holds
2200 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
2203 struct gfar_private *priv = netdev_priv(dev);
2204 u32 result = ether_crc(MAC_ADDR_LEN, addr);
2205 int width = priv->hash_width;
2206 u8 whichbit = (result >> (32 - width)) & 0x1f;
2207 u8 whichreg = result >> (32 - width + 5);
2208 u32 value = (1 << (31-whichbit));
2210 tempval = gfar_read(priv->hash_regs[whichreg]);
2212 gfar_write(priv->hash_regs[whichreg], tempval);
2218 /* There are multiple MAC Address register pairs on some controllers
2219 * This function sets the numth pair to a given address
2221 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
2223 struct gfar_private *priv = netdev_priv(dev);
2225 char tmpbuf[MAC_ADDR_LEN];
2227 u32 __iomem *macptr = &priv->regs->macstnaddr1;
2231 /* Now copy it into the mac registers backwards, cuz */
2232 /* little endian is silly */
2233 for (idx = 0; idx < MAC_ADDR_LEN; idx++)
2234 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
2236 gfar_write(macptr, *((u32 *) (tmpbuf)));
2238 tempval = *((u32 *) (tmpbuf + 4));
2240 gfar_write(macptr+1, tempval);
2243 /* GFAR error interrupt handler */
2244 static irqreturn_t gfar_error(int irq, void *dev_id)
2246 struct net_device *dev = dev_id;
2247 struct gfar_private *priv = netdev_priv(dev);
2249 /* Save ievent for future reference */
2250 u32 events = gfar_read(&priv->regs->ievent);
2253 gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK);
2255 /* Magic Packet is not an error. */
2256 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2257 (events & IEVENT_MAG))
2258 events &= ~IEVENT_MAG;
2261 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2262 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2263 dev->name, events, gfar_read(&priv->regs->imask));
2265 /* Update the error counters */
2266 if (events & IEVENT_TXE) {
2267 dev->stats.tx_errors++;
2269 if (events & IEVENT_LC)
2270 dev->stats.tx_window_errors++;
2271 if (events & IEVENT_CRL)
2272 dev->stats.tx_aborted_errors++;
2273 if (events & IEVENT_XFUN) {
2274 if (netif_msg_tx_err(priv))
2275 printk(KERN_DEBUG "%s: TX FIFO underrun, "
2276 "packet dropped.\n", dev->name);
2277 dev->stats.tx_dropped++;
2278 priv->extra_stats.tx_underrun++;
2280 /* Reactivate the Tx Queues */
2281 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
2283 if (netif_msg_tx_err(priv))
2284 printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
2286 if (events & IEVENT_BSY) {
2287 dev->stats.rx_errors++;
2288 priv->extra_stats.rx_bsy++;
2290 gfar_receive(irq, dev_id);
2292 if (netif_msg_rx_err(priv))
2293 printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
2294 dev->name, gfar_read(&priv->regs->rstat));
2296 if (events & IEVENT_BABR) {
2297 dev->stats.rx_errors++;
2298 priv->extra_stats.rx_babr++;
2300 if (netif_msg_rx_err(priv))
2301 printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
2303 if (events & IEVENT_EBERR) {
2304 priv->extra_stats.eberr++;
2305 if (netif_msg_rx_err(priv))
2306 printk(KERN_DEBUG "%s: bus error\n", dev->name);
2308 if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
2309 printk(KERN_DEBUG "%s: control frame\n", dev->name);
2311 if (events & IEVENT_BABT) {
2312 priv->extra_stats.tx_babt++;
2313 if (netif_msg_tx_err(priv))
2314 printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
2319 /* work with hotplug and coldplug */
2320 MODULE_ALIAS("platform:fsl-gianfar");
2322 static struct of_device_id gfar_match[] =
2326 .compatible = "gianfar",
2331 /* Structure for a device driver */
2332 static struct of_platform_driver gfar_driver = {
2333 .name = "fsl-gianfar",
2334 .match_table = gfar_match,
2336 .probe = gfar_probe,
2337 .remove = gfar_remove,
2338 .suspend = gfar_suspend,
2339 .resume = gfar_resume,
2342 static int __init gfar_init(void)
2344 return of_register_platform_driver(&gfar_driver);
2347 static void __exit gfar_exit(void)
2349 of_unregister_platform_driver(&gfar_driver);
2352 module_init(gfar_init);
2353 module_exit(gfar_exit);