drivers/net/gianfar.c

   1 /*
   2  * drivers/net/gianfar.c
   3  *
   4  * Gianfar Ethernet Driver
   5  * This driver is designed for the non-CPM ethernet controllers
   6  * on the 85xx and 83xx family of integrated processors
   7  * Based on 8260_io/fcc_enet.c
   8  *
   9  * Author: Andy Fleming
  10  * Maintainer: Kumar Gala
  11  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
  12  *
  13  * Copyright 2002-2009 Freescale Semiconductor, Inc.
  14  * Copyright 2007 MontaVista Software, Inc.
  15  *
  16  * This program is free software; you can redistribute  it and/or modify it
  17  * under  the terms of  the GNU General  Public License as published by the
  18  * Free Software Foundation;  either version 2 of the  License, or (at your
  19  * option) any later version.
  20  *
  21  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  22  *  RA 11 31 24.2
  23  *  Dec +69 19 52
  24  *  V 3.84
  25  *  B-V +1.62
  26  *
  27  *  Theory of operation
  28  *
  29  *  The driver is initialized through of_device. Configuration information
  30  *  is therefore conveyed through an OF-style device tree.
  31  *
  32  *  The Gianfar Ethernet Controller uses a ring of buffer
  33  *  descriptors.  The beginning is indicated by a register
  34  *  pointing to the physical address of the start of the ring.
  35  *  The end is determined by a "wrap" bit being set in the
  36  *  last descriptor of the ring.
  37  *
  38  *  When a packet is received, the RXF bit in the
  39  *  IEVENT register is set, triggering an interrupt when the
  40  *  corresponding bit in the IMASK register is also set (if
  41  *  interrupt coalescing is active, then the interrupt may not
  42  *  happen immediately, but will wait until either a set number
  43  *  of frames or amount of time have passed).  In NAPI, the
  44  *  interrupt handler will signal there is work to be done, and
  45  *  exit. This method will start at the last known empty
  46  *  descriptor, and process every subsequent descriptor until there
  47  *  are none left with data (NAPI will stop after a set number of
  48  *  packets to give time to other tasks, but will eventually
  49  *  process all the packets).  The data arrives inside a
  50  *  pre-allocated skb, and so after the skb is passed up to the
  51  *  stack, a new skb must be allocated, and the address field in
  52  *  the buffer descriptor must be updated to indicate this new
  53  *  skb.
  54  *
  55  *  When the kernel requests that a packet be transmitted, the
  56  *  driver starts where it left off last time, and points the
  57  *  descriptor at the buffer which was passed in.  The driver
  58  *  then informs the DMA engine that there are packets ready to
  59  *  be transmitted.  Once the controller is finished transmitting
  60  *  the packet, an interrupt may be triggered (under the same
  61  *  conditions as for reception, but depending on the TXF bit).
  62  *  The driver then cleans up the buffer.
  63  */
  64
  65 #include <linux/kernel.h>
  66 #include <linux/string.h>
  67 #include <linux/errno.h>
  68 #include <linux/unistd.h>
  69 #include <linux/slab.h>
  70 #include <linux/interrupt.h>
  71 #include <linux/init.h>
  72 #include <linux/delay.h>
  73 #include <linux/netdevice.h>
  74 #include <linux/etherdevice.h>
  75 #include <linux/skbuff.h>
  76 #include <linux/if_vlan.h>
  77 #include <linux/spinlock.h>
  78 #include <linux/mm.h>
  79 #include <linux/of_mdio.h>
  80 #include <linux/of_platform.h>
  81 #include <linux/ip.h>
  82 #include <linux/tcp.h>
  83 #include <linux/udp.h>
  84 #include <linux/in.h>
  85
  86 #include <asm/io.h>
  87 #include <asm/irq.h>
  88 #include <asm/uaccess.h>
  89 #include <linux/module.h>
  90 #include <linux/dma-mapping.h>
  91 #include <linux/crc32.h>
  92 #include <linux/mii.h>
  93 #include <linux/phy.h>
  94 #include <linux/phy_fixed.h>
  95 #include <linux/of.h>
  96
  97 #include "gianfar.h"
  98 #include "fsl_pq_mdio.h"
  99
 100 #define TX_TIMEOUT      (1*HZ)
 101 #undef BRIEF_GFAR_ERRORS
 102 #undef VERBOSE_GFAR_ERRORS
 103
 104 const char gfar_driver_name[] = "Gianfar Ethernet";
 105 const char gfar_driver_version[] = "1.3";
 106
 107 static int gfar_enet_open(struct net_device *dev);
 108 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 109 static void gfar_reset_task(struct work_struct *work);
 110 static void gfar_timeout(struct net_device *dev);
 111 static int gfar_close(struct net_device *dev);
 112 struct sk_buff *gfar_new_skb(struct net_device *dev);
 113 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 114                 struct sk_buff *skb);
 115 static int gfar_set_mac_address(struct net_device *dev);
 116 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 117 static irqreturn_t gfar_error(int irq, void *dev_id);
 118 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 119 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 120 static void adjust_link(struct net_device *dev);
 121 static void init_registers(struct net_device *dev);
 122 static int init_phy(struct net_device *dev);
 123 static int gfar_probe(struct of_device *ofdev,
 124                 const struct of_device_id *match);
 125 static int gfar_remove(struct of_device *ofdev);
 126 static void free_skb_resources(struct gfar_private *priv);
 127 static void gfar_set_multi(struct net_device *dev);
 128 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 129 static void gfar_configure_serdes(struct net_device *dev);
 130 static int gfar_poll(struct napi_struct *napi, int budget);
 131 #ifdef CONFIG_NET_POLL_CONTROLLER
 132 static void gfar_netpoll(struct net_device *dev);
 133 #endif
 134 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
 135 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
 136 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
 137                               int amount_pull);
 138 static void gfar_vlan_rx_register(struct net_device *netdev,
 139                                 struct vlan_group *grp);
 140 void gfar_halt(struct net_device *dev);
 141 static void gfar_halt_nodisable(struct net_device *dev);
 142 void gfar_start(struct net_device *dev);
 143 static void gfar_clear_exact_match(struct net_device *dev);
 144 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
 145 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 146 u16 gfar_select_queue(struct net_device *dev, struct sk_buff *skb);
 147
 148 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 149 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 150 MODULE_LICENSE("GPL");
 151
 152 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 153                             dma_addr_t buf)
 154 {
 155         u32 lstatus;
 156
 157         bdp->bufPtr = buf;
 158
 159         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
 160         if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
 161                 lstatus |= BD_LFLAG(RXBD_WRAP);
 162
 163         eieio();
 164
 165         bdp->lstatus = lstatus;
 166 }
 167
 168 static int gfar_init_bds(struct net_device *ndev)
 169 {
 170         struct gfar_private *priv = netdev_priv(ndev);
 171         struct gfar_priv_tx_q *tx_queue = NULL;
 172         struct gfar_priv_rx_q *rx_queue = NULL;
 173         struct txbd8 *txbdp;
 174         struct rxbd8 *rxbdp;
 175         int i, j;
 176
 177         for (i = 0; i < priv->num_tx_queues; i++) {
 178                 tx_queue = priv->tx_queue[i];
 179                 /* Initialize some variables in our dev structure */
 180                 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
 181                 tx_queue->dirty_tx = tx_queue->tx_bd_base;
 182                 tx_queue->cur_tx = tx_queue->tx_bd_base;
 183                 tx_queue->skb_curtx = 0;
 184                 tx_queue->skb_dirtytx = 0;
 185
 186                 /* Initialize Transmit Descriptor Ring */
 187                 txbdp = tx_queue->tx_bd_base;
 188                 for (j = 0; j < tx_queue->tx_ring_size; j++) {
 189                         txbdp->lstatus = 0;
 190                         txbdp->bufPtr = 0;
 191                         txbdp++;
 192                 }
 193
 194                 /* Set the last descriptor in the ring to indicate wrap */
 195                 txbdp--;
 196                 txbdp->status |= TXBD_WRAP;
 197         }
 198
 199         for (i = 0; i < priv->num_rx_queues; i++) {
 200                 rx_queue = priv->rx_queue[i];
 201                 rx_queue->cur_rx = rx_queue->rx_bd_base;
 202                 rx_queue->skb_currx = 0;
 203                 rxbdp = rx_queue->rx_bd_base;
 204
 205                 for (j = 0; j < rx_queue->rx_ring_size; j++) {
 206                         struct sk_buff *skb = rx_queue->rx_skbuff[j];
 207
 208                         if (skb) {
 209                                 gfar_init_rxbdp(rx_queue, rxbdp,
 210                                                 rxbdp->bufPtr);
 211                         } else {
 212                                 skb = gfar_new_skb(ndev);
 213                                 if (!skb) {
 214                                         pr_err("%s: Can't allocate RX buffers\n",
 215                                                         ndev->name);
 216                                         goto err_rxalloc_fail;
 217                                 }
 218                                 rx_queue->rx_skbuff[j] = skb;
 219
 220                                 gfar_new_rxbdp(rx_queue, rxbdp, skb);
 221                         }
 222
 223                         rxbdp++;
 224                 }
 225
 226         }
 227
 228         return 0;
 229
 230 err_rxalloc_fail:
 231         free_skb_resources(priv);
 232         return -ENOMEM;
 233 }
 234
 235 static int gfar_alloc_skb_resources(struct net_device *ndev)
 236 {
 237         void *vaddr;
 238         dma_addr_t addr;
 239         int i, j, k;
 240         struct gfar_private *priv = netdev_priv(ndev);
 241         struct device *dev = &priv->ofdev->dev;
 242         struct gfar_priv_tx_q *tx_queue = NULL;
 243         struct gfar_priv_rx_q *rx_queue = NULL;
 244
 245         priv->total_tx_ring_size = 0;
 246         for (i = 0; i < priv->num_tx_queues; i++)
 247                 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
 248
 249         priv->total_rx_ring_size = 0;
 250         for (i = 0; i < priv->num_rx_queues; i++)
 251                 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
 252
 253         /* Allocate memory for the buffer descriptors */
 254         vaddr = dma_alloc_coherent(dev,
 255                         sizeof(struct txbd8) * priv->total_tx_ring_size +
 256                         sizeof(struct rxbd8) * priv->total_rx_ring_size,
 257                         &addr, GFP_KERNEL);
 258         if (!vaddr) {
 259                 if (netif_msg_ifup(priv))
 260                         pr_err("%s: Could not allocate buffer descriptors!\n",
 261                                ndev->name);
 262                 return -ENOMEM;
 263         }
 264
 265         for (i = 0; i < priv->num_tx_queues; i++) {
 266                 tx_queue = priv->tx_queue[i];
 267                 tx_queue->tx_bd_base = (struct txbd8 *) vaddr;
 268                 tx_queue->tx_bd_dma_base = addr;
 269                 tx_queue->dev = ndev;
 270                 /* enet DMA only understands physical addresses */
 271                 addr    += sizeof(struct txbd8) *tx_queue->tx_ring_size;
 272                 vaddr   += sizeof(struct txbd8) *tx_queue->tx_ring_size;
 273         }
 274
 275         /* Start the rx descriptor ring where the tx ring leaves off */
 276         for (i = 0; i < priv->num_rx_queues; i++) {
 277                 rx_queue = priv->rx_queue[i];
 278                 rx_queue->rx_bd_base = (struct rxbd8 *) vaddr;
 279                 rx_queue->rx_bd_dma_base = addr;
 280                 rx_queue->dev = ndev;
 281                 addr    += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
 282                 vaddr   += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
 283         }
 284
 285         /* Setup the skbuff rings */
 286         for (i = 0; i < priv->num_tx_queues; i++) {
 287                 tx_queue = priv->tx_queue[i];
 288                 tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) *
 289                                   tx_queue->tx_ring_size, GFP_KERNEL);
 290                 if (!tx_queue->tx_skbuff) {
 291                         if (netif_msg_ifup(priv))
 292                                 pr_err("%s: Could not allocate tx_skbuff\n",
 293                                                 ndev->name);
 294                         goto cleanup;
 295                 }
 296
 297                 for (k = 0; k < tx_queue->tx_ring_size; k++)
 298                         tx_queue->tx_skbuff[k] = NULL;
 299         }
 300
 301         for (i = 0; i < priv->num_rx_queues; i++) {
 302                 rx_queue = priv->rx_queue[i];
 303                 rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) *
 304                                   rx_queue->rx_ring_size, GFP_KERNEL);
 305
 306                 if (!rx_queue->rx_skbuff) {
 307                         if (netif_msg_ifup(priv))
 308                                 pr_err("%s: Could not allocate rx_skbuff\n",
 309                                        ndev->name);
 310                         goto cleanup;
 311                 }
 312
 313                 for (j = 0; j < rx_queue->rx_ring_size; j++)
 314                         rx_queue->rx_skbuff[j] = NULL;
 315         }
 316
 317         if (gfar_init_bds(ndev))
 318                 goto cleanup;
 319
 320         return 0;
 321
 322 cleanup:
 323         free_skb_resources(priv);
 324         return -ENOMEM;
 325 }
 326
 327 static void gfar_init_tx_rx_base(struct gfar_private *priv)
 328 {
 329         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 330         u32 *baddr;
 331         int i;
 332
 333         baddr = &regs->tbase0;
 334         for(i = 0; i < priv->num_tx_queues; i++) {
 335                 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
 336                 baddr   += 2;
 337         }
 338
 339         baddr = &regs->rbase0;
 340         for(i = 0; i < priv->num_rx_queues; i++) {
 341                 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
 342                 baddr   += 2;
 343         }
 344 }
 345
 346 static void gfar_init_mac(struct net_device *ndev)
 347 {
 348         struct gfar_private *priv = netdev_priv(ndev);
 349         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 350         u32 rctrl = 0;
 351         u32 tctrl = 0;
 352         u32 attrs = 0;
 353
 354         /* write the tx/rx base registers */
 355         gfar_init_tx_rx_base(priv);
 356
 357         /* Configure the coalescing support */
 358         gfar_configure_coalescing(priv, 0xFF, 0xFF);
 359
 360         if (priv->rx_filer_enable)
 361                 rctrl |= RCTRL_FILREN;
 362
 363         if (priv->rx_csum_enable)
 364                 rctrl |= RCTRL_CHECKSUMMING;
 365
 366         if (priv->extended_hash) {
 367                 rctrl |= RCTRL_EXTHASH;
 368
 369                 gfar_clear_exact_match(ndev);
 370                 rctrl |= RCTRL_EMEN;
 371         }
 372
 373         if (priv->padding) {
 374                 rctrl &= ~RCTRL_PAL_MASK;
 375                 rctrl |= RCTRL_PADDING(priv->padding);
 376         }
 377
 378         /* keep vlan related bits if it's enabled */
 379         if (priv->vlgrp) {
 380                 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
 381                 tctrl |= TCTRL_VLINS;
 382         }
 383
 384         /* Init rctrl based on our settings */
 385         gfar_write(&regs->rctrl, rctrl);
 386
 387         if (ndev->features & NETIF_F_IP_CSUM)
 388                 tctrl |= TCTRL_INIT_CSUM;
 389
 390         tctrl |= TCTRL_TXSCHED_PRIO;
 391
 392         gfar_write(&regs->tctrl, tctrl);
 393
 394         /* Set the extraction length and index */
 395         attrs = ATTRELI_EL(priv->rx_stash_size) |
 396                 ATTRELI_EI(priv->rx_stash_index);
 397
 398         gfar_write(&regs->attreli, attrs);
 399
 400         /* Start with defaults, and add stashing or locking
 401          * depending on the approprate variables */
 402         attrs = ATTR_INIT_SETTINGS;
 403
 404         if (priv->bd_stash_en)
 405                 attrs |= ATTR_BDSTASH;
 406
 407         if (priv->rx_stash_size != 0)
 408                 attrs |= ATTR_BUFSTASH;
 409
 410         gfar_write(&regs->attr, attrs);
 411
 412         gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
 413         gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
 414         gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
 415 }
 416
 417 static const struct net_device_ops gfar_netdev_ops = {
 418         .ndo_open = gfar_enet_open,
 419         .ndo_start_xmit = gfar_start_xmit,
 420         .ndo_stop = gfar_close,
 421         .ndo_change_mtu = gfar_change_mtu,
 422         .ndo_set_multicast_list = gfar_set_multi,
 423         .ndo_tx_timeout = gfar_timeout,
 424         .ndo_do_ioctl = gfar_ioctl,
 425         .ndo_select_queue = gfar_select_queue,
 426         .ndo_vlan_rx_register = gfar_vlan_rx_register,
 427         .ndo_set_mac_address = eth_mac_addr,
 428         .ndo_validate_addr = eth_validate_addr,
 429 #ifdef CONFIG_NET_POLL_CONTROLLER
 430         .ndo_poll_controller = gfar_netpoll,
 431 #endif
 432 };
 433
 434 unsigned int ftp_rqfpr[MAX_FILER_IDX + 1];
 435 unsigned int ftp_rqfcr[MAX_FILER_IDX + 1];
 436
 437 void lock_rx_qs(struct gfar_private *priv)
 438 {
 439         int i = 0x0;
 440
 441         for (i = 0; i < priv->num_rx_queues; i++)
 442                 spin_lock(&priv->rx_queue[i]->rxlock);
 443 }
 444
 445 void lock_tx_qs(struct gfar_private *priv)
 446 {
 447         int i = 0x0;
 448
 449         for (i = 0; i < priv->num_tx_queues; i++)
 450                 spin_lock(&priv->tx_queue[i]->txlock);
 451 }
 452
 453 void unlock_rx_qs(struct gfar_private *priv)
 454 {
 455         int i = 0x0;
 456
 457         for (i = 0; i < priv->num_rx_queues; i++)
 458                 spin_unlock(&priv->rx_queue[i]->rxlock);
 459 }
 460
 461 void unlock_tx_qs(struct gfar_private *priv)
 462 {
 463         int i = 0x0;
 464
 465         for (i = 0; i < priv->num_tx_queues; i++)
 466                 spin_unlock(&priv->tx_queue[i]->txlock);
 467 }
 468
 469 /* Returns 1 if incoming frames use an FCB */
 470 static inline int gfar_uses_fcb(struct gfar_private *priv)
 471 {
 472         return priv->vlgrp || priv->rx_csum_enable;
 473 }
 474
 475 u16 gfar_select_queue(struct net_device *dev, struct sk_buff *skb)
 476 {
 477         return skb_get_queue_mapping(skb);
 478 }
 479 static void free_tx_pointers(struct gfar_private *priv)
 480 {
 481         int i = 0;
 482
 483         for (i = 0; i < priv->num_tx_queues; i++)
 484                 kfree(priv->tx_queue[i]);
 485 }
 486
 487 static void free_rx_pointers(struct gfar_private *priv)
 488 {
 489         int i = 0;
 490
 491         for (i = 0; i < priv->num_rx_queues; i++)
 492                 kfree(priv->rx_queue[i]);
 493 }
 494
 495 static void unmap_group_regs(struct gfar_private *priv)
 496 {
 497         int i = 0;
 498
 499         for (i = 0; i < MAXGROUPS; i++)
 500                 if (priv->gfargrp[i].regs)
 501                         iounmap(priv->gfargrp[i].regs);
 502 }
 503
 504 static void disable_napi(struct gfar_private *priv)
 505 {
 506         int i = 0;
 507
 508         for (i = 0; i < priv->num_grps; i++)
 509                 napi_disable(&priv->gfargrp[i].napi);
 510 }
 511
 512 static void enable_napi(struct gfar_private *priv)
 513 {
 514         int i = 0;
 515
 516         for (i = 0; i < priv->num_grps; i++)
 517                 napi_enable(&priv->gfargrp[i].napi);
 518 }
 519
 520 static int gfar_parse_group(struct device_node *np,
 521                 struct gfar_private *priv, const char *model)
 522 {
 523         u32 *queue_mask;
 524         u64 addr, size;
 525
 526         addr = of_translate_address(np,
 527                         of_get_address(np, 0, &size, NULL));
 528         priv->gfargrp[priv->num_grps].regs = ioremap(addr, size);
 529
 530         if (!priv->gfargrp[priv->num_grps].regs)
 531                 return -ENOMEM;
 532
 533         priv->gfargrp[priv->num_grps].interruptTransmit =
 534                         irq_of_parse_and_map(np, 0);
 535
 536         /* If we aren't the FEC we have multiple interrupts */
 537         if (model && strcasecmp(model, "FEC")) {
 538                 priv->gfargrp[priv->num_grps].interruptReceive =
 539                         irq_of_parse_and_map(np, 1);
 540                 priv->gfargrp[priv->num_grps].interruptError =
 541                         irq_of_parse_and_map(np,2);
 542                 if (priv->gfargrp[priv->num_grps].interruptTransmit < 0 ||
 543                         priv->gfargrp[priv->num_grps].interruptReceive < 0 ||
 544                         priv->gfargrp[priv->num_grps].interruptError < 0) {
 545                         return -EINVAL;
 546                 }
 547         }
 548
 549         priv->gfargrp[priv->num_grps].grp_id = priv->num_grps;
 550         priv->gfargrp[priv->num_grps].priv = priv;
 551         spin_lock_init(&priv->gfargrp[priv->num_grps].grplock);
 552         if(priv->mode == MQ_MG_MODE) {
 553                 queue_mask = (u32 *)of_get_property(np,
 554                                         "fsl,rx-bit-map", NULL);
 555                 priv->gfargrp[priv->num_grps].rx_bit_map =
 556                         queue_mask ?  *queue_mask :(DEFAULT_MAPPING >> priv->num_grps);
 557                 queue_mask = (u32 *)of_get_property(np,
 558                                         "fsl,tx-bit-map", NULL);
 559                 priv->gfargrp[priv->num_grps].tx_bit_map =
 560                         queue_mask ? *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
 561         } else {
 562                 priv->gfargrp[priv->num_grps].rx_bit_map = 0xFF;
 563                 priv->gfargrp[priv->num_grps].tx_bit_map = 0xFF;
 564         }
 565         priv->num_grps++;
 566
 567         return 0;
 568 }
 569
 570 static int gfar_of_init(struct of_device *ofdev, struct net_device **pdev)
 571 {
 572         const char *model;
 573         const char *ctype;
 574         const void *mac_addr;
 575         int err = 0, i;
 576         struct net_device *dev = NULL;
 577         struct gfar_private *priv = NULL;
 578         struct device_node *np = ofdev->node;
 579         struct device_node *child = NULL;
 580         const u32 *stash;
 581         const u32 *stash_len;
 582         const u32 *stash_idx;
 583         unsigned int num_tx_qs, num_rx_qs;
 584         u32 *tx_queues, *rx_queues;
 585
 586         if (!np || !of_device_is_available(np))
 587                 return -ENODEV;
 588
 589         /* parse the num of tx and rx queues */
 590         tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
 591         num_tx_qs = tx_queues ? *tx_queues : 1;
 592
 593         if (num_tx_qs > MAX_TX_QS) {
 594                 printk(KERN_ERR "num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
 595                                 num_tx_qs, MAX_TX_QS);
 596                 printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n");
 597                 return -EINVAL;
 598         }
 599
 600         rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
 601         num_rx_qs = rx_queues ? *rx_queues : 1;
 602
 603         if (num_rx_qs > MAX_RX_QS) {
 604                 printk(KERN_ERR "num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
 605                                 num_tx_qs, MAX_TX_QS);
 606                 printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n");
 607                 return -EINVAL;
 608         }
 609
 610         *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
 611         dev = *pdev;
 612         if (NULL == dev)
 613                 return -ENOMEM;
 614
 615         priv = netdev_priv(dev);
 616         priv->node = ofdev->node;
 617         priv->ndev = dev;
 618
 619         dev->num_tx_queues = num_tx_qs;
 620         dev->real_num_tx_queues = num_tx_qs;
 621         priv->num_tx_queues = num_tx_qs;
 622         priv->num_rx_queues = num_rx_qs;
 623         priv->num_grps = 0x0;
 624
 625         model = of_get_property(np, "model", NULL);
 626
 627         for (i = 0; i < MAXGROUPS; i++)
 628                 priv->gfargrp[i].regs = NULL;
 629
 630         /* Parse and initialize group specific information */
 631         if (of_device_is_compatible(np, "fsl,etsec2")) {
 632                 priv->mode = MQ_MG_MODE;
 633                 for_each_child_of_node(np, child) {
 634                         err = gfar_parse_group(child, priv, model);
 635                         if (err)
 636                                 goto err_grp_init;
 637                 }
 638         } else {
 639                 priv->mode = SQ_SG_MODE;
 640                 err = gfar_parse_group(np, priv, model);
 641                 if(err)
 642                         goto err_grp_init;
 643         }
 644
 645         for (i = 0; i < priv->num_tx_queues; i++)
 646                priv->tx_queue[i] = NULL;
 647         for (i = 0; i < priv->num_rx_queues; i++)
 648                 priv->rx_queue[i] = NULL;
 649
 650         for (i = 0; i < priv->num_tx_queues; i++) {
 651                 priv->tx_queue[i] =  (struct gfar_priv_tx_q *)kmalloc(
 652                                 sizeof (struct gfar_priv_tx_q), GFP_KERNEL);
 653                 if (!priv->tx_queue[i]) {
 654                         err = -ENOMEM;
 655                         goto tx_alloc_failed;
 656                 }
 657                 priv->tx_queue[i]->tx_skbuff = NULL;
 658                 priv->tx_queue[i]->qindex = i;
 659                 priv->tx_queue[i]->dev = dev;
 660                 spin_lock_init(&(priv->tx_queue[i]->txlock));
 661         }
 662
 663         for (i = 0; i < priv->num_rx_queues; i++) {
 664                 priv->rx_queue[i] = (struct gfar_priv_rx_q *)kmalloc(
 665                                         sizeof (struct gfar_priv_rx_q), GFP_KERNEL);
 666                 if (!priv->rx_queue[i]) {
 667                         err = -ENOMEM;
 668                         goto rx_alloc_failed;
 669                 }
 670                 priv->rx_queue[i]->rx_skbuff = NULL;
 671                 priv->rx_queue[i]->qindex = i;
 672                 priv->rx_queue[i]->dev = dev;
 673                 spin_lock_init(&(priv->rx_queue[i]->rxlock));
 674         }
 675
 676
 677         stash = of_get_property(np, "bd-stash", NULL);
 678
 679         if (stash) {
 680                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
 681                 priv->bd_stash_en = 1;
 682         }
 683
 684         stash_len = of_get_property(np, "rx-stash-len", NULL);
 685
 686         if (stash_len)
 687                 priv->rx_stash_size = *stash_len;
 688
 689         stash_idx = of_get_property(np, "rx-stash-idx", NULL);
 690
 691         if (stash_idx)
 692                 priv->rx_stash_index = *stash_idx;
 693
 694         if (stash_len || stash_idx)
 695                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
 696
 697         mac_addr = of_get_mac_address(np);
 698         if (mac_addr)
 699                 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
 700
 701         if (model && !strcasecmp(model, "TSEC"))
 702                 priv->device_flags =
 703                         FSL_GIANFAR_DEV_HAS_GIGABIT |
 704                         FSL_GIANFAR_DEV_HAS_COALESCE |
 705                         FSL_GIANFAR_DEV_HAS_RMON |
 706                         FSL_GIANFAR_DEV_HAS_MULTI_INTR;
 707         if (model && !strcasecmp(model, "eTSEC"))
 708                 priv->device_flags =
 709                         FSL_GIANFAR_DEV_HAS_GIGABIT |
 710                         FSL_GIANFAR_DEV_HAS_COALESCE |
 711                         FSL_GIANFAR_DEV_HAS_RMON |
 712                         FSL_GIANFAR_DEV_HAS_MULTI_INTR |
 713                         FSL_GIANFAR_DEV_HAS_PADDING |
 714                         FSL_GIANFAR_DEV_HAS_CSUM |
 715                         FSL_GIANFAR_DEV_HAS_VLAN |
 716                         FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
 717                         FSL_GIANFAR_DEV_HAS_EXTENDED_HASH;
 718
 719         ctype = of_get_property(np, "phy-connection-type", NULL);
 720
 721         /* We only care about rgmii-id.  The rest are autodetected */
 722         if (ctype && !strcmp(ctype, "rgmii-id"))
 723                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
 724         else
 725                 priv->interface = PHY_INTERFACE_MODE_MII;
 726
 727         if (of_get_property(np, "fsl,magic-packet", NULL))
 728                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
 729
 730         priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
 731
 732         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
 733         priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
 734
 735         return 0;
 736
 737 rx_alloc_failed:
 738         free_rx_pointers(priv);
 739 tx_alloc_failed:
 740         free_tx_pointers(priv);
 741 err_grp_init:
 742         unmap_group_regs(priv);
 743         free_netdev(dev);
 744         return err;
 745 }
 746
 747 /* Ioctl MII Interface */
 748 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 749 {
 750         struct gfar_private *priv = netdev_priv(dev);
 751
 752         if (!netif_running(dev))
 753                 return -EINVAL;
 754
 755         if (!priv->phydev)
 756                 return -ENODEV;
 757
 758         return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
 759 }
 760
 761 static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
 762 {
 763         unsigned int new_bit_map = 0x0;
 764         int mask = 0x1 << (max_qs - 1), i;
 765         for (i = 0; i < max_qs; i++) {
 766                 if (bit_map & mask)
 767                         new_bit_map = new_bit_map + (1 << i);
 768                 mask = mask >> 0x1;
 769         }
 770         return new_bit_map;
 771 }
 772
 773 u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar, u32 class)
 774 {
 775         u32 rqfpr = FPR_FILER_MASK;
 776         u32 rqfcr = 0x0;
 777
 778         rqfar--;
 779         rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
 780         ftp_rqfpr[rqfar] = rqfpr;
 781         ftp_rqfcr[rqfar] = rqfcr;
 782         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 783
 784         rqfar--;
 785         rqfcr = RQFCR_CMP_NOMATCH;
 786         ftp_rqfpr[rqfar] = rqfpr;
 787         ftp_rqfcr[rqfar] = rqfcr;
 788         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 789
 790         rqfar--;
 791         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
 792         rqfpr = class;
 793         ftp_rqfcr[rqfar] = rqfcr;
 794         ftp_rqfpr[rqfar] = rqfpr;
 795         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 796
 797         rqfar--;
 798         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
 799         rqfpr = class;
 800         ftp_rqfcr[rqfar] = rqfcr;
 801         ftp_rqfpr[rqfar] = rqfpr;
 802         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 803
 804         return rqfar;
 805 }
 806
 807 static void gfar_init_filer_table(struct gfar_private *priv)
 808 {
 809         int i = 0x0;
 810         u32 rqfar = MAX_FILER_IDX;
 811         u32 rqfcr = 0x0;
 812         u32 rqfpr = FPR_FILER_MASK;
 813
 814         /* Default rule */
 815         rqfcr = RQFCR_CMP_MATCH;
 816         ftp_rqfcr[rqfar] = rqfcr;
 817         ftp_rqfpr[rqfar] = rqfpr;
 818         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 819
 820         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
 821         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
 822         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
 823         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
 824         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
 825         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
 826
 827         /* cur_filer_idx indicated the fisrt non-masked rule */
 828         priv->cur_filer_idx = rqfar;
 829
 830         /* Rest are masked rules */
 831         rqfcr = RQFCR_CMP_NOMATCH;
 832         for (i = 0; i < rqfar; i++) {
 833                 ftp_rqfcr[i] = rqfcr;
 834                 ftp_rqfpr[i] = rqfpr;
 835                 gfar_write_filer(priv, i, rqfcr, rqfpr);
 836         }
 837 }
 838
 839 /* Set up the ethernet device structure, private data,
 840  * and anything else we need before we start */
 841 static int gfar_probe(struct of_device *ofdev,
 842                 const struct of_device_id *match)
 843 {
 844         u32 tempval;
 845         struct net_device *dev = NULL;
 846         struct gfar_private *priv = NULL;
 847         struct gfar __iomem *regs = NULL;
 848         int err = 0, i, grp_idx = 0;
 849         int len_devname;
 850         u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
 851         u32 isrg = 0;
 852         u32 *baddr;
 853
 854         err = gfar_of_init(ofdev, &dev);
 855
 856         if (err)
 857                 return err;
 858
 859         priv = netdev_priv(dev);
 860         priv->ndev = dev;
 861         priv->ofdev = ofdev;
 862         priv->node = ofdev->node;
 863         SET_NETDEV_DEV(dev, &ofdev->dev);
 864
 865         spin_lock_init(&priv->bflock);
 866         INIT_WORK(&priv->reset_task, gfar_reset_task);
 867
 868         dev_set_drvdata(&ofdev->dev, priv);
 869         regs = priv->gfargrp[0].regs;
 870
 871         /* Stop the DMA engine now, in case it was running before */
 872         /* (The firmware could have used it, and left it running). */
 873         gfar_halt(dev);
 874
 875         /* Reset MAC layer */
 876         gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
 877
 878         /* We need to delay at least 3 TX clocks */
 879         udelay(2);
 880
 881         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
 882         gfar_write(&regs->maccfg1, tempval);
 883
 884         /* Initialize MACCFG2. */
 885         gfar_write(&regs->maccfg2, MACCFG2_INIT_SETTINGS);
 886
 887         /* Initialize ECNTRL */
 888         gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
 889
 890         /* Set the dev->base_addr to the gfar reg region */
 891         dev->base_addr = (unsigned long) regs;
 892
 893         SET_NETDEV_DEV(dev, &ofdev->dev);
 894
 895         /* Fill in the dev structure */
 896         dev->watchdog_timeo = TX_TIMEOUT;
 897         dev->mtu = 1500;
 898         dev->netdev_ops = &gfar_netdev_ops;
 899         dev->ethtool_ops = &gfar_ethtool_ops;
 900
 901         /* Register for napi ...We are registering NAPI for each grp */
 902         for (i = 0; i < priv->num_grps; i++)
 903                 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, GFAR_DEV_WEIGHT);
 904
 905         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
 906                 priv->rx_csum_enable = 1;
 907                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;
 908         } else
 909                 priv->rx_csum_enable = 0;
 910
 911         priv->vlgrp = NULL;
 912
 913         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)
 914                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
 915
 916         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
 917                 priv->extended_hash = 1;
 918                 priv->hash_width = 9;
 919
 920                 priv->hash_regs[0] = &regs->igaddr0;
 921                 priv->hash_regs[1] = &regs->igaddr1;
 922                 priv->hash_regs[2] = &regs->igaddr2;
 923                 priv->hash_regs[3] = &regs->igaddr3;
 924                 priv->hash_regs[4] = &regs->igaddr4;
 925                 priv->hash_regs[5] = &regs->igaddr5;
 926                 priv->hash_regs[6] = &regs->igaddr6;
 927                 priv->hash_regs[7] = &regs->igaddr7;
 928                 priv->hash_regs[8] = &regs->gaddr0;
 929                 priv->hash_regs[9] = &regs->gaddr1;
 930                 priv->hash_regs[10] = &regs->gaddr2;
 931                 priv->hash_regs[11] = &regs->gaddr3;
 932                 priv->hash_regs[12] = &regs->gaddr4;
 933                 priv->hash_regs[13] = &regs->gaddr5;
 934                 priv->hash_regs[14] = &regs->gaddr6;
 935                 priv->hash_regs[15] = &regs->gaddr7;
 936
 937         } else {
 938                 priv->extended_hash = 0;
 939                 priv->hash_width = 8;
 940
 941                 priv->hash_regs[0] = &regs->gaddr0;
 942                 priv->hash_regs[1] = &regs->gaddr1;
 943                 priv->hash_regs[2] = &regs->gaddr2;
 944                 priv->hash_regs[3] = &regs->gaddr3;
 945                 priv->hash_regs[4] = &regs->gaddr4;
 946                 priv->hash_regs[5] = &regs->gaddr5;
 947                 priv->hash_regs[6] = &regs->gaddr6;
 948                 priv->hash_regs[7] = &regs->gaddr7;
 949         }
 950
 951         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
 952                 priv->padding = DEFAULT_PADDING;
 953         else
 954                 priv->padding = 0;
 955
 956         if (dev->features & NETIF_F_IP_CSUM)
 957                 dev->hard_header_len += GMAC_FCB_LEN;
 958
 959         /* Program the isrg regs only if number of grps > 1 */
 960         if (priv->num_grps > 1) {
 961                 baddr = &regs->isrg0;
 962                 for (i = 0; i < priv->num_grps; i++) {
 963                         isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
 964                         isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
 965                         gfar_write(baddr, isrg);
 966                         baddr++;
 967                         isrg = 0x0;
 968                 }
 969         }
 970
 971         /* Need to reverse the bit maps as  bit_map's MSB is q0
 972          * but, for_each_bit parses from right to left, which
 973          * basically reverses the queue numbers */
 974         for (i = 0; i< priv->num_grps; i++) {
 975                 priv->gfargrp[i].tx_bit_map = reverse_bitmap(
 976                                 priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
 977                 priv->gfargrp[i].rx_bit_map = reverse_bitmap(
 978                                 priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
 979         }
 980
 981         /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
 982          * also assign queues to groups */
 983         for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
 984                 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
 985                 for_each_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
 986                                 priv->num_rx_queues) {
 987                         priv->gfargrp[grp_idx].num_rx_queues++;
 988                         priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
 989                         rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
 990                         rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
 991                 }
 992                 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
 993                 for_each_bit (i, &priv->gfargrp[grp_idx].tx_bit_map,
 994                                 priv->num_tx_queues) {
 995                         priv->gfargrp[grp_idx].num_tx_queues++;
 996                         priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
 997                         tstat = tstat | (TSTAT_CLEAR_THALT >> i);
 998                         tqueue = tqueue | (TQUEUE_EN0 >> i);
 999                 }
1000                 priv->gfargrp[grp_idx].rstat = rstat;
1001                 priv->gfargrp[grp_idx].tstat = tstat;
1002                 rstat = tstat =0;
1003         }
1004
1005         gfar_write(&regs->rqueue, rqueue);
1006         gfar_write(&regs->tqueue, tqueue);
1007
1008         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1009
1010         /* Initializing some of the rx/tx queue level parameters */
1011         for (i = 0; i < priv->num_tx_queues; i++) {
1012                 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1013                 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1014                 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1015                 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1016         }
1017
1018         for (i = 0; i < priv->num_rx_queues; i++) {
1019                 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1020                 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1021                 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1022         }
1023
1024         /* Enable most messages by default */
1025         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1026
1027         /* Carrier starts down, phylib will bring it up */
1028         netif_carrier_off(dev);
1029
1030         err = register_netdev(dev);
1031
1032         if (err) {
1033                 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
1034                                 dev->name);
1035                 goto register_fail;
1036         }
1037
1038         device_init_wakeup(&dev->dev,
1039                 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1040
1041         /* fill out IRQ number and name fields */
1042         len_devname = strlen(dev->name);
1043         for (i = 0; i < priv->num_grps; i++) {
1044                 strncpy(&priv->gfargrp[i].int_name_tx[0], dev->name,
1045                                 len_devname);
1046                 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1047                         strncpy(&priv->gfargrp[i].int_name_tx[len_devname],
1048                                 "_g", sizeof("_g"));
1049                         priv->gfargrp[i].int_name_tx[
1050                                 strlen(priv->gfargrp[i].int_name_tx)] = i+48;
1051                         strncpy(&priv->gfargrp[i].int_name_tx[strlen(
1052                                 priv->gfargrp[i].int_name_tx)],
1053                                 "_tx", sizeof("_tx") + 1);
1054
1055                         strncpy(&priv->gfargrp[i].int_name_rx[0], dev->name,
1056                                         len_devname);
1057                         strncpy(&priv->gfargrp[i].int_name_rx[len_devname],
1058                                         "_g", sizeof("_g"));
1059                         priv->gfargrp[i].int_name_rx[
1060                                 strlen(priv->gfargrp[i].int_name_rx)] = i+48;
1061                         strncpy(&priv->gfargrp[i].int_name_rx[strlen(
1062                                 priv->gfargrp[i].int_name_rx)],
1063                                 "_rx", sizeof("_rx") + 1);
1064
1065                         strncpy(&priv->gfargrp[i].int_name_er[0], dev->name,
1066                                         len_devname);
1067                         strncpy(&priv->gfargrp[i].int_name_er[len_devname],
1068                                 "_g", sizeof("_g"));
1069                         priv->gfargrp[i].int_name_er[strlen(
1070                                         priv->gfargrp[i].int_name_er)] = i+48;
1071                         strncpy(&priv->gfargrp[i].int_name_er[strlen(\
1072                                 priv->gfargrp[i].int_name_er)],
1073                                 "_er", sizeof("_er") + 1);
1074                 } else
1075                         priv->gfargrp[i].int_name_tx[len_devname] = '\0';
1076         }
1077
1078         /* Initialize the filer table */
1079         gfar_init_filer_table(priv);
1080
1081         /* Create all the sysfs files */
1082         gfar_init_sysfs(dev);
1083
1084         /* Print out the device info */
1085         printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
1086
1087         /* Even more device info helps when determining which kernel */
1088         /* provided which set of benchmarks. */
1089         printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
1090         for (i = 0; i < priv->num_rx_queues; i++)
1091                 printk(KERN_INFO "%s: :RX BD ring size for Q[%d]: %d\n",
1092                         dev->name, i, priv->rx_queue[i]->rx_ring_size);
1093         for(i = 0; i < priv->num_tx_queues; i++)
1094                  printk(KERN_INFO "%s:TX BD ring size for Q[%d]: %d\n",
1095                         dev->name, i, priv->tx_queue[i]->tx_ring_size);
1096
1097         return 0;
1098
1099 register_fail:
1100         unmap_group_regs(priv);
1101         free_tx_pointers(priv);
1102         free_rx_pointers(priv);
1103         if (priv->phy_node)
1104                 of_node_put(priv->phy_node);
1105         if (priv->tbi_node)
1106                 of_node_put(priv->tbi_node);
1107         free_netdev(dev);
1108         return err;
1109 }
1110
1111 static int gfar_remove(struct of_device *ofdev)
1112 {
1113         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
1114
1115         if (priv->phy_node)
1116                 of_node_put(priv->phy_node);
1117         if (priv->tbi_node)
1118                 of_node_put(priv->tbi_node);
1119
1120         dev_set_drvdata(&ofdev->dev, NULL);
1121
1122         unregister_netdev(priv->ndev);
1123         unmap_group_regs(priv);
1124         free_netdev(priv->ndev);
1125
1126         return 0;
1127 }
1128
1129 #ifdef CONFIG_PM
1130
1131 static int gfar_suspend(struct device *dev)
1132 {
1133         struct gfar_private *priv = dev_get_drvdata(dev);
1134         struct net_device *ndev = priv->ndev;
1135         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1136         unsigned long flags;
1137         u32 tempval;
1138
1139         int magic_packet = priv->wol_en &&
1140                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1141
1142         netif_device_detach(ndev);
1143
1144         if (netif_running(ndev)) {
1145
1146                 local_irq_save(flags);
1147                 lock_tx_qs(priv);
1148                 lock_rx_qs(priv);
1149
1150                 gfar_halt_nodisable(ndev);
1151
1152                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1153                 tempval = gfar_read(&regs->maccfg1);
1154
1155                 tempval &= ~MACCFG1_TX_EN;
1156
1157                 if (!magic_packet)
1158                         tempval &= ~MACCFG1_RX_EN;
1159
1160                 gfar_write(&regs->maccfg1, tempval);
1161
1162                 unlock_rx_qs(priv);
1163                 unlock_tx_qs(priv);
1164                 local_irq_restore(flags);
1165
1166                 disable_napi(priv);
1167
1168                 if (magic_packet) {
1169                         /* Enable interrupt on Magic Packet */
1170                         gfar_write(&regs->imask, IMASK_MAG);
1171
1172                         /* Enable Magic Packet mode */
1173                         tempval = gfar_read(&regs->maccfg2);
1174                         tempval |= MACCFG2_MPEN;
1175                         gfar_write(&regs->maccfg2, tempval);
1176                 } else {
1177                         phy_stop(priv->phydev);
1178                 }
1179         }
1180
1181         return 0;
1182 }
1183
1184 static int gfar_resume(struct device *dev)
1185 {
1186         struct gfar_private *priv = dev_get_drvdata(dev);
1187         struct net_device *ndev = priv->ndev;
1188         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1189         unsigned long flags;
1190         u32 tempval;
1191         int magic_packet = priv->wol_en &&
1192                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1193
1194         if (!netif_running(ndev)) {
1195                 netif_device_attach(ndev);
1196                 return 0;
1197         }
1198
1199         if (!magic_packet && priv->phydev)
1200                 phy_start(priv->phydev);
1201
1202         /* Disable Magic Packet mode, in case something
1203          * else woke us up.
1204          */
1205         local_irq_save(flags);
1206         lock_tx_qs(priv);
1207         lock_rx_qs(priv);
1208
1209         tempval = gfar_read(&regs->maccfg2);
1210         tempval &= ~MACCFG2_MPEN;
1211         gfar_write(&regs->maccfg2, tempval);
1212
1213         gfar_start(ndev);
1214
1215         unlock_rx_qs(priv);
1216         unlock_tx_qs(priv);
1217         local_irq_restore(flags);
1218
1219         netif_device_attach(ndev);
1220
1221         enable_napi(priv);
1222
1223         return 0;
1224 }
1225
1226 static int gfar_restore(struct device *dev)
1227 {
1228         struct gfar_private *priv = dev_get_drvdata(dev);
1229         struct net_device *ndev = priv->ndev;
1230
1231         if (!netif_running(ndev))
1232                 return 0;
1233
1234         gfar_init_bds(ndev);
1235         init_registers(ndev);
1236         gfar_set_mac_address(ndev);
1237         gfar_init_mac(ndev);
1238         gfar_start(ndev);
1239
1240         priv->oldlink = 0;
1241         priv->oldspeed = 0;
1242         priv->oldduplex = -1;
1243
1244         if (priv->phydev)
1245                 phy_start(priv->phydev);
1246
1247         netif_device_attach(ndev);
1248         napi_enable(&priv->gfargrp.napi);
1249
1250         return 0;
1251 }
1252
1253 static struct dev_pm_ops gfar_pm_ops = {
1254         .suspend = gfar_suspend,
1255         .resume = gfar_resume,
1256         .freeze = gfar_suspend,
1257         .thaw = gfar_resume,
1258         .restore = gfar_restore,
1259 };
1260
1261 #define GFAR_PM_OPS (&gfar_pm_ops)
1262
1263 static int gfar_legacy_suspend(struct of_device *ofdev, pm_message_t state)
1264 {
1265         return gfar_suspend(&ofdev->dev);
1266 }
1267
1268 static int gfar_legacy_resume(struct of_device *ofdev)
1269 {
1270         return gfar_resume(&ofdev->dev);
1271 }
1272
1273 #else
1274
1275 #define GFAR_PM_OPS NULL
1276 #define gfar_legacy_suspend NULL
1277 #define gfar_legacy_resume NULL
1278
1279 #endif
1280
1281 /* Reads the controller's registers to determine what interface
1282  * connects it to the PHY.
1283  */
1284 static phy_interface_t gfar_get_interface(struct net_device *dev)
1285 {
1286         struct gfar_private *priv = netdev_priv(dev);
1287         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1288         u32 ecntrl;
1289
1290         ecntrl = gfar_read(&regs->ecntrl);
1291
1292         if (ecntrl & ECNTRL_SGMII_MODE)
1293                 return PHY_INTERFACE_MODE_SGMII;
1294
1295         if (ecntrl & ECNTRL_TBI_MODE) {
1296                 if (ecntrl & ECNTRL_REDUCED_MODE)
1297                         return PHY_INTERFACE_MODE_RTBI;
1298                 else
1299                         return PHY_INTERFACE_MODE_TBI;
1300         }
1301
1302         if (ecntrl & ECNTRL_REDUCED_MODE) {
1303                 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
1304                         return PHY_INTERFACE_MODE_RMII;
1305                 else {
1306                         phy_interface_t interface = priv->interface;
1307
1308                         /*
1309                          * This isn't autodetected right now, so it must
1310                          * be set by the device tree or platform code.
1311                          */
1312                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1313                                 return PHY_INTERFACE_MODE_RGMII_ID;
1314
1315                         return PHY_INTERFACE_MODE_RGMII;
1316                 }
1317         }
1318
1319         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1320                 return PHY_INTERFACE_MODE_GMII;
1321
1322         return PHY_INTERFACE_MODE_MII;
1323 }
1324
1325
1326 /* Initializes driver's PHY state, and attaches to the PHY.
1327  * Returns 0 on success.
1328  */
1329 static int init_phy(struct net_device *dev)
1330 {
1331         struct gfar_private *priv = netdev_priv(dev);
1332         uint gigabit_support =
1333                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1334                 SUPPORTED_1000baseT_Full : 0;
1335         phy_interface_t interface;
1336
1337         priv->oldlink = 0;
1338         priv->oldspeed = 0;
1339         priv->oldduplex = -1;
1340
1341         interface = gfar_get_interface(dev);
1342
1343         priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1344                                       interface);
1345         if (!priv->phydev)
1346                 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1347                                                          interface);
1348         if (!priv->phydev) {
1349                 dev_err(&dev->dev, "could not attach to PHY\n");
1350                 return -ENODEV;
1351         }
1352
1353         if (interface == PHY_INTERFACE_MODE_SGMII)
1354                 gfar_configure_serdes(dev);
1355
1356         /* Remove any features not supported by the controller */
1357         priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1358         priv->phydev->advertising = priv->phydev->supported;
1359
1360         return 0;
1361 }
1362
1363 /*
1364  * Initialize TBI PHY interface for communicating with the
1365  * SERDES lynx PHY on the chip.  We communicate with this PHY
1366  * through the MDIO bus on each controller, treating it as a
1367  * "normal" PHY at the address found in the TBIPA register.  We assume
1368  * that the TBIPA register is valid.  Either the MDIO bus code will set
1369  * it to a value that doesn't conflict with other PHYs on the bus, or the
1370  * value doesn't matter, as there are no other PHYs on the bus.
1371  */
1372 static void gfar_configure_serdes(struct net_device *dev)
1373 {
1374         struct gfar_private *priv = netdev_priv(dev);
1375         struct phy_device *tbiphy;
1376
1377         if (!priv->tbi_node) {
1378                 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1379                                     "device tree specify a tbi-handle\n");
1380                 return;
1381         }
1382
1383         tbiphy = of_phy_find_device(priv->tbi_node);
1384         if (!tbiphy) {
1385                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1386                 return;
1387         }
1388
1389         /*
1390          * If the link is already up, we must already be ok, and don't need to
1391          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1392          * everything for us?  Resetting it takes the link down and requires
1393          * several seconds for it to come back.
1394          */
1395         if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1396                 return;
1397
1398         /* Single clk mode, mii mode off(for serdes communication) */
1399         phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1400
1401         phy_write(tbiphy, MII_ADVERTISE,
1402                         ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1403                         ADVERTISE_1000XPSE_ASYM);
1404
1405         phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE |
1406                         BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
1407 }
1408
1409 static void init_registers(struct net_device *dev)
1410 {
1411         struct gfar_private *priv = netdev_priv(dev);
1412         struct gfar __iomem *regs = NULL;
1413         int i = 0;
1414
1415         for (i = 0; i < priv->num_grps; i++) {
1416                 regs = priv->gfargrp[i].regs;
1417                 /* Clear IEVENT */
1418                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1419
1420                 /* Initialize IMASK */
1421                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1422         }
1423
1424         regs = priv->gfargrp[0].regs;
1425         /* Init hash registers to zero */
1426         gfar_write(&regs->igaddr0, 0);
1427         gfar_write(&regs->igaddr1, 0);
1428         gfar_write(&regs->igaddr2, 0);
1429         gfar_write(&regs->igaddr3, 0);
1430         gfar_write(&regs->igaddr4, 0);
1431         gfar_write(&regs->igaddr5, 0);
1432         gfar_write(&regs->igaddr6, 0);
1433         gfar_write(&regs->igaddr7, 0);
1434
1435         gfar_write(&regs->gaddr0, 0);
1436         gfar_write(&regs->gaddr1, 0);
1437         gfar_write(&regs->gaddr2, 0);
1438         gfar_write(&regs->gaddr3, 0);
1439         gfar_write(&regs->gaddr4, 0);
1440         gfar_write(&regs->gaddr5, 0);
1441         gfar_write(&regs->gaddr6, 0);
1442         gfar_write(&regs->gaddr7, 0);
1443
1444         /* Zero out the rmon mib registers if it has them */
1445         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1446                 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1447
1448                 /* Mask off the CAM interrupts */
1449                 gfar_write(&regs->rmon.cam1, 0xffffffff);
1450                 gfar_write(&regs->rmon.cam2, 0xffffffff);
1451         }
1452
1453         /* Initialize the max receive buffer length */
1454         gfar_write(&regs->mrblr, priv->rx_buffer_size);
1455
1456         /* Initialize the Minimum Frame Length Register */
1457         gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1458 }
1459
1460
1461 /* Halt the receive and transmit queues */
1462 static void gfar_halt_nodisable(struct net_device *dev)
1463 {
1464         struct gfar_private *priv = netdev_priv(dev);
1465         struct gfar __iomem *regs = NULL;
1466         u32 tempval;
1467         int i = 0;
1468
1469         for (i = 0; i < priv->num_grps; i++) {
1470                 regs = priv->gfargrp[i].regs;
1471                 /* Mask all interrupts */
1472                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1473
1474                 /* Clear all interrupts */
1475                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1476         }
1477
1478         regs = priv->gfargrp[0].regs;
1479         /* Stop the DMA, and wait for it to stop */
1480         tempval = gfar_read(&regs->dmactrl);
1481         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
1482             != (DMACTRL_GRS | DMACTRL_GTS)) {
1483                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1484                 gfar_write(&regs->dmactrl, tempval);
1485
1486                 while (!(gfar_read(&regs->ievent) &
1487                          (IEVENT_GRSC | IEVENT_GTSC)))
1488                         cpu_relax();
1489         }
1490 }
1491
1492 /* Halt the receive and transmit queues */
1493 void gfar_halt(struct net_device *dev)
1494 {
1495         struct gfar_private *priv = netdev_priv(dev);
1496         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1497         u32 tempval;
1498
1499         gfar_halt_nodisable(dev);
1500
1501         /* Disable Rx and Tx */
1502         tempval = gfar_read(&regs->maccfg1);
1503         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1504         gfar_write(&regs->maccfg1, tempval);
1505 }
1506
1507 static void free_grp_irqs(struct gfar_priv_grp *grp)
1508 {
1509         free_irq(grp->interruptError, grp);
1510         free_irq(grp->interruptTransmit, grp);
1511         free_irq(grp->interruptReceive, grp);
1512 }
1513
1514 void stop_gfar(struct net_device *dev)
1515 {
1516         struct gfar_private *priv = netdev_priv(dev);
1517         unsigned long flags;
1518         int i;
1519
1520         phy_stop(priv->phydev);
1521
1522
1523         /* Lock it down */
1524         local_irq_save(flags);
1525         lock_tx_qs(priv);
1526         lock_rx_qs(priv);
1527
1528         gfar_halt(dev);
1529
1530         unlock_rx_qs(priv);
1531         unlock_tx_qs(priv);
1532         local_irq_restore(flags);
1533
1534         /* Free the IRQs */
1535         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1536                 for (i = 0; i < priv->num_grps; i++)
1537                         free_grp_irqs(&priv->gfargrp[i]);
1538         } else {
1539                 for (i = 0; i < priv->num_grps; i++)
1540                         free_irq(priv->gfargrp[i].interruptTransmit,
1541                                         &priv->gfargrp[i]);
1542         }
1543
1544         free_skb_resources(priv);
1545 }
1546
1547 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1548 {
1549         struct txbd8 *txbdp;
1550         struct gfar_private *priv = netdev_priv(tx_queue->dev);
1551         int i, j;
1552
1553         txbdp = tx_queue->tx_bd_base;
1554
1555         for (i = 0; i < tx_queue->tx_ring_size; i++) {
1556                 if (!tx_queue->tx_skbuff[i])
1557                         continue;
1558
1559                 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
1560                                 txbdp->length, DMA_TO_DEVICE);
1561                 txbdp->lstatus = 0;
1562                 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1563                                 j++) {
1564                         txbdp++;
1565                         dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
1566                                         txbdp->length, DMA_TO_DEVICE);
1567                 }
1568                 txbdp++;
1569                 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1570                 tx_queue->tx_skbuff[i] = NULL;
1571         }
1572         kfree(tx_queue->tx_skbuff);
1573 }
1574
1575 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1576 {
1577         struct rxbd8 *rxbdp;
1578         struct gfar_private *priv = netdev_priv(rx_queue->dev);
1579         int i;
1580
1581         rxbdp = rx_queue->rx_bd_base;
1582
1583         for (i = 0; i < rx_queue->rx_ring_size; i++) {
1584                 if (rx_queue->rx_skbuff[i]) {
1585                         dma_unmap_single(&priv->ofdev->dev,
1586                                         rxbdp->bufPtr, priv->rx_buffer_size,
1587                                         DMA_FROM_DEVICE);
1588                         dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1589                         rx_queue->rx_skbuff[i] = NULL;
1590                 }
1591                 rxbdp->lstatus = 0;
1592                 rxbdp->bufPtr = 0;
1593                 rxbdp++;
1594         }
1595         kfree(rx_queue->rx_skbuff);
1596 }
1597
1598 /* If there are any tx skbs or rx skbs still around, free them.
1599  * Then free tx_skbuff and rx_skbuff */
1600 static void free_skb_resources(struct gfar_private *priv)
1601 {
1602         struct gfar_priv_tx_q *tx_queue = NULL;
1603         struct gfar_priv_rx_q *rx_queue = NULL;
1604         int i;
1605
1606         /* Go through all the buffer descriptors and free their data buffers */
1607         for (i = 0; i < priv->num_tx_queues; i++) {
1608                 tx_queue = priv->tx_queue[i];
1609                 if(!tx_queue->tx_skbuff)
1610                         free_skb_tx_queue(tx_queue);
1611         }
1612
1613         for (i = 0; i < priv->num_rx_queues; i++) {
1614                 rx_queue = priv->rx_queue[i];
1615                 if(!rx_queue->rx_skbuff)
1616                         free_skb_rx_queue(rx_queue);
1617         }
1618
1619         dma_free_coherent(&priv->ofdev->dev,
1620                         sizeof(struct txbd8) * priv->total_tx_ring_size +
1621                         sizeof(struct rxbd8) * priv->total_rx_ring_size,
1622                         priv->tx_queue[0]->tx_bd_base,
1623                         priv->tx_queue[0]->tx_bd_dma_base);
1624 }
1625
1626 void gfar_start(struct net_device *dev)
1627 {
1628         struct gfar_private *priv = netdev_priv(dev);
1629         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1630         u32 tempval;
1631         int i = 0;
1632
1633         /* Enable Rx and Tx in MACCFG1 */
1634         tempval = gfar_read(&regs->maccfg1);
1635         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1636         gfar_write(&regs->maccfg1, tempval);
1637
1638         /* Initialize DMACTRL to have WWR and WOP */
1639         tempval = gfar_read(&regs->dmactrl);
1640         tempval |= DMACTRL_INIT_SETTINGS;
1641         gfar_write(&regs->dmactrl, tempval);
1642
1643         /* Make sure we aren't stopped */
1644         tempval = gfar_read(&regs->dmactrl);
1645         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1646         gfar_write(&regs->dmactrl, tempval);
1647
1648         for (i = 0; i < priv->num_grps; i++) {
1649                 regs = priv->gfargrp[i].regs;
1650                 /* Clear THLT/RHLT, so that the DMA starts polling now */
1651                 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1652                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1653                 /* Unmask the interrupts we look for */
1654                 gfar_write(&regs->imask, IMASK_DEFAULT);
1655         }
1656
1657         dev->trans_start = jiffies;
1658 }
1659
1660 void gfar_configure_coalescing(struct gfar_private *priv,
1661         unsigned int tx_mask, unsigned int rx_mask)
1662 {
1663         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1664         u32 *baddr;
1665         int i = 0;
1666
1667         /* Backward compatible case ---- even if we enable
1668          * multiple queues, there's only single reg to program
1669          */
1670         gfar_write(&regs->txic, 0);
1671         if(likely(priv->tx_queue[0]->txcoalescing))
1672                 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1673
1674         gfar_write(&regs->rxic, 0);
1675         if(unlikely(priv->rx_queue[0]->rxcoalescing))
1676                 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
1677
1678         if (priv->mode == MQ_MG_MODE) {
1679                 baddr = &regs->txic0;
1680                 for_each_bit (i, &tx_mask, priv->num_tx_queues) {
1681                         if (likely(priv->tx_queue[i]->txcoalescing)) {
1682                                 gfar_write(baddr + i, 0);
1683                                 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1684                         }
1685                 }
1686
1687                 baddr = &regs->rxic0;
1688                 for_each_bit (i, &rx_mask, priv->num_rx_queues) {
1689                         if (likely(priv->rx_queue[i]->rxcoalescing)) {
1690                                 gfar_write(baddr + i, 0);
1691                                 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1692                         }
1693                 }
1694         }
1695 }
1696
1697 static int register_grp_irqs(struct gfar_priv_grp *grp)
1698 {
1699         struct gfar_private *priv = grp->priv;
1700         struct net_device *dev = priv->ndev;
1701         int err;
1702
1703         /* If the device has multiple interrupts, register for
1704          * them.  Otherwise, only register for the one */
1705         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1706                 /* Install our interrupt handlers for Error,
1707                  * Transmit, and Receive */
1708                 if ((err = request_irq(grp->interruptError, gfar_error, 0,
1709                                 grp->int_name_er,grp)) < 0) {
1710                         if (netif_msg_intr(priv))
1711                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1712                                         dev->name, grp->interruptError);
1713
1714                                 goto err_irq_fail;
1715                 }
1716
1717                 if ((err = request_irq(grp->interruptTransmit, gfar_transmit,
1718                                 0, grp->int_name_tx, grp)) < 0) {
1719                         if (netif_msg_intr(priv))
1720                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1721                                         dev->name, grp->interruptTransmit);
1722                         goto tx_irq_fail;
1723                 }
1724
1725                 if ((err = request_irq(grp->interruptReceive, gfar_receive, 0,
1726                                 grp->int_name_rx, grp)) < 0) {
1727                         if (netif_msg_intr(priv))
1728                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1729                                         dev->name, grp->interruptReceive);
1730                         goto rx_irq_fail;
1731                 }
1732         } else {
1733                 if ((err = request_irq(grp->interruptTransmit, gfar_interrupt, 0,
1734                                 grp->int_name_tx, grp)) < 0) {
1735                         if (netif_msg_intr(priv))
1736                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1737                                         dev->name, grp->interruptTransmit);
1738                         goto err_irq_fail;
1739                 }
1740         }
1741
1742         return 0;
1743
1744 rx_irq_fail:
1745         free_irq(grp->interruptTransmit, grp);
1746 tx_irq_fail:
1747         free_irq(grp->interruptError, grp);
1748 err_irq_fail:
1749         return err;
1750
1751 }
1752
1753 /* Bring the controller up and running */
1754 int startup_gfar(struct net_device *ndev)
1755 {
1756         struct gfar_private *priv = netdev_priv(ndev);
1757         struct gfar __iomem *regs = NULL;
1758         int err, i, j;
1759
1760         for (i = 0; i < priv->num_grps; i++) {
1761                 regs= priv->gfargrp[i].regs;
1762                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1763         }
1764
1765         regs= priv->gfargrp[0].regs;
1766         err = gfar_alloc_skb_resources(ndev);
1767         if (err)
1768                 return err;
1769
1770         gfar_init_mac(ndev);
1771
1772         for (i = 0; i < priv->num_grps; i++) {
1773                 err = register_grp_irqs(&priv->gfargrp[i]);
1774                 if (err) {
1775                         for (j = 0; j < i; j++)
1776                                 free_grp_irqs(&priv->gfargrp[j]);
1777                                 goto irq_fail;
1778                 }
1779         }
1780
1781         /* Start the controller */
1782         gfar_start(ndev);
1783
1784         phy_start(priv->phydev);
1785
1786         gfar_configure_coalescing(priv, 0xFF, 0xFF);
1787
1788         return 0;
1789
1790 irq_fail:
1791         free_skb_resources(priv);
1792         return err;
1793 }
1794
1795 /* Called when something needs to use the ethernet device */
1796 /* Returns 0 for success. */
1797 static int gfar_enet_open(struct net_device *dev)
1798 {
1799         struct gfar_private *priv = netdev_priv(dev);
1800         int err;
1801
1802         enable_napi(priv);
1803
1804         skb_queue_head_init(&priv->rx_recycle);
1805
1806         /* Initialize a bunch of registers */
1807         init_registers(dev);
1808
1809         gfar_set_mac_address(dev);
1810
1811         err = init_phy(dev);
1812
1813         if (err) {
1814                 disable_napi(priv);
1815                 return err;
1816         }
1817
1818         err = startup_gfar(dev);
1819         if (err) {
1820                 disable_napi(priv);
1821                 return err;
1822         }
1823
1824         netif_tx_start_all_queues(dev);
1825
1826         device_set_wakeup_enable(&dev->dev, priv->wol_en);
1827
1828         return err;
1829 }
1830
1831 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1832 {
1833         struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1834
1835         memset(fcb, 0, GMAC_FCB_LEN);
1836
1837         return fcb;
1838 }
1839
1840 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1841 {
1842         u8 flags = 0;
1843
1844         /* If we're here, it's a IP packet with a TCP or UDP
1845          * payload.  We set it to checksum, using a pseudo-header
1846          * we provide
1847          */
1848         flags = TXFCB_DEFAULT;
1849
1850         /* Tell the controller what the protocol is */
1851         /* And provide the already calculated phcs */
1852         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1853                 flags |= TXFCB_UDP;
1854                 fcb->phcs = udp_hdr(skb)->check;
1855         } else
1856                 fcb->phcs = tcp_hdr(skb)->check;
1857
1858         /* l3os is the distance between the start of the
1859          * frame (skb->data) and the start of the IP hdr.
1860          * l4os is the distance between the start of the
1861          * l3 hdr and the l4 hdr */
1862         fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
1863         fcb->l4os = skb_network_header_len(skb);
1864
1865         fcb->flags = flags;
1866 }
1867
1868 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1869 {
1870         fcb->flags |= TXFCB_VLN;
1871         fcb->vlctl = vlan_tx_tag_get(skb);
1872 }
1873
1874 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
1875                                struct txbd8 *base, int ring_size)
1876 {
1877         struct txbd8 *new_bd = bdp + stride;
1878
1879         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
1880 }
1881
1882 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
1883                 int ring_size)
1884 {
1885         return skip_txbd(bdp, 1, base, ring_size);
1886 }
1887
1888 /* This is called by the kernel when a frame is ready for transmission. */
1889 /* It is pointed to by the dev->hard_start_xmit function pointer */
1890 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1891 {
1892         struct gfar_private *priv = netdev_priv(dev);
1893         struct gfar_priv_tx_q *tx_queue = NULL;
1894         struct netdev_queue *txq;
1895         struct gfar __iomem *regs = NULL;
1896         struct txfcb *fcb = NULL;
1897         struct txbd8 *txbdp, *txbdp_start, *base;
1898         u32 lstatus;
1899         int i, rq = 0;
1900         u32 bufaddr;
1901         unsigned long flags;
1902         unsigned int nr_frags, length;
1903
1904
1905         rq = skb->queue_mapping;
1906         tx_queue = priv->tx_queue[rq];
1907         txq = netdev_get_tx_queue(dev, rq);
1908         base = tx_queue->tx_bd_base;
1909         regs = tx_queue->grp->regs;
1910
1911         /* make space for additional header when fcb is needed */
1912         if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
1913                         (priv->vlgrp && vlan_tx_tag_present(skb))) &&
1914                         (skb_headroom(skb) < GMAC_FCB_LEN)) {
1915                 struct sk_buff *skb_new;
1916
1917                 skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN);
1918                 if (!skb_new) {
1919                         dev->stats.tx_errors++;
1920                         kfree_skb(skb);
1921                         return NETDEV_TX_OK;
1922                 }
1923                 kfree_skb(skb);
1924                 skb = skb_new;
1925         }
1926
1927         /* total number of fragments in the SKB */
1928         nr_frags = skb_shinfo(skb)->nr_frags;
1929
1930         spin_lock_irqsave(&tx_queue->txlock, flags);
1931
1932         /* check if there is space to queue this packet */
1933         if ((nr_frags+1) > tx_queue->num_txbdfree) {
1934                 /* no space, stop the queue */
1935                 netif_tx_stop_queue(txq);
1936                 dev->stats.tx_fifo_errors++;
1937                 spin_unlock_irqrestore(&tx_queue->txlock, flags);
1938                 return NETDEV_TX_BUSY;
1939         }
1940
1941         /* Update transmit stats */
1942         dev->stats.tx_bytes += skb->len;
1943
1944         txbdp = txbdp_start = tx_queue->cur_tx;
1945
1946         if (nr_frags == 0) {
1947                 lstatus = txbdp->lstatus | BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1948         } else {
1949                 /* Place the fragment addresses and lengths into the TxBDs */
1950                 for (i = 0; i < nr_frags; i++) {
1951                         /* Point at the next BD, wrapping as needed */
1952                         txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
1953
1954                         length = skb_shinfo(skb)->frags[i].size;
1955
1956                         lstatus = txbdp->lstatus | length |
1957                                 BD_LFLAG(TXBD_READY);
1958
1959                         /* Handle the last BD specially */
1960                         if (i == nr_frags - 1)
1961                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1962
1963                         bufaddr = dma_map_page(&priv->ofdev->dev,
1964                                         skb_shinfo(skb)->frags[i].page,
1965                                         skb_shinfo(skb)->frags[i].page_offset,
1966                                         length,
1967                                         DMA_TO_DEVICE);
1968
1969                         /* set the TxBD length and buffer pointer */
1970                         txbdp->bufPtr = bufaddr;
1971                         txbdp->lstatus = lstatus;
1972                 }
1973
1974                 lstatus = txbdp_start->lstatus;
1975         }
1976
1977         /* Set up checksumming */
1978         if (CHECKSUM_PARTIAL == skb->ip_summed) {
1979                 fcb = gfar_add_fcb(skb);
1980                 lstatus |= BD_LFLAG(TXBD_TOE);
1981                 gfar_tx_checksum(skb, fcb);
1982         }
1983
1984         if (priv->vlgrp && vlan_tx_tag_present(skb)) {
1985                 if (unlikely(NULL == fcb)) {
1986                         fcb = gfar_add_fcb(skb);
1987                         lstatus |= BD_LFLAG(TXBD_TOE);
1988                 }
1989
1990                 gfar_tx_vlan(skb, fcb);
1991         }
1992
1993         /* setup the TxBD length and buffer pointer for the first BD */
1994         tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
1995         txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
1996                         skb_headlen(skb), DMA_TO_DEVICE);
1997
1998         lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
1999
2000         /*
2001          * The powerpc-specific eieio() is used, as wmb() has too strong
2002          * semantics (it requires synchronization between cacheable and
2003          * uncacheable mappings, which eieio doesn't provide and which we
2004          * don't need), thus requiring a more expensive sync instruction.  At
2005          * some point, the set of architecture-independent barrier functions
2006          * should be expanded to include weaker barriers.
2007          */
2008         eieio();
2009
2010         txbdp_start->lstatus = lstatus;
2011
2012         /* Update the current skb pointer to the next entry we will use
2013          * (wrapping if necessary) */
2014         tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2015                 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2016
2017         tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2018
2019         /* reduce TxBD free count */
2020         tx_queue->num_txbdfree -= (nr_frags + 1);
2021
2022         dev->trans_start = jiffies;
2023
2024         /* If the next BD still needs to be cleaned up, then the bds
2025            are full.  We need to tell the kernel to stop sending us stuff. */
2026         if (!tx_queue->num_txbdfree) {
2027                 netif_tx_stop_queue(txq);
2028
2029                 dev->stats.tx_fifo_errors++;
2030         }
2031
2032         /* Tell the DMA to go go go */
2033         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2034
2035         /* Unlock priv */
2036         spin_unlock_irqrestore(&tx_queue->txlock, flags);
2037
2038         return NETDEV_TX_OK;
2039 }
2040
2041 /* Stops the kernel queue, and halts the controller */
2042 static int gfar_close(struct net_device *dev)
2043 {
2044         struct gfar_private *priv = netdev_priv(dev);
2045
2046         disable_napi(priv);
2047
2048         skb_queue_purge(&priv->rx_recycle);
2049         cancel_work_sync(&priv->reset_task);
2050         stop_gfar(dev);
2051
2052         /* Disconnect from the PHY */
2053         phy_disconnect(priv->phydev);
2054         priv->phydev = NULL;
2055
2056         netif_tx_stop_all_queues(dev);
2057
2058         return 0;
2059 }
2060
2061 /* Changes the mac address if the controller is not running. */
2062 static int gfar_set_mac_address(struct net_device *dev)
2063 {
2064         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2065
2066         return 0;
2067 }
2068
2069
2070 /* Enables and disables VLAN insertion/extraction */
2071 static void gfar_vlan_rx_register(struct net_device *dev,
2072                 struct vlan_group *grp)
2073 {
2074         struct gfar_private *priv = netdev_priv(dev);
2075         struct gfar __iomem *regs = NULL;
2076         unsigned long flags;
2077         u32 tempval;
2078
2079         regs = priv->gfargrp[0].regs;
2080         local_irq_save(flags);
2081         lock_rx_qs(priv);
2082
2083         priv->vlgrp = grp;
2084
2085         if (grp) {
2086                 /* Enable VLAN tag insertion */
2087                 tempval = gfar_read(&regs->tctrl);
2088                 tempval |= TCTRL_VLINS;
2089
2090                 gfar_write(&regs->tctrl, tempval);
2091
2092                 /* Enable VLAN tag extraction */
2093                 tempval = gfar_read(&regs->rctrl);
2094                 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
2095                 gfar_write(&regs->rctrl, tempval);
2096         } else {
2097                 /* Disable VLAN tag insertion */
2098                 tempval = gfar_read(&regs->tctrl);
2099                 tempval &= ~TCTRL_VLINS;
2100                 gfar_write(&regs->tctrl, tempval);
2101
2102                 /* Disable VLAN tag extraction */
2103                 tempval = gfar_read(&regs->rctrl);
2104                 tempval &= ~RCTRL_VLEX;
2105                 /* If parse is no longer required, then disable parser */
2106                 if (tempval & RCTRL_REQ_PARSER)
2107                         tempval |= RCTRL_PRSDEP_INIT;
2108                 else
2109                         tempval &= ~RCTRL_PRSDEP_INIT;
2110                 gfar_write(&regs->rctrl, tempval);
2111         }
2112
2113         gfar_change_mtu(dev, dev->mtu);
2114
2115         unlock_rx_qs(priv);
2116         local_irq_restore(flags);
2117 }
2118
2119 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2120 {
2121         int tempsize, tempval;
2122         struct gfar_private *priv = netdev_priv(dev);
2123         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2124         int oldsize = priv->rx_buffer_size;
2125         int frame_size = new_mtu + ETH_HLEN;
2126
2127         if (priv->vlgrp)
2128                 frame_size += VLAN_HLEN;
2129
2130         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2131                 if (netif_msg_drv(priv))
2132                         printk(KERN_ERR "%s: Invalid MTU setting\n",
2133                                         dev->name);
2134                 return -EINVAL;
2135         }
2136
2137         if (gfar_uses_fcb(priv))
2138                 frame_size += GMAC_FCB_LEN;
2139
2140         frame_size += priv->padding;
2141
2142         tempsize =
2143             (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2144             INCREMENTAL_BUFFER_SIZE;
2145
2146         /* Only stop and start the controller if it isn't already
2147          * stopped, and we changed something */
2148         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2149                 stop_gfar(dev);
2150
2151         priv->rx_buffer_size = tempsize;
2152
2153         dev->mtu = new_mtu;
2154
2155         gfar_write(&regs->mrblr, priv->rx_buffer_size);
2156         gfar_write(&regs->maxfrm, priv->rx_buffer_size);
2157
2158         /* If the mtu is larger than the max size for standard
2159          * ethernet frames (ie, a jumbo frame), then set maccfg2
2160          * to allow huge frames, and to check the length */
2161         tempval = gfar_read(&regs->maccfg2);
2162
2163         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
2164                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2165         else
2166                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2167
2168         gfar_write(&regs->maccfg2, tempval);
2169
2170         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2171                 startup_gfar(dev);
2172
2173         return 0;
2174 }
2175
2176 /* gfar_reset_task gets scheduled when a packet has not been
2177  * transmitted after a set amount of time.
2178  * For now, assume that clearing out all the structures, and
2179  * starting over will fix the problem.
2180  */
2181 static void gfar_reset_task(struct work_struct *work)
2182 {
2183         struct gfar_private *priv = container_of(work, struct gfar_private,
2184                         reset_task);
2185         struct net_device *dev = priv->ndev;
2186
2187         if (dev->flags & IFF_UP) {
2188                 netif_tx_stop_all_queues(dev);
2189                 stop_gfar(dev);
2190                 startup_gfar(dev);
2191                 netif_tx_start_all_queues(dev);
2192         }
2193
2194         netif_tx_schedule_all(dev);
2195 }
2196
2197 static void gfar_timeout(struct net_device *dev)
2198 {
2199         struct gfar_private *priv = netdev_priv(dev);
2200
2201         dev->stats.tx_errors++;
2202         schedule_work(&priv->reset_task);
2203 }
2204
2205 /* Interrupt Handler for Transmit complete */
2206 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2207 {
2208         struct net_device *dev = tx_queue->dev;
2209         struct gfar_private *priv = netdev_priv(dev);
2210         struct gfar_priv_rx_q *rx_queue = NULL;
2211         struct txbd8 *bdp;
2212         struct txbd8 *lbdp = NULL;
2213         struct txbd8 *base = tx_queue->tx_bd_base;
2214         struct sk_buff *skb;
2215         int skb_dirtytx;
2216         int tx_ring_size = tx_queue->tx_ring_size;
2217         int frags = 0;
2218         int i;
2219         int howmany = 0;
2220         u32 lstatus;
2221
2222         rx_queue = priv->rx_queue[tx_queue->qindex];
2223         bdp = tx_queue->dirty_tx;
2224         skb_dirtytx = tx_queue->skb_dirtytx;
2225
2226         while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2227                 frags = skb_shinfo(skb)->nr_frags;
2228                 lbdp = skip_txbd(bdp, frags, base, tx_ring_size);
2229
2230                 lstatus = lbdp->lstatus;
2231
2232                 /* Only clean completed frames */
2233                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2234                                 (lstatus & BD_LENGTH_MASK))
2235                         break;
2236
2237                 dma_unmap_single(&priv->ofdev->dev,
2238                                 bdp->bufPtr,
2239                                 bdp->length,
2240                                 DMA_TO_DEVICE);
2241
2242                 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2243                 bdp = next_txbd(bdp, base, tx_ring_size);
2244
2245                 for (i = 0; i < frags; i++) {
2246                         dma_unmap_page(&priv->ofdev->dev,
2247                                         bdp->bufPtr,
2248                                         bdp->length,
2249                                         DMA_TO_DEVICE);
2250                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2251                         bdp = next_txbd(bdp, base, tx_ring_size);
2252                 }
2253
2254                 /*
2255                  * If there's room in the queue (limit it to rx_buffer_size)
2256                  * we add this skb back into the pool, if it's the right size
2257                  */
2258                 if (skb_queue_len(&priv->rx_recycle) < rx_queue->rx_ring_size &&
2259                                 skb_recycle_check(skb, priv->rx_buffer_size +
2260                                         RXBUF_ALIGNMENT))
2261                         __skb_queue_head(&priv->rx_recycle, skb);
2262                 else
2263                         dev_kfree_skb_any(skb);
2264
2265                 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2266
2267                 skb_dirtytx = (skb_dirtytx + 1) &
2268                         TX_RING_MOD_MASK(tx_ring_size);
2269
2270                 howmany++;
2271                 tx_queue->num_txbdfree += frags + 1;
2272         }
2273
2274         /* If we freed a buffer, we can restart transmission, if necessary */
2275         if (__netif_subqueue_stopped(dev, tx_queue->qindex) && tx_queue->num_txbdfree)
2276                 netif_wake_subqueue(dev, tx_queue->qindex);
2277
2278         /* Update dirty indicators */
2279         tx_queue->skb_dirtytx = skb_dirtytx;
2280         tx_queue->dirty_tx = bdp;
2281
2282         dev->stats.tx_packets += howmany;
2283
2284         return howmany;
2285 }
2286
2287 static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
2288 {
2289         unsigned long flags;
2290
2291         spin_lock_irqsave(&gfargrp->grplock, flags);
2292         if (napi_schedule_prep(&gfargrp->napi)) {
2293                 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
2294                 __napi_schedule(&gfargrp->napi);
2295         } else {
2296                 /*
2297                  * Clear IEVENT, so interrupts aren't called again
2298                  * because of the packets that have already arrived.
2299                  */
2300                 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2301         }
2302         spin_unlock_irqrestore(&gfargrp->grplock, flags);
2303
2304 }
2305
2306 /* Interrupt Handler for Transmit complete */
2307 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2308 {
2309         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2310         return IRQ_HANDLED;
2311 }
2312
2313 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
2314                 struct sk_buff *skb)
2315 {
2316         struct net_device *dev = rx_queue->dev;
2317         struct gfar_private *priv = netdev_priv(dev);
2318         dma_addr_t buf;
2319
2320         buf = dma_map_single(&priv->ofdev->dev, skb->data,
2321                              priv->rx_buffer_size, DMA_FROM_DEVICE);
2322         gfar_init_rxbdp(rx_queue, bdp, buf);
2323 }
2324
2325
2326 struct sk_buff * gfar_new_skb(struct net_device *dev)
2327 {
2328         unsigned int alignamount;
2329         struct gfar_private *priv = netdev_priv(dev);
2330         struct sk_buff *skb = NULL;
2331
2332         skb = __skb_dequeue(&priv->rx_recycle);
2333         if (!skb)
2334                 skb = netdev_alloc_skb(dev,
2335                                 priv->rx_buffer_size + RXBUF_ALIGNMENT);
2336
2337         if (!skb)
2338                 return NULL;
2339
2340         alignamount = RXBUF_ALIGNMENT -
2341                 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
2342
2343         /* We need the data buffer to be aligned properly.  We will reserve
2344          * as many bytes as needed to align the data properly
2345          */
2346         skb_reserve(skb, alignamount);
2347
2348         return skb;
2349 }
2350
2351 static inline void count_errors(unsigned short status, struct net_device *dev)
2352 {
2353         struct gfar_private *priv = netdev_priv(dev);
2354         struct net_device_stats *stats = &dev->stats;
2355         struct gfar_extra_stats *estats = &priv->extra_stats;
2356
2357         /* If the packet was truncated, none of the other errors
2358          * matter */
2359         if (status & RXBD_TRUNCATED) {
2360                 stats->rx_length_errors++;
2361
2362                 estats->rx_trunc++;
2363
2364                 return;
2365         }
2366         /* Count the errors, if there were any */
2367         if (status & (RXBD_LARGE | RXBD_SHORT)) {
2368                 stats->rx_length_errors++;
2369
2370                 if (status & RXBD_LARGE)
2371                         estats->rx_large++;
2372                 else
2373                         estats->rx_short++;
2374         }
2375         if (status & RXBD_NONOCTET) {
2376                 stats->rx_frame_errors++;
2377                 estats->rx_nonoctet++;
2378         }
2379         if (status & RXBD_CRCERR) {
2380                 estats->rx_crcerr++;
2381                 stats->rx_crc_errors++;
2382         }
2383         if (status & RXBD_OVERRUN) {
2384                 estats->rx_overrun++;
2385                 stats->rx_crc_errors++;
2386         }
2387 }
2388
2389 irqreturn_t gfar_receive(int irq, void *grp_id)
2390 {
2391         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2392         return IRQ_HANDLED;
2393 }
2394
2395 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2396 {
2397         /* If valid headers were found, and valid sums
2398          * were verified, then we tell the kernel that no
2399          * checksumming is necessary.  Otherwise, it is */
2400         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
2401                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2402         else
2403                 skb->ip_summed = CHECKSUM_NONE;
2404 }
2405
2406
2407 /* gfar_process_frame() -- handle one incoming packet if skb
2408  * isn't NULL.  */
2409 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2410                               int amount_pull)
2411 {
2412         struct gfar_private *priv = netdev_priv(dev);
2413         struct rxfcb *fcb = NULL;
2414
2415         int ret;
2416
2417         /* fcb is at the beginning if exists */
2418         fcb = (struct rxfcb *)skb->data;
2419
2420         /* Remove the FCB from the skb */
2421         skb_set_queue_mapping(skb, fcb->rq);
2422         /* Remove the padded bytes, if there are any */
2423         if (amount_pull)
2424                 skb_pull(skb, amount_pull);
2425
2426         if (priv->rx_csum_enable)
2427                 gfar_rx_checksum(skb, fcb);
2428
2429         /* Tell the skb what kind of packet this is */
2430         skb->protocol = eth_type_trans(skb, dev);
2431
2432         /* Send the packet up the stack */
2433         if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
2434                 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
2435         else
2436                 ret = netif_receive_skb(skb);
2437
2438         if (NET_RX_DROP == ret)
2439                 priv->extra_stats.kernel_dropped++;
2440
2441         return 0;
2442 }
2443
2444 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2445  *   until the budget/quota has been reached. Returns the number
2446  *   of frames handled
2447  */
2448 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2449 {
2450         struct net_device *dev = rx_queue->dev;
2451         struct rxbd8 *bdp, *base;
2452         struct sk_buff *skb;
2453         int pkt_len;
2454         int amount_pull;
2455         int howmany = 0;
2456         struct gfar_private *priv = netdev_priv(dev);
2457
2458         /* Get the first full descriptor */
2459         bdp = rx_queue->cur_rx;
2460         base = rx_queue->rx_bd_base;
2461
2462         amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0) +
2463                 priv->padding;
2464
2465         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
2466                 struct sk_buff *newskb;
2467                 rmb();
2468
2469                 /* Add another skb for the future */
2470                 newskb = gfar_new_skb(dev);
2471
2472                 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
2473
2474                 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2475                                 priv->rx_buffer_size, DMA_FROM_DEVICE);
2476
2477                 /* We drop the frame if we failed to allocate a new buffer */
2478                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2479                                  bdp->status & RXBD_ERR)) {
2480                         count_errors(bdp->status, dev);
2481
2482                         if (unlikely(!newskb))
2483                                 newskb = skb;
2484                         else if (skb) {
2485                                 /*
2486                                  * We need to reset ->data to what it
2487                                  * was before gfar_new_skb() re-aligned
2488                                  * it to an RXBUF_ALIGNMENT boundary
2489                                  * before we put the skb back on the
2490                                  * recycle list.
2491                                  */
2492                                 skb->data = skb->head + NET_SKB_PAD;
2493                                 __skb_queue_head(&priv->rx_recycle, skb);
2494                         }
2495                 } else {
2496                         /* Increment the number of packets */
2497                         dev->stats.rx_packets++;
2498                         howmany++;
2499
2500                         if (likely(skb)) {
2501                                 pkt_len = bdp->length - ETH_FCS_LEN;
2502                                 /* Remove the FCS from the packet length */
2503                                 skb_put(skb, pkt_len);
2504                                 dev->stats.rx_bytes += pkt_len;
2505
2506                                 if (in_irq() || irqs_disabled())
2507                                         printk("Interrupt problem!\n");
2508                                 gfar_process_frame(dev, skb, amount_pull);
2509
2510                         } else {
2511                                 if (netif_msg_rx_err(priv))
2512                                         printk(KERN_WARNING
2513                                                "%s: Missing skb!\n", dev->name);
2514                                 dev->stats.rx_dropped++;
2515                                 priv->extra_stats.rx_skbmissing++;
2516                         }
2517
2518                 }
2519
2520                 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
2521
2522                 /* Setup the new bdp */
2523                 gfar_new_rxbdp(rx_queue, bdp, newskb);
2524
2525                 /* Update to the next pointer */
2526                 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2527
2528                 /* update to point at the next skb */
2529                 rx_queue->skb_currx =
2530                     (rx_queue->skb_currx + 1) &
2531                     RX_RING_MOD_MASK(rx_queue->rx_ring_size);
2532         }
2533
2534         /* Update the current rxbd pointer to be the next one */
2535         rx_queue->cur_rx = bdp;
2536
2537         return howmany;
2538 }
2539
2540 static int gfar_poll(struct napi_struct *napi, int budget)
2541 {
2542         struct gfar_priv_grp *gfargrp = container_of(napi,
2543                         struct gfar_priv_grp, napi);
2544         struct gfar_private *priv = gfargrp->priv;
2545         struct gfar __iomem *regs = gfargrp->regs;
2546         struct gfar_priv_tx_q *tx_queue = NULL;
2547         struct gfar_priv_rx_q *rx_queue = NULL;
2548         int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;
2549         int tx_cleaned = 0, i, left_over_budget = budget, serviced_queues = 0;
2550         int num_queues = 0;
2551         unsigned long flags;
2552
2553         num_queues = gfargrp->num_rx_queues;
2554         budget_per_queue = budget/num_queues;
2555
2556         /* Clear IEVENT, so interrupts aren't called again
2557          * because of the packets that have already arrived */
2558         gfar_write(&regs->ievent, IEVENT_RTX_MASK);
2559
2560         while (num_queues && left_over_budget) {
2561
2562                 budget_per_queue = left_over_budget/num_queues;
2563                 left_over_budget = 0;
2564
2565                 for_each_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2566                         if (test_bit(i, &serviced_queues))
2567                                 continue;
2568                         rx_queue = priv->rx_queue[i];
2569                         tx_queue = priv->tx_queue[rx_queue->qindex];
2570
2571                         /* If we fail to get the lock,
2572                          * don't bother with the TX BDs */
2573                         if (spin_trylock_irqsave(&tx_queue->txlock, flags)) {
2574                                 tx_cleaned += gfar_clean_tx_ring(tx_queue);
2575                                 spin_unlock_irqrestore(&tx_queue->txlock,
2576                                                         flags);
2577                         }
2578
2579                         rx_cleaned_per_queue = gfar_clean_rx_ring(rx_queue,
2580                                                         budget_per_queue);
2581                         rx_cleaned += rx_cleaned_per_queue;
2582                         if(rx_cleaned_per_queue < budget_per_queue) {
2583                                 left_over_budget = left_over_budget +
2584                                         (budget_per_queue - rx_cleaned_per_queue);
2585                                 set_bit(i, &serviced_queues);
2586                                 num_queues--;
2587                         }
2588                 }
2589         }
2590
2591         if (tx_cleaned)
2592                 return budget;
2593
2594         if (rx_cleaned < budget) {
2595                 napi_complete(napi);
2596
2597                 /* Clear the halt bit in RSTAT */
2598                 gfar_write(&regs->rstat, gfargrp->rstat);
2599
2600                 gfar_write(&regs->imask, IMASK_DEFAULT);
2601
2602                 /* If we are coalescing interrupts, update the timer */
2603                 /* Otherwise, clear it */
2604                 gfar_configure_coalescing(priv,
2605                                 gfargrp->rx_bit_map, gfargrp->tx_bit_map);
2606         }
2607
2608         return rx_cleaned;
2609 }
2610
2611 #ifdef CONFIG_NET_POLL_CONTROLLER
2612 /*
2613  * Polling 'interrupt' - used by things like netconsole to send skbs
2614  * without having to re-enable interrupts. It's not called while
2615  * the interrupt routine is executing.
2616  */
2617 static void gfar_netpoll(struct net_device *dev)
2618 {
2619         struct gfar_private *priv = netdev_priv(dev);
2620         int i = 0;
2621
2622         /* If the device has multiple interrupts, run tx/rx */
2623         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2624                 for (i = 0; i < priv->num_grps; i++) {
2625                         disable_irq(priv->gfargrp[i].interruptTransmit);
2626                         disable_irq(priv->gfargrp[i].interruptReceive);
2627                         disable_irq(priv->gfargrp[i].interruptError);
2628                         gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2629                                                 &priv->gfargrp[i]);
2630                         enable_irq(priv->gfargrp[i].interruptError);
2631                         enable_irq(priv->gfargrp[i].interruptReceive);
2632                         enable_irq(priv->gfargrp[i].interruptTransmit);
2633                 }
2634         } else {
2635                 for (i = 0; i < priv->num_grps; i++) {
2636                         disable_irq(priv->gfargrp[i].interruptTransmit);
2637                         gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2638                                                 &priv->gfargrp[i]);
2639                         enable_irq(priv->gfargrp[i].interruptTransmit);
2640         }
2641 }
2642 #endif
2643
2644 /* The interrupt handler for devices with one interrupt */
2645 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
2646 {
2647         struct gfar_priv_grp *gfargrp = grp_id;
2648
2649         /* Save ievent for future reference */
2650         u32 events = gfar_read(&gfargrp->regs->ievent);
2651
2652         /* Check for reception */
2653         if (events & IEVENT_RX_MASK)
2654                 gfar_receive(irq, grp_id);
2655
2656         /* Check for transmit completion */
2657         if (events & IEVENT_TX_MASK)
2658                 gfar_transmit(irq, grp_id);
2659
2660         /* Check for errors */
2661         if (events & IEVENT_ERR_MASK)
2662                 gfar_error(irq, grp_id);
2663
2664         return IRQ_HANDLED;
2665 }
2666
2667 /* Called every time the controller might need to be made
2668  * aware of new link state.  The PHY code conveys this
2669  * information through variables in the phydev structure, and this
2670  * function converts those variables into the appropriate
2671  * register values, and can bring down the device if needed.
2672  */
2673 static void adjust_link(struct net_device *dev)
2674 {
2675         struct gfar_private *priv = netdev_priv(dev);
2676         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2677         unsigned long flags;
2678         struct phy_device *phydev = priv->phydev;
2679         int new_state = 0;
2680
2681         local_irq_save(flags);
2682         lock_tx_qs(priv);
2683
2684         if (phydev->link) {
2685                 u32 tempval = gfar_read(&regs->maccfg2);
2686                 u32 ecntrl = gfar_read(&regs->ecntrl);
2687
2688                 /* Now we make sure that we can be in full duplex mode.
2689                  * If not, we operate in half-duplex mode. */
2690                 if (phydev->duplex != priv->oldduplex) {
2691                         new_state = 1;
2692                         if (!(phydev->duplex))
2693                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
2694                         else
2695                                 tempval |= MACCFG2_FULL_DUPLEX;
2696
2697                         priv->oldduplex = phydev->duplex;
2698                 }
2699
2700                 if (phydev->speed != priv->oldspeed) {
2701                         new_state = 1;
2702                         switch (phydev->speed) {
2703                         case 1000:
2704                                 tempval =
2705                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2706
2707                                 ecntrl &= ~(ECNTRL_R100);
2708                                 break;
2709                         case 100:
2710                         case 10:
2711                                 tempval =
2712                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
2713
2714                                 /* Reduced mode distinguishes
2715                                  * between 10 and 100 */
2716                                 if (phydev->speed == SPEED_100)
2717                                         ecntrl |= ECNTRL_R100;
2718                                 else
2719                                         ecntrl &= ~(ECNTRL_R100);
2720                                 break;
2721                         default:
2722                                 if (netif_msg_link(priv))
2723                                         printk(KERN_WARNING
2724                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!\n",
2725                                                 dev->name, phydev->speed);
2726                                 break;
2727                         }
2728
2729                         priv->oldspeed = phydev->speed;
2730                 }
2731
2732                 gfar_write(&regs->maccfg2, tempval);
2733                 gfar_write(&regs->ecntrl, ecntrl);
2734
2735                 if (!priv->oldlink) {
2736                         new_state = 1;
2737                         priv->oldlink = 1;
2738                 }
2739         } else if (priv->oldlink) {
2740                 new_state = 1;
2741                 priv->oldlink = 0;
2742                 priv->oldspeed = 0;
2743                 priv->oldduplex = -1;
2744         }
2745
2746         if (new_state && netif_msg_link(priv))
2747                 phy_print_status(phydev);
2748         unlock_tx_qs(priv);
2749         local_irq_restore(flags);
2750 }
2751
2752 /* Update the hash table based on the current list of multicast
2753  * addresses we subscribe to.  Also, change the promiscuity of
2754  * the device based on the flags (this function is called
2755  * whenever dev->flags is changed */
2756 static void gfar_set_multi(struct net_device *dev)
2757 {
2758         struct dev_mc_list *mc_ptr;
2759         struct gfar_private *priv = netdev_priv(dev);
2760         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2761         u32 tempval;
2762
2763         if (dev->flags & IFF_PROMISC) {
2764                 /* Set RCTRL to PROM */
2765                 tempval = gfar_read(&regs->rctrl);
2766                 tempval |= RCTRL_PROM;
2767                 gfar_write(&regs->rctrl, tempval);
2768         } else {
2769                 /* Set RCTRL to not PROM */
2770                 tempval = gfar_read(&regs->rctrl);
2771                 tempval &= ~(RCTRL_PROM);
2772                 gfar_write(&regs->rctrl, tempval);
2773         }
2774
2775         if (dev->flags & IFF_ALLMULTI) {
2776                 /* Set the hash to rx all multicast frames */
2777                 gfar_write(&regs->igaddr0, 0xffffffff);
2778                 gfar_write(&regs->igaddr1, 0xffffffff);
2779                 gfar_write(&regs->igaddr2, 0xffffffff);
2780                 gfar_write(&regs->igaddr3, 0xffffffff);
2781                 gfar_write(&regs->igaddr4, 0xffffffff);
2782                 gfar_write(&regs->igaddr5, 0xffffffff);
2783                 gfar_write(&regs->igaddr6, 0xffffffff);
2784                 gfar_write(&regs->igaddr7, 0xffffffff);
2785                 gfar_write(&regs->gaddr0, 0xffffffff);
2786                 gfar_write(&regs->gaddr1, 0xffffffff);
2787                 gfar_write(&regs->gaddr2, 0xffffffff);
2788                 gfar_write(&regs->gaddr3, 0xffffffff);
2789                 gfar_write(&regs->gaddr4, 0xffffffff);
2790                 gfar_write(&regs->gaddr5, 0xffffffff);
2791                 gfar_write(&regs->gaddr6, 0xffffffff);
2792                 gfar_write(&regs->gaddr7, 0xffffffff);
2793         } else {
2794                 int em_num;
2795                 int idx;
2796
2797                 /* zero out the hash */
2798                 gfar_write(&regs->igaddr0, 0x0);
2799                 gfar_write(&regs->igaddr1, 0x0);
2800                 gfar_write(&regs->igaddr2, 0x0);
2801                 gfar_write(&regs->igaddr3, 0x0);
2802                 gfar_write(&regs->igaddr4, 0x0);
2803                 gfar_write(&regs->igaddr5, 0x0);
2804                 gfar_write(&regs->igaddr6, 0x0);
2805                 gfar_write(&regs->igaddr7, 0x0);
2806                 gfar_write(&regs->gaddr0, 0x0);
2807                 gfar_write(&regs->gaddr1, 0x0);
2808                 gfar_write(&regs->gaddr2, 0x0);
2809                 gfar_write(&regs->gaddr3, 0x0);
2810                 gfar_write(&regs->gaddr4, 0x0);
2811                 gfar_write(&regs->gaddr5, 0x0);
2812                 gfar_write(&regs->gaddr6, 0x0);
2813                 gfar_write(&regs->gaddr7, 0x0);
2814
2815                 /* If we have extended hash tables, we need to
2816                  * clear the exact match registers to prepare for
2817                  * setting them */
2818                 if (priv->extended_hash) {
2819                         em_num = GFAR_EM_NUM + 1;
2820                         gfar_clear_exact_match(dev);
2821                         idx = 1;
2822                 } else {
2823                         idx = 0;
2824                         em_num = 0;
2825                 }
2826
2827                 if (dev->mc_count == 0)
2828                         return;
2829
2830                 /* Parse the list, and set the appropriate bits */
2831                 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
2832                         if (idx < em_num) {
2833                                 gfar_set_mac_for_addr(dev, idx,
2834                                                 mc_ptr->dmi_addr);
2835                                 idx++;
2836                         } else
2837                                 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
2838                 }
2839         }
2840
2841         return;
2842 }
2843
2844
2845 /* Clears each of the exact match registers to zero, so they
2846  * don't interfere with normal reception */
2847 static void gfar_clear_exact_match(struct net_device *dev)
2848 {
2849         int idx;
2850         u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
2851
2852         for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
2853                 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
2854 }
2855
2856 /* Set the appropriate hash bit for the given addr */
2857 /* The algorithm works like so:
2858  * 1) Take the Destination Address (ie the multicast address), and
2859  * do a CRC on it (little endian), and reverse the bits of the
2860  * result.
2861  * 2) Use the 8 most significant bits as a hash into a 256-entry
2862  * table.  The table is controlled through 8 32-bit registers:
2863  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
2864  * gaddr7.  This means that the 3 most significant bits in the
2865  * hash index which gaddr register to use, and the 5 other bits
2866  * indicate which bit (assuming an IBM numbering scheme, which
2867  * for PowerPC (tm) is usually the case) in the register holds
2868  * the entry. */
2869 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
2870 {
2871         u32 tempval;
2872         struct gfar_private *priv = netdev_priv(dev);
2873         u32 result = ether_crc(MAC_ADDR_LEN, addr);
2874         int width = priv->hash_width;
2875         u8 whichbit = (result >> (32 - width)) & 0x1f;
2876         u8 whichreg = result >> (32 - width + 5);
2877         u32 value = (1 << (31-whichbit));
2878
2879         tempval = gfar_read(priv->hash_regs[whichreg]);
2880         tempval |= value;
2881         gfar_write(priv->hash_regs[whichreg], tempval);
2882
2883         return;
2884 }
2885
2886
2887 /* There are multiple MAC Address register pairs on some controllers
2888  * This function sets the numth pair to a given address
2889  */
2890 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
2891 {
2892         struct gfar_private *priv = netdev_priv(dev);
2893         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2894         int idx;
2895         char tmpbuf[MAC_ADDR_LEN];
2896         u32 tempval;
2897         u32 __iomem *macptr = &regs->macstnaddr1;
2898
2899         macptr += num*2;
2900
2901         /* Now copy it into the mac registers backwards, cuz */
2902         /* little endian is silly */
2903         for (idx = 0; idx < MAC_ADDR_LEN; idx++)
2904                 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
2905
2906         gfar_write(macptr, *((u32 *) (tmpbuf)));
2907
2908         tempval = *((u32 *) (tmpbuf + 4));
2909
2910         gfar_write(macptr+1, tempval);
2911 }
2912
2913 /* GFAR error interrupt handler */
2914 static irqreturn_t gfar_error(int irq, void *grp_id)
2915 {
2916         struct gfar_priv_grp *gfargrp = grp_id;
2917         struct gfar __iomem *regs = gfargrp->regs;
2918         struct gfar_private *priv= gfargrp->priv;
2919         struct net_device *dev = priv->ndev;
2920
2921         /* Save ievent for future reference */
2922         u32 events = gfar_read(&regs->ievent);
2923
2924         /* Clear IEVENT */
2925         gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
2926
2927         /* Magic Packet is not an error. */
2928         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2929             (events & IEVENT_MAG))
2930                 events &= ~IEVENT_MAG;
2931
2932         /* Hmm... */
2933         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2934                 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2935                        dev->name, events, gfar_read(&regs->imask));
2936
2937         /* Update the error counters */
2938         if (events & IEVENT_TXE) {
2939                 dev->stats.tx_errors++;
2940
2941                 if (events & IEVENT_LC)
2942                         dev->stats.tx_window_errors++;
2943                 if (events & IEVENT_CRL)
2944                         dev->stats.tx_aborted_errors++;
2945                 if (events & IEVENT_XFUN) {
2946                         if (netif_msg_tx_err(priv))
2947                                 printk(KERN_DEBUG "%s: TX FIFO underrun, "
2948                                        "packet dropped.\n", dev->name);
2949                         dev->stats.tx_dropped++;
2950                         priv->extra_stats.tx_underrun++;
2951
2952                         /* Reactivate the Tx Queues */
2953                         gfar_write(&regs->tstat, gfargrp->tstat);
2954                 }
2955                 if (netif_msg_tx_err(priv))
2956                         printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
2957         }
2958         if (events & IEVENT_BSY) {
2959                 dev->stats.rx_errors++;
2960                 priv->extra_stats.rx_bsy++;
2961
2962                 gfar_receive(irq, grp_id);
2963
2964                 if (netif_msg_rx_err(priv))
2965                         printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
2966                                dev->name, gfar_read(&regs->rstat));
2967         }
2968         if (events & IEVENT_BABR) {
2969                 dev->stats.rx_errors++;
2970                 priv->extra_stats.rx_babr++;
2971
2972                 if (netif_msg_rx_err(priv))
2973                         printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
2974         }
2975         if (events & IEVENT_EBERR) {
2976                 priv->extra_stats.eberr++;
2977                 if (netif_msg_rx_err(priv))
2978                         printk(KERN_DEBUG "%s: bus error\n", dev->name);
2979         }
2980         if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
2981                 printk(KERN_DEBUG "%s: control frame\n", dev->name);
2982
2983         if (events & IEVENT_BABT) {
2984                 priv->extra_stats.tx_babt++;
2985                 if (netif_msg_tx_err(priv))
2986                         printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
2987         }
2988         return IRQ_HANDLED;
2989 }
2990
2991 static struct of_device_id gfar_match[] =
2992 {
2993         {
2994                 .type = "network",
2995                 .compatible = "gianfar",
2996         },
2997         {
2998                 .compatible = "fsl,etsec2",
2999         },
3000         {},
3001 };
3002 MODULE_DEVICE_TABLE(of, gfar_match);
3003
3004 /* Structure for a device driver */
3005 static struct of_platform_driver gfar_driver = {
3006         .name = "fsl-gianfar",
3007         .match_table = gfar_match,
3008
3009         .probe = gfar_probe,
3010         .remove = gfar_remove,
3011         .suspend = gfar_legacy_suspend,
3012         .resume = gfar_legacy_resume,
3013         .driver.pm = GFAR_PM_OPS,
3014 };
3015
3016 static int __init gfar_init(void)
3017 {
3018         return of_register_platform_driver(&gfar_driver);
3019 }
3020
3021 static void __exit gfar_exit(void)
3022 {
3023         of_unregister_platform_driver(&gfar_driver);
3024 }
3025
3026 module_init(gfar_init);
3027 module_exit(gfar_exit);
3028