2 * drivers/net/gianfar.c
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
10 * Maintainer: Kumar Gala
12 * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
13 * Copyright (c) 2007 MontaVista Software, Inc.
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * Gianfar: AKA Lambda Draconis, "Dragon"
28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
35 * last descriptor of the ring.
37 * When a packet is received, the RXF bit in the
38 * IEVENT register is set, triggering an interrupt when the
39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
42 * of frames or amount of time have passed). In NAPI, the
43 * interrupt handler will signal there is work to be done, and
44 * exit. This method will start at the last known empty
45 * descriptor, and process every subsequent descriptor until there
46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
64 #include <linux/kernel.h>
65 #include <linux/string.h>
66 #include <linux/errno.h>
67 #include <linux/unistd.h>
68 #include <linux/slab.h>
69 #include <linux/interrupt.h>
70 #include <linux/init.h>
71 #include <linux/delay.h>
72 #include <linux/netdevice.h>
73 #include <linux/etherdevice.h>
74 #include <linux/skbuff.h>
75 #include <linux/if_vlan.h>
76 #include <linux/spinlock.h>
78 #include <linux/of_platform.h>
80 #include <linux/tcp.h>
81 #include <linux/udp.h>
86 #include <asm/uaccess.h>
87 #include <linux/module.h>
88 #include <linux/dma-mapping.h>
89 #include <linux/crc32.h>
90 #include <linux/mii.h>
91 #include <linux/phy.h>
92 #include <linux/phy_fixed.h>
96 #include "gianfar_mii.h"
98 #define TX_TIMEOUT (1*HZ)
99 #undef BRIEF_GFAR_ERRORS
100 #undef VERBOSE_GFAR_ERRORS
102 const char gfar_driver_name[] = "Gianfar Ethernet";
103 const char gfar_driver_version[] = "1.3";
105 static int gfar_enet_open(struct net_device *dev);
106 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
107 static void gfar_reset_task(struct work_struct *work);
108 static void gfar_timeout(struct net_device *dev);
109 static int gfar_close(struct net_device *dev);
110 struct sk_buff *gfar_new_skb(struct net_device *dev);
111 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
112 struct sk_buff *skb);
113 static int gfar_set_mac_address(struct net_device *dev);
114 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
115 static irqreturn_t gfar_error(int irq, void *dev_id);
116 static irqreturn_t gfar_transmit(int irq, void *dev_id);
117 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
118 static void adjust_link(struct net_device *dev);
119 static void init_registers(struct net_device *dev);
120 static int init_phy(struct net_device *dev);
121 static int gfar_probe(struct of_device *ofdev,
122 const struct of_device_id *match);
123 static int gfar_remove(struct of_device *ofdev);
124 static void free_skb_resources(struct gfar_private *priv);
125 static void gfar_set_multi(struct net_device *dev);
126 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
127 static void gfar_configure_serdes(struct net_device *dev);
128 static int gfar_poll(struct napi_struct *napi, int budget);
129 #ifdef CONFIG_NET_POLL_CONTROLLER
130 static void gfar_netpoll(struct net_device *dev);
132 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
133 static int gfar_clean_tx_ring(struct net_device *dev);
134 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
136 static void gfar_vlan_rx_register(struct net_device *netdev,
137 struct vlan_group *grp);
138 void gfar_halt(struct net_device *dev);
139 static void gfar_halt_nodisable(struct net_device *dev);
140 void gfar_start(struct net_device *dev);
141 static void gfar_clear_exact_match(struct net_device *dev);
142 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
144 extern const struct ethtool_ops gfar_ethtool_ops;
146 MODULE_AUTHOR("Freescale Semiconductor, Inc");
147 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
148 MODULE_LICENSE("GPL");
150 /* Returns 1 if incoming frames use an FCB */
151 static inline int gfar_uses_fcb(struct gfar_private *priv)
153 return priv->vlgrp || priv->rx_csum_enable;
156 static int gfar_of_init(struct net_device *dev)
158 struct device_node *phy, *mdio;
159 const unsigned int *id;
162 const void *mac_addr;
166 struct gfar_private *priv = netdev_priv(dev);
167 struct device_node *np = priv->node;
168 char bus_name[MII_BUS_ID_SIZE];
170 if (!np || !of_device_is_available(np))
173 /* get a pointer to the register memory */
174 addr = of_translate_address(np, of_get_address(np, 0, &size, NULL));
175 priv->regs = ioremap(addr, size);
177 if (priv->regs == NULL)
180 priv->interruptTransmit = irq_of_parse_and_map(np, 0);
182 model = of_get_property(np, "model", NULL);
184 /* If we aren't the FEC we have multiple interrupts */
185 if (model && strcasecmp(model, "FEC")) {
186 priv->interruptReceive = irq_of_parse_and_map(np, 1);
188 priv->interruptError = irq_of_parse_and_map(np, 2);
190 if (priv->interruptTransmit < 0 ||
191 priv->interruptReceive < 0 ||
192 priv->interruptError < 0) {
198 mac_addr = of_get_mac_address(np);
200 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
202 if (model && !strcasecmp(model, "TSEC"))
204 FSL_GIANFAR_DEV_HAS_GIGABIT |
205 FSL_GIANFAR_DEV_HAS_COALESCE |
206 FSL_GIANFAR_DEV_HAS_RMON |
207 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
208 if (model && !strcasecmp(model, "eTSEC"))
210 FSL_GIANFAR_DEV_HAS_GIGABIT |
211 FSL_GIANFAR_DEV_HAS_COALESCE |
212 FSL_GIANFAR_DEV_HAS_RMON |
213 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
214 FSL_GIANFAR_DEV_HAS_PADDING |
215 FSL_GIANFAR_DEV_HAS_CSUM |
216 FSL_GIANFAR_DEV_HAS_VLAN |
217 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
218 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH;
220 ctype = of_get_property(np, "phy-connection-type", NULL);
222 /* We only care about rgmii-id. The rest are autodetected */
223 if (ctype && !strcmp(ctype, "rgmii-id"))
224 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
226 priv->interface = PHY_INTERFACE_MODE_MII;
228 if (of_get_property(np, "fsl,magic-packet", NULL))
229 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
231 ph = of_get_property(np, "phy-handle", NULL);
235 fixed_link = (u32 *)of_get_property(np, "fixed-link", NULL);
241 snprintf(priv->phy_bus_id, BUS_ID_SIZE, PHY_ID_FMT, "0",
244 phy = of_find_node_by_phandle(*ph);
251 mdio = of_get_parent(phy);
253 id = of_get_property(phy, "reg", NULL);
258 gfar_mdio_bus_name(bus_name, mdio);
259 snprintf(priv->phy_bus_id, BUS_ID_SIZE, "%s:%02x",
263 /* Find the TBI PHY. If it's not there, we don't support SGMII */
264 ph = of_get_property(np, "tbi-handle", NULL);
266 struct device_node *tbi = of_find_node_by_phandle(*ph);
267 struct of_device *ofdev;
273 mdio = of_get_parent(tbi);
277 ofdev = of_find_device_by_node(mdio);
281 id = of_get_property(tbi, "reg", NULL);
287 bus = dev_get_drvdata(&ofdev->dev);
289 priv->tbiphy = bus->phy_map[*id];
299 /* Set up the ethernet device structure, private data,
300 * and anything else we need before we start */
301 static int gfar_probe(struct of_device *ofdev,
302 const struct of_device_id *match)
305 struct net_device *dev = NULL;
306 struct gfar_private *priv = NULL;
308 DECLARE_MAC_BUF(mac);
310 /* Create an ethernet device instance */
311 dev = alloc_etherdev(sizeof (*priv));
316 priv = netdev_priv(dev);
318 priv->node = ofdev->node;
320 err = gfar_of_init(dev);
325 spin_lock_init(&priv->txlock);
326 spin_lock_init(&priv->rxlock);
327 spin_lock_init(&priv->bflock);
328 INIT_WORK(&priv->reset_task, gfar_reset_task);
330 dev_set_drvdata(&ofdev->dev, priv);
332 /* Stop the DMA engine now, in case it was running before */
333 /* (The firmware could have used it, and left it running). */
336 /* Reset MAC layer */
337 gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
339 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
340 gfar_write(&priv->regs->maccfg1, tempval);
342 /* Initialize MACCFG2. */
343 gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
345 /* Initialize ECNTRL */
346 gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
348 /* Set the dev->base_addr to the gfar reg region */
349 dev->base_addr = (unsigned long) (priv->regs);
351 SET_NETDEV_DEV(dev, &ofdev->dev);
353 /* Fill in the dev structure */
354 dev->open = gfar_enet_open;
355 dev->hard_start_xmit = gfar_start_xmit;
356 dev->tx_timeout = gfar_timeout;
357 dev->watchdog_timeo = TX_TIMEOUT;
358 netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT);
359 #ifdef CONFIG_NET_POLL_CONTROLLER
360 dev->poll_controller = gfar_netpoll;
362 dev->stop = gfar_close;
363 dev->change_mtu = gfar_change_mtu;
365 dev->set_multicast_list = gfar_set_multi;
367 dev->ethtool_ops = &gfar_ethtool_ops;
369 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
370 priv->rx_csum_enable = 1;
371 dev->features |= NETIF_F_IP_CSUM;
373 priv->rx_csum_enable = 0;
377 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
378 dev->vlan_rx_register = gfar_vlan_rx_register;
380 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
383 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
384 priv->extended_hash = 1;
385 priv->hash_width = 9;
387 priv->hash_regs[0] = &priv->regs->igaddr0;
388 priv->hash_regs[1] = &priv->regs->igaddr1;
389 priv->hash_regs[2] = &priv->regs->igaddr2;
390 priv->hash_regs[3] = &priv->regs->igaddr3;
391 priv->hash_regs[4] = &priv->regs->igaddr4;
392 priv->hash_regs[5] = &priv->regs->igaddr5;
393 priv->hash_regs[6] = &priv->regs->igaddr6;
394 priv->hash_regs[7] = &priv->regs->igaddr7;
395 priv->hash_regs[8] = &priv->regs->gaddr0;
396 priv->hash_regs[9] = &priv->regs->gaddr1;
397 priv->hash_regs[10] = &priv->regs->gaddr2;
398 priv->hash_regs[11] = &priv->regs->gaddr3;
399 priv->hash_regs[12] = &priv->regs->gaddr4;
400 priv->hash_regs[13] = &priv->regs->gaddr5;
401 priv->hash_regs[14] = &priv->regs->gaddr6;
402 priv->hash_regs[15] = &priv->regs->gaddr7;
405 priv->extended_hash = 0;
406 priv->hash_width = 8;
408 priv->hash_regs[0] = &priv->regs->gaddr0;
409 priv->hash_regs[1] = &priv->regs->gaddr1;
410 priv->hash_regs[2] = &priv->regs->gaddr2;
411 priv->hash_regs[3] = &priv->regs->gaddr3;
412 priv->hash_regs[4] = &priv->regs->gaddr4;
413 priv->hash_regs[5] = &priv->regs->gaddr5;
414 priv->hash_regs[6] = &priv->regs->gaddr6;
415 priv->hash_regs[7] = &priv->regs->gaddr7;
418 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
419 priv->padding = DEFAULT_PADDING;
423 if (dev->features & NETIF_F_IP_CSUM)
424 dev->hard_header_len += GMAC_FCB_LEN;
426 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
427 priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
428 priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
430 priv->txcoalescing = DEFAULT_TX_COALESCE;
431 priv->txic = DEFAULT_TXIC;
432 priv->rxcoalescing = DEFAULT_RX_COALESCE;
433 priv->rxic = DEFAULT_RXIC;
435 /* Enable most messages by default */
436 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
438 /* Carrier starts down, phylib will bring it up */
439 netif_carrier_off(dev);
441 err = register_netdev(dev);
444 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
449 /* Create all the sysfs files */
450 gfar_init_sysfs(dev);
452 /* Print out the device info */
453 printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
455 /* Even more device info helps when determining which kernel */
456 /* provided which set of benchmarks. */
457 printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
458 printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
459 dev->name, priv->rx_ring_size, priv->tx_ring_size);
470 static int gfar_remove(struct of_device *ofdev)
472 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
474 dev_set_drvdata(&ofdev->dev, NULL);
477 free_netdev(priv->dev);
483 static int gfar_suspend(struct of_device *ofdev, pm_message_t state)
485 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
486 struct net_device *dev = priv->dev;
490 int magic_packet = priv->wol_en &&
491 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
493 netif_device_detach(dev);
495 if (netif_running(dev)) {
496 spin_lock_irqsave(&priv->txlock, flags);
497 spin_lock(&priv->rxlock);
499 gfar_halt_nodisable(dev);
501 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
502 tempval = gfar_read(&priv->regs->maccfg1);
504 tempval &= ~MACCFG1_TX_EN;
507 tempval &= ~MACCFG1_RX_EN;
509 gfar_write(&priv->regs->maccfg1, tempval);
511 spin_unlock(&priv->rxlock);
512 spin_unlock_irqrestore(&priv->txlock, flags);
514 napi_disable(&priv->napi);
517 /* Enable interrupt on Magic Packet */
518 gfar_write(&priv->regs->imask, IMASK_MAG);
520 /* Enable Magic Packet mode */
521 tempval = gfar_read(&priv->regs->maccfg2);
522 tempval |= MACCFG2_MPEN;
523 gfar_write(&priv->regs->maccfg2, tempval);
525 phy_stop(priv->phydev);
532 static int gfar_resume(struct of_device *ofdev)
534 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
535 struct net_device *dev = priv->dev;
538 int magic_packet = priv->wol_en &&
539 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
541 if (!netif_running(dev)) {
542 netif_device_attach(dev);
546 if (!magic_packet && priv->phydev)
547 phy_start(priv->phydev);
549 /* Disable Magic Packet mode, in case something
553 spin_lock_irqsave(&priv->txlock, flags);
554 spin_lock(&priv->rxlock);
556 tempval = gfar_read(&priv->regs->maccfg2);
557 tempval &= ~MACCFG2_MPEN;
558 gfar_write(&priv->regs->maccfg2, tempval);
562 spin_unlock(&priv->rxlock);
563 spin_unlock_irqrestore(&priv->txlock, flags);
565 netif_device_attach(dev);
567 napi_enable(&priv->napi);
572 #define gfar_suspend NULL
573 #define gfar_resume NULL
576 /* Reads the controller's registers to determine what interface
577 * connects it to the PHY.
579 static phy_interface_t gfar_get_interface(struct net_device *dev)
581 struct gfar_private *priv = netdev_priv(dev);
582 u32 ecntrl = gfar_read(&priv->regs->ecntrl);
584 if (ecntrl & ECNTRL_SGMII_MODE)
585 return PHY_INTERFACE_MODE_SGMII;
587 if (ecntrl & ECNTRL_TBI_MODE) {
588 if (ecntrl & ECNTRL_REDUCED_MODE)
589 return PHY_INTERFACE_MODE_RTBI;
591 return PHY_INTERFACE_MODE_TBI;
594 if (ecntrl & ECNTRL_REDUCED_MODE) {
595 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
596 return PHY_INTERFACE_MODE_RMII;
598 phy_interface_t interface = priv->interface;
601 * This isn't autodetected right now, so it must
602 * be set by the device tree or platform code.
604 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
605 return PHY_INTERFACE_MODE_RGMII_ID;
607 return PHY_INTERFACE_MODE_RGMII;
611 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
612 return PHY_INTERFACE_MODE_GMII;
614 return PHY_INTERFACE_MODE_MII;
618 /* Initializes driver's PHY state, and attaches to the PHY.
619 * Returns 0 on success.
621 static int init_phy(struct net_device *dev)
623 struct gfar_private *priv = netdev_priv(dev);
624 uint gigabit_support =
625 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
626 SUPPORTED_1000baseT_Full : 0;
627 struct phy_device *phydev;
628 phy_interface_t interface;
632 priv->oldduplex = -1;
634 interface = gfar_get_interface(dev);
636 phydev = phy_connect(dev, priv->phy_bus_id, &adjust_link, 0, interface);
638 if (interface == PHY_INTERFACE_MODE_SGMII)
639 gfar_configure_serdes(dev);
641 if (IS_ERR(phydev)) {
642 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
643 return PTR_ERR(phydev);
646 /* Remove any features not supported by the controller */
647 phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
648 phydev->advertising = phydev->supported;
650 priv->phydev = phydev;
656 * Initialize TBI PHY interface for communicating with the
657 * SERDES lynx PHY on the chip. We communicate with this PHY
658 * through the MDIO bus on each controller, treating it as a
659 * "normal" PHY at the address found in the TBIPA register. We assume
660 * that the TBIPA register is valid. Either the MDIO bus code will set
661 * it to a value that doesn't conflict with other PHYs on the bus, or the
662 * value doesn't matter, as there are no other PHYs on the bus.
664 static void gfar_configure_serdes(struct net_device *dev)
666 struct gfar_private *priv = netdev_priv(dev);
669 printk(KERN_WARNING "SGMII mode requires that the device "
670 "tree specify a tbi-handle\n");
675 * If the link is already up, we must already be ok, and don't need to
676 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
677 * everything for us? Resetting it takes the link down and requires
678 * several seconds for it to come back.
680 if (phy_read(priv->tbiphy, MII_BMSR) & BMSR_LSTATUS)
683 /* Single clk mode, mii mode off(for serdes communication) */
684 phy_write(priv->tbiphy, MII_TBICON, TBICON_CLK_SELECT);
686 phy_write(priv->tbiphy, MII_ADVERTISE,
687 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
688 ADVERTISE_1000XPSE_ASYM);
690 phy_write(priv->tbiphy, MII_BMCR, BMCR_ANENABLE |
691 BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
694 static void init_registers(struct net_device *dev)
696 struct gfar_private *priv = netdev_priv(dev);
699 gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
701 /* Initialize IMASK */
702 gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
704 /* Init hash registers to zero */
705 gfar_write(&priv->regs->igaddr0, 0);
706 gfar_write(&priv->regs->igaddr1, 0);
707 gfar_write(&priv->regs->igaddr2, 0);
708 gfar_write(&priv->regs->igaddr3, 0);
709 gfar_write(&priv->regs->igaddr4, 0);
710 gfar_write(&priv->regs->igaddr5, 0);
711 gfar_write(&priv->regs->igaddr6, 0);
712 gfar_write(&priv->regs->igaddr7, 0);
714 gfar_write(&priv->regs->gaddr0, 0);
715 gfar_write(&priv->regs->gaddr1, 0);
716 gfar_write(&priv->regs->gaddr2, 0);
717 gfar_write(&priv->regs->gaddr3, 0);
718 gfar_write(&priv->regs->gaddr4, 0);
719 gfar_write(&priv->regs->gaddr5, 0);
720 gfar_write(&priv->regs->gaddr6, 0);
721 gfar_write(&priv->regs->gaddr7, 0);
723 /* Zero out the rmon mib registers if it has them */
724 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
725 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
727 /* Mask off the CAM interrupts */
728 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
729 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
732 /* Initialize the max receive buffer length */
733 gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
735 /* Initialize the Minimum Frame Length Register */
736 gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
740 /* Halt the receive and transmit queues */
741 static void gfar_halt_nodisable(struct net_device *dev)
743 struct gfar_private *priv = netdev_priv(dev);
744 struct gfar __iomem *regs = priv->regs;
747 /* Mask all interrupts */
748 gfar_write(®s->imask, IMASK_INIT_CLEAR);
750 /* Clear all interrupts */
751 gfar_write(®s->ievent, IEVENT_INIT_CLEAR);
753 /* Stop the DMA, and wait for it to stop */
754 tempval = gfar_read(&priv->regs->dmactrl);
755 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
756 != (DMACTRL_GRS | DMACTRL_GTS)) {
757 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
758 gfar_write(&priv->regs->dmactrl, tempval);
760 while (!(gfar_read(&priv->regs->ievent) &
761 (IEVENT_GRSC | IEVENT_GTSC)))
766 /* Halt the receive and transmit queues */
767 void gfar_halt(struct net_device *dev)
769 struct gfar_private *priv = netdev_priv(dev);
770 struct gfar __iomem *regs = priv->regs;
773 gfar_halt_nodisable(dev);
775 /* Disable Rx and Tx */
776 tempval = gfar_read(®s->maccfg1);
777 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
778 gfar_write(®s->maccfg1, tempval);
781 void stop_gfar(struct net_device *dev)
783 struct gfar_private *priv = netdev_priv(dev);
784 struct gfar __iomem *regs = priv->regs;
787 phy_stop(priv->phydev);
790 spin_lock_irqsave(&priv->txlock, flags);
791 spin_lock(&priv->rxlock);
795 spin_unlock(&priv->rxlock);
796 spin_unlock_irqrestore(&priv->txlock, flags);
799 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
800 free_irq(priv->interruptError, dev);
801 free_irq(priv->interruptTransmit, dev);
802 free_irq(priv->interruptReceive, dev);
804 free_irq(priv->interruptTransmit, dev);
807 free_skb_resources(priv);
809 dma_free_coherent(&dev->dev,
810 sizeof(struct txbd8)*priv->tx_ring_size
811 + sizeof(struct rxbd8)*priv->rx_ring_size,
813 gfar_read(®s->tbase0));
816 /* If there are any tx skbs or rx skbs still around, free them.
817 * Then free tx_skbuff and rx_skbuff */
818 static void free_skb_resources(struct gfar_private *priv)
824 /* Go through all the buffer descriptors and free their data buffers */
825 txbdp = priv->tx_bd_base;
827 for (i = 0; i < priv->tx_ring_size; i++) {
829 if (priv->tx_skbuff[i]) {
830 dma_unmap_single(&priv->dev->dev, txbdp->bufPtr,
833 dev_kfree_skb_any(priv->tx_skbuff[i]);
834 priv->tx_skbuff[i] = NULL;
840 kfree(priv->tx_skbuff);
842 rxbdp = priv->rx_bd_base;
844 /* rx_skbuff is not guaranteed to be allocated, so only
845 * free it and its contents if it is allocated */
846 if(priv->rx_skbuff != NULL) {
847 for (i = 0; i < priv->rx_ring_size; i++) {
848 if (priv->rx_skbuff[i]) {
849 dma_unmap_single(&priv->dev->dev, rxbdp->bufPtr,
850 priv->rx_buffer_size,
853 dev_kfree_skb_any(priv->rx_skbuff[i]);
854 priv->rx_skbuff[i] = NULL;
864 kfree(priv->rx_skbuff);
868 void gfar_start(struct net_device *dev)
870 struct gfar_private *priv = netdev_priv(dev);
871 struct gfar __iomem *regs = priv->regs;
874 /* Enable Rx and Tx in MACCFG1 */
875 tempval = gfar_read(®s->maccfg1);
876 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
877 gfar_write(®s->maccfg1, tempval);
879 /* Initialize DMACTRL to have WWR and WOP */
880 tempval = gfar_read(&priv->regs->dmactrl);
881 tempval |= DMACTRL_INIT_SETTINGS;
882 gfar_write(&priv->regs->dmactrl, tempval);
884 /* Make sure we aren't stopped */
885 tempval = gfar_read(&priv->regs->dmactrl);
886 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
887 gfar_write(&priv->regs->dmactrl, tempval);
889 /* Clear THLT/RHLT, so that the DMA starts polling now */
890 gfar_write(®s->tstat, TSTAT_CLEAR_THALT);
891 gfar_write(®s->rstat, RSTAT_CLEAR_RHALT);
893 /* Unmask the interrupts we look for */
894 gfar_write(®s->imask, IMASK_DEFAULT);
896 dev->trans_start = jiffies;
899 /* Bring the controller up and running */
900 int startup_gfar(struct net_device *dev)
907 struct gfar_private *priv = netdev_priv(dev);
908 struct gfar __iomem *regs = priv->regs;
913 gfar_write(®s->imask, IMASK_INIT_CLEAR);
915 /* Allocate memory for the buffer descriptors */
916 vaddr = (unsigned long) dma_alloc_coherent(&dev->dev,
917 sizeof (struct txbd8) * priv->tx_ring_size +
918 sizeof (struct rxbd8) * priv->rx_ring_size,
922 if (netif_msg_ifup(priv))
923 printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
928 priv->tx_bd_base = (struct txbd8 *) vaddr;
930 /* enet DMA only understands physical addresses */
931 gfar_write(®s->tbase0, addr);
933 /* Start the rx descriptor ring where the tx ring leaves off */
934 addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
935 vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
936 priv->rx_bd_base = (struct rxbd8 *) vaddr;
937 gfar_write(®s->rbase0, addr);
939 /* Setup the skbuff rings */
941 (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
942 priv->tx_ring_size, GFP_KERNEL);
944 if (NULL == priv->tx_skbuff) {
945 if (netif_msg_ifup(priv))
946 printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
952 for (i = 0; i < priv->tx_ring_size; i++)
953 priv->tx_skbuff[i] = NULL;
956 (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
957 priv->rx_ring_size, GFP_KERNEL);
959 if (NULL == priv->rx_skbuff) {
960 if (netif_msg_ifup(priv))
961 printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
967 for (i = 0; i < priv->rx_ring_size; i++)
968 priv->rx_skbuff[i] = NULL;
970 /* Initialize some variables in our dev structure */
971 priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
972 priv->cur_rx = priv->rx_bd_base;
973 priv->skb_curtx = priv->skb_dirtytx = 0;
976 /* Initialize Transmit Descriptor Ring */
977 txbdp = priv->tx_bd_base;
978 for (i = 0; i < priv->tx_ring_size; i++) {
985 /* Set the last descriptor in the ring to indicate wrap */
987 txbdp->status |= TXBD_WRAP;
989 rxbdp = priv->rx_bd_base;
990 for (i = 0; i < priv->rx_ring_size; i++) {
993 skb = gfar_new_skb(dev);
996 printk(KERN_ERR "%s: Can't allocate RX buffers\n",
999 goto err_rxalloc_fail;
1002 priv->rx_skbuff[i] = skb;
1004 gfar_new_rxbdp(dev, rxbdp, skb);
1009 /* Set the last descriptor in the ring to wrap */
1011 rxbdp->status |= RXBD_WRAP;
1013 /* If the device has multiple interrupts, register for
1014 * them. Otherwise, only register for the one */
1015 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1016 /* Install our interrupt handlers for Error,
1017 * Transmit, and Receive */
1018 if (request_irq(priv->interruptError, gfar_error,
1019 0, "enet_error", dev) < 0) {
1020 if (netif_msg_intr(priv))
1021 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1022 dev->name, priv->interruptError);
1028 if (request_irq(priv->interruptTransmit, gfar_transmit,
1029 0, "enet_tx", dev) < 0) {
1030 if (netif_msg_intr(priv))
1031 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1032 dev->name, priv->interruptTransmit);
1039 if (request_irq(priv->interruptReceive, gfar_receive,
1040 0, "enet_rx", dev) < 0) {
1041 if (netif_msg_intr(priv))
1042 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
1043 dev->name, priv->interruptReceive);
1049 if (request_irq(priv->interruptTransmit, gfar_interrupt,
1050 0, "gfar_interrupt", dev) < 0) {
1051 if (netif_msg_intr(priv))
1052 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1053 dev->name, priv->interruptError);
1060 phy_start(priv->phydev);
1062 /* Configure the coalescing support */
1063 gfar_write(®s->txic, 0);
1064 if (priv->txcoalescing)
1065 gfar_write(®s->txic, priv->txic);
1067 gfar_write(®s->rxic, 0);
1068 if (priv->rxcoalescing)
1069 gfar_write(®s->rxic, priv->rxic);
1071 if (priv->rx_csum_enable)
1072 rctrl |= RCTRL_CHECKSUMMING;
1074 if (priv->extended_hash) {
1075 rctrl |= RCTRL_EXTHASH;
1077 gfar_clear_exact_match(dev);
1078 rctrl |= RCTRL_EMEN;
1081 if (priv->padding) {
1082 rctrl &= ~RCTRL_PAL_MASK;
1083 rctrl |= RCTRL_PADDING(priv->padding);
1086 /* Init rctrl based on our settings */
1087 gfar_write(&priv->regs->rctrl, rctrl);
1089 if (dev->features & NETIF_F_IP_CSUM)
1090 gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
1092 /* Set the extraction length and index */
1093 attrs = ATTRELI_EL(priv->rx_stash_size) |
1094 ATTRELI_EI(priv->rx_stash_index);
1096 gfar_write(&priv->regs->attreli, attrs);
1098 /* Start with defaults, and add stashing or locking
1099 * depending on the approprate variables */
1100 attrs = ATTR_INIT_SETTINGS;
1102 if (priv->bd_stash_en)
1103 attrs |= ATTR_BDSTASH;
1105 if (priv->rx_stash_size != 0)
1106 attrs |= ATTR_BUFSTASH;
1108 gfar_write(&priv->regs->attr, attrs);
1110 gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
1111 gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
1112 gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
1114 /* Start the controller */
1120 free_irq(priv->interruptTransmit, dev);
1122 free_irq(priv->interruptError, dev);
1126 free_skb_resources(priv);
1128 dma_free_coherent(&dev->dev,
1129 sizeof(struct txbd8)*priv->tx_ring_size
1130 + sizeof(struct rxbd8)*priv->rx_ring_size,
1132 gfar_read(®s->tbase0));
1137 /* Called when something needs to use the ethernet device */
1138 /* Returns 0 for success. */
1139 static int gfar_enet_open(struct net_device *dev)
1141 struct gfar_private *priv = netdev_priv(dev);
1144 napi_enable(&priv->napi);
1146 /* Initialize a bunch of registers */
1147 init_registers(dev);
1149 gfar_set_mac_address(dev);
1151 err = init_phy(dev);
1154 napi_disable(&priv->napi);
1158 err = startup_gfar(dev);
1160 napi_disable(&priv->napi);
1164 netif_start_queue(dev);
1169 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1171 struct txfcb *fcb = (struct txfcb *)skb_push (skb, GMAC_FCB_LEN);
1173 cacheable_memzero(fcb, GMAC_FCB_LEN);
1178 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1182 /* If we're here, it's a IP packet with a TCP or UDP
1183 * payload. We set it to checksum, using a pseudo-header
1186 flags = TXFCB_DEFAULT;
1188 /* Tell the controller what the protocol is */
1189 /* And provide the already calculated phcs */
1190 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1192 fcb->phcs = udp_hdr(skb)->check;
1194 fcb->phcs = tcp_hdr(skb)->check;
1196 /* l3os is the distance between the start of the
1197 * frame (skb->data) and the start of the IP hdr.
1198 * l4os is the distance between the start of the
1199 * l3 hdr and the l4 hdr */
1200 fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
1201 fcb->l4os = skb_network_header_len(skb);
1206 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1208 fcb->flags |= TXFCB_VLN;
1209 fcb->vlctl = vlan_tx_tag_get(skb);
1212 /* This is called by the kernel when a frame is ready for transmission. */
1213 /* It is pointed to by the dev->hard_start_xmit function pointer */
1214 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1216 struct gfar_private *priv = netdev_priv(dev);
1217 struct txfcb *fcb = NULL;
1218 struct txbd8 *txbdp;
1220 unsigned long flags;
1222 /* Update transmit stats */
1223 dev->stats.tx_bytes += skb->len;
1226 spin_lock_irqsave(&priv->txlock, flags);
1228 /* Point at the first free tx descriptor */
1229 txbdp = priv->cur_tx;
1231 /* Clear all but the WRAP status flags */
1232 status = txbdp->status & TXBD_WRAP;
1234 /* Set up checksumming */
1235 if (CHECKSUM_PARTIAL == skb->ip_summed) {
1236 fcb = gfar_add_fcb(skb);
1238 gfar_tx_checksum(skb, fcb);
1241 if (priv->vlgrp && vlan_tx_tag_present(skb)) {
1242 if (unlikely(NULL == fcb)) {
1243 fcb = gfar_add_fcb(skb);
1247 gfar_tx_vlan(skb, fcb);
1250 /* Set buffer length and pointer */
1251 txbdp->length = skb->len;
1252 txbdp->bufPtr = dma_map_single(&dev->dev, skb->data,
1253 skb->len, DMA_TO_DEVICE);
1255 /* Save the skb pointer so we can free it later */
1256 priv->tx_skbuff[priv->skb_curtx] = skb;
1258 /* Update the current skb pointer (wrapping if this was the last) */
1260 (priv->skb_curtx + 1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1262 /* Flag the BD as interrupt-causing */
1263 status |= TXBD_INTERRUPT;
1265 /* Flag the BD as ready to go, last in frame, and */
1266 /* in need of CRC */
1267 status |= (TXBD_READY | TXBD_LAST | TXBD_CRC);
1269 dev->trans_start = jiffies;
1271 /* The powerpc-specific eieio() is used, as wmb() has too strong
1272 * semantics (it requires synchronization between cacheable and
1273 * uncacheable mappings, which eieio doesn't provide and which we
1274 * don't need), thus requiring a more expensive sync instruction. At
1275 * some point, the set of architecture-independent barrier functions
1276 * should be expanded to include weaker barriers.
1280 txbdp->status = status;
1282 /* If this was the last BD in the ring, the next one */
1283 /* is at the beginning of the ring */
1284 if (txbdp->status & TXBD_WRAP)
1285 txbdp = priv->tx_bd_base;
1289 /* If the next BD still needs to be cleaned up, then the bds
1290 are full. We need to tell the kernel to stop sending us stuff. */
1291 if (txbdp == priv->dirty_tx) {
1292 netif_stop_queue(dev);
1294 dev->stats.tx_fifo_errors++;
1297 /* Update the current txbd to the next one */
1298 priv->cur_tx = txbdp;
1300 /* Tell the DMA to go go go */
1301 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1304 spin_unlock_irqrestore(&priv->txlock, flags);
1309 /* Stops the kernel queue, and halts the controller */
1310 static int gfar_close(struct net_device *dev)
1312 struct gfar_private *priv = netdev_priv(dev);
1314 napi_disable(&priv->napi);
1316 cancel_work_sync(&priv->reset_task);
1319 /* Disconnect from the PHY */
1320 phy_disconnect(priv->phydev);
1321 priv->phydev = NULL;
1323 netif_stop_queue(dev);
1328 /* Changes the mac address if the controller is not running. */
1329 static int gfar_set_mac_address(struct net_device *dev)
1331 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1337 /* Enables and disables VLAN insertion/extraction */
1338 static void gfar_vlan_rx_register(struct net_device *dev,
1339 struct vlan_group *grp)
1341 struct gfar_private *priv = netdev_priv(dev);
1342 unsigned long flags;
1343 struct vlan_group *old_grp;
1346 spin_lock_irqsave(&priv->rxlock, flags);
1348 old_grp = priv->vlgrp;
1354 /* Enable VLAN tag insertion */
1355 tempval = gfar_read(&priv->regs->tctrl);
1356 tempval |= TCTRL_VLINS;
1358 gfar_write(&priv->regs->tctrl, tempval);
1360 /* Enable VLAN tag extraction */
1361 tempval = gfar_read(&priv->regs->rctrl);
1362 tempval |= RCTRL_VLEX;
1363 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
1364 gfar_write(&priv->regs->rctrl, tempval);
1366 /* Disable VLAN tag insertion */
1367 tempval = gfar_read(&priv->regs->tctrl);
1368 tempval &= ~TCTRL_VLINS;
1369 gfar_write(&priv->regs->tctrl, tempval);
1371 /* Disable VLAN tag extraction */
1372 tempval = gfar_read(&priv->regs->rctrl);
1373 tempval &= ~RCTRL_VLEX;
1374 /* If parse is no longer required, then disable parser */
1375 if (tempval & RCTRL_REQ_PARSER)
1376 tempval |= RCTRL_PRSDEP_INIT;
1378 tempval &= ~RCTRL_PRSDEP_INIT;
1379 gfar_write(&priv->regs->rctrl, tempval);
1382 gfar_change_mtu(dev, dev->mtu);
1384 spin_unlock_irqrestore(&priv->rxlock, flags);
1387 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1389 int tempsize, tempval;
1390 struct gfar_private *priv = netdev_priv(dev);
1391 int oldsize = priv->rx_buffer_size;
1392 int frame_size = new_mtu + ETH_HLEN;
1395 frame_size += VLAN_HLEN;
1397 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1398 if (netif_msg_drv(priv))
1399 printk(KERN_ERR "%s: Invalid MTU setting\n",
1404 if (gfar_uses_fcb(priv))
1405 frame_size += GMAC_FCB_LEN;
1407 frame_size += priv->padding;
1410 (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1411 INCREMENTAL_BUFFER_SIZE;
1413 /* Only stop and start the controller if it isn't already
1414 * stopped, and we changed something */
1415 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1418 priv->rx_buffer_size = tempsize;
1422 gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1423 gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1425 /* If the mtu is larger than the max size for standard
1426 * ethernet frames (ie, a jumbo frame), then set maccfg2
1427 * to allow huge frames, and to check the length */
1428 tempval = gfar_read(&priv->regs->maccfg2);
1430 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1431 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1433 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1435 gfar_write(&priv->regs->maccfg2, tempval);
1437 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1443 /* gfar_reset_task gets scheduled when a packet has not been
1444 * transmitted after a set amount of time.
1445 * For now, assume that clearing out all the structures, and
1446 * starting over will fix the problem.
1448 static void gfar_reset_task(struct work_struct *work)
1450 struct gfar_private *priv = container_of(work, struct gfar_private,
1452 struct net_device *dev = priv->dev;
1454 if (dev->flags & IFF_UP) {
1459 netif_tx_schedule_all(dev);
1462 static void gfar_timeout(struct net_device *dev)
1464 struct gfar_private *priv = netdev_priv(dev);
1466 dev->stats.tx_errors++;
1467 schedule_work(&priv->reset_task);
1470 /* Interrupt Handler for Transmit complete */
1471 static int gfar_clean_tx_ring(struct net_device *dev)
1474 struct gfar_private *priv = netdev_priv(dev);
1477 bdp = priv->dirty_tx;
1478 while ((bdp->status & TXBD_READY) == 0) {
1479 /* If dirty_tx and cur_tx are the same, then either the */
1480 /* ring is empty or full now (it could only be full in the beginning, */
1481 /* obviously). If it is empty, we are done. */
1482 if ((bdp == priv->cur_tx) && (netif_queue_stopped(dev) == 0))
1487 /* Deferred means some collisions occurred during transmit, */
1488 /* but we eventually sent the packet. */
1489 if (bdp->status & TXBD_DEF)
1490 dev->stats.collisions++;
1492 /* Unmap the DMA memory */
1493 dma_unmap_single(&priv->dev->dev, bdp->bufPtr,
1494 bdp->length, DMA_TO_DEVICE);
1496 /* Free the sk buffer associated with this TxBD */
1497 dev_kfree_skb_irq(priv->tx_skbuff[priv->skb_dirtytx]);
1499 priv->tx_skbuff[priv->skb_dirtytx] = NULL;
1501 (priv->skb_dirtytx +
1502 1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1504 /* Clean BD length for empty detection */
1507 /* update bdp to point at next bd in the ring (wrapping if necessary) */
1508 if (bdp->status & TXBD_WRAP)
1509 bdp = priv->tx_bd_base;
1513 /* Move dirty_tx to be the next bd */
1514 priv->dirty_tx = bdp;
1516 /* We freed a buffer, so now we can restart transmission */
1517 if (netif_queue_stopped(dev))
1518 netif_wake_queue(dev);
1519 } /* while ((bdp->status & TXBD_READY) == 0) */
1521 dev->stats.tx_packets += howmany;
1526 /* Interrupt Handler for Transmit complete */
1527 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1529 struct net_device *dev = (struct net_device *) dev_id;
1530 struct gfar_private *priv = netdev_priv(dev);
1533 gfar_write(&priv->regs->ievent, IEVENT_TX_MASK);
1536 spin_lock(&priv->txlock);
1538 gfar_clean_tx_ring(dev);
1540 /* If we are coalescing the interrupts, reset the timer */
1541 /* Otherwise, clear it */
1542 if (likely(priv->txcoalescing)) {
1543 gfar_write(&priv->regs->txic, 0);
1544 gfar_write(&priv->regs->txic, priv->txic);
1547 spin_unlock(&priv->txlock);
1552 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
1553 struct sk_buff *skb)
1555 struct gfar_private *priv = netdev_priv(dev);
1556 u32 * status_len = (u32 *)bdp;
1559 bdp->bufPtr = dma_map_single(&dev->dev, skb->data,
1560 priv->rx_buffer_size, DMA_FROM_DEVICE);
1562 flags = RXBD_EMPTY | RXBD_INTERRUPT;
1564 if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1)
1569 *status_len = (u32)flags << 16;
1573 struct sk_buff * gfar_new_skb(struct net_device *dev)
1575 unsigned int alignamount;
1576 struct gfar_private *priv = netdev_priv(dev);
1577 struct sk_buff *skb = NULL;
1579 /* We have to allocate the skb, so keep trying till we succeed */
1580 skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
1585 alignamount = RXBUF_ALIGNMENT -
1586 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
1588 /* We need the data buffer to be aligned properly. We will reserve
1589 * as many bytes as needed to align the data properly
1591 skb_reserve(skb, alignamount);
1596 static inline void count_errors(unsigned short status, struct net_device *dev)
1598 struct gfar_private *priv = netdev_priv(dev);
1599 struct net_device_stats *stats = &dev->stats;
1600 struct gfar_extra_stats *estats = &priv->extra_stats;
1602 /* If the packet was truncated, none of the other errors
1604 if (status & RXBD_TRUNCATED) {
1605 stats->rx_length_errors++;
1611 /* Count the errors, if there were any */
1612 if (status & (RXBD_LARGE | RXBD_SHORT)) {
1613 stats->rx_length_errors++;
1615 if (status & RXBD_LARGE)
1620 if (status & RXBD_NONOCTET) {
1621 stats->rx_frame_errors++;
1622 estats->rx_nonoctet++;
1624 if (status & RXBD_CRCERR) {
1625 estats->rx_crcerr++;
1626 stats->rx_crc_errors++;
1628 if (status & RXBD_OVERRUN) {
1629 estats->rx_overrun++;
1630 stats->rx_crc_errors++;
1634 irqreturn_t gfar_receive(int irq, void *dev_id)
1636 struct net_device *dev = (struct net_device *) dev_id;
1637 struct gfar_private *priv = netdev_priv(dev);
1641 /* Clear IEVENT, so interrupts aren't called again
1642 * because of the packets that have already arrived */
1643 gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1645 if (netif_rx_schedule_prep(dev, &priv->napi)) {
1646 tempval = gfar_read(&priv->regs->imask);
1647 tempval &= IMASK_RTX_DISABLED;
1648 gfar_write(&priv->regs->imask, tempval);
1650 __netif_rx_schedule(dev, &priv->napi);
1652 if (netif_msg_rx_err(priv))
1653 printk(KERN_DEBUG "%s: receive called twice (%x)[%x]\n",
1654 dev->name, gfar_read(&priv->regs->ievent),
1655 gfar_read(&priv->regs->imask));
1661 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1663 /* If valid headers were found, and valid sums
1664 * were verified, then we tell the kernel that no
1665 * checksumming is necessary. Otherwise, it is */
1666 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1667 skb->ip_summed = CHECKSUM_UNNECESSARY;
1669 skb->ip_summed = CHECKSUM_NONE;
1673 /* gfar_process_frame() -- handle one incoming packet if skb
1675 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1678 struct gfar_private *priv = netdev_priv(dev);
1679 struct rxfcb *fcb = NULL;
1683 /* fcb is at the beginning if exists */
1684 fcb = (struct rxfcb *)skb->data;
1686 /* Remove the FCB from the skb */
1687 /* Remove the padded bytes, if there are any */
1689 skb_pull(skb, amount_pull);
1691 if (priv->rx_csum_enable)
1692 gfar_rx_checksum(skb, fcb);
1694 /* Tell the skb what kind of packet this is */
1695 skb->protocol = eth_type_trans(skb, dev);
1697 /* Send the packet up the stack */
1698 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
1699 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
1701 ret = netif_receive_skb(skb);
1703 if (NET_RX_DROP == ret)
1704 priv->extra_stats.kernel_dropped++;
1709 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1710 * until the budget/quota has been reached. Returns the number
1713 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1716 struct sk_buff *skb;
1720 struct gfar_private *priv = netdev_priv(dev);
1722 /* Get the first full descriptor */
1725 amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0) +
1728 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1729 struct sk_buff *newskb;
1732 /* Add another skb for the future */
1733 newskb = gfar_new_skb(dev);
1735 skb = priv->rx_skbuff[priv->skb_currx];
1737 dma_unmap_single(&priv->dev->dev, bdp->bufPtr,
1738 priv->rx_buffer_size, DMA_FROM_DEVICE);
1740 /* We drop the frame if we failed to allocate a new buffer */
1741 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
1742 bdp->status & RXBD_ERR)) {
1743 count_errors(bdp->status, dev);
1745 if (unlikely(!newskb))
1749 dev_kfree_skb_any(skb);
1751 /* Increment the number of packets */
1752 dev->stats.rx_packets++;
1756 pkt_len = bdp->length - ETH_FCS_LEN;
1757 /* Remove the FCS from the packet length */
1758 skb_put(skb, pkt_len);
1759 dev->stats.rx_bytes += pkt_len;
1761 gfar_process_frame(dev, skb, amount_pull);
1764 if (netif_msg_rx_err(priv))
1766 "%s: Missing skb!\n", dev->name);
1767 dev->stats.rx_dropped++;
1768 priv->extra_stats.rx_skbmissing++;
1773 priv->rx_skbuff[priv->skb_currx] = newskb;
1775 /* Setup the new bdp */
1776 gfar_new_rxbdp(dev, bdp, newskb);
1778 /* Update to the next pointer */
1779 if (bdp->status & RXBD_WRAP)
1780 bdp = priv->rx_bd_base;
1784 /* update to point at the next skb */
1786 (priv->skb_currx + 1) &
1787 RX_RING_MOD_MASK(priv->rx_ring_size);
1790 /* Update the current rxbd pointer to be the next one */
1796 static int gfar_poll(struct napi_struct *napi, int budget)
1798 struct gfar_private *priv = container_of(napi, struct gfar_private, napi);
1799 struct net_device *dev = priv->dev;
1801 unsigned long flags;
1803 /* If we fail to get the lock, don't bother with the TX BDs */
1804 if (spin_trylock_irqsave(&priv->txlock, flags)) {
1805 gfar_clean_tx_ring(dev);
1806 spin_unlock_irqrestore(&priv->txlock, flags);
1809 howmany = gfar_clean_rx_ring(dev, budget);
1811 if (howmany < budget) {
1812 netif_rx_complete(dev, napi);
1814 /* Clear the halt bit in RSTAT */
1815 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1817 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1819 /* If we are coalescing interrupts, update the timer */
1820 /* Otherwise, clear it */
1821 if (likely(priv->rxcoalescing)) {
1822 gfar_write(&priv->regs->rxic, 0);
1823 gfar_write(&priv->regs->rxic, priv->rxic);
1830 #ifdef CONFIG_NET_POLL_CONTROLLER
1832 * Polling 'interrupt' - used by things like netconsole to send skbs
1833 * without having to re-enable interrupts. It's not called while
1834 * the interrupt routine is executing.
1836 static void gfar_netpoll(struct net_device *dev)
1838 struct gfar_private *priv = netdev_priv(dev);
1840 /* If the device has multiple interrupts, run tx/rx */
1841 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1842 disable_irq(priv->interruptTransmit);
1843 disable_irq(priv->interruptReceive);
1844 disable_irq(priv->interruptError);
1845 gfar_interrupt(priv->interruptTransmit, dev);
1846 enable_irq(priv->interruptError);
1847 enable_irq(priv->interruptReceive);
1848 enable_irq(priv->interruptTransmit);
1850 disable_irq(priv->interruptTransmit);
1851 gfar_interrupt(priv->interruptTransmit, dev);
1852 enable_irq(priv->interruptTransmit);
1857 /* The interrupt handler for devices with one interrupt */
1858 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
1860 struct net_device *dev = dev_id;
1861 struct gfar_private *priv = netdev_priv(dev);
1863 /* Save ievent for future reference */
1864 u32 events = gfar_read(&priv->regs->ievent);
1866 /* Check for reception */
1867 if (events & IEVENT_RX_MASK)
1868 gfar_receive(irq, dev_id);
1870 /* Check for transmit completion */
1871 if (events & IEVENT_TX_MASK)
1872 gfar_transmit(irq, dev_id);
1874 /* Check for errors */
1875 if (events & IEVENT_ERR_MASK)
1876 gfar_error(irq, dev_id);
1881 /* Called every time the controller might need to be made
1882 * aware of new link state. The PHY code conveys this
1883 * information through variables in the phydev structure, and this
1884 * function converts those variables into the appropriate
1885 * register values, and can bring down the device if needed.
1887 static void adjust_link(struct net_device *dev)
1889 struct gfar_private *priv = netdev_priv(dev);
1890 struct gfar __iomem *regs = priv->regs;
1891 unsigned long flags;
1892 struct phy_device *phydev = priv->phydev;
1895 spin_lock_irqsave(&priv->txlock, flags);
1897 u32 tempval = gfar_read(®s->maccfg2);
1898 u32 ecntrl = gfar_read(®s->ecntrl);
1900 /* Now we make sure that we can be in full duplex mode.
1901 * If not, we operate in half-duplex mode. */
1902 if (phydev->duplex != priv->oldduplex) {
1904 if (!(phydev->duplex))
1905 tempval &= ~(MACCFG2_FULL_DUPLEX);
1907 tempval |= MACCFG2_FULL_DUPLEX;
1909 priv->oldduplex = phydev->duplex;
1912 if (phydev->speed != priv->oldspeed) {
1914 switch (phydev->speed) {
1917 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
1922 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
1924 /* Reduced mode distinguishes
1925 * between 10 and 100 */
1926 if (phydev->speed == SPEED_100)
1927 ecntrl |= ECNTRL_R100;
1929 ecntrl &= ~(ECNTRL_R100);
1932 if (netif_msg_link(priv))
1934 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
1935 dev->name, phydev->speed);
1939 priv->oldspeed = phydev->speed;
1942 gfar_write(®s->maccfg2, tempval);
1943 gfar_write(®s->ecntrl, ecntrl);
1945 if (!priv->oldlink) {
1949 } else if (priv->oldlink) {
1953 priv->oldduplex = -1;
1956 if (new_state && netif_msg_link(priv))
1957 phy_print_status(phydev);
1959 spin_unlock_irqrestore(&priv->txlock, flags);
1962 /* Update the hash table based on the current list of multicast
1963 * addresses we subscribe to. Also, change the promiscuity of
1964 * the device based on the flags (this function is called
1965 * whenever dev->flags is changed */
1966 static void gfar_set_multi(struct net_device *dev)
1968 struct dev_mc_list *mc_ptr;
1969 struct gfar_private *priv = netdev_priv(dev);
1970 struct gfar __iomem *regs = priv->regs;
1973 if(dev->flags & IFF_PROMISC) {
1974 /* Set RCTRL to PROM */
1975 tempval = gfar_read(®s->rctrl);
1976 tempval |= RCTRL_PROM;
1977 gfar_write(®s->rctrl, tempval);
1979 /* Set RCTRL to not PROM */
1980 tempval = gfar_read(®s->rctrl);
1981 tempval &= ~(RCTRL_PROM);
1982 gfar_write(®s->rctrl, tempval);
1985 if(dev->flags & IFF_ALLMULTI) {
1986 /* Set the hash to rx all multicast frames */
1987 gfar_write(®s->igaddr0, 0xffffffff);
1988 gfar_write(®s->igaddr1, 0xffffffff);
1989 gfar_write(®s->igaddr2, 0xffffffff);
1990 gfar_write(®s->igaddr3, 0xffffffff);
1991 gfar_write(®s->igaddr4, 0xffffffff);
1992 gfar_write(®s->igaddr5, 0xffffffff);
1993 gfar_write(®s->igaddr6, 0xffffffff);
1994 gfar_write(®s->igaddr7, 0xffffffff);
1995 gfar_write(®s->gaddr0, 0xffffffff);
1996 gfar_write(®s->gaddr1, 0xffffffff);
1997 gfar_write(®s->gaddr2, 0xffffffff);
1998 gfar_write(®s->gaddr3, 0xffffffff);
1999 gfar_write(®s->gaddr4, 0xffffffff);
2000 gfar_write(®s->gaddr5, 0xffffffff);
2001 gfar_write(®s->gaddr6, 0xffffffff);
2002 gfar_write(®s->gaddr7, 0xffffffff);
2007 /* zero out the hash */
2008 gfar_write(®s->igaddr0, 0x0);
2009 gfar_write(®s->igaddr1, 0x0);
2010 gfar_write(®s->igaddr2, 0x0);
2011 gfar_write(®s->igaddr3, 0x0);
2012 gfar_write(®s->igaddr4, 0x0);
2013 gfar_write(®s->igaddr5, 0x0);
2014 gfar_write(®s->igaddr6, 0x0);
2015 gfar_write(®s->igaddr7, 0x0);
2016 gfar_write(®s->gaddr0, 0x0);
2017 gfar_write(®s->gaddr1, 0x0);
2018 gfar_write(®s->gaddr2, 0x0);
2019 gfar_write(®s->gaddr3, 0x0);
2020 gfar_write(®s->gaddr4, 0x0);
2021 gfar_write(®s->gaddr5, 0x0);
2022 gfar_write(®s->gaddr6, 0x0);
2023 gfar_write(®s->gaddr7, 0x0);
2025 /* If we have extended hash tables, we need to
2026 * clear the exact match registers to prepare for
2028 if (priv->extended_hash) {
2029 em_num = GFAR_EM_NUM + 1;
2030 gfar_clear_exact_match(dev);
2037 if(dev->mc_count == 0)
2040 /* Parse the list, and set the appropriate bits */
2041 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
2043 gfar_set_mac_for_addr(dev, idx,
2047 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
2055 /* Clears each of the exact match registers to zero, so they
2056 * don't interfere with normal reception */
2057 static void gfar_clear_exact_match(struct net_device *dev)
2060 u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
2062 for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
2063 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
2066 /* Set the appropriate hash bit for the given addr */
2067 /* The algorithm works like so:
2068 * 1) Take the Destination Address (ie the multicast address), and
2069 * do a CRC on it (little endian), and reverse the bits of the
2071 * 2) Use the 8 most significant bits as a hash into a 256-entry
2072 * table. The table is controlled through 8 32-bit registers:
2073 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
2074 * gaddr7. This means that the 3 most significant bits in the
2075 * hash index which gaddr register to use, and the 5 other bits
2076 * indicate which bit (assuming an IBM numbering scheme, which
2077 * for PowerPC (tm) is usually the case) in the register holds
2079 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
2082 struct gfar_private *priv = netdev_priv(dev);
2083 u32 result = ether_crc(MAC_ADDR_LEN, addr);
2084 int width = priv->hash_width;
2085 u8 whichbit = (result >> (32 - width)) & 0x1f;
2086 u8 whichreg = result >> (32 - width + 5);
2087 u32 value = (1 << (31-whichbit));
2089 tempval = gfar_read(priv->hash_regs[whichreg]);
2091 gfar_write(priv->hash_regs[whichreg], tempval);
2097 /* There are multiple MAC Address register pairs on some controllers
2098 * This function sets the numth pair to a given address
2100 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
2102 struct gfar_private *priv = netdev_priv(dev);
2104 char tmpbuf[MAC_ADDR_LEN];
2106 u32 __iomem *macptr = &priv->regs->macstnaddr1;
2110 /* Now copy it into the mac registers backwards, cuz */
2111 /* little endian is silly */
2112 for (idx = 0; idx < MAC_ADDR_LEN; idx++)
2113 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
2115 gfar_write(macptr, *((u32 *) (tmpbuf)));
2117 tempval = *((u32 *) (tmpbuf + 4));
2119 gfar_write(macptr+1, tempval);
2122 /* GFAR error interrupt handler */
2123 static irqreturn_t gfar_error(int irq, void *dev_id)
2125 struct net_device *dev = dev_id;
2126 struct gfar_private *priv = netdev_priv(dev);
2128 /* Save ievent for future reference */
2129 u32 events = gfar_read(&priv->regs->ievent);
2132 gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK);
2134 /* Magic Packet is not an error. */
2135 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2136 (events & IEVENT_MAG))
2137 events &= ~IEVENT_MAG;
2140 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2141 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2142 dev->name, events, gfar_read(&priv->regs->imask));
2144 /* Update the error counters */
2145 if (events & IEVENT_TXE) {
2146 dev->stats.tx_errors++;
2148 if (events & IEVENT_LC)
2149 dev->stats.tx_window_errors++;
2150 if (events & IEVENT_CRL)
2151 dev->stats.tx_aborted_errors++;
2152 if (events & IEVENT_XFUN) {
2153 if (netif_msg_tx_err(priv))
2154 printk(KERN_DEBUG "%s: TX FIFO underrun, "
2155 "packet dropped.\n", dev->name);
2156 dev->stats.tx_dropped++;
2157 priv->extra_stats.tx_underrun++;
2159 /* Reactivate the Tx Queues */
2160 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
2162 if (netif_msg_tx_err(priv))
2163 printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
2165 if (events & IEVENT_BSY) {
2166 dev->stats.rx_errors++;
2167 priv->extra_stats.rx_bsy++;
2169 gfar_receive(irq, dev_id);
2171 if (netif_msg_rx_err(priv))
2172 printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
2173 dev->name, gfar_read(&priv->regs->rstat));
2175 if (events & IEVENT_BABR) {
2176 dev->stats.rx_errors++;
2177 priv->extra_stats.rx_babr++;
2179 if (netif_msg_rx_err(priv))
2180 printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
2182 if (events & IEVENT_EBERR) {
2183 priv->extra_stats.eberr++;
2184 if (netif_msg_rx_err(priv))
2185 printk(KERN_DEBUG "%s: bus error\n", dev->name);
2187 if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
2188 printk(KERN_DEBUG "%s: control frame\n", dev->name);
2190 if (events & IEVENT_BABT) {
2191 priv->extra_stats.tx_babt++;
2192 if (netif_msg_tx_err(priv))
2193 printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
2198 /* work with hotplug and coldplug */
2199 MODULE_ALIAS("platform:fsl-gianfar");
2201 static struct of_device_id gfar_match[] =
2205 .compatible = "gianfar",
2210 /* Structure for a device driver */
2211 static struct of_platform_driver gfar_driver = {
2212 .name = "fsl-gianfar",
2213 .match_table = gfar_match,
2215 .probe = gfar_probe,
2216 .remove = gfar_remove,
2217 .suspend = gfar_suspend,
2218 .resume = gfar_resume,
2221 static int __init gfar_init(void)
2223 int err = gfar_mdio_init();
2228 err = of_register_platform_driver(&gfar_driver);
2236 static void __exit gfar_exit(void)
2238 of_unregister_platform_driver(&gfar_driver);
2242 module_init(gfar_init);
2243 module_exit(gfar_exit);