2 * drivers/net/gianfar.c
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
10 * Maintainer: Kumar Gala
12 * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
13 * Copyright (c) 2007 MontaVista Software, Inc.
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * Gianfar: AKA Lambda Draconis, "Dragon"
28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
35 * last descriptor of the ring.
37 * When a packet is received, the RXF bit in the
38 * IEVENT register is set, triggering an interrupt when the
39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
42 * of frames or amount of time have passed). In NAPI, the
43 * interrupt handler will signal there is work to be done, and
44 * exit. This method will start at the last known empty
45 * descriptor, and process every subsequent descriptor until there
46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
64 #include <linux/kernel.h>
65 #include <linux/string.h>
66 #include <linux/errno.h>
67 #include <linux/unistd.h>
68 #include <linux/slab.h>
69 #include <linux/interrupt.h>
70 #include <linux/init.h>
71 #include <linux/delay.h>
72 #include <linux/netdevice.h>
73 #include <linux/etherdevice.h>
74 #include <linux/skbuff.h>
75 #include <linux/if_vlan.h>
76 #include <linux/spinlock.h>
78 #include <linux/of_mdio.h>
79 #include <linux/of_platform.h>
81 #include <linux/tcp.h>
82 #include <linux/udp.h>
87 #include <asm/uaccess.h>
88 #include <linux/module.h>
89 #include <linux/dma-mapping.h>
90 #include <linux/crc32.h>
91 #include <linux/mii.h>
92 #include <linux/phy.h>
93 #include <linux/phy_fixed.h>
97 #include "fsl_pq_mdio.h"
99 #define TX_TIMEOUT (1*HZ)
100 #undef BRIEF_GFAR_ERRORS
101 #undef VERBOSE_GFAR_ERRORS
103 const char gfar_driver_name[] = "Gianfar Ethernet";
104 const char gfar_driver_version[] = "1.3";
106 static int gfar_enet_open(struct net_device *dev);
107 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
108 static void gfar_reset_task(struct work_struct *work);
109 static void gfar_timeout(struct net_device *dev);
110 static int gfar_close(struct net_device *dev);
111 struct sk_buff *gfar_new_skb(struct net_device *dev);
112 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
113 struct sk_buff *skb);
114 static int gfar_set_mac_address(struct net_device *dev);
115 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
116 static irqreturn_t gfar_error(int irq, void *dev_id);
117 static irqreturn_t gfar_transmit(int irq, void *dev_id);
118 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
119 static void adjust_link(struct net_device *dev);
120 static void init_registers(struct net_device *dev);
121 static int init_phy(struct net_device *dev);
122 static int gfar_probe(struct of_device *ofdev,
123 const struct of_device_id *match);
124 static int gfar_remove(struct of_device *ofdev);
125 static void free_skb_resources(struct gfar_private *priv);
126 static void gfar_set_multi(struct net_device *dev);
127 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
128 static void gfar_configure_serdes(struct net_device *dev);
129 static int gfar_poll(struct napi_struct *napi, int budget);
130 #ifdef CONFIG_NET_POLL_CONTROLLER
131 static void gfar_netpoll(struct net_device *dev);
133 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
134 static int gfar_clean_tx_ring(struct net_device *dev);
135 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
137 static void gfar_vlan_rx_register(struct net_device *netdev,
138 struct vlan_group *grp);
139 void gfar_halt(struct net_device *dev);
140 static void gfar_halt_nodisable(struct net_device *dev);
141 void gfar_start(struct net_device *dev);
142 static void gfar_clear_exact_match(struct net_device *dev);
143 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
144 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
146 MODULE_AUTHOR("Freescale Semiconductor, Inc");
147 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
148 MODULE_LICENSE("GPL");
150 static const struct net_device_ops gfar_netdev_ops = {
151 .ndo_open = gfar_enet_open,
152 .ndo_start_xmit = gfar_start_xmit,
153 .ndo_stop = gfar_close,
154 .ndo_change_mtu = gfar_change_mtu,
155 .ndo_set_multicast_list = gfar_set_multi,
156 .ndo_tx_timeout = gfar_timeout,
157 .ndo_do_ioctl = gfar_ioctl,
158 .ndo_vlan_rx_register = gfar_vlan_rx_register,
159 .ndo_set_mac_address = eth_mac_addr,
160 .ndo_validate_addr = eth_validate_addr,
161 #ifdef CONFIG_NET_POLL_CONTROLLER
162 .ndo_poll_controller = gfar_netpoll,
166 /* Returns 1 if incoming frames use an FCB */
167 static inline int gfar_uses_fcb(struct gfar_private *priv)
169 return priv->vlgrp || priv->rx_csum_enable;
172 static int gfar_of_init(struct net_device *dev)
176 const void *mac_addr;
179 struct gfar_private *priv = netdev_priv(dev);
180 struct device_node *np = priv->node;
182 const u32 *stash_len;
183 const u32 *stash_idx;
185 if (!np || !of_device_is_available(np))
188 /* get a pointer to the register memory */
189 addr = of_translate_address(np, of_get_address(np, 0, &size, NULL));
190 priv->regs = ioremap(addr, size);
192 if (priv->regs == NULL)
195 priv->interruptTransmit = irq_of_parse_and_map(np, 0);
197 model = of_get_property(np, "model", NULL);
199 /* If we aren't the FEC we have multiple interrupts */
200 if (model && strcasecmp(model, "FEC")) {
201 priv->interruptReceive = irq_of_parse_and_map(np, 1);
203 priv->interruptError = irq_of_parse_and_map(np, 2);
205 if (priv->interruptTransmit < 0 ||
206 priv->interruptReceive < 0 ||
207 priv->interruptError < 0) {
213 stash = of_get_property(np, "bd-stash", NULL);
216 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
217 priv->bd_stash_en = 1;
220 stash_len = of_get_property(np, "rx-stash-len", NULL);
223 priv->rx_stash_size = *stash_len;
225 stash_idx = of_get_property(np, "rx-stash-idx", NULL);
228 priv->rx_stash_index = *stash_idx;
230 if (stash_len || stash_idx)
231 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
233 mac_addr = of_get_mac_address(np);
235 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
237 if (model && !strcasecmp(model, "TSEC"))
239 FSL_GIANFAR_DEV_HAS_GIGABIT |
240 FSL_GIANFAR_DEV_HAS_COALESCE |
241 FSL_GIANFAR_DEV_HAS_RMON |
242 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
243 if (model && !strcasecmp(model, "eTSEC"))
245 FSL_GIANFAR_DEV_HAS_GIGABIT |
246 FSL_GIANFAR_DEV_HAS_COALESCE |
247 FSL_GIANFAR_DEV_HAS_RMON |
248 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
249 FSL_GIANFAR_DEV_HAS_PADDING |
250 FSL_GIANFAR_DEV_HAS_CSUM |
251 FSL_GIANFAR_DEV_HAS_VLAN |
252 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
253 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH;
255 ctype = of_get_property(np, "phy-connection-type", NULL);
257 /* We only care about rgmii-id. The rest are autodetected */
258 if (ctype && !strcmp(ctype, "rgmii-id"))
259 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
261 priv->interface = PHY_INTERFACE_MODE_MII;
263 if (of_get_property(np, "fsl,magic-packet", NULL))
264 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
266 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
268 /* Find the TBI PHY. If it's not there, we don't support SGMII */
269 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
278 /* Ioctl MII Interface */
279 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
281 struct gfar_private *priv = netdev_priv(dev);
283 if (!netif_running(dev))
289 return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
292 /* Set up the ethernet device structure, private data,
293 * and anything else we need before we start */
294 static int gfar_probe(struct of_device *ofdev,
295 const struct of_device_id *match)
298 struct net_device *dev = NULL;
299 struct gfar_private *priv = NULL;
303 /* Create an ethernet device instance */
304 dev = alloc_etherdev(sizeof (*priv));
309 priv = netdev_priv(dev);
312 priv->node = ofdev->node;
313 SET_NETDEV_DEV(dev, &ofdev->dev);
315 err = gfar_of_init(dev);
320 spin_lock_init(&priv->txlock);
321 spin_lock_init(&priv->rxlock);
322 spin_lock_init(&priv->bflock);
323 INIT_WORK(&priv->reset_task, gfar_reset_task);
325 dev_set_drvdata(&ofdev->dev, priv);
327 /* Stop the DMA engine now, in case it was running before */
328 /* (The firmware could have used it, and left it running). */
331 /* Reset MAC layer */
332 gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
334 /* We need to delay at least 3 TX clocks */
337 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
338 gfar_write(&priv->regs->maccfg1, tempval);
340 /* Initialize MACCFG2. */
341 gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
343 /* Initialize ECNTRL */
344 gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
346 /* Set the dev->base_addr to the gfar reg region */
347 dev->base_addr = (unsigned long) (priv->regs);
349 SET_NETDEV_DEV(dev, &ofdev->dev);
351 /* Fill in the dev structure */
352 dev->watchdog_timeo = TX_TIMEOUT;
353 netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT);
356 dev->netdev_ops = &gfar_netdev_ops;
357 dev->ethtool_ops = &gfar_ethtool_ops;
359 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
360 priv->rx_csum_enable = 1;
361 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;
363 priv->rx_csum_enable = 0;
367 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)
368 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
370 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
371 priv->extended_hash = 1;
372 priv->hash_width = 9;
374 priv->hash_regs[0] = &priv->regs->igaddr0;
375 priv->hash_regs[1] = &priv->regs->igaddr1;
376 priv->hash_regs[2] = &priv->regs->igaddr2;
377 priv->hash_regs[3] = &priv->regs->igaddr3;
378 priv->hash_regs[4] = &priv->regs->igaddr4;
379 priv->hash_regs[5] = &priv->regs->igaddr5;
380 priv->hash_regs[6] = &priv->regs->igaddr6;
381 priv->hash_regs[7] = &priv->regs->igaddr7;
382 priv->hash_regs[8] = &priv->regs->gaddr0;
383 priv->hash_regs[9] = &priv->regs->gaddr1;
384 priv->hash_regs[10] = &priv->regs->gaddr2;
385 priv->hash_regs[11] = &priv->regs->gaddr3;
386 priv->hash_regs[12] = &priv->regs->gaddr4;
387 priv->hash_regs[13] = &priv->regs->gaddr5;
388 priv->hash_regs[14] = &priv->regs->gaddr6;
389 priv->hash_regs[15] = &priv->regs->gaddr7;
392 priv->extended_hash = 0;
393 priv->hash_width = 8;
395 priv->hash_regs[0] = &priv->regs->gaddr0;
396 priv->hash_regs[1] = &priv->regs->gaddr1;
397 priv->hash_regs[2] = &priv->regs->gaddr2;
398 priv->hash_regs[3] = &priv->regs->gaddr3;
399 priv->hash_regs[4] = &priv->regs->gaddr4;
400 priv->hash_regs[5] = &priv->regs->gaddr5;
401 priv->hash_regs[6] = &priv->regs->gaddr6;
402 priv->hash_regs[7] = &priv->regs->gaddr7;
405 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
406 priv->padding = DEFAULT_PADDING;
410 if (dev->features & NETIF_F_IP_CSUM)
411 dev->hard_header_len += GMAC_FCB_LEN;
413 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
414 priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
415 priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
416 priv->num_txbdfree = DEFAULT_TX_RING_SIZE;
418 priv->txcoalescing = DEFAULT_TX_COALESCE;
419 priv->txic = DEFAULT_TXIC;
420 priv->rxcoalescing = DEFAULT_RX_COALESCE;
421 priv->rxic = DEFAULT_RXIC;
423 /* Enable most messages by default */
424 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
426 /* Carrier starts down, phylib will bring it up */
427 netif_carrier_off(dev);
429 err = register_netdev(dev);
432 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
437 device_init_wakeup(&dev->dev,
438 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
440 /* fill out IRQ number and name fields */
441 len_devname = strlen(dev->name);
442 strncpy(&priv->int_name_tx[0], dev->name, len_devname);
443 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
444 strncpy(&priv->int_name_tx[len_devname],
445 "_tx", sizeof("_tx") + 1);
447 strncpy(&priv->int_name_rx[0], dev->name, len_devname);
448 strncpy(&priv->int_name_rx[len_devname],
449 "_rx", sizeof("_rx") + 1);
451 strncpy(&priv->int_name_er[0], dev->name, len_devname);
452 strncpy(&priv->int_name_er[len_devname],
453 "_er", sizeof("_er") + 1);
455 priv->int_name_tx[len_devname] = '\0';
457 /* Create all the sysfs files */
458 gfar_init_sysfs(dev);
460 /* Print out the device info */
461 printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
463 /* Even more device info helps when determining which kernel */
464 /* provided which set of benchmarks. */
465 printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
466 printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
467 dev->name, priv->rx_ring_size, priv->tx_ring_size);
475 of_node_put(priv->phy_node);
477 of_node_put(priv->tbi_node);
482 static int gfar_remove(struct of_device *ofdev)
484 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
487 of_node_put(priv->phy_node);
489 of_node_put(priv->tbi_node);
491 dev_set_drvdata(&ofdev->dev, NULL);
493 unregister_netdev(priv->ndev);
495 free_netdev(priv->ndev);
501 static int gfar_suspend(struct of_device *ofdev, pm_message_t state)
503 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
504 struct net_device *dev = priv->ndev;
508 int magic_packet = priv->wol_en &&
509 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
511 netif_device_detach(dev);
513 if (netif_running(dev)) {
514 spin_lock_irqsave(&priv->txlock, flags);
515 spin_lock(&priv->rxlock);
517 gfar_halt_nodisable(dev);
519 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
520 tempval = gfar_read(&priv->regs->maccfg1);
522 tempval &= ~MACCFG1_TX_EN;
525 tempval &= ~MACCFG1_RX_EN;
527 gfar_write(&priv->regs->maccfg1, tempval);
529 spin_unlock(&priv->rxlock);
530 spin_unlock_irqrestore(&priv->txlock, flags);
532 napi_disable(&priv->napi);
535 /* Enable interrupt on Magic Packet */
536 gfar_write(&priv->regs->imask, IMASK_MAG);
538 /* Enable Magic Packet mode */
539 tempval = gfar_read(&priv->regs->maccfg2);
540 tempval |= MACCFG2_MPEN;
541 gfar_write(&priv->regs->maccfg2, tempval);
543 phy_stop(priv->phydev);
550 static int gfar_resume(struct of_device *ofdev)
552 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
553 struct net_device *dev = priv->ndev;
556 int magic_packet = priv->wol_en &&
557 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
559 if (!netif_running(dev)) {
560 netif_device_attach(dev);
564 if (!magic_packet && priv->phydev)
565 phy_start(priv->phydev);
567 /* Disable Magic Packet mode, in case something
571 spin_lock_irqsave(&priv->txlock, flags);
572 spin_lock(&priv->rxlock);
574 tempval = gfar_read(&priv->regs->maccfg2);
575 tempval &= ~MACCFG2_MPEN;
576 gfar_write(&priv->regs->maccfg2, tempval);
580 spin_unlock(&priv->rxlock);
581 spin_unlock_irqrestore(&priv->txlock, flags);
583 netif_device_attach(dev);
585 napi_enable(&priv->napi);
590 #define gfar_suspend NULL
591 #define gfar_resume NULL
594 /* Reads the controller's registers to determine what interface
595 * connects it to the PHY.
597 static phy_interface_t gfar_get_interface(struct net_device *dev)
599 struct gfar_private *priv = netdev_priv(dev);
600 u32 ecntrl = gfar_read(&priv->regs->ecntrl);
602 if (ecntrl & ECNTRL_SGMII_MODE)
603 return PHY_INTERFACE_MODE_SGMII;
605 if (ecntrl & ECNTRL_TBI_MODE) {
606 if (ecntrl & ECNTRL_REDUCED_MODE)
607 return PHY_INTERFACE_MODE_RTBI;
609 return PHY_INTERFACE_MODE_TBI;
612 if (ecntrl & ECNTRL_REDUCED_MODE) {
613 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
614 return PHY_INTERFACE_MODE_RMII;
616 phy_interface_t interface = priv->interface;
619 * This isn't autodetected right now, so it must
620 * be set by the device tree or platform code.
622 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
623 return PHY_INTERFACE_MODE_RGMII_ID;
625 return PHY_INTERFACE_MODE_RGMII;
629 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
630 return PHY_INTERFACE_MODE_GMII;
632 return PHY_INTERFACE_MODE_MII;
636 /* Initializes driver's PHY state, and attaches to the PHY.
637 * Returns 0 on success.
639 static int init_phy(struct net_device *dev)
641 struct gfar_private *priv = netdev_priv(dev);
642 uint gigabit_support =
643 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
644 SUPPORTED_1000baseT_Full : 0;
645 phy_interface_t interface;
649 priv->oldduplex = -1;
651 interface = gfar_get_interface(dev);
653 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
656 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
659 dev_err(&dev->dev, "could not attach to PHY\n");
663 if (interface == PHY_INTERFACE_MODE_SGMII)
664 gfar_configure_serdes(dev);
666 /* Remove any features not supported by the controller */
667 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
668 priv->phydev->advertising = priv->phydev->supported;
674 * Initialize TBI PHY interface for communicating with the
675 * SERDES lynx PHY on the chip. We communicate with this PHY
676 * through the MDIO bus on each controller, treating it as a
677 * "normal" PHY at the address found in the TBIPA register. We assume
678 * that the TBIPA register is valid. Either the MDIO bus code will set
679 * it to a value that doesn't conflict with other PHYs on the bus, or the
680 * value doesn't matter, as there are no other PHYs on the bus.
682 static void gfar_configure_serdes(struct net_device *dev)
684 struct gfar_private *priv = netdev_priv(dev);
685 struct phy_device *tbiphy;
687 if (!priv->tbi_node) {
688 dev_warn(&dev->dev, "error: SGMII mode requires that the "
689 "device tree specify a tbi-handle\n");
693 tbiphy = of_phy_find_device(priv->tbi_node);
695 dev_err(&dev->dev, "error: Could not get TBI device\n");
700 * If the link is already up, we must already be ok, and don't need to
701 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
702 * everything for us? Resetting it takes the link down and requires
703 * several seconds for it to come back.
705 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
708 /* Single clk mode, mii mode off(for serdes communication) */
709 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
711 phy_write(tbiphy, MII_ADVERTISE,
712 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
713 ADVERTISE_1000XPSE_ASYM);
715 phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE |
716 BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
719 static void init_registers(struct net_device *dev)
721 struct gfar_private *priv = netdev_priv(dev);
724 gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
726 /* Initialize IMASK */
727 gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
729 /* Init hash registers to zero */
730 gfar_write(&priv->regs->igaddr0, 0);
731 gfar_write(&priv->regs->igaddr1, 0);
732 gfar_write(&priv->regs->igaddr2, 0);
733 gfar_write(&priv->regs->igaddr3, 0);
734 gfar_write(&priv->regs->igaddr4, 0);
735 gfar_write(&priv->regs->igaddr5, 0);
736 gfar_write(&priv->regs->igaddr6, 0);
737 gfar_write(&priv->regs->igaddr7, 0);
739 gfar_write(&priv->regs->gaddr0, 0);
740 gfar_write(&priv->regs->gaddr1, 0);
741 gfar_write(&priv->regs->gaddr2, 0);
742 gfar_write(&priv->regs->gaddr3, 0);
743 gfar_write(&priv->regs->gaddr4, 0);
744 gfar_write(&priv->regs->gaddr5, 0);
745 gfar_write(&priv->regs->gaddr6, 0);
746 gfar_write(&priv->regs->gaddr7, 0);
748 /* Zero out the rmon mib registers if it has them */
749 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
750 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
752 /* Mask off the CAM interrupts */
753 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
754 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
757 /* Initialize the max receive buffer length */
758 gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
760 /* Initialize the Minimum Frame Length Register */
761 gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
765 /* Halt the receive and transmit queues */
766 static void gfar_halt_nodisable(struct net_device *dev)
768 struct gfar_private *priv = netdev_priv(dev);
769 struct gfar __iomem *regs = priv->regs;
772 /* Mask all interrupts */
773 gfar_write(®s->imask, IMASK_INIT_CLEAR);
775 /* Clear all interrupts */
776 gfar_write(®s->ievent, IEVENT_INIT_CLEAR);
778 /* Stop the DMA, and wait for it to stop */
779 tempval = gfar_read(&priv->regs->dmactrl);
780 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
781 != (DMACTRL_GRS | DMACTRL_GTS)) {
782 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
783 gfar_write(&priv->regs->dmactrl, tempval);
785 while (!(gfar_read(&priv->regs->ievent) &
786 (IEVENT_GRSC | IEVENT_GTSC)))
791 /* Halt the receive and transmit queues */
792 void gfar_halt(struct net_device *dev)
794 struct gfar_private *priv = netdev_priv(dev);
795 struct gfar __iomem *regs = priv->regs;
798 gfar_halt_nodisable(dev);
800 /* Disable Rx and Tx */
801 tempval = gfar_read(®s->maccfg1);
802 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
803 gfar_write(®s->maccfg1, tempval);
806 void stop_gfar(struct net_device *dev)
808 struct gfar_private *priv = netdev_priv(dev);
809 struct gfar __iomem *regs = priv->regs;
812 phy_stop(priv->phydev);
815 spin_lock_irqsave(&priv->txlock, flags);
816 spin_lock(&priv->rxlock);
820 spin_unlock(&priv->rxlock);
821 spin_unlock_irqrestore(&priv->txlock, flags);
824 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
825 free_irq(priv->interruptError, dev);
826 free_irq(priv->interruptTransmit, dev);
827 free_irq(priv->interruptReceive, dev);
829 free_irq(priv->interruptTransmit, dev);
832 free_skb_resources(priv);
834 dma_free_coherent(&priv->ofdev->dev,
835 sizeof(struct txbd8)*priv->tx_ring_size
836 + sizeof(struct rxbd8)*priv->rx_ring_size,
838 gfar_read(®s->tbase0));
841 /* If there are any tx skbs or rx skbs still around, free them.
842 * Then free tx_skbuff and rx_skbuff */
843 static void free_skb_resources(struct gfar_private *priv)
849 /* Go through all the buffer descriptors and free their data buffers */
850 txbdp = priv->tx_bd_base;
852 for (i = 0; i < priv->tx_ring_size; i++) {
853 if (!priv->tx_skbuff[i])
856 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
857 txbdp->length, DMA_TO_DEVICE);
859 for (j = 0; j < skb_shinfo(priv->tx_skbuff[i])->nr_frags; j++) {
861 dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
862 txbdp->length, DMA_TO_DEVICE);
865 dev_kfree_skb_any(priv->tx_skbuff[i]);
866 priv->tx_skbuff[i] = NULL;
869 kfree(priv->tx_skbuff);
871 rxbdp = priv->rx_bd_base;
873 /* rx_skbuff is not guaranteed to be allocated, so only
874 * free it and its contents if it is allocated */
875 if(priv->rx_skbuff != NULL) {
876 for (i = 0; i < priv->rx_ring_size; i++) {
877 if (priv->rx_skbuff[i]) {
878 dma_unmap_single(&priv->ofdev->dev, rxbdp->bufPtr,
879 priv->rx_buffer_size,
882 dev_kfree_skb_any(priv->rx_skbuff[i]);
883 priv->rx_skbuff[i] = NULL;
892 kfree(priv->rx_skbuff);
896 void gfar_start(struct net_device *dev)
898 struct gfar_private *priv = netdev_priv(dev);
899 struct gfar __iomem *regs = priv->regs;
902 /* Enable Rx and Tx in MACCFG1 */
903 tempval = gfar_read(®s->maccfg1);
904 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
905 gfar_write(®s->maccfg1, tempval);
907 /* Initialize DMACTRL to have WWR and WOP */
908 tempval = gfar_read(&priv->regs->dmactrl);
909 tempval |= DMACTRL_INIT_SETTINGS;
910 gfar_write(&priv->regs->dmactrl, tempval);
912 /* Make sure we aren't stopped */
913 tempval = gfar_read(&priv->regs->dmactrl);
914 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
915 gfar_write(&priv->regs->dmactrl, tempval);
917 /* Clear THLT/RHLT, so that the DMA starts polling now */
918 gfar_write(®s->tstat, TSTAT_CLEAR_THALT);
919 gfar_write(®s->rstat, RSTAT_CLEAR_RHALT);
921 /* Unmask the interrupts we look for */
922 gfar_write(®s->imask, IMASK_DEFAULT);
924 dev->trans_start = jiffies;
927 /* Bring the controller up and running */
928 int startup_gfar(struct net_device *ndev)
935 struct gfar_private *priv = netdev_priv(ndev);
936 struct device *dev = &priv->ofdev->dev;
937 struct gfar __iomem *regs = priv->regs;
943 gfar_write(®s->imask, IMASK_INIT_CLEAR);
945 /* Allocate memory for the buffer descriptors */
946 vaddr = dma_alloc_coherent(dev, sizeof(*txbdp) * priv->tx_ring_size +
947 sizeof(*rxbdp) * priv->rx_ring_size,
950 if (netif_msg_ifup(priv))
951 pr_err("%s: Could not allocate buffer descriptors!\n",
956 priv->tx_bd_base = vaddr;
958 /* enet DMA only understands physical addresses */
959 gfar_write(®s->tbase0, addr);
961 /* Start the rx descriptor ring where the tx ring leaves off */
962 addr = addr + sizeof(*txbdp) * priv->tx_ring_size;
963 vaddr = vaddr + sizeof(*txbdp) * priv->tx_ring_size;
964 priv->rx_bd_base = vaddr;
965 gfar_write(®s->rbase0, addr);
967 /* Setup the skbuff rings */
968 priv->tx_skbuff = kmalloc(sizeof(*priv->tx_skbuff) *
969 priv->tx_ring_size, GFP_KERNEL);
970 if (!priv->tx_skbuff) {
971 if (netif_msg_ifup(priv))
972 pr_err("%s: Could not allocate tx_skbuff\n",
978 for (i = 0; i < priv->tx_ring_size; i++)
979 priv->tx_skbuff[i] = NULL;
981 priv->rx_skbuff = kmalloc(sizeof(*priv->rx_skbuff) *
982 priv->rx_ring_size, GFP_KERNEL);
983 if (!priv->rx_skbuff) {
984 if (netif_msg_ifup(priv))
985 pr_err("%s: Could not allocate rx_skbuff\n",
991 for (i = 0; i < priv->rx_ring_size; i++)
992 priv->rx_skbuff[i] = NULL;
994 /* Initialize some variables in our dev structure */
995 priv->num_txbdfree = priv->tx_ring_size;
996 priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
997 priv->cur_rx = priv->rx_bd_base;
998 priv->skb_curtx = priv->skb_dirtytx = 0;
1001 /* Initialize Transmit Descriptor Ring */
1002 txbdp = priv->tx_bd_base;
1003 for (i = 0; i < priv->tx_ring_size; i++) {
1009 /* Set the last descriptor in the ring to indicate wrap */
1011 txbdp->status |= TXBD_WRAP;
1013 rxbdp = priv->rx_bd_base;
1014 for (i = 0; i < priv->rx_ring_size; i++) {
1015 struct sk_buff *skb;
1017 skb = gfar_new_skb(ndev);
1019 pr_err("%s: Can't allocate RX buffers\n", ndev->name);
1021 goto err_rxalloc_fail;
1024 priv->rx_skbuff[i] = skb;
1026 gfar_new_rxbdp(ndev, rxbdp, skb);
1031 /* Set the last descriptor in the ring to wrap */
1033 rxbdp->status |= RXBD_WRAP;
1035 /* If the device has multiple interrupts, register for
1036 * them. Otherwise, only register for the one */
1037 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1038 /* Install our interrupt handlers for Error,
1039 * Transmit, and Receive */
1040 err = request_irq(priv->interruptError, gfar_error, 0,
1041 priv->int_name_er, ndev);
1043 if (netif_msg_intr(priv))
1044 pr_err("%s: Can't get IRQ %d\n", ndev->name,
1045 priv->interruptError);
1049 err = request_irq(priv->interruptTransmit, gfar_transmit, 0,
1050 priv->int_name_tx, ndev);
1052 if (netif_msg_intr(priv))
1053 pr_err("%s: Can't get IRQ %d\n", ndev->name,
1054 priv->interruptTransmit);
1058 err = request_irq(priv->interruptReceive, gfar_receive, 0,
1059 priv->int_name_rx, ndev);
1061 if (netif_msg_intr(priv))
1062 pr_err("%s: Can't get IRQ %d (receive0)\n",
1063 ndev->name, priv->interruptReceive);
1067 err = request_irq(priv->interruptTransmit, gfar_interrupt,
1068 0, priv->int_name_tx, ndev);
1070 if (netif_msg_intr(priv))
1071 pr_err("%s: Can't get IRQ %d\n", ndev->name,
1072 priv->interruptTransmit);
1077 phy_start(priv->phydev);
1079 /* Configure the coalescing support */
1080 gfar_write(®s->txic, 0);
1081 if (priv->txcoalescing)
1082 gfar_write(®s->txic, priv->txic);
1084 gfar_write(®s->rxic, 0);
1085 if (priv->rxcoalescing)
1086 gfar_write(®s->rxic, priv->rxic);
1088 if (priv->rx_csum_enable)
1089 rctrl |= RCTRL_CHECKSUMMING;
1091 if (priv->extended_hash) {
1092 rctrl |= RCTRL_EXTHASH;
1094 gfar_clear_exact_match(ndev);
1095 rctrl |= RCTRL_EMEN;
1098 if (priv->padding) {
1099 rctrl &= ~RCTRL_PAL_MASK;
1100 rctrl |= RCTRL_PADDING(priv->padding);
1103 /* keep vlan related bits if it's enabled */
1105 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
1106 tctrl |= TCTRL_VLINS;
1109 /* Init rctrl based on our settings */
1110 gfar_write(®s->rctrl, rctrl);
1112 if (ndev->features & NETIF_F_IP_CSUM)
1113 tctrl |= TCTRL_INIT_CSUM;
1115 gfar_write(®s->tctrl, tctrl);
1117 /* Set the extraction length and index */
1118 attrs = ATTRELI_EL(priv->rx_stash_size) |
1119 ATTRELI_EI(priv->rx_stash_index);
1121 gfar_write(®s->attreli, attrs);
1123 /* Start with defaults, and add stashing or locking
1124 * depending on the approprate variables */
1125 attrs = ATTR_INIT_SETTINGS;
1127 if (priv->bd_stash_en)
1128 attrs |= ATTR_BDSTASH;
1130 if (priv->rx_stash_size != 0)
1131 attrs |= ATTR_BUFSTASH;
1133 gfar_write(®s->attr, attrs);
1135 gfar_write(®s->fifo_tx_thr, priv->fifo_threshold);
1136 gfar_write(®s->fifo_tx_starve, priv->fifo_starve);
1137 gfar_write(®s->fifo_tx_starve_shutoff, priv->fifo_starve_off);
1139 /* Start the controller */
1145 free_irq(priv->interruptTransmit, ndev);
1147 free_irq(priv->interruptError, ndev);
1151 free_skb_resources(priv);
1153 dma_free_coherent(dev, sizeof(*txbdp) * priv->tx_ring_size +
1154 sizeof(*rxbdp) * priv->rx_ring_size,
1155 priv->tx_bd_base, gfar_read(®s->tbase0));
1159 /* Called when something needs to use the ethernet device */
1160 /* Returns 0 for success. */
1161 static int gfar_enet_open(struct net_device *dev)
1163 struct gfar_private *priv = netdev_priv(dev);
1166 napi_enable(&priv->napi);
1168 skb_queue_head_init(&priv->rx_recycle);
1170 /* Initialize a bunch of registers */
1171 init_registers(dev);
1173 gfar_set_mac_address(dev);
1175 err = init_phy(dev);
1178 napi_disable(&priv->napi);
1182 err = startup_gfar(dev);
1184 napi_disable(&priv->napi);
1188 netif_start_queue(dev);
1190 device_set_wakeup_enable(&dev->dev, priv->wol_en);
1195 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1197 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1199 memset(fcb, 0, GMAC_FCB_LEN);
1204 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1208 /* If we're here, it's a IP packet with a TCP or UDP
1209 * payload. We set it to checksum, using a pseudo-header
1212 flags = TXFCB_DEFAULT;
1214 /* Tell the controller what the protocol is */
1215 /* And provide the already calculated phcs */
1216 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1218 fcb->phcs = udp_hdr(skb)->check;
1220 fcb->phcs = tcp_hdr(skb)->check;
1222 /* l3os is the distance between the start of the
1223 * frame (skb->data) and the start of the IP hdr.
1224 * l4os is the distance between the start of the
1225 * l3 hdr and the l4 hdr */
1226 fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
1227 fcb->l4os = skb_network_header_len(skb);
1232 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1234 fcb->flags |= TXFCB_VLN;
1235 fcb->vlctl = vlan_tx_tag_get(skb);
1238 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
1239 struct txbd8 *base, int ring_size)
1241 struct txbd8 *new_bd = bdp + stride;
1243 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
1246 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
1249 return skip_txbd(bdp, 1, base, ring_size);
1252 /* This is called by the kernel when a frame is ready for transmission. */
1253 /* It is pointed to by the dev->hard_start_xmit function pointer */
1254 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1256 struct gfar_private *priv = netdev_priv(dev);
1257 struct txfcb *fcb = NULL;
1258 struct txbd8 *txbdp, *txbdp_start, *base;
1262 unsigned long flags;
1263 unsigned int nr_frags, length;
1265 base = priv->tx_bd_base;
1267 /* make space for additional header when fcb is needed */
1268 if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
1269 (priv->vlgrp && vlan_tx_tag_present(skb))) &&
1270 (skb_headroom(skb) < GMAC_FCB_LEN)) {
1271 struct sk_buff *skb_new;
1273 skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN);
1275 dev->stats.tx_errors++;
1277 return NETDEV_TX_OK;
1283 /* total number of fragments in the SKB */
1284 nr_frags = skb_shinfo(skb)->nr_frags;
1286 spin_lock_irqsave(&priv->txlock, flags);
1288 /* check if there is space to queue this packet */
1289 if ((nr_frags+1) > priv->num_txbdfree) {
1290 /* no space, stop the queue */
1291 netif_stop_queue(dev);
1292 dev->stats.tx_fifo_errors++;
1293 spin_unlock_irqrestore(&priv->txlock, flags);
1294 return NETDEV_TX_BUSY;
1297 /* Update transmit stats */
1298 dev->stats.tx_bytes += skb->len;
1300 txbdp = txbdp_start = priv->cur_tx;
1302 if (nr_frags == 0) {
1303 lstatus = txbdp->lstatus | BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1305 /* Place the fragment addresses and lengths into the TxBDs */
1306 for (i = 0; i < nr_frags; i++) {
1307 /* Point at the next BD, wrapping as needed */
1308 txbdp = next_txbd(txbdp, base, priv->tx_ring_size);
1310 length = skb_shinfo(skb)->frags[i].size;
1312 lstatus = txbdp->lstatus | length |
1313 BD_LFLAG(TXBD_READY);
1315 /* Handle the last BD specially */
1316 if (i == nr_frags - 1)
1317 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1319 bufaddr = dma_map_page(&priv->ofdev->dev,
1320 skb_shinfo(skb)->frags[i].page,
1321 skb_shinfo(skb)->frags[i].page_offset,
1325 /* set the TxBD length and buffer pointer */
1326 txbdp->bufPtr = bufaddr;
1327 txbdp->lstatus = lstatus;
1330 lstatus = txbdp_start->lstatus;
1333 /* Set up checksumming */
1334 if (CHECKSUM_PARTIAL == skb->ip_summed) {
1335 fcb = gfar_add_fcb(skb);
1336 lstatus |= BD_LFLAG(TXBD_TOE);
1337 gfar_tx_checksum(skb, fcb);
1340 if (priv->vlgrp && vlan_tx_tag_present(skb)) {
1341 if (unlikely(NULL == fcb)) {
1342 fcb = gfar_add_fcb(skb);
1343 lstatus |= BD_LFLAG(TXBD_TOE);
1346 gfar_tx_vlan(skb, fcb);
1349 /* setup the TxBD length and buffer pointer for the first BD */
1350 priv->tx_skbuff[priv->skb_curtx] = skb;
1351 txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
1352 skb_headlen(skb), DMA_TO_DEVICE);
1354 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
1357 * The powerpc-specific eieio() is used, as wmb() has too strong
1358 * semantics (it requires synchronization between cacheable and
1359 * uncacheable mappings, which eieio doesn't provide and which we
1360 * don't need), thus requiring a more expensive sync instruction. At
1361 * some point, the set of architecture-independent barrier functions
1362 * should be expanded to include weaker barriers.
1366 txbdp_start->lstatus = lstatus;
1368 /* Update the current skb pointer to the next entry we will use
1369 * (wrapping if necessary) */
1370 priv->skb_curtx = (priv->skb_curtx + 1) &
1371 TX_RING_MOD_MASK(priv->tx_ring_size);
1373 priv->cur_tx = next_txbd(txbdp, base, priv->tx_ring_size);
1375 /* reduce TxBD free count */
1376 priv->num_txbdfree -= (nr_frags + 1);
1378 dev->trans_start = jiffies;
1380 /* If the next BD still needs to be cleaned up, then the bds
1381 are full. We need to tell the kernel to stop sending us stuff. */
1382 if (!priv->num_txbdfree) {
1383 netif_stop_queue(dev);
1385 dev->stats.tx_fifo_errors++;
1388 /* Tell the DMA to go go go */
1389 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1392 spin_unlock_irqrestore(&priv->txlock, flags);
1394 return NETDEV_TX_OK;
1397 /* Stops the kernel queue, and halts the controller */
1398 static int gfar_close(struct net_device *dev)
1400 struct gfar_private *priv = netdev_priv(dev);
1402 napi_disable(&priv->napi);
1404 skb_queue_purge(&priv->rx_recycle);
1405 cancel_work_sync(&priv->reset_task);
1408 /* Disconnect from the PHY */
1409 phy_disconnect(priv->phydev);
1410 priv->phydev = NULL;
1412 netif_stop_queue(dev);
1417 /* Changes the mac address if the controller is not running. */
1418 static int gfar_set_mac_address(struct net_device *dev)
1420 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1426 /* Enables and disables VLAN insertion/extraction */
1427 static void gfar_vlan_rx_register(struct net_device *dev,
1428 struct vlan_group *grp)
1430 struct gfar_private *priv = netdev_priv(dev);
1431 unsigned long flags;
1434 spin_lock_irqsave(&priv->rxlock, flags);
1439 /* Enable VLAN tag insertion */
1440 tempval = gfar_read(&priv->regs->tctrl);
1441 tempval |= TCTRL_VLINS;
1443 gfar_write(&priv->regs->tctrl, tempval);
1445 /* Enable VLAN tag extraction */
1446 tempval = gfar_read(&priv->regs->rctrl);
1447 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
1448 gfar_write(&priv->regs->rctrl, tempval);
1450 /* Disable VLAN tag insertion */
1451 tempval = gfar_read(&priv->regs->tctrl);
1452 tempval &= ~TCTRL_VLINS;
1453 gfar_write(&priv->regs->tctrl, tempval);
1455 /* Disable VLAN tag extraction */
1456 tempval = gfar_read(&priv->regs->rctrl);
1457 tempval &= ~RCTRL_VLEX;
1458 /* If parse is no longer required, then disable parser */
1459 if (tempval & RCTRL_REQ_PARSER)
1460 tempval |= RCTRL_PRSDEP_INIT;
1462 tempval &= ~RCTRL_PRSDEP_INIT;
1463 gfar_write(&priv->regs->rctrl, tempval);
1466 gfar_change_mtu(dev, dev->mtu);
1468 spin_unlock_irqrestore(&priv->rxlock, flags);
1471 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1473 int tempsize, tempval;
1474 struct gfar_private *priv = netdev_priv(dev);
1475 int oldsize = priv->rx_buffer_size;
1476 int frame_size = new_mtu + ETH_HLEN;
1479 frame_size += VLAN_HLEN;
1481 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1482 if (netif_msg_drv(priv))
1483 printk(KERN_ERR "%s: Invalid MTU setting\n",
1488 if (gfar_uses_fcb(priv))
1489 frame_size += GMAC_FCB_LEN;
1491 frame_size += priv->padding;
1494 (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1495 INCREMENTAL_BUFFER_SIZE;
1497 /* Only stop and start the controller if it isn't already
1498 * stopped, and we changed something */
1499 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1502 priv->rx_buffer_size = tempsize;
1506 gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1507 gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1509 /* If the mtu is larger than the max size for standard
1510 * ethernet frames (ie, a jumbo frame), then set maccfg2
1511 * to allow huge frames, and to check the length */
1512 tempval = gfar_read(&priv->regs->maccfg2);
1514 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1515 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1517 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1519 gfar_write(&priv->regs->maccfg2, tempval);
1521 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1527 /* gfar_reset_task gets scheduled when a packet has not been
1528 * transmitted after a set amount of time.
1529 * For now, assume that clearing out all the structures, and
1530 * starting over will fix the problem.
1532 static void gfar_reset_task(struct work_struct *work)
1534 struct gfar_private *priv = container_of(work, struct gfar_private,
1536 struct net_device *dev = priv->ndev;
1538 if (dev->flags & IFF_UP) {
1539 netif_stop_queue(dev);
1542 netif_start_queue(dev);
1545 netif_tx_schedule_all(dev);
1548 static void gfar_timeout(struct net_device *dev)
1550 struct gfar_private *priv = netdev_priv(dev);
1552 dev->stats.tx_errors++;
1553 schedule_work(&priv->reset_task);
1556 /* Interrupt Handler for Transmit complete */
1557 static int gfar_clean_tx_ring(struct net_device *dev)
1559 struct gfar_private *priv = netdev_priv(dev);
1561 struct txbd8 *lbdp = NULL;
1562 struct txbd8 *base = priv->tx_bd_base;
1563 struct sk_buff *skb;
1565 int tx_ring_size = priv->tx_ring_size;
1571 bdp = priv->dirty_tx;
1572 skb_dirtytx = priv->skb_dirtytx;
1574 while ((skb = priv->tx_skbuff[skb_dirtytx])) {
1575 frags = skb_shinfo(skb)->nr_frags;
1576 lbdp = skip_txbd(bdp, frags, base, tx_ring_size);
1578 lstatus = lbdp->lstatus;
1580 /* Only clean completed frames */
1581 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
1582 (lstatus & BD_LENGTH_MASK))
1585 dma_unmap_single(&priv->ofdev->dev,
1590 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1591 bdp = next_txbd(bdp, base, tx_ring_size);
1593 for (i = 0; i < frags; i++) {
1594 dma_unmap_page(&priv->ofdev->dev,
1598 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1599 bdp = next_txbd(bdp, base, tx_ring_size);
1603 * If there's room in the queue (limit it to rx_buffer_size)
1604 * we add this skb back into the pool, if it's the right size
1606 if (skb_queue_len(&priv->rx_recycle) < priv->rx_ring_size &&
1607 skb_recycle_check(skb, priv->rx_buffer_size +
1609 __skb_queue_head(&priv->rx_recycle, skb);
1611 dev_kfree_skb_any(skb);
1613 priv->tx_skbuff[skb_dirtytx] = NULL;
1615 skb_dirtytx = (skb_dirtytx + 1) &
1616 TX_RING_MOD_MASK(tx_ring_size);
1619 priv->num_txbdfree += frags + 1;
1622 /* If we freed a buffer, we can restart transmission, if necessary */
1623 if (netif_queue_stopped(dev) && priv->num_txbdfree)
1624 netif_wake_queue(dev);
1626 /* Update dirty indicators */
1627 priv->skb_dirtytx = skb_dirtytx;
1628 priv->dirty_tx = bdp;
1630 dev->stats.tx_packets += howmany;
1635 static void gfar_schedule_cleanup(struct net_device *dev)
1637 struct gfar_private *priv = netdev_priv(dev);
1638 unsigned long flags;
1640 spin_lock_irqsave(&priv->txlock, flags);
1641 spin_lock(&priv->rxlock);
1643 if (napi_schedule_prep(&priv->napi)) {
1644 gfar_write(&priv->regs->imask, IMASK_RTX_DISABLED);
1645 __napi_schedule(&priv->napi);
1648 * Clear IEVENT, so interrupts aren't called again
1649 * because of the packets that have already arrived.
1651 gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1654 spin_unlock(&priv->rxlock);
1655 spin_unlock_irqrestore(&priv->txlock, flags);
1658 /* Interrupt Handler for Transmit complete */
1659 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1661 gfar_schedule_cleanup((struct net_device *)dev_id);
1665 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
1666 struct sk_buff *skb)
1668 struct gfar_private *priv = netdev_priv(dev);
1671 bdp->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
1672 priv->rx_buffer_size, DMA_FROM_DEVICE);
1674 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
1676 if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1)
1677 lstatus |= BD_LFLAG(RXBD_WRAP);
1681 bdp->lstatus = lstatus;
1685 struct sk_buff * gfar_new_skb(struct net_device *dev)
1687 unsigned int alignamount;
1688 struct gfar_private *priv = netdev_priv(dev);
1689 struct sk_buff *skb = NULL;
1691 skb = __skb_dequeue(&priv->rx_recycle);
1693 skb = netdev_alloc_skb(dev,
1694 priv->rx_buffer_size + RXBUF_ALIGNMENT);
1699 alignamount = RXBUF_ALIGNMENT -
1700 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
1702 /* We need the data buffer to be aligned properly. We will reserve
1703 * as many bytes as needed to align the data properly
1705 skb_reserve(skb, alignamount);
1710 static inline void count_errors(unsigned short status, struct net_device *dev)
1712 struct gfar_private *priv = netdev_priv(dev);
1713 struct net_device_stats *stats = &dev->stats;
1714 struct gfar_extra_stats *estats = &priv->extra_stats;
1716 /* If the packet was truncated, none of the other errors
1718 if (status & RXBD_TRUNCATED) {
1719 stats->rx_length_errors++;
1725 /* Count the errors, if there were any */
1726 if (status & (RXBD_LARGE | RXBD_SHORT)) {
1727 stats->rx_length_errors++;
1729 if (status & RXBD_LARGE)
1734 if (status & RXBD_NONOCTET) {
1735 stats->rx_frame_errors++;
1736 estats->rx_nonoctet++;
1738 if (status & RXBD_CRCERR) {
1739 estats->rx_crcerr++;
1740 stats->rx_crc_errors++;
1742 if (status & RXBD_OVERRUN) {
1743 estats->rx_overrun++;
1744 stats->rx_crc_errors++;
1748 irqreturn_t gfar_receive(int irq, void *dev_id)
1750 gfar_schedule_cleanup((struct net_device *)dev_id);
1754 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1756 /* If valid headers were found, and valid sums
1757 * were verified, then we tell the kernel that no
1758 * checksumming is necessary. Otherwise, it is */
1759 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1760 skb->ip_summed = CHECKSUM_UNNECESSARY;
1762 skb->ip_summed = CHECKSUM_NONE;
1766 /* gfar_process_frame() -- handle one incoming packet if skb
1768 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1771 struct gfar_private *priv = netdev_priv(dev);
1772 struct rxfcb *fcb = NULL;
1776 /* fcb is at the beginning if exists */
1777 fcb = (struct rxfcb *)skb->data;
1779 /* Remove the FCB from the skb */
1780 /* Remove the padded bytes, if there are any */
1782 skb_pull(skb, amount_pull);
1784 if (priv->rx_csum_enable)
1785 gfar_rx_checksum(skb, fcb);
1787 /* Tell the skb what kind of packet this is */
1788 skb->protocol = eth_type_trans(skb, dev);
1790 /* Send the packet up the stack */
1791 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
1792 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
1794 ret = netif_receive_skb(skb);
1796 if (NET_RX_DROP == ret)
1797 priv->extra_stats.kernel_dropped++;
1802 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1803 * until the budget/quota has been reached. Returns the number
1806 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1808 struct rxbd8 *bdp, *base;
1809 struct sk_buff *skb;
1813 struct gfar_private *priv = netdev_priv(dev);
1815 /* Get the first full descriptor */
1817 base = priv->rx_bd_base;
1819 amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0) +
1822 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1823 struct sk_buff *newskb;
1826 /* Add another skb for the future */
1827 newskb = gfar_new_skb(dev);
1829 skb = priv->rx_skbuff[priv->skb_currx];
1831 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
1832 priv->rx_buffer_size, DMA_FROM_DEVICE);
1834 /* We drop the frame if we failed to allocate a new buffer */
1835 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
1836 bdp->status & RXBD_ERR)) {
1837 count_errors(bdp->status, dev);
1839 if (unlikely(!newskb))
1843 * We need to reset ->data to what it
1844 * was before gfar_new_skb() re-aligned
1845 * it to an RXBUF_ALIGNMENT boundary
1846 * before we put the skb back on the
1849 skb->data = skb->head + NET_SKB_PAD;
1850 __skb_queue_head(&priv->rx_recycle, skb);
1853 /* Increment the number of packets */
1854 dev->stats.rx_packets++;
1858 pkt_len = bdp->length - ETH_FCS_LEN;
1859 /* Remove the FCS from the packet length */
1860 skb_put(skb, pkt_len);
1861 dev->stats.rx_bytes += pkt_len;
1863 if (in_irq() || irqs_disabled())
1864 printk("Interrupt problem!\n");
1865 gfar_process_frame(dev, skb, amount_pull);
1868 if (netif_msg_rx_err(priv))
1870 "%s: Missing skb!\n", dev->name);
1871 dev->stats.rx_dropped++;
1872 priv->extra_stats.rx_skbmissing++;
1877 priv->rx_skbuff[priv->skb_currx] = newskb;
1879 /* Setup the new bdp */
1880 gfar_new_rxbdp(dev, bdp, newskb);
1882 /* Update to the next pointer */
1883 bdp = next_bd(bdp, base, priv->rx_ring_size);
1885 /* update to point at the next skb */
1887 (priv->skb_currx + 1) &
1888 RX_RING_MOD_MASK(priv->rx_ring_size);
1891 /* Update the current rxbd pointer to be the next one */
1897 static int gfar_poll(struct napi_struct *napi, int budget)
1899 struct gfar_private *priv = container_of(napi, struct gfar_private, napi);
1900 struct net_device *dev = priv->ndev;
1903 unsigned long flags;
1905 /* Clear IEVENT, so interrupts aren't called again
1906 * because of the packets that have already arrived */
1907 gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1909 /* If we fail to get the lock, don't bother with the TX BDs */
1910 if (spin_trylock_irqsave(&priv->txlock, flags)) {
1911 tx_cleaned = gfar_clean_tx_ring(dev);
1912 spin_unlock_irqrestore(&priv->txlock, flags);
1915 rx_cleaned = gfar_clean_rx_ring(dev, budget);
1920 if (rx_cleaned < budget) {
1921 napi_complete(napi);
1923 /* Clear the halt bit in RSTAT */
1924 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1926 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1928 /* If we are coalescing interrupts, update the timer */
1929 /* Otherwise, clear it */
1930 if (likely(priv->rxcoalescing)) {
1931 gfar_write(&priv->regs->rxic, 0);
1932 gfar_write(&priv->regs->rxic, priv->rxic);
1934 if (likely(priv->txcoalescing)) {
1935 gfar_write(&priv->regs->txic, 0);
1936 gfar_write(&priv->regs->txic, priv->txic);
1943 #ifdef CONFIG_NET_POLL_CONTROLLER
1945 * Polling 'interrupt' - used by things like netconsole to send skbs
1946 * without having to re-enable interrupts. It's not called while
1947 * the interrupt routine is executing.
1949 static void gfar_netpoll(struct net_device *dev)
1951 struct gfar_private *priv = netdev_priv(dev);
1953 /* If the device has multiple interrupts, run tx/rx */
1954 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1955 disable_irq(priv->interruptTransmit);
1956 disable_irq(priv->interruptReceive);
1957 disable_irq(priv->interruptError);
1958 gfar_interrupt(priv->interruptTransmit, dev);
1959 enable_irq(priv->interruptError);
1960 enable_irq(priv->interruptReceive);
1961 enable_irq(priv->interruptTransmit);
1963 disable_irq(priv->interruptTransmit);
1964 gfar_interrupt(priv->interruptTransmit, dev);
1965 enable_irq(priv->interruptTransmit);
1970 /* The interrupt handler for devices with one interrupt */
1971 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
1973 struct net_device *dev = dev_id;
1974 struct gfar_private *priv = netdev_priv(dev);
1976 /* Save ievent for future reference */
1977 u32 events = gfar_read(&priv->regs->ievent);
1979 /* Check for reception */
1980 if (events & IEVENT_RX_MASK)
1981 gfar_receive(irq, dev_id);
1983 /* Check for transmit completion */
1984 if (events & IEVENT_TX_MASK)
1985 gfar_transmit(irq, dev_id);
1987 /* Check for errors */
1988 if (events & IEVENT_ERR_MASK)
1989 gfar_error(irq, dev_id);
1994 /* Called every time the controller might need to be made
1995 * aware of new link state. The PHY code conveys this
1996 * information through variables in the phydev structure, and this
1997 * function converts those variables into the appropriate
1998 * register values, and can bring down the device if needed.
2000 static void adjust_link(struct net_device *dev)
2002 struct gfar_private *priv = netdev_priv(dev);
2003 struct gfar __iomem *regs = priv->regs;
2004 unsigned long flags;
2005 struct phy_device *phydev = priv->phydev;
2008 spin_lock_irqsave(&priv->txlock, flags);
2010 u32 tempval = gfar_read(®s->maccfg2);
2011 u32 ecntrl = gfar_read(®s->ecntrl);
2013 /* Now we make sure that we can be in full duplex mode.
2014 * If not, we operate in half-duplex mode. */
2015 if (phydev->duplex != priv->oldduplex) {
2017 if (!(phydev->duplex))
2018 tempval &= ~(MACCFG2_FULL_DUPLEX);
2020 tempval |= MACCFG2_FULL_DUPLEX;
2022 priv->oldduplex = phydev->duplex;
2025 if (phydev->speed != priv->oldspeed) {
2027 switch (phydev->speed) {
2030 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2032 ecntrl &= ~(ECNTRL_R100);
2037 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
2039 /* Reduced mode distinguishes
2040 * between 10 and 100 */
2041 if (phydev->speed == SPEED_100)
2042 ecntrl |= ECNTRL_R100;
2044 ecntrl &= ~(ECNTRL_R100);
2047 if (netif_msg_link(priv))
2049 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
2050 dev->name, phydev->speed);
2054 priv->oldspeed = phydev->speed;
2057 gfar_write(®s->maccfg2, tempval);
2058 gfar_write(®s->ecntrl, ecntrl);
2060 if (!priv->oldlink) {
2064 } else if (priv->oldlink) {
2068 priv->oldduplex = -1;
2071 if (new_state && netif_msg_link(priv))
2072 phy_print_status(phydev);
2074 spin_unlock_irqrestore(&priv->txlock, flags);
2077 /* Update the hash table based on the current list of multicast
2078 * addresses we subscribe to. Also, change the promiscuity of
2079 * the device based on the flags (this function is called
2080 * whenever dev->flags is changed */
2081 static void gfar_set_multi(struct net_device *dev)
2083 struct dev_mc_list *mc_ptr;
2084 struct gfar_private *priv = netdev_priv(dev);
2085 struct gfar __iomem *regs = priv->regs;
2088 if(dev->flags & IFF_PROMISC) {
2089 /* Set RCTRL to PROM */
2090 tempval = gfar_read(®s->rctrl);
2091 tempval |= RCTRL_PROM;
2092 gfar_write(®s->rctrl, tempval);
2094 /* Set RCTRL to not PROM */
2095 tempval = gfar_read(®s->rctrl);
2096 tempval &= ~(RCTRL_PROM);
2097 gfar_write(®s->rctrl, tempval);
2100 if(dev->flags & IFF_ALLMULTI) {
2101 /* Set the hash to rx all multicast frames */
2102 gfar_write(®s->igaddr0, 0xffffffff);
2103 gfar_write(®s->igaddr1, 0xffffffff);
2104 gfar_write(®s->igaddr2, 0xffffffff);
2105 gfar_write(®s->igaddr3, 0xffffffff);
2106 gfar_write(®s->igaddr4, 0xffffffff);
2107 gfar_write(®s->igaddr5, 0xffffffff);
2108 gfar_write(®s->igaddr6, 0xffffffff);
2109 gfar_write(®s->igaddr7, 0xffffffff);
2110 gfar_write(®s->gaddr0, 0xffffffff);
2111 gfar_write(®s->gaddr1, 0xffffffff);
2112 gfar_write(®s->gaddr2, 0xffffffff);
2113 gfar_write(®s->gaddr3, 0xffffffff);
2114 gfar_write(®s->gaddr4, 0xffffffff);
2115 gfar_write(®s->gaddr5, 0xffffffff);
2116 gfar_write(®s->gaddr6, 0xffffffff);
2117 gfar_write(®s->gaddr7, 0xffffffff);
2122 /* zero out the hash */
2123 gfar_write(®s->igaddr0, 0x0);
2124 gfar_write(®s->igaddr1, 0x0);
2125 gfar_write(®s->igaddr2, 0x0);
2126 gfar_write(®s->igaddr3, 0x0);
2127 gfar_write(®s->igaddr4, 0x0);
2128 gfar_write(®s->igaddr5, 0x0);
2129 gfar_write(®s->igaddr6, 0x0);
2130 gfar_write(®s->igaddr7, 0x0);
2131 gfar_write(®s->gaddr0, 0x0);
2132 gfar_write(®s->gaddr1, 0x0);
2133 gfar_write(®s->gaddr2, 0x0);
2134 gfar_write(®s->gaddr3, 0x0);
2135 gfar_write(®s->gaddr4, 0x0);
2136 gfar_write(®s->gaddr5, 0x0);
2137 gfar_write(®s->gaddr6, 0x0);
2138 gfar_write(®s->gaddr7, 0x0);
2140 /* If we have extended hash tables, we need to
2141 * clear the exact match registers to prepare for
2143 if (priv->extended_hash) {
2144 em_num = GFAR_EM_NUM + 1;
2145 gfar_clear_exact_match(dev);
2152 if(dev->mc_count == 0)
2155 /* Parse the list, and set the appropriate bits */
2156 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
2158 gfar_set_mac_for_addr(dev, idx,
2162 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
2170 /* Clears each of the exact match registers to zero, so they
2171 * don't interfere with normal reception */
2172 static void gfar_clear_exact_match(struct net_device *dev)
2175 u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
2177 for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
2178 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
2181 /* Set the appropriate hash bit for the given addr */
2182 /* The algorithm works like so:
2183 * 1) Take the Destination Address (ie the multicast address), and
2184 * do a CRC on it (little endian), and reverse the bits of the
2186 * 2) Use the 8 most significant bits as a hash into a 256-entry
2187 * table. The table is controlled through 8 32-bit registers:
2188 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
2189 * gaddr7. This means that the 3 most significant bits in the
2190 * hash index which gaddr register to use, and the 5 other bits
2191 * indicate which bit (assuming an IBM numbering scheme, which
2192 * for PowerPC (tm) is usually the case) in the register holds
2194 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
2197 struct gfar_private *priv = netdev_priv(dev);
2198 u32 result = ether_crc(MAC_ADDR_LEN, addr);
2199 int width = priv->hash_width;
2200 u8 whichbit = (result >> (32 - width)) & 0x1f;
2201 u8 whichreg = result >> (32 - width + 5);
2202 u32 value = (1 << (31-whichbit));
2204 tempval = gfar_read(priv->hash_regs[whichreg]);
2206 gfar_write(priv->hash_regs[whichreg], tempval);
2212 /* There are multiple MAC Address register pairs on some controllers
2213 * This function sets the numth pair to a given address
2215 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
2217 struct gfar_private *priv = netdev_priv(dev);
2219 char tmpbuf[MAC_ADDR_LEN];
2221 u32 __iomem *macptr = &priv->regs->macstnaddr1;
2225 /* Now copy it into the mac registers backwards, cuz */
2226 /* little endian is silly */
2227 for (idx = 0; idx < MAC_ADDR_LEN; idx++)
2228 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
2230 gfar_write(macptr, *((u32 *) (tmpbuf)));
2232 tempval = *((u32 *) (tmpbuf + 4));
2234 gfar_write(macptr+1, tempval);
2237 /* GFAR error interrupt handler */
2238 static irqreturn_t gfar_error(int irq, void *dev_id)
2240 struct net_device *dev = dev_id;
2241 struct gfar_private *priv = netdev_priv(dev);
2243 /* Save ievent for future reference */
2244 u32 events = gfar_read(&priv->regs->ievent);
2247 gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK);
2249 /* Magic Packet is not an error. */
2250 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2251 (events & IEVENT_MAG))
2252 events &= ~IEVENT_MAG;
2255 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2256 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2257 dev->name, events, gfar_read(&priv->regs->imask));
2259 /* Update the error counters */
2260 if (events & IEVENT_TXE) {
2261 dev->stats.tx_errors++;
2263 if (events & IEVENT_LC)
2264 dev->stats.tx_window_errors++;
2265 if (events & IEVENT_CRL)
2266 dev->stats.tx_aborted_errors++;
2267 if (events & IEVENT_XFUN) {
2268 if (netif_msg_tx_err(priv))
2269 printk(KERN_DEBUG "%s: TX FIFO underrun, "
2270 "packet dropped.\n", dev->name);
2271 dev->stats.tx_dropped++;
2272 priv->extra_stats.tx_underrun++;
2274 /* Reactivate the Tx Queues */
2275 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
2277 if (netif_msg_tx_err(priv))
2278 printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
2280 if (events & IEVENT_BSY) {
2281 dev->stats.rx_errors++;
2282 priv->extra_stats.rx_bsy++;
2284 gfar_receive(irq, dev_id);
2286 if (netif_msg_rx_err(priv))
2287 printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
2288 dev->name, gfar_read(&priv->regs->rstat));
2290 if (events & IEVENT_BABR) {
2291 dev->stats.rx_errors++;
2292 priv->extra_stats.rx_babr++;
2294 if (netif_msg_rx_err(priv))
2295 printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
2297 if (events & IEVENT_EBERR) {
2298 priv->extra_stats.eberr++;
2299 if (netif_msg_rx_err(priv))
2300 printk(KERN_DEBUG "%s: bus error\n", dev->name);
2302 if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
2303 printk(KERN_DEBUG "%s: control frame\n", dev->name);
2305 if (events & IEVENT_BABT) {
2306 priv->extra_stats.tx_babt++;
2307 if (netif_msg_tx_err(priv))
2308 printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
2313 /* work with hotplug and coldplug */
2314 MODULE_ALIAS("platform:fsl-gianfar");
2316 static struct of_device_id gfar_match[] =
2320 .compatible = "gianfar",
2325 /* Structure for a device driver */
2326 static struct of_platform_driver gfar_driver = {
2327 .name = "fsl-gianfar",
2328 .match_table = gfar_match,
2330 .probe = gfar_probe,
2331 .remove = gfar_remove,
2332 .suspend = gfar_suspend,
2333 .resume = gfar_resume,
2336 static int __init gfar_init(void)
2338 return of_register_platform_driver(&gfar_driver);
2341 static void __exit gfar_exit(void)
2343 of_unregister_platform_driver(&gfar_driver);
2346 module_init(gfar_init);
2347 module_exit(gfar_exit);