2 * drivers/net/gianfar.c
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
10 * Maintainer: Kumar Gala
11 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
13 * Copyright 2002-2009 Freescale Semiconductor, Inc.
14 * Copyright 2007 MontaVista Software, Inc.
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
21 * Gianfar: AKA Lambda Draconis, "Dragon"
29 * The driver is initialized through of_device. Configuration information
30 * is therefore conveyed through an OF-style device tree.
32 * The Gianfar Ethernet Controller uses a ring of buffer
33 * descriptors. The beginning is indicated by a register
34 * pointing to the physical address of the start of the ring.
35 * The end is determined by a "wrap" bit being set in the
36 * last descriptor of the ring.
38 * When a packet is received, the RXF bit in the
39 * IEVENT register is set, triggering an interrupt when the
40 * corresponding bit in the IMASK register is also set (if
41 * interrupt coalescing is active, then the interrupt may not
42 * happen immediately, but will wait until either a set number
43 * of frames or amount of time have passed). In NAPI, the
44 * interrupt handler will signal there is work to be done, and
45 * exit. This method will start at the last known empty
46 * descriptor, and process every subsequent descriptor until there
47 * are none left with data (NAPI will stop after a set number of
48 * packets to give time to other tasks, but will eventually
49 * process all the packets). The data arrives inside a
50 * pre-allocated skb, and so after the skb is passed up to the
51 * stack, a new skb must be allocated, and the address field in
52 * the buffer descriptor must be updated to indicate this new
55 * When the kernel requests that a packet be transmitted, the
56 * driver starts where it left off last time, and points the
57 * descriptor at the buffer which was passed in. The driver
58 * then informs the DMA engine that there are packets ready to
59 * be transmitted. Once the controller is finished transmitting
60 * the packet, an interrupt may be triggered (under the same
61 * conditions as for reception, but depending on the TXF bit).
62 * The driver then cleans up the buffer.
65 #include <linux/kernel.h>
66 #include <linux/string.h>
67 #include <linux/errno.h>
68 #include <linux/unistd.h>
69 #include <linux/slab.h>
70 #include <linux/interrupt.h>
71 #include <linux/init.h>
72 #include <linux/delay.h>
73 #include <linux/netdevice.h>
74 #include <linux/etherdevice.h>
75 #include <linux/skbuff.h>
76 #include <linux/if_vlan.h>
77 #include <linux/spinlock.h>
79 #include <linux/of_mdio.h>
80 #include <linux/of_platform.h>
82 #include <linux/tcp.h>
83 #include <linux/udp.h>
85 #include <linux/net_tstamp.h>
90 #include <asm/uaccess.h>
91 #include <linux/module.h>
92 #include <linux/dma-mapping.h>
93 #include <linux/crc32.h>
94 #include <linux/mii.h>
95 #include <linux/phy.h>
96 #include <linux/phy_fixed.h>
100 #include "fsl_pq_mdio.h"
102 #define TX_TIMEOUT (1*HZ)
103 #undef BRIEF_GFAR_ERRORS
104 #undef VERBOSE_GFAR_ERRORS
106 const char gfar_driver_name[] = "Gianfar Ethernet";
107 const char gfar_driver_version[] = "1.3";
109 static int gfar_enet_open(struct net_device *dev);
110 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
111 static void gfar_reset_task(struct work_struct *work);
112 static void gfar_timeout(struct net_device *dev);
113 static int gfar_close(struct net_device *dev);
114 struct sk_buff *gfar_new_skb(struct net_device *dev);
115 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
116 struct sk_buff *skb);
117 static int gfar_set_mac_address(struct net_device *dev);
118 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
119 static irqreturn_t gfar_error(int irq, void *dev_id);
120 static irqreturn_t gfar_transmit(int irq, void *dev_id);
121 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
122 static void adjust_link(struct net_device *dev);
123 static void init_registers(struct net_device *dev);
124 static int init_phy(struct net_device *dev);
125 static int gfar_probe(struct platform_device *ofdev,
126 const struct of_device_id *match);
127 static int gfar_remove(struct platform_device *ofdev);
128 static void free_skb_resources(struct gfar_private *priv);
129 static void gfar_set_multi(struct net_device *dev);
130 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
131 static void gfar_configure_serdes(struct net_device *dev);
132 static int gfar_poll(struct napi_struct *napi, int budget);
133 #ifdef CONFIG_NET_POLL_CONTROLLER
134 static void gfar_netpoll(struct net_device *dev);
136 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
137 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
138 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
140 static void gfar_vlan_rx_register(struct net_device *netdev,
141 struct vlan_group *grp);
142 void gfar_halt(struct net_device *dev);
143 static void gfar_halt_nodisable(struct net_device *dev);
144 void gfar_start(struct net_device *dev);
145 static void gfar_clear_exact_match(struct net_device *dev);
146 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
148 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
150 MODULE_AUTHOR("Freescale Semiconductor, Inc");
151 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
152 MODULE_LICENSE("GPL");
154 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
161 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
162 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
163 lstatus |= BD_LFLAG(RXBD_WRAP);
167 bdp->lstatus = lstatus;
170 static int gfar_init_bds(struct net_device *ndev)
172 struct gfar_private *priv = netdev_priv(ndev);
173 struct gfar_priv_tx_q *tx_queue = NULL;
174 struct gfar_priv_rx_q *rx_queue = NULL;
179 for (i = 0; i < priv->num_tx_queues; i++) {
180 tx_queue = priv->tx_queue[i];
181 /* Initialize some variables in our dev structure */
182 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
183 tx_queue->dirty_tx = tx_queue->tx_bd_base;
184 tx_queue->cur_tx = tx_queue->tx_bd_base;
185 tx_queue->skb_curtx = 0;
186 tx_queue->skb_dirtytx = 0;
188 /* Initialize Transmit Descriptor Ring */
189 txbdp = tx_queue->tx_bd_base;
190 for (j = 0; j < tx_queue->tx_ring_size; j++) {
196 /* Set the last descriptor in the ring to indicate wrap */
198 txbdp->status |= TXBD_WRAP;
201 for (i = 0; i < priv->num_rx_queues; i++) {
202 rx_queue = priv->rx_queue[i];
203 rx_queue->cur_rx = rx_queue->rx_bd_base;
204 rx_queue->skb_currx = 0;
205 rxbdp = rx_queue->rx_bd_base;
207 for (j = 0; j < rx_queue->rx_ring_size; j++) {
208 struct sk_buff *skb = rx_queue->rx_skbuff[j];
211 gfar_init_rxbdp(rx_queue, rxbdp,
214 skb = gfar_new_skb(ndev);
216 pr_err("%s: Can't allocate RX buffers\n",
218 goto err_rxalloc_fail;
220 rx_queue->rx_skbuff[j] = skb;
222 gfar_new_rxbdp(rx_queue, rxbdp, skb);
233 free_skb_resources(priv);
237 static int gfar_alloc_skb_resources(struct net_device *ndev)
242 struct gfar_private *priv = netdev_priv(ndev);
243 struct device *dev = &priv->ofdev->dev;
244 struct gfar_priv_tx_q *tx_queue = NULL;
245 struct gfar_priv_rx_q *rx_queue = NULL;
247 priv->total_tx_ring_size = 0;
248 for (i = 0; i < priv->num_tx_queues; i++)
249 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
251 priv->total_rx_ring_size = 0;
252 for (i = 0; i < priv->num_rx_queues; i++)
253 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
255 /* Allocate memory for the buffer descriptors */
256 vaddr = dma_alloc_coherent(dev,
257 sizeof(struct txbd8) * priv->total_tx_ring_size +
258 sizeof(struct rxbd8) * priv->total_rx_ring_size,
261 if (netif_msg_ifup(priv))
262 pr_err("%s: Could not allocate buffer descriptors!\n",
267 for (i = 0; i < priv->num_tx_queues; i++) {
268 tx_queue = priv->tx_queue[i];
269 tx_queue->tx_bd_base = (struct txbd8 *) vaddr;
270 tx_queue->tx_bd_dma_base = addr;
271 tx_queue->dev = ndev;
272 /* enet DMA only understands physical addresses */
273 addr += sizeof(struct txbd8) *tx_queue->tx_ring_size;
274 vaddr += sizeof(struct txbd8) *tx_queue->tx_ring_size;
277 /* Start the rx descriptor ring where the tx ring leaves off */
278 for (i = 0; i < priv->num_rx_queues; i++) {
279 rx_queue = priv->rx_queue[i];
280 rx_queue->rx_bd_base = (struct rxbd8 *) vaddr;
281 rx_queue->rx_bd_dma_base = addr;
282 rx_queue->dev = ndev;
283 addr += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
284 vaddr += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
287 /* Setup the skbuff rings */
288 for (i = 0; i < priv->num_tx_queues; i++) {
289 tx_queue = priv->tx_queue[i];
290 tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) *
291 tx_queue->tx_ring_size, GFP_KERNEL);
292 if (!tx_queue->tx_skbuff) {
293 if (netif_msg_ifup(priv))
294 pr_err("%s: Could not allocate tx_skbuff\n",
299 for (k = 0; k < tx_queue->tx_ring_size; k++)
300 tx_queue->tx_skbuff[k] = NULL;
303 for (i = 0; i < priv->num_rx_queues; i++) {
304 rx_queue = priv->rx_queue[i];
305 rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) *
306 rx_queue->rx_ring_size, GFP_KERNEL);
308 if (!rx_queue->rx_skbuff) {
309 if (netif_msg_ifup(priv))
310 pr_err("%s: Could not allocate rx_skbuff\n",
315 for (j = 0; j < rx_queue->rx_ring_size; j++)
316 rx_queue->rx_skbuff[j] = NULL;
319 if (gfar_init_bds(ndev))
325 free_skb_resources(priv);
329 static void gfar_init_tx_rx_base(struct gfar_private *priv)
331 struct gfar __iomem *regs = priv->gfargrp[0].regs;
335 baddr = ®s->tbase0;
336 for(i = 0; i < priv->num_tx_queues; i++) {
337 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
341 baddr = ®s->rbase0;
342 for(i = 0; i < priv->num_rx_queues; i++) {
343 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
348 static void gfar_init_mac(struct net_device *ndev)
350 struct gfar_private *priv = netdev_priv(ndev);
351 struct gfar __iomem *regs = priv->gfargrp[0].regs;
356 /* write the tx/rx base registers */
357 gfar_init_tx_rx_base(priv);
359 /* Configure the coalescing support */
360 gfar_configure_coalescing(priv, 0xFF, 0xFF);
362 if (priv->rx_filer_enable) {
363 rctrl |= RCTRL_FILREN;
364 /* Program the RIR0 reg with the required distribution */
365 gfar_write(®s->rir0, DEFAULT_RIR0);
368 if (priv->rx_csum_enable)
369 rctrl |= RCTRL_CHECKSUMMING;
371 if (priv->extended_hash) {
372 rctrl |= RCTRL_EXTHASH;
374 gfar_clear_exact_match(ndev);
379 rctrl &= ~RCTRL_PAL_MASK;
380 rctrl |= RCTRL_PADDING(priv->padding);
383 /* Insert receive time stamps into padding alignment bytes */
384 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
385 rctrl &= ~RCTRL_PAL_MASK;
386 rctrl |= RCTRL_PADDING(8);
390 /* Enable HW time stamping if requested from user space */
391 if (priv->hwts_rx_en)
392 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
394 /* keep vlan related bits if it's enabled */
396 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
397 tctrl |= TCTRL_VLINS;
400 /* Init rctrl based on our settings */
401 gfar_write(®s->rctrl, rctrl);
403 if (ndev->features & NETIF_F_IP_CSUM)
404 tctrl |= TCTRL_INIT_CSUM;
406 tctrl |= TCTRL_TXSCHED_PRIO;
408 gfar_write(®s->tctrl, tctrl);
410 /* Set the extraction length and index */
411 attrs = ATTRELI_EL(priv->rx_stash_size) |
412 ATTRELI_EI(priv->rx_stash_index);
414 gfar_write(®s->attreli, attrs);
416 /* Start with defaults, and add stashing or locking
417 * depending on the approprate variables */
418 attrs = ATTR_INIT_SETTINGS;
420 if (priv->bd_stash_en)
421 attrs |= ATTR_BDSTASH;
423 if (priv->rx_stash_size != 0)
424 attrs |= ATTR_BUFSTASH;
426 gfar_write(®s->attr, attrs);
428 gfar_write(®s->fifo_tx_thr, priv->fifo_threshold);
429 gfar_write(®s->fifo_tx_starve, priv->fifo_starve);
430 gfar_write(®s->fifo_tx_starve_shutoff, priv->fifo_starve_off);
433 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
435 struct gfar_private *priv = netdev_priv(dev);
436 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
437 unsigned long tx_packets = 0, tx_bytes = 0;
440 for (i = 0; i < priv->num_rx_queues; i++) {
441 rx_packets += priv->rx_queue[i]->stats.rx_packets;
442 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
443 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
446 dev->stats.rx_packets = rx_packets;
447 dev->stats.rx_bytes = rx_bytes;
448 dev->stats.rx_dropped = rx_dropped;
450 for (i = 0; i < priv->num_tx_queues; i++) {
451 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
452 tx_packets += priv->tx_queue[i]->stats.tx_packets;
455 dev->stats.tx_bytes = tx_bytes;
456 dev->stats.tx_packets = tx_packets;
461 static const struct net_device_ops gfar_netdev_ops = {
462 .ndo_open = gfar_enet_open,
463 .ndo_start_xmit = gfar_start_xmit,
464 .ndo_stop = gfar_close,
465 .ndo_change_mtu = gfar_change_mtu,
466 .ndo_set_multicast_list = gfar_set_multi,
467 .ndo_tx_timeout = gfar_timeout,
468 .ndo_do_ioctl = gfar_ioctl,
469 .ndo_get_stats = gfar_get_stats,
470 .ndo_vlan_rx_register = gfar_vlan_rx_register,
471 .ndo_set_mac_address = eth_mac_addr,
472 .ndo_validate_addr = eth_validate_addr,
473 #ifdef CONFIG_NET_POLL_CONTROLLER
474 .ndo_poll_controller = gfar_netpoll,
478 unsigned int ftp_rqfpr[MAX_FILER_IDX + 1];
479 unsigned int ftp_rqfcr[MAX_FILER_IDX + 1];
481 void lock_rx_qs(struct gfar_private *priv)
485 for (i = 0; i < priv->num_rx_queues; i++)
486 spin_lock(&priv->rx_queue[i]->rxlock);
489 void lock_tx_qs(struct gfar_private *priv)
493 for (i = 0; i < priv->num_tx_queues; i++)
494 spin_lock(&priv->tx_queue[i]->txlock);
497 void unlock_rx_qs(struct gfar_private *priv)
501 for (i = 0; i < priv->num_rx_queues; i++)
502 spin_unlock(&priv->rx_queue[i]->rxlock);
505 void unlock_tx_qs(struct gfar_private *priv)
509 for (i = 0; i < priv->num_tx_queues; i++)
510 spin_unlock(&priv->tx_queue[i]->txlock);
513 /* Returns 1 if incoming frames use an FCB */
514 static inline int gfar_uses_fcb(struct gfar_private *priv)
516 return priv->vlgrp || priv->rx_csum_enable ||
517 (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER);
520 static void free_tx_pointers(struct gfar_private *priv)
524 for (i = 0; i < priv->num_tx_queues; i++)
525 kfree(priv->tx_queue[i]);
528 static void free_rx_pointers(struct gfar_private *priv)
532 for (i = 0; i < priv->num_rx_queues; i++)
533 kfree(priv->rx_queue[i]);
536 static void unmap_group_regs(struct gfar_private *priv)
540 for (i = 0; i < MAXGROUPS; i++)
541 if (priv->gfargrp[i].regs)
542 iounmap(priv->gfargrp[i].regs);
545 static void disable_napi(struct gfar_private *priv)
549 for (i = 0; i < priv->num_grps; i++)
550 napi_disable(&priv->gfargrp[i].napi);
553 static void enable_napi(struct gfar_private *priv)
557 for (i = 0; i < priv->num_grps; i++)
558 napi_enable(&priv->gfargrp[i].napi);
561 static int gfar_parse_group(struct device_node *np,
562 struct gfar_private *priv, const char *model)
566 priv->gfargrp[priv->num_grps].regs = of_iomap(np, 0);
567 if (!priv->gfargrp[priv->num_grps].regs)
570 priv->gfargrp[priv->num_grps].interruptTransmit =
571 irq_of_parse_and_map(np, 0);
573 /* If we aren't the FEC we have multiple interrupts */
574 if (model && strcasecmp(model, "FEC")) {
575 priv->gfargrp[priv->num_grps].interruptReceive =
576 irq_of_parse_and_map(np, 1);
577 priv->gfargrp[priv->num_grps].interruptError =
578 irq_of_parse_and_map(np,2);
579 if (priv->gfargrp[priv->num_grps].interruptTransmit == NO_IRQ ||
580 priv->gfargrp[priv->num_grps].interruptReceive == NO_IRQ ||
581 priv->gfargrp[priv->num_grps].interruptError == NO_IRQ)
585 priv->gfargrp[priv->num_grps].grp_id = priv->num_grps;
586 priv->gfargrp[priv->num_grps].priv = priv;
587 spin_lock_init(&priv->gfargrp[priv->num_grps].grplock);
588 if(priv->mode == MQ_MG_MODE) {
589 queue_mask = (u32 *)of_get_property(np,
590 "fsl,rx-bit-map", NULL);
591 priv->gfargrp[priv->num_grps].rx_bit_map =
592 queue_mask ? *queue_mask :(DEFAULT_MAPPING >> priv->num_grps);
593 queue_mask = (u32 *)of_get_property(np,
594 "fsl,tx-bit-map", NULL);
595 priv->gfargrp[priv->num_grps].tx_bit_map =
596 queue_mask ? *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
598 priv->gfargrp[priv->num_grps].rx_bit_map = 0xFF;
599 priv->gfargrp[priv->num_grps].tx_bit_map = 0xFF;
606 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
610 const void *mac_addr;
612 struct net_device *dev = NULL;
613 struct gfar_private *priv = NULL;
614 struct device_node *np = ofdev->dev.of_node;
615 struct device_node *child = NULL;
617 const u32 *stash_len;
618 const u32 *stash_idx;
619 unsigned int num_tx_qs, num_rx_qs;
620 u32 *tx_queues, *rx_queues;
622 if (!np || !of_device_is_available(np))
625 /* parse the num of tx and rx queues */
626 tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
627 num_tx_qs = tx_queues ? *tx_queues : 1;
629 if (num_tx_qs > MAX_TX_QS) {
630 printk(KERN_ERR "num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
631 num_tx_qs, MAX_TX_QS);
632 printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n");
636 rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
637 num_rx_qs = rx_queues ? *rx_queues : 1;
639 if (num_rx_qs > MAX_RX_QS) {
640 printk(KERN_ERR "num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
641 num_tx_qs, MAX_TX_QS);
642 printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n");
646 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
651 priv = netdev_priv(dev);
652 priv->node = ofdev->dev.of_node;
655 priv->num_tx_queues = num_tx_qs;
656 netif_set_real_num_rx_queues(dev, num_rx_qs);
657 priv->num_rx_queues = num_rx_qs;
658 priv->num_grps = 0x0;
660 model = of_get_property(np, "model", NULL);
662 for (i = 0; i < MAXGROUPS; i++)
663 priv->gfargrp[i].regs = NULL;
665 /* Parse and initialize group specific information */
666 if (of_device_is_compatible(np, "fsl,etsec2")) {
667 priv->mode = MQ_MG_MODE;
668 for_each_child_of_node(np, child) {
669 err = gfar_parse_group(child, priv, model);
674 priv->mode = SQ_SG_MODE;
675 err = gfar_parse_group(np, priv, model);
680 for (i = 0; i < priv->num_tx_queues; i++)
681 priv->tx_queue[i] = NULL;
682 for (i = 0; i < priv->num_rx_queues; i++)
683 priv->rx_queue[i] = NULL;
685 for (i = 0; i < priv->num_tx_queues; i++) {
686 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
688 if (!priv->tx_queue[i]) {
690 goto tx_alloc_failed;
692 priv->tx_queue[i]->tx_skbuff = NULL;
693 priv->tx_queue[i]->qindex = i;
694 priv->tx_queue[i]->dev = dev;
695 spin_lock_init(&(priv->tx_queue[i]->txlock));
698 for (i = 0; i < priv->num_rx_queues; i++) {
699 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
701 if (!priv->rx_queue[i]) {
703 goto rx_alloc_failed;
705 priv->rx_queue[i]->rx_skbuff = NULL;
706 priv->rx_queue[i]->qindex = i;
707 priv->rx_queue[i]->dev = dev;
708 spin_lock_init(&(priv->rx_queue[i]->rxlock));
712 stash = of_get_property(np, "bd-stash", NULL);
715 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
716 priv->bd_stash_en = 1;
719 stash_len = of_get_property(np, "rx-stash-len", NULL);
722 priv->rx_stash_size = *stash_len;
724 stash_idx = of_get_property(np, "rx-stash-idx", NULL);
727 priv->rx_stash_index = *stash_idx;
729 if (stash_len || stash_idx)
730 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
732 mac_addr = of_get_mac_address(np);
734 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
736 if (model && !strcasecmp(model, "TSEC"))
738 FSL_GIANFAR_DEV_HAS_GIGABIT |
739 FSL_GIANFAR_DEV_HAS_COALESCE |
740 FSL_GIANFAR_DEV_HAS_RMON |
741 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
742 if (model && !strcasecmp(model, "eTSEC"))
744 FSL_GIANFAR_DEV_HAS_GIGABIT |
745 FSL_GIANFAR_DEV_HAS_COALESCE |
746 FSL_GIANFAR_DEV_HAS_RMON |
747 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
748 FSL_GIANFAR_DEV_HAS_PADDING |
749 FSL_GIANFAR_DEV_HAS_CSUM |
750 FSL_GIANFAR_DEV_HAS_VLAN |
751 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
752 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
753 FSL_GIANFAR_DEV_HAS_TIMER;
755 ctype = of_get_property(np, "phy-connection-type", NULL);
757 /* We only care about rgmii-id. The rest are autodetected */
758 if (ctype && !strcmp(ctype, "rgmii-id"))
759 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
761 priv->interface = PHY_INTERFACE_MODE_MII;
763 if (of_get_property(np, "fsl,magic-packet", NULL))
764 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
766 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
768 /* Find the TBI PHY. If it's not there, we don't support SGMII */
769 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
774 free_rx_pointers(priv);
776 free_tx_pointers(priv);
778 unmap_group_regs(priv);
783 static int gfar_hwtstamp_ioctl(struct net_device *netdev,
784 struct ifreq *ifr, int cmd)
786 struct hwtstamp_config config;
787 struct gfar_private *priv = netdev_priv(netdev);
789 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
792 /* reserved for future extensions */
796 switch (config.tx_type) {
797 case HWTSTAMP_TX_OFF:
798 priv->hwts_tx_en = 0;
801 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
803 priv->hwts_tx_en = 1;
809 switch (config.rx_filter) {
810 case HWTSTAMP_FILTER_NONE:
811 if (priv->hwts_rx_en) {
813 priv->hwts_rx_en = 0;
814 startup_gfar(netdev);
818 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
820 if (!priv->hwts_rx_en) {
822 priv->hwts_rx_en = 1;
823 startup_gfar(netdev);
825 config.rx_filter = HWTSTAMP_FILTER_ALL;
829 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
833 /* Ioctl MII Interface */
834 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
836 struct gfar_private *priv = netdev_priv(dev);
838 if (!netif_running(dev))
841 if (cmd == SIOCSHWTSTAMP)
842 return gfar_hwtstamp_ioctl(dev, rq, cmd);
847 return phy_mii_ioctl(priv->phydev, rq, cmd);
850 static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
852 unsigned int new_bit_map = 0x0;
853 int mask = 0x1 << (max_qs - 1), i;
854 for (i = 0; i < max_qs; i++) {
856 new_bit_map = new_bit_map + (1 << i);
862 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
865 u32 rqfpr = FPR_FILER_MASK;
869 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
870 ftp_rqfpr[rqfar] = rqfpr;
871 ftp_rqfcr[rqfar] = rqfcr;
872 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
875 rqfcr = RQFCR_CMP_NOMATCH;
876 ftp_rqfpr[rqfar] = rqfpr;
877 ftp_rqfcr[rqfar] = rqfcr;
878 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
881 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
883 ftp_rqfcr[rqfar] = rqfcr;
884 ftp_rqfpr[rqfar] = rqfpr;
885 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
888 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
890 ftp_rqfcr[rqfar] = rqfcr;
891 ftp_rqfpr[rqfar] = rqfpr;
892 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
897 static void gfar_init_filer_table(struct gfar_private *priv)
900 u32 rqfar = MAX_FILER_IDX;
902 u32 rqfpr = FPR_FILER_MASK;
905 rqfcr = RQFCR_CMP_MATCH;
906 ftp_rqfcr[rqfar] = rqfcr;
907 ftp_rqfpr[rqfar] = rqfpr;
908 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
910 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
911 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
912 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
913 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
914 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
915 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
917 /* cur_filer_idx indicated the first non-masked rule */
918 priv->cur_filer_idx = rqfar;
920 /* Rest are masked rules */
921 rqfcr = RQFCR_CMP_NOMATCH;
922 for (i = 0; i < rqfar; i++) {
923 ftp_rqfcr[i] = rqfcr;
924 ftp_rqfpr[i] = rqfpr;
925 gfar_write_filer(priv, i, rqfcr, rqfpr);
929 static void gfar_detect_errata(struct gfar_private *priv)
931 struct device *dev = &priv->ofdev->dev;
932 unsigned int pvr = mfspr(SPRN_PVR);
933 unsigned int svr = mfspr(SPRN_SVR);
934 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
935 unsigned int rev = svr & 0xffff;
937 /* MPC8313 Rev 2.0 and higher; All MPC837x */
938 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
939 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
940 priv->errata |= GFAR_ERRATA_74;
942 /* MPC8313 and MPC837x all rev */
943 if ((pvr == 0x80850010 && mod == 0x80b0) ||
944 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
945 priv->errata |= GFAR_ERRATA_76;
947 /* MPC8313 and MPC837x all rev */
948 if ((pvr == 0x80850010 && mod == 0x80b0) ||
949 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
950 priv->errata |= GFAR_ERRATA_A002;
953 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
957 /* Set up the ethernet device structure, private data,
958 * and anything else we need before we start */
959 static int gfar_probe(struct platform_device *ofdev,
960 const struct of_device_id *match)
963 struct net_device *dev = NULL;
964 struct gfar_private *priv = NULL;
965 struct gfar __iomem *regs = NULL;
966 int err = 0, i, grp_idx = 0;
968 u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
972 err = gfar_of_init(ofdev, &dev);
977 priv = netdev_priv(dev);
980 priv->node = ofdev->dev.of_node;
981 SET_NETDEV_DEV(dev, &ofdev->dev);
983 spin_lock_init(&priv->bflock);
984 INIT_WORK(&priv->reset_task, gfar_reset_task);
986 dev_set_drvdata(&ofdev->dev, priv);
987 regs = priv->gfargrp[0].regs;
989 gfar_detect_errata(priv);
991 /* Stop the DMA engine now, in case it was running before */
992 /* (The firmware could have used it, and left it running). */
995 /* Reset MAC layer */
996 gfar_write(®s->maccfg1, MACCFG1_SOFT_RESET);
998 /* We need to delay at least 3 TX clocks */
1001 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
1002 gfar_write(®s->maccfg1, tempval);
1004 /* Initialize MACCFG2. */
1005 tempval = MACCFG2_INIT_SETTINGS;
1006 if (gfar_has_errata(priv, GFAR_ERRATA_74))
1007 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1008 gfar_write(®s->maccfg2, tempval);
1010 /* Initialize ECNTRL */
1011 gfar_write(®s->ecntrl, ECNTRL_INIT_SETTINGS);
1013 /* Set the dev->base_addr to the gfar reg region */
1014 dev->base_addr = (unsigned long) regs;
1016 SET_NETDEV_DEV(dev, &ofdev->dev);
1018 /* Fill in the dev structure */
1019 dev->watchdog_timeo = TX_TIMEOUT;
1021 dev->netdev_ops = &gfar_netdev_ops;
1022 dev->ethtool_ops = &gfar_ethtool_ops;
1024 /* Register for napi ...We are registering NAPI for each grp */
1025 for (i = 0; i < priv->num_grps; i++)
1026 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, GFAR_DEV_WEIGHT);
1028 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1029 priv->rx_csum_enable = 1;
1030 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;
1032 priv->rx_csum_enable = 0;
1036 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)
1037 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1039 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1040 priv->extended_hash = 1;
1041 priv->hash_width = 9;
1043 priv->hash_regs[0] = ®s->igaddr0;
1044 priv->hash_regs[1] = ®s->igaddr1;
1045 priv->hash_regs[2] = ®s->igaddr2;
1046 priv->hash_regs[3] = ®s->igaddr3;
1047 priv->hash_regs[4] = ®s->igaddr4;
1048 priv->hash_regs[5] = ®s->igaddr5;
1049 priv->hash_regs[6] = ®s->igaddr6;
1050 priv->hash_regs[7] = ®s->igaddr7;
1051 priv->hash_regs[8] = ®s->gaddr0;
1052 priv->hash_regs[9] = ®s->gaddr1;
1053 priv->hash_regs[10] = ®s->gaddr2;
1054 priv->hash_regs[11] = ®s->gaddr3;
1055 priv->hash_regs[12] = ®s->gaddr4;
1056 priv->hash_regs[13] = ®s->gaddr5;
1057 priv->hash_regs[14] = ®s->gaddr6;
1058 priv->hash_regs[15] = ®s->gaddr7;
1061 priv->extended_hash = 0;
1062 priv->hash_width = 8;
1064 priv->hash_regs[0] = ®s->gaddr0;
1065 priv->hash_regs[1] = ®s->gaddr1;
1066 priv->hash_regs[2] = ®s->gaddr2;
1067 priv->hash_regs[3] = ®s->gaddr3;
1068 priv->hash_regs[4] = ®s->gaddr4;
1069 priv->hash_regs[5] = ®s->gaddr5;
1070 priv->hash_regs[6] = ®s->gaddr6;
1071 priv->hash_regs[7] = ®s->gaddr7;
1074 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
1075 priv->padding = DEFAULT_PADDING;
1079 if (dev->features & NETIF_F_IP_CSUM ||
1080 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1081 dev->hard_header_len += GMAC_FCB_LEN;
1083 /* Program the isrg regs only if number of grps > 1 */
1084 if (priv->num_grps > 1) {
1085 baddr = ®s->isrg0;
1086 for (i = 0; i < priv->num_grps; i++) {
1087 isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1088 isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1089 gfar_write(baddr, isrg);
1095 /* Need to reverse the bit maps as bit_map's MSB is q0
1096 * but, for_each_set_bit parses from right to left, which
1097 * basically reverses the queue numbers */
1098 for (i = 0; i< priv->num_grps; i++) {
1099 priv->gfargrp[i].tx_bit_map = reverse_bitmap(
1100 priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1101 priv->gfargrp[i].rx_bit_map = reverse_bitmap(
1102 priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
1105 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1106 * also assign queues to groups */
1107 for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1108 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
1109 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
1110 priv->num_rx_queues) {
1111 priv->gfargrp[grp_idx].num_rx_queues++;
1112 priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1113 rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1114 rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1116 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
1117 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
1118 priv->num_tx_queues) {
1119 priv->gfargrp[grp_idx].num_tx_queues++;
1120 priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1121 tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1122 tqueue = tqueue | (TQUEUE_EN0 >> i);
1124 priv->gfargrp[grp_idx].rstat = rstat;
1125 priv->gfargrp[grp_idx].tstat = tstat;
1129 gfar_write(®s->rqueue, rqueue);
1130 gfar_write(®s->tqueue, tqueue);
1132 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1134 /* Initializing some of the rx/tx queue level parameters */
1135 for (i = 0; i < priv->num_tx_queues; i++) {
1136 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1137 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1138 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1139 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1142 for (i = 0; i < priv->num_rx_queues; i++) {
1143 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1144 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1145 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1148 /* enable filer if using multiple RX queues*/
1149 if(priv->num_rx_queues > 1)
1150 priv->rx_filer_enable = 1;
1151 /* Enable most messages by default */
1152 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1154 /* Carrier starts down, phylib will bring it up */
1155 netif_carrier_off(dev);
1157 err = register_netdev(dev);
1160 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
1165 device_init_wakeup(&dev->dev,
1166 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1168 /* fill out IRQ number and name fields */
1169 len_devname = strlen(dev->name);
1170 for (i = 0; i < priv->num_grps; i++) {
1171 strncpy(&priv->gfargrp[i].int_name_tx[0], dev->name,
1173 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1174 strncpy(&priv->gfargrp[i].int_name_tx[len_devname],
1175 "_g", sizeof("_g"));
1176 priv->gfargrp[i].int_name_tx[
1177 strlen(priv->gfargrp[i].int_name_tx)] = i+48;
1178 strncpy(&priv->gfargrp[i].int_name_tx[strlen(
1179 priv->gfargrp[i].int_name_tx)],
1180 "_tx", sizeof("_tx") + 1);
1182 strncpy(&priv->gfargrp[i].int_name_rx[0], dev->name,
1184 strncpy(&priv->gfargrp[i].int_name_rx[len_devname],
1185 "_g", sizeof("_g"));
1186 priv->gfargrp[i].int_name_rx[
1187 strlen(priv->gfargrp[i].int_name_rx)] = i+48;
1188 strncpy(&priv->gfargrp[i].int_name_rx[strlen(
1189 priv->gfargrp[i].int_name_rx)],
1190 "_rx", sizeof("_rx") + 1);
1192 strncpy(&priv->gfargrp[i].int_name_er[0], dev->name,
1194 strncpy(&priv->gfargrp[i].int_name_er[len_devname],
1195 "_g", sizeof("_g"));
1196 priv->gfargrp[i].int_name_er[strlen(
1197 priv->gfargrp[i].int_name_er)] = i+48;
1198 strncpy(&priv->gfargrp[i].int_name_er[strlen(\
1199 priv->gfargrp[i].int_name_er)],
1200 "_er", sizeof("_er") + 1);
1202 priv->gfargrp[i].int_name_tx[len_devname] = '\0';
1205 /* Initialize the filer table */
1206 gfar_init_filer_table(priv);
1208 /* Create all the sysfs files */
1209 gfar_init_sysfs(dev);
1211 /* Print out the device info */
1212 printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
1214 /* Even more device info helps when determining which kernel */
1215 /* provided which set of benchmarks. */
1216 printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
1217 for (i = 0; i < priv->num_rx_queues; i++)
1218 printk(KERN_INFO "%s: RX BD ring size for Q[%d]: %d\n",
1219 dev->name, i, priv->rx_queue[i]->rx_ring_size);
1220 for(i = 0; i < priv->num_tx_queues; i++)
1221 printk(KERN_INFO "%s: TX BD ring size for Q[%d]: %d\n",
1222 dev->name, i, priv->tx_queue[i]->tx_ring_size);
1227 unmap_group_regs(priv);
1228 free_tx_pointers(priv);
1229 free_rx_pointers(priv);
1231 of_node_put(priv->phy_node);
1233 of_node_put(priv->tbi_node);
1238 static int gfar_remove(struct platform_device *ofdev)
1240 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
1243 of_node_put(priv->phy_node);
1245 of_node_put(priv->tbi_node);
1247 dev_set_drvdata(&ofdev->dev, NULL);
1249 unregister_netdev(priv->ndev);
1250 unmap_group_regs(priv);
1251 free_netdev(priv->ndev);
1258 static int gfar_suspend(struct device *dev)
1260 struct gfar_private *priv = dev_get_drvdata(dev);
1261 struct net_device *ndev = priv->ndev;
1262 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1263 unsigned long flags;
1266 int magic_packet = priv->wol_en &&
1267 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1269 netif_device_detach(ndev);
1271 if (netif_running(ndev)) {
1273 local_irq_save(flags);
1277 gfar_halt_nodisable(ndev);
1279 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1280 tempval = gfar_read(®s->maccfg1);
1282 tempval &= ~MACCFG1_TX_EN;
1285 tempval &= ~MACCFG1_RX_EN;
1287 gfar_write(®s->maccfg1, tempval);
1291 local_irq_restore(flags);
1296 /* Enable interrupt on Magic Packet */
1297 gfar_write(®s->imask, IMASK_MAG);
1299 /* Enable Magic Packet mode */
1300 tempval = gfar_read(®s->maccfg2);
1301 tempval |= MACCFG2_MPEN;
1302 gfar_write(®s->maccfg2, tempval);
1304 phy_stop(priv->phydev);
1311 static int gfar_resume(struct device *dev)
1313 struct gfar_private *priv = dev_get_drvdata(dev);
1314 struct net_device *ndev = priv->ndev;
1315 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1316 unsigned long flags;
1318 int magic_packet = priv->wol_en &&
1319 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1321 if (!netif_running(ndev)) {
1322 netif_device_attach(ndev);
1326 if (!magic_packet && priv->phydev)
1327 phy_start(priv->phydev);
1329 /* Disable Magic Packet mode, in case something
1332 local_irq_save(flags);
1336 tempval = gfar_read(®s->maccfg2);
1337 tempval &= ~MACCFG2_MPEN;
1338 gfar_write(®s->maccfg2, tempval);
1344 local_irq_restore(flags);
1346 netif_device_attach(ndev);
1353 static int gfar_restore(struct device *dev)
1355 struct gfar_private *priv = dev_get_drvdata(dev);
1356 struct net_device *ndev = priv->ndev;
1358 if (!netif_running(ndev))
1361 gfar_init_bds(ndev);
1362 init_registers(ndev);
1363 gfar_set_mac_address(ndev);
1364 gfar_init_mac(ndev);
1369 priv->oldduplex = -1;
1372 phy_start(priv->phydev);
1374 netif_device_attach(ndev);
1380 static struct dev_pm_ops gfar_pm_ops = {
1381 .suspend = gfar_suspend,
1382 .resume = gfar_resume,
1383 .freeze = gfar_suspend,
1384 .thaw = gfar_resume,
1385 .restore = gfar_restore,
1388 #define GFAR_PM_OPS (&gfar_pm_ops)
1392 #define GFAR_PM_OPS NULL
1396 /* Reads the controller's registers to determine what interface
1397 * connects it to the PHY.
1399 static phy_interface_t gfar_get_interface(struct net_device *dev)
1401 struct gfar_private *priv = netdev_priv(dev);
1402 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1405 ecntrl = gfar_read(®s->ecntrl);
1407 if (ecntrl & ECNTRL_SGMII_MODE)
1408 return PHY_INTERFACE_MODE_SGMII;
1410 if (ecntrl & ECNTRL_TBI_MODE) {
1411 if (ecntrl & ECNTRL_REDUCED_MODE)
1412 return PHY_INTERFACE_MODE_RTBI;
1414 return PHY_INTERFACE_MODE_TBI;
1417 if (ecntrl & ECNTRL_REDUCED_MODE) {
1418 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
1419 return PHY_INTERFACE_MODE_RMII;
1421 phy_interface_t interface = priv->interface;
1424 * This isn't autodetected right now, so it must
1425 * be set by the device tree or platform code.
1427 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1428 return PHY_INTERFACE_MODE_RGMII_ID;
1430 return PHY_INTERFACE_MODE_RGMII;
1434 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1435 return PHY_INTERFACE_MODE_GMII;
1437 return PHY_INTERFACE_MODE_MII;
1441 /* Initializes driver's PHY state, and attaches to the PHY.
1442 * Returns 0 on success.
1444 static int init_phy(struct net_device *dev)
1446 struct gfar_private *priv = netdev_priv(dev);
1447 uint gigabit_support =
1448 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1449 SUPPORTED_1000baseT_Full : 0;
1450 phy_interface_t interface;
1454 priv->oldduplex = -1;
1456 interface = gfar_get_interface(dev);
1458 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1461 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1463 if (!priv->phydev) {
1464 dev_err(&dev->dev, "could not attach to PHY\n");
1468 if (interface == PHY_INTERFACE_MODE_SGMII)
1469 gfar_configure_serdes(dev);
1471 /* Remove any features not supported by the controller */
1472 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1473 priv->phydev->advertising = priv->phydev->supported;
1479 * Initialize TBI PHY interface for communicating with the
1480 * SERDES lynx PHY on the chip. We communicate with this PHY
1481 * through the MDIO bus on each controller, treating it as a
1482 * "normal" PHY at the address found in the TBIPA register. We assume
1483 * that the TBIPA register is valid. Either the MDIO bus code will set
1484 * it to a value that doesn't conflict with other PHYs on the bus, or the
1485 * value doesn't matter, as there are no other PHYs on the bus.
1487 static void gfar_configure_serdes(struct net_device *dev)
1489 struct gfar_private *priv = netdev_priv(dev);
1490 struct phy_device *tbiphy;
1492 if (!priv->tbi_node) {
1493 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1494 "device tree specify a tbi-handle\n");
1498 tbiphy = of_phy_find_device(priv->tbi_node);
1500 dev_err(&dev->dev, "error: Could not get TBI device\n");
1505 * If the link is already up, we must already be ok, and don't need to
1506 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1507 * everything for us? Resetting it takes the link down and requires
1508 * several seconds for it to come back.
1510 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1513 /* Single clk mode, mii mode off(for serdes communication) */
1514 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1516 phy_write(tbiphy, MII_ADVERTISE,
1517 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1518 ADVERTISE_1000XPSE_ASYM);
1520 phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE |
1521 BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
1524 static void init_registers(struct net_device *dev)
1526 struct gfar_private *priv = netdev_priv(dev);
1527 struct gfar __iomem *regs = NULL;
1530 for (i = 0; i < priv->num_grps; i++) {
1531 regs = priv->gfargrp[i].regs;
1533 gfar_write(®s->ievent, IEVENT_INIT_CLEAR);
1535 /* Initialize IMASK */
1536 gfar_write(®s->imask, IMASK_INIT_CLEAR);
1539 regs = priv->gfargrp[0].regs;
1540 /* Init hash registers to zero */
1541 gfar_write(®s->igaddr0, 0);
1542 gfar_write(®s->igaddr1, 0);
1543 gfar_write(®s->igaddr2, 0);
1544 gfar_write(®s->igaddr3, 0);
1545 gfar_write(®s->igaddr4, 0);
1546 gfar_write(®s->igaddr5, 0);
1547 gfar_write(®s->igaddr6, 0);
1548 gfar_write(®s->igaddr7, 0);
1550 gfar_write(®s->gaddr0, 0);
1551 gfar_write(®s->gaddr1, 0);
1552 gfar_write(®s->gaddr2, 0);
1553 gfar_write(®s->gaddr3, 0);
1554 gfar_write(®s->gaddr4, 0);
1555 gfar_write(®s->gaddr5, 0);
1556 gfar_write(®s->gaddr6, 0);
1557 gfar_write(®s->gaddr7, 0);
1559 /* Zero out the rmon mib registers if it has them */
1560 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1561 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1563 /* Mask off the CAM interrupts */
1564 gfar_write(®s->rmon.cam1, 0xffffffff);
1565 gfar_write(®s->rmon.cam2, 0xffffffff);
1568 /* Initialize the max receive buffer length */
1569 gfar_write(®s->mrblr, priv->rx_buffer_size);
1571 /* Initialize the Minimum Frame Length Register */
1572 gfar_write(®s->minflr, MINFLR_INIT_SETTINGS);
1575 static int __gfar_is_rx_idle(struct gfar_private *priv)
1580 * Normaly TSEC should not hang on GRS commands, so we should
1581 * actually wait for IEVENT_GRSC flag.
1583 if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002)))
1587 * Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1588 * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1589 * and the Rx can be safely reset.
1591 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1593 if ((res & 0xffff) == (res >> 16))
1599 /* Halt the receive and transmit queues */
1600 static void gfar_halt_nodisable(struct net_device *dev)
1602 struct gfar_private *priv = netdev_priv(dev);
1603 struct gfar __iomem *regs = NULL;
1607 for (i = 0; i < priv->num_grps; i++) {
1608 regs = priv->gfargrp[i].regs;
1609 /* Mask all interrupts */
1610 gfar_write(®s->imask, IMASK_INIT_CLEAR);
1612 /* Clear all interrupts */
1613 gfar_write(®s->ievent, IEVENT_INIT_CLEAR);
1616 regs = priv->gfargrp[0].regs;
1617 /* Stop the DMA, and wait for it to stop */
1618 tempval = gfar_read(®s->dmactrl);
1619 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
1620 != (DMACTRL_GRS | DMACTRL_GTS)) {
1623 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1624 gfar_write(®s->dmactrl, tempval);
1627 ret = spin_event_timeout(((gfar_read(®s->ievent) &
1628 (IEVENT_GRSC | IEVENT_GTSC)) ==
1629 (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
1630 if (!ret && !(gfar_read(®s->ievent) & IEVENT_GRSC))
1631 ret = __gfar_is_rx_idle(priv);
1636 /* Halt the receive and transmit queues */
1637 void gfar_halt(struct net_device *dev)
1639 struct gfar_private *priv = netdev_priv(dev);
1640 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1643 gfar_halt_nodisable(dev);
1645 /* Disable Rx and Tx */
1646 tempval = gfar_read(®s->maccfg1);
1647 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1648 gfar_write(®s->maccfg1, tempval);
1651 static void free_grp_irqs(struct gfar_priv_grp *grp)
1653 free_irq(grp->interruptError, grp);
1654 free_irq(grp->interruptTransmit, grp);
1655 free_irq(grp->interruptReceive, grp);
1658 void stop_gfar(struct net_device *dev)
1660 struct gfar_private *priv = netdev_priv(dev);
1661 unsigned long flags;
1664 phy_stop(priv->phydev);
1668 local_irq_save(flags);
1676 local_irq_restore(flags);
1679 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1680 for (i = 0; i < priv->num_grps; i++)
1681 free_grp_irqs(&priv->gfargrp[i]);
1683 for (i = 0; i < priv->num_grps; i++)
1684 free_irq(priv->gfargrp[i].interruptTransmit,
1688 free_skb_resources(priv);
1691 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1693 struct txbd8 *txbdp;
1694 struct gfar_private *priv = netdev_priv(tx_queue->dev);
1697 txbdp = tx_queue->tx_bd_base;
1699 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1700 if (!tx_queue->tx_skbuff[i])
1703 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
1704 txbdp->length, DMA_TO_DEVICE);
1706 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1709 dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
1710 txbdp->length, DMA_TO_DEVICE);
1713 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1714 tx_queue->tx_skbuff[i] = NULL;
1716 kfree(tx_queue->tx_skbuff);
1719 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1721 struct rxbd8 *rxbdp;
1722 struct gfar_private *priv = netdev_priv(rx_queue->dev);
1725 rxbdp = rx_queue->rx_bd_base;
1727 for (i = 0; i < rx_queue->rx_ring_size; i++) {
1728 if (rx_queue->rx_skbuff[i]) {
1729 dma_unmap_single(&priv->ofdev->dev,
1730 rxbdp->bufPtr, priv->rx_buffer_size,
1732 dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1733 rx_queue->rx_skbuff[i] = NULL;
1739 kfree(rx_queue->rx_skbuff);
1742 /* If there are any tx skbs or rx skbs still around, free them.
1743 * Then free tx_skbuff and rx_skbuff */
1744 static void free_skb_resources(struct gfar_private *priv)
1746 struct gfar_priv_tx_q *tx_queue = NULL;
1747 struct gfar_priv_rx_q *rx_queue = NULL;
1750 /* Go through all the buffer descriptors and free their data buffers */
1751 for (i = 0; i < priv->num_tx_queues; i++) {
1752 tx_queue = priv->tx_queue[i];
1753 if(tx_queue->tx_skbuff)
1754 free_skb_tx_queue(tx_queue);
1757 for (i = 0; i < priv->num_rx_queues; i++) {
1758 rx_queue = priv->rx_queue[i];
1759 if(rx_queue->rx_skbuff)
1760 free_skb_rx_queue(rx_queue);
1763 dma_free_coherent(&priv->ofdev->dev,
1764 sizeof(struct txbd8) * priv->total_tx_ring_size +
1765 sizeof(struct rxbd8) * priv->total_rx_ring_size,
1766 priv->tx_queue[0]->tx_bd_base,
1767 priv->tx_queue[0]->tx_bd_dma_base);
1768 skb_queue_purge(&priv->rx_recycle);
1771 void gfar_start(struct net_device *dev)
1773 struct gfar_private *priv = netdev_priv(dev);
1774 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1778 /* Enable Rx and Tx in MACCFG1 */
1779 tempval = gfar_read(®s->maccfg1);
1780 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1781 gfar_write(®s->maccfg1, tempval);
1783 /* Initialize DMACTRL to have WWR and WOP */
1784 tempval = gfar_read(®s->dmactrl);
1785 tempval |= DMACTRL_INIT_SETTINGS;
1786 gfar_write(®s->dmactrl, tempval);
1788 /* Make sure we aren't stopped */
1789 tempval = gfar_read(®s->dmactrl);
1790 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1791 gfar_write(®s->dmactrl, tempval);
1793 for (i = 0; i < priv->num_grps; i++) {
1794 regs = priv->gfargrp[i].regs;
1795 /* Clear THLT/RHLT, so that the DMA starts polling now */
1796 gfar_write(®s->tstat, priv->gfargrp[i].tstat);
1797 gfar_write(®s->rstat, priv->gfargrp[i].rstat);
1798 /* Unmask the interrupts we look for */
1799 gfar_write(®s->imask, IMASK_DEFAULT);
1802 dev->trans_start = jiffies; /* prevent tx timeout */
1805 void gfar_configure_coalescing(struct gfar_private *priv,
1806 unsigned long tx_mask, unsigned long rx_mask)
1808 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1812 /* Backward compatible case ---- even if we enable
1813 * multiple queues, there's only single reg to program
1815 gfar_write(®s->txic, 0);
1816 if(likely(priv->tx_queue[0]->txcoalescing))
1817 gfar_write(®s->txic, priv->tx_queue[0]->txic);
1819 gfar_write(®s->rxic, 0);
1820 if(unlikely(priv->rx_queue[0]->rxcoalescing))
1821 gfar_write(®s->rxic, priv->rx_queue[0]->rxic);
1823 if (priv->mode == MQ_MG_MODE) {
1824 baddr = ®s->txic0;
1825 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
1826 if (likely(priv->tx_queue[i]->txcoalescing)) {
1827 gfar_write(baddr + i, 0);
1828 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1832 baddr = ®s->rxic0;
1833 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
1834 if (likely(priv->rx_queue[i]->rxcoalescing)) {
1835 gfar_write(baddr + i, 0);
1836 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1842 static int register_grp_irqs(struct gfar_priv_grp *grp)
1844 struct gfar_private *priv = grp->priv;
1845 struct net_device *dev = priv->ndev;
1848 /* If the device has multiple interrupts, register for
1849 * them. Otherwise, only register for the one */
1850 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1851 /* Install our interrupt handlers for Error,
1852 * Transmit, and Receive */
1853 if ((err = request_irq(grp->interruptError, gfar_error, 0,
1854 grp->int_name_er,grp)) < 0) {
1855 if (netif_msg_intr(priv))
1856 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1857 dev->name, grp->interruptError);
1862 if ((err = request_irq(grp->interruptTransmit, gfar_transmit,
1863 0, grp->int_name_tx, grp)) < 0) {
1864 if (netif_msg_intr(priv))
1865 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1866 dev->name, grp->interruptTransmit);
1870 if ((err = request_irq(grp->interruptReceive, gfar_receive, 0,
1871 grp->int_name_rx, grp)) < 0) {
1872 if (netif_msg_intr(priv))
1873 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1874 dev->name, grp->interruptReceive);
1878 if ((err = request_irq(grp->interruptTransmit, gfar_interrupt, 0,
1879 grp->int_name_tx, grp)) < 0) {
1880 if (netif_msg_intr(priv))
1881 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1882 dev->name, grp->interruptTransmit);
1890 free_irq(grp->interruptTransmit, grp);
1892 free_irq(grp->interruptError, grp);
1898 /* Bring the controller up and running */
1899 int startup_gfar(struct net_device *ndev)
1901 struct gfar_private *priv = netdev_priv(ndev);
1902 struct gfar __iomem *regs = NULL;
1905 for (i = 0; i < priv->num_grps; i++) {
1906 regs= priv->gfargrp[i].regs;
1907 gfar_write(®s->imask, IMASK_INIT_CLEAR);
1910 regs= priv->gfargrp[0].regs;
1911 err = gfar_alloc_skb_resources(ndev);
1915 gfar_init_mac(ndev);
1917 for (i = 0; i < priv->num_grps; i++) {
1918 err = register_grp_irqs(&priv->gfargrp[i]);
1920 for (j = 0; j < i; j++)
1921 free_grp_irqs(&priv->gfargrp[j]);
1926 /* Start the controller */
1929 phy_start(priv->phydev);
1931 gfar_configure_coalescing(priv, 0xFF, 0xFF);
1936 free_skb_resources(priv);
1940 /* Called when something needs to use the ethernet device */
1941 /* Returns 0 for success. */
1942 static int gfar_enet_open(struct net_device *dev)
1944 struct gfar_private *priv = netdev_priv(dev);
1949 skb_queue_head_init(&priv->rx_recycle);
1951 /* Initialize a bunch of registers */
1952 init_registers(dev);
1954 gfar_set_mac_address(dev);
1956 err = init_phy(dev);
1963 err = startup_gfar(dev);
1969 netif_tx_start_all_queues(dev);
1971 device_set_wakeup_enable(&dev->dev, priv->wol_en);
1976 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1978 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1980 memset(fcb, 0, GMAC_FCB_LEN);
1985 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1989 /* If we're here, it's a IP packet with a TCP or UDP
1990 * payload. We set it to checksum, using a pseudo-header
1993 flags = TXFCB_DEFAULT;
1995 /* Tell the controller what the protocol is */
1996 /* And provide the already calculated phcs */
1997 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1999 fcb->phcs = udp_hdr(skb)->check;
2001 fcb->phcs = tcp_hdr(skb)->check;
2003 /* l3os is the distance between the start of the
2004 * frame (skb->data) and the start of the IP hdr.
2005 * l4os is the distance between the start of the
2006 * l3 hdr and the l4 hdr */
2007 fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
2008 fcb->l4os = skb_network_header_len(skb);
2013 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2015 fcb->flags |= TXFCB_VLN;
2016 fcb->vlctl = vlan_tx_tag_get(skb);
2019 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2020 struct txbd8 *base, int ring_size)
2022 struct txbd8 *new_bd = bdp + stride;
2024 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2027 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2030 return skip_txbd(bdp, 1, base, ring_size);
2033 /* This is called by the kernel when a frame is ready for transmission. */
2034 /* It is pointed to by the dev->hard_start_xmit function pointer */
2035 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2037 struct gfar_private *priv = netdev_priv(dev);
2038 struct gfar_priv_tx_q *tx_queue = NULL;
2039 struct netdev_queue *txq;
2040 struct gfar __iomem *regs = NULL;
2041 struct txfcb *fcb = NULL;
2042 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2044 int i, rq = 0, do_tstamp = 0;
2046 unsigned long flags;
2047 unsigned int nr_frags, nr_txbds, length;
2050 * TOE=1 frames larger than 2500 bytes may see excess delays
2051 * before start of transmission.
2053 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) &&
2054 skb->ip_summed == CHECKSUM_PARTIAL &&
2058 ret = skb_checksum_help(skb);
2063 rq = skb->queue_mapping;
2064 tx_queue = priv->tx_queue[rq];
2065 txq = netdev_get_tx_queue(dev, rq);
2066 base = tx_queue->tx_bd_base;
2067 regs = tx_queue->grp->regs;
2069 /* check if time stamp should be generated */
2070 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
2074 /* make space for additional header when fcb is needed */
2075 if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
2076 vlan_tx_tag_present(skb) ||
2077 unlikely(do_tstamp)) &&
2078 (skb_headroom(skb) < GMAC_FCB_LEN)) {
2079 struct sk_buff *skb_new;
2081 skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN);
2083 dev->stats.tx_errors++;
2085 return NETDEV_TX_OK;
2091 /* total number of fragments in the SKB */
2092 nr_frags = skb_shinfo(skb)->nr_frags;
2094 /* calculate the required number of TxBDs for this skb */
2095 if (unlikely(do_tstamp))
2096 nr_txbds = nr_frags + 2;
2098 nr_txbds = nr_frags + 1;
2100 /* check if there is space to queue this packet */
2101 if (nr_txbds > tx_queue->num_txbdfree) {
2102 /* no space, stop the queue */
2103 netif_tx_stop_queue(txq);
2104 dev->stats.tx_fifo_errors++;
2105 return NETDEV_TX_BUSY;
2108 /* Update transmit stats */
2109 tx_queue->stats.tx_bytes += skb->len;
2110 tx_queue->stats.tx_packets++;
2112 txbdp = txbdp_start = tx_queue->cur_tx;
2113 lstatus = txbdp->lstatus;
2115 /* Time stamp insertion requires one additional TxBD */
2116 if (unlikely(do_tstamp))
2117 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2118 tx_queue->tx_ring_size);
2120 if (nr_frags == 0) {
2121 if (unlikely(do_tstamp))
2122 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2125 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2127 /* Place the fragment addresses and lengths into the TxBDs */
2128 for (i = 0; i < nr_frags; i++) {
2129 /* Point at the next BD, wrapping as needed */
2130 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2132 length = skb_shinfo(skb)->frags[i].size;
2134 lstatus = txbdp->lstatus | length |
2135 BD_LFLAG(TXBD_READY);
2137 /* Handle the last BD specially */
2138 if (i == nr_frags - 1)
2139 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2141 bufaddr = dma_map_page(&priv->ofdev->dev,
2142 skb_shinfo(skb)->frags[i].page,
2143 skb_shinfo(skb)->frags[i].page_offset,
2147 /* set the TxBD length and buffer pointer */
2148 txbdp->bufPtr = bufaddr;
2149 txbdp->lstatus = lstatus;
2152 lstatus = txbdp_start->lstatus;
2155 /* Set up checksumming */
2156 if (CHECKSUM_PARTIAL == skb->ip_summed) {
2157 fcb = gfar_add_fcb(skb);
2158 lstatus |= BD_LFLAG(TXBD_TOE);
2159 gfar_tx_checksum(skb, fcb);
2162 if (vlan_tx_tag_present(skb)) {
2163 if (unlikely(NULL == fcb)) {
2164 fcb = gfar_add_fcb(skb);
2165 lstatus |= BD_LFLAG(TXBD_TOE);
2168 gfar_tx_vlan(skb, fcb);
2171 /* Setup tx hardware time stamping if requested */
2172 if (unlikely(do_tstamp)) {
2173 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2175 fcb = gfar_add_fcb(skb);
2177 lstatus |= BD_LFLAG(TXBD_TOE);
2180 txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
2181 skb_headlen(skb), DMA_TO_DEVICE);
2184 * If time stamping is requested one additional TxBD must be set up. The
2185 * first TxBD points to the FCB and must have a data length of
2186 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2187 * the full frame length.
2189 if (unlikely(do_tstamp)) {
2190 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + GMAC_FCB_LEN;
2191 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2192 (skb_headlen(skb) - GMAC_FCB_LEN);
2193 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2195 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2199 * We can work in parallel with gfar_clean_tx_ring(), except
2200 * when modifying num_txbdfree. Note that we didn't grab the lock
2201 * when we were reading the num_txbdfree and checking for available
2202 * space, that's because outside of this function it can only grow,
2203 * and once we've got needed space, it cannot suddenly disappear.
2205 * The lock also protects us from gfar_error(), which can modify
2206 * regs->tstat and thus retrigger the transfers, which is why we
2207 * also must grab the lock before setting ready bit for the first
2208 * to be transmitted BD.
2210 spin_lock_irqsave(&tx_queue->txlock, flags);
2213 * The powerpc-specific eieio() is used, as wmb() has too strong
2214 * semantics (it requires synchronization between cacheable and
2215 * uncacheable mappings, which eieio doesn't provide and which we
2216 * don't need), thus requiring a more expensive sync instruction. At
2217 * some point, the set of architecture-independent barrier functions
2218 * should be expanded to include weaker barriers.
2222 txbdp_start->lstatus = lstatus;
2224 eieio(); /* force lstatus write before tx_skbuff */
2226 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2228 /* Update the current skb pointer to the next entry we will use
2229 * (wrapping if necessary) */
2230 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2231 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2233 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2235 /* reduce TxBD free count */
2236 tx_queue->num_txbdfree -= (nr_txbds);
2238 /* If the next BD still needs to be cleaned up, then the bds
2239 are full. We need to tell the kernel to stop sending us stuff. */
2240 if (!tx_queue->num_txbdfree) {
2241 netif_tx_stop_queue(txq);
2243 dev->stats.tx_fifo_errors++;
2246 /* Tell the DMA to go go go */
2247 gfar_write(®s->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2250 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2252 return NETDEV_TX_OK;
2255 /* Stops the kernel queue, and halts the controller */
2256 static int gfar_close(struct net_device *dev)
2258 struct gfar_private *priv = netdev_priv(dev);
2262 cancel_work_sync(&priv->reset_task);
2265 /* Disconnect from the PHY */
2266 phy_disconnect(priv->phydev);
2267 priv->phydev = NULL;
2269 netif_tx_stop_all_queues(dev);
2274 /* Changes the mac address if the controller is not running. */
2275 static int gfar_set_mac_address(struct net_device *dev)
2277 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2283 /* Enables and disables VLAN insertion/extraction */
2284 static void gfar_vlan_rx_register(struct net_device *dev,
2285 struct vlan_group *grp)
2287 struct gfar_private *priv = netdev_priv(dev);
2288 struct gfar __iomem *regs = NULL;
2289 unsigned long flags;
2292 regs = priv->gfargrp[0].regs;
2293 local_irq_save(flags);
2299 /* Enable VLAN tag insertion */
2300 tempval = gfar_read(®s->tctrl);
2301 tempval |= TCTRL_VLINS;
2303 gfar_write(®s->tctrl, tempval);
2305 /* Enable VLAN tag extraction */
2306 tempval = gfar_read(®s->rctrl);
2307 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
2308 gfar_write(®s->rctrl, tempval);
2310 /* Disable VLAN tag insertion */
2311 tempval = gfar_read(®s->tctrl);
2312 tempval &= ~TCTRL_VLINS;
2313 gfar_write(®s->tctrl, tempval);
2315 /* Disable VLAN tag extraction */
2316 tempval = gfar_read(®s->rctrl);
2317 tempval &= ~RCTRL_VLEX;
2318 /* If parse is no longer required, then disable parser */
2319 if (tempval & RCTRL_REQ_PARSER)
2320 tempval |= RCTRL_PRSDEP_INIT;
2322 tempval &= ~RCTRL_PRSDEP_INIT;
2323 gfar_write(®s->rctrl, tempval);
2326 gfar_change_mtu(dev, dev->mtu);
2329 local_irq_restore(flags);
2332 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2334 int tempsize, tempval;
2335 struct gfar_private *priv = netdev_priv(dev);
2336 struct gfar __iomem *regs = priv->gfargrp[0].regs;
2337 int oldsize = priv->rx_buffer_size;
2338 int frame_size = new_mtu + ETH_HLEN;
2341 frame_size += VLAN_HLEN;
2343 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2344 if (netif_msg_drv(priv))
2345 printk(KERN_ERR "%s: Invalid MTU setting\n",
2350 if (gfar_uses_fcb(priv))
2351 frame_size += GMAC_FCB_LEN;
2353 frame_size += priv->padding;
2356 (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2357 INCREMENTAL_BUFFER_SIZE;
2359 /* Only stop and start the controller if it isn't already
2360 * stopped, and we changed something */
2361 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2364 priv->rx_buffer_size = tempsize;
2368 gfar_write(®s->mrblr, priv->rx_buffer_size);
2369 gfar_write(®s->maxfrm, priv->rx_buffer_size);
2371 /* If the mtu is larger than the max size for standard
2372 * ethernet frames (ie, a jumbo frame), then set maccfg2
2373 * to allow huge frames, and to check the length */
2374 tempval = gfar_read(®s->maccfg2);
2376 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
2377 gfar_has_errata(priv, GFAR_ERRATA_74))
2378 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2380 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2382 gfar_write(®s->maccfg2, tempval);
2384 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2390 /* gfar_reset_task gets scheduled when a packet has not been
2391 * transmitted after a set amount of time.
2392 * For now, assume that clearing out all the structures, and
2393 * starting over will fix the problem.
2395 static void gfar_reset_task(struct work_struct *work)
2397 struct gfar_private *priv = container_of(work, struct gfar_private,
2399 struct net_device *dev = priv->ndev;
2401 if (dev->flags & IFF_UP) {
2402 netif_tx_stop_all_queues(dev);
2405 netif_tx_start_all_queues(dev);
2408 netif_tx_schedule_all(dev);
2411 static void gfar_timeout(struct net_device *dev)
2413 struct gfar_private *priv = netdev_priv(dev);
2415 dev->stats.tx_errors++;
2416 schedule_work(&priv->reset_task);
2419 static void gfar_align_skb(struct sk_buff *skb)
2421 /* We need the data buffer to be aligned properly. We will reserve
2422 * as many bytes as needed to align the data properly
2424 skb_reserve(skb, RXBUF_ALIGNMENT -
2425 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
2428 /* Interrupt Handler for Transmit complete */
2429 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2431 struct net_device *dev = tx_queue->dev;
2432 struct gfar_private *priv = netdev_priv(dev);
2433 struct gfar_priv_rx_q *rx_queue = NULL;
2434 struct txbd8 *bdp, *next = NULL;
2435 struct txbd8 *lbdp = NULL;
2436 struct txbd8 *base = tx_queue->tx_bd_base;
2437 struct sk_buff *skb;
2439 int tx_ring_size = tx_queue->tx_ring_size;
2440 int frags = 0, nr_txbds = 0;
2446 rx_queue = priv->rx_queue[tx_queue->qindex];
2447 bdp = tx_queue->dirty_tx;
2448 skb_dirtytx = tx_queue->skb_dirtytx;
2450 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2451 unsigned long flags;
2453 frags = skb_shinfo(skb)->nr_frags;
2456 * When time stamping, one additional TxBD must be freed.
2457 * Also, we need to dma_unmap_single() the TxPAL.
2459 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2460 nr_txbds = frags + 2;
2462 nr_txbds = frags + 1;
2464 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2466 lstatus = lbdp->lstatus;
2468 /* Only clean completed frames */
2469 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2470 (lstatus & BD_LENGTH_MASK))
2473 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2474 next = next_txbd(bdp, base, tx_ring_size);
2475 buflen = next->length + GMAC_FCB_LEN;
2477 buflen = bdp->length;
2479 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2480 buflen, DMA_TO_DEVICE);
2482 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2483 struct skb_shared_hwtstamps shhwtstamps;
2484 u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2485 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2486 shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2487 skb_tstamp_tx(skb, &shhwtstamps);
2488 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2492 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2493 bdp = next_txbd(bdp, base, tx_ring_size);
2495 for (i = 0; i < frags; i++) {
2496 dma_unmap_page(&priv->ofdev->dev,
2500 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2501 bdp = next_txbd(bdp, base, tx_ring_size);
2505 * If there's room in the queue (limit it to rx_buffer_size)
2506 * we add this skb back into the pool, if it's the right size
2508 if (skb_queue_len(&priv->rx_recycle) < rx_queue->rx_ring_size &&
2509 skb_recycle_check(skb, priv->rx_buffer_size +
2511 gfar_align_skb(skb);
2512 skb_queue_head(&priv->rx_recycle, skb);
2514 dev_kfree_skb_any(skb);
2516 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2518 skb_dirtytx = (skb_dirtytx + 1) &
2519 TX_RING_MOD_MASK(tx_ring_size);
2522 spin_lock_irqsave(&tx_queue->txlock, flags);
2523 tx_queue->num_txbdfree += nr_txbds;
2524 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2527 /* If we freed a buffer, we can restart transmission, if necessary */
2528 if (__netif_subqueue_stopped(dev, tx_queue->qindex) && tx_queue->num_txbdfree)
2529 netif_wake_subqueue(dev, tx_queue->qindex);
2531 /* Update dirty indicators */
2532 tx_queue->skb_dirtytx = skb_dirtytx;
2533 tx_queue->dirty_tx = bdp;
2538 static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
2540 unsigned long flags;
2542 spin_lock_irqsave(&gfargrp->grplock, flags);
2543 if (napi_schedule_prep(&gfargrp->napi)) {
2544 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
2545 __napi_schedule(&gfargrp->napi);
2548 * Clear IEVENT, so interrupts aren't called again
2549 * because of the packets that have already arrived.
2551 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2553 spin_unlock_irqrestore(&gfargrp->grplock, flags);
2557 /* Interrupt Handler for Transmit complete */
2558 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2560 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2564 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
2565 struct sk_buff *skb)
2567 struct net_device *dev = rx_queue->dev;
2568 struct gfar_private *priv = netdev_priv(dev);
2571 buf = dma_map_single(&priv->ofdev->dev, skb->data,
2572 priv->rx_buffer_size, DMA_FROM_DEVICE);
2573 gfar_init_rxbdp(rx_queue, bdp, buf);
2576 static struct sk_buff * gfar_alloc_skb(struct net_device *dev)
2578 struct gfar_private *priv = netdev_priv(dev);
2579 struct sk_buff *skb = NULL;
2581 skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
2585 gfar_align_skb(skb);
2590 struct sk_buff * gfar_new_skb(struct net_device *dev)
2592 struct gfar_private *priv = netdev_priv(dev);
2593 struct sk_buff *skb = NULL;
2595 skb = skb_dequeue(&priv->rx_recycle);
2597 skb = gfar_alloc_skb(dev);
2602 static inline void count_errors(unsigned short status, struct net_device *dev)
2604 struct gfar_private *priv = netdev_priv(dev);
2605 struct net_device_stats *stats = &dev->stats;
2606 struct gfar_extra_stats *estats = &priv->extra_stats;
2608 /* If the packet was truncated, none of the other errors
2610 if (status & RXBD_TRUNCATED) {
2611 stats->rx_length_errors++;
2617 /* Count the errors, if there were any */
2618 if (status & (RXBD_LARGE | RXBD_SHORT)) {
2619 stats->rx_length_errors++;
2621 if (status & RXBD_LARGE)
2626 if (status & RXBD_NONOCTET) {
2627 stats->rx_frame_errors++;
2628 estats->rx_nonoctet++;
2630 if (status & RXBD_CRCERR) {
2631 estats->rx_crcerr++;
2632 stats->rx_crc_errors++;
2634 if (status & RXBD_OVERRUN) {
2635 estats->rx_overrun++;
2636 stats->rx_crc_errors++;
2640 irqreturn_t gfar_receive(int irq, void *grp_id)
2642 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2646 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2648 /* If valid headers were found, and valid sums
2649 * were verified, then we tell the kernel that no
2650 * checksumming is necessary. Otherwise, it is */
2651 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
2652 skb->ip_summed = CHECKSUM_UNNECESSARY;
2654 skb_checksum_none_assert(skb);
2658 /* gfar_process_frame() -- handle one incoming packet if skb
2660 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2663 struct gfar_private *priv = netdev_priv(dev);
2664 struct rxfcb *fcb = NULL;
2668 /* fcb is at the beginning if exists */
2669 fcb = (struct rxfcb *)skb->data;
2671 /* Remove the FCB from the skb */
2672 /* Remove the padded bytes, if there are any */
2674 skb_record_rx_queue(skb, fcb->rq);
2675 skb_pull(skb, amount_pull);
2678 /* Get receive timestamp from the skb */
2679 if (priv->hwts_rx_en) {
2680 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2681 u64 *ns = (u64 *) skb->data;
2682 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2683 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2687 skb_pull(skb, priv->padding);
2689 if (priv->rx_csum_enable)
2690 gfar_rx_checksum(skb, fcb);
2692 /* Tell the skb what kind of packet this is */
2693 skb->protocol = eth_type_trans(skb, dev);
2695 /* Send the packet up the stack */
2696 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
2697 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
2699 ret = netif_receive_skb(skb);
2701 if (NET_RX_DROP == ret)
2702 priv->extra_stats.kernel_dropped++;
2707 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2708 * until the budget/quota has been reached. Returns the number
2711 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2713 struct net_device *dev = rx_queue->dev;
2714 struct rxbd8 *bdp, *base;
2715 struct sk_buff *skb;
2719 struct gfar_private *priv = netdev_priv(dev);
2721 /* Get the first full descriptor */
2722 bdp = rx_queue->cur_rx;
2723 base = rx_queue->rx_bd_base;
2725 amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0);
2727 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
2728 struct sk_buff *newskb;
2731 /* Add another skb for the future */
2732 newskb = gfar_new_skb(dev);
2734 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
2736 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2737 priv->rx_buffer_size, DMA_FROM_DEVICE);
2739 if (unlikely(!(bdp->status & RXBD_ERR) &&
2740 bdp->length > priv->rx_buffer_size))
2741 bdp->status = RXBD_LARGE;
2743 /* We drop the frame if we failed to allocate a new buffer */
2744 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2745 bdp->status & RXBD_ERR)) {
2746 count_errors(bdp->status, dev);
2748 if (unlikely(!newskb))
2751 skb_queue_head(&priv->rx_recycle, skb);
2753 /* Increment the number of packets */
2754 rx_queue->stats.rx_packets++;
2758 pkt_len = bdp->length - ETH_FCS_LEN;
2759 /* Remove the FCS from the packet length */
2760 skb_put(skb, pkt_len);
2761 rx_queue->stats.rx_bytes += pkt_len;
2762 skb_record_rx_queue(skb, rx_queue->qindex);
2763 gfar_process_frame(dev, skb, amount_pull);
2766 if (netif_msg_rx_err(priv))
2768 "%s: Missing skb!\n", dev->name);
2769 rx_queue->stats.rx_dropped++;
2770 priv->extra_stats.rx_skbmissing++;
2775 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
2777 /* Setup the new bdp */
2778 gfar_new_rxbdp(rx_queue, bdp, newskb);
2780 /* Update to the next pointer */
2781 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2783 /* update to point at the next skb */
2784 rx_queue->skb_currx =
2785 (rx_queue->skb_currx + 1) &
2786 RX_RING_MOD_MASK(rx_queue->rx_ring_size);
2789 /* Update the current rxbd pointer to be the next one */
2790 rx_queue->cur_rx = bdp;
2795 static int gfar_poll(struct napi_struct *napi, int budget)
2797 struct gfar_priv_grp *gfargrp = container_of(napi,
2798 struct gfar_priv_grp, napi);
2799 struct gfar_private *priv = gfargrp->priv;
2800 struct gfar __iomem *regs = gfargrp->regs;
2801 struct gfar_priv_tx_q *tx_queue = NULL;
2802 struct gfar_priv_rx_q *rx_queue = NULL;
2803 int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;
2804 int tx_cleaned = 0, i, left_over_budget = budget;
2805 unsigned long serviced_queues = 0;
2808 num_queues = gfargrp->num_rx_queues;
2809 budget_per_queue = budget/num_queues;
2811 /* Clear IEVENT, so interrupts aren't called again
2812 * because of the packets that have already arrived */
2813 gfar_write(®s->ievent, IEVENT_RTX_MASK);
2815 while (num_queues && left_over_budget) {
2817 budget_per_queue = left_over_budget/num_queues;
2818 left_over_budget = 0;
2820 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2821 if (test_bit(i, &serviced_queues))
2823 rx_queue = priv->rx_queue[i];
2824 tx_queue = priv->tx_queue[rx_queue->qindex];
2826 tx_cleaned += gfar_clean_tx_ring(tx_queue);
2827 rx_cleaned_per_queue = gfar_clean_rx_ring(rx_queue,
2829 rx_cleaned += rx_cleaned_per_queue;
2830 if(rx_cleaned_per_queue < budget_per_queue) {
2831 left_over_budget = left_over_budget +
2832 (budget_per_queue - rx_cleaned_per_queue);
2833 set_bit(i, &serviced_queues);
2842 if (rx_cleaned < budget) {
2843 napi_complete(napi);
2845 /* Clear the halt bit in RSTAT */
2846 gfar_write(®s->rstat, gfargrp->rstat);
2848 gfar_write(®s->imask, IMASK_DEFAULT);
2850 /* If we are coalescing interrupts, update the timer */
2851 /* Otherwise, clear it */
2852 gfar_configure_coalescing(priv,
2853 gfargrp->rx_bit_map, gfargrp->tx_bit_map);
2859 #ifdef CONFIG_NET_POLL_CONTROLLER
2861 * Polling 'interrupt' - used by things like netconsole to send skbs
2862 * without having to re-enable interrupts. It's not called while
2863 * the interrupt routine is executing.
2865 static void gfar_netpoll(struct net_device *dev)
2867 struct gfar_private *priv = netdev_priv(dev);
2870 /* If the device has multiple interrupts, run tx/rx */
2871 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2872 for (i = 0; i < priv->num_grps; i++) {
2873 disable_irq(priv->gfargrp[i].interruptTransmit);
2874 disable_irq(priv->gfargrp[i].interruptReceive);
2875 disable_irq(priv->gfargrp[i].interruptError);
2876 gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2878 enable_irq(priv->gfargrp[i].interruptError);
2879 enable_irq(priv->gfargrp[i].interruptReceive);
2880 enable_irq(priv->gfargrp[i].interruptTransmit);
2883 for (i = 0; i < priv->num_grps; i++) {
2884 disable_irq(priv->gfargrp[i].interruptTransmit);
2885 gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2887 enable_irq(priv->gfargrp[i].interruptTransmit);
2893 /* The interrupt handler for devices with one interrupt */
2894 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
2896 struct gfar_priv_grp *gfargrp = grp_id;
2898 /* Save ievent for future reference */
2899 u32 events = gfar_read(&gfargrp->regs->ievent);
2901 /* Check for reception */
2902 if (events & IEVENT_RX_MASK)
2903 gfar_receive(irq, grp_id);
2905 /* Check for transmit completion */
2906 if (events & IEVENT_TX_MASK)
2907 gfar_transmit(irq, grp_id);
2909 /* Check for errors */
2910 if (events & IEVENT_ERR_MASK)
2911 gfar_error(irq, grp_id);
2916 /* Called every time the controller might need to be made
2917 * aware of new link state. The PHY code conveys this
2918 * information through variables in the phydev structure, and this
2919 * function converts those variables into the appropriate
2920 * register values, and can bring down the device if needed.
2922 static void adjust_link(struct net_device *dev)
2924 struct gfar_private *priv = netdev_priv(dev);
2925 struct gfar __iomem *regs = priv->gfargrp[0].regs;
2926 unsigned long flags;
2927 struct phy_device *phydev = priv->phydev;
2930 local_irq_save(flags);
2934 u32 tempval = gfar_read(®s->maccfg2);
2935 u32 ecntrl = gfar_read(®s->ecntrl);
2937 /* Now we make sure that we can be in full duplex mode.
2938 * If not, we operate in half-duplex mode. */
2939 if (phydev->duplex != priv->oldduplex) {
2941 if (!(phydev->duplex))
2942 tempval &= ~(MACCFG2_FULL_DUPLEX);
2944 tempval |= MACCFG2_FULL_DUPLEX;
2946 priv->oldduplex = phydev->duplex;
2949 if (phydev->speed != priv->oldspeed) {
2951 switch (phydev->speed) {
2954 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2956 ecntrl &= ~(ECNTRL_R100);
2961 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
2963 /* Reduced mode distinguishes
2964 * between 10 and 100 */
2965 if (phydev->speed == SPEED_100)
2966 ecntrl |= ECNTRL_R100;
2968 ecntrl &= ~(ECNTRL_R100);
2971 if (netif_msg_link(priv))
2973 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
2974 dev->name, phydev->speed);
2978 priv->oldspeed = phydev->speed;
2981 gfar_write(®s->maccfg2, tempval);
2982 gfar_write(®s->ecntrl, ecntrl);
2984 if (!priv->oldlink) {
2988 } else if (priv->oldlink) {
2992 priv->oldduplex = -1;
2995 if (new_state && netif_msg_link(priv))
2996 phy_print_status(phydev);
2998 local_irq_restore(flags);
3001 /* Update the hash table based on the current list of multicast
3002 * addresses we subscribe to. Also, change the promiscuity of
3003 * the device based on the flags (this function is called
3004 * whenever dev->flags is changed */
3005 static void gfar_set_multi(struct net_device *dev)
3007 struct netdev_hw_addr *ha;
3008 struct gfar_private *priv = netdev_priv(dev);
3009 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3012 if (dev->flags & IFF_PROMISC) {
3013 /* Set RCTRL to PROM */
3014 tempval = gfar_read(®s->rctrl);
3015 tempval |= RCTRL_PROM;
3016 gfar_write(®s->rctrl, tempval);
3018 /* Set RCTRL to not PROM */
3019 tempval = gfar_read(®s->rctrl);
3020 tempval &= ~(RCTRL_PROM);
3021 gfar_write(®s->rctrl, tempval);
3024 if (dev->flags & IFF_ALLMULTI) {
3025 /* Set the hash to rx all multicast frames */
3026 gfar_write(®s->igaddr0, 0xffffffff);
3027 gfar_write(®s->igaddr1, 0xffffffff);
3028 gfar_write(®s->igaddr2, 0xffffffff);
3029 gfar_write(®s->igaddr3, 0xffffffff);
3030 gfar_write(®s->igaddr4, 0xffffffff);
3031 gfar_write(®s->igaddr5, 0xffffffff);
3032 gfar_write(®s->igaddr6, 0xffffffff);
3033 gfar_write(®s->igaddr7, 0xffffffff);
3034 gfar_write(®s->gaddr0, 0xffffffff);
3035 gfar_write(®s->gaddr1, 0xffffffff);
3036 gfar_write(®s->gaddr2, 0xffffffff);
3037 gfar_write(®s->gaddr3, 0xffffffff);
3038 gfar_write(®s->gaddr4, 0xffffffff);
3039 gfar_write(®s->gaddr5, 0xffffffff);
3040 gfar_write(®s->gaddr6, 0xffffffff);
3041 gfar_write(®s->gaddr7, 0xffffffff);
3046 /* zero out the hash */
3047 gfar_write(®s->igaddr0, 0x0);
3048 gfar_write(®s->igaddr1, 0x0);
3049 gfar_write(®s->igaddr2, 0x0);
3050 gfar_write(®s->igaddr3, 0x0);
3051 gfar_write(®s->igaddr4, 0x0);
3052 gfar_write(®s->igaddr5, 0x0);
3053 gfar_write(®s->igaddr6, 0x0);
3054 gfar_write(®s->igaddr7, 0x0);
3055 gfar_write(®s->gaddr0, 0x0);
3056 gfar_write(®s->gaddr1, 0x0);
3057 gfar_write(®s->gaddr2, 0x0);
3058 gfar_write(®s->gaddr3, 0x0);
3059 gfar_write(®s->gaddr4, 0x0);
3060 gfar_write(®s->gaddr5, 0x0);
3061 gfar_write(®s->gaddr6, 0x0);
3062 gfar_write(®s->gaddr7, 0x0);
3064 /* If we have extended hash tables, we need to
3065 * clear the exact match registers to prepare for
3067 if (priv->extended_hash) {
3068 em_num = GFAR_EM_NUM + 1;
3069 gfar_clear_exact_match(dev);
3076 if (netdev_mc_empty(dev))
3079 /* Parse the list, and set the appropriate bits */
3080 netdev_for_each_mc_addr(ha, dev) {
3082 gfar_set_mac_for_addr(dev, idx, ha->addr);
3085 gfar_set_hash_for_addr(dev, ha->addr);
3091 /* Clears each of the exact match registers to zero, so they
3092 * don't interfere with normal reception */
3093 static void gfar_clear_exact_match(struct net_device *dev)
3096 static const u8 zero_arr[MAC_ADDR_LEN] = {0, 0, 0, 0, 0, 0};
3098 for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
3099 gfar_set_mac_for_addr(dev, idx, zero_arr);
3102 /* Set the appropriate hash bit for the given addr */
3103 /* The algorithm works like so:
3104 * 1) Take the Destination Address (ie the multicast address), and
3105 * do a CRC on it (little endian), and reverse the bits of the
3107 * 2) Use the 8 most significant bits as a hash into a 256-entry
3108 * table. The table is controlled through 8 32-bit registers:
3109 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
3110 * gaddr7. This means that the 3 most significant bits in the
3111 * hash index which gaddr register to use, and the 5 other bits
3112 * indicate which bit (assuming an IBM numbering scheme, which
3113 * for PowerPC (tm) is usually the case) in the register holds
3115 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3118 struct gfar_private *priv = netdev_priv(dev);
3119 u32 result = ether_crc(MAC_ADDR_LEN, addr);
3120 int width = priv->hash_width;
3121 u8 whichbit = (result >> (32 - width)) & 0x1f;
3122 u8 whichreg = result >> (32 - width + 5);
3123 u32 value = (1 << (31-whichbit));
3125 tempval = gfar_read(priv->hash_regs[whichreg]);
3127 gfar_write(priv->hash_regs[whichreg], tempval);
3131 /* There are multiple MAC Address register pairs on some controllers
3132 * This function sets the numth pair to a given address
3134 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3137 struct gfar_private *priv = netdev_priv(dev);
3138 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3140 char tmpbuf[MAC_ADDR_LEN];
3142 u32 __iomem *macptr = ®s->macstnaddr1;
3146 /* Now copy it into the mac registers backwards, cuz */
3147 /* little endian is silly */
3148 for (idx = 0; idx < MAC_ADDR_LEN; idx++)
3149 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
3151 gfar_write(macptr, *((u32 *) (tmpbuf)));
3153 tempval = *((u32 *) (tmpbuf + 4));
3155 gfar_write(macptr+1, tempval);
3158 /* GFAR error interrupt handler */
3159 static irqreturn_t gfar_error(int irq, void *grp_id)
3161 struct gfar_priv_grp *gfargrp = grp_id;
3162 struct gfar __iomem *regs = gfargrp->regs;
3163 struct gfar_private *priv= gfargrp->priv;
3164 struct net_device *dev = priv->ndev;
3166 /* Save ievent for future reference */
3167 u32 events = gfar_read(®s->ievent);
3170 gfar_write(®s->ievent, events & IEVENT_ERR_MASK);
3172 /* Magic Packet is not an error. */
3173 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3174 (events & IEVENT_MAG))
3175 events &= ~IEVENT_MAG;
3178 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3179 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
3180 dev->name, events, gfar_read(®s->imask));
3182 /* Update the error counters */
3183 if (events & IEVENT_TXE) {
3184 dev->stats.tx_errors++;
3186 if (events & IEVENT_LC)
3187 dev->stats.tx_window_errors++;
3188 if (events & IEVENT_CRL)
3189 dev->stats.tx_aborted_errors++;
3190 if (events & IEVENT_XFUN) {
3191 unsigned long flags;
3193 if (netif_msg_tx_err(priv))
3194 printk(KERN_DEBUG "%s: TX FIFO underrun, "
3195 "packet dropped.\n", dev->name);
3196 dev->stats.tx_dropped++;
3197 priv->extra_stats.tx_underrun++;
3199 local_irq_save(flags);
3202 /* Reactivate the Tx Queues */
3203 gfar_write(®s->tstat, gfargrp->tstat);
3206 local_irq_restore(flags);
3208 if (netif_msg_tx_err(priv))
3209 printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
3211 if (events & IEVENT_BSY) {
3212 dev->stats.rx_errors++;
3213 priv->extra_stats.rx_bsy++;
3215 gfar_receive(irq, grp_id);
3217 if (netif_msg_rx_err(priv))
3218 printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
3219 dev->name, gfar_read(®s->rstat));
3221 if (events & IEVENT_BABR) {
3222 dev->stats.rx_errors++;
3223 priv->extra_stats.rx_babr++;
3225 if (netif_msg_rx_err(priv))
3226 printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
3228 if (events & IEVENT_EBERR) {
3229 priv->extra_stats.eberr++;
3230 if (netif_msg_rx_err(priv))
3231 printk(KERN_DEBUG "%s: bus error\n", dev->name);
3233 if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
3234 printk(KERN_DEBUG "%s: control frame\n", dev->name);
3236 if (events & IEVENT_BABT) {
3237 priv->extra_stats.tx_babt++;
3238 if (netif_msg_tx_err(priv))
3239 printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
3244 static struct of_device_id gfar_match[] =
3248 .compatible = "gianfar",
3251 .compatible = "fsl,etsec2",
3255 MODULE_DEVICE_TABLE(of, gfar_match);
3257 /* Structure for a device driver */
3258 static struct of_platform_driver gfar_driver = {
3260 .name = "fsl-gianfar",
3261 .owner = THIS_MODULE,
3263 .of_match_table = gfar_match,
3265 .probe = gfar_probe,
3266 .remove = gfar_remove,
3269 static int __init gfar_init(void)
3271 return of_register_platform_driver(&gfar_driver);
3274 static void __exit gfar_exit(void)
3276 of_unregister_platform_driver(&gfar_driver);
3279 module_init(gfar_init);
3280 module_exit(gfar_exit);