2 * drivers/net/gianfar.c
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
10 * Maintainer: Kumar Gala
12 * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
13 * Copyright (c) 2007 MontaVista Software, Inc.
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * Gianfar: AKA Lambda Draconis, "Dragon"
28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
35 * last descriptor of the ring.
37 * When a packet is received, the RXF bit in the
38 * IEVENT register is set, triggering an interrupt when the
39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
42 * of frames or amount of time have passed). In NAPI, the
43 * interrupt handler will signal there is work to be done, and
44 * exit. This method will start at the last known empty
45 * descriptor, and process every subsequent descriptor until there
46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
64 #include <linux/kernel.h>
65 #include <linux/string.h>
66 #include <linux/errno.h>
67 #include <linux/unistd.h>
68 #include <linux/slab.h>
69 #include <linux/interrupt.h>
70 #include <linux/init.h>
71 #include <linux/delay.h>
72 #include <linux/netdevice.h>
73 #include <linux/etherdevice.h>
74 #include <linux/skbuff.h>
75 #include <linux/if_vlan.h>
76 #include <linux/spinlock.h>
78 #include <linux/of_mdio.h>
79 #include <linux/of_platform.h>
81 #include <linux/tcp.h>
82 #include <linux/udp.h>
87 #include <asm/uaccess.h>
88 #include <linux/module.h>
89 #include <linux/dma-mapping.h>
90 #include <linux/crc32.h>
91 #include <linux/mii.h>
92 #include <linux/phy.h>
93 #include <linux/phy_fixed.h>
97 #include "fsl_pq_mdio.h"
99 #define TX_TIMEOUT (1*HZ)
100 #undef BRIEF_GFAR_ERRORS
101 #undef VERBOSE_GFAR_ERRORS
103 const char gfar_driver_name[] = "Gianfar Ethernet";
104 const char gfar_driver_version[] = "1.3";
106 static int gfar_enet_open(struct net_device *dev);
107 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
108 static void gfar_reset_task(struct work_struct *work);
109 static void gfar_timeout(struct net_device *dev);
110 static int gfar_close(struct net_device *dev);
111 struct sk_buff *gfar_new_skb(struct net_device *dev);
112 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
113 struct sk_buff *skb);
114 static int gfar_set_mac_address(struct net_device *dev);
115 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
116 static irqreturn_t gfar_error(int irq, void *dev_id);
117 static irqreturn_t gfar_transmit(int irq, void *dev_id);
118 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
119 static void adjust_link(struct net_device *dev);
120 static void init_registers(struct net_device *dev);
121 static int init_phy(struct net_device *dev);
122 static int gfar_probe(struct of_device *ofdev,
123 const struct of_device_id *match);
124 static int gfar_remove(struct of_device *ofdev);
125 static void free_skb_resources(struct gfar_private *priv);
126 static void gfar_set_multi(struct net_device *dev);
127 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
128 static void gfar_configure_serdes(struct net_device *dev);
129 static int gfar_poll(struct napi_struct *napi, int budget);
130 #ifdef CONFIG_NET_POLL_CONTROLLER
131 static void gfar_netpoll(struct net_device *dev);
133 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
134 static int gfar_clean_tx_ring(struct net_device *dev);
135 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
137 static void gfar_vlan_rx_register(struct net_device *netdev,
138 struct vlan_group *grp);
139 void gfar_halt(struct net_device *dev);
140 static void gfar_halt_nodisable(struct net_device *dev);
141 void gfar_start(struct net_device *dev);
142 static void gfar_clear_exact_match(struct net_device *dev);
143 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
144 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
146 MODULE_AUTHOR("Freescale Semiconductor, Inc");
147 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
148 MODULE_LICENSE("GPL");
150 static void gfar_init_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
153 struct gfar_private *priv = netdev_priv(dev);
158 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
159 if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1)
160 lstatus |= BD_LFLAG(RXBD_WRAP);
164 bdp->lstatus = lstatus;
167 static int gfar_init_bds(struct net_device *ndev)
169 struct gfar_private *priv = netdev_priv(ndev);
174 /* Initialize some variables in our dev structure */
175 priv->num_txbdfree = priv->tx_ring_size;
176 priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
177 priv->cur_rx = priv->rx_bd_base;
178 priv->skb_curtx = priv->skb_dirtytx = 0;
181 /* Initialize Transmit Descriptor Ring */
182 txbdp = priv->tx_bd_base;
183 for (i = 0; i < priv->tx_ring_size; i++) {
189 /* Set the last descriptor in the ring to indicate wrap */
191 txbdp->status |= TXBD_WRAP;
193 rxbdp = priv->rx_bd_base;
194 for (i = 0; i < priv->rx_ring_size; i++) {
195 struct sk_buff *skb = priv->rx_skbuff[i];
198 gfar_init_rxbdp(ndev, rxbdp, rxbdp->bufPtr);
200 skb = gfar_new_skb(ndev);
202 pr_err("%s: Can't allocate RX buffers\n",
206 priv->rx_skbuff[i] = skb;
208 gfar_new_rxbdp(ndev, rxbdp, skb);
217 static int gfar_alloc_skb_resources(struct net_device *ndev)
221 struct gfar_private *priv = netdev_priv(ndev);
222 struct device *dev = &priv->ofdev->dev;
224 /* Allocate memory for the buffer descriptors */
225 vaddr = dma_alloc_coherent(dev,
226 sizeof(*priv->tx_bd_base) * priv->tx_ring_size +
227 sizeof(*priv->rx_bd_base) * priv->rx_ring_size,
228 &priv->tx_bd_dma_base, GFP_KERNEL);
230 if (netif_msg_ifup(priv))
231 pr_err("%s: Could not allocate buffer descriptors!\n",
236 priv->tx_bd_base = vaddr;
238 /* Start the rx descriptor ring where the tx ring leaves off */
239 vaddr = vaddr + sizeof(*priv->tx_bd_base) * priv->tx_ring_size;
240 priv->rx_bd_base = vaddr;
242 /* Setup the skbuff rings */
243 priv->tx_skbuff = kmalloc(sizeof(*priv->tx_skbuff) *
244 priv->tx_ring_size, GFP_KERNEL);
245 if (!priv->tx_skbuff) {
246 if (netif_msg_ifup(priv))
247 pr_err("%s: Could not allocate tx_skbuff\n",
252 for (i = 0; i < priv->tx_ring_size; i++)
253 priv->tx_skbuff[i] = NULL;
255 priv->rx_skbuff = kmalloc(sizeof(*priv->rx_skbuff) *
256 priv->rx_ring_size, GFP_KERNEL);
257 if (!priv->rx_skbuff) {
258 if (netif_msg_ifup(priv))
259 pr_err("%s: Could not allocate rx_skbuff\n",
264 for (i = 0; i < priv->rx_ring_size; i++)
265 priv->rx_skbuff[i] = NULL;
267 if (gfar_init_bds(ndev))
273 free_skb_resources(priv);
277 static void gfar_init_mac(struct net_device *ndev)
279 struct gfar_private *priv = netdev_priv(ndev);
280 struct gfar __iomem *regs = priv->regs;
285 /* enet DMA only understands physical addresses */
286 gfar_write(®s->tbase0, priv->tx_bd_dma_base);
287 gfar_write(®s->rbase0, priv->tx_bd_dma_base +
288 sizeof(*priv->tx_bd_base) *
291 /* Configure the coalescing support */
292 gfar_write(®s->txic, 0);
293 if (priv->txcoalescing)
294 gfar_write(®s->txic, priv->txic);
296 gfar_write(®s->rxic, 0);
297 if (priv->rxcoalescing)
298 gfar_write(®s->rxic, priv->rxic);
300 if (priv->rx_csum_enable)
301 rctrl |= RCTRL_CHECKSUMMING;
303 if (priv->extended_hash) {
304 rctrl |= RCTRL_EXTHASH;
306 gfar_clear_exact_match(ndev);
311 rctrl &= ~RCTRL_PAL_MASK;
312 rctrl |= RCTRL_PADDING(priv->padding);
315 /* keep vlan related bits if it's enabled */
317 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
318 tctrl |= TCTRL_VLINS;
321 /* Init rctrl based on our settings */
322 gfar_write(®s->rctrl, rctrl);
324 if (ndev->features & NETIF_F_IP_CSUM)
325 tctrl |= TCTRL_INIT_CSUM;
327 gfar_write(®s->tctrl, tctrl);
329 /* Set the extraction length and index */
330 attrs = ATTRELI_EL(priv->rx_stash_size) |
331 ATTRELI_EI(priv->rx_stash_index);
333 gfar_write(®s->attreli, attrs);
335 /* Start with defaults, and add stashing or locking
336 * depending on the approprate variables */
337 attrs = ATTR_INIT_SETTINGS;
339 if (priv->bd_stash_en)
340 attrs |= ATTR_BDSTASH;
342 if (priv->rx_stash_size != 0)
343 attrs |= ATTR_BUFSTASH;
345 gfar_write(®s->attr, attrs);
347 gfar_write(®s->fifo_tx_thr, priv->fifo_threshold);
348 gfar_write(®s->fifo_tx_starve, priv->fifo_starve);
349 gfar_write(®s->fifo_tx_starve_shutoff, priv->fifo_starve_off);
352 static const struct net_device_ops gfar_netdev_ops = {
353 .ndo_open = gfar_enet_open,
354 .ndo_start_xmit = gfar_start_xmit,
355 .ndo_stop = gfar_close,
356 .ndo_change_mtu = gfar_change_mtu,
357 .ndo_set_multicast_list = gfar_set_multi,
358 .ndo_tx_timeout = gfar_timeout,
359 .ndo_do_ioctl = gfar_ioctl,
360 .ndo_vlan_rx_register = gfar_vlan_rx_register,
361 .ndo_set_mac_address = eth_mac_addr,
362 .ndo_validate_addr = eth_validate_addr,
363 #ifdef CONFIG_NET_POLL_CONTROLLER
364 .ndo_poll_controller = gfar_netpoll,
368 /* Returns 1 if incoming frames use an FCB */
369 static inline int gfar_uses_fcb(struct gfar_private *priv)
371 return priv->vlgrp || priv->rx_csum_enable;
374 static int gfar_of_init(struct net_device *dev)
378 const void *mac_addr;
381 struct gfar_private *priv = netdev_priv(dev);
382 struct device_node *np = priv->node;
384 const u32 *stash_len;
385 const u32 *stash_idx;
387 if (!np || !of_device_is_available(np))
390 /* get a pointer to the register memory */
391 addr = of_translate_address(np, of_get_address(np, 0, &size, NULL));
392 priv->regs = ioremap(addr, size);
394 if (priv->regs == NULL)
397 priv->interruptTransmit = irq_of_parse_and_map(np, 0);
399 model = of_get_property(np, "model", NULL);
401 /* If we aren't the FEC we have multiple interrupts */
402 if (model && strcasecmp(model, "FEC")) {
403 priv->interruptReceive = irq_of_parse_and_map(np, 1);
405 priv->interruptError = irq_of_parse_and_map(np, 2);
407 if (priv->interruptTransmit < 0 ||
408 priv->interruptReceive < 0 ||
409 priv->interruptError < 0) {
415 stash = of_get_property(np, "bd-stash", NULL);
418 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
419 priv->bd_stash_en = 1;
422 stash_len = of_get_property(np, "rx-stash-len", NULL);
425 priv->rx_stash_size = *stash_len;
427 stash_idx = of_get_property(np, "rx-stash-idx", NULL);
430 priv->rx_stash_index = *stash_idx;
432 if (stash_len || stash_idx)
433 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
435 mac_addr = of_get_mac_address(np);
437 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
439 if (model && !strcasecmp(model, "TSEC"))
441 FSL_GIANFAR_DEV_HAS_GIGABIT |
442 FSL_GIANFAR_DEV_HAS_COALESCE |
443 FSL_GIANFAR_DEV_HAS_RMON |
444 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
445 if (model && !strcasecmp(model, "eTSEC"))
447 FSL_GIANFAR_DEV_HAS_GIGABIT |
448 FSL_GIANFAR_DEV_HAS_COALESCE |
449 FSL_GIANFAR_DEV_HAS_RMON |
450 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
451 FSL_GIANFAR_DEV_HAS_PADDING |
452 FSL_GIANFAR_DEV_HAS_CSUM |
453 FSL_GIANFAR_DEV_HAS_VLAN |
454 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
455 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH;
457 ctype = of_get_property(np, "phy-connection-type", NULL);
459 /* We only care about rgmii-id. The rest are autodetected */
460 if (ctype && !strcmp(ctype, "rgmii-id"))
461 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
463 priv->interface = PHY_INTERFACE_MODE_MII;
465 if (of_get_property(np, "fsl,magic-packet", NULL))
466 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
468 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
470 /* Find the TBI PHY. If it's not there, we don't support SGMII */
471 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
480 /* Ioctl MII Interface */
481 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
483 struct gfar_private *priv = netdev_priv(dev);
485 if (!netif_running(dev))
491 return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
494 /* Set up the ethernet device structure, private data,
495 * and anything else we need before we start */
496 static int gfar_probe(struct of_device *ofdev,
497 const struct of_device_id *match)
500 struct net_device *dev = NULL;
501 struct gfar_private *priv = NULL;
505 /* Create an ethernet device instance */
506 dev = alloc_etherdev(sizeof (*priv));
511 priv = netdev_priv(dev);
514 priv->node = ofdev->node;
515 SET_NETDEV_DEV(dev, &ofdev->dev);
517 err = gfar_of_init(dev);
522 spin_lock_init(&priv->txlock);
523 spin_lock_init(&priv->rxlock);
524 spin_lock_init(&priv->bflock);
525 INIT_WORK(&priv->reset_task, gfar_reset_task);
527 dev_set_drvdata(&ofdev->dev, priv);
529 /* Stop the DMA engine now, in case it was running before */
530 /* (The firmware could have used it, and left it running). */
533 /* Reset MAC layer */
534 gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
536 /* We need to delay at least 3 TX clocks */
539 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
540 gfar_write(&priv->regs->maccfg1, tempval);
542 /* Initialize MACCFG2. */
543 gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
545 /* Initialize ECNTRL */
546 gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
548 /* Set the dev->base_addr to the gfar reg region */
549 dev->base_addr = (unsigned long) (priv->regs);
551 SET_NETDEV_DEV(dev, &ofdev->dev);
553 /* Fill in the dev structure */
554 dev->watchdog_timeo = TX_TIMEOUT;
555 netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT);
558 dev->netdev_ops = &gfar_netdev_ops;
559 dev->ethtool_ops = &gfar_ethtool_ops;
561 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
562 priv->rx_csum_enable = 1;
563 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;
565 priv->rx_csum_enable = 0;
569 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)
570 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
572 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
573 priv->extended_hash = 1;
574 priv->hash_width = 9;
576 priv->hash_regs[0] = &priv->regs->igaddr0;
577 priv->hash_regs[1] = &priv->regs->igaddr1;
578 priv->hash_regs[2] = &priv->regs->igaddr2;
579 priv->hash_regs[3] = &priv->regs->igaddr3;
580 priv->hash_regs[4] = &priv->regs->igaddr4;
581 priv->hash_regs[5] = &priv->regs->igaddr5;
582 priv->hash_regs[6] = &priv->regs->igaddr6;
583 priv->hash_regs[7] = &priv->regs->igaddr7;
584 priv->hash_regs[8] = &priv->regs->gaddr0;
585 priv->hash_regs[9] = &priv->regs->gaddr1;
586 priv->hash_regs[10] = &priv->regs->gaddr2;
587 priv->hash_regs[11] = &priv->regs->gaddr3;
588 priv->hash_regs[12] = &priv->regs->gaddr4;
589 priv->hash_regs[13] = &priv->regs->gaddr5;
590 priv->hash_regs[14] = &priv->regs->gaddr6;
591 priv->hash_regs[15] = &priv->regs->gaddr7;
594 priv->extended_hash = 0;
595 priv->hash_width = 8;
597 priv->hash_regs[0] = &priv->regs->gaddr0;
598 priv->hash_regs[1] = &priv->regs->gaddr1;
599 priv->hash_regs[2] = &priv->regs->gaddr2;
600 priv->hash_regs[3] = &priv->regs->gaddr3;
601 priv->hash_regs[4] = &priv->regs->gaddr4;
602 priv->hash_regs[5] = &priv->regs->gaddr5;
603 priv->hash_regs[6] = &priv->regs->gaddr6;
604 priv->hash_regs[7] = &priv->regs->gaddr7;
607 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
608 priv->padding = DEFAULT_PADDING;
612 if (dev->features & NETIF_F_IP_CSUM)
613 dev->hard_header_len += GMAC_FCB_LEN;
615 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
616 priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
617 priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
618 priv->num_txbdfree = DEFAULT_TX_RING_SIZE;
620 priv->txcoalescing = DEFAULT_TX_COALESCE;
621 priv->txic = DEFAULT_TXIC;
622 priv->rxcoalescing = DEFAULT_RX_COALESCE;
623 priv->rxic = DEFAULT_RXIC;
625 /* Enable most messages by default */
626 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
628 /* Carrier starts down, phylib will bring it up */
629 netif_carrier_off(dev);
631 err = register_netdev(dev);
634 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
639 device_init_wakeup(&dev->dev,
640 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
642 /* fill out IRQ number and name fields */
643 len_devname = strlen(dev->name);
644 strncpy(&priv->int_name_tx[0], dev->name, len_devname);
645 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
646 strncpy(&priv->int_name_tx[len_devname],
647 "_tx", sizeof("_tx") + 1);
649 strncpy(&priv->int_name_rx[0], dev->name, len_devname);
650 strncpy(&priv->int_name_rx[len_devname],
651 "_rx", sizeof("_rx") + 1);
653 strncpy(&priv->int_name_er[0], dev->name, len_devname);
654 strncpy(&priv->int_name_er[len_devname],
655 "_er", sizeof("_er") + 1);
657 priv->int_name_tx[len_devname] = '\0';
659 /* Create all the sysfs files */
660 gfar_init_sysfs(dev);
662 /* Print out the device info */
663 printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
665 /* Even more device info helps when determining which kernel */
666 /* provided which set of benchmarks. */
667 printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
668 printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
669 dev->name, priv->rx_ring_size, priv->tx_ring_size);
677 of_node_put(priv->phy_node);
679 of_node_put(priv->tbi_node);
684 static int gfar_remove(struct of_device *ofdev)
686 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
689 of_node_put(priv->phy_node);
691 of_node_put(priv->tbi_node);
693 dev_set_drvdata(&ofdev->dev, NULL);
695 unregister_netdev(priv->ndev);
697 free_netdev(priv->ndev);
704 static int gfar_suspend(struct device *dev)
706 struct gfar_private *priv = dev_get_drvdata(dev);
707 struct net_device *ndev = priv->ndev;
711 int magic_packet = priv->wol_en &&
712 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
714 netif_device_detach(ndev);
716 if (netif_running(ndev)) {
717 spin_lock_irqsave(&priv->txlock, flags);
718 spin_lock(&priv->rxlock);
720 gfar_halt_nodisable(ndev);
722 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
723 tempval = gfar_read(&priv->regs->maccfg1);
725 tempval &= ~MACCFG1_TX_EN;
728 tempval &= ~MACCFG1_RX_EN;
730 gfar_write(&priv->regs->maccfg1, tempval);
732 spin_unlock(&priv->rxlock);
733 spin_unlock_irqrestore(&priv->txlock, flags);
735 napi_disable(&priv->napi);
738 /* Enable interrupt on Magic Packet */
739 gfar_write(&priv->regs->imask, IMASK_MAG);
741 /* Enable Magic Packet mode */
742 tempval = gfar_read(&priv->regs->maccfg2);
743 tempval |= MACCFG2_MPEN;
744 gfar_write(&priv->regs->maccfg2, tempval);
746 phy_stop(priv->phydev);
753 static int gfar_resume(struct device *dev)
755 struct gfar_private *priv = dev_get_drvdata(dev);
756 struct net_device *ndev = priv->ndev;
759 int magic_packet = priv->wol_en &&
760 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
762 if (!netif_running(ndev)) {
763 netif_device_attach(ndev);
767 if (!magic_packet && priv->phydev)
768 phy_start(priv->phydev);
770 /* Disable Magic Packet mode, in case something
774 spin_lock_irqsave(&priv->txlock, flags);
775 spin_lock(&priv->rxlock);
777 tempval = gfar_read(&priv->regs->maccfg2);
778 tempval &= ~MACCFG2_MPEN;
779 gfar_write(&priv->regs->maccfg2, tempval);
783 spin_unlock(&priv->rxlock);
784 spin_unlock_irqrestore(&priv->txlock, flags);
786 netif_device_attach(ndev);
788 napi_enable(&priv->napi);
793 static int gfar_restore(struct device *dev)
795 struct gfar_private *priv = dev_get_drvdata(dev);
796 struct net_device *ndev = priv->ndev;
798 if (!netif_running(ndev))
802 init_registers(ndev);
803 gfar_set_mac_address(ndev);
809 priv->oldduplex = -1;
812 phy_start(priv->phydev);
814 netif_device_attach(ndev);
815 napi_enable(&priv->napi);
820 static struct dev_pm_ops gfar_pm_ops = {
821 .suspend = gfar_suspend,
822 .resume = gfar_resume,
823 .freeze = gfar_suspend,
825 .restore = gfar_restore,
828 #define GFAR_PM_OPS (&gfar_pm_ops)
830 static int gfar_legacy_suspend(struct of_device *ofdev, pm_message_t state)
832 return gfar_suspend(&ofdev->dev);
835 static int gfar_legacy_resume(struct of_device *ofdev)
837 return gfar_resume(&ofdev->dev);
842 #define GFAR_PM_OPS NULL
843 #define gfar_legacy_suspend NULL
844 #define gfar_legacy_resume NULL
848 /* Reads the controller's registers to determine what interface
849 * connects it to the PHY.
851 static phy_interface_t gfar_get_interface(struct net_device *dev)
853 struct gfar_private *priv = netdev_priv(dev);
854 u32 ecntrl = gfar_read(&priv->regs->ecntrl);
856 if (ecntrl & ECNTRL_SGMII_MODE)
857 return PHY_INTERFACE_MODE_SGMII;
859 if (ecntrl & ECNTRL_TBI_MODE) {
860 if (ecntrl & ECNTRL_REDUCED_MODE)
861 return PHY_INTERFACE_MODE_RTBI;
863 return PHY_INTERFACE_MODE_TBI;
866 if (ecntrl & ECNTRL_REDUCED_MODE) {
867 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
868 return PHY_INTERFACE_MODE_RMII;
870 phy_interface_t interface = priv->interface;
873 * This isn't autodetected right now, so it must
874 * be set by the device tree or platform code.
876 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
877 return PHY_INTERFACE_MODE_RGMII_ID;
879 return PHY_INTERFACE_MODE_RGMII;
883 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
884 return PHY_INTERFACE_MODE_GMII;
886 return PHY_INTERFACE_MODE_MII;
890 /* Initializes driver's PHY state, and attaches to the PHY.
891 * Returns 0 on success.
893 static int init_phy(struct net_device *dev)
895 struct gfar_private *priv = netdev_priv(dev);
896 uint gigabit_support =
897 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
898 SUPPORTED_1000baseT_Full : 0;
899 phy_interface_t interface;
903 priv->oldduplex = -1;
905 interface = gfar_get_interface(dev);
907 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
910 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
913 dev_err(&dev->dev, "could not attach to PHY\n");
917 if (interface == PHY_INTERFACE_MODE_SGMII)
918 gfar_configure_serdes(dev);
920 /* Remove any features not supported by the controller */
921 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
922 priv->phydev->advertising = priv->phydev->supported;
928 * Initialize TBI PHY interface for communicating with the
929 * SERDES lynx PHY on the chip. We communicate with this PHY
930 * through the MDIO bus on each controller, treating it as a
931 * "normal" PHY at the address found in the TBIPA register. We assume
932 * that the TBIPA register is valid. Either the MDIO bus code will set
933 * it to a value that doesn't conflict with other PHYs on the bus, or the
934 * value doesn't matter, as there are no other PHYs on the bus.
936 static void gfar_configure_serdes(struct net_device *dev)
938 struct gfar_private *priv = netdev_priv(dev);
939 struct phy_device *tbiphy;
941 if (!priv->tbi_node) {
942 dev_warn(&dev->dev, "error: SGMII mode requires that the "
943 "device tree specify a tbi-handle\n");
947 tbiphy = of_phy_find_device(priv->tbi_node);
949 dev_err(&dev->dev, "error: Could not get TBI device\n");
954 * If the link is already up, we must already be ok, and don't need to
955 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
956 * everything for us? Resetting it takes the link down and requires
957 * several seconds for it to come back.
959 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
962 /* Single clk mode, mii mode off(for serdes communication) */
963 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
965 phy_write(tbiphy, MII_ADVERTISE,
966 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
967 ADVERTISE_1000XPSE_ASYM);
969 phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE |
970 BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
973 static void init_registers(struct net_device *dev)
975 struct gfar_private *priv = netdev_priv(dev);
978 gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
980 /* Initialize IMASK */
981 gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
983 /* Init hash registers to zero */
984 gfar_write(&priv->regs->igaddr0, 0);
985 gfar_write(&priv->regs->igaddr1, 0);
986 gfar_write(&priv->regs->igaddr2, 0);
987 gfar_write(&priv->regs->igaddr3, 0);
988 gfar_write(&priv->regs->igaddr4, 0);
989 gfar_write(&priv->regs->igaddr5, 0);
990 gfar_write(&priv->regs->igaddr6, 0);
991 gfar_write(&priv->regs->igaddr7, 0);
993 gfar_write(&priv->regs->gaddr0, 0);
994 gfar_write(&priv->regs->gaddr1, 0);
995 gfar_write(&priv->regs->gaddr2, 0);
996 gfar_write(&priv->regs->gaddr3, 0);
997 gfar_write(&priv->regs->gaddr4, 0);
998 gfar_write(&priv->regs->gaddr5, 0);
999 gfar_write(&priv->regs->gaddr6, 0);
1000 gfar_write(&priv->regs->gaddr7, 0);
1002 /* Zero out the rmon mib registers if it has them */
1003 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1004 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
1006 /* Mask off the CAM interrupts */
1007 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
1008 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
1011 /* Initialize the max receive buffer length */
1012 gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1014 /* Initialize the Minimum Frame Length Register */
1015 gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
1019 /* Halt the receive and transmit queues */
1020 static void gfar_halt_nodisable(struct net_device *dev)
1022 struct gfar_private *priv = netdev_priv(dev);
1023 struct gfar __iomem *regs = priv->regs;
1026 /* Mask all interrupts */
1027 gfar_write(®s->imask, IMASK_INIT_CLEAR);
1029 /* Clear all interrupts */
1030 gfar_write(®s->ievent, IEVENT_INIT_CLEAR);
1032 /* Stop the DMA, and wait for it to stop */
1033 tempval = gfar_read(&priv->regs->dmactrl);
1034 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
1035 != (DMACTRL_GRS | DMACTRL_GTS)) {
1036 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1037 gfar_write(&priv->regs->dmactrl, tempval);
1039 while (!(gfar_read(&priv->regs->ievent) &
1040 (IEVENT_GRSC | IEVENT_GTSC)))
1045 /* Halt the receive and transmit queues */
1046 void gfar_halt(struct net_device *dev)
1048 struct gfar_private *priv = netdev_priv(dev);
1049 struct gfar __iomem *regs = priv->regs;
1052 gfar_halt_nodisable(dev);
1054 /* Disable Rx and Tx */
1055 tempval = gfar_read(®s->maccfg1);
1056 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1057 gfar_write(®s->maccfg1, tempval);
1060 void stop_gfar(struct net_device *dev)
1062 struct gfar_private *priv = netdev_priv(dev);
1063 unsigned long flags;
1065 phy_stop(priv->phydev);
1068 spin_lock_irqsave(&priv->txlock, flags);
1069 spin_lock(&priv->rxlock);
1073 spin_unlock(&priv->rxlock);
1074 spin_unlock_irqrestore(&priv->txlock, flags);
1077 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1078 free_irq(priv->interruptError, dev);
1079 free_irq(priv->interruptTransmit, dev);
1080 free_irq(priv->interruptReceive, dev);
1082 free_irq(priv->interruptTransmit, dev);
1085 free_skb_resources(priv);
1088 /* If there are any tx skbs or rx skbs still around, free them.
1089 * Then free tx_skbuff and rx_skbuff */
1090 static void free_skb_resources(struct gfar_private *priv)
1092 struct device *dev = &priv->ofdev->dev;
1093 struct rxbd8 *rxbdp;
1094 struct txbd8 *txbdp;
1097 /* Go through all the buffer descriptors and free their data buffers */
1098 txbdp = priv->tx_bd_base;
1100 if (!priv->tx_skbuff)
1101 goto skip_tx_skbuff;
1103 for (i = 0; i < priv->tx_ring_size; i++) {
1104 if (!priv->tx_skbuff[i])
1107 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
1108 txbdp->length, DMA_TO_DEVICE);
1110 for (j = 0; j < skb_shinfo(priv->tx_skbuff[i])->nr_frags; j++) {
1112 dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
1113 txbdp->length, DMA_TO_DEVICE);
1116 dev_kfree_skb_any(priv->tx_skbuff[i]);
1117 priv->tx_skbuff[i] = NULL;
1120 kfree(priv->tx_skbuff);
1123 rxbdp = priv->rx_bd_base;
1125 if (!priv->rx_skbuff)
1126 goto skip_rx_skbuff;
1128 for (i = 0; i < priv->rx_ring_size; i++) {
1129 if (priv->rx_skbuff[i]) {
1130 dma_unmap_single(&priv->ofdev->dev, rxbdp->bufPtr,
1131 priv->rx_buffer_size,
1133 dev_kfree_skb_any(priv->rx_skbuff[i]);
1134 priv->rx_skbuff[i] = NULL;
1142 kfree(priv->rx_skbuff);
1145 dma_free_coherent(dev, sizeof(*txbdp) * priv->tx_ring_size +
1146 sizeof(*rxbdp) * priv->rx_ring_size,
1147 priv->tx_bd_base, priv->tx_bd_dma_base);
1150 void gfar_start(struct net_device *dev)
1152 struct gfar_private *priv = netdev_priv(dev);
1153 struct gfar __iomem *regs = priv->regs;
1156 /* Enable Rx and Tx in MACCFG1 */
1157 tempval = gfar_read(®s->maccfg1);
1158 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1159 gfar_write(®s->maccfg1, tempval);
1161 /* Initialize DMACTRL to have WWR and WOP */
1162 tempval = gfar_read(&priv->regs->dmactrl);
1163 tempval |= DMACTRL_INIT_SETTINGS;
1164 gfar_write(&priv->regs->dmactrl, tempval);
1166 /* Make sure we aren't stopped */
1167 tempval = gfar_read(&priv->regs->dmactrl);
1168 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1169 gfar_write(&priv->regs->dmactrl, tempval);
1171 /* Clear THLT/RHLT, so that the DMA starts polling now */
1172 gfar_write(®s->tstat, TSTAT_CLEAR_THALT);
1173 gfar_write(®s->rstat, RSTAT_CLEAR_RHALT);
1175 /* Unmask the interrupts we look for */
1176 gfar_write(®s->imask, IMASK_DEFAULT);
1178 dev->trans_start = jiffies;
1181 /* Bring the controller up and running */
1182 int startup_gfar(struct net_device *ndev)
1184 struct gfar_private *priv = netdev_priv(ndev);
1185 struct gfar __iomem *regs = priv->regs;
1188 gfar_write(®s->imask, IMASK_INIT_CLEAR);
1190 err = gfar_alloc_skb_resources(ndev);
1194 gfar_init_mac(ndev);
1196 /* If the device has multiple interrupts, register for
1197 * them. Otherwise, only register for the one */
1198 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1199 /* Install our interrupt handlers for Error,
1200 * Transmit, and Receive */
1201 err = request_irq(priv->interruptError, gfar_error, 0,
1202 priv->int_name_er, ndev);
1204 if (netif_msg_intr(priv))
1205 pr_err("%s: Can't get IRQ %d\n", ndev->name,
1206 priv->interruptError);
1210 err = request_irq(priv->interruptTransmit, gfar_transmit, 0,
1211 priv->int_name_tx, ndev);
1213 if (netif_msg_intr(priv))
1214 pr_err("%s: Can't get IRQ %d\n", ndev->name,
1215 priv->interruptTransmit);
1219 err = request_irq(priv->interruptReceive, gfar_receive, 0,
1220 priv->int_name_rx, ndev);
1222 if (netif_msg_intr(priv))
1223 pr_err("%s: Can't get IRQ %d (receive0)\n",
1224 ndev->name, priv->interruptReceive);
1228 err = request_irq(priv->interruptTransmit, gfar_interrupt,
1229 0, priv->int_name_tx, ndev);
1231 if (netif_msg_intr(priv))
1232 pr_err("%s: Can't get IRQ %d\n", ndev->name,
1233 priv->interruptTransmit);
1238 /* Start the controller */
1241 phy_start(priv->phydev);
1246 free_irq(priv->interruptTransmit, ndev);
1248 free_irq(priv->interruptError, ndev);
1250 free_skb_resources(priv);
1254 /* Called when something needs to use the ethernet device */
1255 /* Returns 0 for success. */
1256 static int gfar_enet_open(struct net_device *dev)
1258 struct gfar_private *priv = netdev_priv(dev);
1261 napi_enable(&priv->napi);
1263 skb_queue_head_init(&priv->rx_recycle);
1265 /* Initialize a bunch of registers */
1266 init_registers(dev);
1268 gfar_set_mac_address(dev);
1270 err = init_phy(dev);
1273 napi_disable(&priv->napi);
1277 err = startup_gfar(dev);
1279 napi_disable(&priv->napi);
1283 netif_start_queue(dev);
1285 device_set_wakeup_enable(&dev->dev, priv->wol_en);
1290 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1292 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1294 memset(fcb, 0, GMAC_FCB_LEN);
1299 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1303 /* If we're here, it's a IP packet with a TCP or UDP
1304 * payload. We set it to checksum, using a pseudo-header
1307 flags = TXFCB_DEFAULT;
1309 /* Tell the controller what the protocol is */
1310 /* And provide the already calculated phcs */
1311 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1313 fcb->phcs = udp_hdr(skb)->check;
1315 fcb->phcs = tcp_hdr(skb)->check;
1317 /* l3os is the distance between the start of the
1318 * frame (skb->data) and the start of the IP hdr.
1319 * l4os is the distance between the start of the
1320 * l3 hdr and the l4 hdr */
1321 fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
1322 fcb->l4os = skb_network_header_len(skb);
1327 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1329 fcb->flags |= TXFCB_VLN;
1330 fcb->vlctl = vlan_tx_tag_get(skb);
1333 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
1334 struct txbd8 *base, int ring_size)
1336 struct txbd8 *new_bd = bdp + stride;
1338 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
1341 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
1344 return skip_txbd(bdp, 1, base, ring_size);
1347 /* This is called by the kernel when a frame is ready for transmission. */
1348 /* It is pointed to by the dev->hard_start_xmit function pointer */
1349 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1351 struct gfar_private *priv = netdev_priv(dev);
1352 struct txfcb *fcb = NULL;
1353 struct txbd8 *txbdp, *txbdp_start, *base;
1357 unsigned long flags;
1358 unsigned int nr_frags, length;
1360 base = priv->tx_bd_base;
1362 /* make space for additional header when fcb is needed */
1363 if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
1364 (priv->vlgrp && vlan_tx_tag_present(skb))) &&
1365 (skb_headroom(skb) < GMAC_FCB_LEN)) {
1366 struct sk_buff *skb_new;
1368 skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN);
1370 dev->stats.tx_errors++;
1372 return NETDEV_TX_OK;
1378 /* total number of fragments in the SKB */
1379 nr_frags = skb_shinfo(skb)->nr_frags;
1381 spin_lock_irqsave(&priv->txlock, flags);
1383 /* check if there is space to queue this packet */
1384 if ((nr_frags+1) > priv->num_txbdfree) {
1385 /* no space, stop the queue */
1386 netif_stop_queue(dev);
1387 dev->stats.tx_fifo_errors++;
1388 spin_unlock_irqrestore(&priv->txlock, flags);
1389 return NETDEV_TX_BUSY;
1392 /* Update transmit stats */
1393 dev->stats.tx_bytes += skb->len;
1395 txbdp = txbdp_start = priv->cur_tx;
1397 if (nr_frags == 0) {
1398 lstatus = txbdp->lstatus | BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1400 /* Place the fragment addresses and lengths into the TxBDs */
1401 for (i = 0; i < nr_frags; i++) {
1402 /* Point at the next BD, wrapping as needed */
1403 txbdp = next_txbd(txbdp, base, priv->tx_ring_size);
1405 length = skb_shinfo(skb)->frags[i].size;
1407 lstatus = txbdp->lstatus | length |
1408 BD_LFLAG(TXBD_READY);
1410 /* Handle the last BD specially */
1411 if (i == nr_frags - 1)
1412 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1414 bufaddr = dma_map_page(&priv->ofdev->dev,
1415 skb_shinfo(skb)->frags[i].page,
1416 skb_shinfo(skb)->frags[i].page_offset,
1420 /* set the TxBD length and buffer pointer */
1421 txbdp->bufPtr = bufaddr;
1422 txbdp->lstatus = lstatus;
1425 lstatus = txbdp_start->lstatus;
1428 /* Set up checksumming */
1429 if (CHECKSUM_PARTIAL == skb->ip_summed) {
1430 fcb = gfar_add_fcb(skb);
1431 lstatus |= BD_LFLAG(TXBD_TOE);
1432 gfar_tx_checksum(skb, fcb);
1435 if (priv->vlgrp && vlan_tx_tag_present(skb)) {
1436 if (unlikely(NULL == fcb)) {
1437 fcb = gfar_add_fcb(skb);
1438 lstatus |= BD_LFLAG(TXBD_TOE);
1441 gfar_tx_vlan(skb, fcb);
1444 /* setup the TxBD length and buffer pointer for the first BD */
1445 priv->tx_skbuff[priv->skb_curtx] = skb;
1446 txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
1447 skb_headlen(skb), DMA_TO_DEVICE);
1449 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
1452 * The powerpc-specific eieio() is used, as wmb() has too strong
1453 * semantics (it requires synchronization between cacheable and
1454 * uncacheable mappings, which eieio doesn't provide and which we
1455 * don't need), thus requiring a more expensive sync instruction. At
1456 * some point, the set of architecture-independent barrier functions
1457 * should be expanded to include weaker barriers.
1461 txbdp_start->lstatus = lstatus;
1463 /* Update the current skb pointer to the next entry we will use
1464 * (wrapping if necessary) */
1465 priv->skb_curtx = (priv->skb_curtx + 1) &
1466 TX_RING_MOD_MASK(priv->tx_ring_size);
1468 priv->cur_tx = next_txbd(txbdp, base, priv->tx_ring_size);
1470 /* reduce TxBD free count */
1471 priv->num_txbdfree -= (nr_frags + 1);
1473 dev->trans_start = jiffies;
1475 /* If the next BD still needs to be cleaned up, then the bds
1476 are full. We need to tell the kernel to stop sending us stuff. */
1477 if (!priv->num_txbdfree) {
1478 netif_stop_queue(dev);
1480 dev->stats.tx_fifo_errors++;
1483 /* Tell the DMA to go go go */
1484 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1487 spin_unlock_irqrestore(&priv->txlock, flags);
1489 return NETDEV_TX_OK;
1492 /* Stops the kernel queue, and halts the controller */
1493 static int gfar_close(struct net_device *dev)
1495 struct gfar_private *priv = netdev_priv(dev);
1497 napi_disable(&priv->napi);
1499 skb_queue_purge(&priv->rx_recycle);
1500 cancel_work_sync(&priv->reset_task);
1503 /* Disconnect from the PHY */
1504 phy_disconnect(priv->phydev);
1505 priv->phydev = NULL;
1507 netif_stop_queue(dev);
1512 /* Changes the mac address if the controller is not running. */
1513 static int gfar_set_mac_address(struct net_device *dev)
1515 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1521 /* Enables and disables VLAN insertion/extraction */
1522 static void gfar_vlan_rx_register(struct net_device *dev,
1523 struct vlan_group *grp)
1525 struct gfar_private *priv = netdev_priv(dev);
1526 unsigned long flags;
1529 spin_lock_irqsave(&priv->rxlock, flags);
1534 /* Enable VLAN tag insertion */
1535 tempval = gfar_read(&priv->regs->tctrl);
1536 tempval |= TCTRL_VLINS;
1538 gfar_write(&priv->regs->tctrl, tempval);
1540 /* Enable VLAN tag extraction */
1541 tempval = gfar_read(&priv->regs->rctrl);
1542 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
1543 gfar_write(&priv->regs->rctrl, tempval);
1545 /* Disable VLAN tag insertion */
1546 tempval = gfar_read(&priv->regs->tctrl);
1547 tempval &= ~TCTRL_VLINS;
1548 gfar_write(&priv->regs->tctrl, tempval);
1550 /* Disable VLAN tag extraction */
1551 tempval = gfar_read(&priv->regs->rctrl);
1552 tempval &= ~RCTRL_VLEX;
1553 /* If parse is no longer required, then disable parser */
1554 if (tempval & RCTRL_REQ_PARSER)
1555 tempval |= RCTRL_PRSDEP_INIT;
1557 tempval &= ~RCTRL_PRSDEP_INIT;
1558 gfar_write(&priv->regs->rctrl, tempval);
1561 gfar_change_mtu(dev, dev->mtu);
1563 spin_unlock_irqrestore(&priv->rxlock, flags);
1566 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1568 int tempsize, tempval;
1569 struct gfar_private *priv = netdev_priv(dev);
1570 int oldsize = priv->rx_buffer_size;
1571 int frame_size = new_mtu + ETH_HLEN;
1574 frame_size += VLAN_HLEN;
1576 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1577 if (netif_msg_drv(priv))
1578 printk(KERN_ERR "%s: Invalid MTU setting\n",
1583 if (gfar_uses_fcb(priv))
1584 frame_size += GMAC_FCB_LEN;
1586 frame_size += priv->padding;
1589 (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1590 INCREMENTAL_BUFFER_SIZE;
1592 /* Only stop and start the controller if it isn't already
1593 * stopped, and we changed something */
1594 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1597 priv->rx_buffer_size = tempsize;
1601 gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1602 gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1604 /* If the mtu is larger than the max size for standard
1605 * ethernet frames (ie, a jumbo frame), then set maccfg2
1606 * to allow huge frames, and to check the length */
1607 tempval = gfar_read(&priv->regs->maccfg2);
1609 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1610 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1612 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1614 gfar_write(&priv->regs->maccfg2, tempval);
1616 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1622 /* gfar_reset_task gets scheduled when a packet has not been
1623 * transmitted after a set amount of time.
1624 * For now, assume that clearing out all the structures, and
1625 * starting over will fix the problem.
1627 static void gfar_reset_task(struct work_struct *work)
1629 struct gfar_private *priv = container_of(work, struct gfar_private,
1631 struct net_device *dev = priv->ndev;
1633 if (dev->flags & IFF_UP) {
1634 netif_stop_queue(dev);
1637 netif_start_queue(dev);
1640 netif_tx_schedule_all(dev);
1643 static void gfar_timeout(struct net_device *dev)
1645 struct gfar_private *priv = netdev_priv(dev);
1647 dev->stats.tx_errors++;
1648 schedule_work(&priv->reset_task);
1651 /* Interrupt Handler for Transmit complete */
1652 static int gfar_clean_tx_ring(struct net_device *dev)
1654 struct gfar_private *priv = netdev_priv(dev);
1656 struct txbd8 *lbdp = NULL;
1657 struct txbd8 *base = priv->tx_bd_base;
1658 struct sk_buff *skb;
1660 int tx_ring_size = priv->tx_ring_size;
1666 bdp = priv->dirty_tx;
1667 skb_dirtytx = priv->skb_dirtytx;
1669 while ((skb = priv->tx_skbuff[skb_dirtytx])) {
1670 frags = skb_shinfo(skb)->nr_frags;
1671 lbdp = skip_txbd(bdp, frags, base, tx_ring_size);
1673 lstatus = lbdp->lstatus;
1675 /* Only clean completed frames */
1676 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
1677 (lstatus & BD_LENGTH_MASK))
1680 dma_unmap_single(&priv->ofdev->dev,
1685 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1686 bdp = next_txbd(bdp, base, tx_ring_size);
1688 for (i = 0; i < frags; i++) {
1689 dma_unmap_page(&priv->ofdev->dev,
1693 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1694 bdp = next_txbd(bdp, base, tx_ring_size);
1698 * If there's room in the queue (limit it to rx_buffer_size)
1699 * we add this skb back into the pool, if it's the right size
1701 if (skb_queue_len(&priv->rx_recycle) < priv->rx_ring_size &&
1702 skb_recycle_check(skb, priv->rx_buffer_size +
1704 __skb_queue_head(&priv->rx_recycle, skb);
1706 dev_kfree_skb_any(skb);
1708 priv->tx_skbuff[skb_dirtytx] = NULL;
1710 skb_dirtytx = (skb_dirtytx + 1) &
1711 TX_RING_MOD_MASK(tx_ring_size);
1714 priv->num_txbdfree += frags + 1;
1717 /* If we freed a buffer, we can restart transmission, if necessary */
1718 if (netif_queue_stopped(dev) && priv->num_txbdfree)
1719 netif_wake_queue(dev);
1721 /* Update dirty indicators */
1722 priv->skb_dirtytx = skb_dirtytx;
1723 priv->dirty_tx = bdp;
1725 dev->stats.tx_packets += howmany;
1730 static void gfar_schedule_cleanup(struct net_device *dev)
1732 struct gfar_private *priv = netdev_priv(dev);
1733 unsigned long flags;
1735 spin_lock_irqsave(&priv->txlock, flags);
1736 spin_lock(&priv->rxlock);
1738 if (napi_schedule_prep(&priv->napi)) {
1739 gfar_write(&priv->regs->imask, IMASK_RTX_DISABLED);
1740 __napi_schedule(&priv->napi);
1743 * Clear IEVENT, so interrupts aren't called again
1744 * because of the packets that have already arrived.
1746 gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1749 spin_unlock(&priv->rxlock);
1750 spin_unlock_irqrestore(&priv->txlock, flags);
1753 /* Interrupt Handler for Transmit complete */
1754 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1756 gfar_schedule_cleanup((struct net_device *)dev_id);
1760 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
1761 struct sk_buff *skb)
1763 struct gfar_private *priv = netdev_priv(dev);
1766 buf = dma_map_single(&priv->ofdev->dev, skb->data,
1767 priv->rx_buffer_size, DMA_FROM_DEVICE);
1768 gfar_init_rxbdp(dev, bdp, buf);
1772 struct sk_buff * gfar_new_skb(struct net_device *dev)
1774 unsigned int alignamount;
1775 struct gfar_private *priv = netdev_priv(dev);
1776 struct sk_buff *skb = NULL;
1778 skb = __skb_dequeue(&priv->rx_recycle);
1780 skb = netdev_alloc_skb(dev,
1781 priv->rx_buffer_size + RXBUF_ALIGNMENT);
1786 alignamount = RXBUF_ALIGNMENT -
1787 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
1789 /* We need the data buffer to be aligned properly. We will reserve
1790 * as many bytes as needed to align the data properly
1792 skb_reserve(skb, alignamount);
1797 static inline void count_errors(unsigned short status, struct net_device *dev)
1799 struct gfar_private *priv = netdev_priv(dev);
1800 struct net_device_stats *stats = &dev->stats;
1801 struct gfar_extra_stats *estats = &priv->extra_stats;
1803 /* If the packet was truncated, none of the other errors
1805 if (status & RXBD_TRUNCATED) {
1806 stats->rx_length_errors++;
1812 /* Count the errors, if there were any */
1813 if (status & (RXBD_LARGE | RXBD_SHORT)) {
1814 stats->rx_length_errors++;
1816 if (status & RXBD_LARGE)
1821 if (status & RXBD_NONOCTET) {
1822 stats->rx_frame_errors++;
1823 estats->rx_nonoctet++;
1825 if (status & RXBD_CRCERR) {
1826 estats->rx_crcerr++;
1827 stats->rx_crc_errors++;
1829 if (status & RXBD_OVERRUN) {
1830 estats->rx_overrun++;
1831 stats->rx_crc_errors++;
1835 irqreturn_t gfar_receive(int irq, void *dev_id)
1837 gfar_schedule_cleanup((struct net_device *)dev_id);
1841 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1843 /* If valid headers were found, and valid sums
1844 * were verified, then we tell the kernel that no
1845 * checksumming is necessary. Otherwise, it is */
1846 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1847 skb->ip_summed = CHECKSUM_UNNECESSARY;
1849 skb->ip_summed = CHECKSUM_NONE;
1853 /* gfar_process_frame() -- handle one incoming packet if skb
1855 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1858 struct gfar_private *priv = netdev_priv(dev);
1859 struct rxfcb *fcb = NULL;
1863 /* fcb is at the beginning if exists */
1864 fcb = (struct rxfcb *)skb->data;
1866 /* Remove the FCB from the skb */
1867 /* Remove the padded bytes, if there are any */
1869 skb_pull(skb, amount_pull);
1871 if (priv->rx_csum_enable)
1872 gfar_rx_checksum(skb, fcb);
1874 /* Tell the skb what kind of packet this is */
1875 skb->protocol = eth_type_trans(skb, dev);
1877 /* Send the packet up the stack */
1878 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
1879 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
1881 ret = netif_receive_skb(skb);
1883 if (NET_RX_DROP == ret)
1884 priv->extra_stats.kernel_dropped++;
1889 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1890 * until the budget/quota has been reached. Returns the number
1893 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1895 struct rxbd8 *bdp, *base;
1896 struct sk_buff *skb;
1900 struct gfar_private *priv = netdev_priv(dev);
1902 /* Get the first full descriptor */
1904 base = priv->rx_bd_base;
1906 amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0) +
1909 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1910 struct sk_buff *newskb;
1913 /* Add another skb for the future */
1914 newskb = gfar_new_skb(dev);
1916 skb = priv->rx_skbuff[priv->skb_currx];
1918 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
1919 priv->rx_buffer_size, DMA_FROM_DEVICE);
1921 /* We drop the frame if we failed to allocate a new buffer */
1922 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
1923 bdp->status & RXBD_ERR)) {
1924 count_errors(bdp->status, dev);
1926 if (unlikely(!newskb))
1930 * We need to reset ->data to what it
1931 * was before gfar_new_skb() re-aligned
1932 * it to an RXBUF_ALIGNMENT boundary
1933 * before we put the skb back on the
1936 skb->data = skb->head + NET_SKB_PAD;
1937 __skb_queue_head(&priv->rx_recycle, skb);
1940 /* Increment the number of packets */
1941 dev->stats.rx_packets++;
1945 pkt_len = bdp->length - ETH_FCS_LEN;
1946 /* Remove the FCS from the packet length */
1947 skb_put(skb, pkt_len);
1948 dev->stats.rx_bytes += pkt_len;
1950 if (in_irq() || irqs_disabled())
1951 printk("Interrupt problem!\n");
1952 gfar_process_frame(dev, skb, amount_pull);
1955 if (netif_msg_rx_err(priv))
1957 "%s: Missing skb!\n", dev->name);
1958 dev->stats.rx_dropped++;
1959 priv->extra_stats.rx_skbmissing++;
1964 priv->rx_skbuff[priv->skb_currx] = newskb;
1966 /* Setup the new bdp */
1967 gfar_new_rxbdp(dev, bdp, newskb);
1969 /* Update to the next pointer */
1970 bdp = next_bd(bdp, base, priv->rx_ring_size);
1972 /* update to point at the next skb */
1974 (priv->skb_currx + 1) &
1975 RX_RING_MOD_MASK(priv->rx_ring_size);
1978 /* Update the current rxbd pointer to be the next one */
1984 static int gfar_poll(struct napi_struct *napi, int budget)
1986 struct gfar_private *priv = container_of(napi, struct gfar_private, napi);
1987 struct net_device *dev = priv->ndev;
1990 unsigned long flags;
1992 /* Clear IEVENT, so interrupts aren't called again
1993 * because of the packets that have already arrived */
1994 gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1996 /* If we fail to get the lock, don't bother with the TX BDs */
1997 if (spin_trylock_irqsave(&priv->txlock, flags)) {
1998 tx_cleaned = gfar_clean_tx_ring(dev);
1999 spin_unlock_irqrestore(&priv->txlock, flags);
2002 rx_cleaned = gfar_clean_rx_ring(dev, budget);
2007 if (rx_cleaned < budget) {
2008 napi_complete(napi);
2010 /* Clear the halt bit in RSTAT */
2011 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
2013 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
2015 /* If we are coalescing interrupts, update the timer */
2016 /* Otherwise, clear it */
2017 if (likely(priv->rxcoalescing)) {
2018 gfar_write(&priv->regs->rxic, 0);
2019 gfar_write(&priv->regs->rxic, priv->rxic);
2021 if (likely(priv->txcoalescing)) {
2022 gfar_write(&priv->regs->txic, 0);
2023 gfar_write(&priv->regs->txic, priv->txic);
2030 #ifdef CONFIG_NET_POLL_CONTROLLER
2032 * Polling 'interrupt' - used by things like netconsole to send skbs
2033 * without having to re-enable interrupts. It's not called while
2034 * the interrupt routine is executing.
2036 static void gfar_netpoll(struct net_device *dev)
2038 struct gfar_private *priv = netdev_priv(dev);
2040 /* If the device has multiple interrupts, run tx/rx */
2041 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2042 disable_irq(priv->interruptTransmit);
2043 disable_irq(priv->interruptReceive);
2044 disable_irq(priv->interruptError);
2045 gfar_interrupt(priv->interruptTransmit, dev);
2046 enable_irq(priv->interruptError);
2047 enable_irq(priv->interruptReceive);
2048 enable_irq(priv->interruptTransmit);
2050 disable_irq(priv->interruptTransmit);
2051 gfar_interrupt(priv->interruptTransmit, dev);
2052 enable_irq(priv->interruptTransmit);
2057 /* The interrupt handler for devices with one interrupt */
2058 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
2060 struct net_device *dev = dev_id;
2061 struct gfar_private *priv = netdev_priv(dev);
2063 /* Save ievent for future reference */
2064 u32 events = gfar_read(&priv->regs->ievent);
2066 /* Check for reception */
2067 if (events & IEVENT_RX_MASK)
2068 gfar_receive(irq, dev_id);
2070 /* Check for transmit completion */
2071 if (events & IEVENT_TX_MASK)
2072 gfar_transmit(irq, dev_id);
2074 /* Check for errors */
2075 if (events & IEVENT_ERR_MASK)
2076 gfar_error(irq, dev_id);
2081 /* Called every time the controller might need to be made
2082 * aware of new link state. The PHY code conveys this
2083 * information through variables in the phydev structure, and this
2084 * function converts those variables into the appropriate
2085 * register values, and can bring down the device if needed.
2087 static void adjust_link(struct net_device *dev)
2089 struct gfar_private *priv = netdev_priv(dev);
2090 struct gfar __iomem *regs = priv->regs;
2091 unsigned long flags;
2092 struct phy_device *phydev = priv->phydev;
2095 spin_lock_irqsave(&priv->txlock, flags);
2097 u32 tempval = gfar_read(®s->maccfg2);
2098 u32 ecntrl = gfar_read(®s->ecntrl);
2100 /* Now we make sure that we can be in full duplex mode.
2101 * If not, we operate in half-duplex mode. */
2102 if (phydev->duplex != priv->oldduplex) {
2104 if (!(phydev->duplex))
2105 tempval &= ~(MACCFG2_FULL_DUPLEX);
2107 tempval |= MACCFG2_FULL_DUPLEX;
2109 priv->oldduplex = phydev->duplex;
2112 if (phydev->speed != priv->oldspeed) {
2114 switch (phydev->speed) {
2117 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2119 ecntrl &= ~(ECNTRL_R100);
2124 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
2126 /* Reduced mode distinguishes
2127 * between 10 and 100 */
2128 if (phydev->speed == SPEED_100)
2129 ecntrl |= ECNTRL_R100;
2131 ecntrl &= ~(ECNTRL_R100);
2134 if (netif_msg_link(priv))
2136 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
2137 dev->name, phydev->speed);
2141 priv->oldspeed = phydev->speed;
2144 gfar_write(®s->maccfg2, tempval);
2145 gfar_write(®s->ecntrl, ecntrl);
2147 if (!priv->oldlink) {
2151 } else if (priv->oldlink) {
2155 priv->oldduplex = -1;
2158 if (new_state && netif_msg_link(priv))
2159 phy_print_status(phydev);
2161 spin_unlock_irqrestore(&priv->txlock, flags);
2164 /* Update the hash table based on the current list of multicast
2165 * addresses we subscribe to. Also, change the promiscuity of
2166 * the device based on the flags (this function is called
2167 * whenever dev->flags is changed */
2168 static void gfar_set_multi(struct net_device *dev)
2170 struct dev_mc_list *mc_ptr;
2171 struct gfar_private *priv = netdev_priv(dev);
2172 struct gfar __iomem *regs = priv->regs;
2175 if(dev->flags & IFF_PROMISC) {
2176 /* Set RCTRL to PROM */
2177 tempval = gfar_read(®s->rctrl);
2178 tempval |= RCTRL_PROM;
2179 gfar_write(®s->rctrl, tempval);
2181 /* Set RCTRL to not PROM */
2182 tempval = gfar_read(®s->rctrl);
2183 tempval &= ~(RCTRL_PROM);
2184 gfar_write(®s->rctrl, tempval);
2187 if(dev->flags & IFF_ALLMULTI) {
2188 /* Set the hash to rx all multicast frames */
2189 gfar_write(®s->igaddr0, 0xffffffff);
2190 gfar_write(®s->igaddr1, 0xffffffff);
2191 gfar_write(®s->igaddr2, 0xffffffff);
2192 gfar_write(®s->igaddr3, 0xffffffff);
2193 gfar_write(®s->igaddr4, 0xffffffff);
2194 gfar_write(®s->igaddr5, 0xffffffff);
2195 gfar_write(®s->igaddr6, 0xffffffff);
2196 gfar_write(®s->igaddr7, 0xffffffff);
2197 gfar_write(®s->gaddr0, 0xffffffff);
2198 gfar_write(®s->gaddr1, 0xffffffff);
2199 gfar_write(®s->gaddr2, 0xffffffff);
2200 gfar_write(®s->gaddr3, 0xffffffff);
2201 gfar_write(®s->gaddr4, 0xffffffff);
2202 gfar_write(®s->gaddr5, 0xffffffff);
2203 gfar_write(®s->gaddr6, 0xffffffff);
2204 gfar_write(®s->gaddr7, 0xffffffff);
2209 /* zero out the hash */
2210 gfar_write(®s->igaddr0, 0x0);
2211 gfar_write(®s->igaddr1, 0x0);
2212 gfar_write(®s->igaddr2, 0x0);
2213 gfar_write(®s->igaddr3, 0x0);
2214 gfar_write(®s->igaddr4, 0x0);
2215 gfar_write(®s->igaddr5, 0x0);
2216 gfar_write(®s->igaddr6, 0x0);
2217 gfar_write(®s->igaddr7, 0x0);
2218 gfar_write(®s->gaddr0, 0x0);
2219 gfar_write(®s->gaddr1, 0x0);
2220 gfar_write(®s->gaddr2, 0x0);
2221 gfar_write(®s->gaddr3, 0x0);
2222 gfar_write(®s->gaddr4, 0x0);
2223 gfar_write(®s->gaddr5, 0x0);
2224 gfar_write(®s->gaddr6, 0x0);
2225 gfar_write(®s->gaddr7, 0x0);
2227 /* If we have extended hash tables, we need to
2228 * clear the exact match registers to prepare for
2230 if (priv->extended_hash) {
2231 em_num = GFAR_EM_NUM + 1;
2232 gfar_clear_exact_match(dev);
2239 if(dev->mc_count == 0)
2242 /* Parse the list, and set the appropriate bits */
2243 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
2245 gfar_set_mac_for_addr(dev, idx,
2249 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
2257 /* Clears each of the exact match registers to zero, so they
2258 * don't interfere with normal reception */
2259 static void gfar_clear_exact_match(struct net_device *dev)
2262 u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
2264 for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
2265 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
2268 /* Set the appropriate hash bit for the given addr */
2269 /* The algorithm works like so:
2270 * 1) Take the Destination Address (ie the multicast address), and
2271 * do a CRC on it (little endian), and reverse the bits of the
2273 * 2) Use the 8 most significant bits as a hash into a 256-entry
2274 * table. The table is controlled through 8 32-bit registers:
2275 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
2276 * gaddr7. This means that the 3 most significant bits in the
2277 * hash index which gaddr register to use, and the 5 other bits
2278 * indicate which bit (assuming an IBM numbering scheme, which
2279 * for PowerPC (tm) is usually the case) in the register holds
2281 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
2284 struct gfar_private *priv = netdev_priv(dev);
2285 u32 result = ether_crc(MAC_ADDR_LEN, addr);
2286 int width = priv->hash_width;
2287 u8 whichbit = (result >> (32 - width)) & 0x1f;
2288 u8 whichreg = result >> (32 - width + 5);
2289 u32 value = (1 << (31-whichbit));
2291 tempval = gfar_read(priv->hash_regs[whichreg]);
2293 gfar_write(priv->hash_regs[whichreg], tempval);
2299 /* There are multiple MAC Address register pairs on some controllers
2300 * This function sets the numth pair to a given address
2302 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
2304 struct gfar_private *priv = netdev_priv(dev);
2306 char tmpbuf[MAC_ADDR_LEN];
2308 u32 __iomem *macptr = &priv->regs->macstnaddr1;
2312 /* Now copy it into the mac registers backwards, cuz */
2313 /* little endian is silly */
2314 for (idx = 0; idx < MAC_ADDR_LEN; idx++)
2315 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
2317 gfar_write(macptr, *((u32 *) (tmpbuf)));
2319 tempval = *((u32 *) (tmpbuf + 4));
2321 gfar_write(macptr+1, tempval);
2324 /* GFAR error interrupt handler */
2325 static irqreturn_t gfar_error(int irq, void *dev_id)
2327 struct net_device *dev = dev_id;
2328 struct gfar_private *priv = netdev_priv(dev);
2330 /* Save ievent for future reference */
2331 u32 events = gfar_read(&priv->regs->ievent);
2334 gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK);
2336 /* Magic Packet is not an error. */
2337 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2338 (events & IEVENT_MAG))
2339 events &= ~IEVENT_MAG;
2342 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2343 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2344 dev->name, events, gfar_read(&priv->regs->imask));
2346 /* Update the error counters */
2347 if (events & IEVENT_TXE) {
2348 dev->stats.tx_errors++;
2350 if (events & IEVENT_LC)
2351 dev->stats.tx_window_errors++;
2352 if (events & IEVENT_CRL)
2353 dev->stats.tx_aborted_errors++;
2354 if (events & IEVENT_XFUN) {
2355 if (netif_msg_tx_err(priv))
2356 printk(KERN_DEBUG "%s: TX FIFO underrun, "
2357 "packet dropped.\n", dev->name);
2358 dev->stats.tx_dropped++;
2359 priv->extra_stats.tx_underrun++;
2361 /* Reactivate the Tx Queues */
2362 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
2364 if (netif_msg_tx_err(priv))
2365 printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
2367 if (events & IEVENT_BSY) {
2368 dev->stats.rx_errors++;
2369 priv->extra_stats.rx_bsy++;
2371 gfar_receive(irq, dev_id);
2373 if (netif_msg_rx_err(priv))
2374 printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
2375 dev->name, gfar_read(&priv->regs->rstat));
2377 if (events & IEVENT_BABR) {
2378 dev->stats.rx_errors++;
2379 priv->extra_stats.rx_babr++;
2381 if (netif_msg_rx_err(priv))
2382 printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
2384 if (events & IEVENT_EBERR) {
2385 priv->extra_stats.eberr++;
2386 if (netif_msg_rx_err(priv))
2387 printk(KERN_DEBUG "%s: bus error\n", dev->name);
2389 if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
2390 printk(KERN_DEBUG "%s: control frame\n", dev->name);
2392 if (events & IEVENT_BABT) {
2393 priv->extra_stats.tx_babt++;
2394 if (netif_msg_tx_err(priv))
2395 printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
2400 static struct of_device_id gfar_match[] =
2404 .compatible = "gianfar",
2408 MODULE_DEVICE_TABLE(of, gfar_match);
2410 /* Structure for a device driver */
2411 static struct of_platform_driver gfar_driver = {
2412 .name = "fsl-gianfar",
2413 .match_table = gfar_match,
2415 .probe = gfar_probe,
2416 .remove = gfar_remove,
2417 .suspend = gfar_legacy_suspend,
2418 .resume = gfar_legacy_resume,
2419 .driver.pm = GFAR_PM_OPS,
2422 static int __init gfar_init(void)
2424 return of_register_platform_driver(&gfar_driver);
2427 static void __exit gfar_exit(void)
2429 of_unregister_platform_driver(&gfar_driver);
2432 module_init(gfar_init);
2433 module_exit(gfar_exit);