2 * drivers/net/gianfar.c
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
10 * Maintainer: Kumar Gala
12 * Copyright (c) 2002-2004 Freescale Semiconductor, Inc.
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
19 * Gianfar: AKA Lambda Draconis, "Dragon"
27 * The driver is initialized through platform_device. Structures which
28 * define the configuration needed by the board are defined in a
29 * board structure in arch/ppc/platforms (though I do not
30 * discount the possibility that other architectures could one
33 * The Gianfar Ethernet Controller uses a ring of buffer
34 * descriptors. The beginning is indicated by a register
35 * pointing to the physical address of the start of the ring.
36 * The end is determined by a "wrap" bit being set in the
37 * last descriptor of the ring.
39 * When a packet is received, the RXF bit in the
40 * IEVENT register is set, triggering an interrupt when the
41 * corresponding bit in the IMASK register is also set (if
42 * interrupt coalescing is active, then the interrupt may not
43 * happen immediately, but will wait until either a set number
44 * of frames or amount of time have passed). In NAPI, the
45 * interrupt handler will signal there is work to be done, and
46 * exit. Without NAPI, the packet(s) will be handled
47 * immediately. Both methods will start at the last known empty
48 * descriptor, and process every subsequent descriptor until there
49 * are none left with data (NAPI will stop after a set number of
50 * packets to give time to other tasks, but will eventually
51 * process all the packets). The data arrives inside a
52 * pre-allocated skb, and so after the skb is passed up to the
53 * stack, a new skb must be allocated, and the address field in
54 * the buffer descriptor must be updated to indicate this new
57 * When the kernel requests that a packet be transmitted, the
58 * driver starts where it left off last time, and points the
59 * descriptor at the buffer which was passed in. The driver
60 * then informs the DMA engine that there are packets ready to
61 * be transmitted. Once the controller is finished transmitting
62 * the packet, an interrupt may be triggered (under the same
63 * conditions as for reception, but depending on the TXF bit).
64 * The driver then cleans up the buffer.
67 #include <linux/config.h>
68 #include <linux/kernel.h>
69 #include <linux/sched.h>
70 #include <linux/string.h>
71 #include <linux/errno.h>
72 #include <linux/unistd.h>
73 #include <linux/slab.h>
74 #include <linux/interrupt.h>
75 #include <linux/init.h>
76 #include <linux/delay.h>
77 #include <linux/netdevice.h>
78 #include <linux/etherdevice.h>
79 #include <linux/skbuff.h>
80 #include <linux/if_vlan.h>
81 #include <linux/spinlock.h>
83 #include <linux/platform_device.h>
85 #include <linux/tcp.h>
86 #include <linux/udp.h>
91 #include <asm/uaccess.h>
92 #include <linux/module.h>
93 #include <linux/dma-mapping.h>
94 #include <linux/crc32.h>
95 #include <linux/mii.h>
96 #include <linux/phy.h>
99 #include "gianfar_mii.h"
101 #define TX_TIMEOUT (1*HZ)
102 #define SKB_ALLOC_TIMEOUT 1000000
103 #undef BRIEF_GFAR_ERRORS
104 #undef VERBOSE_GFAR_ERRORS
106 #ifdef CONFIG_GFAR_NAPI
107 #define RECEIVE(x) netif_receive_skb(x)
109 #define RECEIVE(x) netif_rx(x)
112 const char gfar_driver_name[] = "Gianfar Ethernet";
113 const char gfar_driver_version[] = "1.3";
115 static int gfar_enet_open(struct net_device *dev);
116 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
117 static void gfar_timeout(struct net_device *dev);
118 static int gfar_close(struct net_device *dev);
119 struct sk_buff *gfar_new_skb(struct net_device *dev, struct rxbd8 *bdp);
120 static struct net_device_stats *gfar_get_stats(struct net_device *dev);
121 static int gfar_set_mac_address(struct net_device *dev);
122 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
123 static irqreturn_t gfar_error(int irq, void *dev_id, struct pt_regs *regs);
124 static irqreturn_t gfar_transmit(int irq, void *dev_id, struct pt_regs *regs);
125 static irqreturn_t gfar_interrupt(int irq, void *dev_id, struct pt_regs *regs);
126 static void adjust_link(struct net_device *dev);
127 static void init_registers(struct net_device *dev);
128 static int init_phy(struct net_device *dev);
129 static int gfar_probe(struct platform_device *pdev);
130 static int gfar_remove(struct platform_device *pdev);
131 static void free_skb_resources(struct gfar_private *priv);
132 static void gfar_set_multi(struct net_device *dev);
133 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
134 #ifdef CONFIG_GFAR_NAPI
135 static int gfar_poll(struct net_device *dev, int *budget);
137 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
138 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, int length);
139 static void gfar_vlan_rx_register(struct net_device *netdev,
140 struct vlan_group *grp);
141 static void gfar_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid);
142 void gfar_halt(struct net_device *dev);
143 void gfar_start(struct net_device *dev);
144 static void gfar_clear_exact_match(struct net_device *dev);
145 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
147 extern struct ethtool_ops gfar_ethtool_ops;
149 MODULE_AUTHOR("Freescale Semiconductor, Inc");
150 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
151 MODULE_LICENSE("GPL");
153 /* Returns 1 if incoming frames use an FCB */
154 static inline int gfar_uses_fcb(struct gfar_private *priv)
156 return (priv->vlan_enable || priv->rx_csum_enable);
159 /* Set up the ethernet device structure, private data,
160 * and anything else we need before we start */
161 static int gfar_probe(struct platform_device *pdev)
164 struct net_device *dev = NULL;
165 struct gfar_private *priv = NULL;
166 struct gianfar_platform_data *einfo;
171 einfo = (struct gianfar_platform_data *) pdev->dev.platform_data;
174 printk(KERN_ERR "gfar %d: Missing additional data!\n",
180 /* Create an ethernet device instance */
181 dev = alloc_etherdev(sizeof (*priv));
186 priv = netdev_priv(dev);
188 /* Set the info in the priv to the current info */
191 /* fill out IRQ fields */
192 if (einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
193 priv->interruptTransmit = platform_get_irq_byname(pdev, "tx");
194 priv->interruptReceive = platform_get_irq_byname(pdev, "rx");
195 priv->interruptError = platform_get_irq_byname(pdev, "error");
197 priv->interruptTransmit = platform_get_irq(pdev, 0);
200 /* get a pointer to the register memory */
201 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
202 priv->regs = (struct gfar *)
203 ioremap(r->start, sizeof (struct gfar));
205 if (NULL == priv->regs) {
210 spin_lock_init(&priv->lock);
212 platform_set_drvdata(pdev, dev);
214 /* Stop the DMA engine now, in case it was running before */
215 /* (The firmware could have used it, and left it running). */
216 /* To do this, we write Graceful Receive Stop and Graceful */
217 /* Transmit Stop, and then wait until the corresponding bits */
218 /* in IEVENT indicate the stops have completed. */
219 tempval = gfar_read(&priv->regs->dmactrl);
220 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
221 gfar_write(&priv->regs->dmactrl, tempval);
223 tempval = gfar_read(&priv->regs->dmactrl);
224 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
225 gfar_write(&priv->regs->dmactrl, tempval);
227 while (!(gfar_read(&priv->regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC)))
230 /* Reset MAC layer */
231 gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
233 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
234 gfar_write(&priv->regs->maccfg1, tempval);
236 /* Initialize MACCFG2. */
237 gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
239 /* Initialize ECNTRL */
240 gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
242 /* Copy the station address into the dev structure, */
243 memcpy(dev->dev_addr, einfo->mac_addr, MAC_ADDR_LEN);
245 /* Set the dev->base_addr to the gfar reg region */
246 dev->base_addr = (unsigned long) (priv->regs);
248 SET_MODULE_OWNER(dev);
249 SET_NETDEV_DEV(dev, &pdev->dev);
251 /* Fill in the dev structure */
252 dev->open = gfar_enet_open;
253 dev->hard_start_xmit = gfar_start_xmit;
254 dev->tx_timeout = gfar_timeout;
255 dev->watchdog_timeo = TX_TIMEOUT;
256 #ifdef CONFIG_GFAR_NAPI
257 dev->poll = gfar_poll;
258 dev->weight = GFAR_DEV_WEIGHT;
260 dev->stop = gfar_close;
261 dev->get_stats = gfar_get_stats;
262 dev->change_mtu = gfar_change_mtu;
264 dev->set_multicast_list = gfar_set_multi;
266 dev->ethtool_ops = &gfar_ethtool_ops;
268 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
269 priv->rx_csum_enable = 1;
270 dev->features |= NETIF_F_IP_CSUM;
272 priv->rx_csum_enable = 0;
276 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
277 dev->vlan_rx_register = gfar_vlan_rx_register;
278 dev->vlan_rx_kill_vid = gfar_vlan_rx_kill_vid;
280 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
282 priv->vlan_enable = 1;
285 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
286 priv->extended_hash = 1;
287 priv->hash_width = 9;
289 priv->hash_regs[0] = &priv->regs->igaddr0;
290 priv->hash_regs[1] = &priv->regs->igaddr1;
291 priv->hash_regs[2] = &priv->regs->igaddr2;
292 priv->hash_regs[3] = &priv->regs->igaddr3;
293 priv->hash_regs[4] = &priv->regs->igaddr4;
294 priv->hash_regs[5] = &priv->regs->igaddr5;
295 priv->hash_regs[6] = &priv->regs->igaddr6;
296 priv->hash_regs[7] = &priv->regs->igaddr7;
297 priv->hash_regs[8] = &priv->regs->gaddr0;
298 priv->hash_regs[9] = &priv->regs->gaddr1;
299 priv->hash_regs[10] = &priv->regs->gaddr2;
300 priv->hash_regs[11] = &priv->regs->gaddr3;
301 priv->hash_regs[12] = &priv->regs->gaddr4;
302 priv->hash_regs[13] = &priv->regs->gaddr5;
303 priv->hash_regs[14] = &priv->regs->gaddr6;
304 priv->hash_regs[15] = &priv->regs->gaddr7;
307 priv->extended_hash = 0;
308 priv->hash_width = 8;
310 priv->hash_regs[0] = &priv->regs->gaddr0;
311 priv->hash_regs[1] = &priv->regs->gaddr1;
312 priv->hash_regs[2] = &priv->regs->gaddr2;
313 priv->hash_regs[3] = &priv->regs->gaddr3;
314 priv->hash_regs[4] = &priv->regs->gaddr4;
315 priv->hash_regs[5] = &priv->regs->gaddr5;
316 priv->hash_regs[6] = &priv->regs->gaddr6;
317 priv->hash_regs[7] = &priv->regs->gaddr7;
320 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
321 priv->padding = DEFAULT_PADDING;
325 if (dev->features & NETIF_F_IP_CSUM)
326 dev->hard_header_len += GMAC_FCB_LEN;
328 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
329 priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
330 priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
332 priv->txcoalescing = DEFAULT_TX_COALESCE;
333 priv->txcount = DEFAULT_TXCOUNT;
334 priv->txtime = DEFAULT_TXTIME;
335 priv->rxcoalescing = DEFAULT_RX_COALESCE;
336 priv->rxcount = DEFAULT_RXCOUNT;
337 priv->rxtime = DEFAULT_RXTIME;
339 /* Enable most messages by default */
340 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
342 err = register_netdev(dev);
345 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
350 /* Create all the sysfs files */
351 gfar_init_sysfs(dev);
353 /* Print out the device info */
354 printk(KERN_INFO DEVICE_NAME, dev->name);
355 for (idx = 0; idx < 6; idx++)
356 printk("%2.2x%c", dev->dev_addr[idx], idx == 5 ? ' ' : ':');
359 /* Even more device info helps when determining which kernel */
360 /* provided which set of benchmarks. */
361 #ifdef CONFIG_GFAR_NAPI
362 printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
364 printk(KERN_INFO "%s: Running with NAPI disabled\n", dev->name);
366 printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
367 dev->name, priv->rx_ring_size, priv->tx_ring_size);
372 iounmap((void *) priv->regs);
378 static int gfar_remove(struct platform_device *pdev)
380 struct net_device *dev = platform_get_drvdata(pdev);
381 struct gfar_private *priv = netdev_priv(dev);
383 platform_set_drvdata(pdev, NULL);
385 iounmap((void *) priv->regs);
392 /* Initializes driver's PHY state, and attaches to the PHY.
393 * Returns 0 on success.
395 static int init_phy(struct net_device *dev)
397 struct gfar_private *priv = netdev_priv(dev);
398 uint gigabit_support =
399 priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
400 SUPPORTED_1000baseT_Full : 0;
401 struct phy_device *phydev;
405 priv->oldduplex = -1;
407 phydev = phy_connect(dev, priv->einfo->bus_id, &adjust_link, 0);
409 if (IS_ERR(phydev)) {
410 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
411 return PTR_ERR(phydev);
414 /* Remove any features not supported by the controller */
415 phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
416 phydev->advertising = phydev->supported;
418 priv->phydev = phydev;
423 static void init_registers(struct net_device *dev)
425 struct gfar_private *priv = netdev_priv(dev);
428 gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
430 /* Initialize IMASK */
431 gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
433 /* Init hash registers to zero */
434 gfar_write(&priv->regs->igaddr0, 0);
435 gfar_write(&priv->regs->igaddr1, 0);
436 gfar_write(&priv->regs->igaddr2, 0);
437 gfar_write(&priv->regs->igaddr3, 0);
438 gfar_write(&priv->regs->igaddr4, 0);
439 gfar_write(&priv->regs->igaddr5, 0);
440 gfar_write(&priv->regs->igaddr6, 0);
441 gfar_write(&priv->regs->igaddr7, 0);
443 gfar_write(&priv->regs->gaddr0, 0);
444 gfar_write(&priv->regs->gaddr1, 0);
445 gfar_write(&priv->regs->gaddr2, 0);
446 gfar_write(&priv->regs->gaddr3, 0);
447 gfar_write(&priv->regs->gaddr4, 0);
448 gfar_write(&priv->regs->gaddr5, 0);
449 gfar_write(&priv->regs->gaddr6, 0);
450 gfar_write(&priv->regs->gaddr7, 0);
452 /* Zero out the rmon mib registers if it has them */
453 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
454 memset((void *) &(priv->regs->rmon), 0,
455 sizeof (struct rmon_mib));
457 /* Mask off the CAM interrupts */
458 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
459 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
462 /* Initialize the max receive buffer length */
463 gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
465 /* Initialize the Minimum Frame Length Register */
466 gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
468 /* Assign the TBI an address which won't conflict with the PHYs */
469 gfar_write(&priv->regs->tbipa, TBIPA_VALUE);
473 /* Halt the receive and transmit queues */
474 void gfar_halt(struct net_device *dev)
476 struct gfar_private *priv = netdev_priv(dev);
477 struct gfar *regs = priv->regs;
480 /* Mask all interrupts */
481 gfar_write(®s->imask, IMASK_INIT_CLEAR);
483 /* Clear all interrupts */
484 gfar_write(®s->ievent, IEVENT_INIT_CLEAR);
486 /* Stop the DMA, and wait for it to stop */
487 tempval = gfar_read(&priv->regs->dmactrl);
488 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
489 != (DMACTRL_GRS | DMACTRL_GTS)) {
490 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
491 gfar_write(&priv->regs->dmactrl, tempval);
493 while (!(gfar_read(&priv->regs->ievent) &
494 (IEVENT_GRSC | IEVENT_GTSC)))
498 /* Disable Rx and Tx */
499 tempval = gfar_read(®s->maccfg1);
500 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
501 gfar_write(®s->maccfg1, tempval);
504 void stop_gfar(struct net_device *dev)
506 struct gfar_private *priv = netdev_priv(dev);
507 struct gfar *regs = priv->regs;
510 phy_stop(priv->phydev);
513 spin_lock_irqsave(&priv->lock, flags);
517 spin_unlock_irqrestore(&priv->lock, flags);
520 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
521 free_irq(priv->interruptError, dev);
522 free_irq(priv->interruptTransmit, dev);
523 free_irq(priv->interruptReceive, dev);
525 free_irq(priv->interruptTransmit, dev);
528 free_skb_resources(priv);
530 dma_free_coherent(NULL,
531 sizeof(struct txbd8)*priv->tx_ring_size
532 + sizeof(struct rxbd8)*priv->rx_ring_size,
534 gfar_read(®s->tbase0));
537 /* If there are any tx skbs or rx skbs still around, free them.
538 * Then free tx_skbuff and rx_skbuff */
539 static void free_skb_resources(struct gfar_private *priv)
545 /* Go through all the buffer descriptors and free their data buffers */
546 txbdp = priv->tx_bd_base;
548 for (i = 0; i < priv->tx_ring_size; i++) {
550 if (priv->tx_skbuff[i]) {
551 dma_unmap_single(NULL, txbdp->bufPtr,
554 dev_kfree_skb_any(priv->tx_skbuff[i]);
555 priv->tx_skbuff[i] = NULL;
559 kfree(priv->tx_skbuff);
561 rxbdp = priv->rx_bd_base;
563 /* rx_skbuff is not guaranteed to be allocated, so only
564 * free it and its contents if it is allocated */
565 if(priv->rx_skbuff != NULL) {
566 for (i = 0; i < priv->rx_ring_size; i++) {
567 if (priv->rx_skbuff[i]) {
568 dma_unmap_single(NULL, rxbdp->bufPtr,
569 priv->rx_buffer_size,
572 dev_kfree_skb_any(priv->rx_skbuff[i]);
573 priv->rx_skbuff[i] = NULL;
583 kfree(priv->rx_skbuff);
587 void gfar_start(struct net_device *dev)
589 struct gfar_private *priv = netdev_priv(dev);
590 struct gfar *regs = priv->regs;
593 /* Enable Rx and Tx in MACCFG1 */
594 tempval = gfar_read(®s->maccfg1);
595 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
596 gfar_write(®s->maccfg1, tempval);
598 /* Initialize DMACTRL to have WWR and WOP */
599 tempval = gfar_read(&priv->regs->dmactrl);
600 tempval |= DMACTRL_INIT_SETTINGS;
601 gfar_write(&priv->regs->dmactrl, tempval);
603 /* Clear THLT, so that the DMA starts polling now */
604 gfar_write(®s->tstat, TSTAT_CLEAR_THALT);
606 /* Make sure we aren't stopped */
607 tempval = gfar_read(&priv->regs->dmactrl);
608 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
609 gfar_write(&priv->regs->dmactrl, tempval);
611 /* Unmask the interrupts we look for */
612 gfar_write(®s->imask, IMASK_DEFAULT);
615 /* Bring the controller up and running */
616 int startup_gfar(struct net_device *dev)
623 struct gfar_private *priv = netdev_priv(dev);
624 struct gfar *regs = priv->regs;
629 gfar_write(®s->imask, IMASK_INIT_CLEAR);
631 /* Allocate memory for the buffer descriptors */
632 vaddr = (unsigned long) dma_alloc_coherent(NULL,
633 sizeof (struct txbd8) * priv->tx_ring_size +
634 sizeof (struct rxbd8) * priv->rx_ring_size,
638 if (netif_msg_ifup(priv))
639 printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
644 priv->tx_bd_base = (struct txbd8 *) vaddr;
646 /* enet DMA only understands physical addresses */
647 gfar_write(®s->tbase0, addr);
649 /* Start the rx descriptor ring where the tx ring leaves off */
650 addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
651 vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
652 priv->rx_bd_base = (struct rxbd8 *) vaddr;
653 gfar_write(®s->rbase0, addr);
655 /* Setup the skbuff rings */
657 (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
658 priv->tx_ring_size, GFP_KERNEL);
660 if (NULL == priv->tx_skbuff) {
661 if (netif_msg_ifup(priv))
662 printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
668 for (i = 0; i < priv->tx_ring_size; i++)
669 priv->tx_skbuff[i] = NULL;
672 (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
673 priv->rx_ring_size, GFP_KERNEL);
675 if (NULL == priv->rx_skbuff) {
676 if (netif_msg_ifup(priv))
677 printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
683 for (i = 0; i < priv->rx_ring_size; i++)
684 priv->rx_skbuff[i] = NULL;
686 /* Initialize some variables in our dev structure */
687 priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
688 priv->cur_rx = priv->rx_bd_base;
689 priv->skb_curtx = priv->skb_dirtytx = 0;
692 /* Initialize Transmit Descriptor Ring */
693 txbdp = priv->tx_bd_base;
694 for (i = 0; i < priv->tx_ring_size; i++) {
701 /* Set the last descriptor in the ring to indicate wrap */
703 txbdp->status |= TXBD_WRAP;
705 rxbdp = priv->rx_bd_base;
706 for (i = 0; i < priv->rx_ring_size; i++) {
707 struct sk_buff *skb = NULL;
711 skb = gfar_new_skb(dev, rxbdp);
713 priv->rx_skbuff[i] = skb;
718 /* Set the last descriptor in the ring to wrap */
720 rxbdp->status |= RXBD_WRAP;
722 /* If the device has multiple interrupts, register for
723 * them. Otherwise, only register for the one */
724 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
725 /* Install our interrupt handlers for Error,
726 * Transmit, and Receive */
727 if (request_irq(priv->interruptError, gfar_error,
728 0, "enet_error", dev) < 0) {
729 if (netif_msg_intr(priv))
730 printk(KERN_ERR "%s: Can't get IRQ %d\n",
731 dev->name, priv->interruptError);
737 if (request_irq(priv->interruptTransmit, gfar_transmit,
738 0, "enet_tx", dev) < 0) {
739 if (netif_msg_intr(priv))
740 printk(KERN_ERR "%s: Can't get IRQ %d\n",
741 dev->name, priv->interruptTransmit);
748 if (request_irq(priv->interruptReceive, gfar_receive,
749 0, "enet_rx", dev) < 0) {
750 if (netif_msg_intr(priv))
751 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
752 dev->name, priv->interruptReceive);
758 if (request_irq(priv->interruptTransmit, gfar_interrupt,
759 0, "gfar_interrupt", dev) < 0) {
760 if (netif_msg_intr(priv))
761 printk(KERN_ERR "%s: Can't get IRQ %d\n",
762 dev->name, priv->interruptError);
769 phy_start(priv->phydev);
771 /* Configure the coalescing support */
772 if (priv->txcoalescing)
773 gfar_write(®s->txic,
774 mk_ic_value(priv->txcount, priv->txtime));
776 gfar_write(®s->txic, 0);
778 if (priv->rxcoalescing)
779 gfar_write(®s->rxic,
780 mk_ic_value(priv->rxcount, priv->rxtime));
782 gfar_write(®s->rxic, 0);
784 if (priv->rx_csum_enable)
785 rctrl |= RCTRL_CHECKSUMMING;
787 if (priv->extended_hash) {
788 rctrl |= RCTRL_EXTHASH;
790 gfar_clear_exact_match(dev);
794 if (priv->vlan_enable)
798 rctrl &= ~RCTRL_PAL_MASK;
799 rctrl |= RCTRL_PADDING(priv->padding);
802 /* Init rctrl based on our settings */
803 gfar_write(&priv->regs->rctrl, rctrl);
805 if (dev->features & NETIF_F_IP_CSUM)
806 gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
808 /* Set the extraction length and index */
809 attrs = ATTRELI_EL(priv->rx_stash_size) |
810 ATTRELI_EI(priv->rx_stash_index);
812 gfar_write(&priv->regs->attreli, attrs);
814 /* Start with defaults, and add stashing or locking
815 * depending on the approprate variables */
816 attrs = ATTR_INIT_SETTINGS;
818 if (priv->bd_stash_en)
819 attrs |= ATTR_BDSTASH;
821 if (priv->rx_stash_size != 0)
822 attrs |= ATTR_BUFSTASH;
824 gfar_write(&priv->regs->attr, attrs);
826 gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
827 gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
828 gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
830 /* Start the controller */
836 free_irq(priv->interruptTransmit, dev);
838 free_irq(priv->interruptError, dev);
841 free_skb_resources(priv);
843 dma_free_coherent(NULL,
844 sizeof(struct txbd8)*priv->tx_ring_size
845 + sizeof(struct rxbd8)*priv->rx_ring_size,
847 gfar_read(®s->tbase0));
852 /* Called when something needs to use the ethernet device */
853 /* Returns 0 for success. */
854 static int gfar_enet_open(struct net_device *dev)
858 /* Initialize a bunch of registers */
861 gfar_set_mac_address(dev);
868 err = startup_gfar(dev);
870 netif_start_queue(dev);
875 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb, struct txbd8 *bdp)
877 struct txfcb *fcb = (struct txfcb *)skb_push (skb, GMAC_FCB_LEN);
879 memset(fcb, 0, GMAC_FCB_LEN);
884 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
888 /* If we're here, it's a IP packet with a TCP or UDP
889 * payload. We set it to checksum, using a pseudo-header
892 flags = TXFCB_DEFAULT;
894 /* Tell the controller what the protocol is */
895 /* And provide the already calculated phcs */
896 if (skb->nh.iph->protocol == IPPROTO_UDP) {
898 fcb->phcs = skb->h.uh->check;
900 fcb->phcs = skb->h.th->check;
902 /* l3os is the distance between the start of the
903 * frame (skb->data) and the start of the IP hdr.
904 * l4os is the distance between the start of the
905 * l3 hdr and the l4 hdr */
906 fcb->l3os = (u16)(skb->nh.raw - skb->data - GMAC_FCB_LEN);
907 fcb->l4os = (u16)(skb->h.raw - skb->nh.raw);
912 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
914 fcb->flags |= TXFCB_VLN;
915 fcb->vlctl = vlan_tx_tag_get(skb);
918 /* This is called by the kernel when a frame is ready for transmission. */
919 /* It is pointed to by the dev->hard_start_xmit function pointer */
920 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
922 struct gfar_private *priv = netdev_priv(dev);
923 struct txfcb *fcb = NULL;
927 /* Update transmit stats */
928 priv->stats.tx_bytes += skb->len;
931 spin_lock_irq(&priv->lock);
933 /* Point at the first free tx descriptor */
934 txbdp = priv->cur_tx;
936 /* Clear all but the WRAP status flags */
937 status = txbdp->status & TXBD_WRAP;
939 /* Set up checksumming */
940 if (likely((dev->features & NETIF_F_IP_CSUM)
941 && (CHECKSUM_HW == skb->ip_summed))) {
942 fcb = gfar_add_fcb(skb, txbdp);
944 gfar_tx_checksum(skb, fcb);
947 if (priv->vlan_enable &&
948 unlikely(priv->vlgrp && vlan_tx_tag_present(skb))) {
949 if (unlikely(NULL == fcb)) {
950 fcb = gfar_add_fcb(skb, txbdp);
954 gfar_tx_vlan(skb, fcb);
957 /* Set buffer length and pointer */
958 txbdp->length = skb->len;
959 txbdp->bufPtr = dma_map_single(NULL, skb->data,
960 skb->len, DMA_TO_DEVICE);
962 /* Save the skb pointer so we can free it later */
963 priv->tx_skbuff[priv->skb_curtx] = skb;
965 /* Update the current skb pointer (wrapping if this was the last) */
967 (priv->skb_curtx + 1) & TX_RING_MOD_MASK(priv->tx_ring_size);
969 /* Flag the BD as interrupt-causing */
970 status |= TXBD_INTERRUPT;
972 /* Flag the BD as ready to go, last in frame, and */
974 status |= (TXBD_READY | TXBD_LAST | TXBD_CRC);
976 dev->trans_start = jiffies;
978 txbdp->status = status;
980 /* If this was the last BD in the ring, the next one */
981 /* is at the beginning of the ring */
982 if (txbdp->status & TXBD_WRAP)
983 txbdp = priv->tx_bd_base;
987 /* If the next BD still needs to be cleaned up, then the bds
988 are full. We need to tell the kernel to stop sending us stuff. */
989 if (txbdp == priv->dirty_tx) {
990 netif_stop_queue(dev);
992 priv->stats.tx_fifo_errors++;
995 /* Update the current txbd to the next one */
996 priv->cur_tx = txbdp;
998 /* Tell the DMA to go go go */
999 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1002 spin_unlock_irq(&priv->lock);
1007 /* Stops the kernel queue, and halts the controller */
1008 static int gfar_close(struct net_device *dev)
1010 struct gfar_private *priv = netdev_priv(dev);
1013 /* Disconnect from the PHY */
1014 phy_disconnect(priv->phydev);
1015 priv->phydev = NULL;
1017 netif_stop_queue(dev);
1022 /* returns a net_device_stats structure pointer */
1023 static struct net_device_stats * gfar_get_stats(struct net_device *dev)
1025 struct gfar_private *priv = netdev_priv(dev);
1027 return &(priv->stats);
1030 /* Changes the mac address if the controller is not running. */
1031 int gfar_set_mac_address(struct net_device *dev)
1033 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1039 /* Enables and disables VLAN insertion/extraction */
1040 static void gfar_vlan_rx_register(struct net_device *dev,
1041 struct vlan_group *grp)
1043 struct gfar_private *priv = netdev_priv(dev);
1044 unsigned long flags;
1047 spin_lock_irqsave(&priv->lock, flags);
1052 /* Enable VLAN tag insertion */
1053 tempval = gfar_read(&priv->regs->tctrl);
1054 tempval |= TCTRL_VLINS;
1056 gfar_write(&priv->regs->tctrl, tempval);
1058 /* Enable VLAN tag extraction */
1059 tempval = gfar_read(&priv->regs->rctrl);
1060 tempval |= RCTRL_VLEX;
1061 gfar_write(&priv->regs->rctrl, tempval);
1063 /* Disable VLAN tag insertion */
1064 tempval = gfar_read(&priv->regs->tctrl);
1065 tempval &= ~TCTRL_VLINS;
1066 gfar_write(&priv->regs->tctrl, tempval);
1068 /* Disable VLAN tag extraction */
1069 tempval = gfar_read(&priv->regs->rctrl);
1070 tempval &= ~RCTRL_VLEX;
1071 gfar_write(&priv->regs->rctrl, tempval);
1074 spin_unlock_irqrestore(&priv->lock, flags);
1078 static void gfar_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid)
1080 struct gfar_private *priv = netdev_priv(dev);
1081 unsigned long flags;
1083 spin_lock_irqsave(&priv->lock, flags);
1086 priv->vlgrp->vlan_devices[vid] = NULL;
1088 spin_unlock_irqrestore(&priv->lock, flags);
1092 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1094 int tempsize, tempval;
1095 struct gfar_private *priv = netdev_priv(dev);
1096 int oldsize = priv->rx_buffer_size;
1097 int frame_size = new_mtu + ETH_HLEN;
1099 if (priv->vlan_enable)
1100 frame_size += VLAN_ETH_HLEN;
1102 if (gfar_uses_fcb(priv))
1103 frame_size += GMAC_FCB_LEN;
1105 frame_size += priv->padding;
1107 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1108 if (netif_msg_drv(priv))
1109 printk(KERN_ERR "%s: Invalid MTU setting\n",
1115 (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1116 INCREMENTAL_BUFFER_SIZE;
1118 /* Only stop and start the controller if it isn't already
1119 * stopped, and we changed something */
1120 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1123 priv->rx_buffer_size = tempsize;
1127 gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1128 gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1130 /* If the mtu is larger than the max size for standard
1131 * ethernet frames (ie, a jumbo frame), then set maccfg2
1132 * to allow huge frames, and to check the length */
1133 tempval = gfar_read(&priv->regs->maccfg2);
1135 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1136 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1138 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1140 gfar_write(&priv->regs->maccfg2, tempval);
1142 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1148 /* gfar_timeout gets called when a packet has not been
1149 * transmitted after a set amount of time.
1150 * For now, assume that clearing out all the structures, and
1151 * starting over will fix the problem. */
1152 static void gfar_timeout(struct net_device *dev)
1154 struct gfar_private *priv = netdev_priv(dev);
1156 priv->stats.tx_errors++;
1158 if (dev->flags & IFF_UP) {
1163 netif_schedule(dev);
1166 /* Interrupt Handler for Transmit complete */
1167 static irqreturn_t gfar_transmit(int irq, void *dev_id, struct pt_regs *regs)
1169 struct net_device *dev = (struct net_device *) dev_id;
1170 struct gfar_private *priv = netdev_priv(dev);
1174 gfar_write(&priv->regs->ievent, IEVENT_TX_MASK);
1177 spin_lock(&priv->lock);
1178 bdp = priv->dirty_tx;
1179 while ((bdp->status & TXBD_READY) == 0) {
1180 /* If dirty_tx and cur_tx are the same, then either the */
1181 /* ring is empty or full now (it could only be full in the beginning, */
1182 /* obviously). If it is empty, we are done. */
1183 if ((bdp == priv->cur_tx) && (netif_queue_stopped(dev) == 0))
1186 priv->stats.tx_packets++;
1188 /* Deferred means some collisions occurred during transmit, */
1189 /* but we eventually sent the packet. */
1190 if (bdp->status & TXBD_DEF)
1191 priv->stats.collisions++;
1193 /* Free the sk buffer associated with this TxBD */
1194 dev_kfree_skb_irq(priv->tx_skbuff[priv->skb_dirtytx]);
1195 priv->tx_skbuff[priv->skb_dirtytx] = NULL;
1197 (priv->skb_dirtytx +
1198 1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1200 /* update bdp to point at next bd in the ring (wrapping if necessary) */
1201 if (bdp->status & TXBD_WRAP)
1202 bdp = priv->tx_bd_base;
1206 /* Move dirty_tx to be the next bd */
1207 priv->dirty_tx = bdp;
1209 /* We freed a buffer, so now we can restart transmission */
1210 if (netif_queue_stopped(dev))
1211 netif_wake_queue(dev);
1212 } /* while ((bdp->status & TXBD_READY) == 0) */
1214 /* If we are coalescing the interrupts, reset the timer */
1215 /* Otherwise, clear it */
1216 if (priv->txcoalescing)
1217 gfar_write(&priv->regs->txic,
1218 mk_ic_value(priv->txcount, priv->txtime));
1220 gfar_write(&priv->regs->txic, 0);
1222 spin_unlock(&priv->lock);
1227 struct sk_buff * gfar_new_skb(struct net_device *dev, struct rxbd8 *bdp)
1229 unsigned int alignamount;
1230 struct gfar_private *priv = netdev_priv(dev);
1231 struct sk_buff *skb = NULL;
1232 unsigned int timeout = SKB_ALLOC_TIMEOUT;
1234 /* We have to allocate the skb, so keep trying till we succeed */
1235 while ((!skb) && timeout--)
1236 skb = dev_alloc_skb(priv->rx_buffer_size + RXBUF_ALIGNMENT);
1241 alignamount = RXBUF_ALIGNMENT -
1242 (((unsigned) skb->data) & (RXBUF_ALIGNMENT - 1));
1244 /* We need the data buffer to be aligned properly. We will reserve
1245 * as many bytes as needed to align the data properly
1247 skb_reserve(skb, alignamount);
1251 bdp->bufPtr = dma_map_single(NULL, skb->data,
1252 priv->rx_buffer_size, DMA_FROM_DEVICE);
1256 /* Mark the buffer empty */
1257 bdp->status |= (RXBD_EMPTY | RXBD_INTERRUPT);
1262 static inline void count_errors(unsigned short status, struct gfar_private *priv)
1264 struct net_device_stats *stats = &priv->stats;
1265 struct gfar_extra_stats *estats = &priv->extra_stats;
1267 /* If the packet was truncated, none of the other errors
1269 if (status & RXBD_TRUNCATED) {
1270 stats->rx_length_errors++;
1276 /* Count the errors, if there were any */
1277 if (status & (RXBD_LARGE | RXBD_SHORT)) {
1278 stats->rx_length_errors++;
1280 if (status & RXBD_LARGE)
1285 if (status & RXBD_NONOCTET) {
1286 stats->rx_frame_errors++;
1287 estats->rx_nonoctet++;
1289 if (status & RXBD_CRCERR) {
1290 estats->rx_crcerr++;
1291 stats->rx_crc_errors++;
1293 if (status & RXBD_OVERRUN) {
1294 estats->rx_overrun++;
1295 stats->rx_crc_errors++;
1299 irqreturn_t gfar_receive(int irq, void *dev_id, struct pt_regs *regs)
1301 struct net_device *dev = (struct net_device *) dev_id;
1302 struct gfar_private *priv = netdev_priv(dev);
1304 #ifdef CONFIG_GFAR_NAPI
1308 /* Clear IEVENT, so rx interrupt isn't called again
1309 * because of this interrupt */
1310 gfar_write(&priv->regs->ievent, IEVENT_RX_MASK);
1313 #ifdef CONFIG_GFAR_NAPI
1314 if (netif_rx_schedule_prep(dev)) {
1315 tempval = gfar_read(&priv->regs->imask);
1316 tempval &= IMASK_RX_DISABLED;
1317 gfar_write(&priv->regs->imask, tempval);
1319 __netif_rx_schedule(dev);
1321 if (netif_msg_rx_err(priv))
1322 printk(KERN_DEBUG "%s: receive called twice (%x)[%x]\n",
1323 dev->name, gfar_read(&priv->regs->ievent),
1324 gfar_read(&priv->regs->imask));
1328 spin_lock(&priv->lock);
1329 gfar_clean_rx_ring(dev, priv->rx_ring_size);
1331 /* If we are coalescing interrupts, update the timer */
1332 /* Otherwise, clear it */
1333 if (priv->rxcoalescing)
1334 gfar_write(&priv->regs->rxic,
1335 mk_ic_value(priv->rxcount, priv->rxtime));
1337 gfar_write(&priv->regs->rxic, 0);
1339 spin_unlock(&priv->lock);
1345 static inline int gfar_rx_vlan(struct sk_buff *skb,
1346 struct vlan_group *vlgrp, unsigned short vlctl)
1348 #ifdef CONFIG_GFAR_NAPI
1349 return vlan_hwaccel_receive_skb(skb, vlgrp, vlctl);
1351 return vlan_hwaccel_rx(skb, vlgrp, vlctl);
1355 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1357 /* If valid headers were found, and valid sums
1358 * were verified, then we tell the kernel that no
1359 * checksumming is necessary. Otherwise, it is */
1360 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1361 skb->ip_summed = CHECKSUM_UNNECESSARY;
1363 skb->ip_summed = CHECKSUM_NONE;
1367 static inline struct rxfcb *gfar_get_fcb(struct sk_buff *skb)
1369 struct rxfcb *fcb = (struct rxfcb *)skb->data;
1371 /* Remove the FCB from the skb */
1372 skb_pull(skb, GMAC_FCB_LEN);
1377 /* gfar_process_frame() -- handle one incoming packet if skb
1379 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1382 struct gfar_private *priv = netdev_priv(dev);
1383 struct rxfcb *fcb = NULL;
1386 if (netif_msg_rx_err(priv))
1387 printk(KERN_WARNING "%s: Missing skb!!.\n", dev->name);
1388 priv->stats.rx_dropped++;
1389 priv->extra_stats.rx_skbmissing++;
1393 /* Prep the skb for the packet */
1394 skb_put(skb, length);
1396 /* Grab the FCB if there is one */
1397 if (gfar_uses_fcb(priv))
1398 fcb = gfar_get_fcb(skb);
1400 /* Remove the padded bytes, if there are any */
1402 skb_pull(skb, priv->padding);
1404 if (priv->rx_csum_enable)
1405 gfar_rx_checksum(skb, fcb);
1407 /* Tell the skb what kind of packet this is */
1408 skb->protocol = eth_type_trans(skb, dev);
1410 /* Send the packet up the stack */
1411 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
1412 ret = gfar_rx_vlan(skb, priv->vlgrp, fcb->vlctl);
1416 if (NET_RX_DROP == ret)
1417 priv->extra_stats.kernel_dropped++;
1423 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1424 * until the budget/quota has been reached. Returns the number
1427 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1430 struct sk_buff *skb;
1433 struct gfar_private *priv = netdev_priv(dev);
1435 /* Get the first full descriptor */
1438 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1439 skb = priv->rx_skbuff[priv->skb_currx];
1442 (RXBD_LARGE | RXBD_SHORT | RXBD_NONOCTET
1443 | RXBD_CRCERR | RXBD_OVERRUN | RXBD_TRUNCATED))) {
1444 /* Increment the number of packets */
1445 priv->stats.rx_packets++;
1448 /* Remove the FCS from the packet length */
1449 pkt_len = bdp->length - 4;
1451 gfar_process_frame(dev, skb, pkt_len);
1453 priv->stats.rx_bytes += pkt_len;
1455 count_errors(bdp->status, priv);
1458 dev_kfree_skb_any(skb);
1460 priv->rx_skbuff[priv->skb_currx] = NULL;
1463 dev->last_rx = jiffies;
1465 /* Clear the status flags for this buffer */
1466 bdp->status &= ~RXBD_STATS;
1468 /* Add another skb for the future */
1469 skb = gfar_new_skb(dev, bdp);
1470 priv->rx_skbuff[priv->skb_currx] = skb;
1472 /* Update to the next pointer */
1473 if (bdp->status & RXBD_WRAP)
1474 bdp = priv->rx_bd_base;
1478 /* update to point at the next skb */
1481 1) & RX_RING_MOD_MASK(priv->rx_ring_size);
1485 /* Update the current rxbd pointer to be the next one */
1488 /* If no packets have arrived since the
1489 * last one we processed, clear the IEVENT RX and
1490 * BSY bits so that another interrupt won't be
1491 * generated when we set IMASK */
1492 if (bdp->status & RXBD_EMPTY)
1493 gfar_write(&priv->regs->ievent, IEVENT_RX_MASK);
1498 #ifdef CONFIG_GFAR_NAPI
1499 static int gfar_poll(struct net_device *dev, int *budget)
1502 struct gfar_private *priv = netdev_priv(dev);
1503 int rx_work_limit = *budget;
1505 if (rx_work_limit > dev->quota)
1506 rx_work_limit = dev->quota;
1508 howmany = gfar_clean_rx_ring(dev, rx_work_limit);
1510 dev->quota -= howmany;
1511 rx_work_limit -= howmany;
1514 if (rx_work_limit >= 0) {
1515 netif_rx_complete(dev);
1517 /* Clear the halt bit in RSTAT */
1518 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1520 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1522 /* If we are coalescing interrupts, update the timer */
1523 /* Otherwise, clear it */
1524 if (priv->rxcoalescing)
1525 gfar_write(&priv->regs->rxic,
1526 mk_ic_value(priv->rxcount, priv->rxtime));
1528 gfar_write(&priv->regs->rxic, 0);
1531 return (rx_work_limit < 0) ? 1 : 0;
1535 /* The interrupt handler for devices with one interrupt */
1536 static irqreturn_t gfar_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1538 struct net_device *dev = dev_id;
1539 struct gfar_private *priv = netdev_priv(dev);
1541 /* Save ievent for future reference */
1542 u32 events = gfar_read(&priv->regs->ievent);
1545 gfar_write(&priv->regs->ievent, events);
1547 /* Check for reception */
1548 if ((events & IEVENT_RXF0) || (events & IEVENT_RXB0))
1549 gfar_receive(irq, dev_id, regs);
1551 /* Check for transmit completion */
1552 if ((events & IEVENT_TXF) || (events & IEVENT_TXB))
1553 gfar_transmit(irq, dev_id, regs);
1555 /* Update error statistics */
1556 if (events & IEVENT_TXE) {
1557 priv->stats.tx_errors++;
1559 if (events & IEVENT_LC)
1560 priv->stats.tx_window_errors++;
1561 if (events & IEVENT_CRL)
1562 priv->stats.tx_aborted_errors++;
1563 if (events & IEVENT_XFUN) {
1564 if (netif_msg_tx_err(priv))
1565 printk(KERN_WARNING "%s: tx underrun. dropped packet\n", dev->name);
1566 priv->stats.tx_dropped++;
1567 priv->extra_stats.tx_underrun++;
1569 /* Reactivate the Tx Queues */
1570 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1573 if (events & IEVENT_BSY) {
1574 priv->stats.rx_errors++;
1575 priv->extra_stats.rx_bsy++;
1577 gfar_receive(irq, dev_id, regs);
1579 #ifndef CONFIG_GFAR_NAPI
1580 /* Clear the halt bit in RSTAT */
1581 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1584 if (netif_msg_rx_err(priv))
1585 printk(KERN_DEBUG "%s: busy error (rhalt: %x)\n",
1587 gfar_read(&priv->regs->rstat));
1589 if (events & IEVENT_BABR) {
1590 priv->stats.rx_errors++;
1591 priv->extra_stats.rx_babr++;
1593 if (netif_msg_rx_err(priv))
1594 printk(KERN_DEBUG "%s: babbling error\n", dev->name);
1596 if (events & IEVENT_EBERR) {
1597 priv->extra_stats.eberr++;
1598 if (netif_msg_rx_err(priv))
1599 printk(KERN_DEBUG "%s: EBERR\n", dev->name);
1601 if ((events & IEVENT_RXC) && (netif_msg_rx_err(priv)))
1602 printk(KERN_DEBUG "%s: control frame\n", dev->name);
1604 if (events & IEVENT_BABT) {
1605 priv->extra_stats.tx_babt++;
1606 if (netif_msg_rx_err(priv))
1607 printk(KERN_DEBUG "%s: babt error\n", dev->name);
1613 /* Called every time the controller might need to be made
1614 * aware of new link state. The PHY code conveys this
1615 * information through variables in the phydev structure, and this
1616 * function converts those variables into the appropriate
1617 * register values, and can bring down the device if needed.
1619 static void adjust_link(struct net_device *dev)
1621 struct gfar_private *priv = netdev_priv(dev);
1622 struct gfar *regs = priv->regs;
1623 unsigned long flags;
1624 struct phy_device *phydev = priv->phydev;
1627 spin_lock_irqsave(&priv->lock, flags);
1629 u32 tempval = gfar_read(®s->maccfg2);
1630 u32 ecntrl = gfar_read(®s->ecntrl);
1632 /* Now we make sure that we can be in full duplex mode.
1633 * If not, we operate in half-duplex mode. */
1634 if (phydev->duplex != priv->oldduplex) {
1636 if (!(phydev->duplex))
1637 tempval &= ~(MACCFG2_FULL_DUPLEX);
1639 tempval |= MACCFG2_FULL_DUPLEX;
1641 priv->oldduplex = phydev->duplex;
1644 if (phydev->speed != priv->oldspeed) {
1646 switch (phydev->speed) {
1649 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
1654 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
1656 /* Reduced mode distinguishes
1657 * between 10 and 100 */
1658 if (phydev->speed == SPEED_100)
1659 ecntrl |= ECNTRL_R100;
1661 ecntrl &= ~(ECNTRL_R100);
1664 if (netif_msg_link(priv))
1666 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
1667 dev->name, phydev->speed);
1671 priv->oldspeed = phydev->speed;
1674 gfar_write(®s->maccfg2, tempval);
1675 gfar_write(®s->ecntrl, ecntrl);
1677 if (!priv->oldlink) {
1680 netif_schedule(dev);
1682 } else if (priv->oldlink) {
1686 priv->oldduplex = -1;
1689 if (new_state && netif_msg_link(priv))
1690 phy_print_status(phydev);
1692 spin_unlock_irqrestore(&priv->lock, flags);
1695 /* Update the hash table based on the current list of multicast
1696 * addresses we subscribe to. Also, change the promiscuity of
1697 * the device based on the flags (this function is called
1698 * whenever dev->flags is changed */
1699 static void gfar_set_multi(struct net_device *dev)
1701 struct dev_mc_list *mc_ptr;
1702 struct gfar_private *priv = netdev_priv(dev);
1703 struct gfar *regs = priv->regs;
1706 if(dev->flags & IFF_PROMISC) {
1707 if (netif_msg_drv(priv))
1708 printk(KERN_INFO "%s: Entering promiscuous mode.\n",
1710 /* Set RCTRL to PROM */
1711 tempval = gfar_read(®s->rctrl);
1712 tempval |= RCTRL_PROM;
1713 gfar_write(®s->rctrl, tempval);
1715 /* Set RCTRL to not PROM */
1716 tempval = gfar_read(®s->rctrl);
1717 tempval &= ~(RCTRL_PROM);
1718 gfar_write(®s->rctrl, tempval);
1721 if(dev->flags & IFF_ALLMULTI) {
1722 /* Set the hash to rx all multicast frames */
1723 gfar_write(®s->igaddr0, 0xffffffff);
1724 gfar_write(®s->igaddr1, 0xffffffff);
1725 gfar_write(®s->igaddr2, 0xffffffff);
1726 gfar_write(®s->igaddr3, 0xffffffff);
1727 gfar_write(®s->igaddr4, 0xffffffff);
1728 gfar_write(®s->igaddr5, 0xffffffff);
1729 gfar_write(®s->igaddr6, 0xffffffff);
1730 gfar_write(®s->igaddr7, 0xffffffff);
1731 gfar_write(®s->gaddr0, 0xffffffff);
1732 gfar_write(®s->gaddr1, 0xffffffff);
1733 gfar_write(®s->gaddr2, 0xffffffff);
1734 gfar_write(®s->gaddr3, 0xffffffff);
1735 gfar_write(®s->gaddr4, 0xffffffff);
1736 gfar_write(®s->gaddr5, 0xffffffff);
1737 gfar_write(®s->gaddr6, 0xffffffff);
1738 gfar_write(®s->gaddr7, 0xffffffff);
1743 /* zero out the hash */
1744 gfar_write(®s->igaddr0, 0x0);
1745 gfar_write(®s->igaddr1, 0x0);
1746 gfar_write(®s->igaddr2, 0x0);
1747 gfar_write(®s->igaddr3, 0x0);
1748 gfar_write(®s->igaddr4, 0x0);
1749 gfar_write(®s->igaddr5, 0x0);
1750 gfar_write(®s->igaddr6, 0x0);
1751 gfar_write(®s->igaddr7, 0x0);
1752 gfar_write(®s->gaddr0, 0x0);
1753 gfar_write(®s->gaddr1, 0x0);
1754 gfar_write(®s->gaddr2, 0x0);
1755 gfar_write(®s->gaddr3, 0x0);
1756 gfar_write(®s->gaddr4, 0x0);
1757 gfar_write(®s->gaddr5, 0x0);
1758 gfar_write(®s->gaddr6, 0x0);
1759 gfar_write(®s->gaddr7, 0x0);
1761 /* If we have extended hash tables, we need to
1762 * clear the exact match registers to prepare for
1764 if (priv->extended_hash) {
1765 em_num = GFAR_EM_NUM + 1;
1766 gfar_clear_exact_match(dev);
1773 if(dev->mc_count == 0)
1776 /* Parse the list, and set the appropriate bits */
1777 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
1779 gfar_set_mac_for_addr(dev, idx,
1783 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
1791 /* Clears each of the exact match registers to zero, so they
1792 * don't interfere with normal reception */
1793 static void gfar_clear_exact_match(struct net_device *dev)
1796 u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
1798 for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
1799 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
1802 /* Set the appropriate hash bit for the given addr */
1803 /* The algorithm works like so:
1804 * 1) Take the Destination Address (ie the multicast address), and
1805 * do a CRC on it (little endian), and reverse the bits of the
1807 * 2) Use the 8 most significant bits as a hash into a 256-entry
1808 * table. The table is controlled through 8 32-bit registers:
1809 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
1810 * gaddr7. This means that the 3 most significant bits in the
1811 * hash index which gaddr register to use, and the 5 other bits
1812 * indicate which bit (assuming an IBM numbering scheme, which
1813 * for PowerPC (tm) is usually the case) in the register holds
1815 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
1818 struct gfar_private *priv = netdev_priv(dev);
1819 u32 result = ether_crc(MAC_ADDR_LEN, addr);
1820 int width = priv->hash_width;
1821 u8 whichbit = (result >> (32 - width)) & 0x1f;
1822 u8 whichreg = result >> (32 - width + 5);
1823 u32 value = (1 << (31-whichbit));
1825 tempval = gfar_read(priv->hash_regs[whichreg]);
1827 gfar_write(priv->hash_regs[whichreg], tempval);
1833 /* There are multiple MAC Address register pairs on some controllers
1834 * This function sets the numth pair to a given address
1836 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
1838 struct gfar_private *priv = netdev_priv(dev);
1840 char tmpbuf[MAC_ADDR_LEN];
1842 u32 *macptr = &priv->regs->macstnaddr1;
1846 /* Now copy it into the mac registers backwards, cuz */
1847 /* little endian is silly */
1848 for (idx = 0; idx < MAC_ADDR_LEN; idx++)
1849 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
1851 gfar_write(macptr, *((u32 *) (tmpbuf)));
1853 tempval = *((u32 *) (tmpbuf + 4));
1855 gfar_write(macptr+1, tempval);
1858 /* GFAR error interrupt handler */
1859 static irqreturn_t gfar_error(int irq, void *dev_id, struct pt_regs *regs)
1861 struct net_device *dev = dev_id;
1862 struct gfar_private *priv = netdev_priv(dev);
1864 /* Save ievent for future reference */
1865 u32 events = gfar_read(&priv->regs->ievent);
1868 gfar_write(&priv->regs->ievent, IEVENT_ERR_MASK);
1871 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
1872 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
1873 dev->name, events, gfar_read(&priv->regs->imask));
1875 /* Update the error counters */
1876 if (events & IEVENT_TXE) {
1877 priv->stats.tx_errors++;
1879 if (events & IEVENT_LC)
1880 priv->stats.tx_window_errors++;
1881 if (events & IEVENT_CRL)
1882 priv->stats.tx_aborted_errors++;
1883 if (events & IEVENT_XFUN) {
1884 if (netif_msg_tx_err(priv))
1885 printk(KERN_DEBUG "%s: underrun. packet dropped.\n",
1887 priv->stats.tx_dropped++;
1888 priv->extra_stats.tx_underrun++;
1890 /* Reactivate the Tx Queues */
1891 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1893 if (netif_msg_tx_err(priv))
1894 printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
1896 if (events & IEVENT_BSY) {
1897 priv->stats.rx_errors++;
1898 priv->extra_stats.rx_bsy++;
1900 gfar_receive(irq, dev_id, regs);
1902 #ifndef CONFIG_GFAR_NAPI
1903 /* Clear the halt bit in RSTAT */
1904 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1907 if (netif_msg_rx_err(priv))
1908 printk(KERN_DEBUG "%s: busy error (rhalt: %x)\n",
1910 gfar_read(&priv->regs->rstat));
1912 if (events & IEVENT_BABR) {
1913 priv->stats.rx_errors++;
1914 priv->extra_stats.rx_babr++;
1916 if (netif_msg_rx_err(priv))
1917 printk(KERN_DEBUG "%s: babbling error\n", dev->name);
1919 if (events & IEVENT_EBERR) {
1920 priv->extra_stats.eberr++;
1921 if (netif_msg_rx_err(priv))
1922 printk(KERN_DEBUG "%s: EBERR\n", dev->name);
1924 if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
1925 if (netif_msg_rx_status(priv))
1926 printk(KERN_DEBUG "%s: control frame\n", dev->name);
1928 if (events & IEVENT_BABT) {
1929 priv->extra_stats.tx_babt++;
1930 if (netif_msg_tx_err(priv))
1931 printk(KERN_DEBUG "%s: babt error\n", dev->name);
1936 /* Structure for a device driver */
1937 static struct platform_driver gfar_driver = {
1938 .probe = gfar_probe,
1939 .remove = gfar_remove,
1941 .name = "fsl-gianfar",
1945 static int __init gfar_init(void)
1947 int err = gfar_mdio_init();
1952 err = platform_driver_register(&gfar_driver);
1960 static void __exit gfar_exit(void)
1962 platform_driver_unregister(&gfar_driver);
1966 module_init(gfar_init);
1967 module_exit(gfar_exit);