2 * drivers/net/gianfar.c
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
10 * Maintainer: Kumar Gala
11 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
13 * Copyright 2002-2009 Freescale Semiconductor, Inc.
14 * Copyright 2007 MontaVista Software, Inc.
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
21 * Gianfar: AKA Lambda Draconis, "Dragon"
29 * The driver is initialized through of_device. Configuration information
30 * is therefore conveyed through an OF-style device tree.
32 * The Gianfar Ethernet Controller uses a ring of buffer
33 * descriptors. The beginning is indicated by a register
34 * pointing to the physical address of the start of the ring.
35 * The end is determined by a "wrap" bit being set in the
36 * last descriptor of the ring.
38 * When a packet is received, the RXF bit in the
39 * IEVENT register is set, triggering an interrupt when the
40 * corresponding bit in the IMASK register is also set (if
41 * interrupt coalescing is active, then the interrupt may not
42 * happen immediately, but will wait until either a set number
43 * of frames or amount of time have passed). In NAPI, the
44 * interrupt handler will signal there is work to be done, and
45 * exit. This method will start at the last known empty
46 * descriptor, and process every subsequent descriptor until there
47 * are none left with data (NAPI will stop after a set number of
48 * packets to give time to other tasks, but will eventually
49 * process all the packets). The data arrives inside a
50 * pre-allocated skb, and so after the skb is passed up to the
51 * stack, a new skb must be allocated, and the address field in
52 * the buffer descriptor must be updated to indicate this new
55 * When the kernel requests that a packet be transmitted, the
56 * driver starts where it left off last time, and points the
57 * descriptor at the buffer which was passed in. The driver
58 * then informs the DMA engine that there are packets ready to
59 * be transmitted. Once the controller is finished transmitting
60 * the packet, an interrupt may be triggered (under the same
61 * conditions as for reception, but depending on the TXF bit).
62 * The driver then cleans up the buffer.
65 #include <linux/kernel.h>
66 #include <linux/string.h>
67 #include <linux/errno.h>
68 #include <linux/unistd.h>
69 #include <linux/slab.h>
70 #include <linux/interrupt.h>
71 #include <linux/init.h>
72 #include <linux/delay.h>
73 #include <linux/netdevice.h>
74 #include <linux/etherdevice.h>
75 #include <linux/skbuff.h>
76 #include <linux/if_vlan.h>
77 #include <linux/spinlock.h>
79 #include <linux/of_mdio.h>
80 #include <linux/of_platform.h>
82 #include <linux/tcp.h>
83 #include <linux/udp.h>
85 #include <linux/net_tstamp.h>
90 #include <asm/uaccess.h>
91 #include <linux/module.h>
92 #include <linux/dma-mapping.h>
93 #include <linux/crc32.h>
94 #include <linux/mii.h>
95 #include <linux/phy.h>
96 #include <linux/phy_fixed.h>
100 #include "fsl_pq_mdio.h"
102 #define TX_TIMEOUT (1*HZ)
103 #undef BRIEF_GFAR_ERRORS
104 #undef VERBOSE_GFAR_ERRORS
106 const char gfar_driver_name[] = "Gianfar Ethernet";
107 const char gfar_driver_version[] = "1.3";
109 static int gfar_enet_open(struct net_device *dev);
110 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
111 static void gfar_reset_task(struct work_struct *work);
112 static void gfar_timeout(struct net_device *dev);
113 static int gfar_close(struct net_device *dev);
114 struct sk_buff *gfar_new_skb(struct net_device *dev);
115 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
116 struct sk_buff *skb);
117 static int gfar_set_mac_address(struct net_device *dev);
118 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
119 static irqreturn_t gfar_error(int irq, void *dev_id);
120 static irqreturn_t gfar_transmit(int irq, void *dev_id);
121 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
122 static void adjust_link(struct net_device *dev);
123 static void init_registers(struct net_device *dev);
124 static int init_phy(struct net_device *dev);
125 static int gfar_probe(struct platform_device *ofdev,
126 const struct of_device_id *match);
127 static int gfar_remove(struct platform_device *ofdev);
128 static void free_skb_resources(struct gfar_private *priv);
129 static void gfar_set_multi(struct net_device *dev);
130 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
131 static void gfar_configure_serdes(struct net_device *dev);
132 static int gfar_poll(struct napi_struct *napi, int budget);
133 #ifdef CONFIG_NET_POLL_CONTROLLER
134 static void gfar_netpoll(struct net_device *dev);
136 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
137 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
138 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
140 static void gfar_vlan_rx_register(struct net_device *netdev,
141 struct vlan_group *grp);
142 void gfar_halt(struct net_device *dev);
143 static void gfar_halt_nodisable(struct net_device *dev);
144 void gfar_start(struct net_device *dev);
145 static void gfar_clear_exact_match(struct net_device *dev);
146 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
147 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
149 MODULE_AUTHOR("Freescale Semiconductor, Inc");
150 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
151 MODULE_LICENSE("GPL");
153 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
160 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
161 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
162 lstatus |= BD_LFLAG(RXBD_WRAP);
166 bdp->lstatus = lstatus;
169 static int gfar_init_bds(struct net_device *ndev)
171 struct gfar_private *priv = netdev_priv(ndev);
172 struct gfar_priv_tx_q *tx_queue = NULL;
173 struct gfar_priv_rx_q *rx_queue = NULL;
178 for (i = 0; i < priv->num_tx_queues; i++) {
179 tx_queue = priv->tx_queue[i];
180 /* Initialize some variables in our dev structure */
181 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
182 tx_queue->dirty_tx = tx_queue->tx_bd_base;
183 tx_queue->cur_tx = tx_queue->tx_bd_base;
184 tx_queue->skb_curtx = 0;
185 tx_queue->skb_dirtytx = 0;
187 /* Initialize Transmit Descriptor Ring */
188 txbdp = tx_queue->tx_bd_base;
189 for (j = 0; j < tx_queue->tx_ring_size; j++) {
195 /* Set the last descriptor in the ring to indicate wrap */
197 txbdp->status |= TXBD_WRAP;
200 for (i = 0; i < priv->num_rx_queues; i++) {
201 rx_queue = priv->rx_queue[i];
202 rx_queue->cur_rx = rx_queue->rx_bd_base;
203 rx_queue->skb_currx = 0;
204 rxbdp = rx_queue->rx_bd_base;
206 for (j = 0; j < rx_queue->rx_ring_size; j++) {
207 struct sk_buff *skb = rx_queue->rx_skbuff[j];
210 gfar_init_rxbdp(rx_queue, rxbdp,
213 skb = gfar_new_skb(ndev);
215 pr_err("%s: Can't allocate RX buffers\n",
217 goto err_rxalloc_fail;
219 rx_queue->rx_skbuff[j] = skb;
221 gfar_new_rxbdp(rx_queue, rxbdp, skb);
232 free_skb_resources(priv);
236 static int gfar_alloc_skb_resources(struct net_device *ndev)
241 struct gfar_private *priv = netdev_priv(ndev);
242 struct device *dev = &priv->ofdev->dev;
243 struct gfar_priv_tx_q *tx_queue = NULL;
244 struct gfar_priv_rx_q *rx_queue = NULL;
246 priv->total_tx_ring_size = 0;
247 for (i = 0; i < priv->num_tx_queues; i++)
248 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
250 priv->total_rx_ring_size = 0;
251 for (i = 0; i < priv->num_rx_queues; i++)
252 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
254 /* Allocate memory for the buffer descriptors */
255 vaddr = dma_alloc_coherent(dev,
256 sizeof(struct txbd8) * priv->total_tx_ring_size +
257 sizeof(struct rxbd8) * priv->total_rx_ring_size,
260 if (netif_msg_ifup(priv))
261 pr_err("%s: Could not allocate buffer descriptors!\n",
266 for (i = 0; i < priv->num_tx_queues; i++) {
267 tx_queue = priv->tx_queue[i];
268 tx_queue->tx_bd_base = (struct txbd8 *) vaddr;
269 tx_queue->tx_bd_dma_base = addr;
270 tx_queue->dev = ndev;
271 /* enet DMA only understands physical addresses */
272 addr += sizeof(struct txbd8) *tx_queue->tx_ring_size;
273 vaddr += sizeof(struct txbd8) *tx_queue->tx_ring_size;
276 /* Start the rx descriptor ring where the tx ring leaves off */
277 for (i = 0; i < priv->num_rx_queues; i++) {
278 rx_queue = priv->rx_queue[i];
279 rx_queue->rx_bd_base = (struct rxbd8 *) vaddr;
280 rx_queue->rx_bd_dma_base = addr;
281 rx_queue->dev = ndev;
282 addr += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
283 vaddr += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
286 /* Setup the skbuff rings */
287 for (i = 0; i < priv->num_tx_queues; i++) {
288 tx_queue = priv->tx_queue[i];
289 tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) *
290 tx_queue->tx_ring_size, GFP_KERNEL);
291 if (!tx_queue->tx_skbuff) {
292 if (netif_msg_ifup(priv))
293 pr_err("%s: Could not allocate tx_skbuff\n",
298 for (k = 0; k < tx_queue->tx_ring_size; k++)
299 tx_queue->tx_skbuff[k] = NULL;
302 for (i = 0; i < priv->num_rx_queues; i++) {
303 rx_queue = priv->rx_queue[i];
304 rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) *
305 rx_queue->rx_ring_size, GFP_KERNEL);
307 if (!rx_queue->rx_skbuff) {
308 if (netif_msg_ifup(priv))
309 pr_err("%s: Could not allocate rx_skbuff\n",
314 for (j = 0; j < rx_queue->rx_ring_size; j++)
315 rx_queue->rx_skbuff[j] = NULL;
318 if (gfar_init_bds(ndev))
324 free_skb_resources(priv);
328 static void gfar_init_tx_rx_base(struct gfar_private *priv)
330 struct gfar __iomem *regs = priv->gfargrp[0].regs;
334 baddr = ®s->tbase0;
335 for(i = 0; i < priv->num_tx_queues; i++) {
336 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
340 baddr = ®s->rbase0;
341 for(i = 0; i < priv->num_rx_queues; i++) {
342 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
347 static void gfar_init_mac(struct net_device *ndev)
349 struct gfar_private *priv = netdev_priv(ndev);
350 struct gfar __iomem *regs = priv->gfargrp[0].regs;
355 /* write the tx/rx base registers */
356 gfar_init_tx_rx_base(priv);
358 /* Configure the coalescing support */
359 gfar_configure_coalescing(priv, 0xFF, 0xFF);
361 if (priv->rx_filer_enable) {
362 rctrl |= RCTRL_FILREN;
363 /* Program the RIR0 reg with the required distribution */
364 gfar_write(®s->rir0, DEFAULT_RIR0);
367 if (priv->rx_csum_enable)
368 rctrl |= RCTRL_CHECKSUMMING;
370 if (priv->extended_hash) {
371 rctrl |= RCTRL_EXTHASH;
373 gfar_clear_exact_match(ndev);
378 rctrl &= ~RCTRL_PAL_MASK;
379 rctrl |= RCTRL_PADDING(priv->padding);
382 /* Insert receive time stamps into padding alignment bytes */
383 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
384 rctrl &= ~RCTRL_PAL_MASK;
385 rctrl |= RCTRL_PADDING(8);
389 /* Enable HW time stamping if requested from user space */
390 if (priv->hwts_rx_en)
391 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
393 /* keep vlan related bits if it's enabled */
395 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
396 tctrl |= TCTRL_VLINS;
399 /* Init rctrl based on our settings */
400 gfar_write(®s->rctrl, rctrl);
402 if (ndev->features & NETIF_F_IP_CSUM)
403 tctrl |= TCTRL_INIT_CSUM;
405 tctrl |= TCTRL_TXSCHED_PRIO;
407 gfar_write(®s->tctrl, tctrl);
409 /* Set the extraction length and index */
410 attrs = ATTRELI_EL(priv->rx_stash_size) |
411 ATTRELI_EI(priv->rx_stash_index);
413 gfar_write(®s->attreli, attrs);
415 /* Start with defaults, and add stashing or locking
416 * depending on the approprate variables */
417 attrs = ATTR_INIT_SETTINGS;
419 if (priv->bd_stash_en)
420 attrs |= ATTR_BDSTASH;
422 if (priv->rx_stash_size != 0)
423 attrs |= ATTR_BUFSTASH;
425 gfar_write(®s->attr, attrs);
427 gfar_write(®s->fifo_tx_thr, priv->fifo_threshold);
428 gfar_write(®s->fifo_tx_starve, priv->fifo_starve);
429 gfar_write(®s->fifo_tx_starve_shutoff, priv->fifo_starve_off);
432 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
434 struct gfar_private *priv = netdev_priv(dev);
435 struct netdev_queue *txq;
436 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
437 unsigned long tx_packets = 0, tx_bytes = 0;
440 for (i = 0; i < priv->num_rx_queues; i++) {
441 rx_packets += priv->rx_queue[i]->stats.rx_packets;
442 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
443 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
446 dev->stats.rx_packets = rx_packets;
447 dev->stats.rx_bytes = rx_bytes;
448 dev->stats.rx_dropped = rx_dropped;
450 for (i = 0; i < priv->num_tx_queues; i++) {
451 txq = netdev_get_tx_queue(dev, i);
452 tx_bytes += txq->tx_bytes;
453 tx_packets += txq->tx_packets;
456 dev->stats.tx_bytes = tx_bytes;
457 dev->stats.tx_packets = tx_packets;
462 static const struct net_device_ops gfar_netdev_ops = {
463 .ndo_open = gfar_enet_open,
464 .ndo_start_xmit = gfar_start_xmit,
465 .ndo_stop = gfar_close,
466 .ndo_change_mtu = gfar_change_mtu,
467 .ndo_set_multicast_list = gfar_set_multi,
468 .ndo_tx_timeout = gfar_timeout,
469 .ndo_do_ioctl = gfar_ioctl,
470 .ndo_get_stats = gfar_get_stats,
471 .ndo_vlan_rx_register = gfar_vlan_rx_register,
472 .ndo_set_mac_address = eth_mac_addr,
473 .ndo_validate_addr = eth_validate_addr,
474 #ifdef CONFIG_NET_POLL_CONTROLLER
475 .ndo_poll_controller = gfar_netpoll,
479 unsigned int ftp_rqfpr[MAX_FILER_IDX + 1];
480 unsigned int ftp_rqfcr[MAX_FILER_IDX + 1];
482 void lock_rx_qs(struct gfar_private *priv)
486 for (i = 0; i < priv->num_rx_queues; i++)
487 spin_lock(&priv->rx_queue[i]->rxlock);
490 void lock_tx_qs(struct gfar_private *priv)
494 for (i = 0; i < priv->num_tx_queues; i++)
495 spin_lock(&priv->tx_queue[i]->txlock);
498 void unlock_rx_qs(struct gfar_private *priv)
502 for (i = 0; i < priv->num_rx_queues; i++)
503 spin_unlock(&priv->rx_queue[i]->rxlock);
506 void unlock_tx_qs(struct gfar_private *priv)
510 for (i = 0; i < priv->num_tx_queues; i++)
511 spin_unlock(&priv->tx_queue[i]->txlock);
514 /* Returns 1 if incoming frames use an FCB */
515 static inline int gfar_uses_fcb(struct gfar_private *priv)
517 return priv->vlgrp || priv->rx_csum_enable ||
518 (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER);
521 static void free_tx_pointers(struct gfar_private *priv)
525 for (i = 0; i < priv->num_tx_queues; i++)
526 kfree(priv->tx_queue[i]);
529 static void free_rx_pointers(struct gfar_private *priv)
533 for (i = 0; i < priv->num_rx_queues; i++)
534 kfree(priv->rx_queue[i]);
537 static void unmap_group_regs(struct gfar_private *priv)
541 for (i = 0; i < MAXGROUPS; i++)
542 if (priv->gfargrp[i].regs)
543 iounmap(priv->gfargrp[i].regs);
546 static void disable_napi(struct gfar_private *priv)
550 for (i = 0; i < priv->num_grps; i++)
551 napi_disable(&priv->gfargrp[i].napi);
554 static void enable_napi(struct gfar_private *priv)
558 for (i = 0; i < priv->num_grps; i++)
559 napi_enable(&priv->gfargrp[i].napi);
562 static int gfar_parse_group(struct device_node *np,
563 struct gfar_private *priv, const char *model)
567 priv->gfargrp[priv->num_grps].regs = of_iomap(np, 0);
568 if (!priv->gfargrp[priv->num_grps].regs)
571 priv->gfargrp[priv->num_grps].interruptTransmit =
572 irq_of_parse_and_map(np, 0);
574 /* If we aren't the FEC we have multiple interrupts */
575 if (model && strcasecmp(model, "FEC")) {
576 priv->gfargrp[priv->num_grps].interruptReceive =
577 irq_of_parse_and_map(np, 1);
578 priv->gfargrp[priv->num_grps].interruptError =
579 irq_of_parse_and_map(np,2);
580 if (priv->gfargrp[priv->num_grps].interruptTransmit < 0 ||
581 priv->gfargrp[priv->num_grps].interruptReceive < 0 ||
582 priv->gfargrp[priv->num_grps].interruptError < 0) {
587 priv->gfargrp[priv->num_grps].grp_id = priv->num_grps;
588 priv->gfargrp[priv->num_grps].priv = priv;
589 spin_lock_init(&priv->gfargrp[priv->num_grps].grplock);
590 if(priv->mode == MQ_MG_MODE) {
591 queue_mask = (u32 *)of_get_property(np,
592 "fsl,rx-bit-map", NULL);
593 priv->gfargrp[priv->num_grps].rx_bit_map =
594 queue_mask ? *queue_mask :(DEFAULT_MAPPING >> priv->num_grps);
595 queue_mask = (u32 *)of_get_property(np,
596 "fsl,tx-bit-map", NULL);
597 priv->gfargrp[priv->num_grps].tx_bit_map =
598 queue_mask ? *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
600 priv->gfargrp[priv->num_grps].rx_bit_map = 0xFF;
601 priv->gfargrp[priv->num_grps].tx_bit_map = 0xFF;
608 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
612 const void *mac_addr;
614 struct net_device *dev = NULL;
615 struct gfar_private *priv = NULL;
616 struct device_node *np = ofdev->dev.of_node;
617 struct device_node *child = NULL;
619 const u32 *stash_len;
620 const u32 *stash_idx;
621 unsigned int num_tx_qs, num_rx_qs;
622 u32 *tx_queues, *rx_queues;
624 if (!np || !of_device_is_available(np))
627 /* parse the num of tx and rx queues */
628 tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
629 num_tx_qs = tx_queues ? *tx_queues : 1;
631 if (num_tx_qs > MAX_TX_QS) {
632 printk(KERN_ERR "num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
633 num_tx_qs, MAX_TX_QS);
634 printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n");
638 rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
639 num_rx_qs = rx_queues ? *rx_queues : 1;
641 if (num_rx_qs > MAX_RX_QS) {
642 printk(KERN_ERR "num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
643 num_tx_qs, MAX_TX_QS);
644 printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n");
648 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
653 priv = netdev_priv(dev);
654 priv->node = ofdev->dev.of_node;
657 priv->num_tx_queues = num_tx_qs;
658 netif_set_real_num_rx_queues(dev, num_rx_qs);
659 priv->num_rx_queues = num_rx_qs;
660 priv->num_grps = 0x0;
662 model = of_get_property(np, "model", NULL);
664 for (i = 0; i < MAXGROUPS; i++)
665 priv->gfargrp[i].regs = NULL;
667 /* Parse and initialize group specific information */
668 if (of_device_is_compatible(np, "fsl,etsec2")) {
669 priv->mode = MQ_MG_MODE;
670 for_each_child_of_node(np, child) {
671 err = gfar_parse_group(child, priv, model);
676 priv->mode = SQ_SG_MODE;
677 err = gfar_parse_group(np, priv, model);
682 for (i = 0; i < priv->num_tx_queues; i++)
683 priv->tx_queue[i] = NULL;
684 for (i = 0; i < priv->num_rx_queues; i++)
685 priv->rx_queue[i] = NULL;
687 for (i = 0; i < priv->num_tx_queues; i++) {
688 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
690 if (!priv->tx_queue[i]) {
692 goto tx_alloc_failed;
694 priv->tx_queue[i]->tx_skbuff = NULL;
695 priv->tx_queue[i]->qindex = i;
696 priv->tx_queue[i]->dev = dev;
697 spin_lock_init(&(priv->tx_queue[i]->txlock));
700 for (i = 0; i < priv->num_rx_queues; i++) {
701 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
703 if (!priv->rx_queue[i]) {
705 goto rx_alloc_failed;
707 priv->rx_queue[i]->rx_skbuff = NULL;
708 priv->rx_queue[i]->qindex = i;
709 priv->rx_queue[i]->dev = dev;
710 spin_lock_init(&(priv->rx_queue[i]->rxlock));
714 stash = of_get_property(np, "bd-stash", NULL);
717 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
718 priv->bd_stash_en = 1;
721 stash_len = of_get_property(np, "rx-stash-len", NULL);
724 priv->rx_stash_size = *stash_len;
726 stash_idx = of_get_property(np, "rx-stash-idx", NULL);
729 priv->rx_stash_index = *stash_idx;
731 if (stash_len || stash_idx)
732 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
734 mac_addr = of_get_mac_address(np);
736 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
738 if (model && !strcasecmp(model, "TSEC"))
740 FSL_GIANFAR_DEV_HAS_GIGABIT |
741 FSL_GIANFAR_DEV_HAS_COALESCE |
742 FSL_GIANFAR_DEV_HAS_RMON |
743 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
744 if (model && !strcasecmp(model, "eTSEC"))
746 FSL_GIANFAR_DEV_HAS_GIGABIT |
747 FSL_GIANFAR_DEV_HAS_COALESCE |
748 FSL_GIANFAR_DEV_HAS_RMON |
749 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
750 FSL_GIANFAR_DEV_HAS_PADDING |
751 FSL_GIANFAR_DEV_HAS_CSUM |
752 FSL_GIANFAR_DEV_HAS_VLAN |
753 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
754 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
755 FSL_GIANFAR_DEV_HAS_TIMER;
757 ctype = of_get_property(np, "phy-connection-type", NULL);
759 /* We only care about rgmii-id. The rest are autodetected */
760 if (ctype && !strcmp(ctype, "rgmii-id"))
761 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
763 priv->interface = PHY_INTERFACE_MODE_MII;
765 if (of_get_property(np, "fsl,magic-packet", NULL))
766 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
768 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
770 /* Find the TBI PHY. If it's not there, we don't support SGMII */
771 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
776 free_rx_pointers(priv);
778 free_tx_pointers(priv);
780 unmap_group_regs(priv);
785 static int gfar_hwtstamp_ioctl(struct net_device *netdev,
786 struct ifreq *ifr, int cmd)
788 struct hwtstamp_config config;
789 struct gfar_private *priv = netdev_priv(netdev);
791 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
794 /* reserved for future extensions */
798 switch (config.tx_type) {
799 case HWTSTAMP_TX_OFF:
800 priv->hwts_tx_en = 0;
803 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
805 priv->hwts_tx_en = 1;
811 switch (config.rx_filter) {
812 case HWTSTAMP_FILTER_NONE:
813 if (priv->hwts_rx_en) {
815 priv->hwts_rx_en = 0;
816 startup_gfar(netdev);
820 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
822 if (!priv->hwts_rx_en) {
824 priv->hwts_rx_en = 1;
825 startup_gfar(netdev);
827 config.rx_filter = HWTSTAMP_FILTER_ALL;
831 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
835 /* Ioctl MII Interface */
836 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
838 struct gfar_private *priv = netdev_priv(dev);
840 if (!netif_running(dev))
843 if (cmd == SIOCSHWTSTAMP)
844 return gfar_hwtstamp_ioctl(dev, rq, cmd);
849 return phy_mii_ioctl(priv->phydev, rq, cmd);
852 static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
854 unsigned int new_bit_map = 0x0;
855 int mask = 0x1 << (max_qs - 1), i;
856 for (i = 0; i < max_qs; i++) {
858 new_bit_map = new_bit_map + (1 << i);
864 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
867 u32 rqfpr = FPR_FILER_MASK;
871 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
872 ftp_rqfpr[rqfar] = rqfpr;
873 ftp_rqfcr[rqfar] = rqfcr;
874 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
877 rqfcr = RQFCR_CMP_NOMATCH;
878 ftp_rqfpr[rqfar] = rqfpr;
879 ftp_rqfcr[rqfar] = rqfcr;
880 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
883 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
885 ftp_rqfcr[rqfar] = rqfcr;
886 ftp_rqfpr[rqfar] = rqfpr;
887 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
890 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
892 ftp_rqfcr[rqfar] = rqfcr;
893 ftp_rqfpr[rqfar] = rqfpr;
894 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
899 static void gfar_init_filer_table(struct gfar_private *priv)
902 u32 rqfar = MAX_FILER_IDX;
904 u32 rqfpr = FPR_FILER_MASK;
907 rqfcr = RQFCR_CMP_MATCH;
908 ftp_rqfcr[rqfar] = rqfcr;
909 ftp_rqfpr[rqfar] = rqfpr;
910 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
912 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
913 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
914 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
915 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
916 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
917 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
919 /* cur_filer_idx indicated the first non-masked rule */
920 priv->cur_filer_idx = rqfar;
922 /* Rest are masked rules */
923 rqfcr = RQFCR_CMP_NOMATCH;
924 for (i = 0; i < rqfar; i++) {
925 ftp_rqfcr[i] = rqfcr;
926 ftp_rqfpr[i] = rqfpr;
927 gfar_write_filer(priv, i, rqfcr, rqfpr);
931 static void gfar_detect_errata(struct gfar_private *priv)
933 struct device *dev = &priv->ofdev->dev;
934 unsigned int pvr = mfspr(SPRN_PVR);
935 unsigned int svr = mfspr(SPRN_SVR);
936 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
937 unsigned int rev = svr & 0xffff;
939 /* MPC8313 Rev 2.0 and higher; All MPC837x */
940 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
941 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
942 priv->errata |= GFAR_ERRATA_74;
944 /* MPC8313 and MPC837x all rev */
945 if ((pvr == 0x80850010 && mod == 0x80b0) ||
946 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
947 priv->errata |= GFAR_ERRATA_76;
949 /* MPC8313 and MPC837x all rev */
950 if ((pvr == 0x80850010 && mod == 0x80b0) ||
951 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
952 priv->errata |= GFAR_ERRATA_A002;
955 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
959 /* Set up the ethernet device structure, private data,
960 * and anything else we need before we start */
961 static int gfar_probe(struct platform_device *ofdev,
962 const struct of_device_id *match)
965 struct net_device *dev = NULL;
966 struct gfar_private *priv = NULL;
967 struct gfar __iomem *regs = NULL;
968 int err = 0, i, grp_idx = 0;
970 u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
974 err = gfar_of_init(ofdev, &dev);
979 priv = netdev_priv(dev);
982 priv->node = ofdev->dev.of_node;
983 SET_NETDEV_DEV(dev, &ofdev->dev);
985 spin_lock_init(&priv->bflock);
986 INIT_WORK(&priv->reset_task, gfar_reset_task);
988 dev_set_drvdata(&ofdev->dev, priv);
989 regs = priv->gfargrp[0].regs;
991 gfar_detect_errata(priv);
993 /* Stop the DMA engine now, in case it was running before */
994 /* (The firmware could have used it, and left it running). */
997 /* Reset MAC layer */
998 gfar_write(®s->maccfg1, MACCFG1_SOFT_RESET);
1000 /* We need to delay at least 3 TX clocks */
1003 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
1004 gfar_write(®s->maccfg1, tempval);
1006 /* Initialize MACCFG2. */
1007 tempval = MACCFG2_INIT_SETTINGS;
1008 if (gfar_has_errata(priv, GFAR_ERRATA_74))
1009 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1010 gfar_write(®s->maccfg2, tempval);
1012 /* Initialize ECNTRL */
1013 gfar_write(®s->ecntrl, ECNTRL_INIT_SETTINGS);
1015 /* Set the dev->base_addr to the gfar reg region */
1016 dev->base_addr = (unsigned long) regs;
1018 SET_NETDEV_DEV(dev, &ofdev->dev);
1020 /* Fill in the dev structure */
1021 dev->watchdog_timeo = TX_TIMEOUT;
1023 dev->netdev_ops = &gfar_netdev_ops;
1024 dev->ethtool_ops = &gfar_ethtool_ops;
1026 /* Register for napi ...We are registering NAPI for each grp */
1027 for (i = 0; i < priv->num_grps; i++)
1028 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, GFAR_DEV_WEIGHT);
1030 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1031 priv->rx_csum_enable = 1;
1032 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;
1034 priv->rx_csum_enable = 0;
1038 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)
1039 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1041 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1042 priv->extended_hash = 1;
1043 priv->hash_width = 9;
1045 priv->hash_regs[0] = ®s->igaddr0;
1046 priv->hash_regs[1] = ®s->igaddr1;
1047 priv->hash_regs[2] = ®s->igaddr2;
1048 priv->hash_regs[3] = ®s->igaddr3;
1049 priv->hash_regs[4] = ®s->igaddr4;
1050 priv->hash_regs[5] = ®s->igaddr5;
1051 priv->hash_regs[6] = ®s->igaddr6;
1052 priv->hash_regs[7] = ®s->igaddr7;
1053 priv->hash_regs[8] = ®s->gaddr0;
1054 priv->hash_regs[9] = ®s->gaddr1;
1055 priv->hash_regs[10] = ®s->gaddr2;
1056 priv->hash_regs[11] = ®s->gaddr3;
1057 priv->hash_regs[12] = ®s->gaddr4;
1058 priv->hash_regs[13] = ®s->gaddr5;
1059 priv->hash_regs[14] = ®s->gaddr6;
1060 priv->hash_regs[15] = ®s->gaddr7;
1063 priv->extended_hash = 0;
1064 priv->hash_width = 8;
1066 priv->hash_regs[0] = ®s->gaddr0;
1067 priv->hash_regs[1] = ®s->gaddr1;
1068 priv->hash_regs[2] = ®s->gaddr2;
1069 priv->hash_regs[3] = ®s->gaddr3;
1070 priv->hash_regs[4] = ®s->gaddr4;
1071 priv->hash_regs[5] = ®s->gaddr5;
1072 priv->hash_regs[6] = ®s->gaddr6;
1073 priv->hash_regs[7] = ®s->gaddr7;
1076 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
1077 priv->padding = DEFAULT_PADDING;
1081 if (dev->features & NETIF_F_IP_CSUM ||
1082 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1083 dev->hard_header_len += GMAC_FCB_LEN;
1085 /* Program the isrg regs only if number of grps > 1 */
1086 if (priv->num_grps > 1) {
1087 baddr = ®s->isrg0;
1088 for (i = 0; i < priv->num_grps; i++) {
1089 isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1090 isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1091 gfar_write(baddr, isrg);
1097 /* Need to reverse the bit maps as bit_map's MSB is q0
1098 * but, for_each_set_bit parses from right to left, which
1099 * basically reverses the queue numbers */
1100 for (i = 0; i< priv->num_grps; i++) {
1101 priv->gfargrp[i].tx_bit_map = reverse_bitmap(
1102 priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1103 priv->gfargrp[i].rx_bit_map = reverse_bitmap(
1104 priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
1107 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1108 * also assign queues to groups */
1109 for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1110 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
1111 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
1112 priv->num_rx_queues) {
1113 priv->gfargrp[grp_idx].num_rx_queues++;
1114 priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1115 rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1116 rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1118 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
1119 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
1120 priv->num_tx_queues) {
1121 priv->gfargrp[grp_idx].num_tx_queues++;
1122 priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1123 tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1124 tqueue = tqueue | (TQUEUE_EN0 >> i);
1126 priv->gfargrp[grp_idx].rstat = rstat;
1127 priv->gfargrp[grp_idx].tstat = tstat;
1131 gfar_write(®s->rqueue, rqueue);
1132 gfar_write(®s->tqueue, tqueue);
1134 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1136 /* Initializing some of the rx/tx queue level parameters */
1137 for (i = 0; i < priv->num_tx_queues; i++) {
1138 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1139 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1140 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1141 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1144 for (i = 0; i < priv->num_rx_queues; i++) {
1145 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1146 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1147 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1150 /* enable filer if using multiple RX queues*/
1151 if(priv->num_rx_queues > 1)
1152 priv->rx_filer_enable = 1;
1153 /* Enable most messages by default */
1154 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1156 /* Carrier starts down, phylib will bring it up */
1157 netif_carrier_off(dev);
1159 err = register_netdev(dev);
1162 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
1167 device_init_wakeup(&dev->dev,
1168 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1170 /* fill out IRQ number and name fields */
1171 len_devname = strlen(dev->name);
1172 for (i = 0; i < priv->num_grps; i++) {
1173 strncpy(&priv->gfargrp[i].int_name_tx[0], dev->name,
1175 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1176 strncpy(&priv->gfargrp[i].int_name_tx[len_devname],
1177 "_g", sizeof("_g"));
1178 priv->gfargrp[i].int_name_tx[
1179 strlen(priv->gfargrp[i].int_name_tx)] = i+48;
1180 strncpy(&priv->gfargrp[i].int_name_tx[strlen(
1181 priv->gfargrp[i].int_name_tx)],
1182 "_tx", sizeof("_tx") + 1);
1184 strncpy(&priv->gfargrp[i].int_name_rx[0], dev->name,
1186 strncpy(&priv->gfargrp[i].int_name_rx[len_devname],
1187 "_g", sizeof("_g"));
1188 priv->gfargrp[i].int_name_rx[
1189 strlen(priv->gfargrp[i].int_name_rx)] = i+48;
1190 strncpy(&priv->gfargrp[i].int_name_rx[strlen(
1191 priv->gfargrp[i].int_name_rx)],
1192 "_rx", sizeof("_rx") + 1);
1194 strncpy(&priv->gfargrp[i].int_name_er[0], dev->name,
1196 strncpy(&priv->gfargrp[i].int_name_er[len_devname],
1197 "_g", sizeof("_g"));
1198 priv->gfargrp[i].int_name_er[strlen(
1199 priv->gfargrp[i].int_name_er)] = i+48;
1200 strncpy(&priv->gfargrp[i].int_name_er[strlen(\
1201 priv->gfargrp[i].int_name_er)],
1202 "_er", sizeof("_er") + 1);
1204 priv->gfargrp[i].int_name_tx[len_devname] = '\0';
1207 /* Initialize the filer table */
1208 gfar_init_filer_table(priv);
1210 /* Create all the sysfs files */
1211 gfar_init_sysfs(dev);
1213 /* Print out the device info */
1214 printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
1216 /* Even more device info helps when determining which kernel */
1217 /* provided which set of benchmarks. */
1218 printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
1219 for (i = 0; i < priv->num_rx_queues; i++)
1220 printk(KERN_INFO "%s: RX BD ring size for Q[%d]: %d\n",
1221 dev->name, i, priv->rx_queue[i]->rx_ring_size);
1222 for(i = 0; i < priv->num_tx_queues; i++)
1223 printk(KERN_INFO "%s: TX BD ring size for Q[%d]: %d\n",
1224 dev->name, i, priv->tx_queue[i]->tx_ring_size);
1229 unmap_group_regs(priv);
1230 free_tx_pointers(priv);
1231 free_rx_pointers(priv);
1233 of_node_put(priv->phy_node);
1235 of_node_put(priv->tbi_node);
1240 static int gfar_remove(struct platform_device *ofdev)
1242 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
1245 of_node_put(priv->phy_node);
1247 of_node_put(priv->tbi_node);
1249 dev_set_drvdata(&ofdev->dev, NULL);
1251 unregister_netdev(priv->ndev);
1252 unmap_group_regs(priv);
1253 free_netdev(priv->ndev);
1260 static int gfar_suspend(struct device *dev)
1262 struct gfar_private *priv = dev_get_drvdata(dev);
1263 struct net_device *ndev = priv->ndev;
1264 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1265 unsigned long flags;
1268 int magic_packet = priv->wol_en &&
1269 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1271 netif_device_detach(ndev);
1273 if (netif_running(ndev)) {
1275 local_irq_save(flags);
1279 gfar_halt_nodisable(ndev);
1281 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1282 tempval = gfar_read(®s->maccfg1);
1284 tempval &= ~MACCFG1_TX_EN;
1287 tempval &= ~MACCFG1_RX_EN;
1289 gfar_write(®s->maccfg1, tempval);
1293 local_irq_restore(flags);
1298 /* Enable interrupt on Magic Packet */
1299 gfar_write(®s->imask, IMASK_MAG);
1301 /* Enable Magic Packet mode */
1302 tempval = gfar_read(®s->maccfg2);
1303 tempval |= MACCFG2_MPEN;
1304 gfar_write(®s->maccfg2, tempval);
1306 phy_stop(priv->phydev);
1313 static int gfar_resume(struct device *dev)
1315 struct gfar_private *priv = dev_get_drvdata(dev);
1316 struct net_device *ndev = priv->ndev;
1317 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1318 unsigned long flags;
1320 int magic_packet = priv->wol_en &&
1321 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1323 if (!netif_running(ndev)) {
1324 netif_device_attach(ndev);
1328 if (!magic_packet && priv->phydev)
1329 phy_start(priv->phydev);
1331 /* Disable Magic Packet mode, in case something
1334 local_irq_save(flags);
1338 tempval = gfar_read(®s->maccfg2);
1339 tempval &= ~MACCFG2_MPEN;
1340 gfar_write(®s->maccfg2, tempval);
1346 local_irq_restore(flags);
1348 netif_device_attach(ndev);
1355 static int gfar_restore(struct device *dev)
1357 struct gfar_private *priv = dev_get_drvdata(dev);
1358 struct net_device *ndev = priv->ndev;
1360 if (!netif_running(ndev))
1363 gfar_init_bds(ndev);
1364 init_registers(ndev);
1365 gfar_set_mac_address(ndev);
1366 gfar_init_mac(ndev);
1371 priv->oldduplex = -1;
1374 phy_start(priv->phydev);
1376 netif_device_attach(ndev);
1382 static struct dev_pm_ops gfar_pm_ops = {
1383 .suspend = gfar_suspend,
1384 .resume = gfar_resume,
1385 .freeze = gfar_suspend,
1386 .thaw = gfar_resume,
1387 .restore = gfar_restore,
1390 #define GFAR_PM_OPS (&gfar_pm_ops)
1394 #define GFAR_PM_OPS NULL
1398 /* Reads the controller's registers to determine what interface
1399 * connects it to the PHY.
1401 static phy_interface_t gfar_get_interface(struct net_device *dev)
1403 struct gfar_private *priv = netdev_priv(dev);
1404 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1407 ecntrl = gfar_read(®s->ecntrl);
1409 if (ecntrl & ECNTRL_SGMII_MODE)
1410 return PHY_INTERFACE_MODE_SGMII;
1412 if (ecntrl & ECNTRL_TBI_MODE) {
1413 if (ecntrl & ECNTRL_REDUCED_MODE)
1414 return PHY_INTERFACE_MODE_RTBI;
1416 return PHY_INTERFACE_MODE_TBI;
1419 if (ecntrl & ECNTRL_REDUCED_MODE) {
1420 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
1421 return PHY_INTERFACE_MODE_RMII;
1423 phy_interface_t interface = priv->interface;
1426 * This isn't autodetected right now, so it must
1427 * be set by the device tree or platform code.
1429 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1430 return PHY_INTERFACE_MODE_RGMII_ID;
1432 return PHY_INTERFACE_MODE_RGMII;
1436 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1437 return PHY_INTERFACE_MODE_GMII;
1439 return PHY_INTERFACE_MODE_MII;
1443 /* Initializes driver's PHY state, and attaches to the PHY.
1444 * Returns 0 on success.
1446 static int init_phy(struct net_device *dev)
1448 struct gfar_private *priv = netdev_priv(dev);
1449 uint gigabit_support =
1450 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1451 SUPPORTED_1000baseT_Full : 0;
1452 phy_interface_t interface;
1456 priv->oldduplex = -1;
1458 interface = gfar_get_interface(dev);
1460 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1463 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1465 if (!priv->phydev) {
1466 dev_err(&dev->dev, "could not attach to PHY\n");
1470 if (interface == PHY_INTERFACE_MODE_SGMII)
1471 gfar_configure_serdes(dev);
1473 /* Remove any features not supported by the controller */
1474 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1475 priv->phydev->advertising = priv->phydev->supported;
1481 * Initialize TBI PHY interface for communicating with the
1482 * SERDES lynx PHY on the chip. We communicate with this PHY
1483 * through the MDIO bus on each controller, treating it as a
1484 * "normal" PHY at the address found in the TBIPA register. We assume
1485 * that the TBIPA register is valid. Either the MDIO bus code will set
1486 * it to a value that doesn't conflict with other PHYs on the bus, or the
1487 * value doesn't matter, as there are no other PHYs on the bus.
1489 static void gfar_configure_serdes(struct net_device *dev)
1491 struct gfar_private *priv = netdev_priv(dev);
1492 struct phy_device *tbiphy;
1494 if (!priv->tbi_node) {
1495 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1496 "device tree specify a tbi-handle\n");
1500 tbiphy = of_phy_find_device(priv->tbi_node);
1502 dev_err(&dev->dev, "error: Could not get TBI device\n");
1507 * If the link is already up, we must already be ok, and don't need to
1508 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1509 * everything for us? Resetting it takes the link down and requires
1510 * several seconds for it to come back.
1512 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1515 /* Single clk mode, mii mode off(for serdes communication) */
1516 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1518 phy_write(tbiphy, MII_ADVERTISE,
1519 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1520 ADVERTISE_1000XPSE_ASYM);
1522 phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE |
1523 BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
1526 static void init_registers(struct net_device *dev)
1528 struct gfar_private *priv = netdev_priv(dev);
1529 struct gfar __iomem *regs = NULL;
1532 for (i = 0; i < priv->num_grps; i++) {
1533 regs = priv->gfargrp[i].regs;
1535 gfar_write(®s->ievent, IEVENT_INIT_CLEAR);
1537 /* Initialize IMASK */
1538 gfar_write(®s->imask, IMASK_INIT_CLEAR);
1541 regs = priv->gfargrp[0].regs;
1542 /* Init hash registers to zero */
1543 gfar_write(®s->igaddr0, 0);
1544 gfar_write(®s->igaddr1, 0);
1545 gfar_write(®s->igaddr2, 0);
1546 gfar_write(®s->igaddr3, 0);
1547 gfar_write(®s->igaddr4, 0);
1548 gfar_write(®s->igaddr5, 0);
1549 gfar_write(®s->igaddr6, 0);
1550 gfar_write(®s->igaddr7, 0);
1552 gfar_write(®s->gaddr0, 0);
1553 gfar_write(®s->gaddr1, 0);
1554 gfar_write(®s->gaddr2, 0);
1555 gfar_write(®s->gaddr3, 0);
1556 gfar_write(®s->gaddr4, 0);
1557 gfar_write(®s->gaddr5, 0);
1558 gfar_write(®s->gaddr6, 0);
1559 gfar_write(®s->gaddr7, 0);
1561 /* Zero out the rmon mib registers if it has them */
1562 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1563 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1565 /* Mask off the CAM interrupts */
1566 gfar_write(®s->rmon.cam1, 0xffffffff);
1567 gfar_write(®s->rmon.cam2, 0xffffffff);
1570 /* Initialize the max receive buffer length */
1571 gfar_write(®s->mrblr, priv->rx_buffer_size);
1573 /* Initialize the Minimum Frame Length Register */
1574 gfar_write(®s->minflr, MINFLR_INIT_SETTINGS);
1577 static int __gfar_is_rx_idle(struct gfar_private *priv)
1582 * Normaly TSEC should not hang on GRS commands, so we should
1583 * actually wait for IEVENT_GRSC flag.
1585 if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002)))
1589 * Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1590 * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1591 * and the Rx can be safely reset.
1593 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1595 if ((res & 0xffff) == (res >> 16))
1601 /* Halt the receive and transmit queues */
1602 static void gfar_halt_nodisable(struct net_device *dev)
1604 struct gfar_private *priv = netdev_priv(dev);
1605 struct gfar __iomem *regs = NULL;
1609 for (i = 0; i < priv->num_grps; i++) {
1610 regs = priv->gfargrp[i].regs;
1611 /* Mask all interrupts */
1612 gfar_write(®s->imask, IMASK_INIT_CLEAR);
1614 /* Clear all interrupts */
1615 gfar_write(®s->ievent, IEVENT_INIT_CLEAR);
1618 regs = priv->gfargrp[0].regs;
1619 /* Stop the DMA, and wait for it to stop */
1620 tempval = gfar_read(®s->dmactrl);
1621 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
1622 != (DMACTRL_GRS | DMACTRL_GTS)) {
1625 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1626 gfar_write(®s->dmactrl, tempval);
1629 ret = spin_event_timeout(((gfar_read(®s->ievent) &
1630 (IEVENT_GRSC | IEVENT_GTSC)) ==
1631 (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
1632 if (!ret && !(gfar_read(®s->ievent) & IEVENT_GRSC))
1633 ret = __gfar_is_rx_idle(priv);
1638 /* Halt the receive and transmit queues */
1639 void gfar_halt(struct net_device *dev)
1641 struct gfar_private *priv = netdev_priv(dev);
1642 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1645 gfar_halt_nodisable(dev);
1647 /* Disable Rx and Tx */
1648 tempval = gfar_read(®s->maccfg1);
1649 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1650 gfar_write(®s->maccfg1, tempval);
1653 static void free_grp_irqs(struct gfar_priv_grp *grp)
1655 free_irq(grp->interruptError, grp);
1656 free_irq(grp->interruptTransmit, grp);
1657 free_irq(grp->interruptReceive, grp);
1660 void stop_gfar(struct net_device *dev)
1662 struct gfar_private *priv = netdev_priv(dev);
1663 unsigned long flags;
1666 phy_stop(priv->phydev);
1670 local_irq_save(flags);
1678 local_irq_restore(flags);
1681 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1682 for (i = 0; i < priv->num_grps; i++)
1683 free_grp_irqs(&priv->gfargrp[i]);
1685 for (i = 0; i < priv->num_grps; i++)
1686 free_irq(priv->gfargrp[i].interruptTransmit,
1690 free_skb_resources(priv);
1693 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1695 struct txbd8 *txbdp;
1696 struct gfar_private *priv = netdev_priv(tx_queue->dev);
1699 txbdp = tx_queue->tx_bd_base;
1701 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1702 if (!tx_queue->tx_skbuff[i])
1705 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
1706 txbdp->length, DMA_TO_DEVICE);
1708 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1711 dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
1712 txbdp->length, DMA_TO_DEVICE);
1715 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1716 tx_queue->tx_skbuff[i] = NULL;
1718 kfree(tx_queue->tx_skbuff);
1721 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1723 struct rxbd8 *rxbdp;
1724 struct gfar_private *priv = netdev_priv(rx_queue->dev);
1727 rxbdp = rx_queue->rx_bd_base;
1729 for (i = 0; i < rx_queue->rx_ring_size; i++) {
1730 if (rx_queue->rx_skbuff[i]) {
1731 dma_unmap_single(&priv->ofdev->dev,
1732 rxbdp->bufPtr, priv->rx_buffer_size,
1734 dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1735 rx_queue->rx_skbuff[i] = NULL;
1741 kfree(rx_queue->rx_skbuff);
1744 /* If there are any tx skbs or rx skbs still around, free them.
1745 * Then free tx_skbuff and rx_skbuff */
1746 static void free_skb_resources(struct gfar_private *priv)
1748 struct gfar_priv_tx_q *tx_queue = NULL;
1749 struct gfar_priv_rx_q *rx_queue = NULL;
1752 /* Go through all the buffer descriptors and free their data buffers */
1753 for (i = 0; i < priv->num_tx_queues; i++) {
1754 tx_queue = priv->tx_queue[i];
1755 if(tx_queue->tx_skbuff)
1756 free_skb_tx_queue(tx_queue);
1759 for (i = 0; i < priv->num_rx_queues; i++) {
1760 rx_queue = priv->rx_queue[i];
1761 if(rx_queue->rx_skbuff)
1762 free_skb_rx_queue(rx_queue);
1765 dma_free_coherent(&priv->ofdev->dev,
1766 sizeof(struct txbd8) * priv->total_tx_ring_size +
1767 sizeof(struct rxbd8) * priv->total_rx_ring_size,
1768 priv->tx_queue[0]->tx_bd_base,
1769 priv->tx_queue[0]->tx_bd_dma_base);
1770 skb_queue_purge(&priv->rx_recycle);
1773 void gfar_start(struct net_device *dev)
1775 struct gfar_private *priv = netdev_priv(dev);
1776 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1780 /* Enable Rx and Tx in MACCFG1 */
1781 tempval = gfar_read(®s->maccfg1);
1782 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1783 gfar_write(®s->maccfg1, tempval);
1785 /* Initialize DMACTRL to have WWR and WOP */
1786 tempval = gfar_read(®s->dmactrl);
1787 tempval |= DMACTRL_INIT_SETTINGS;
1788 gfar_write(®s->dmactrl, tempval);
1790 /* Make sure we aren't stopped */
1791 tempval = gfar_read(®s->dmactrl);
1792 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1793 gfar_write(®s->dmactrl, tempval);
1795 for (i = 0; i < priv->num_grps; i++) {
1796 regs = priv->gfargrp[i].regs;
1797 /* Clear THLT/RHLT, so that the DMA starts polling now */
1798 gfar_write(®s->tstat, priv->gfargrp[i].tstat);
1799 gfar_write(®s->rstat, priv->gfargrp[i].rstat);
1800 /* Unmask the interrupts we look for */
1801 gfar_write(®s->imask, IMASK_DEFAULT);
1804 dev->trans_start = jiffies; /* prevent tx timeout */
1807 void gfar_configure_coalescing(struct gfar_private *priv,
1808 unsigned long tx_mask, unsigned long rx_mask)
1810 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1814 /* Backward compatible case ---- even if we enable
1815 * multiple queues, there's only single reg to program
1817 gfar_write(®s->txic, 0);
1818 if(likely(priv->tx_queue[0]->txcoalescing))
1819 gfar_write(®s->txic, priv->tx_queue[0]->txic);
1821 gfar_write(®s->rxic, 0);
1822 if(unlikely(priv->rx_queue[0]->rxcoalescing))
1823 gfar_write(®s->rxic, priv->rx_queue[0]->rxic);
1825 if (priv->mode == MQ_MG_MODE) {
1826 baddr = ®s->txic0;
1827 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
1828 if (likely(priv->tx_queue[i]->txcoalescing)) {
1829 gfar_write(baddr + i, 0);
1830 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1834 baddr = ®s->rxic0;
1835 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
1836 if (likely(priv->rx_queue[i]->rxcoalescing)) {
1837 gfar_write(baddr + i, 0);
1838 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1844 static int register_grp_irqs(struct gfar_priv_grp *grp)
1846 struct gfar_private *priv = grp->priv;
1847 struct net_device *dev = priv->ndev;
1850 /* If the device has multiple interrupts, register for
1851 * them. Otherwise, only register for the one */
1852 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1853 /* Install our interrupt handlers for Error,
1854 * Transmit, and Receive */
1855 if ((err = request_irq(grp->interruptError, gfar_error, 0,
1856 grp->int_name_er,grp)) < 0) {
1857 if (netif_msg_intr(priv))
1858 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1859 dev->name, grp->interruptError);
1864 if ((err = request_irq(grp->interruptTransmit, gfar_transmit,
1865 0, grp->int_name_tx, grp)) < 0) {
1866 if (netif_msg_intr(priv))
1867 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1868 dev->name, grp->interruptTransmit);
1872 if ((err = request_irq(grp->interruptReceive, gfar_receive, 0,
1873 grp->int_name_rx, grp)) < 0) {
1874 if (netif_msg_intr(priv))
1875 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1876 dev->name, grp->interruptReceive);
1880 if ((err = request_irq(grp->interruptTransmit, gfar_interrupt, 0,
1881 grp->int_name_tx, grp)) < 0) {
1882 if (netif_msg_intr(priv))
1883 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1884 dev->name, grp->interruptTransmit);
1892 free_irq(grp->interruptTransmit, grp);
1894 free_irq(grp->interruptError, grp);
1900 /* Bring the controller up and running */
1901 int startup_gfar(struct net_device *ndev)
1903 struct gfar_private *priv = netdev_priv(ndev);
1904 struct gfar __iomem *regs = NULL;
1907 for (i = 0; i < priv->num_grps; i++) {
1908 regs= priv->gfargrp[i].regs;
1909 gfar_write(®s->imask, IMASK_INIT_CLEAR);
1912 regs= priv->gfargrp[0].regs;
1913 err = gfar_alloc_skb_resources(ndev);
1917 gfar_init_mac(ndev);
1919 for (i = 0; i < priv->num_grps; i++) {
1920 err = register_grp_irqs(&priv->gfargrp[i]);
1922 for (j = 0; j < i; j++)
1923 free_grp_irqs(&priv->gfargrp[j]);
1928 /* Start the controller */
1931 phy_start(priv->phydev);
1933 gfar_configure_coalescing(priv, 0xFF, 0xFF);
1938 free_skb_resources(priv);
1942 /* Called when something needs to use the ethernet device */
1943 /* Returns 0 for success. */
1944 static int gfar_enet_open(struct net_device *dev)
1946 struct gfar_private *priv = netdev_priv(dev);
1951 skb_queue_head_init(&priv->rx_recycle);
1953 /* Initialize a bunch of registers */
1954 init_registers(dev);
1956 gfar_set_mac_address(dev);
1958 err = init_phy(dev);
1965 err = startup_gfar(dev);
1971 netif_tx_start_all_queues(dev);
1973 device_set_wakeup_enable(&dev->dev, priv->wol_en);
1978 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1980 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1982 memset(fcb, 0, GMAC_FCB_LEN);
1987 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1991 /* If we're here, it's a IP packet with a TCP or UDP
1992 * payload. We set it to checksum, using a pseudo-header
1995 flags = TXFCB_DEFAULT;
1997 /* Tell the controller what the protocol is */
1998 /* And provide the already calculated phcs */
1999 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
2001 fcb->phcs = udp_hdr(skb)->check;
2003 fcb->phcs = tcp_hdr(skb)->check;
2005 /* l3os is the distance between the start of the
2006 * frame (skb->data) and the start of the IP hdr.
2007 * l4os is the distance between the start of the
2008 * l3 hdr and the l4 hdr */
2009 fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
2010 fcb->l4os = skb_network_header_len(skb);
2015 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2017 fcb->flags |= TXFCB_VLN;
2018 fcb->vlctl = vlan_tx_tag_get(skb);
2021 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2022 struct txbd8 *base, int ring_size)
2024 struct txbd8 *new_bd = bdp + stride;
2026 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2029 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2032 return skip_txbd(bdp, 1, base, ring_size);
2035 /* This is called by the kernel when a frame is ready for transmission. */
2036 /* It is pointed to by the dev->hard_start_xmit function pointer */
2037 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2039 struct gfar_private *priv = netdev_priv(dev);
2040 struct gfar_priv_tx_q *tx_queue = NULL;
2041 struct netdev_queue *txq;
2042 struct gfar __iomem *regs = NULL;
2043 struct txfcb *fcb = NULL;
2044 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2046 int i, rq = 0, do_tstamp = 0;
2048 unsigned long flags;
2049 unsigned int nr_frags, nr_txbds, length;
2052 * TOE=1 frames larger than 2500 bytes may see excess delays
2053 * before start of transmission.
2055 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) &&
2056 skb->ip_summed == CHECKSUM_PARTIAL &&
2060 ret = skb_checksum_help(skb);
2065 rq = skb->queue_mapping;
2066 tx_queue = priv->tx_queue[rq];
2067 txq = netdev_get_tx_queue(dev, rq);
2068 base = tx_queue->tx_bd_base;
2069 regs = tx_queue->grp->regs;
2071 /* check if time stamp should be generated */
2072 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
2076 /* make space for additional header when fcb is needed */
2077 if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
2078 vlan_tx_tag_present(skb) ||
2079 unlikely(do_tstamp)) &&
2080 (skb_headroom(skb) < GMAC_FCB_LEN)) {
2081 struct sk_buff *skb_new;
2083 skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN);
2085 dev->stats.tx_errors++;
2087 return NETDEV_TX_OK;
2093 /* total number of fragments in the SKB */
2094 nr_frags = skb_shinfo(skb)->nr_frags;
2096 /* calculate the required number of TxBDs for this skb */
2097 if (unlikely(do_tstamp))
2098 nr_txbds = nr_frags + 2;
2100 nr_txbds = nr_frags + 1;
2102 /* check if there is space to queue this packet */
2103 if (nr_txbds > tx_queue->num_txbdfree) {
2104 /* no space, stop the queue */
2105 netif_tx_stop_queue(txq);
2106 dev->stats.tx_fifo_errors++;
2107 return NETDEV_TX_BUSY;
2110 /* Update transmit stats */
2111 txq->tx_bytes += skb->len;
2114 txbdp = txbdp_start = tx_queue->cur_tx;
2115 lstatus = txbdp->lstatus;
2117 /* Time stamp insertion requires one additional TxBD */
2118 if (unlikely(do_tstamp))
2119 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2120 tx_queue->tx_ring_size);
2122 if (nr_frags == 0) {
2123 if (unlikely(do_tstamp))
2124 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2127 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2129 /* Place the fragment addresses and lengths into the TxBDs */
2130 for (i = 0; i < nr_frags; i++) {
2131 /* Point at the next BD, wrapping as needed */
2132 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2134 length = skb_shinfo(skb)->frags[i].size;
2136 lstatus = txbdp->lstatus | length |
2137 BD_LFLAG(TXBD_READY);
2139 /* Handle the last BD specially */
2140 if (i == nr_frags - 1)
2141 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2143 bufaddr = dma_map_page(&priv->ofdev->dev,
2144 skb_shinfo(skb)->frags[i].page,
2145 skb_shinfo(skb)->frags[i].page_offset,
2149 /* set the TxBD length and buffer pointer */
2150 txbdp->bufPtr = bufaddr;
2151 txbdp->lstatus = lstatus;
2154 lstatus = txbdp_start->lstatus;
2157 /* Set up checksumming */
2158 if (CHECKSUM_PARTIAL == skb->ip_summed) {
2159 fcb = gfar_add_fcb(skb);
2160 lstatus |= BD_LFLAG(TXBD_TOE);
2161 gfar_tx_checksum(skb, fcb);
2164 if (vlan_tx_tag_present(skb)) {
2165 if (unlikely(NULL == fcb)) {
2166 fcb = gfar_add_fcb(skb);
2167 lstatus |= BD_LFLAG(TXBD_TOE);
2170 gfar_tx_vlan(skb, fcb);
2173 /* Setup tx hardware time stamping if requested */
2174 if (unlikely(do_tstamp)) {
2175 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2177 fcb = gfar_add_fcb(skb);
2179 lstatus |= BD_LFLAG(TXBD_TOE);
2182 txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
2183 skb_headlen(skb), DMA_TO_DEVICE);
2186 * If time stamping is requested one additional TxBD must be set up. The
2187 * first TxBD points to the FCB and must have a data length of
2188 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2189 * the full frame length.
2191 if (unlikely(do_tstamp)) {
2192 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + GMAC_FCB_LEN;
2193 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2194 (skb_headlen(skb) - GMAC_FCB_LEN);
2195 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2197 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2201 * We can work in parallel with gfar_clean_tx_ring(), except
2202 * when modifying num_txbdfree. Note that we didn't grab the lock
2203 * when we were reading the num_txbdfree and checking for available
2204 * space, that's because outside of this function it can only grow,
2205 * and once we've got needed space, it cannot suddenly disappear.
2207 * The lock also protects us from gfar_error(), which can modify
2208 * regs->tstat and thus retrigger the transfers, which is why we
2209 * also must grab the lock before setting ready bit for the first
2210 * to be transmitted BD.
2212 spin_lock_irqsave(&tx_queue->txlock, flags);
2215 * The powerpc-specific eieio() is used, as wmb() has too strong
2216 * semantics (it requires synchronization between cacheable and
2217 * uncacheable mappings, which eieio doesn't provide and which we
2218 * don't need), thus requiring a more expensive sync instruction. At
2219 * some point, the set of architecture-independent barrier functions
2220 * should be expanded to include weaker barriers.
2224 txbdp_start->lstatus = lstatus;
2226 eieio(); /* force lstatus write before tx_skbuff */
2228 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2230 /* Update the current skb pointer to the next entry we will use
2231 * (wrapping if necessary) */
2232 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2233 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2235 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2237 /* reduce TxBD free count */
2238 tx_queue->num_txbdfree -= (nr_txbds);
2240 /* If the next BD still needs to be cleaned up, then the bds
2241 are full. We need to tell the kernel to stop sending us stuff. */
2242 if (!tx_queue->num_txbdfree) {
2243 netif_tx_stop_queue(txq);
2245 dev->stats.tx_fifo_errors++;
2248 /* Tell the DMA to go go go */
2249 gfar_write(®s->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2252 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2254 return NETDEV_TX_OK;
2257 /* Stops the kernel queue, and halts the controller */
2258 static int gfar_close(struct net_device *dev)
2260 struct gfar_private *priv = netdev_priv(dev);
2264 cancel_work_sync(&priv->reset_task);
2267 /* Disconnect from the PHY */
2268 phy_disconnect(priv->phydev);
2269 priv->phydev = NULL;
2271 netif_tx_stop_all_queues(dev);
2276 /* Changes the mac address if the controller is not running. */
2277 static int gfar_set_mac_address(struct net_device *dev)
2279 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2285 /* Enables and disables VLAN insertion/extraction */
2286 static void gfar_vlan_rx_register(struct net_device *dev,
2287 struct vlan_group *grp)
2289 struct gfar_private *priv = netdev_priv(dev);
2290 struct gfar __iomem *regs = NULL;
2291 unsigned long flags;
2294 regs = priv->gfargrp[0].regs;
2295 local_irq_save(flags);
2301 /* Enable VLAN tag insertion */
2302 tempval = gfar_read(®s->tctrl);
2303 tempval |= TCTRL_VLINS;
2305 gfar_write(®s->tctrl, tempval);
2307 /* Enable VLAN tag extraction */
2308 tempval = gfar_read(®s->rctrl);
2309 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
2310 gfar_write(®s->rctrl, tempval);
2312 /* Disable VLAN tag insertion */
2313 tempval = gfar_read(®s->tctrl);
2314 tempval &= ~TCTRL_VLINS;
2315 gfar_write(®s->tctrl, tempval);
2317 /* Disable VLAN tag extraction */
2318 tempval = gfar_read(®s->rctrl);
2319 tempval &= ~RCTRL_VLEX;
2320 /* If parse is no longer required, then disable parser */
2321 if (tempval & RCTRL_REQ_PARSER)
2322 tempval |= RCTRL_PRSDEP_INIT;
2324 tempval &= ~RCTRL_PRSDEP_INIT;
2325 gfar_write(®s->rctrl, tempval);
2328 gfar_change_mtu(dev, dev->mtu);
2331 local_irq_restore(flags);
2334 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2336 int tempsize, tempval;
2337 struct gfar_private *priv = netdev_priv(dev);
2338 struct gfar __iomem *regs = priv->gfargrp[0].regs;
2339 int oldsize = priv->rx_buffer_size;
2340 int frame_size = new_mtu + ETH_HLEN;
2343 frame_size += VLAN_HLEN;
2345 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2346 if (netif_msg_drv(priv))
2347 printk(KERN_ERR "%s: Invalid MTU setting\n",
2352 if (gfar_uses_fcb(priv))
2353 frame_size += GMAC_FCB_LEN;
2355 frame_size += priv->padding;
2358 (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2359 INCREMENTAL_BUFFER_SIZE;
2361 /* Only stop and start the controller if it isn't already
2362 * stopped, and we changed something */
2363 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2366 priv->rx_buffer_size = tempsize;
2370 gfar_write(®s->mrblr, priv->rx_buffer_size);
2371 gfar_write(®s->maxfrm, priv->rx_buffer_size);
2373 /* If the mtu is larger than the max size for standard
2374 * ethernet frames (ie, a jumbo frame), then set maccfg2
2375 * to allow huge frames, and to check the length */
2376 tempval = gfar_read(®s->maccfg2);
2378 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
2379 gfar_has_errata(priv, GFAR_ERRATA_74))
2380 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2382 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2384 gfar_write(®s->maccfg2, tempval);
2386 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2392 /* gfar_reset_task gets scheduled when a packet has not been
2393 * transmitted after a set amount of time.
2394 * For now, assume that clearing out all the structures, and
2395 * starting over will fix the problem.
2397 static void gfar_reset_task(struct work_struct *work)
2399 struct gfar_private *priv = container_of(work, struct gfar_private,
2401 struct net_device *dev = priv->ndev;
2403 if (dev->flags & IFF_UP) {
2404 netif_tx_stop_all_queues(dev);
2407 netif_tx_start_all_queues(dev);
2410 netif_tx_schedule_all(dev);
2413 static void gfar_timeout(struct net_device *dev)
2415 struct gfar_private *priv = netdev_priv(dev);
2417 dev->stats.tx_errors++;
2418 schedule_work(&priv->reset_task);
2421 static void gfar_align_skb(struct sk_buff *skb)
2423 /* We need the data buffer to be aligned properly. We will reserve
2424 * as many bytes as needed to align the data properly
2426 skb_reserve(skb, RXBUF_ALIGNMENT -
2427 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
2430 /* Interrupt Handler for Transmit complete */
2431 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2433 struct net_device *dev = tx_queue->dev;
2434 struct gfar_private *priv = netdev_priv(dev);
2435 struct gfar_priv_rx_q *rx_queue = NULL;
2436 struct txbd8 *bdp, *next = NULL;
2437 struct txbd8 *lbdp = NULL;
2438 struct txbd8 *base = tx_queue->tx_bd_base;
2439 struct sk_buff *skb;
2441 int tx_ring_size = tx_queue->tx_ring_size;
2442 int frags = 0, nr_txbds = 0;
2448 rx_queue = priv->rx_queue[tx_queue->qindex];
2449 bdp = tx_queue->dirty_tx;
2450 skb_dirtytx = tx_queue->skb_dirtytx;
2452 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2453 unsigned long flags;
2455 frags = skb_shinfo(skb)->nr_frags;
2458 * When time stamping, one additional TxBD must be freed.
2459 * Also, we need to dma_unmap_single() the TxPAL.
2461 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2462 nr_txbds = frags + 2;
2464 nr_txbds = frags + 1;
2466 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2468 lstatus = lbdp->lstatus;
2470 /* Only clean completed frames */
2471 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2472 (lstatus & BD_LENGTH_MASK))
2475 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2476 next = next_txbd(bdp, base, tx_ring_size);
2477 buflen = next->length + GMAC_FCB_LEN;
2479 buflen = bdp->length;
2481 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2482 buflen, DMA_TO_DEVICE);
2484 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2485 struct skb_shared_hwtstamps shhwtstamps;
2486 u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2487 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2488 shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2489 skb_tstamp_tx(skb, &shhwtstamps);
2490 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2494 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2495 bdp = next_txbd(bdp, base, tx_ring_size);
2497 for (i = 0; i < frags; i++) {
2498 dma_unmap_page(&priv->ofdev->dev,
2502 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2503 bdp = next_txbd(bdp, base, tx_ring_size);
2507 * If there's room in the queue (limit it to rx_buffer_size)
2508 * we add this skb back into the pool, if it's the right size
2510 if (skb_queue_len(&priv->rx_recycle) < rx_queue->rx_ring_size &&
2511 skb_recycle_check(skb, priv->rx_buffer_size +
2513 gfar_align_skb(skb);
2514 skb_queue_head(&priv->rx_recycle, skb);
2516 dev_kfree_skb_any(skb);
2518 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2520 skb_dirtytx = (skb_dirtytx + 1) &
2521 TX_RING_MOD_MASK(tx_ring_size);
2524 spin_lock_irqsave(&tx_queue->txlock, flags);
2525 tx_queue->num_txbdfree += nr_txbds;
2526 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2529 /* If we freed a buffer, we can restart transmission, if necessary */
2530 if (__netif_subqueue_stopped(dev, tx_queue->qindex) && tx_queue->num_txbdfree)
2531 netif_wake_subqueue(dev, tx_queue->qindex);
2533 /* Update dirty indicators */
2534 tx_queue->skb_dirtytx = skb_dirtytx;
2535 tx_queue->dirty_tx = bdp;
2540 static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
2542 unsigned long flags;
2544 spin_lock_irqsave(&gfargrp->grplock, flags);
2545 if (napi_schedule_prep(&gfargrp->napi)) {
2546 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
2547 __napi_schedule(&gfargrp->napi);
2550 * Clear IEVENT, so interrupts aren't called again
2551 * because of the packets that have already arrived.
2553 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2555 spin_unlock_irqrestore(&gfargrp->grplock, flags);
2559 /* Interrupt Handler for Transmit complete */
2560 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2562 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2566 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
2567 struct sk_buff *skb)
2569 struct net_device *dev = rx_queue->dev;
2570 struct gfar_private *priv = netdev_priv(dev);
2573 buf = dma_map_single(&priv->ofdev->dev, skb->data,
2574 priv->rx_buffer_size, DMA_FROM_DEVICE);
2575 gfar_init_rxbdp(rx_queue, bdp, buf);
2578 static struct sk_buff * gfar_alloc_skb(struct net_device *dev)
2580 struct gfar_private *priv = netdev_priv(dev);
2581 struct sk_buff *skb = NULL;
2583 skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
2587 gfar_align_skb(skb);
2592 struct sk_buff * gfar_new_skb(struct net_device *dev)
2594 struct gfar_private *priv = netdev_priv(dev);
2595 struct sk_buff *skb = NULL;
2597 skb = skb_dequeue(&priv->rx_recycle);
2599 skb = gfar_alloc_skb(dev);
2604 static inline void count_errors(unsigned short status, struct net_device *dev)
2606 struct gfar_private *priv = netdev_priv(dev);
2607 struct net_device_stats *stats = &dev->stats;
2608 struct gfar_extra_stats *estats = &priv->extra_stats;
2610 /* If the packet was truncated, none of the other errors
2612 if (status & RXBD_TRUNCATED) {
2613 stats->rx_length_errors++;
2619 /* Count the errors, if there were any */
2620 if (status & (RXBD_LARGE | RXBD_SHORT)) {
2621 stats->rx_length_errors++;
2623 if (status & RXBD_LARGE)
2628 if (status & RXBD_NONOCTET) {
2629 stats->rx_frame_errors++;
2630 estats->rx_nonoctet++;
2632 if (status & RXBD_CRCERR) {
2633 estats->rx_crcerr++;
2634 stats->rx_crc_errors++;
2636 if (status & RXBD_OVERRUN) {
2637 estats->rx_overrun++;
2638 stats->rx_crc_errors++;
2642 irqreturn_t gfar_receive(int irq, void *grp_id)
2644 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2648 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2650 /* If valid headers were found, and valid sums
2651 * were verified, then we tell the kernel that no
2652 * checksumming is necessary. Otherwise, it is */
2653 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
2654 skb->ip_summed = CHECKSUM_UNNECESSARY;
2656 skb_checksum_none_assert(skb);
2660 /* gfar_process_frame() -- handle one incoming packet if skb
2662 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2665 struct gfar_private *priv = netdev_priv(dev);
2666 struct rxfcb *fcb = NULL;
2670 /* fcb is at the beginning if exists */
2671 fcb = (struct rxfcb *)skb->data;
2673 /* Remove the FCB from the skb */
2674 /* Remove the padded bytes, if there are any */
2676 skb_record_rx_queue(skb, fcb->rq);
2677 skb_pull(skb, amount_pull);
2680 /* Get receive timestamp from the skb */
2681 if (priv->hwts_rx_en) {
2682 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2683 u64 *ns = (u64 *) skb->data;
2684 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2685 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2689 skb_pull(skb, priv->padding);
2691 if (priv->rx_csum_enable)
2692 gfar_rx_checksum(skb, fcb);
2694 /* Tell the skb what kind of packet this is */
2695 skb->protocol = eth_type_trans(skb, dev);
2697 /* Send the packet up the stack */
2698 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
2699 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
2701 ret = netif_receive_skb(skb);
2703 if (NET_RX_DROP == ret)
2704 priv->extra_stats.kernel_dropped++;
2709 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2710 * until the budget/quota has been reached. Returns the number
2713 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2715 struct net_device *dev = rx_queue->dev;
2716 struct rxbd8 *bdp, *base;
2717 struct sk_buff *skb;
2721 struct gfar_private *priv = netdev_priv(dev);
2723 /* Get the first full descriptor */
2724 bdp = rx_queue->cur_rx;
2725 base = rx_queue->rx_bd_base;
2727 amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0);
2729 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
2730 struct sk_buff *newskb;
2733 /* Add another skb for the future */
2734 newskb = gfar_new_skb(dev);
2736 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
2738 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2739 priv->rx_buffer_size, DMA_FROM_DEVICE);
2741 if (unlikely(!(bdp->status & RXBD_ERR) &&
2742 bdp->length > priv->rx_buffer_size))
2743 bdp->status = RXBD_LARGE;
2745 /* We drop the frame if we failed to allocate a new buffer */
2746 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2747 bdp->status & RXBD_ERR)) {
2748 count_errors(bdp->status, dev);
2750 if (unlikely(!newskb))
2753 skb_queue_head(&priv->rx_recycle, skb);
2755 /* Increment the number of packets */
2756 rx_queue->stats.rx_packets++;
2760 pkt_len = bdp->length - ETH_FCS_LEN;
2761 /* Remove the FCS from the packet length */
2762 skb_put(skb, pkt_len);
2763 rx_queue->stats.rx_bytes += pkt_len;
2764 skb_record_rx_queue(skb, rx_queue->qindex);
2765 gfar_process_frame(dev, skb, amount_pull);
2768 if (netif_msg_rx_err(priv))
2770 "%s: Missing skb!\n", dev->name);
2771 rx_queue->stats.rx_dropped++;
2772 priv->extra_stats.rx_skbmissing++;
2777 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
2779 /* Setup the new bdp */
2780 gfar_new_rxbdp(rx_queue, bdp, newskb);
2782 /* Update to the next pointer */
2783 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2785 /* update to point at the next skb */
2786 rx_queue->skb_currx =
2787 (rx_queue->skb_currx + 1) &
2788 RX_RING_MOD_MASK(rx_queue->rx_ring_size);
2791 /* Update the current rxbd pointer to be the next one */
2792 rx_queue->cur_rx = bdp;
2797 static int gfar_poll(struct napi_struct *napi, int budget)
2799 struct gfar_priv_grp *gfargrp = container_of(napi,
2800 struct gfar_priv_grp, napi);
2801 struct gfar_private *priv = gfargrp->priv;
2802 struct gfar __iomem *regs = gfargrp->regs;
2803 struct gfar_priv_tx_q *tx_queue = NULL;
2804 struct gfar_priv_rx_q *rx_queue = NULL;
2805 int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;
2806 int tx_cleaned = 0, i, left_over_budget = budget;
2807 unsigned long serviced_queues = 0;
2810 num_queues = gfargrp->num_rx_queues;
2811 budget_per_queue = budget/num_queues;
2813 /* Clear IEVENT, so interrupts aren't called again
2814 * because of the packets that have already arrived */
2815 gfar_write(®s->ievent, IEVENT_RTX_MASK);
2817 while (num_queues && left_over_budget) {
2819 budget_per_queue = left_over_budget/num_queues;
2820 left_over_budget = 0;
2822 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2823 if (test_bit(i, &serviced_queues))
2825 rx_queue = priv->rx_queue[i];
2826 tx_queue = priv->tx_queue[rx_queue->qindex];
2828 tx_cleaned += gfar_clean_tx_ring(tx_queue);
2829 rx_cleaned_per_queue = gfar_clean_rx_ring(rx_queue,
2831 rx_cleaned += rx_cleaned_per_queue;
2832 if(rx_cleaned_per_queue < budget_per_queue) {
2833 left_over_budget = left_over_budget +
2834 (budget_per_queue - rx_cleaned_per_queue);
2835 set_bit(i, &serviced_queues);
2844 if (rx_cleaned < budget) {
2845 napi_complete(napi);
2847 /* Clear the halt bit in RSTAT */
2848 gfar_write(®s->rstat, gfargrp->rstat);
2850 gfar_write(®s->imask, IMASK_DEFAULT);
2852 /* If we are coalescing interrupts, update the timer */
2853 /* Otherwise, clear it */
2854 gfar_configure_coalescing(priv,
2855 gfargrp->rx_bit_map, gfargrp->tx_bit_map);
2861 #ifdef CONFIG_NET_POLL_CONTROLLER
2863 * Polling 'interrupt' - used by things like netconsole to send skbs
2864 * without having to re-enable interrupts. It's not called while
2865 * the interrupt routine is executing.
2867 static void gfar_netpoll(struct net_device *dev)
2869 struct gfar_private *priv = netdev_priv(dev);
2872 /* If the device has multiple interrupts, run tx/rx */
2873 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2874 for (i = 0; i < priv->num_grps; i++) {
2875 disable_irq(priv->gfargrp[i].interruptTransmit);
2876 disable_irq(priv->gfargrp[i].interruptReceive);
2877 disable_irq(priv->gfargrp[i].interruptError);
2878 gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2880 enable_irq(priv->gfargrp[i].interruptError);
2881 enable_irq(priv->gfargrp[i].interruptReceive);
2882 enable_irq(priv->gfargrp[i].interruptTransmit);
2885 for (i = 0; i < priv->num_grps; i++) {
2886 disable_irq(priv->gfargrp[i].interruptTransmit);
2887 gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2889 enable_irq(priv->gfargrp[i].interruptTransmit);
2895 /* The interrupt handler for devices with one interrupt */
2896 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
2898 struct gfar_priv_grp *gfargrp = grp_id;
2900 /* Save ievent for future reference */
2901 u32 events = gfar_read(&gfargrp->regs->ievent);
2903 /* Check for reception */
2904 if (events & IEVENT_RX_MASK)
2905 gfar_receive(irq, grp_id);
2907 /* Check for transmit completion */
2908 if (events & IEVENT_TX_MASK)
2909 gfar_transmit(irq, grp_id);
2911 /* Check for errors */
2912 if (events & IEVENT_ERR_MASK)
2913 gfar_error(irq, grp_id);
2918 /* Called every time the controller might need to be made
2919 * aware of new link state. The PHY code conveys this
2920 * information through variables in the phydev structure, and this
2921 * function converts those variables into the appropriate
2922 * register values, and can bring down the device if needed.
2924 static void adjust_link(struct net_device *dev)
2926 struct gfar_private *priv = netdev_priv(dev);
2927 struct gfar __iomem *regs = priv->gfargrp[0].regs;
2928 unsigned long flags;
2929 struct phy_device *phydev = priv->phydev;
2932 local_irq_save(flags);
2936 u32 tempval = gfar_read(®s->maccfg2);
2937 u32 ecntrl = gfar_read(®s->ecntrl);
2939 /* Now we make sure that we can be in full duplex mode.
2940 * If not, we operate in half-duplex mode. */
2941 if (phydev->duplex != priv->oldduplex) {
2943 if (!(phydev->duplex))
2944 tempval &= ~(MACCFG2_FULL_DUPLEX);
2946 tempval |= MACCFG2_FULL_DUPLEX;
2948 priv->oldduplex = phydev->duplex;
2951 if (phydev->speed != priv->oldspeed) {
2953 switch (phydev->speed) {
2956 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2958 ecntrl &= ~(ECNTRL_R100);
2963 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
2965 /* Reduced mode distinguishes
2966 * between 10 and 100 */
2967 if (phydev->speed == SPEED_100)
2968 ecntrl |= ECNTRL_R100;
2970 ecntrl &= ~(ECNTRL_R100);
2973 if (netif_msg_link(priv))
2975 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
2976 dev->name, phydev->speed);
2980 priv->oldspeed = phydev->speed;
2983 gfar_write(®s->maccfg2, tempval);
2984 gfar_write(®s->ecntrl, ecntrl);
2986 if (!priv->oldlink) {
2990 } else if (priv->oldlink) {
2994 priv->oldduplex = -1;
2997 if (new_state && netif_msg_link(priv))
2998 phy_print_status(phydev);
3000 local_irq_restore(flags);
3003 /* Update the hash table based on the current list of multicast
3004 * addresses we subscribe to. Also, change the promiscuity of
3005 * the device based on the flags (this function is called
3006 * whenever dev->flags is changed */
3007 static void gfar_set_multi(struct net_device *dev)
3009 struct netdev_hw_addr *ha;
3010 struct gfar_private *priv = netdev_priv(dev);
3011 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3014 if (dev->flags & IFF_PROMISC) {
3015 /* Set RCTRL to PROM */
3016 tempval = gfar_read(®s->rctrl);
3017 tempval |= RCTRL_PROM;
3018 gfar_write(®s->rctrl, tempval);
3020 /* Set RCTRL to not PROM */
3021 tempval = gfar_read(®s->rctrl);
3022 tempval &= ~(RCTRL_PROM);
3023 gfar_write(®s->rctrl, tempval);
3026 if (dev->flags & IFF_ALLMULTI) {
3027 /* Set the hash to rx all multicast frames */
3028 gfar_write(®s->igaddr0, 0xffffffff);
3029 gfar_write(®s->igaddr1, 0xffffffff);
3030 gfar_write(®s->igaddr2, 0xffffffff);
3031 gfar_write(®s->igaddr3, 0xffffffff);
3032 gfar_write(®s->igaddr4, 0xffffffff);
3033 gfar_write(®s->igaddr5, 0xffffffff);
3034 gfar_write(®s->igaddr6, 0xffffffff);
3035 gfar_write(®s->igaddr7, 0xffffffff);
3036 gfar_write(®s->gaddr0, 0xffffffff);
3037 gfar_write(®s->gaddr1, 0xffffffff);
3038 gfar_write(®s->gaddr2, 0xffffffff);
3039 gfar_write(®s->gaddr3, 0xffffffff);
3040 gfar_write(®s->gaddr4, 0xffffffff);
3041 gfar_write(®s->gaddr5, 0xffffffff);
3042 gfar_write(®s->gaddr6, 0xffffffff);
3043 gfar_write(®s->gaddr7, 0xffffffff);
3048 /* zero out the hash */
3049 gfar_write(®s->igaddr0, 0x0);
3050 gfar_write(®s->igaddr1, 0x0);
3051 gfar_write(®s->igaddr2, 0x0);
3052 gfar_write(®s->igaddr3, 0x0);
3053 gfar_write(®s->igaddr4, 0x0);
3054 gfar_write(®s->igaddr5, 0x0);
3055 gfar_write(®s->igaddr6, 0x0);
3056 gfar_write(®s->igaddr7, 0x0);
3057 gfar_write(®s->gaddr0, 0x0);
3058 gfar_write(®s->gaddr1, 0x0);
3059 gfar_write(®s->gaddr2, 0x0);
3060 gfar_write(®s->gaddr3, 0x0);
3061 gfar_write(®s->gaddr4, 0x0);
3062 gfar_write(®s->gaddr5, 0x0);
3063 gfar_write(®s->gaddr6, 0x0);
3064 gfar_write(®s->gaddr7, 0x0);
3066 /* If we have extended hash tables, we need to
3067 * clear the exact match registers to prepare for
3069 if (priv->extended_hash) {
3070 em_num = GFAR_EM_NUM + 1;
3071 gfar_clear_exact_match(dev);
3078 if (netdev_mc_empty(dev))
3081 /* Parse the list, and set the appropriate bits */
3082 netdev_for_each_mc_addr(ha, dev) {
3084 gfar_set_mac_for_addr(dev, idx, ha->addr);
3087 gfar_set_hash_for_addr(dev, ha->addr);
3093 /* Clears each of the exact match registers to zero, so they
3094 * don't interfere with normal reception */
3095 static void gfar_clear_exact_match(struct net_device *dev)
3098 u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
3100 for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
3101 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
3104 /* Set the appropriate hash bit for the given addr */
3105 /* The algorithm works like so:
3106 * 1) Take the Destination Address (ie the multicast address), and
3107 * do a CRC on it (little endian), and reverse the bits of the
3109 * 2) Use the 8 most significant bits as a hash into a 256-entry
3110 * table. The table is controlled through 8 32-bit registers:
3111 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
3112 * gaddr7. This means that the 3 most significant bits in the
3113 * hash index which gaddr register to use, and the 5 other bits
3114 * indicate which bit (assuming an IBM numbering scheme, which
3115 * for PowerPC (tm) is usually the case) in the register holds
3117 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3120 struct gfar_private *priv = netdev_priv(dev);
3121 u32 result = ether_crc(MAC_ADDR_LEN, addr);
3122 int width = priv->hash_width;
3123 u8 whichbit = (result >> (32 - width)) & 0x1f;
3124 u8 whichreg = result >> (32 - width + 5);
3125 u32 value = (1 << (31-whichbit));
3127 tempval = gfar_read(priv->hash_regs[whichreg]);
3129 gfar_write(priv->hash_regs[whichreg], tempval);
3133 /* There are multiple MAC Address register pairs on some controllers
3134 * This function sets the numth pair to a given address
3136 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
3138 struct gfar_private *priv = netdev_priv(dev);
3139 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3141 char tmpbuf[MAC_ADDR_LEN];
3143 u32 __iomem *macptr = ®s->macstnaddr1;
3147 /* Now copy it into the mac registers backwards, cuz */
3148 /* little endian is silly */
3149 for (idx = 0; idx < MAC_ADDR_LEN; idx++)
3150 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
3152 gfar_write(macptr, *((u32 *) (tmpbuf)));
3154 tempval = *((u32 *) (tmpbuf + 4));
3156 gfar_write(macptr+1, tempval);
3159 /* GFAR error interrupt handler */
3160 static irqreturn_t gfar_error(int irq, void *grp_id)
3162 struct gfar_priv_grp *gfargrp = grp_id;
3163 struct gfar __iomem *regs = gfargrp->regs;
3164 struct gfar_private *priv= gfargrp->priv;
3165 struct net_device *dev = priv->ndev;
3167 /* Save ievent for future reference */
3168 u32 events = gfar_read(®s->ievent);
3171 gfar_write(®s->ievent, events & IEVENT_ERR_MASK);
3173 /* Magic Packet is not an error. */
3174 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3175 (events & IEVENT_MAG))
3176 events &= ~IEVENT_MAG;
3179 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3180 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
3181 dev->name, events, gfar_read(®s->imask));
3183 /* Update the error counters */
3184 if (events & IEVENT_TXE) {
3185 dev->stats.tx_errors++;
3187 if (events & IEVENT_LC)
3188 dev->stats.tx_window_errors++;
3189 if (events & IEVENT_CRL)
3190 dev->stats.tx_aborted_errors++;
3191 if (events & IEVENT_XFUN) {
3192 unsigned long flags;
3194 if (netif_msg_tx_err(priv))
3195 printk(KERN_DEBUG "%s: TX FIFO underrun, "
3196 "packet dropped.\n", dev->name);
3197 dev->stats.tx_dropped++;
3198 priv->extra_stats.tx_underrun++;
3200 local_irq_save(flags);
3203 /* Reactivate the Tx Queues */
3204 gfar_write(®s->tstat, gfargrp->tstat);
3207 local_irq_restore(flags);
3209 if (netif_msg_tx_err(priv))
3210 printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
3212 if (events & IEVENT_BSY) {
3213 dev->stats.rx_errors++;
3214 priv->extra_stats.rx_bsy++;
3216 gfar_receive(irq, grp_id);
3218 if (netif_msg_rx_err(priv))
3219 printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
3220 dev->name, gfar_read(®s->rstat));
3222 if (events & IEVENT_BABR) {
3223 dev->stats.rx_errors++;
3224 priv->extra_stats.rx_babr++;
3226 if (netif_msg_rx_err(priv))
3227 printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
3229 if (events & IEVENT_EBERR) {
3230 priv->extra_stats.eberr++;
3231 if (netif_msg_rx_err(priv))
3232 printk(KERN_DEBUG "%s: bus error\n", dev->name);
3234 if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
3235 printk(KERN_DEBUG "%s: control frame\n", dev->name);
3237 if (events & IEVENT_BABT) {
3238 priv->extra_stats.tx_babt++;
3239 if (netif_msg_tx_err(priv))
3240 printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
3245 static struct of_device_id gfar_match[] =
3249 .compatible = "gianfar",
3252 .compatible = "fsl,etsec2",
3256 MODULE_DEVICE_TABLE(of, gfar_match);
3258 /* Structure for a device driver */
3259 static struct of_platform_driver gfar_driver = {
3261 .name = "fsl-gianfar",
3262 .owner = THIS_MODULE,
3264 .of_match_table = gfar_match,
3266 .probe = gfar_probe,
3267 .remove = gfar_remove,
3270 static int __init gfar_init(void)
3272 return of_register_platform_driver(&gfar_driver);
3275 static void __exit gfar_exit(void)
3277 of_unregister_platform_driver(&gfar_driver);
3280 module_init(gfar_init);
3281 module_exit(gfar_exit);