2 * AT86RF230/RF231 driver
4 * Copyright (C) 2009-2012 Siemens AG
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2
8 * as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
20 * Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
21 * Alexander Smirnov <alex.bluesman.smirnov@gmail.com>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/interrupt.h>
26 #include <linux/gpio.h>
27 #include <linux/delay.h>
28 #include <linux/mutex.h>
29 #include <linux/workqueue.h>
30 #include <linux/spinlock.h>
31 #include <linux/spi/spi.h>
32 #include <linux/spi/at86rf230.h>
33 #include <linux/skbuff.h>
35 #include <net/mac802154.h>
36 #include <net/wpan-phy.h>
38 struct at86rf230_local {
39 struct spi_device *spi;
47 struct work_struct irqwork;
48 struct completion tx_complete;
50 struct ieee802154_dev *dev;
57 static inline int is_rf212(struct at86rf230_local *local)
59 return local->part == 7;
62 #define RG_TRX_STATUS (0x01)
63 #define SR_TRX_STATUS 0x01, 0x1f, 0
64 #define SR_RESERVED_01_3 0x01, 0x20, 5
65 #define SR_CCA_STATUS 0x01, 0x40, 6
66 #define SR_CCA_DONE 0x01, 0x80, 7
67 #define RG_TRX_STATE (0x02)
68 #define SR_TRX_CMD 0x02, 0x1f, 0
69 #define SR_TRAC_STATUS 0x02, 0xe0, 5
70 #define RG_TRX_CTRL_0 (0x03)
71 #define SR_CLKM_CTRL 0x03, 0x07, 0
72 #define SR_CLKM_SHA_SEL 0x03, 0x08, 3
73 #define SR_PAD_IO_CLKM 0x03, 0x30, 4
74 #define SR_PAD_IO 0x03, 0xc0, 6
75 #define RG_TRX_CTRL_1 (0x04)
76 #define SR_IRQ_POLARITY 0x04, 0x01, 0
77 #define SR_IRQ_MASK_MODE 0x04, 0x02, 1
78 #define SR_SPI_CMD_MODE 0x04, 0x0c, 2
79 #define SR_RX_BL_CTRL 0x04, 0x10, 4
80 #define SR_TX_AUTO_CRC_ON 0x04, 0x20, 5
81 #define SR_IRQ_2_EXT_EN 0x04, 0x40, 6
82 #define SR_PA_EXT_EN 0x04, 0x80, 7
83 #define RG_PHY_TX_PWR (0x05)
84 #define SR_TX_PWR 0x05, 0x0f, 0
85 #define SR_PA_LT 0x05, 0x30, 4
86 #define SR_PA_BUF_LT 0x05, 0xc0, 6
87 #define RG_PHY_RSSI (0x06)
88 #define SR_RSSI 0x06, 0x1f, 0
89 #define SR_RND_VALUE 0x06, 0x60, 5
90 #define SR_RX_CRC_VALID 0x06, 0x80, 7
91 #define RG_PHY_ED_LEVEL (0x07)
92 #define SR_ED_LEVEL 0x07, 0xff, 0
93 #define RG_PHY_CC_CCA (0x08)
94 #define SR_CHANNEL 0x08, 0x1f, 0
95 #define SR_CCA_MODE 0x08, 0x60, 5
96 #define SR_CCA_REQUEST 0x08, 0x80, 7
97 #define RG_CCA_THRES (0x09)
98 #define SR_CCA_ED_THRES 0x09, 0x0f, 0
99 #define SR_RESERVED_09_1 0x09, 0xf0, 4
100 #define RG_RX_CTRL (0x0a)
101 #define SR_PDT_THRES 0x0a, 0x0f, 0
102 #define SR_RESERVED_0a_1 0x0a, 0xf0, 4
103 #define RG_SFD_VALUE (0x0b)
104 #define SR_SFD_VALUE 0x0b, 0xff, 0
105 #define RG_TRX_CTRL_2 (0x0c)
106 #define SR_OQPSK_DATA_RATE 0x0c, 0x03, 0
107 #define SR_SUB_MODE 0x0c, 0x04, 2
108 #define SR_BPSK_QPSK 0x0c, 0x08, 3
109 #define SR_RESERVED_0c_4 0x0c, 0x70, 4
110 #define SR_RX_SAFE_MODE 0x0c, 0x80, 7
111 #define RG_ANT_DIV (0x0d)
112 #define SR_ANT_CTRL 0x0d, 0x03, 0
113 #define SR_ANT_EXT_SW_EN 0x0d, 0x04, 2
114 #define SR_ANT_DIV_EN 0x0d, 0x08, 3
115 #define SR_RESERVED_0d_2 0x0d, 0x70, 4
116 #define SR_ANT_SEL 0x0d, 0x80, 7
117 #define RG_IRQ_MASK (0x0e)
118 #define SR_IRQ_MASK 0x0e, 0xff, 0
119 #define RG_IRQ_STATUS (0x0f)
120 #define SR_IRQ_0_PLL_LOCK 0x0f, 0x01, 0
121 #define SR_IRQ_1_PLL_UNLOCK 0x0f, 0x02, 1
122 #define SR_IRQ_2_RX_START 0x0f, 0x04, 2
123 #define SR_IRQ_3_TRX_END 0x0f, 0x08, 3
124 #define SR_IRQ_4_CCA_ED_DONE 0x0f, 0x10, 4
125 #define SR_IRQ_5_AMI 0x0f, 0x20, 5
126 #define SR_IRQ_6_TRX_UR 0x0f, 0x40, 6
127 #define SR_IRQ_7_BAT_LOW 0x0f, 0x80, 7
128 #define RG_VREG_CTRL (0x10)
129 #define SR_RESERVED_10_6 0x10, 0x03, 0
130 #define SR_DVDD_OK 0x10, 0x04, 2
131 #define SR_DVREG_EXT 0x10, 0x08, 3
132 #define SR_RESERVED_10_3 0x10, 0x30, 4
133 #define SR_AVDD_OK 0x10, 0x40, 6
134 #define SR_AVREG_EXT 0x10, 0x80, 7
135 #define RG_BATMON (0x11)
136 #define SR_BATMON_VTH 0x11, 0x0f, 0
137 #define SR_BATMON_HR 0x11, 0x10, 4
138 #define SR_BATMON_OK 0x11, 0x20, 5
139 #define SR_RESERVED_11_1 0x11, 0xc0, 6
140 #define RG_XOSC_CTRL (0x12)
141 #define SR_XTAL_TRIM 0x12, 0x0f, 0
142 #define SR_XTAL_MODE 0x12, 0xf0, 4
143 #define RG_RX_SYN (0x15)
144 #define SR_RX_PDT_LEVEL 0x15, 0x0f, 0
145 #define SR_RESERVED_15_2 0x15, 0x70, 4
146 #define SR_RX_PDT_DIS 0x15, 0x80, 7
147 #define RG_XAH_CTRL_1 (0x17)
148 #define SR_RESERVED_17_8 0x17, 0x01, 0
149 #define SR_AACK_PROM_MODE 0x17, 0x02, 1
150 #define SR_AACK_ACK_TIME 0x17, 0x04, 2
151 #define SR_RESERVED_17_5 0x17, 0x08, 3
152 #define SR_AACK_UPLD_RES_FT 0x17, 0x10, 4
153 #define SR_AACK_FLTR_RES_FT 0x17, 0x20, 5
154 #define SR_RESERVED_17_2 0x17, 0x40, 6
155 #define SR_RESERVED_17_1 0x17, 0x80, 7
156 #define RG_FTN_CTRL (0x18)
157 #define SR_RESERVED_18_2 0x18, 0x7f, 0
158 #define SR_FTN_START 0x18, 0x80, 7
159 #define RG_PLL_CF (0x1a)
160 #define SR_RESERVED_1a_2 0x1a, 0x7f, 0
161 #define SR_PLL_CF_START 0x1a, 0x80, 7
162 #define RG_PLL_DCU (0x1b)
163 #define SR_RESERVED_1b_3 0x1b, 0x3f, 0
164 #define SR_RESERVED_1b_2 0x1b, 0x40, 6
165 #define SR_PLL_DCU_START 0x1b, 0x80, 7
166 #define RG_PART_NUM (0x1c)
167 #define SR_PART_NUM 0x1c, 0xff, 0
168 #define RG_VERSION_NUM (0x1d)
169 #define SR_VERSION_NUM 0x1d, 0xff, 0
170 #define RG_MAN_ID_0 (0x1e)
171 #define SR_MAN_ID_0 0x1e, 0xff, 0
172 #define RG_MAN_ID_1 (0x1f)
173 #define SR_MAN_ID_1 0x1f, 0xff, 0
174 #define RG_SHORT_ADDR_0 (0x20)
175 #define SR_SHORT_ADDR_0 0x20, 0xff, 0
176 #define RG_SHORT_ADDR_1 (0x21)
177 #define SR_SHORT_ADDR_1 0x21, 0xff, 0
178 #define RG_PAN_ID_0 (0x22)
179 #define SR_PAN_ID_0 0x22, 0xff, 0
180 #define RG_PAN_ID_1 (0x23)
181 #define SR_PAN_ID_1 0x23, 0xff, 0
182 #define RG_IEEE_ADDR_0 (0x24)
183 #define SR_IEEE_ADDR_0 0x24, 0xff, 0
184 #define RG_IEEE_ADDR_1 (0x25)
185 #define SR_IEEE_ADDR_1 0x25, 0xff, 0
186 #define RG_IEEE_ADDR_2 (0x26)
187 #define SR_IEEE_ADDR_2 0x26, 0xff, 0
188 #define RG_IEEE_ADDR_3 (0x27)
189 #define SR_IEEE_ADDR_3 0x27, 0xff, 0
190 #define RG_IEEE_ADDR_4 (0x28)
191 #define SR_IEEE_ADDR_4 0x28, 0xff, 0
192 #define RG_IEEE_ADDR_5 (0x29)
193 #define SR_IEEE_ADDR_5 0x29, 0xff, 0
194 #define RG_IEEE_ADDR_6 (0x2a)
195 #define SR_IEEE_ADDR_6 0x2a, 0xff, 0
196 #define RG_IEEE_ADDR_7 (0x2b)
197 #define SR_IEEE_ADDR_7 0x2b, 0xff, 0
198 #define RG_XAH_CTRL_0 (0x2c)
199 #define SR_SLOTTED_OPERATION 0x2c, 0x01, 0
200 #define SR_MAX_CSMA_RETRIES 0x2c, 0x0e, 1
201 #define SR_MAX_FRAME_RETRIES 0x2c, 0xf0, 4
202 #define RG_CSMA_SEED_0 (0x2d)
203 #define SR_CSMA_SEED_0 0x2d, 0xff, 0
204 #define RG_CSMA_SEED_1 (0x2e)
205 #define SR_CSMA_SEED_1 0x2e, 0x07, 0
206 #define SR_AACK_I_AM_COORD 0x2e, 0x08, 3
207 #define SR_AACK_DIS_ACK 0x2e, 0x10, 4
208 #define SR_AACK_SET_PD 0x2e, 0x20, 5
209 #define SR_AACK_FVN_MODE 0x2e, 0xc0, 6
210 #define RG_CSMA_BE (0x2f)
211 #define SR_MIN_BE 0x2f, 0x0f, 0
212 #define SR_MAX_BE 0x2f, 0xf0, 4
215 #define CMD_REG_MASK 0x3f
216 #define CMD_WRITE 0x40
219 #define IRQ_BAT_LOW (1 << 7)
220 #define IRQ_TRX_UR (1 << 6)
221 #define IRQ_AMI (1 << 5)
222 #define IRQ_CCA_ED (1 << 4)
223 #define IRQ_TRX_END (1 << 3)
224 #define IRQ_RX_START (1 << 2)
225 #define IRQ_PLL_UNL (1 << 1)
226 #define IRQ_PLL_LOCK (1 << 0)
228 #define IRQ_ACTIVE_HIGH 0
229 #define IRQ_ACTIVE_LOW 1
231 #define STATE_P_ON 0x00 /* BUSY */
232 #define STATE_BUSY_RX 0x01
233 #define STATE_BUSY_TX 0x02
234 #define STATE_FORCE_TRX_OFF 0x03
235 #define STATE_FORCE_TX_ON 0x04 /* IDLE */
236 /* 0x05 */ /* INVALID_PARAMETER */
237 #define STATE_RX_ON 0x06
238 /* 0x07 */ /* SUCCESS */
239 #define STATE_TRX_OFF 0x08
240 #define STATE_TX_ON 0x09
241 /* 0x0a - 0x0e */ /* 0x0a - UNSUPPORTED_ATTRIBUTE */
242 #define STATE_SLEEP 0x0F
243 #define STATE_BUSY_RX_AACK 0x11
244 #define STATE_BUSY_TX_ARET 0x12
245 #define STATE_RX_AACK_ON 0x16
246 #define STATE_TX_ARET_ON 0x19
247 #define STATE_RX_ON_NOCLK 0x1C
248 #define STATE_RX_AACK_ON_NOCLK 0x1D
249 #define STATE_BUSY_RX_AACK_NOCLK 0x1E
250 #define STATE_TRANSITION_IN_PROGRESS 0x1F
253 __at86rf230_detect_device(struct spi_device *spi, u16 *man_id, u8 *part,
257 u8 *buf = kmalloc(2, GFP_KERNEL);
259 struct spi_message msg;
260 struct spi_transfer xfer = {
270 for (reg = RG_PART_NUM; reg <= RG_MAN_ID_1; reg++) {
271 buf[0] = (reg & CMD_REG_MASK) | CMD_REG;
273 dev_vdbg(&spi->dev, "buf[0] = %02x\n", buf[0]);
274 spi_message_init(&msg);
275 spi_message_add_tail(&xfer, &msg);
277 status = spi_sync(spi, &msg);
278 dev_vdbg(&spi->dev, "status = %d\n", status);
282 dev_vdbg(&spi->dev, "status = %d\n", status);
283 dev_vdbg(&spi->dev, "buf[0] = %02x\n", buf[0]);
284 dev_vdbg(&spi->dev, "buf[1] = %02x\n", buf[1]);
287 data[reg - RG_PART_NUM] = buf[1];
295 *man_id = (data[3] << 8) | data[2];
304 __at86rf230_write(struct at86rf230_local *lp, u8 addr, u8 data)
308 struct spi_message msg;
309 struct spi_transfer xfer = {
314 buf[0] = (addr & CMD_REG_MASK) | CMD_REG | CMD_WRITE;
316 dev_vdbg(&lp->spi->dev, "buf[0] = %02x\n", buf[0]);
317 dev_vdbg(&lp->spi->dev, "buf[1] = %02x\n", buf[1]);
318 spi_message_init(&msg);
319 spi_message_add_tail(&xfer, &msg);
321 status = spi_sync(lp->spi, &msg);
322 dev_vdbg(&lp->spi->dev, "status = %d\n", status);
326 dev_vdbg(&lp->spi->dev, "status = %d\n", status);
327 dev_vdbg(&lp->spi->dev, "buf[0] = %02x\n", buf[0]);
328 dev_vdbg(&lp->spi->dev, "buf[1] = %02x\n", buf[1]);
334 __at86rf230_read_subreg(struct at86rf230_local *lp,
335 u8 addr, u8 mask, int shift, u8 *data)
339 struct spi_message msg;
340 struct spi_transfer xfer = {
346 buf[0] = (addr & CMD_REG_MASK) | CMD_REG;
348 dev_vdbg(&lp->spi->dev, "buf[0] = %02x\n", buf[0]);
349 spi_message_init(&msg);
350 spi_message_add_tail(&xfer, &msg);
352 status = spi_sync(lp->spi, &msg);
353 dev_vdbg(&lp->spi->dev, "status = %d\n", status);
357 dev_vdbg(&lp->spi->dev, "status = %d\n", status);
358 dev_vdbg(&lp->spi->dev, "buf[0] = %02x\n", buf[0]);
359 dev_vdbg(&lp->spi->dev, "buf[1] = %02x\n", buf[1]);
368 at86rf230_read_subreg(struct at86rf230_local *lp,
369 u8 addr, u8 mask, int shift, u8 *data)
373 mutex_lock(&lp->bmux);
374 status = __at86rf230_read_subreg(lp, addr, mask, shift, data);
375 mutex_unlock(&lp->bmux);
381 at86rf230_write_subreg(struct at86rf230_local *lp,
382 u8 addr, u8 mask, int shift, u8 data)
387 mutex_lock(&lp->bmux);
388 status = __at86rf230_read_subreg(lp, addr, 0xff, 0, &val);
393 val |= (data << shift) & mask;
395 status = __at86rf230_write(lp, addr, val);
397 mutex_unlock(&lp->bmux);
403 at86rf230_write_fbuf(struct at86rf230_local *lp, u8 *data, u8 len)
407 struct spi_message msg;
408 struct spi_transfer xfer_head = {
413 struct spi_transfer xfer_buf = {
418 mutex_lock(&lp->bmux);
419 buf[0] = CMD_WRITE | CMD_FB;
420 buf[1] = len + 2; /* 2 bytes for CRC that isn't written */
422 dev_vdbg(&lp->spi->dev, "buf[0] = %02x\n", buf[0]);
423 dev_vdbg(&lp->spi->dev, "buf[1] = %02x\n", buf[1]);
425 spi_message_init(&msg);
426 spi_message_add_tail(&xfer_head, &msg);
427 spi_message_add_tail(&xfer_buf, &msg);
429 status = spi_sync(lp->spi, &msg);
430 dev_vdbg(&lp->spi->dev, "status = %d\n", status);
434 dev_vdbg(&lp->spi->dev, "status = %d\n", status);
435 dev_vdbg(&lp->spi->dev, "buf[0] = %02x\n", buf[0]);
436 dev_vdbg(&lp->spi->dev, "buf[1] = %02x\n", buf[1]);
438 mutex_unlock(&lp->bmux);
443 at86rf230_read_fbuf(struct at86rf230_local *lp, u8 *data, u8 *len, u8 *lqi)
447 struct spi_message msg;
448 struct spi_transfer xfer_head = {
453 struct spi_transfer xfer_head1 = {
458 struct spi_transfer xfer_buf = {
463 mutex_lock(&lp->bmux);
468 spi_message_init(&msg);
469 spi_message_add_tail(&xfer_head, &msg);
471 status = spi_sync(lp->spi, &msg);
472 dev_vdbg(&lp->spi->dev, "status = %d\n", status);
474 xfer_buf.len = *(buf + 1) + 1;
480 spi_message_init(&msg);
481 spi_message_add_tail(&xfer_head1, &msg);
482 spi_message_add_tail(&xfer_buf, &msg);
484 status = spi_sync(lp->spi, &msg);
489 dev_vdbg(&lp->spi->dev, "status = %d\n", status);
490 dev_vdbg(&lp->spi->dev, "buf[0] = %02x\n", buf[0]);
491 dev_vdbg(&lp->spi->dev, "buf[1] = %02x\n", buf[1]);
494 if (lqi && (*len > lp->buf[1]))
495 *lqi = data[lp->buf[1]];
497 mutex_unlock(&lp->bmux);
503 at86rf230_ed(struct ieee802154_dev *dev, u8 *level)
512 at86rf230_state(struct ieee802154_dev *dev, int state)
514 struct at86rf230_local *lp = dev->priv;
521 if (state == STATE_FORCE_TX_ON)
522 desired_status = STATE_TX_ON;
523 else if (state == STATE_FORCE_TRX_OFF)
524 desired_status = STATE_TRX_OFF;
526 desired_status = state;
529 rc = at86rf230_read_subreg(lp, SR_TRX_STATUS, &val);
532 } while (val == STATE_TRANSITION_IN_PROGRESS);
534 if (val == desired_status)
537 /* state is equal to phy states */
538 rc = at86rf230_write_subreg(lp, SR_TRX_CMD, state);
543 rc = at86rf230_read_subreg(lp, SR_TRX_STATUS, &val);
546 } while (val == STATE_TRANSITION_IN_PROGRESS);
549 if (val == desired_status)
552 pr_err("unexpected state change: %d, asked for %d\n", val, state);
556 pr_err("error: %d\n", rc);
561 at86rf230_start(struct ieee802154_dev *dev)
563 struct at86rf230_local *lp = dev->priv;
566 rc = at86rf230_write_subreg(lp, SR_RX_SAFE_MODE, 1);
570 return at86rf230_state(dev, STATE_RX_AACK_ON);
574 at86rf230_stop(struct ieee802154_dev *dev)
576 at86rf230_state(dev, STATE_FORCE_TRX_OFF);
580 at86rf230_set_channel(struct at86rf230_local *lp, int page, int channel)
582 return at86rf230_write_subreg(lp, SR_CHANNEL, channel);
586 at86rf212_set_channel(struct at86rf230_local *lp, int page, int channel)
591 rc = at86rf230_write_subreg(lp, SR_SUB_MODE, 0);
593 rc = at86rf230_write_subreg(lp, SR_SUB_MODE, 1);
597 return at86rf230_write_subreg(lp, SR_CHANNEL, channel);
601 at86rf230_channel(struct ieee802154_dev *dev, int page, int channel)
603 struct at86rf230_local *lp = dev->priv;
608 if (page < 0 || page > 31 ||
609 !(lp->dev->phy->channels_supported[page] & BIT(channel))) {
615 rc = at86rf212_set_channel(lp, page, channel);
617 rc = at86rf230_set_channel(lp, page, channel);
621 msleep(1); /* Wait for PLL */
622 dev->phy->current_channel = channel;
628 at86rf230_xmit(struct ieee802154_dev *dev, struct sk_buff *skb)
630 struct at86rf230_local *lp = dev->priv;
634 spin_lock(&lp->lock);
636 spin_unlock(&lp->lock);
639 spin_unlock(&lp->lock);
643 rc = at86rf230_state(dev, STATE_FORCE_TX_ON);
647 spin_lock_irqsave(&lp->lock, flags);
649 reinit_completion(&lp->tx_complete);
650 spin_unlock_irqrestore(&lp->lock, flags);
652 rc = at86rf230_write_fbuf(lp, skb->data, skb->len);
656 rc = at86rf230_write_subreg(lp, SR_TRX_CMD, STATE_BUSY_TX);
660 rc = wait_for_completion_interruptible(&lp->tx_complete);
664 rc = at86rf230_start(dev);
669 at86rf230_start(dev);
671 pr_err("error: %d\n", rc);
673 spin_lock_irqsave(&lp->lock, flags);
675 spin_unlock_irqrestore(&lp->lock, flags);
680 static int at86rf230_rx(struct at86rf230_local *lp)
682 u8 len = 128, lqi = 0;
685 skb = alloc_skb(len, GFP_KERNEL);
690 if (at86rf230_read_fbuf(lp, skb_put(skb, len), &len, &lqi))
696 skb_trim(skb, len - 2); /* We do not put CRC into the frame */
698 ieee802154_rx_irqsafe(lp->dev, skb, lqi);
700 dev_dbg(&lp->spi->dev, "READ_FBUF: %d %x\n", len, lqi);
704 pr_debug("received frame is too small\n");
711 at86rf230_set_hw_addr_filt(struct ieee802154_dev *dev,
712 struct ieee802154_hw_addr_filt *filt,
713 unsigned long changed)
715 struct at86rf230_local *lp = dev->priv;
717 if (changed & IEEE802515_AFILT_SADDR_CHANGED) {
718 dev_vdbg(&lp->spi->dev,
719 "at86rf230_set_hw_addr_filt called for saddr\n");
720 __at86rf230_write(lp, RG_SHORT_ADDR_0, filt->short_addr);
721 __at86rf230_write(lp, RG_SHORT_ADDR_1, filt->short_addr >> 8);
724 if (changed & IEEE802515_AFILT_PANID_CHANGED) {
725 dev_vdbg(&lp->spi->dev,
726 "at86rf230_set_hw_addr_filt called for pan id\n");
727 __at86rf230_write(lp, RG_PAN_ID_0, filt->pan_id);
728 __at86rf230_write(lp, RG_PAN_ID_1, filt->pan_id >> 8);
731 if (changed & IEEE802515_AFILT_IEEEADDR_CHANGED) {
732 dev_vdbg(&lp->spi->dev,
733 "at86rf230_set_hw_addr_filt called for IEEE addr\n");
734 at86rf230_write_subreg(lp, SR_IEEE_ADDR_0, filt->ieee_addr[7]);
735 at86rf230_write_subreg(lp, SR_IEEE_ADDR_1, filt->ieee_addr[6]);
736 at86rf230_write_subreg(lp, SR_IEEE_ADDR_2, filt->ieee_addr[5]);
737 at86rf230_write_subreg(lp, SR_IEEE_ADDR_3, filt->ieee_addr[4]);
738 at86rf230_write_subreg(lp, SR_IEEE_ADDR_4, filt->ieee_addr[3]);
739 at86rf230_write_subreg(lp, SR_IEEE_ADDR_5, filt->ieee_addr[2]);
740 at86rf230_write_subreg(lp, SR_IEEE_ADDR_6, filt->ieee_addr[1]);
741 at86rf230_write_subreg(lp, SR_IEEE_ADDR_7, filt->ieee_addr[0]);
744 if (changed & IEEE802515_AFILT_PANC_CHANGED) {
745 dev_vdbg(&lp->spi->dev,
746 "at86rf230_set_hw_addr_filt called for panc change\n");
748 at86rf230_write_subreg(lp, SR_AACK_I_AM_COORD, 1);
750 at86rf230_write_subreg(lp, SR_AACK_I_AM_COORD, 0);
757 at86rf212_set_txpower(struct ieee802154_dev *dev, int db)
759 struct at86rf230_local *lp = dev->priv;
762 /* typical maximum output is 5dBm with RG_PHY_TX_PWR 0x60, lower five
763 * bits decrease power in 1dB steps. 0x60 represents extra PA gain of
765 * thus, supported values for db range from -26 to 5, for 31dB of
766 * reduction to 0dB of reduction.
768 if (db > 5 || db < -26)
773 rc = __at86rf230_write(lp, RG_PHY_TX_PWR, 0x60 | db);
780 static struct ieee802154_ops at86rf230_ops = {
781 .owner = THIS_MODULE,
782 .xmit = at86rf230_xmit,
784 .set_channel = at86rf230_channel,
785 .start = at86rf230_start,
786 .stop = at86rf230_stop,
787 .set_hw_addr_filt = at86rf230_set_hw_addr_filt,
790 static struct ieee802154_ops at86rf212_ops = {
791 .owner = THIS_MODULE,
792 .xmit = at86rf230_xmit,
794 .set_channel = at86rf230_channel,
795 .start = at86rf230_start,
796 .stop = at86rf230_stop,
797 .set_hw_addr_filt = at86rf230_set_hw_addr_filt,
798 .set_txpower = at86rf212_set_txpower,
801 static void at86rf230_irqwork(struct work_struct *work)
803 struct at86rf230_local *lp =
804 container_of(work, struct at86rf230_local, irqwork);
809 rc = at86rf230_read_subreg(lp, RG_IRQ_STATUS, 0xff, 0, &val);
812 status &= ~IRQ_PLL_LOCK; /* ignore */
813 status &= ~IRQ_RX_START; /* ignore */
814 status &= ~IRQ_AMI; /* ignore */
815 status &= ~IRQ_TRX_UR; /* FIXME: possibly handle ???*/
817 if (status & IRQ_TRX_END) {
818 spin_lock_irqsave(&lp->lock, flags);
819 status &= ~IRQ_TRX_END;
822 spin_unlock_irqrestore(&lp->lock, flags);
823 complete(&lp->tx_complete);
825 spin_unlock_irqrestore(&lp->lock, flags);
830 spin_lock_irqsave(&lp->lock, flags);
832 spin_unlock_irqrestore(&lp->lock, flags);
835 static void at86rf230_irqwork_level(struct work_struct *work)
837 struct at86rf230_local *lp =
838 container_of(work, struct at86rf230_local, irqwork);
840 at86rf230_irqwork(work);
842 enable_irq(lp->spi->irq);
845 static irqreturn_t at86rf230_isr(int irq, void *data)
847 struct at86rf230_local *lp = data;
849 spin_lock(&lp->lock);
851 spin_unlock(&lp->lock);
853 schedule_work(&lp->irqwork);
858 static irqreturn_t at86rf230_isr_level(int irq, void *data)
860 disable_irq_nosync(irq);
862 return at86rf230_isr(irq, data);
865 static int at86rf230_irq_polarity(struct at86rf230_local *lp, int pol)
867 return at86rf230_write_subreg(lp, SR_IRQ_POLARITY, pol);
870 static int at86rf230_hw_init(struct at86rf230_local *lp)
872 struct at86rf230_platform_data *pdata = lp->spi->dev.platform_data;
876 rc = at86rf230_read_subreg(lp, SR_TRX_STATUS, &status);
880 dev_info(&lp->spi->dev, "Status: %02x\n", status);
881 if (status == STATE_P_ON) {
882 rc = at86rf230_write_subreg(lp, SR_TRX_CMD,
883 STATE_FORCE_TRX_OFF);
887 rc = at86rf230_read_subreg(lp, SR_TRX_STATUS, &status);
890 dev_info(&lp->spi->dev, "Status: %02x\n", status);
893 /* configure irq polarity, defaults to high active */
894 if (pdata->irq_type & (IRQF_TRIGGER_FALLING | IRQF_TRIGGER_LOW))
895 irq_pol = IRQ_ACTIVE_LOW;
897 irq_pol = IRQ_ACTIVE_HIGH;
899 rc = at86rf230_irq_polarity(lp, irq_pol);
903 rc = at86rf230_write_subreg(lp, SR_IRQ_MASK, IRQ_TRX_END);
907 /* CLKM changes are applied immediately */
908 rc = at86rf230_write_subreg(lp, SR_CLKM_SHA_SEL, 0x00);
913 rc = at86rf230_write_subreg(lp, SR_CLKM_CTRL, 0x00);
916 /* Wait the next SLEEP cycle */
919 rc = at86rf230_write_subreg(lp, SR_TRX_CMD, STATE_TX_ON);
924 rc = at86rf230_read_subreg(lp, SR_TRX_STATUS, &status);
927 dev_info(&lp->spi->dev, "Status: %02x\n", status);
929 rc = at86rf230_read_subreg(lp, SR_DVDD_OK, &status);
933 dev_err(&lp->spi->dev, "DVDD error\n");
937 rc = at86rf230_read_subreg(lp, SR_AVDD_OK, &status);
941 dev_err(&lp->spi->dev, "AVDD error\n");
948 static int at86rf230_probe(struct spi_device *spi)
950 struct at86rf230_platform_data *pdata;
951 struct ieee802154_dev *dev;
952 struct at86rf230_local *lp;
954 u8 part = 0, version = 0, status;
955 irq_handler_t irq_handler;
956 work_func_t irq_worker;
959 struct ieee802154_ops *ops = NULL;
962 dev_err(&spi->dev, "no IRQ specified\n");
966 pdata = spi->dev.platform_data;
968 dev_err(&spi->dev, "no platform_data\n");
972 rc = gpio_request(pdata->rstn, "rstn");
976 if (gpio_is_valid(pdata->slp_tr)) {
977 rc = gpio_request(pdata->slp_tr, "slp_tr");
982 rc = gpio_direction_output(pdata->rstn, 1);
986 if (gpio_is_valid(pdata->slp_tr)) {
987 rc = gpio_direction_output(pdata->slp_tr, 0);
994 gpio_set_value(pdata->rstn, 0);
996 gpio_set_value(pdata->rstn, 1);
999 rc = __at86rf230_detect_device(spi, &man_id, &part, &version);
1003 if (man_id != 0x001f) {
1004 dev_err(&spi->dev, "Non-Atmel dev found (MAN_ID %02x %02x)\n",
1005 man_id >> 8, man_id & 0xFF);
1013 /* FIXME: should be easy to support; */
1017 ops = &at86rf230_ops;
1022 ops = &at86rf212_ops;
1029 dev_info(&spi->dev, "Detected %s chip version %d\n", chip, version);
1035 dev = ieee802154_alloc_device(sizeof(*lp), ops);
1048 dev->parent = &spi->dev;
1049 dev->extra_tx_headroom = 0;
1050 dev->flags = IEEE802154_HW_OMIT_CKSUM | IEEE802154_HW_AACK;
1052 if (pdata->irq_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
1053 irq_worker = at86rf230_irqwork;
1054 irq_handler = at86rf230_isr;
1056 irq_worker = at86rf230_irqwork_level;
1057 irq_handler = at86rf230_isr_level;
1060 mutex_init(&lp->bmux);
1061 INIT_WORK(&lp->irqwork, irq_worker);
1062 spin_lock_init(&lp->lock);
1063 init_completion(&lp->tx_complete);
1065 spi_set_drvdata(spi, lp);
1068 dev->phy->channels_supported[0] = 0x00007FF;
1070 dev->phy->channels_supported[0] = 0x7FFF800;
1072 rc = at86rf230_hw_init(lp);
1076 rc = request_irq(spi->irq, irq_handler,
1077 IRQF_SHARED | pdata->irq_type,
1078 dev_name(&spi->dev), lp);
1082 /* Read irq status register to reset irq line */
1083 rc = at86rf230_read_subreg(lp, RG_IRQ_STATUS, 0xff, 0, &status);
1087 rc = ieee802154_register_device(lp->dev);
1094 free_irq(spi->irq, lp);
1096 flush_work(&lp->irqwork);
1097 spi_set_drvdata(spi, NULL);
1098 mutex_destroy(&lp->bmux);
1099 ieee802154_free_device(lp->dev);
1102 if (gpio_is_valid(pdata->slp_tr))
1103 gpio_free(pdata->slp_tr);
1105 gpio_free(pdata->rstn);
1109 static int at86rf230_remove(struct spi_device *spi)
1111 struct at86rf230_local *lp = spi_get_drvdata(spi);
1112 struct at86rf230_platform_data *pdata = spi->dev.platform_data;
1114 ieee802154_unregister_device(lp->dev);
1116 free_irq(spi->irq, lp);
1117 flush_work(&lp->irqwork);
1119 if (gpio_is_valid(pdata->slp_tr))
1120 gpio_free(pdata->slp_tr);
1121 gpio_free(pdata->rstn);
1123 mutex_destroy(&lp->bmux);
1124 ieee802154_free_device(lp->dev);
1126 dev_dbg(&spi->dev, "unregistered at86rf230\n");
1130 static struct spi_driver at86rf230_driver = {
1132 .name = "at86rf230",
1133 .owner = THIS_MODULE,
1135 .probe = at86rf230_probe,
1136 .remove = at86rf230_remove,
1139 module_spi_driver(at86rf230_driver);
1141 MODULE_DESCRIPTION("AT86RF230 Transceiver Driver");
1142 MODULE_LICENSE("GPL v2");