2 * Driver for Microchip MRF24J40 802.15.4 Wireless-PAN Networking controller
4 * Copyright (C) 2012 Alan Ott <alan@signal11.us>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #include <linux/spi/spi.h>
23 #include <linux/interrupt.h>
24 #include <linux/module.h>
25 #include <linux/pinctrl/consumer.h>
26 #include <net/wpan-phy.h>
27 #include <net/mac802154.h>
28 #include <net/ieee802154.h>
30 /* MRF24J40 Short Address Registers */
31 #define REG_RXMCR 0x00 /* Receive MAC control */
32 #define REG_PANIDL 0x01 /* PAN ID (low) */
33 #define REG_PANIDH 0x02 /* PAN ID (high) */
34 #define REG_SADRL 0x03 /* Short address (low) */
35 #define REG_SADRH 0x04 /* Short address (high) */
36 #define REG_EADR0 0x05 /* Long address (low) (high is EADR7) */
37 #define REG_TXMCR 0x11 /* Transmit MAC control */
38 #define REG_PACON0 0x16 /* Power Amplifier Control */
39 #define REG_PACON1 0x17 /* Power Amplifier Control */
40 #define REG_PACON2 0x18 /* Power Amplifier Control */
41 #define REG_TXNCON 0x1B /* Transmit Normal FIFO Control */
42 #define REG_TXSTAT 0x24 /* TX MAC Status Register */
43 #define REG_SOFTRST 0x2A /* Soft Reset */
44 #define REG_TXSTBL 0x2E /* TX Stabilization */
45 #define REG_INTSTAT 0x31 /* Interrupt Status */
46 #define REG_INTCON 0x32 /* Interrupt Control */
47 #define REG_RFCTL 0x36 /* RF Control Mode Register */
48 #define REG_BBREG1 0x39 /* Baseband Registers */
49 #define REG_BBREG2 0x3A /* */
50 #define REG_BBREG6 0x3E /* */
51 #define REG_CCAEDTH 0x3F /* Energy Detection Threshold */
53 /* MRF24J40 Long Address Registers */
54 #define REG_RFCON0 0x200 /* RF Control Registers */
55 #define REG_RFCON1 0x201
56 #define REG_RFCON2 0x202
57 #define REG_RFCON3 0x203
58 #define REG_RFCON5 0x205
59 #define REG_RFCON6 0x206
60 #define REG_RFCON7 0x207
61 #define REG_RFCON8 0x208
62 #define REG_RSSI 0x210
63 #define REG_SLPCON0 0x211 /* Sleep Clock Control Registers */
64 #define REG_SLPCON1 0x220
65 #define REG_WAKETIMEL 0x222 /* Wake-up Time Match Value Low */
66 #define REG_WAKETIMEH 0x223 /* Wake-up Time Match Value High */
67 #define REG_RX_FIFO 0x300 /* Receive FIFO */
69 /* Device configuration: Only channels 11-26 on page 0 are supported. */
70 #define MRF24J40_CHAN_MIN 11
71 #define MRF24J40_CHAN_MAX 26
72 #define CHANNEL_MASK (((u32)1 << (MRF24J40_CHAN_MAX + 1)) \
73 - ((u32)1 << MRF24J40_CHAN_MIN))
75 #define TX_FIFO_SIZE 128 /* From datasheet */
76 #define RX_FIFO_SIZE 144 /* From datasheet */
77 #define SET_CHANNEL_DELAY_US 192 /* From datasheet */
79 /* Device Private Data */
81 struct spi_device *spi;
82 struct ieee802154_dev *dev;
84 struct mutex buffer_mutex; /* only used to protect buf */
85 struct completion tx_complete;
86 struct work_struct irqwork;
87 u8 *buf; /* 3 bytes. Used for SPI single-register transfers. */
90 /* Read/Write SPI Commands for Short and Long Address registers. */
91 #define MRF24J40_READSHORT(reg) ((reg) << 1)
92 #define MRF24J40_WRITESHORT(reg) ((reg) << 1 | 1)
93 #define MRF24J40_READLONG(reg) (1 << 15 | (reg) << 5)
94 #define MRF24J40_WRITELONG(reg) (1 << 15 | (reg) << 5 | 1 << 4)
96 /* The datasheet indicates the theoretical maximum for SCK to be 10MHz */
97 #define MAX_SPI_SPEED_HZ 10000000
99 #define printdev(X) (&X->spi->dev)
101 static int write_short_reg(struct mrf24j40 *devrec, u8 reg, u8 value)
104 struct spi_message msg;
105 struct spi_transfer xfer = {
107 .tx_buf = devrec->buf,
108 .rx_buf = devrec->buf,
111 spi_message_init(&msg);
112 spi_message_add_tail(&xfer, &msg);
114 mutex_lock(&devrec->buffer_mutex);
115 devrec->buf[0] = MRF24J40_WRITESHORT(reg);
116 devrec->buf[1] = value;
118 ret = spi_sync(devrec->spi, &msg);
120 dev_err(printdev(devrec),
121 "SPI write Failed for short register 0x%hhx\n", reg);
123 mutex_unlock(&devrec->buffer_mutex);
127 static int read_short_reg(struct mrf24j40 *devrec, u8 reg, u8 *val)
130 struct spi_message msg;
131 struct spi_transfer xfer = {
133 .tx_buf = devrec->buf,
134 .rx_buf = devrec->buf,
137 spi_message_init(&msg);
138 spi_message_add_tail(&xfer, &msg);
140 mutex_lock(&devrec->buffer_mutex);
141 devrec->buf[0] = MRF24J40_READSHORT(reg);
144 ret = spi_sync(devrec->spi, &msg);
146 dev_err(printdev(devrec),
147 "SPI read Failed for short register 0x%hhx\n", reg);
149 *val = devrec->buf[1];
151 mutex_unlock(&devrec->buffer_mutex);
155 static int read_long_reg(struct mrf24j40 *devrec, u16 reg, u8 *value)
159 struct spi_message msg;
160 struct spi_transfer xfer = {
162 .tx_buf = devrec->buf,
163 .rx_buf = devrec->buf,
166 spi_message_init(&msg);
167 spi_message_add_tail(&xfer, &msg);
169 cmd = MRF24J40_READLONG(reg);
170 mutex_lock(&devrec->buffer_mutex);
171 devrec->buf[0] = cmd >> 8 & 0xff;
172 devrec->buf[1] = cmd & 0xff;
175 ret = spi_sync(devrec->spi, &msg);
177 dev_err(printdev(devrec),
178 "SPI read Failed for long register 0x%hx\n", reg);
180 *value = devrec->buf[2];
182 mutex_unlock(&devrec->buffer_mutex);
186 static int write_long_reg(struct mrf24j40 *devrec, u16 reg, u8 val)
190 struct spi_message msg;
191 struct spi_transfer xfer = {
193 .tx_buf = devrec->buf,
194 .rx_buf = devrec->buf,
197 spi_message_init(&msg);
198 spi_message_add_tail(&xfer, &msg);
200 cmd = MRF24J40_WRITELONG(reg);
201 mutex_lock(&devrec->buffer_mutex);
202 devrec->buf[0] = cmd >> 8 & 0xff;
203 devrec->buf[1] = cmd & 0xff;
204 devrec->buf[2] = val;
206 ret = spi_sync(devrec->spi, &msg);
208 dev_err(printdev(devrec),
209 "SPI write Failed for long register 0x%hx\n", reg);
211 mutex_unlock(&devrec->buffer_mutex);
215 /* This function relies on an undocumented write method. Once a write command
216 and address is set, as many bytes of data as desired can be clocked into
217 the device. The datasheet only shows setting one byte at a time. */
218 static int write_tx_buf(struct mrf24j40 *devrec, u16 reg,
219 const u8 *data, size_t length)
224 struct spi_message msg;
225 struct spi_transfer addr_xfer = {
227 .tx_buf = devrec->buf,
229 struct spi_transfer lengths_xfer = {
231 .tx_buf = &lengths, /* TODO: Is DMA really required for SPI? */
233 struct spi_transfer data_xfer = {
238 /* Range check the length. 2 bytes are used for the length fields.*/
239 if (length > TX_FIFO_SIZE-2) {
240 dev_err(printdev(devrec), "write_tx_buf() was passed too large a buffer. Performing short write.\n");
241 length = TX_FIFO_SIZE-2;
244 spi_message_init(&msg);
245 spi_message_add_tail(&addr_xfer, &msg);
246 spi_message_add_tail(&lengths_xfer, &msg);
247 spi_message_add_tail(&data_xfer, &msg);
249 cmd = MRF24J40_WRITELONG(reg);
250 mutex_lock(&devrec->buffer_mutex);
251 devrec->buf[0] = cmd >> 8 & 0xff;
252 devrec->buf[1] = cmd & 0xff;
253 lengths[0] = 0x0; /* Header Length. Set to 0 for now. TODO */
254 lengths[1] = length; /* Total length */
256 ret = spi_sync(devrec->spi, &msg);
258 dev_err(printdev(devrec), "SPI write Failed for TX buf\n");
260 mutex_unlock(&devrec->buffer_mutex);
264 static int mrf24j40_read_rx_buf(struct mrf24j40 *devrec,
265 u8 *data, u8 *len, u8 *lqi)
272 struct spi_message msg;
273 struct spi_transfer addr_xfer = {
277 struct spi_transfer data_xfer = {
278 .len = 0x0, /* set below */
281 struct spi_transfer status_xfer = {
286 /* Get the length of the data in the RX FIFO. The length in this
287 * register exclues the 1-byte length field at the beginning. */
288 ret = read_long_reg(devrec, REG_RX_FIFO, &rx_len);
292 /* Range check the RX FIFO length, accounting for the one-byte
293 * length field at the begining. */
294 if (rx_len > RX_FIFO_SIZE-1) {
295 dev_err(printdev(devrec), "Invalid length read from device. Performing short read.\n");
296 rx_len = RX_FIFO_SIZE-1;
300 /* Passed in buffer wasn't big enough. Should never happen. */
301 dev_err(printdev(devrec), "Buffer not big enough. Performing short read\n");
305 /* Set up the commands to read the data. */
306 cmd = MRF24J40_READLONG(REG_RX_FIFO+1);
307 addr[0] = cmd >> 8 & 0xff;
308 addr[1] = cmd & 0xff;
309 data_xfer.len = rx_len;
311 spi_message_init(&msg);
312 spi_message_add_tail(&addr_xfer, &msg);
313 spi_message_add_tail(&data_xfer, &msg);
314 spi_message_add_tail(&status_xfer, &msg);
316 ret = spi_sync(devrec->spi, &msg);
318 dev_err(printdev(devrec), "SPI RX Buffer Read Failed.\n");
326 print_hex_dump(KERN_DEBUG, "mrf24j40 rx: ",
327 DUMP_PREFIX_OFFSET, 16, 1, data, *len, 0);
328 printk(KERN_DEBUG "mrf24j40 rx: lqi: %02hhx rssi: %02hhx\n",
329 lqi_rssi[0], lqi_rssi[1]);
336 static int mrf24j40_tx(struct ieee802154_dev *dev, struct sk_buff *skb)
338 struct mrf24j40 *devrec = dev->priv;
342 dev_dbg(printdev(devrec), "tx packet of %d bytes\n", skb->len);
344 ret = write_tx_buf(devrec, 0x000, skb->data, skb->len);
348 /* Set TXNTRIG bit of TXNCON to send packet */
349 ret = read_short_reg(devrec, REG_TXNCON, &val);
353 /* Set TXNACKREQ if the ACK bit is set in the packet. */
354 if (skb->data[0] & IEEE802154_FC_ACK_REQ)
356 write_short_reg(devrec, REG_TXNCON, val);
358 INIT_COMPLETION(devrec->tx_complete);
360 /* Wait for the device to send the TX complete interrupt. */
361 ret = wait_for_completion_interruptible_timeout(
362 &devrec->tx_complete,
364 if (ret == -ERESTARTSYS)
367 dev_warn(printdev(devrec), "Timeout waiting for TX interrupt\n");
372 /* Check for send error from the device. */
373 ret = read_short_reg(devrec, REG_TXSTAT, &val);
377 dev_dbg(printdev(devrec), "Error Sending. Retry count exceeded\n");
378 ret = -ECOMM; /* TODO: Better error code ? */
380 dev_dbg(printdev(devrec), "Packet Sent\n");
387 static int mrf24j40_ed(struct ieee802154_dev *dev, u8 *level)
390 printk(KERN_WARNING "mrf24j40: ed not implemented\n");
395 static int mrf24j40_start(struct ieee802154_dev *dev)
397 struct mrf24j40 *devrec = dev->priv;
401 dev_dbg(printdev(devrec), "start\n");
403 ret = read_short_reg(devrec, REG_INTCON, &val);
406 val &= ~(0x1|0x8); /* Clear TXNIE and RXIE. Enable interrupts */
407 write_short_reg(devrec, REG_INTCON, val);
412 static void mrf24j40_stop(struct ieee802154_dev *dev)
414 struct mrf24j40 *devrec = dev->priv;
417 dev_dbg(printdev(devrec), "stop\n");
419 ret = read_short_reg(devrec, REG_INTCON, &val);
422 val |= 0x1|0x8; /* Set TXNIE and RXIE. Disable Interrupts */
423 write_short_reg(devrec, REG_INTCON, val);
428 static int mrf24j40_set_channel(struct ieee802154_dev *dev,
429 int page, int channel)
431 struct mrf24j40 *devrec = dev->priv;
435 dev_dbg(printdev(devrec), "Set Channel %d\n", channel);
438 WARN_ON(channel < MRF24J40_CHAN_MIN);
439 WARN_ON(channel > MRF24J40_CHAN_MAX);
441 /* Set Channel TODO */
442 val = (channel-11) << 4 | 0x03;
443 write_long_reg(devrec, REG_RFCON0, val);
446 ret = read_short_reg(devrec, REG_RFCTL, &val);
450 write_short_reg(devrec, REG_RFCTL, val);
452 write_short_reg(devrec, REG_RFCTL, val);
454 udelay(SET_CHANNEL_DELAY_US); /* per datasheet */
459 static int mrf24j40_filter(struct ieee802154_dev *dev,
460 struct ieee802154_hw_addr_filt *filt,
461 unsigned long changed)
463 struct mrf24j40 *devrec = dev->priv;
465 dev_dbg(printdev(devrec), "filter\n");
467 if (changed & IEEE802515_AFILT_SADDR_CHANGED) {
470 addrh = filt->short_addr >> 8 & 0xff;
471 addrl = filt->short_addr & 0xff;
473 write_short_reg(devrec, REG_SADRH, addrh);
474 write_short_reg(devrec, REG_SADRL, addrl);
475 dev_dbg(printdev(devrec),
476 "Set short addr to %04hx\n", filt->short_addr);
479 if (changed & IEEE802515_AFILT_IEEEADDR_CHANGED) {
482 for (i = 0; i < 8; i++)
483 write_short_reg(devrec, REG_EADR0+i,
484 filt->ieee_addr[7-i]);
487 printk(KERN_DEBUG "Set long addr to: ");
488 for (i = 0; i < 8; i++)
489 printk("%02hhx ", filt->ieee_addr[i]);
490 printk(KERN_DEBUG "\n");
494 if (changed & IEEE802515_AFILT_PANID_CHANGED) {
497 panidh = filt->pan_id >> 8 & 0xff;
498 panidl = filt->pan_id & 0xff;
499 write_short_reg(devrec, REG_PANIDH, panidh);
500 write_short_reg(devrec, REG_PANIDL, panidl);
502 dev_dbg(printdev(devrec), "Set PANID to %04hx\n", filt->pan_id);
505 if (changed & IEEE802515_AFILT_PANC_CHANGED) {
506 /* Pan Coordinator */
510 ret = read_short_reg(devrec, REG_RXMCR, &val);
517 write_short_reg(devrec, REG_RXMCR, val);
519 /* REG_SLOTTED is maintained as default (unslotted/CSMA-CA).
520 * REG_ORDER is maintained as default (no beacon/superframe).
523 dev_dbg(printdev(devrec), "Set Pan Coord to %s\n",
524 filt->pan_coord ? "on" : "off");
530 static int mrf24j40_handle_rx(struct mrf24j40 *devrec)
532 u8 len = RX_FIFO_SIZE;
538 /* Turn off reception of packets off the air. This prevents the
539 * device from overwriting the buffer while we're reading it. */
540 ret = read_short_reg(devrec, REG_BBREG1, &val);
543 val |= 4; /* SET RXDECINV */
544 write_short_reg(devrec, REG_BBREG1, val);
546 skb = alloc_skb(len, GFP_KERNEL);
552 ret = mrf24j40_read_rx_buf(devrec, skb_put(skb, len), &len, &lqi);
554 dev_err(printdev(devrec), "Failure reading RX FIFO\n");
560 /* Cut off the checksum */
561 skb_trim(skb, len-2);
563 /* TODO: Other drivers call ieee20154_rx_irqsafe() here (eg: cc2040,
564 * also from a workqueue). I think irqsafe is not necessary here.
565 * Can someone confirm? */
566 ieee802154_rx_irqsafe(devrec->dev, skb, lqi);
568 dev_dbg(printdev(devrec), "RX Handled\n");
571 /* Turn back on reception of packets off the air. */
572 ret = read_short_reg(devrec, REG_BBREG1, &val);
575 val &= ~0x4; /* Clear RXDECINV */
576 write_short_reg(devrec, REG_BBREG1, val);
581 static struct ieee802154_ops mrf24j40_ops = {
582 .owner = THIS_MODULE,
585 .start = mrf24j40_start,
586 .stop = mrf24j40_stop,
587 .set_channel = mrf24j40_set_channel,
588 .set_hw_addr_filt = mrf24j40_filter,
591 static irqreturn_t mrf24j40_isr(int irq, void *data)
593 struct mrf24j40 *devrec = data;
595 disable_irq_nosync(irq);
597 schedule_work(&devrec->irqwork);
602 static void mrf24j40_isrwork(struct work_struct *work)
604 struct mrf24j40 *devrec = container_of(work, struct mrf24j40, irqwork);
608 /* Read the interrupt status */
609 ret = read_short_reg(devrec, REG_INTSTAT, &intstat);
613 /* Check for TX complete */
615 complete(&devrec->tx_complete);
619 mrf24j40_handle_rx(devrec);
622 enable_irq(devrec->spi->irq);
625 static int mrf24j40_probe(struct spi_device *spi)
629 struct mrf24j40 *devrec;
630 struct pinctrl *pinctrl;
632 printk(KERN_INFO "mrf24j40: probe(). IRQ: %d\n", spi->irq);
634 devrec = kzalloc(sizeof(struct mrf24j40), GFP_KERNEL);
637 devrec->buf = kzalloc(3, GFP_KERNEL);
641 pinctrl = devm_pinctrl_get_select_default(&spi->dev);
644 "pinctrl pins are not configured from the driver");
646 spi->mode = SPI_MODE_0; /* TODO: Is this appropriate for right here? */
647 if (spi->max_speed_hz > MAX_SPI_SPEED_HZ)
648 spi->max_speed_hz = MAX_SPI_SPEED_HZ;
650 mutex_init(&devrec->buffer_mutex);
651 init_completion(&devrec->tx_complete);
652 INIT_WORK(&devrec->irqwork, mrf24j40_isrwork);
654 spi_set_drvdata(spi, devrec);
656 /* Register with the 802154 subsystem */
658 devrec->dev = ieee802154_alloc_device(0, &mrf24j40_ops);
662 devrec->dev->priv = devrec;
663 devrec->dev->parent = &devrec->spi->dev;
664 devrec->dev->phy->channels_supported[0] = CHANNEL_MASK;
665 devrec->dev->flags = IEEE802154_HW_OMIT_CKSUM|IEEE802154_HW_AACK;
667 dev_dbg(printdev(devrec), "registered mrf24j40\n");
668 ret = ieee802154_register_device(devrec->dev);
670 goto err_register_device;
672 /* Initialize the device.
673 From datasheet section 3.2: Initialization. */
674 write_short_reg(devrec, REG_SOFTRST, 0x07);
675 write_short_reg(devrec, REG_PACON2, 0x98);
676 write_short_reg(devrec, REG_TXSTBL, 0x95);
677 write_long_reg(devrec, REG_RFCON0, 0x03);
678 write_long_reg(devrec, REG_RFCON1, 0x01);
679 write_long_reg(devrec, REG_RFCON2, 0x80);
680 write_long_reg(devrec, REG_RFCON6, 0x90);
681 write_long_reg(devrec, REG_RFCON7, 0x80);
682 write_long_reg(devrec, REG_RFCON8, 0x10);
683 write_long_reg(devrec, REG_SLPCON1, 0x21);
684 write_short_reg(devrec, REG_BBREG2, 0x80);
685 write_short_reg(devrec, REG_CCAEDTH, 0x60);
686 write_short_reg(devrec, REG_BBREG6, 0x40);
687 write_short_reg(devrec, REG_RFCTL, 0x04);
688 write_short_reg(devrec, REG_RFCTL, 0x0);
691 /* Set RX Mode. RXMCR<1:0>: 0x0 normal, 0x1 promisc, 0x2 error */
692 ret = read_short_reg(devrec, REG_RXMCR, &val);
695 val &= ~0x3; /* Clear RX mode (normal) */
696 write_short_reg(devrec, REG_RXMCR, val);
698 ret = request_irq(spi->irq,
700 IRQF_TRIGGER_FALLING,
705 dev_err(printdev(devrec), "Unable to get IRQ");
713 ieee802154_unregister_device(devrec->dev);
715 ieee802154_free_device(devrec->dev);
724 static int mrf24j40_remove(struct spi_device *spi)
726 struct mrf24j40 *devrec = spi_get_drvdata(spi);
728 dev_dbg(printdev(devrec), "remove\n");
730 free_irq(spi->irq, devrec);
731 flush_work(&devrec->irqwork); /* TODO: Is this the right call? */
732 ieee802154_unregister_device(devrec->dev);
733 ieee802154_free_device(devrec->dev);
734 /* TODO: Will ieee802154_free_device() wait until ->xmit() is
737 /* Clean up the SPI stuff. */
738 spi_set_drvdata(spi, NULL);
744 static const struct spi_device_id mrf24j40_ids[] = {
749 MODULE_DEVICE_TABLE(spi, mrf24j40_ids);
751 static struct spi_driver mrf24j40_driver = {
754 .bus = &spi_bus_type,
755 .owner = THIS_MODULE,
757 .id_table = mrf24j40_ids,
758 .probe = mrf24j40_probe,
759 .remove = mrf24j40_remove,
762 module_spi_driver(mrf24j40_driver);
764 MODULE_LICENSE("GPL");
765 MODULE_AUTHOR("Alan Ott");
766 MODULE_DESCRIPTION("MRF24J40 SPI 802.15.4 Controller Driver");