2 * Driver for Microchip MRF24J40 802.15.4 Wireless-PAN Networking controller
4 * Copyright (C) 2012 Alan Ott <alan@signal11.us>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/spi/spi.h>
19 #include <linux/interrupt.h>
20 #include <linux/module.h>
21 #include <linux/regmap.h>
22 #include <linux/ieee802154.h>
23 #include <net/cfg802154.h>
24 #include <net/mac802154.h>
26 /* MRF24J40 Short Address Registers */
27 #define REG_RXMCR 0x00 /* Receive MAC control */
28 #define REG_PANIDL 0x01 /* PAN ID (low) */
29 #define REG_PANIDH 0x02 /* PAN ID (high) */
30 #define REG_SADRL 0x03 /* Short address (low) */
31 #define REG_SADRH 0x04 /* Short address (high) */
32 #define REG_EADR0 0x05 /* Long address (low) (high is EADR7) */
33 #define REG_EADR1 0x06
34 #define REG_EADR2 0x07
35 #define REG_EADR3 0x08
36 #define REG_EADR4 0x09
37 #define REG_EADR5 0x0A
38 #define REG_EADR6 0x0B
39 #define REG_EADR7 0x0C
40 #define REG_RXFLUSH 0x0D
41 #define REG_ORDER 0x10
42 #define REG_TXMCR 0x11 /* Transmit MAC control */
43 #define REG_ACKTMOUT 0x12
44 #define REG_ESLOTG1 0x13
45 #define REG_SYMTICKL 0x14
46 #define REG_SYMTICKH 0x15
47 #define REG_PACON0 0x16 /* Power Amplifier Control */
48 #define REG_PACON1 0x17 /* Power Amplifier Control */
49 #define REG_PACON2 0x18 /* Power Amplifier Control */
50 #define REG_TXBCON0 0x1A
51 #define REG_TXNCON 0x1B /* Transmit Normal FIFO Control */
52 #define REG_TXG1CON 0x1C
53 #define REG_TXG2CON 0x1D
54 #define REG_ESLOTG23 0x1E
55 #define REG_ESLOTG45 0x1F
56 #define REG_ESLOTG67 0x20
57 #define REG_TXPEND 0x21
58 #define REG_WAKECON 0x22
59 #define REG_FROMOFFSET 0x23
60 #define REG_TXSTAT 0x24 /* TX MAC Status Register */
61 #define REG_TXBCON1 0x25
62 #define REG_GATECLK 0x26
63 #define REG_TXTIME 0x27
64 #define REG_HSYMTMRL 0x28
65 #define REG_HSYMTMRH 0x29
66 #define REG_SOFTRST 0x2A /* Soft Reset */
67 #define REG_SECCON0 0x2C
68 #define REG_SECCON1 0x2D
69 #define REG_TXSTBL 0x2E /* TX Stabilization */
71 #define REG_INTSTAT 0x31 /* Interrupt Status */
72 #define REG_INTCON 0x32 /* Interrupt Control */
73 #define REG_GPIO 0x33 /* GPIO */
74 #define REG_TRISGPIO 0x34 /* GPIO direction */
75 #define REG_SLPACK 0x35
76 #define REG_RFCTL 0x36 /* RF Control Mode Register */
77 #define REG_SECCR2 0x37
78 #define REG_BBREG0 0x38
79 #define REG_BBREG1 0x39 /* Baseband Registers */
80 #define REG_BBREG2 0x3A /* */
81 #define REG_BBREG3 0x3B
82 #define REG_BBREG4 0x3C
83 #define REG_BBREG6 0x3E /* */
84 #define REG_CCAEDTH 0x3F /* Energy Detection Threshold */
86 /* MRF24J40 Long Address Registers */
87 #define REG_RFCON0 0x200 /* RF Control Registers */
88 #define REG_RFCON1 0x201
89 #define REG_RFCON2 0x202
90 #define REG_RFCON3 0x203
91 #define REG_RFCON5 0x205
92 #define REG_RFCON6 0x206
93 #define REG_RFCON7 0x207
94 #define REG_RFCON8 0x208
95 #define REG_SLPCAL0 0x209
96 #define REG_SLPCAL1 0x20A
97 #define REG_SLPCAL2 0x20B
98 #define REG_RFSTATE 0x20F
99 #define REG_RSSI 0x210
100 #define REG_SLPCON0 0x211 /* Sleep Clock Control Registers */
101 #define REG_SLPCON1 0x220
102 #define REG_WAKETIMEL 0x222 /* Wake-up Time Match Value Low */
103 #define REG_WAKETIMEH 0x223 /* Wake-up Time Match Value High */
104 #define REG_REMCNTL 0x224
105 #define REG_REMCNTH 0x225
106 #define REG_MAINCNT0 0x226
107 #define REG_MAINCNT1 0x227
108 #define REG_MAINCNT2 0x228
109 #define REG_MAINCNT3 0x229
110 #define REG_TESTMODE 0x22F /* Test mode */
111 #define REG_ASSOEAR0 0x230
112 #define REG_ASSOEAR1 0x231
113 #define REG_ASSOEAR2 0x232
114 #define REG_ASSOEAR3 0x233
115 #define REG_ASSOEAR4 0x234
116 #define REG_ASSOEAR5 0x235
117 #define REG_ASSOEAR6 0x236
118 #define REG_ASSOEAR7 0x237
119 #define REG_ASSOSAR0 0x238
120 #define REG_ASSOSAR1 0x239
121 #define REG_UNONCE0 0x240
122 #define REG_UNONCE1 0x241
123 #define REG_UNONCE2 0x242
124 #define REG_UNONCE3 0x243
125 #define REG_UNONCE4 0x244
126 #define REG_UNONCE5 0x245
127 #define REG_UNONCE6 0x246
128 #define REG_UNONCE7 0x247
129 #define REG_UNONCE8 0x248
130 #define REG_UNONCE9 0x249
131 #define REG_UNONCE10 0x24A
132 #define REG_UNONCE11 0x24B
133 #define REG_UNONCE12 0x24C
134 #define REG_RX_FIFO 0x300 /* Receive FIFO */
136 /* Device configuration: Only channels 11-26 on page 0 are supported. */
137 #define MRF24J40_CHAN_MIN 11
138 #define MRF24J40_CHAN_MAX 26
139 #define CHANNEL_MASK (((u32)1 << (MRF24J40_CHAN_MAX + 1)) \
140 - ((u32)1 << MRF24J40_CHAN_MIN))
142 #define TX_FIFO_SIZE 128 /* From datasheet */
143 #define RX_FIFO_SIZE 144 /* From datasheet */
144 #define SET_CHANNEL_DELAY_US 192 /* From datasheet */
146 enum mrf24j40_modules { MRF24J40, MRF24J40MA, MRF24J40MC };
148 /* Device Private Data */
150 struct spi_device *spi;
151 struct ieee802154_hw *hw;
153 struct regmap *regmap_short;
154 struct regmap *regmap_long;
156 /* for writing txfifo */
157 struct spi_message tx_msg;
159 struct spi_transfer tx_hdr_trx;
161 struct spi_transfer tx_len_trx;
162 struct spi_transfer tx_buf_trx;
163 struct sk_buff *tx_skb;
165 /* post transmit message to send frame out */
166 struct spi_message tx_post_msg;
168 struct spi_transfer tx_post_trx;
170 /* for protect/unprotect/read length rxfifo */
171 struct spi_message rx_msg;
173 struct spi_transfer rx_trx;
175 /* receive handling */
176 struct spi_message rx_buf_msg;
178 struct spi_transfer rx_addr_trx;
180 struct spi_transfer rx_lqi_trx;
181 u8 rx_fifo_buf[RX_FIFO_SIZE];
182 struct spi_transfer rx_fifo_buf_trx;
184 /* isr handling for reading intstat */
185 struct spi_message irq_msg;
187 struct spi_transfer irq_trx;
190 /* regmap information for short address register access */
191 #define MRF24J40_SHORT_WRITE 0x01
192 #define MRF24J40_SHORT_READ 0x00
193 #define MRF24J40_SHORT_NUMREGS 0x3F
195 /* regmap information for long address register access */
196 #define MRF24J40_LONG_ACCESS 0x80
197 #define MRF24J40_LONG_NUMREGS 0x38F
199 /* Read/Write SPI Commands for Short and Long Address registers. */
200 #define MRF24J40_READSHORT(reg) ((reg) << 1)
201 #define MRF24J40_WRITESHORT(reg) ((reg) << 1 | 1)
202 #define MRF24J40_READLONG(reg) (1 << 15 | (reg) << 5)
203 #define MRF24J40_WRITELONG(reg) (1 << 15 | (reg) << 5 | 1 << 4)
205 /* The datasheet indicates the theoretical maximum for SCK to be 10MHz */
206 #define MAX_SPI_SPEED_HZ 10000000
208 #define printdev(X) (&X->spi->dev)
211 mrf24j40_short_reg_writeable(struct device *dev, unsigned int reg)
276 mrf24j40_short_reg_readable(struct device *dev, unsigned int reg)
280 /* all writeable are also readable */
281 rc = mrf24j40_short_reg_writeable(dev, reg);
296 mrf24j40_short_reg_volatile(struct device *dev, unsigned int reg)
298 /* can be changed during runtime */
315 /* use them in spi_async and regmap so it's volatile */
324 mrf24j40_short_reg_precious(struct device *dev, unsigned int reg)
326 /* don't clear irq line on read */
335 static const struct regmap_config mrf24j40_short_regmap = {
336 .name = "mrf24j40_short",
340 .write_flag_mask = MRF24J40_SHORT_WRITE,
341 .read_flag_mask = MRF24J40_SHORT_READ,
342 .cache_type = REGCACHE_RBTREE,
343 .max_register = MRF24J40_SHORT_NUMREGS,
344 .writeable_reg = mrf24j40_short_reg_writeable,
345 .readable_reg = mrf24j40_short_reg_readable,
346 .volatile_reg = mrf24j40_short_reg_volatile,
347 .precious_reg = mrf24j40_short_reg_precious,
351 mrf24j40_long_reg_writeable(struct device *dev, unsigned int reg)
404 mrf24j40_long_reg_readable(struct device *dev, unsigned int reg)
408 /* all writeable are also readable */
409 rc = mrf24j40_long_reg_writeable(dev, reg);
426 mrf24j40_long_reg_volatile(struct device *dev, unsigned int reg)
428 /* can be changed during runtime */
442 static const struct regmap_config mrf24j40_long_regmap = {
443 .name = "mrf24j40_long",
447 .write_flag_mask = MRF24J40_LONG_ACCESS,
448 .read_flag_mask = MRF24J40_LONG_ACCESS,
449 .cache_type = REGCACHE_RBTREE,
450 .max_register = MRF24J40_LONG_NUMREGS,
451 .writeable_reg = mrf24j40_long_reg_writeable,
452 .readable_reg = mrf24j40_long_reg_readable,
453 .volatile_reg = mrf24j40_long_reg_volatile,
456 static int mrf24j40_long_regmap_write(void *context, const void *data,
459 struct spi_device *spi = context;
465 /* regmap supports read/write mask only in frist byte
466 * long write access need to set the 12th bit, so we
467 * make special handling for write.
469 memcpy(buf, data, count);
472 return spi_write(spi, buf, count);
476 mrf24j40_long_regmap_read(void *context, const void *reg, size_t reg_size,
477 void *val, size_t val_size)
479 struct spi_device *spi = context;
481 return spi_write_then_read(spi, reg, reg_size, val, val_size);
484 static const struct regmap_bus mrf24j40_long_regmap_bus = {
485 .write = mrf24j40_long_regmap_write,
486 .read = mrf24j40_long_regmap_read,
487 .reg_format_endian_default = REGMAP_ENDIAN_BIG,
488 .val_format_endian_default = REGMAP_ENDIAN_BIG,
491 static void write_tx_buf_complete(void *context)
493 struct mrf24j40 *devrec = context;
494 __le16 fc = ieee802154_get_fc_from_skb(devrec->tx_skb);
498 if (ieee802154_is_ackreq(fc))
501 devrec->tx_post_msg.complete = NULL;
502 devrec->tx_post_buf[0] = MRF24J40_WRITESHORT(REG_TXNCON);
503 devrec->tx_post_buf[1] = val;
505 ret = spi_async(devrec->spi, &devrec->tx_post_msg);
507 dev_err(printdev(devrec), "SPI write Failed for transmit buf\n");
510 /* This function relies on an undocumented write method. Once a write command
511 and address is set, as many bytes of data as desired can be clocked into
512 the device. The datasheet only shows setting one byte at a time. */
513 static int write_tx_buf(struct mrf24j40 *devrec, u16 reg,
514 const u8 *data, size_t length)
519 /* Range check the length. 2 bytes are used for the length fields.*/
520 if (length > TX_FIFO_SIZE-2) {
521 dev_err(printdev(devrec), "write_tx_buf() was passed too large a buffer. Performing short write.\n");
522 length = TX_FIFO_SIZE-2;
525 cmd = MRF24J40_WRITELONG(reg);
526 devrec->tx_hdr_buf[0] = cmd >> 8 & 0xff;
527 devrec->tx_hdr_buf[1] = cmd & 0xff;
528 devrec->tx_len_buf[0] = 0x0; /* Header Length. Set to 0 for now. TODO */
529 devrec->tx_len_buf[1] = length; /* Total length */
530 devrec->tx_buf_trx.tx_buf = data;
531 devrec->tx_buf_trx.len = length;
533 ret = spi_async(devrec->spi, &devrec->tx_msg);
535 dev_err(printdev(devrec), "SPI write Failed for TX buf\n");
540 static int mrf24j40_tx(struct ieee802154_hw *hw, struct sk_buff *skb)
542 struct mrf24j40 *devrec = hw->priv;
544 dev_dbg(printdev(devrec), "tx packet of %d bytes\n", skb->len);
545 devrec->tx_skb = skb;
547 return write_tx_buf(devrec, 0x000, skb->data, skb->len);
550 static int mrf24j40_ed(struct ieee802154_hw *hw, u8 *level)
553 pr_warn("mrf24j40: ed not implemented\n");
558 static int mrf24j40_start(struct ieee802154_hw *hw)
560 struct mrf24j40 *devrec = hw->priv;
562 dev_dbg(printdev(devrec), "start\n");
564 /* Clear TXNIE and RXIE. Enable interrupts */
565 return regmap_update_bits(devrec->regmap_short, REG_INTCON,
569 static void mrf24j40_stop(struct ieee802154_hw *hw)
571 struct mrf24j40 *devrec = hw->priv;
573 dev_dbg(printdev(devrec), "stop\n");
575 /* Set TXNIE and RXIE. Disable Interrupts */
576 regmap_update_bits(devrec->regmap_short, REG_INTCON, 0x01 | 0x08,
580 static int mrf24j40_set_channel(struct ieee802154_hw *hw, u8 page, u8 channel)
582 struct mrf24j40 *devrec = hw->priv;
586 dev_dbg(printdev(devrec), "Set Channel %d\n", channel);
589 WARN_ON(channel < MRF24J40_CHAN_MIN);
590 WARN_ON(channel > MRF24J40_CHAN_MAX);
592 /* Set Channel TODO */
593 val = (channel-11) << 4 | 0x03;
594 ret = regmap_update_bits(devrec->regmap_long, REG_RFCON0, 0xf0, val);
599 ret = regmap_update_bits(devrec->regmap_short, REG_RFCTL, 0x04, 0x04);
603 ret = regmap_update_bits(devrec->regmap_short, REG_RFCTL, 0x04, 0x00);
605 udelay(SET_CHANNEL_DELAY_US); /* per datasheet */
610 static int mrf24j40_filter(struct ieee802154_hw *hw,
611 struct ieee802154_hw_addr_filt *filt,
612 unsigned long changed)
614 struct mrf24j40 *devrec = hw->priv;
616 dev_dbg(printdev(devrec), "filter\n");
618 if (changed & IEEE802154_AFILT_SADDR_CHANGED) {
622 addrh = le16_to_cpu(filt->short_addr) >> 8 & 0xff;
623 addrl = le16_to_cpu(filt->short_addr) & 0xff;
625 regmap_write(devrec->regmap_short, REG_SADRH, addrh);
626 regmap_write(devrec->regmap_short, REG_SADRL, addrl);
627 dev_dbg(printdev(devrec),
628 "Set short addr to %04hx\n", filt->short_addr);
631 if (changed & IEEE802154_AFILT_IEEEADDR_CHANGED) {
635 memcpy(addr, &filt->ieee_addr, 8);
636 for (i = 0; i < 8; i++)
637 regmap_write(devrec->regmap_short, REG_EADR0 + i,
641 pr_debug("Set long addr to: ");
642 for (i = 0; i < 8; i++)
643 pr_debug("%02hhx ", addr[7 - i]);
648 if (changed & IEEE802154_AFILT_PANID_CHANGED) {
652 panidh = le16_to_cpu(filt->pan_id) >> 8 & 0xff;
653 panidl = le16_to_cpu(filt->pan_id) & 0xff;
654 regmap_write(devrec->regmap_short, REG_PANIDH, panidh);
655 regmap_write(devrec->regmap_short, REG_PANIDL, panidl);
657 dev_dbg(printdev(devrec), "Set PANID to %04hx\n", filt->pan_id);
660 if (changed & IEEE802154_AFILT_PANC_CHANGED) {
661 /* Pan Coordinator */
669 ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR, 0x8,
674 /* REG_SLOTTED is maintained as default (unslotted/CSMA-CA).
675 * REG_ORDER is maintained as default (no beacon/superframe).
678 dev_dbg(printdev(devrec), "Set Pan Coord to %s\n",
679 filt->pan_coord ? "on" : "off");
685 static void mrf24j40_handle_rx_read_buf_unlock(struct mrf24j40 *devrec)
689 /* Turn back on reception of packets off the air. */
690 devrec->rx_msg.complete = NULL;
691 devrec->rx_buf[0] = MRF24J40_WRITESHORT(REG_BBREG1);
692 devrec->rx_buf[1] = 0x00; /* CLR RXDECINV */
693 ret = spi_async(devrec->spi, &devrec->rx_msg);
695 dev_err(printdev(devrec), "failed to unlock rx buffer\n");
698 static void mrf24j40_handle_rx_read_buf_complete(void *context)
700 struct mrf24j40 *devrec = context;
701 u8 len = devrec->rx_buf[2];
702 u8 rx_local_buf[RX_FIFO_SIZE];
705 memcpy(rx_local_buf, devrec->rx_fifo_buf, len);
706 mrf24j40_handle_rx_read_buf_unlock(devrec);
708 skb = dev_alloc_skb(IEEE802154_MTU);
710 dev_err(printdev(devrec), "failed to allocate skb\n");
714 memcpy(skb_put(skb, len), rx_local_buf, len);
715 ieee802154_rx_irqsafe(devrec->hw, skb, 0);
718 print_hex_dump(KERN_DEBUG, "mrf24j40 rx: ", DUMP_PREFIX_OFFSET, 16, 1,
719 rx_local_buf, len, 0);
720 pr_debug("mrf24j40 rx: lqi: %02hhx rssi: %02hhx\n",
721 devrec->rx_lqi_buf[0], devrec->rx_lqi_buf[1]);
725 static void mrf24j40_handle_rx_read_buf(void *context)
727 struct mrf24j40 *devrec = context;
731 /* if length is invalid read the full MTU */
732 if (!ieee802154_is_valid_psdu_len(devrec->rx_buf[2]))
733 devrec->rx_buf[2] = IEEE802154_MTU;
735 cmd = MRF24J40_READLONG(REG_RX_FIFO + 1);
736 devrec->rx_addr_buf[0] = cmd >> 8 & 0xff;
737 devrec->rx_addr_buf[1] = cmd & 0xff;
738 devrec->rx_fifo_buf_trx.len = devrec->rx_buf[2];
739 ret = spi_async(devrec->spi, &devrec->rx_buf_msg);
741 dev_err(printdev(devrec), "failed to read rx buffer\n");
742 mrf24j40_handle_rx_read_buf_unlock(devrec);
746 static void mrf24j40_handle_rx_read_len(void *context)
748 struct mrf24j40 *devrec = context;
752 /* read the length of received frame */
753 devrec->rx_msg.complete = mrf24j40_handle_rx_read_buf;
754 devrec->rx_trx.len = 3;
755 cmd = MRF24J40_READLONG(REG_RX_FIFO);
756 devrec->rx_buf[0] = cmd >> 8 & 0xff;
757 devrec->rx_buf[1] = cmd & 0xff;
759 ret = spi_async(devrec->spi, &devrec->rx_msg);
761 dev_err(printdev(devrec), "failed to read rx buffer length\n");
762 mrf24j40_handle_rx_read_buf_unlock(devrec);
766 static int mrf24j40_handle_rx(struct mrf24j40 *devrec)
768 /* Turn off reception of packets off the air. This prevents the
769 * device from overwriting the buffer while we're reading it.
771 devrec->rx_msg.complete = mrf24j40_handle_rx_read_len;
772 devrec->rx_trx.len = 2;
773 devrec->rx_buf[0] = MRF24J40_WRITESHORT(REG_BBREG1);
774 devrec->rx_buf[1] = 0x04; /* SET RXDECINV */
776 return spi_async(devrec->spi, &devrec->rx_msg);
780 mrf24j40_csma_params(struct ieee802154_hw *hw, u8 min_be, u8 max_be,
783 struct mrf24j40 *devrec = hw->priv;
791 return regmap_update_bits(devrec->regmap_short, REG_TXMCR, 0x1f, val);
794 static int mrf24j40_set_cca_mode(struct ieee802154_hw *hw,
795 const struct wpan_phy_cca *cca)
797 struct mrf24j40 *devrec = hw->priv;
800 /* mapping 802.15.4 to driver spec */
802 case NL802154_CCA_ENERGY:
805 case NL802154_CCA_CARRIER:
808 case NL802154_CCA_ENERGY_CARRIER:
810 case NL802154_CCA_OPT_ENERGY_CARRIER_AND:
821 return regmap_update_bits(devrec->regmap_short, REG_BBREG2, 0xc0,
825 static const struct ieee802154_ops mrf24j40_ops = {
826 .owner = THIS_MODULE,
827 .xmit_async = mrf24j40_tx,
829 .start = mrf24j40_start,
830 .stop = mrf24j40_stop,
831 .set_channel = mrf24j40_set_channel,
832 .set_hw_addr_filt = mrf24j40_filter,
833 .set_csma_params = mrf24j40_csma_params,
834 .set_cca_mode = mrf24j40_set_cca_mode,
837 static void mrf24j40_intstat_complete(void *context)
839 struct mrf24j40 *devrec = context;
840 u8 intstat = devrec->irq_buf[1];
842 enable_irq(devrec->spi->irq);
844 /* Check for TX complete */
846 ieee802154_xmit_complete(devrec->hw, devrec->tx_skb, false);
850 mrf24j40_handle_rx(devrec);
853 static irqreturn_t mrf24j40_isr(int irq, void *data)
855 struct mrf24j40 *devrec = data;
858 disable_irq_nosync(irq);
860 devrec->irq_buf[0] = MRF24J40_READSHORT(REG_INTSTAT);
861 /* Read the interrupt status */
862 ret = spi_async(devrec->spi, &devrec->irq_msg);
871 static int mrf24j40_hw_init(struct mrf24j40 *devrec)
875 /* Initialize the device.
876 From datasheet section 3.2: Initialization. */
877 ret = regmap_write(devrec->regmap_short, REG_SOFTRST, 0x07);
881 ret = regmap_write(devrec->regmap_short, REG_PACON2, 0x98);
885 ret = regmap_write(devrec->regmap_short, REG_TXSTBL, 0x95);
889 ret = regmap_write(devrec->regmap_long, REG_RFCON0, 0x03);
893 ret = regmap_write(devrec->regmap_long, REG_RFCON1, 0x01);
897 ret = regmap_write(devrec->regmap_long, REG_RFCON2, 0x80);
901 ret = regmap_write(devrec->regmap_long, REG_RFCON6, 0x90);
905 ret = regmap_write(devrec->regmap_long, REG_RFCON7, 0x80);
909 ret = regmap_write(devrec->regmap_long, REG_RFCON8, 0x10);
913 ret = regmap_write(devrec->regmap_long, REG_SLPCON1, 0x21);
917 ret = regmap_write(devrec->regmap_short, REG_BBREG2, 0x80);
921 ret = regmap_write(devrec->regmap_short, REG_CCAEDTH, 0x60);
925 ret = regmap_write(devrec->regmap_short, REG_BBREG6, 0x40);
929 ret = regmap_write(devrec->regmap_short, REG_RFCTL, 0x04);
933 ret = regmap_write(devrec->regmap_short, REG_RFCTL, 0x0);
939 /* Set RX Mode. RXMCR<1:0>: 0x0 normal, 0x1 promisc, 0x2 error */
940 ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR, 0x03, 0x00);
944 if (spi_get_device_id(devrec->spi)->driver_data == MRF24J40MC) {
945 /* Enable external amplifier.
946 * From MRF24J40MC datasheet section 1.3: Operation.
948 regmap_update_bits(devrec->regmap_long, REG_TESTMODE, 0x07,
951 /* Set GPIO3 as output. */
952 regmap_update_bits(devrec->regmap_short, REG_TRISGPIO, 0x08,
955 /* Set GPIO3 HIGH to enable U5 voltage regulator */
956 regmap_update_bits(devrec->regmap_short, REG_GPIO, 0x08, 0x08);
958 /* Reduce TX pwr to meet FCC requirements.
959 * From MRF24J40MC datasheet section 3.1.1
961 regmap_write(devrec->regmap_long, REG_RFCON3, 0x28);
971 mrf24j40_setup_tx_spi_messages(struct mrf24j40 *devrec)
973 spi_message_init(&devrec->tx_msg);
974 devrec->tx_msg.context = devrec;
975 devrec->tx_msg.complete = write_tx_buf_complete;
976 devrec->tx_hdr_trx.len = 2;
977 devrec->tx_hdr_trx.tx_buf = devrec->tx_hdr_buf;
978 spi_message_add_tail(&devrec->tx_hdr_trx, &devrec->tx_msg);
979 devrec->tx_len_trx.len = 2;
980 devrec->tx_len_trx.tx_buf = devrec->tx_len_buf;
981 spi_message_add_tail(&devrec->tx_len_trx, &devrec->tx_msg);
982 spi_message_add_tail(&devrec->tx_buf_trx, &devrec->tx_msg);
984 spi_message_init(&devrec->tx_post_msg);
985 devrec->tx_post_msg.context = devrec;
986 devrec->tx_post_trx.len = 2;
987 devrec->tx_post_trx.tx_buf = devrec->tx_post_buf;
988 spi_message_add_tail(&devrec->tx_post_trx, &devrec->tx_post_msg);
992 mrf24j40_setup_rx_spi_messages(struct mrf24j40 *devrec)
994 spi_message_init(&devrec->rx_msg);
995 devrec->rx_msg.context = devrec;
996 devrec->rx_trx.len = 2;
997 devrec->rx_trx.tx_buf = devrec->rx_buf;
998 devrec->rx_trx.rx_buf = devrec->rx_buf;
999 spi_message_add_tail(&devrec->rx_trx, &devrec->rx_msg);
1001 spi_message_init(&devrec->rx_buf_msg);
1002 devrec->rx_buf_msg.context = devrec;
1003 devrec->rx_buf_msg.complete = mrf24j40_handle_rx_read_buf_complete;
1004 devrec->rx_addr_trx.len = 2;
1005 devrec->rx_addr_trx.tx_buf = devrec->rx_addr_buf;
1006 spi_message_add_tail(&devrec->rx_addr_trx, &devrec->rx_buf_msg);
1007 devrec->rx_fifo_buf_trx.rx_buf = devrec->rx_fifo_buf;
1008 spi_message_add_tail(&devrec->rx_fifo_buf_trx, &devrec->rx_buf_msg);
1009 devrec->rx_lqi_trx.len = 2;
1010 devrec->rx_lqi_trx.rx_buf = devrec->rx_lqi_buf;
1011 spi_message_add_tail(&devrec->rx_lqi_trx, &devrec->rx_buf_msg);
1015 mrf24j40_setup_irq_spi_messages(struct mrf24j40 *devrec)
1017 spi_message_init(&devrec->irq_msg);
1018 devrec->irq_msg.context = devrec;
1019 devrec->irq_msg.complete = mrf24j40_intstat_complete;
1020 devrec->irq_trx.len = 2;
1021 devrec->irq_trx.tx_buf = devrec->irq_buf;
1022 devrec->irq_trx.rx_buf = devrec->irq_buf;
1023 spi_message_add_tail(&devrec->irq_trx, &devrec->irq_msg);
1026 static void mrf24j40_phy_setup(struct mrf24j40 *devrec)
1028 ieee802154_random_extended_addr(&devrec->hw->phy->perm_extended_addr);
1029 devrec->hw->phy->current_channel = 11;
1031 /* mrf24j40 supports max_minbe 0 - 3 */
1032 devrec->hw->phy->supported.max_minbe = 3;
1033 /* datasheet doesn't say anything about max_be, but we have min_be
1034 * So we assume the max_be default.
1036 devrec->hw->phy->supported.min_maxbe = 5;
1037 devrec->hw->phy->supported.max_maxbe = 5;
1039 devrec->hw->phy->cca.mode = NL802154_CCA_CARRIER;;
1040 devrec->hw->phy->supported.cca_modes = BIT(NL802154_CCA_ENERGY) |
1041 BIT(NL802154_CCA_CARRIER) |
1042 BIT(NL802154_CCA_ENERGY_CARRIER);
1043 devrec->hw->phy->supported.cca_opts = BIT(NL802154_CCA_OPT_ENERGY_CARRIER_AND);
1046 static int mrf24j40_probe(struct spi_device *spi)
1049 struct ieee802154_hw *hw;
1050 struct mrf24j40 *devrec;
1052 dev_info(&spi->dev, "probe(). IRQ: %d\n", spi->irq);
1054 /* Register with the 802154 subsystem */
1056 hw = ieee802154_alloc_hw(sizeof(*devrec), &mrf24j40_ops);
1062 spi_set_drvdata(spi, devrec);
1064 devrec->hw->parent = &spi->dev;
1065 devrec->hw->phy->supported.channels[0] = CHANNEL_MASK;
1066 devrec->hw->flags = IEEE802154_HW_TX_OMIT_CKSUM | IEEE802154_HW_AFILT |
1067 IEEE802154_HW_CSMA_PARAMS;
1069 devrec->hw->phy->flags = WPAN_PHY_FLAG_CCA_MODE;
1071 mrf24j40_setup_tx_spi_messages(devrec);
1072 mrf24j40_setup_rx_spi_messages(devrec);
1073 mrf24j40_setup_irq_spi_messages(devrec);
1075 devrec->regmap_short = devm_regmap_init_spi(spi,
1076 &mrf24j40_short_regmap);
1077 if (IS_ERR(devrec->regmap_short)) {
1078 ret = PTR_ERR(devrec->regmap_short);
1079 dev_err(&spi->dev, "Failed to allocate short register map: %d\n",
1081 goto err_register_device;
1084 devrec->regmap_long = devm_regmap_init(&spi->dev,
1085 &mrf24j40_long_regmap_bus,
1086 spi, &mrf24j40_long_regmap);
1087 if (IS_ERR(devrec->regmap_long)) {
1088 ret = PTR_ERR(devrec->regmap_long);
1089 dev_err(&spi->dev, "Failed to allocate long register map: %d\n",
1091 goto err_register_device;
1094 if (spi->max_speed_hz > MAX_SPI_SPEED_HZ) {
1095 dev_warn(&spi->dev, "spi clock above possible maximum: %d",
1100 ret = mrf24j40_hw_init(devrec);
1102 goto err_register_device;
1104 mrf24j40_phy_setup(devrec);
1106 ret = devm_request_irq(&spi->dev, spi->irq, mrf24j40_isr,
1107 IRQF_TRIGGER_LOW, dev_name(&spi->dev),
1110 dev_err(printdev(devrec), "Unable to get IRQ");
1111 goto err_register_device;
1114 dev_dbg(printdev(devrec), "registered mrf24j40\n");
1115 ret = ieee802154_register_hw(devrec->hw);
1117 goto err_register_device;
1121 err_register_device:
1122 ieee802154_free_hw(devrec->hw);
1127 static int mrf24j40_remove(struct spi_device *spi)
1129 struct mrf24j40 *devrec = spi_get_drvdata(spi);
1131 dev_dbg(printdev(devrec), "remove\n");
1133 ieee802154_unregister_hw(devrec->hw);
1134 ieee802154_free_hw(devrec->hw);
1135 /* TODO: Will ieee802154_free_device() wait until ->xmit() is
1141 static const struct of_device_id mrf24j40_of_match[] = {
1142 { .compatible = "microchip,mrf24j40", .data = (void *)MRF24J40 },
1143 { .compatible = "microchip,mrf24j40ma", .data = (void *)MRF24J40MA },
1144 { .compatible = "microchip,mrf24j40mc", .data = (void *)MRF24J40MC },
1147 MODULE_DEVICE_TABLE(of, mrf24j40_of_match);
1149 static const struct spi_device_id mrf24j40_ids[] = {
1150 { "mrf24j40", MRF24J40 },
1151 { "mrf24j40ma", MRF24J40MA },
1152 { "mrf24j40mc", MRF24J40MC },
1155 MODULE_DEVICE_TABLE(spi, mrf24j40_ids);
1157 static struct spi_driver mrf24j40_driver = {
1159 .of_match_table = of_match_ptr(mrf24j40_of_match),
1161 .owner = THIS_MODULE,
1163 .id_table = mrf24j40_ids,
1164 .probe = mrf24j40_probe,
1165 .remove = mrf24j40_remove,
1168 module_spi_driver(mrf24j40_driver);
1170 MODULE_LICENSE("GPL");
1171 MODULE_AUTHOR("Alan Ott");
1172 MODULE_DESCRIPTION("MRF24J40 SPI 802.15.4 Controller Driver");