drivers/net/igb/e1000_82575.c

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 /* e1000_82575
  29  * e1000_82576
  30  */
  31
  32 #include <linux/types.h>
  33 #include <linux/slab.h>
  34
  35 #include "e1000_mac.h"
  36 #include "e1000_82575.h"
  37
  38 static s32  igb_get_invariants_82575(struct e1000_hw *);
  39 static s32  igb_acquire_phy_82575(struct e1000_hw *);
  40 static void igb_release_phy_82575(struct e1000_hw *);
  41 static s32  igb_acquire_nvm_82575(struct e1000_hw *);
  42 static void igb_release_nvm_82575(struct e1000_hw *);
  43 static s32  igb_check_for_link_82575(struct e1000_hw *);
  44 static s32  igb_get_cfg_done_82575(struct e1000_hw *);
  45 static s32  igb_init_hw_82575(struct e1000_hw *);
  46 static s32  igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
  47 static s32  igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
  48 static void igb_rar_set_82575(struct e1000_hw *, u8 *, u32);
  49 static s32  igb_reset_hw_82575(struct e1000_hw *);
  50 static s32  igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
  51 static s32  igb_setup_copper_link_82575(struct e1000_hw *);
  52 static s32  igb_setup_fiber_serdes_link_82575(struct e1000_hw *);
  53 static s32  igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
  54 static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
  55 static s32  igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
  56 static s32  igb_configure_pcs_link_82575(struct e1000_hw *);
  57 static s32  igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
  58                                                  u16 *);
  59 static s32  igb_get_phy_id_82575(struct e1000_hw *);
  60 static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
  61 static bool igb_sgmii_active_82575(struct e1000_hw *);
  62 static s32  igb_reset_init_script_82575(struct e1000_hw *);
  63 static s32  igb_read_mac_addr_82575(struct e1000_hw *);
  64
  65
  66 struct e1000_dev_spec_82575 {
  67         bool sgmii_active;
  68 };
  69
  70 static s32 igb_get_invariants_82575(struct e1000_hw *hw)
  71 {
  72         struct e1000_phy_info *phy = &hw->phy;
  73         struct e1000_nvm_info *nvm = &hw->nvm;
  74         struct e1000_mac_info *mac = &hw->mac;
  75         struct e1000_dev_spec_82575 *dev_spec;
  76         u32 eecd;
  77         s32 ret_val;
  78         u16 size;
  79         u32 ctrl_ext = 0;
  80
  81         switch (hw->device_id) {
  82         case E1000_DEV_ID_82575EB_COPPER:
  83         case E1000_DEV_ID_82575EB_FIBER_SERDES:
  84         case E1000_DEV_ID_82575GB_QUAD_COPPER:
  85                 mac->type = e1000_82575;
  86                 break;
  87         default:
  88                 return -E1000_ERR_MAC_INIT;
  89                 break;
  90         }
  91
  92         /* MAC initialization */
  93         hw->dev_spec_size = sizeof(struct e1000_dev_spec_82575);
  94
  95         /* Device-specific structure allocation */
  96         hw->dev_spec = kzalloc(hw->dev_spec_size, GFP_KERNEL);
  97
  98         if (!hw->dev_spec)
  99                 return -ENOMEM;
 100
 101         dev_spec = (struct e1000_dev_spec_82575 *)hw->dev_spec;
 102
 103         /* Set media type */
 104         /*
 105          * The 82575 uses bits 22:23 for link mode. The mode can be changed
 106          * based on the EEPROM. We cannot rely upon device ID. There
 107          * is no distinguishable difference between fiber and internal
 108          * SerDes mode on the 82575. There can be an external PHY attached
 109          * on the SGMII interface. For this, we'll set sgmii_active to true.
 110          */
 111         phy->media_type = e1000_media_type_copper;
 112         dev_spec->sgmii_active = false;
 113
 114         ctrl_ext = rd32(E1000_CTRL_EXT);
 115         if ((ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) ==
 116             E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES) {
 117                 hw->phy.media_type = e1000_media_type_internal_serdes;
 118                 ctrl_ext |= E1000_CTRL_I2C_ENA;
 119         } else if (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII) {
 120                 dev_spec->sgmii_active = true;
 121                 ctrl_ext |= E1000_CTRL_I2C_ENA;
 122         } else {
 123                 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
 124         }
 125         wr32(E1000_CTRL_EXT, ctrl_ext);
 126
 127         /* Set mta register count */
 128         mac->mta_reg_count = 128;
 129         /* Set rar entry count */
 130         mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
 131         /* Set if part includes ASF firmware */
 132         mac->asf_firmware_present = true;
 133         /* Set if manageability features are enabled. */
 134         mac->arc_subsystem_valid =
 135                 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
 136                         ? true : false;
 137
 138         /* physical interface link setup */
 139         mac->ops.setup_physical_interface =
 140                 (hw->phy.media_type == e1000_media_type_copper)
 141                         ? igb_setup_copper_link_82575
 142                         : igb_setup_fiber_serdes_link_82575;
 143
 144         /* NVM initialization */
 145         eecd = rd32(E1000_EECD);
 146
 147         nvm->opcode_bits        = 8;
 148         nvm->delay_usec         = 1;
 149         switch (nvm->override) {
 150         case e1000_nvm_override_spi_large:
 151                 nvm->page_size    = 32;
 152                 nvm->address_bits = 16;
 153                 break;
 154         case e1000_nvm_override_spi_small:
 155                 nvm->page_size    = 8;
 156                 nvm->address_bits = 8;
 157                 break;
 158         default:
 159                 nvm->page_size    = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 160                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 161                 break;
 162         }
 163
 164         nvm->type = e1000_nvm_eeprom_spi;
 165
 166         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 167                      E1000_EECD_SIZE_EX_SHIFT);
 168
 169         /*
 170          * Added to a constant, "size" becomes the left-shift value
 171          * for setting word_size.
 172          */
 173         size += NVM_WORD_SIZE_BASE_SHIFT;
 174
 175         /* EEPROM access above 16k is unsupported */
 176         if (size > 14)
 177                 size = 14;
 178         nvm->word_size = 1 << size;
 179
 180         /* setup PHY parameters */
 181         if (phy->media_type != e1000_media_type_copper) {
 182                 phy->type = e1000_phy_none;
 183                 return 0;
 184         }
 185
 186         phy->autoneg_mask        = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 187         phy->reset_delay_us      = 100;
 188
 189         /* PHY function pointers */
 190         if (igb_sgmii_active_82575(hw)) {
 191                 phy->ops.reset_phy          = igb_phy_hw_reset_sgmii_82575;
 192                 phy->ops.read_phy_reg       = igb_read_phy_reg_sgmii_82575;
 193                 phy->ops.write_phy_reg      = igb_write_phy_reg_sgmii_82575;
 194         } else {
 195                 phy->ops.reset_phy          = igb_phy_hw_reset;
 196                 phy->ops.read_phy_reg       = igb_read_phy_reg_igp;
 197                 phy->ops.write_phy_reg      = igb_write_phy_reg_igp;
 198         }
 199
 200         /* Set phy->phy_addr and phy->id. */
 201         ret_val = igb_get_phy_id_82575(hw);
 202         if (ret_val)
 203                 return ret_val;
 204
 205         /* Verify phy id and set remaining function pointers */
 206         switch (phy->id) {
 207         case M88E1111_I_PHY_ID:
 208                 phy->type                   = e1000_phy_m88;
 209                 phy->ops.get_phy_info       = igb_get_phy_info_m88;
 210                 phy->ops.get_cable_length   = igb_get_cable_length_m88;
 211                 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
 212                 break;
 213         case IGP03E1000_E_PHY_ID:
 214                 phy->type                   = e1000_phy_igp_3;
 215                 phy->ops.get_phy_info       = igb_get_phy_info_igp;
 216                 phy->ops.get_cable_length   = igb_get_cable_length_igp_2;
 217                 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
 218                 phy->ops.set_d0_lplu_state  = igb_set_d0_lplu_state_82575;
 219                 phy->ops.set_d3_lplu_state  = igb_set_d3_lplu_state;
 220                 break;
 221         default:
 222                 return -E1000_ERR_PHY;
 223         }
 224
 225         return 0;
 226 }
 227
 228 /**
 229  *  e1000_acquire_phy_82575 - Acquire rights to access PHY
 230  *  @hw: pointer to the HW structure
 231  *
 232  *  Acquire access rights to the correct PHY.  This is a
 233  *  function pointer entry point called by the api module.
 234  **/
 235 static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
 236 {
 237         u16 mask;
 238
 239         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
 240
 241         return igb_acquire_swfw_sync_82575(hw, mask);
 242 }
 243
 244 /**
 245  *  e1000_release_phy_82575 - Release rights to access PHY
 246  *  @hw: pointer to the HW structure
 247  *
 248  *  A wrapper to release access rights to the correct PHY.  This is a
 249  *  function pointer entry point called by the api module.
 250  **/
 251 static void igb_release_phy_82575(struct e1000_hw *hw)
 252 {
 253         u16 mask;
 254
 255         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
 256         igb_release_swfw_sync_82575(hw, mask);
 257 }
 258
 259 /**
 260  *  e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
 261  *  @hw: pointer to the HW structure
 262  *  @offset: register offset to be read
 263  *  @data: pointer to the read data
 264  *
 265  *  Reads the PHY register at offset using the serial gigabit media independent
 266  *  interface and stores the retrieved information in data.
 267  **/
 268 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 269                                           u16 *data)
 270 {
 271         struct e1000_phy_info *phy = &hw->phy;
 272         u32 i, i2ccmd = 0;
 273
 274         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 275                 hw_dbg(hw, "PHY Address %u is out of range\n", offset);
 276                 return -E1000_ERR_PARAM;
 277         }
 278
 279         /*
 280          * Set up Op-code, Phy Address, and register address in the I2CCMD
 281          * register.  The MAC will take care of interfacing with the
 282          * PHY to retrieve the desired data.
 283          */
 284         i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
 285                   (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
 286                   (E1000_I2CCMD_OPCODE_READ));
 287
 288         wr32(E1000_I2CCMD, i2ccmd);
 289
 290         /* Poll the ready bit to see if the I2C read completed */
 291         for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
 292                 udelay(50);
 293                 i2ccmd = rd32(E1000_I2CCMD);
 294                 if (i2ccmd & E1000_I2CCMD_READY)
 295                         break;
 296         }
 297         if (!(i2ccmd & E1000_I2CCMD_READY)) {
 298                 hw_dbg(hw, "I2CCMD Read did not complete\n");
 299                 return -E1000_ERR_PHY;
 300         }
 301         if (i2ccmd & E1000_I2CCMD_ERROR) {
 302                 hw_dbg(hw, "I2CCMD Error bit set\n");
 303                 return -E1000_ERR_PHY;
 304         }
 305
 306         /* Need to byte-swap the 16-bit value. */
 307         *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
 308
 309         return 0;
 310 }
 311
 312 /**
 313  *  e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
 314  *  @hw: pointer to the HW structure
 315  *  @offset: register offset to write to
 316  *  @data: data to write at register offset
 317  *
 318  *  Writes the data to PHY register at the offset using the serial gigabit
 319  *  media independent interface.
 320  **/
 321 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 322                                            u16 data)
 323 {
 324         struct e1000_phy_info *phy = &hw->phy;
 325         u32 i, i2ccmd = 0;
 326         u16 phy_data_swapped;
 327
 328         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 329                 hw_dbg(hw, "PHY Address %d is out of range\n", offset);
 330                 return -E1000_ERR_PARAM;
 331         }
 332
 333         /* Swap the data bytes for the I2C interface */
 334         phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
 335
 336         /*
 337          * Set up Op-code, Phy Address, and register address in the I2CCMD
 338          * register.  The MAC will take care of interfacing with the
 339          * PHY to retrieve the desired data.
 340          */
 341         i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
 342                   (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
 343                   E1000_I2CCMD_OPCODE_WRITE |
 344                   phy_data_swapped);
 345
 346         wr32(E1000_I2CCMD, i2ccmd);
 347
 348         /* Poll the ready bit to see if the I2C read completed */
 349         for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
 350                 udelay(50);
 351                 i2ccmd = rd32(E1000_I2CCMD);
 352                 if (i2ccmd & E1000_I2CCMD_READY)
 353                         break;
 354         }
 355         if (!(i2ccmd & E1000_I2CCMD_READY)) {
 356                 hw_dbg(hw, "I2CCMD Write did not complete\n");
 357                 return -E1000_ERR_PHY;
 358         }
 359         if (i2ccmd & E1000_I2CCMD_ERROR) {
 360                 hw_dbg(hw, "I2CCMD Error bit set\n");
 361                 return -E1000_ERR_PHY;
 362         }
 363
 364         return 0;
 365 }
 366
 367 /**
 368  *  e1000_get_phy_id_82575 - Retreive PHY addr and id
 369  *  @hw: pointer to the HW structure
 370  *
 371  *  Retreives the PHY address and ID for both PHY's which do and do not use
 372  *  sgmi interface.
 373  **/
 374 static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
 375 {
 376         struct e1000_phy_info *phy = &hw->phy;
 377         s32  ret_val = 0;
 378         u16 phy_id;
 379
 380         /*
 381          * For SGMII PHYs, we try the list of possible addresses until
 382          * we find one that works.  For non-SGMII PHYs
 383          * (e.g. integrated copper PHYs), an address of 1 should
 384          * work.  The result of this function should mean phy->phy_addr
 385          * and phy->id are set correctly.
 386          */
 387         if (!(igb_sgmii_active_82575(hw))) {
 388                 phy->addr = 1;
 389                 ret_val = igb_get_phy_id(hw);
 390                 goto out;
 391         }
 392
 393         /*
 394          * The address field in the I2CCMD register is 3 bits and 0 is invalid.
 395          * Therefore, we need to test 1-7
 396          */
 397         for (phy->addr = 1; phy->addr < 8; phy->addr++) {
 398                 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
 399                 if (ret_val == 0) {
 400                         hw_dbg(hw, "Vendor ID 0x%08X read at address %u\n",
 401                                   phy_id,
 402                                   phy->addr);
 403                         /*
 404                          * At the time of this writing, The M88 part is
 405                          * the only supported SGMII PHY product.
 406                          */
 407                         if (phy_id == M88_VENDOR)
 408                                 break;
 409                 } else {
 410                         hw_dbg(hw, "PHY address %u was unreadable\n",
 411                                   phy->addr);
 412                 }
 413         }
 414
 415         /* A valid PHY type couldn't be found. */
 416         if (phy->addr == 8) {
 417                 phy->addr = 0;
 418                 ret_val = -E1000_ERR_PHY;
 419                 goto out;
 420         }
 421
 422         ret_val = igb_get_phy_id(hw);
 423
 424 out:
 425         return ret_val;
 426 }
 427
 428 /**
 429  *  e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
 430  *  @hw: pointer to the HW structure
 431  *
 432  *  Resets the PHY using the serial gigabit media independent interface.
 433  **/
 434 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
 435 {
 436         s32 ret_val;
 437
 438         /*
 439          * This isn't a true "hard" reset, but is the only reset
 440          * available to us at this time.
 441          */
 442
 443         hw_dbg(hw, "Soft resetting SGMII attached PHY...\n");
 444
 445         /*
 446          * SFP documentation requires the following to configure the SPF module
 447          * to work on SGMII.  No further documentation is given.
 448          */
 449         ret_val = hw->phy.ops.write_phy_reg(hw, 0x1B, 0x8084);
 450         if (ret_val)
 451                 goto out;
 452
 453         ret_val = igb_phy_sw_reset(hw);
 454
 455 out:
 456         return ret_val;
 457 }
 458
 459 /**
 460  *  e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
 461  *  @hw: pointer to the HW structure
 462  *  @active: true to enable LPLU, false to disable
 463  *
 464  *  Sets the LPLU D0 state according to the active flag.  When
 465  *  activating LPLU this function also disables smart speed
 466  *  and vice versa.  LPLU will not be activated unless the
 467  *  device autonegotiation advertisement meets standards of
 468  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 469  *  This is a function pointer entry point only called by
 470  *  PHY setup routines.
 471  **/
 472 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
 473 {
 474         struct e1000_phy_info *phy = &hw->phy;
 475         s32 ret_val;
 476         u16 data;
 477
 478         ret_val = hw->phy.ops.read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 479                                            &data);
 480         if (ret_val)
 481                 goto out;
 482
 483         if (active) {
 484                 data |= IGP02E1000_PM_D0_LPLU;
 485                 ret_val = hw->phy.ops.write_phy_reg(hw,
 486                                               IGP02E1000_PHY_POWER_MGMT,
 487                                               data);
 488                 if (ret_val)
 489                         goto out;
 490
 491                 /* When LPLU is enabled, we should disable SmartSpeed */
 492                 ret_val = hw->phy.ops.read_phy_reg(hw,
 493                                              IGP01E1000_PHY_PORT_CONFIG,
 494                                              &data);
 495                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 496                 ret_val = hw->phy.ops.write_phy_reg(hw,
 497                                               IGP01E1000_PHY_PORT_CONFIG,
 498                                               data);
 499                 if (ret_val)
 500                         goto out;
 501         } else {
 502                 data &= ~IGP02E1000_PM_D0_LPLU;
 503                 ret_val = hw->phy.ops.write_phy_reg(hw,
 504                                               IGP02E1000_PHY_POWER_MGMT,
 505                                               data);
 506                 /*
 507                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 508                  * during Dx states where the power conservation is most
 509                  * important.  During driver activity we should enable
 510                  * SmartSpeed, so performance is maintained.
 511                  */
 512                 if (phy->smart_speed == e1000_smart_speed_on) {
 513                         ret_val = hw->phy.ops.read_phy_reg(hw,
 514                                                      IGP01E1000_PHY_PORT_CONFIG,
 515                                                      &data);
 516                         if (ret_val)
 517                                 goto out;
 518
 519                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 520                         ret_val = hw->phy.ops.write_phy_reg(hw,
 521                                                      IGP01E1000_PHY_PORT_CONFIG,
 522                                                      data);
 523                         if (ret_val)
 524                                 goto out;
 525                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 526                         ret_val = hw->phy.ops.read_phy_reg(hw,
 527                                                      IGP01E1000_PHY_PORT_CONFIG,
 528                                                      &data);
 529                         if (ret_val)
 530                                 goto out;
 531
 532                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 533                         ret_val = hw->phy.ops.write_phy_reg(hw,
 534                                                      IGP01E1000_PHY_PORT_CONFIG,
 535                                                      data);
 536                         if (ret_val)
 537                                 goto out;
 538                 }
 539         }
 540
 541 out:
 542         return ret_val;
 543 }
 544
 545 /**
 546  *  e1000_acquire_nvm_82575 - Request for access to EEPROM
 547  *  @hw: pointer to the HW structure
 548  *
 549  *  Acquire the necessary semaphores for exclussive access to the EEPROM.
 550  *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
 551  *  Return successful if access grant bit set, else clear the request for
 552  *  EEPROM access and return -E1000_ERR_NVM (-1).
 553  **/
 554 static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
 555 {
 556         s32 ret_val;
 557
 558         ret_val = igb_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
 559         if (ret_val)
 560                 goto out;
 561
 562         ret_val = igb_acquire_nvm(hw);
 563
 564         if (ret_val)
 565                 igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
 566
 567 out:
 568         return ret_val;
 569 }
 570
 571 /**
 572  *  e1000_release_nvm_82575 - Release exclusive access to EEPROM
 573  *  @hw: pointer to the HW structure
 574  *
 575  *  Stop any current commands to the EEPROM and clear the EEPROM request bit,
 576  *  then release the semaphores acquired.
 577  **/
 578 static void igb_release_nvm_82575(struct e1000_hw *hw)
 579 {
 580         igb_release_nvm(hw);
 581         igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
 582 }
 583
 584 /**
 585  *  e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
 586  *  @hw: pointer to the HW structure
 587  *  @mask: specifies which semaphore to acquire
 588  *
 589  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
 590  *  will also specify which port we're acquiring the lock for.
 591  **/
 592 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
 593 {
 594         u32 swfw_sync;
 595         u32 swmask = mask;
 596         u32 fwmask = mask << 16;
 597         s32 ret_val = 0;
 598         s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
 599
 600         while (i < timeout) {
 601                 if (igb_get_hw_semaphore(hw)) {
 602                         ret_val = -E1000_ERR_SWFW_SYNC;
 603                         goto out;
 604                 }
 605
 606                 swfw_sync = rd32(E1000_SW_FW_SYNC);
 607                 if (!(swfw_sync & (fwmask | swmask)))
 608                         break;
 609
 610                 /*
 611                  * Firmware currently using resource (fwmask)
 612                  * or other software thread using resource (swmask)
 613                  */
 614                 igb_put_hw_semaphore(hw);
 615                 mdelay(5);
 616                 i++;
 617         }
 618
 619         if (i == timeout) {
 620                 hw_dbg(hw, "Can't access resource, SW_FW_SYNC timeout.\n");
 621                 ret_val = -E1000_ERR_SWFW_SYNC;
 622                 goto out;
 623         }
 624
 625         swfw_sync |= swmask;
 626         wr32(E1000_SW_FW_SYNC, swfw_sync);
 627
 628         igb_put_hw_semaphore(hw);
 629
 630 out:
 631         return ret_val;
 632 }
 633
 634 /**
 635  *  e1000_release_swfw_sync_82575 - Release SW/FW semaphore
 636  *  @hw: pointer to the HW structure
 637  *  @mask: specifies which semaphore to acquire
 638  *
 639  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
 640  *  will also specify which port we're releasing the lock for.
 641  **/
 642 static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
 643 {
 644         u32 swfw_sync;
 645
 646         while (igb_get_hw_semaphore(hw) != 0);
 647         /* Empty */
 648
 649         swfw_sync = rd32(E1000_SW_FW_SYNC);
 650         swfw_sync &= ~mask;
 651         wr32(E1000_SW_FW_SYNC, swfw_sync);
 652
 653         igb_put_hw_semaphore(hw);
 654 }
 655
 656 /**
 657  *  e1000_get_cfg_done_82575 - Read config done bit
 658  *  @hw: pointer to the HW structure
 659  *
 660  *  Read the management control register for the config done bit for
 661  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
 662  *  to read the config done bit, so an error is *ONLY* logged and returns
 663  *  0.  If we were to return with error, EEPROM-less silicon
 664  *  would not be able to be reset or change link.
 665  **/
 666 static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
 667 {
 668         s32 timeout = PHY_CFG_TIMEOUT;
 669         s32 ret_val = 0;
 670         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
 671
 672         if (hw->bus.func == 1)
 673                 mask = E1000_NVM_CFG_DONE_PORT_1;
 674
 675         while (timeout) {
 676                 if (rd32(E1000_EEMNGCTL) & mask)
 677                         break;
 678                 msleep(1);
 679                 timeout--;
 680         }
 681         if (!timeout)
 682                 hw_dbg(hw, "MNG configuration cycle has not completed.\n");
 683
 684         /* If EEPROM is not marked present, init the PHY manually */
 685         if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
 686             (hw->phy.type == e1000_phy_igp_3))
 687                 igb_phy_init_script_igp3(hw);
 688
 689         return ret_val;
 690 }
 691
 692 /**
 693  *  e1000_check_for_link_82575 - Check for link
 694  *  @hw: pointer to the HW structure
 695  *
 696  *  If sgmii is enabled, then use the pcs register to determine link, otherwise
 697  *  use the generic interface for determining link.
 698  **/
 699 static s32 igb_check_for_link_82575(struct e1000_hw *hw)
 700 {
 701         s32 ret_val;
 702         u16 speed, duplex;
 703
 704         /* SGMII link check is done through the PCS register. */
 705         if ((hw->phy.media_type != e1000_media_type_copper) ||
 706             (igb_sgmii_active_82575(hw)))
 707                 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
 708                                                                &duplex);
 709         else
 710                 ret_val = igb_check_for_copper_link(hw);
 711
 712         return ret_val;
 713 }
 714
 715 /**
 716  *  e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
 717  *  @hw: pointer to the HW structure
 718  *  @speed: stores the current speed
 719  *  @duplex: stores the current duplex
 720  *
 721  *  Using the physical coding sub-layer (PCS), retreive the current speed and
 722  *  duplex, then store the values in the pointers provided.
 723  **/
 724 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
 725                                                 u16 *duplex)
 726 {
 727         struct e1000_mac_info *mac = &hw->mac;
 728         u32 pcs;
 729
 730         /* Set up defaults for the return values of this function */
 731         mac->serdes_has_link = false;
 732         *speed = 0;
 733         *duplex = 0;
 734
 735         /*
 736          * Read the PCS Status register for link state. For non-copper mode,
 737          * the status register is not accurate. The PCS status register is
 738          * used instead.
 739          */
 740         pcs = rd32(E1000_PCS_LSTAT);
 741
 742         /*
 743          * The link up bit determines when link is up on autoneg. The sync ok
 744          * gets set once both sides sync up and agree upon link. Stable link
 745          * can be determined by checking for both link up and link sync ok
 746          */
 747         if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
 748                 mac->serdes_has_link = true;
 749
 750                 /* Detect and store PCS speed */
 751                 if (pcs & E1000_PCS_LSTS_SPEED_1000) {
 752                         *speed = SPEED_1000;
 753                 } else if (pcs & E1000_PCS_LSTS_SPEED_100) {
 754                         *speed = SPEED_100;
 755                 } else {
 756                         *speed = SPEED_10;
 757                 }
 758
 759                 /* Detect and store PCS duplex */
 760                 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
 761                         *duplex = FULL_DUPLEX;
 762                 } else {
 763                         *duplex = HALF_DUPLEX;
 764                 }
 765         }
 766
 767         return 0;
 768 }
 769
 770 /**
 771  *  e1000_rar_set_82575 - Set receive address register
 772  *  @hw: pointer to the HW structure
 773  *  @addr: pointer to the receive address
 774  *  @index: receive address array register
 775  *
 776  *  Sets the receive address array register at index to the address passed
 777  *  in by addr.
 778  **/
 779 static void igb_rar_set_82575(struct e1000_hw *hw, u8 *addr, u32 index)
 780 {
 781         if (index < E1000_RAR_ENTRIES_82575)
 782                 igb_rar_set(hw, addr, index);
 783
 784         return;
 785 }
 786
 787 /**
 788  *  e1000_reset_hw_82575 - Reset hardware
 789  *  @hw: pointer to the HW structure
 790  *
 791  *  This resets the hardware into a known state.  This is a
 792  *  function pointer entry point called by the api module.
 793  **/
 794 static s32 igb_reset_hw_82575(struct e1000_hw *hw)
 795 {
 796         u32 ctrl, icr;
 797         s32 ret_val;
 798
 799         /*
 800          * Prevent the PCI-E bus from sticking if there is no TLP connection
 801          * on the last TLP read/write transaction when MAC is reset.
 802          */
 803         ret_val = igb_disable_pcie_master(hw);
 804         if (ret_val)
 805                 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
 806
 807         hw_dbg(hw, "Masking off all interrupts\n");
 808         wr32(E1000_IMC, 0xffffffff);
 809
 810         wr32(E1000_RCTL, 0);
 811         wr32(E1000_TCTL, E1000_TCTL_PSP);
 812         wrfl();
 813
 814         msleep(10);
 815
 816         ctrl = rd32(E1000_CTRL);
 817
 818         hw_dbg(hw, "Issuing a global reset to MAC\n");
 819         wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
 820
 821         ret_val = igb_get_auto_rd_done(hw);
 822         if (ret_val) {
 823                 /*
 824                  * When auto config read does not complete, do not
 825                  * return with an error. This can happen in situations
 826                  * where there is no eeprom and prevents getting link.
 827                  */
 828                 hw_dbg(hw, "Auto Read Done did not complete\n");
 829         }
 830
 831         /* If EEPROM is not present, run manual init scripts */
 832         if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
 833                 igb_reset_init_script_82575(hw);
 834
 835         /* Clear any pending interrupt events. */
 836         wr32(E1000_IMC, 0xffffffff);
 837         icr = rd32(E1000_ICR);
 838
 839         igb_check_alt_mac_addr(hw);
 840
 841         return ret_val;
 842 }
 843
 844 /**
 845  *  e1000_init_hw_82575 - Initialize hardware
 846  *  @hw: pointer to the HW structure
 847  *
 848  *  This inits the hardware readying it for operation.
 849  **/
 850 static s32 igb_init_hw_82575(struct e1000_hw *hw)
 851 {
 852         struct e1000_mac_info *mac = &hw->mac;
 853         s32 ret_val;
 854         u16 i, rar_count = mac->rar_entry_count;
 855
 856         /* Initialize identification LED */
 857         ret_val = igb_id_led_init(hw);
 858         if (ret_val) {
 859                 hw_dbg(hw, "Error initializing identification LED\n");
 860                 /* This is not fatal and we should not stop init due to this */
 861         }
 862
 863         /* Disabling VLAN filtering */
 864         hw_dbg(hw, "Initializing the IEEE VLAN\n");
 865         igb_clear_vfta(hw);
 866
 867         /* Setup the receive address */
 868         igb_init_rx_addrs(hw, rar_count);
 869         /* Zero out the Multicast HASH table */
 870         hw_dbg(hw, "Zeroing the MTA\n");
 871         for (i = 0; i < mac->mta_reg_count; i++)
 872                 array_wr32(E1000_MTA, i, 0);
 873
 874         /* Setup link and flow control */
 875         ret_val = igb_setup_link(hw);
 876
 877         /*
 878          * Clear all of the statistics registers (clear on read).  It is
 879          * important that we do this after we have tried to establish link
 880          * because the symbol error count will increment wildly if there
 881          * is no link.
 882          */
 883         igb_clear_hw_cntrs_82575(hw);
 884
 885         return ret_val;
 886 }
 887
 888 /**
 889  *  e1000_setup_copper_link_82575 - Configure copper link settings
 890  *  @hw: pointer to the HW structure
 891  *
 892  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
 893  *  for link, once link is established calls to configure collision distance
 894  *  and flow control are called.
 895  **/
 896 static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
 897 {
 898         u32 ctrl, led_ctrl;
 899         s32  ret_val;
 900         bool link;
 901
 902         ctrl = rd32(E1000_CTRL);
 903         ctrl |= E1000_CTRL_SLU;
 904         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
 905         wr32(E1000_CTRL, ctrl);
 906
 907         switch (hw->phy.type) {
 908         case e1000_phy_m88:
 909                 ret_val = igb_copper_link_setup_m88(hw);
 910                 break;
 911         case e1000_phy_igp_3:
 912                 ret_val = igb_copper_link_setup_igp(hw);
 913                 /* Setup activity LED */
 914                 led_ctrl = rd32(E1000_LEDCTL);
 915                 led_ctrl &= IGP_ACTIVITY_LED_MASK;
 916                 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
 917                 wr32(E1000_LEDCTL, led_ctrl);
 918                 break;
 919         default:
 920                 ret_val = -E1000_ERR_PHY;
 921                 break;
 922         }
 923
 924         if (ret_val)
 925                 goto out;
 926
 927         if (hw->mac.autoneg) {
 928                 /*
 929                  * Setup autoneg and flow control advertisement
 930                  * and perform autonegotiation.
 931                  */
 932                 ret_val = igb_copper_link_autoneg(hw);
 933                 if (ret_val)
 934                         goto out;
 935         } else {
 936                 /*
 937                  * PHY will be set to 10H, 10F, 100H or 100F
 938                  * depending on user settings.
 939                  */
 940                 hw_dbg(hw, "Forcing Speed and Duplex\n");
 941                 ret_val = igb_phy_force_speed_duplex(hw);
 942                 if (ret_val) {
 943                         hw_dbg(hw, "Error Forcing Speed and Duplex\n");
 944                         goto out;
 945                 }
 946         }
 947
 948         ret_val = igb_configure_pcs_link_82575(hw);
 949         if (ret_val)
 950                 goto out;
 951
 952         /*
 953          * Check link status. Wait up to 100 microseconds for link to become
 954          * valid.
 955          */
 956         ret_val = igb_phy_has_link(hw,
 957                                              COPPER_LINK_UP_LIMIT,
 958                                              10,
 959                                              &link);
 960         if (ret_val)
 961                 goto out;
 962
 963         if (link) {
 964                 hw_dbg(hw, "Valid link established!!!\n");
 965                 /* Config the MAC and PHY after link is up */
 966                 igb_config_collision_dist(hw);
 967                 ret_val = igb_config_fc_after_link_up(hw);
 968         } else {
 969                 hw_dbg(hw, "Unable to establish link!!!\n");
 970         }
 971
 972 out:
 973         return ret_val;
 974 }
 975
 976 /**
 977  *  e1000_setup_fiber_serdes_link_82575 - Setup link for fiber/serdes
 978  *  @hw: pointer to the HW structure
 979  *
 980  *  Configures speed and duplex for fiber and serdes links.
 981  **/
 982 static s32 igb_setup_fiber_serdes_link_82575(struct e1000_hw *hw)
 983 {
 984         u32 reg;
 985
 986         /*
 987          * On the 82575, SerDes loopback mode persists until it is
 988          * explicitly turned off or a power cycle is performed.  A read to
 989          * the register does not indicate its status.  Therefore, we ensure
 990          * loopback mode is disabled during initialization.
 991          */
 992         wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
 993
 994         /* Force link up, set 1gb, set both sw defined pins */
 995         reg = rd32(E1000_CTRL);
 996         reg |= E1000_CTRL_SLU |
 997                E1000_CTRL_SPD_1000 |
 998                E1000_CTRL_FRCSPD |
 999                E1000_CTRL_SWDPIN0 |
1000                E1000_CTRL_SWDPIN1;
1001         wr32(E1000_CTRL, reg);
1002
1003         /* Set switch control to serdes energy detect */
1004         reg = rd32(E1000_CONNSW);
1005         reg |= E1000_CONNSW_ENRGSRC;
1006         wr32(E1000_CONNSW, reg);
1007
1008         /*
1009          * New SerDes mode allows for forcing speed or autonegotiating speed
1010          * at 1gb. Autoneg should be default set by most drivers. This is the
1011          * mode that will be compatible with older link partners and switches.
1012          * However, both are supported by the hardware and some drivers/tools.
1013          */
1014         reg = rd32(E1000_PCS_LCTL);
1015
1016         reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1017                 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1018
1019         if (hw->mac.autoneg) {
1020                 /* Set PCS register for autoneg */
1021                 reg |= E1000_PCS_LCTL_FSV_1000 |      /* Force 1000    */
1022                        E1000_PCS_LCTL_FDV_FULL |      /* SerDes Full duplex */
1023                        E1000_PCS_LCTL_AN_ENABLE |     /* Enable Autoneg */
1024                        E1000_PCS_LCTL_AN_RESTART;     /* Restart autoneg */
1025                 hw_dbg(hw, "Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg);
1026         } else {
1027                 /* Set PCS register for forced speed */
1028                 reg |= E1000_PCS_LCTL_FLV_LINK_UP |   /* Force link up */
1029                        E1000_PCS_LCTL_FSV_1000 |      /* Force 1000    */
1030                        E1000_PCS_LCTL_FDV_FULL |      /* SerDes Full duplex */
1031                        E1000_PCS_LCTL_FSD |           /* Force Speed */
1032                        E1000_PCS_LCTL_FORCE_LINK;     /* Force Link */
1033                 hw_dbg(hw, "Configuring Forced Link; PCS_LCTL = 0x%08X\n", reg);
1034         }
1035         wr32(E1000_PCS_LCTL, reg);
1036
1037         return 0;
1038 }
1039
1040 /**
1041  *  e1000_configure_pcs_link_82575 - Configure PCS link
1042  *  @hw: pointer to the HW structure
1043  *
1044  *  Configure the physical coding sub-layer (PCS) link.  The PCS link is
1045  *  only used on copper connections where the serialized gigabit media
1046  *  independent interface (sgmii) is being used.  Configures the link
1047  *  for auto-negotiation or forces speed/duplex.
1048  **/
1049 static s32 igb_configure_pcs_link_82575(struct e1000_hw *hw)
1050 {
1051         struct e1000_mac_info *mac = &hw->mac;
1052         u32 reg = 0;
1053
1054         if (hw->phy.media_type != e1000_media_type_copper ||
1055             !(igb_sgmii_active_82575(hw)))
1056                 goto out;
1057
1058         /* For SGMII, we need to issue a PCS autoneg restart */
1059         reg = rd32(E1000_PCS_LCTL);
1060
1061         /* AN time out should be disabled for SGMII mode */
1062         reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1063
1064         if (mac->autoneg) {
1065                 /* Make sure forced speed and force link are not set */
1066                 reg &= ~(E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1067
1068                 /*
1069                  * The PHY should be setup prior to calling this function.
1070                  * All we need to do is restart autoneg and enable autoneg.
1071                  */
1072                 reg |= E1000_PCS_LCTL_AN_RESTART | E1000_PCS_LCTL_AN_ENABLE;
1073         } else {
1074                 /* Set PCS regiseter for forced speed */
1075
1076                 /* Turn off bits for full duplex, speed, and autoneg */
1077                 reg &= ~(E1000_PCS_LCTL_FSV_1000 |
1078                          E1000_PCS_LCTL_FSV_100 |
1079                          E1000_PCS_LCTL_FDV_FULL |
1080                          E1000_PCS_LCTL_AN_ENABLE);
1081
1082                 /* Check for duplex first */
1083                 if (mac->forced_speed_duplex & E1000_ALL_FULL_DUPLEX)
1084                         reg |= E1000_PCS_LCTL_FDV_FULL;
1085
1086                 /* Now set speed */
1087                 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED)
1088                         reg |= E1000_PCS_LCTL_FSV_100;
1089
1090                 /* Force speed and force link */
1091                 reg |= E1000_PCS_LCTL_FSD |
1092                        E1000_PCS_LCTL_FORCE_LINK |
1093                        E1000_PCS_LCTL_FLV_LINK_UP;
1094
1095                 hw_dbg(hw,
1096                        "Wrote 0x%08X to PCS_LCTL to configure forced link\n",
1097                        reg);
1098         }
1099         wr32(E1000_PCS_LCTL, reg);
1100
1101 out:
1102         return 0;
1103 }
1104
1105 /**
1106  *  e1000_sgmii_active_82575 - Return sgmii state
1107  *  @hw: pointer to the HW structure
1108  *
1109  *  82575 silicon has a serialized gigabit media independent interface (sgmii)
1110  *  which can be enabled for use in the embedded applications.  Simply
1111  *  return the current state of the sgmii interface.
1112  **/
1113 static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1114 {
1115         struct e1000_dev_spec_82575 *dev_spec;
1116         bool ret_val;
1117
1118         if (hw->mac.type != e1000_82575) {
1119                 ret_val = false;
1120                 goto out;
1121         }
1122
1123         dev_spec = (struct e1000_dev_spec_82575 *)hw->dev_spec;
1124
1125         ret_val = dev_spec->sgmii_active;
1126
1127 out:
1128         return ret_val;
1129 }
1130
1131 /**
1132  *  e1000_reset_init_script_82575 - Inits HW defaults after reset
1133  *  @hw: pointer to the HW structure
1134  *
1135  *  Inits recommended HW defaults after a reset when there is no EEPROM
1136  *  detected. This is only for the 82575.
1137  **/
1138 static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1139 {
1140         if (hw->mac.type == e1000_82575) {
1141                 hw_dbg(hw, "Running reset init script for 82575\n");
1142                 /* SerDes configuration via SERDESCTRL */
1143                 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1144                 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1145                 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1146                 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1147
1148                 /* CCM configuration via CCMCTL register */
1149                 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1150                 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1151
1152                 /* PCIe lanes configuration */
1153                 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1154                 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1155                 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1156                 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1157
1158                 /* PCIe PLL Configuration */
1159                 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1160                 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1161                 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1162         }
1163
1164         return 0;
1165 }
1166
1167 /**
1168  *  e1000_read_mac_addr_82575 - Read device MAC address
1169  *  @hw: pointer to the HW structure
1170  **/
1171 static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1172 {
1173         s32 ret_val = 0;
1174
1175         if (igb_check_alt_mac_addr(hw))
1176                 ret_val = igb_read_mac_addr(hw);
1177
1178         return ret_val;
1179 }
1180
1181 /**
1182  *  e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
1183  *  @hw: pointer to the HW structure
1184  *
1185  *  Clears the hardware counters by reading the counter registers.
1186  **/
1187 static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1188 {
1189         u32 temp;
1190
1191         igb_clear_hw_cntrs_base(hw);
1192
1193         temp = rd32(E1000_PRC64);
1194         temp = rd32(E1000_PRC127);
1195         temp = rd32(E1000_PRC255);
1196         temp = rd32(E1000_PRC511);
1197         temp = rd32(E1000_PRC1023);
1198         temp = rd32(E1000_PRC1522);
1199         temp = rd32(E1000_PTC64);
1200         temp = rd32(E1000_PTC127);
1201         temp = rd32(E1000_PTC255);
1202         temp = rd32(E1000_PTC511);
1203         temp = rd32(E1000_PTC1023);
1204         temp = rd32(E1000_PTC1522);
1205
1206         temp = rd32(E1000_ALGNERRC);
1207         temp = rd32(E1000_RXERRC);
1208         temp = rd32(E1000_TNCRS);
1209         temp = rd32(E1000_CEXTERR);
1210         temp = rd32(E1000_TSCTC);
1211         temp = rd32(E1000_TSCTFC);
1212
1213         temp = rd32(E1000_MGTPRC);
1214         temp = rd32(E1000_MGTPDC);
1215         temp = rd32(E1000_MGTPTC);
1216
1217         temp = rd32(E1000_IAC);
1218         temp = rd32(E1000_ICRXOC);
1219
1220         temp = rd32(E1000_ICRXPTC);
1221         temp = rd32(E1000_ICRXATC);
1222         temp = rd32(E1000_ICTXPTC);
1223         temp = rd32(E1000_ICTXATC);
1224         temp = rd32(E1000_ICTXQEC);
1225         temp = rd32(E1000_ICTXQMTC);
1226         temp = rd32(E1000_ICRXDMTC);
1227
1228         temp = rd32(E1000_CBTMPC);
1229         temp = rd32(E1000_HTDPMC);
1230         temp = rd32(E1000_CBRMPC);
1231         temp = rd32(E1000_RPTHC);
1232         temp = rd32(E1000_HGPTC);
1233         temp = rd32(E1000_HTCBDPC);
1234         temp = rd32(E1000_HGORCL);
1235         temp = rd32(E1000_HGORCH);
1236         temp = rd32(E1000_HGOTCL);
1237         temp = rd32(E1000_HGOTCH);
1238         temp = rd32(E1000_LENERRS);
1239
1240         /* This register should not be read in copper configurations */
1241         if (hw->phy.media_type == e1000_media_type_internal_serdes)
1242                 temp = rd32(E1000_SCVPC);
1243 }
1244
1245 static struct e1000_mac_operations e1000_mac_ops_82575 = {
1246         .reset_hw             = igb_reset_hw_82575,
1247         .init_hw              = igb_init_hw_82575,
1248         .check_for_link       = igb_check_for_link_82575,
1249         .rar_set              = igb_rar_set_82575,
1250         .read_mac_addr        = igb_read_mac_addr_82575,
1251         .get_speed_and_duplex = igb_get_speed_and_duplex_copper,
1252 };
1253
1254 static struct e1000_phy_operations e1000_phy_ops_82575 = {
1255         .acquire_phy          = igb_acquire_phy_82575,
1256         .get_cfg_done         = igb_get_cfg_done_82575,
1257         .release_phy          = igb_release_phy_82575,
1258 };
1259
1260 static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
1261         .acquire_nvm          = igb_acquire_nvm_82575,
1262         .read_nvm             = igb_read_nvm_eerd,
1263         .release_nvm          = igb_release_nvm_82575,
1264         .write_nvm            = igb_write_nvm_spi,
1265 };
1266
1267 const struct e1000_info e1000_82575_info = {
1268         .get_invariants = igb_get_invariants_82575,
1269         .mac_ops = &e1000_mac_ops_82575,
1270         .phy_ops = &e1000_phy_ops_82575,
1271         .nvm_ops = &e1000_nvm_ops_82575,
1272 };
1273