1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
32 #include <linux/types.h>
33 #include <linux/slab.h>
34 #include <linux/if_ether.h>
36 #include "e1000_mac.h"
37 #include "e1000_82575.h"
39 static s32 igb_get_invariants_82575(struct e1000_hw *);
40 static s32 igb_acquire_phy_82575(struct e1000_hw *);
41 static void igb_release_phy_82575(struct e1000_hw *);
42 static s32 igb_acquire_nvm_82575(struct e1000_hw *);
43 static void igb_release_nvm_82575(struct e1000_hw *);
44 static s32 igb_check_for_link_82575(struct e1000_hw *);
45 static s32 igb_get_cfg_done_82575(struct e1000_hw *);
46 static s32 igb_init_hw_82575(struct e1000_hw *);
47 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
48 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
49 static s32 igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *);
50 static s32 igb_write_phy_reg_82580(struct e1000_hw *, u32, u16);
51 static s32 igb_reset_hw_82575(struct e1000_hw *);
52 static s32 igb_reset_hw_82580(struct e1000_hw *);
53 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
54 static s32 igb_setup_copper_link_82575(struct e1000_hw *);
55 static s32 igb_setup_serdes_link_82575(struct e1000_hw *);
56 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
57 static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
58 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
59 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
61 static s32 igb_get_phy_id_82575(struct e1000_hw *);
62 static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
63 static bool igb_sgmii_active_82575(struct e1000_hw *);
64 static s32 igb_reset_init_script_82575(struct e1000_hw *);
65 static s32 igb_read_mac_addr_82575(struct e1000_hw *);
66 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw);
68 static const u16 e1000_82580_rxpbs_table[] =
69 { 36, 72, 144, 1, 2, 4, 8, 16,
71 #define E1000_82580_RXPBS_TABLE_SIZE \
72 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
74 static s32 igb_get_invariants_82575(struct e1000_hw *hw)
76 struct e1000_phy_info *phy = &hw->phy;
77 struct e1000_nvm_info *nvm = &hw->nvm;
78 struct e1000_mac_info *mac = &hw->mac;
79 struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575;
85 switch (hw->device_id) {
86 case E1000_DEV_ID_82575EB_COPPER:
87 case E1000_DEV_ID_82575EB_FIBER_SERDES:
88 case E1000_DEV_ID_82575GB_QUAD_COPPER:
89 mac->type = e1000_82575;
91 case E1000_DEV_ID_82576:
92 case E1000_DEV_ID_82576_NS:
93 case E1000_DEV_ID_82576_NS_SERDES:
94 case E1000_DEV_ID_82576_FIBER:
95 case E1000_DEV_ID_82576_SERDES:
96 case E1000_DEV_ID_82576_QUAD_COPPER:
97 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
98 case E1000_DEV_ID_82576_SERDES_QUAD:
99 mac->type = e1000_82576;
101 case E1000_DEV_ID_82580_COPPER:
102 case E1000_DEV_ID_82580_FIBER:
103 case E1000_DEV_ID_82580_SERDES:
104 case E1000_DEV_ID_82580_SGMII:
105 case E1000_DEV_ID_82580_COPPER_DUAL:
106 mac->type = e1000_82580;
109 return -E1000_ERR_MAC_INIT;
115 * The 82575 uses bits 22:23 for link mode. The mode can be changed
116 * based on the EEPROM. We cannot rely upon device ID. There
117 * is no distinguishable difference between fiber and internal
118 * SerDes mode on the 82575. There can be an external PHY attached
119 * on the SGMII interface. For this, we'll set sgmii_active to true.
121 phy->media_type = e1000_media_type_copper;
122 dev_spec->sgmii_active = false;
124 ctrl_ext = rd32(E1000_CTRL_EXT);
125 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
126 case E1000_CTRL_EXT_LINK_MODE_SGMII:
127 dev_spec->sgmii_active = true;
128 ctrl_ext |= E1000_CTRL_I2C_ENA;
130 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
131 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
132 hw->phy.media_type = e1000_media_type_internal_serdes;
133 ctrl_ext |= E1000_CTRL_I2C_ENA;
136 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
140 wr32(E1000_CTRL_EXT, ctrl_ext);
143 * if using i2c make certain the MDICNFG register is cleared to prevent
144 * communications from being misrouted to the mdic registers
146 if ((ctrl_ext & E1000_CTRL_I2C_ENA) && (hw->mac.type == e1000_82580))
147 wr32(E1000_MDICNFG, 0);
149 /* Set mta register count */
150 mac->mta_reg_count = 128;
151 /* Set rar entry count */
152 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
153 if (mac->type == e1000_82576)
154 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
155 if (mac->type == e1000_82580)
156 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
158 if (mac->type == e1000_82580)
159 mac->ops.reset_hw = igb_reset_hw_82580;
161 mac->ops.reset_hw = igb_reset_hw_82575;
162 /* Set if part includes ASF firmware */
163 mac->asf_firmware_present = true;
164 /* Set if manageability features are enabled. */
165 mac->arc_subsystem_valid =
166 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
169 /* physical interface link setup */
170 mac->ops.setup_physical_interface =
171 (hw->phy.media_type == e1000_media_type_copper)
172 ? igb_setup_copper_link_82575
173 : igb_setup_serdes_link_82575;
175 /* NVM initialization */
176 eecd = rd32(E1000_EECD);
178 nvm->opcode_bits = 8;
180 switch (nvm->override) {
181 case e1000_nvm_override_spi_large:
183 nvm->address_bits = 16;
185 case e1000_nvm_override_spi_small:
187 nvm->address_bits = 8;
190 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
191 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
195 nvm->type = e1000_nvm_eeprom_spi;
197 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
198 E1000_EECD_SIZE_EX_SHIFT);
201 * Added to a constant, "size" becomes the left-shift value
202 * for setting word_size.
204 size += NVM_WORD_SIZE_BASE_SHIFT;
206 /* EEPROM access above 16k is unsupported */
209 nvm->word_size = 1 << size;
211 /* if 82576 then initialize mailbox parameters */
212 if (mac->type == e1000_82576)
213 igb_init_mbx_params_pf(hw);
215 /* setup PHY parameters */
216 if (phy->media_type != e1000_media_type_copper) {
217 phy->type = e1000_phy_none;
221 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
222 phy->reset_delay_us = 100;
224 /* PHY function pointers */
225 if (igb_sgmii_active_82575(hw)) {
226 phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
227 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
228 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
229 } else if (hw->mac.type == e1000_82580) {
230 phy->ops.reset = igb_phy_hw_reset;
231 phy->ops.read_reg = igb_read_phy_reg_82580;
232 phy->ops.write_reg = igb_write_phy_reg_82580;
234 phy->ops.reset = igb_phy_hw_reset;
235 phy->ops.read_reg = igb_read_phy_reg_igp;
236 phy->ops.write_reg = igb_write_phy_reg_igp;
240 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
241 E1000_STATUS_FUNC_SHIFT;
243 /* Set phy->phy_addr and phy->id. */
244 ret_val = igb_get_phy_id_82575(hw);
248 /* Verify phy id and set remaining function pointers */
250 case M88E1111_I_PHY_ID:
251 phy->type = e1000_phy_m88;
252 phy->ops.get_phy_info = igb_get_phy_info_m88;
253 phy->ops.get_cable_length = igb_get_cable_length_m88;
254 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
256 case IGP03E1000_E_PHY_ID:
257 phy->type = e1000_phy_igp_3;
258 phy->ops.get_phy_info = igb_get_phy_info_igp;
259 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
260 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
261 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
262 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
264 case I82580_I_PHY_ID:
265 phy->type = e1000_phy_82580;
266 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_82580;
267 phy->ops.get_cable_length = igb_get_cable_length_82580;
268 phy->ops.get_phy_info = igb_get_phy_info_82580;
271 return -E1000_ERR_PHY;
278 * igb_acquire_phy_82575 - Acquire rights to access PHY
279 * @hw: pointer to the HW structure
281 * Acquire access rights to the correct PHY. This is a
282 * function pointer entry point called by the api module.
284 static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
286 u16 mask = E1000_SWFW_PHY0_SM;
288 if (hw->bus.func == E1000_FUNC_1)
289 mask = E1000_SWFW_PHY1_SM;
291 return igb_acquire_swfw_sync_82575(hw, mask);
295 * igb_release_phy_82575 - Release rights to access PHY
296 * @hw: pointer to the HW structure
298 * A wrapper to release access rights to the correct PHY. This is a
299 * function pointer entry point called by the api module.
301 static void igb_release_phy_82575(struct e1000_hw *hw)
303 u16 mask = E1000_SWFW_PHY0_SM;
305 if (hw->bus.func == E1000_FUNC_1)
306 mask = E1000_SWFW_PHY1_SM;
308 igb_release_swfw_sync_82575(hw, mask);
312 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
313 * @hw: pointer to the HW structure
314 * @offset: register offset to be read
315 * @data: pointer to the read data
317 * Reads the PHY register at offset using the serial gigabit media independent
318 * interface and stores the retrieved information in data.
320 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
323 s32 ret_val = -E1000_ERR_PARAM;
325 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
326 hw_dbg("PHY Address %u is out of range\n", offset);
330 ret_val = hw->phy.ops.acquire(hw);
334 ret_val = igb_read_phy_reg_i2c(hw, offset, data);
336 hw->phy.ops.release(hw);
343 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
344 * @hw: pointer to the HW structure
345 * @offset: register offset to write to
346 * @data: data to write at register offset
348 * Writes the data to PHY register at the offset using the serial gigabit
349 * media independent interface.
351 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
354 s32 ret_val = -E1000_ERR_PARAM;
357 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
358 hw_dbg("PHY Address %d is out of range\n", offset);
362 ret_val = hw->phy.ops.acquire(hw);
366 ret_val = igb_write_phy_reg_i2c(hw, offset, data);
368 hw->phy.ops.release(hw);
375 * igb_get_phy_id_82575 - Retrieve PHY addr and id
376 * @hw: pointer to the HW structure
378 * Retrieves the PHY address and ID for both PHY's which do and do not use
381 static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
383 struct e1000_phy_info *phy = &hw->phy;
389 * For SGMII PHYs, we try the list of possible addresses until
390 * we find one that works. For non-SGMII PHYs
391 * (e.g. integrated copper PHYs), an address of 1 should
392 * work. The result of this function should mean phy->phy_addr
393 * and phy->id are set correctly.
395 if (!(igb_sgmii_active_82575(hw))) {
397 ret_val = igb_get_phy_id(hw);
401 /* Power on sgmii phy if it is disabled */
402 ctrl_ext = rd32(E1000_CTRL_EXT);
403 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
408 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
409 * Therefore, we need to test 1-7
411 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
412 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
414 hw_dbg("Vendor ID 0x%08X read at address %u\n",
417 * At the time of this writing, The M88 part is
418 * the only supported SGMII PHY product.
420 if (phy_id == M88_VENDOR)
423 hw_dbg("PHY address %u was unreadable\n", phy->addr);
427 /* A valid PHY type couldn't be found. */
428 if (phy->addr == 8) {
430 ret_val = -E1000_ERR_PHY;
433 ret_val = igb_get_phy_id(hw);
436 /* restore previous sfp cage power state */
437 wr32(E1000_CTRL_EXT, ctrl_ext);
444 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
445 * @hw: pointer to the HW structure
447 * Resets the PHY using the serial gigabit media independent interface.
449 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
454 * This isn't a true "hard" reset, but is the only reset
455 * available to us at this time.
458 hw_dbg("Soft resetting SGMII attached PHY...\n");
461 * SFP documentation requires the following to configure the SPF module
462 * to work on SGMII. No further documentation is given.
464 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
468 ret_val = igb_phy_sw_reset(hw);
475 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
476 * @hw: pointer to the HW structure
477 * @active: true to enable LPLU, false to disable
479 * Sets the LPLU D0 state according to the active flag. When
480 * activating LPLU this function also disables smart speed
481 * and vice versa. LPLU will not be activated unless the
482 * device autonegotiation advertisement meets standards of
483 * either 10 or 10/100 or 10/100/1000 at all duplexes.
484 * This is a function pointer entry point only called by
485 * PHY setup routines.
487 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
489 struct e1000_phy_info *phy = &hw->phy;
493 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
498 data |= IGP02E1000_PM_D0_LPLU;
499 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
504 /* When LPLU is enabled, we should disable SmartSpeed */
505 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
507 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
508 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
513 data &= ~IGP02E1000_PM_D0_LPLU;
514 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
517 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
518 * during Dx states where the power conservation is most
519 * important. During driver activity we should enable
520 * SmartSpeed, so performance is maintained.
522 if (phy->smart_speed == e1000_smart_speed_on) {
523 ret_val = phy->ops.read_reg(hw,
524 IGP01E1000_PHY_PORT_CONFIG, &data);
528 data |= IGP01E1000_PSCFR_SMART_SPEED;
529 ret_val = phy->ops.write_reg(hw,
530 IGP01E1000_PHY_PORT_CONFIG, data);
533 } else if (phy->smart_speed == e1000_smart_speed_off) {
534 ret_val = phy->ops.read_reg(hw,
535 IGP01E1000_PHY_PORT_CONFIG, &data);
539 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
540 ret_val = phy->ops.write_reg(hw,
541 IGP01E1000_PHY_PORT_CONFIG, data);
552 * igb_acquire_nvm_82575 - Request for access to EEPROM
553 * @hw: pointer to the HW structure
555 * Acquire the necessary semaphores for exclusive access to the EEPROM.
556 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
557 * Return successful if access grant bit set, else clear the request for
558 * EEPROM access and return -E1000_ERR_NVM (-1).
560 static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
564 ret_val = igb_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
568 ret_val = igb_acquire_nvm(hw);
571 igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
578 * igb_release_nvm_82575 - Release exclusive access to EEPROM
579 * @hw: pointer to the HW structure
581 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
582 * then release the semaphores acquired.
584 static void igb_release_nvm_82575(struct e1000_hw *hw)
587 igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
591 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
592 * @hw: pointer to the HW structure
593 * @mask: specifies which semaphore to acquire
595 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
596 * will also specify which port we're acquiring the lock for.
598 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
602 u32 fwmask = mask << 16;
604 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
606 while (i < timeout) {
607 if (igb_get_hw_semaphore(hw)) {
608 ret_val = -E1000_ERR_SWFW_SYNC;
612 swfw_sync = rd32(E1000_SW_FW_SYNC);
613 if (!(swfw_sync & (fwmask | swmask)))
617 * Firmware currently using resource (fwmask)
618 * or other software thread using resource (swmask)
620 igb_put_hw_semaphore(hw);
626 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
627 ret_val = -E1000_ERR_SWFW_SYNC;
632 wr32(E1000_SW_FW_SYNC, swfw_sync);
634 igb_put_hw_semaphore(hw);
641 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
642 * @hw: pointer to the HW structure
643 * @mask: specifies which semaphore to acquire
645 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
646 * will also specify which port we're releasing the lock for.
648 static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
652 while (igb_get_hw_semaphore(hw) != 0);
655 swfw_sync = rd32(E1000_SW_FW_SYNC);
657 wr32(E1000_SW_FW_SYNC, swfw_sync);
659 igb_put_hw_semaphore(hw);
663 * igb_get_cfg_done_82575 - Read config done bit
664 * @hw: pointer to the HW structure
666 * Read the management control register for the config done bit for
667 * completion status. NOTE: silicon which is EEPROM-less will fail trying
668 * to read the config done bit, so an error is *ONLY* logged and returns
669 * 0. If we were to return with error, EEPROM-less silicon
670 * would not be able to be reset or change link.
672 static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
674 s32 timeout = PHY_CFG_TIMEOUT;
676 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
678 if (hw->bus.func == 1)
679 mask = E1000_NVM_CFG_DONE_PORT_1;
680 else if (hw->bus.func == E1000_FUNC_2)
681 mask = E1000_NVM_CFG_DONE_PORT_2;
682 else if (hw->bus.func == E1000_FUNC_3)
683 mask = E1000_NVM_CFG_DONE_PORT_3;
686 if (rd32(E1000_EEMNGCTL) & mask)
692 hw_dbg("MNG configuration cycle has not completed.\n");
694 /* If EEPROM is not marked present, init the PHY manually */
695 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
696 (hw->phy.type == e1000_phy_igp_3))
697 igb_phy_init_script_igp3(hw);
703 * igb_check_for_link_82575 - Check for link
704 * @hw: pointer to the HW structure
706 * If sgmii is enabled, then use the pcs register to determine link, otherwise
707 * use the generic interface for determining link.
709 static s32 igb_check_for_link_82575(struct e1000_hw *hw)
714 if (hw->phy.media_type != e1000_media_type_copper) {
715 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
718 * Use this flag to determine if link needs to be checked or
719 * not. If we have link clear the flag so that we do not
720 * continue to check for link.
722 hw->mac.get_link_status = !hw->mac.serdes_has_link;
724 ret_val = igb_check_for_copper_link(hw);
731 * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
732 * @hw: pointer to the HW structure
734 void igb_power_up_serdes_link_82575(struct e1000_hw *hw)
739 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
740 !igb_sgmii_active_82575(hw))
743 /* Enable PCS to turn on link */
744 reg = rd32(E1000_PCS_CFG0);
745 reg |= E1000_PCS_CFG_PCS_EN;
746 wr32(E1000_PCS_CFG0, reg);
748 /* Power up the laser */
749 reg = rd32(E1000_CTRL_EXT);
750 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
751 wr32(E1000_CTRL_EXT, reg);
753 /* flush the write to verify completion */
759 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
760 * @hw: pointer to the HW structure
761 * @speed: stores the current speed
762 * @duplex: stores the current duplex
764 * Using the physical coding sub-layer (PCS), retrieve the current speed and
765 * duplex, then store the values in the pointers provided.
767 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
770 struct e1000_mac_info *mac = &hw->mac;
773 /* Set up defaults for the return values of this function */
774 mac->serdes_has_link = false;
779 * Read the PCS Status register for link state. For non-copper mode,
780 * the status register is not accurate. The PCS status register is
783 pcs = rd32(E1000_PCS_LSTAT);
786 * The link up bit determines when link is up on autoneg. The sync ok
787 * gets set once both sides sync up and agree upon link. Stable link
788 * can be determined by checking for both link up and link sync ok
790 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
791 mac->serdes_has_link = true;
793 /* Detect and store PCS speed */
794 if (pcs & E1000_PCS_LSTS_SPEED_1000) {
796 } else if (pcs & E1000_PCS_LSTS_SPEED_100) {
802 /* Detect and store PCS duplex */
803 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
804 *duplex = FULL_DUPLEX;
806 *duplex = HALF_DUPLEX;
814 * igb_shutdown_serdes_link_82575 - Remove link during power down
815 * @hw: pointer to the HW structure
817 * In the case of fiber serdes, shut down optics and PCS on driver unload
818 * when management pass thru is not enabled.
820 void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
824 if (hw->phy.media_type != e1000_media_type_internal_serdes &&
825 igb_sgmii_active_82575(hw))
828 if (!igb_enable_mng_pass_thru(hw)) {
829 /* Disable PCS to turn off link */
830 reg = rd32(E1000_PCS_CFG0);
831 reg &= ~E1000_PCS_CFG_PCS_EN;
832 wr32(E1000_PCS_CFG0, reg);
834 /* shutdown the laser */
835 reg = rd32(E1000_CTRL_EXT);
836 reg |= E1000_CTRL_EXT_SDP3_DATA;
837 wr32(E1000_CTRL_EXT, reg);
839 /* flush the write to verify completion */
846 * igb_reset_hw_82575 - Reset hardware
847 * @hw: pointer to the HW structure
849 * This resets the hardware into a known state. This is a
850 * function pointer entry point called by the api module.
852 static s32 igb_reset_hw_82575(struct e1000_hw *hw)
858 * Prevent the PCI-E bus from sticking if there is no TLP connection
859 * on the last TLP read/write transaction when MAC is reset.
861 ret_val = igb_disable_pcie_master(hw);
863 hw_dbg("PCI-E Master disable polling has failed.\n");
865 /* set the completion timeout for interface */
866 ret_val = igb_set_pcie_completion_timeout(hw);
868 hw_dbg("PCI-E Set completion timeout has failed.\n");
871 hw_dbg("Masking off all interrupts\n");
872 wr32(E1000_IMC, 0xffffffff);
875 wr32(E1000_TCTL, E1000_TCTL_PSP);
880 ctrl = rd32(E1000_CTRL);
882 hw_dbg("Issuing a global reset to MAC\n");
883 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
885 ret_val = igb_get_auto_rd_done(hw);
888 * When auto config read does not complete, do not
889 * return with an error. This can happen in situations
890 * where there is no eeprom and prevents getting link.
892 hw_dbg("Auto Read Done did not complete\n");
895 /* If EEPROM is not present, run manual init scripts */
896 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
897 igb_reset_init_script_82575(hw);
899 /* Clear any pending interrupt events. */
900 wr32(E1000_IMC, 0xffffffff);
901 icr = rd32(E1000_ICR);
903 /* Install any alternate MAC address into RAR0 */
904 ret_val = igb_check_alt_mac_addr(hw);
910 * igb_init_hw_82575 - Initialize hardware
911 * @hw: pointer to the HW structure
913 * This inits the hardware readying it for operation.
915 static s32 igb_init_hw_82575(struct e1000_hw *hw)
917 struct e1000_mac_info *mac = &hw->mac;
919 u16 i, rar_count = mac->rar_entry_count;
921 /* Initialize identification LED */
922 ret_val = igb_id_led_init(hw);
924 hw_dbg("Error initializing identification LED\n");
925 /* This is not fatal and we should not stop init due to this */
928 /* Disabling VLAN filtering */
929 hw_dbg("Initializing the IEEE VLAN\n");
932 /* Setup the receive address */
933 igb_init_rx_addrs(hw, rar_count);
935 /* Zero out the Multicast HASH table */
936 hw_dbg("Zeroing the MTA\n");
937 for (i = 0; i < mac->mta_reg_count; i++)
938 array_wr32(E1000_MTA, i, 0);
940 /* Zero out the Unicast HASH table */
941 hw_dbg("Zeroing the UTA\n");
942 for (i = 0; i < mac->uta_reg_count; i++)
943 array_wr32(E1000_UTA, i, 0);
945 /* Setup link and flow control */
946 ret_val = igb_setup_link(hw);
949 * Clear all of the statistics registers (clear on read). It is
950 * important that we do this after we have tried to establish link
951 * because the symbol error count will increment wildly if there
954 igb_clear_hw_cntrs_82575(hw);
960 * igb_setup_copper_link_82575 - Configure copper link settings
961 * @hw: pointer to the HW structure
963 * Configures the link for auto-neg or forced speed and duplex. Then we check
964 * for link, once link is established calls to configure collision distance
965 * and flow control are called.
967 static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
972 ctrl = rd32(E1000_CTRL);
973 ctrl |= E1000_CTRL_SLU;
974 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
975 wr32(E1000_CTRL, ctrl);
977 ret_val = igb_setup_serdes_link_82575(hw);
981 if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
982 /* allow time for SFP cage time to power up phy */
985 ret_val = hw->phy.ops.reset(hw);
987 hw_dbg("Error resetting the PHY.\n");
991 switch (hw->phy.type) {
993 ret_val = igb_copper_link_setup_m88(hw);
995 case e1000_phy_igp_3:
996 ret_val = igb_copper_link_setup_igp(hw);
998 case e1000_phy_82580:
999 ret_val = igb_copper_link_setup_82580(hw);
1002 ret_val = -E1000_ERR_PHY;
1009 ret_val = igb_setup_copper_link(hw);
1015 * igb_setup_serdes_link_82575 - Setup link for serdes
1016 * @hw: pointer to the HW structure
1018 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1019 * used on copper connections where the serialized gigabit media independent
1020 * interface (sgmii), or serdes fiber is being used. Configures the link
1021 * for auto-negotiation or forces speed/duplex.
1023 static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
1025 u32 ctrl_ext, ctrl_reg, reg;
1028 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1029 !igb_sgmii_active_82575(hw))
1033 * On the 82575, SerDes loopback mode persists until it is
1034 * explicitly turned off or a power cycle is performed. A read to
1035 * the register does not indicate its status. Therefore, we ensure
1036 * loopback mode is disabled during initialization.
1038 wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1040 /* power on the sfp cage if present */
1041 ctrl_ext = rd32(E1000_CTRL_EXT);
1042 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1043 wr32(E1000_CTRL_EXT, ctrl_ext);
1045 ctrl_reg = rd32(E1000_CTRL);
1046 ctrl_reg |= E1000_CTRL_SLU;
1048 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1049 /* set both sw defined pins */
1050 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1052 /* Set switch control to serdes energy detect */
1053 reg = rd32(E1000_CONNSW);
1054 reg |= E1000_CONNSW_ENRGSRC;
1055 wr32(E1000_CONNSW, reg);
1058 reg = rd32(E1000_PCS_LCTL);
1060 /* default pcs_autoneg to the same setting as mac autoneg */
1061 pcs_autoneg = hw->mac.autoneg;
1063 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1064 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1065 /* sgmii mode lets the phy handle forcing speed/duplex */
1067 /* autoneg time out should be disabled for SGMII mode */
1068 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1070 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1071 /* disable PCS autoneg and support parallel detect only */
1072 pcs_autoneg = false;
1075 * non-SGMII modes only supports a speed of 1000/Full for the
1076 * link so it is best to just force the MAC and let the pcs
1077 * link either autoneg or be forced to 1000/Full
1079 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1080 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1082 /* set speed of 1000/Full if speed/duplex is forced */
1083 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1087 wr32(E1000_CTRL, ctrl_reg);
1090 * New SerDes mode allows for forcing speed or autonegotiating speed
1091 * at 1gb. Autoneg should be default set by most drivers. This is the
1092 * mode that will be compatible with older link partners and switches.
1093 * However, both are supported by the hardware and some drivers/tools.
1095 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1096 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1099 * We force flow control to prevent the CTRL register values from being
1100 * overwritten by the autonegotiated flow control values
1102 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1105 /* Set PCS register for autoneg */
1106 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1107 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1108 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1110 /* Set PCS register for forced link */
1111 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
1113 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1116 wr32(E1000_PCS_LCTL, reg);
1118 if (!igb_sgmii_active_82575(hw))
1119 igb_force_mac_fc(hw);
1125 * igb_sgmii_active_82575 - Return sgmii state
1126 * @hw: pointer to the HW structure
1128 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1129 * which can be enabled for use in the embedded applications. Simply
1130 * return the current state of the sgmii interface.
1132 static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1134 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1135 return dev_spec->sgmii_active;
1139 * igb_reset_init_script_82575 - Inits HW defaults after reset
1140 * @hw: pointer to the HW structure
1142 * Inits recommended HW defaults after a reset when there is no EEPROM
1143 * detected. This is only for the 82575.
1145 static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1147 if (hw->mac.type == e1000_82575) {
1148 hw_dbg("Running reset init script for 82575\n");
1149 /* SerDes configuration via SERDESCTRL */
1150 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1151 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1152 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1153 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1155 /* CCM configuration via CCMCTL register */
1156 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1157 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1159 /* PCIe lanes configuration */
1160 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1161 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1162 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1163 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1165 /* PCIe PLL Configuration */
1166 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1167 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1168 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1175 * igb_read_mac_addr_82575 - Read device MAC address
1176 * @hw: pointer to the HW structure
1178 static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1183 * If there's an alternate MAC address place it in RAR0
1184 * so that it will override the Si installed default perm
1187 ret_val = igb_check_alt_mac_addr(hw);
1191 ret_val = igb_read_mac_addr(hw);
1198 * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1199 * @hw: pointer to the HW structure
1201 * In the case of a PHY power down to save power, or to turn off link during a
1202 * driver unload, or wake on lan is not enabled, remove the link.
1204 void igb_power_down_phy_copper_82575(struct e1000_hw *hw)
1206 /* If the management interface is not enabled, then power down */
1207 if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw)))
1208 igb_power_down_phy_copper(hw);
1214 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
1215 * @hw: pointer to the HW structure
1217 * Clears the hardware counters by reading the counter registers.
1219 static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1221 igb_clear_hw_cntrs_base(hw);
1227 rd32(E1000_PRC1023);
1228 rd32(E1000_PRC1522);
1233 rd32(E1000_PTC1023);
1234 rd32(E1000_PTC1522);
1236 rd32(E1000_ALGNERRC);
1239 rd32(E1000_CEXTERR);
1250 rd32(E1000_ICRXPTC);
1251 rd32(E1000_ICRXATC);
1252 rd32(E1000_ICTXPTC);
1253 rd32(E1000_ICTXATC);
1254 rd32(E1000_ICTXQEC);
1255 rd32(E1000_ICTXQMTC);
1256 rd32(E1000_ICRXDMTC);
1263 rd32(E1000_HTCBDPC);
1268 rd32(E1000_LENERRS);
1270 /* This register should not be read in copper configurations */
1271 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1272 igb_sgmii_active_82575(hw))
1277 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1278 * @hw: pointer to the HW structure
1280 * After rx enable if managability is enabled then there is likely some
1281 * bad data at the start of the fifo and possibly in the DMA fifo. This
1282 * function clears the fifos and flushes any packets that came in as rx was
1285 void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1287 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1290 if (hw->mac.type != e1000_82575 ||
1291 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1294 /* Disable all RX queues */
1295 for (i = 0; i < 4; i++) {
1296 rxdctl[i] = rd32(E1000_RXDCTL(i));
1297 wr32(E1000_RXDCTL(i),
1298 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1300 /* Poll all queues to verify they have shut down */
1301 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1304 for (i = 0; i < 4; i++)
1305 rx_enabled |= rd32(E1000_RXDCTL(i));
1306 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1311 hw_dbg("Queue disable timed out after 10ms\n");
1313 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1314 * incoming packets are rejected. Set enable and wait 2ms so that
1315 * any packet that was coming in as RCTL.EN was set is flushed
1317 rfctl = rd32(E1000_RFCTL);
1318 wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1320 rlpml = rd32(E1000_RLPML);
1321 wr32(E1000_RLPML, 0);
1323 rctl = rd32(E1000_RCTL);
1324 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1325 temp_rctl |= E1000_RCTL_LPE;
1327 wr32(E1000_RCTL, temp_rctl);
1328 wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1332 /* Enable RX queues that were previously enabled and restore our
1335 for (i = 0; i < 4; i++)
1336 wr32(E1000_RXDCTL(i), rxdctl[i]);
1337 wr32(E1000_RCTL, rctl);
1340 wr32(E1000_RLPML, rlpml);
1341 wr32(E1000_RFCTL, rfctl);
1343 /* Flush receive errors generated by workaround */
1350 * igb_set_pcie_completion_timeout - set pci-e completion timeout
1351 * @hw: pointer to the HW structure
1353 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1354 * however the hardware default for these parts is 500us to 1ms which is less
1355 * than the 10ms recommended by the pci-e spec. To address this we need to
1356 * increase the value to either 10ms to 200ms for capability version 1 config,
1357 * or 16ms to 55ms for version 2.
1359 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
1361 u32 gcr = rd32(E1000_GCR);
1365 /* only take action if timeout value is defaulted to 0 */
1366 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
1370 * if capababilities version is type 1 we can write the
1371 * timeout of 10ms to 200ms through the GCR register
1373 if (!(gcr & E1000_GCR_CAP_VER2)) {
1374 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
1379 * for version 2 capabilities we need to write the config space
1380 * directly in order to set the completion timeout value for
1383 ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1388 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
1390 ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1393 /* disable completion timeout resend */
1394 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
1396 wr32(E1000_GCR, gcr);
1401 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
1402 * @hw: pointer to the hardware struct
1403 * @enable: state to enter, either enabled or disabled
1405 * enables/disables L2 switch loopback functionality.
1407 void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
1409 u32 dtxswc = rd32(E1000_DTXSWC);
1412 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1414 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1416 wr32(E1000_DTXSWC, dtxswc);
1420 * igb_vmdq_set_replication_pf - enable or disable vmdq replication
1421 * @hw: pointer to the hardware struct
1422 * @enable: state to enter, either enabled or disabled
1424 * enables/disables replication of packets across multiple pools.
1426 void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
1428 u32 vt_ctl = rd32(E1000_VT_CTL);
1431 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
1433 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
1435 wr32(E1000_VT_CTL, vt_ctl);
1439 * igb_read_phy_reg_82580 - Read 82580 MDI control register
1440 * @hw: pointer to the HW structure
1441 * @offset: register offset to be read
1442 * @data: pointer to the read data
1444 * Reads the MDI control register in the PHY at offset and stores the
1445 * information read to data.
1447 static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
1453 ret_val = hw->phy.ops.acquire(hw);
1458 * We config the phy address in MDICNFG register now. Same bits
1459 * as before. The values in MDIC can be written but will be
1460 * ignored. This allows us to call the old function after
1461 * configuring the PHY address in the new register
1463 mdicnfg = (hw->phy.addr << E1000_MDIC_PHY_SHIFT);
1464 wr32(E1000_MDICNFG, mdicnfg);
1466 ret_val = igb_read_phy_reg_mdic(hw, offset, data);
1468 hw->phy.ops.release(hw);
1475 * igb_write_phy_reg_82580 - Write 82580 MDI control register
1476 * @hw: pointer to the HW structure
1477 * @offset: register offset to write to
1478 * @data: data to write to register at offset
1480 * Writes data to MDI control register in the PHY at offset.
1482 static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
1488 ret_val = hw->phy.ops.acquire(hw);
1493 * We config the phy address in MDICNFG register now. Same bits
1494 * as before. The values in MDIC can be written but will be
1495 * ignored. This allows us to call the old function after
1496 * configuring the PHY address in the new register
1498 mdicnfg = (hw->phy.addr << E1000_MDIC_PHY_SHIFT);
1499 wr32(E1000_MDICNFG, mdicnfg);
1501 ret_val = igb_write_phy_reg_mdic(hw, offset, data);
1503 hw->phy.ops.release(hw);
1510 * igb_reset_hw_82580 - Reset hardware
1511 * @hw: pointer to the HW structure
1513 * This resets function or entire device (all ports, etc.)
1516 static s32 igb_reset_hw_82580(struct e1000_hw *hw)
1519 /* BH SW mailbox bit in SW_FW_SYNC */
1520 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
1522 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
1525 hw->dev_spec._82575.global_device_reset = false;
1527 /* Get current control state. */
1528 ctrl = rd32(E1000_CTRL);
1531 * Prevent the PCI-E bus from sticking if there is no TLP connection
1532 * on the last TLP read/write transaction when MAC is reset.
1534 ret_val = igb_disable_pcie_master(hw);
1536 hw_dbg("PCI-E Master disable polling has failed.\n");
1538 hw_dbg("Masking off all interrupts\n");
1539 wr32(E1000_IMC, 0xffffffff);
1540 wr32(E1000_RCTL, 0);
1541 wr32(E1000_TCTL, E1000_TCTL_PSP);
1546 /* Determine whether or not a global dev reset is requested */
1547 if (global_device_reset &&
1548 igb_acquire_swfw_sync_82575(hw, swmbsw_mask))
1549 global_device_reset = false;
1551 if (global_device_reset &&
1552 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET))
1553 ctrl |= E1000_CTRL_DEV_RST;
1555 ctrl |= E1000_CTRL_RST;
1557 wr32(E1000_CTRL, ctrl);
1559 /* Add delay to insure DEV_RST has time to complete */
1560 if (global_device_reset)
1563 ret_val = igb_get_auto_rd_done(hw);
1566 * When auto config read does not complete, do not
1567 * return with an error. This can happen in situations
1568 * where there is no eeprom and prevents getting link.
1570 hw_dbg("Auto Read Done did not complete\n");
1573 /* If EEPROM is not present, run manual init scripts */
1574 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
1575 igb_reset_init_script_82575(hw);
1577 /* clear global device reset status bit */
1578 wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET);
1580 /* Clear any pending interrupt events. */
1581 wr32(E1000_IMC, 0xffffffff);
1582 icr = rd32(E1000_ICR);
1584 /* Install any alternate MAC address into RAR0 */
1585 ret_val = igb_check_alt_mac_addr(hw);
1587 /* Release semaphore */
1588 if (global_device_reset)
1589 igb_release_swfw_sync_82575(hw, swmbsw_mask);
1595 * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
1596 * @data: data received by reading RXPBS register
1598 * The 82580 uses a table based approach for packet buffer allocation sizes.
1599 * This function converts the retrieved value into the correct table value
1600 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
1601 * 0x0 36 72 144 1 2 4 8 16
1602 * 0x8 35 70 140 rsv rsv rsv rsv rsv
1604 u16 igb_rxpbs_adjust_82580(u32 data)
1608 if (data < E1000_82580_RXPBS_TABLE_SIZE)
1609 ret_val = e1000_82580_rxpbs_table[data];
1614 static struct e1000_mac_operations e1000_mac_ops_82575 = {
1615 .init_hw = igb_init_hw_82575,
1616 .check_for_link = igb_check_for_link_82575,
1617 .rar_set = igb_rar_set,
1618 .read_mac_addr = igb_read_mac_addr_82575,
1619 .get_speed_and_duplex = igb_get_speed_and_duplex_copper,
1622 static struct e1000_phy_operations e1000_phy_ops_82575 = {
1623 .acquire = igb_acquire_phy_82575,
1624 .get_cfg_done = igb_get_cfg_done_82575,
1625 .release = igb_release_phy_82575,
1628 static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
1629 .acquire = igb_acquire_nvm_82575,
1630 .read = igb_read_nvm_eerd,
1631 .release = igb_release_nvm_82575,
1632 .write = igb_write_nvm_spi,
1635 const struct e1000_info e1000_82575_info = {
1636 .get_invariants = igb_get_invariants_82575,
1637 .mac_ops = &e1000_mac_ops_82575,
1638 .phy_ops = &e1000_phy_ops_82575,
1639 .nvm_ops = &e1000_nvm_ops_82575,