1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
31 #include <linux/types.h>
32 #include <linux/delay.h>
34 #include <linux/netdevice.h>
36 #include "e1000_regs.h"
37 #include "e1000_defines.h"
41 #define E1000_DEV_ID_82576 0x10C9
42 #define E1000_DEV_ID_82576_FIBER 0x10E6
43 #define E1000_DEV_ID_82576_SERDES 0x10E7
44 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
45 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526
46 #define E1000_DEV_ID_82576_NS 0x150A
47 #define E1000_DEV_ID_82576_NS_SERDES 0x1518
48 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D
49 #define E1000_DEV_ID_82575EB_COPPER 0x10A7
50 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
51 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
52 #define E1000_DEV_ID_82580_COPPER 0x150E
53 #define E1000_DEV_ID_82580_FIBER 0x150F
54 #define E1000_DEV_ID_82580_SERDES 0x1510
55 #define E1000_DEV_ID_82580_SGMII 0x1511
56 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516
57 #define E1000_DEV_ID_I350_COPPER 0x1521
58 #define E1000_DEV_ID_I350_FIBER 0x1522
59 #define E1000_DEV_ID_I350_SERDES 0x1523
60 #define E1000_DEV_ID_I350_SGMII 0x1524
62 #define E1000_REVISION_2 2
63 #define E1000_REVISION_4 4
65 #define E1000_FUNC_0 0
66 #define E1000_FUNC_1 1
67 #define E1000_FUNC_2 2
68 #define E1000_FUNC_3 3
70 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
71 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
72 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6
73 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9
81 e1000_num_macs /* List is 1-based, so subtract 1 for true count. */
84 enum e1000_media_type {
85 e1000_media_type_unknown = 0,
86 e1000_media_type_copper = 1,
87 e1000_media_type_internal_serdes = 2,
92 e1000_nvm_unknown = 0,
99 enum e1000_nvm_override {
100 e1000_nvm_override_none = 0,
101 e1000_nvm_override_spi_small,
102 e1000_nvm_override_spi_large,
105 enum e1000_phy_type {
106 e1000_phy_unknown = 0,
117 enum e1000_bus_type {
118 e1000_bus_type_unknown = 0,
121 e1000_bus_type_pci_express,
122 e1000_bus_type_reserved
125 enum e1000_bus_speed {
126 e1000_bus_speed_unknown = 0,
132 e1000_bus_speed_2500,
133 e1000_bus_speed_5000,
134 e1000_bus_speed_reserved
137 enum e1000_bus_width {
138 e1000_bus_width_unknown = 0,
139 e1000_bus_width_pcie_x1,
140 e1000_bus_width_pcie_x2,
141 e1000_bus_width_pcie_x4 = 4,
142 e1000_bus_width_pcie_x8 = 8,
145 e1000_bus_width_reserved
148 enum e1000_1000t_rx_status {
149 e1000_1000t_rx_status_not_ok = 0,
150 e1000_1000t_rx_status_ok,
151 e1000_1000t_rx_status_undefined = 0xFF
154 enum e1000_rev_polarity {
155 e1000_rev_polarity_normal = 0,
156 e1000_rev_polarity_reversed,
157 e1000_rev_polarity_undefined = 0xFF
165 e1000_fc_default = 0xFF
168 /* Statistics counters collected by the MAC */
169 struct e1000_hw_stats {
248 struct e1000_phy_stats {
253 struct e1000_host_mng_dhcp_cookie {
264 /* Host Interface "Rev 1" */
265 struct e1000_host_command_header {
272 #define E1000_HI_MAX_DATA_LENGTH 252
273 struct e1000_host_command_info {
274 struct e1000_host_command_header command_header;
275 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
278 /* Host Interface "Rev 2" */
279 struct e1000_host_mng_command_header {
287 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
288 struct e1000_host_mng_command_info {
289 struct e1000_host_mng_command_header command_header;
290 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
293 #include "e1000_mac.h"
294 #include "e1000_phy.h"
295 #include "e1000_nvm.h"
296 #include "e1000_mbx.h"
298 struct e1000_mac_operations {
299 s32 (*check_for_link)(struct e1000_hw *);
300 s32 (*reset_hw)(struct e1000_hw *);
301 s32 (*init_hw)(struct e1000_hw *);
302 bool (*check_mng_mode)(struct e1000_hw *);
303 s32 (*setup_physical_interface)(struct e1000_hw *);
304 void (*rar_set)(struct e1000_hw *, u8 *, u32);
305 s32 (*read_mac_addr)(struct e1000_hw *);
306 s32 (*get_speed_and_duplex)(struct e1000_hw *, u16 *, u16 *);
309 struct e1000_phy_operations {
310 s32 (*acquire)(struct e1000_hw *);
311 s32 (*check_polarity)(struct e1000_hw *);
312 s32 (*check_reset_block)(struct e1000_hw *);
313 s32 (*force_speed_duplex)(struct e1000_hw *);
314 s32 (*get_cfg_done)(struct e1000_hw *hw);
315 s32 (*get_cable_length)(struct e1000_hw *);
316 s32 (*get_phy_info)(struct e1000_hw *);
317 s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
318 void (*release)(struct e1000_hw *);
319 s32 (*reset)(struct e1000_hw *);
320 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
321 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
322 s32 (*write_reg)(struct e1000_hw *, u32, u16);
325 struct e1000_nvm_operations {
326 s32 (*acquire)(struct e1000_hw *);
327 s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
328 void (*release)(struct e1000_hw *);
329 s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
333 s32 (*get_invariants)(struct e1000_hw *);
334 struct e1000_mac_operations *mac_ops;
335 struct e1000_phy_operations *phy_ops;
336 struct e1000_nvm_operations *nvm_ops;
339 extern const struct e1000_info e1000_82575_info;
341 struct e1000_mac_info {
342 struct e1000_mac_operations ops;
347 enum e1000_mac_type type;
358 /* Maximum size of the MTA register table in all supported adapters */
359 #define MAX_MTA_REG 128
360 u32 mta_shadow[MAX_MTA_REG];
363 u8 forced_speed_duplex;
366 bool arc_subsystem_valid;
367 bool asf_firmware_present;
370 bool disable_hw_init_bits;
371 bool get_link_status;
372 bool ifs_params_forced;
374 bool report_tx_early;
375 bool serdes_has_link;
376 bool tx_pkt_filtering;
379 struct e1000_phy_info {
380 struct e1000_phy_operations ops;
382 enum e1000_phy_type type;
384 enum e1000_1000t_rx_status local_rx;
385 enum e1000_1000t_rx_status remote_rx;
386 enum e1000_ms_type ms_type;
387 enum e1000_ms_type original_ms_type;
388 enum e1000_rev_polarity cable_polarity;
389 enum e1000_smart_speed smart_speed;
393 u32 reset_delay_us; /* in usec */
396 enum e1000_media_type media_type;
398 u16 autoneg_advertised;
401 u16 max_cable_length;
402 u16 min_cable_length;
406 bool disable_polarity_correction;
408 bool polarity_correction;
410 bool speed_downgraded;
411 bool autoneg_wait_to_complete;
414 struct e1000_nvm_info {
415 struct e1000_nvm_operations ops;
417 enum e1000_nvm_type type;
418 enum e1000_nvm_override override;
430 struct e1000_bus_info {
431 enum e1000_bus_type type;
432 enum e1000_bus_speed speed;
433 enum e1000_bus_width width;
441 struct e1000_fc_info {
442 u32 high_water; /* Flow control high-water mark */
443 u32 low_water; /* Flow control low-water mark */
444 u16 pause_time; /* Flow control pause timer */
445 bool send_xon; /* Flow control send XON */
446 bool strict_ieee; /* Strict IEEE mode */
447 enum e1000_fc_mode current_mode; /* Type of flow control */
448 enum e1000_fc_mode requested_mode;
451 struct e1000_mbx_operations {
452 s32 (*init_params)(struct e1000_hw *hw);
453 s32 (*read)(struct e1000_hw *, u32 *, u16, u16);
454 s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
455 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16);
456 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
457 s32 (*check_for_msg)(struct e1000_hw *, u16);
458 s32 (*check_for_ack)(struct e1000_hw *, u16);
459 s32 (*check_for_rst)(struct e1000_hw *, u16);
462 struct e1000_mbx_stats {
471 struct e1000_mbx_info {
472 struct e1000_mbx_operations ops;
473 struct e1000_mbx_stats stats;
479 struct e1000_dev_spec_82575 {
481 bool global_device_reset;
488 u8 __iomem *flash_address;
489 unsigned long io_base;
491 struct e1000_mac_info mac;
492 struct e1000_fc_info fc;
493 struct e1000_phy_info phy;
494 struct e1000_nvm_info nvm;
495 struct e1000_bus_info bus;
496 struct e1000_mbx_info mbx;
497 struct e1000_host_mng_dhcp_cookie mng_cookie;
500 struct e1000_dev_spec_82575 _82575;
504 u16 subsystem_vendor_id;
505 u16 subsystem_device_id;
511 extern struct net_device *igb_get_hw_dev(struct e1000_hw *hw);
512 #define hw_dbg(format, arg...) \
513 netdev_dbg(igb_get_hw_dev(hw), format, ##arg)
515 /* These functions must be implemented by drivers */
516 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
517 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
518 #endif /* _E1000_HW_H_ */