1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/if_ether.h>
29 #include <linux/delay.h>
31 #include "e1000_mac.h"
32 #include "e1000_nvm.h"
35 * igb_raise_eec_clk - Raise EEPROM clock
36 * @hw: pointer to the HW structure
37 * @eecd: pointer to the EEPROM
39 * Enable/Raise the EEPROM clock bit.
41 static void igb_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
43 *eecd = *eecd | E1000_EECD_SK;
44 wr32(E1000_EECD, *eecd);
46 udelay(hw->nvm.delay_usec);
50 * igb_lower_eec_clk - Lower EEPROM clock
51 * @hw: pointer to the HW structure
52 * @eecd: pointer to the EEPROM
54 * Clear/Lower the EEPROM clock bit.
56 static void igb_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
58 *eecd = *eecd & ~E1000_EECD_SK;
59 wr32(E1000_EECD, *eecd);
61 udelay(hw->nvm.delay_usec);
65 * igb_shift_out_eec_bits - Shift data bits our to the EEPROM
66 * @hw: pointer to the HW structure
67 * @data: data to send to the EEPROM
68 * @count: number of bits to shift out
70 * We need to shift 'count' bits out to the EEPROM. So, the value in the
71 * "data" parameter will be shifted out to the EEPROM one bit at a time.
72 * In order to do this, "data" must be broken down into bits.
74 static void igb_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
76 struct e1000_nvm_info *nvm = &hw->nvm;
77 u32 eecd = rd32(E1000_EECD);
80 mask = 0x01 << (count - 1);
81 if (nvm->type == e1000_nvm_eeprom_spi)
82 eecd |= E1000_EECD_DO;
85 eecd &= ~E1000_EECD_DI;
88 eecd |= E1000_EECD_DI;
90 wr32(E1000_EECD, eecd);
93 udelay(nvm->delay_usec);
95 igb_raise_eec_clk(hw, &eecd);
96 igb_lower_eec_clk(hw, &eecd);
101 eecd &= ~E1000_EECD_DI;
102 wr32(E1000_EECD, eecd);
106 * igb_shift_in_eec_bits - Shift data bits in from the EEPROM
107 * @hw: pointer to the HW structure
108 * @count: number of bits to shift in
110 * In order to read a register from the EEPROM, we need to shift 'count' bits
111 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
112 * the EEPROM (setting the SK bit), and then reading the value of the data out
113 * "DO" bit. During this "shifting in" process the data in "DI" bit should
116 static u16 igb_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
122 eecd = rd32(E1000_EECD);
124 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
127 for (i = 0; i < count; i++) {
129 igb_raise_eec_clk(hw, &eecd);
131 eecd = rd32(E1000_EECD);
133 eecd &= ~E1000_EECD_DI;
134 if (eecd & E1000_EECD_DO)
137 igb_lower_eec_clk(hw, &eecd);
144 * igb_poll_eerd_eewr_done - Poll for EEPROM read/write completion
145 * @hw: pointer to the HW structure
146 * @ee_reg: EEPROM flag for polling
148 * Polls the EEPROM status bit for either read or write completion based
149 * upon the value of 'ee_reg'.
151 static s32 igb_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
153 u32 attempts = 100000;
155 s32 ret_val = -E1000_ERR_NVM;
157 for (i = 0; i < attempts; i++) {
158 if (ee_reg == E1000_NVM_POLL_READ)
159 reg = rd32(E1000_EERD);
161 reg = rd32(E1000_EEWR);
163 if (reg & E1000_NVM_RW_REG_DONE) {
175 * igb_acquire_nvm - Generic request for access to EEPROM
176 * @hw: pointer to the HW structure
178 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
179 * Return successful if access grant bit set, else clear the request for
180 * EEPROM access and return -E1000_ERR_NVM (-1).
182 s32 igb_acquire_nvm(struct e1000_hw *hw)
184 u32 eecd = rd32(E1000_EECD);
185 s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
189 wr32(E1000_EECD, eecd | E1000_EECD_REQ);
190 eecd = rd32(E1000_EECD);
193 if (eecd & E1000_EECD_GNT)
196 eecd = rd32(E1000_EECD);
201 eecd &= ~E1000_EECD_REQ;
202 wr32(E1000_EECD, eecd);
203 hw_dbg("Could not acquire NVM grant\n");
204 ret_val = -E1000_ERR_NVM;
211 * igb_standby_nvm - Return EEPROM to standby state
212 * @hw: pointer to the HW structure
214 * Return the EEPROM to a standby state.
216 static void igb_standby_nvm(struct e1000_hw *hw)
218 struct e1000_nvm_info *nvm = &hw->nvm;
219 u32 eecd = rd32(E1000_EECD);
221 if (nvm->type == e1000_nvm_eeprom_spi) {
222 /* Toggle CS to flush commands */
223 eecd |= E1000_EECD_CS;
224 wr32(E1000_EECD, eecd);
226 udelay(nvm->delay_usec);
227 eecd &= ~E1000_EECD_CS;
228 wr32(E1000_EECD, eecd);
230 udelay(nvm->delay_usec);
235 * e1000_stop_nvm - Terminate EEPROM command
236 * @hw: pointer to the HW structure
238 * Terminates the current command by inverting the EEPROM's chip select pin.
240 static void e1000_stop_nvm(struct e1000_hw *hw)
244 eecd = rd32(E1000_EECD);
245 if (hw->nvm.type == e1000_nvm_eeprom_spi) {
247 eecd |= E1000_EECD_CS;
248 igb_lower_eec_clk(hw, &eecd);
253 * igb_release_nvm - Release exclusive access to EEPROM
254 * @hw: pointer to the HW structure
256 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
258 void igb_release_nvm(struct e1000_hw *hw)
264 eecd = rd32(E1000_EECD);
265 eecd &= ~E1000_EECD_REQ;
266 wr32(E1000_EECD, eecd);
270 * igb_ready_nvm_eeprom - Prepares EEPROM for read/write
271 * @hw: pointer to the HW structure
273 * Setups the EEPROM for reading and writing.
275 static s32 igb_ready_nvm_eeprom(struct e1000_hw *hw)
277 struct e1000_nvm_info *nvm = &hw->nvm;
278 u32 eecd = rd32(E1000_EECD);
284 if (nvm->type == e1000_nvm_eeprom_spi) {
285 /* Clear SK and CS */
286 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
287 wr32(E1000_EECD, eecd);
289 timeout = NVM_MAX_RETRY_SPI;
292 * Read "Status Register" repeatedly until the LSB is cleared.
293 * The EEPROM will signal that the command has been completed
294 * by clearing bit 0 of the internal status register. If it's
295 * not cleared within 'timeout', then error out.
298 igb_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
299 hw->nvm.opcode_bits);
300 spi_stat_reg = (u8)igb_shift_in_eec_bits(hw, 8);
301 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
310 hw_dbg("SPI NVM Status error\n");
311 ret_val = -E1000_ERR_NVM;
321 * igb_read_nvm_eerd - Reads EEPROM using EERD register
322 * @hw: pointer to the HW structure
323 * @offset: offset of word in the EEPROM to read
324 * @words: number of words to read
325 * @data: word read from the EEPROM
327 * Reads a 16 bit word from the EEPROM using the EERD register.
329 s32 igb_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
331 struct e1000_nvm_info *nvm = &hw->nvm;
336 * A check for invalid values: offset too large, too many words,
337 * and not enough words.
339 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
341 hw_dbg("nvm parameter(s) out of bounds\n");
342 ret_val = -E1000_ERR_NVM;
346 for (i = 0; i < words; i++) {
347 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
348 E1000_NVM_RW_REG_START;
350 wr32(E1000_EERD, eerd);
351 ret_val = igb_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
355 data[i] = (rd32(E1000_EERD) >>
356 E1000_NVM_RW_REG_DATA);
364 * igb_write_nvm_spi - Write to EEPROM using SPI
365 * @hw: pointer to the HW structure
366 * @offset: offset within the EEPROM to be written to
367 * @words: number of words to write
368 * @data: 16 bit word(s) to be written to the EEPROM
370 * Writes data to EEPROM at offset using SPI interface.
372 * If e1000_update_nvm_checksum is not called after this function , the
373 * EEPROM will most likley contain an invalid checksum.
375 s32 igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
377 struct e1000_nvm_info *nvm = &hw->nvm;
382 * A check for invalid values: offset too large, too many words,
383 * and not enough words.
385 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
387 hw_dbg("nvm parameter(s) out of bounds\n");
388 ret_val = -E1000_ERR_NVM;
392 ret_val = hw->nvm.ops.acquire(hw);
398 while (widx < words) {
399 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
401 ret_val = igb_ready_nvm_eeprom(hw);
407 /* Send the WRITE ENABLE command (8 bit opcode) */
408 igb_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
414 * Some SPI eeproms use the 8th address bit embedded in the
417 if ((nvm->address_bits == 8) && (offset >= 128))
418 write_opcode |= NVM_A8_OPCODE_SPI;
420 /* Send the Write command (8-bit opcode + addr) */
421 igb_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
422 igb_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
425 /* Loop to allow for up to whole page write of eeprom */
426 while (widx < words) {
427 u16 word_out = data[widx];
428 word_out = (word_out >> 8) | (word_out << 8);
429 igb_shift_out_eec_bits(hw, word_out, 16);
432 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
441 hw->nvm.ops.release(hw);
448 * igb_read_part_num - Read device part number
449 * @hw: pointer to the HW structure
450 * @part_num: pointer to device part number
452 * Reads the product board assembly (PBA) number from the EEPROM and stores
453 * the value in part_num.
455 s32 igb_read_part_num(struct e1000_hw *hw, u32 *part_num)
460 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
462 hw_dbg("NVM Read Error\n");
465 *part_num = (u32)(nvm_data << 16);
467 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
469 hw_dbg("NVM Read Error\n");
472 *part_num |= nvm_data;
479 * igb_read_mac_addr - Read device MAC address
480 * @hw: pointer to the HW structure
482 * Reads the device MAC address from the EEPROM and stores the value.
483 * Since devices with two ports use the same EEPROM, we increment the
484 * last bit in the MAC address for the second port.
486 s32 igb_read_mac_addr(struct e1000_hw *hw)
492 rar_high = rd32(E1000_RAH(0));
493 rar_low = rd32(E1000_RAL(0));
495 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
496 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
498 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
499 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
501 for (i = 0; i < ETH_ALEN; i++)
502 hw->mac.addr[i] = hw->mac.perm_addr[i];
508 * igb_validate_nvm_checksum - Validate EEPROM checksum
509 * @hw: pointer to the HW structure
511 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
512 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
514 s32 igb_validate_nvm_checksum(struct e1000_hw *hw)
520 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
521 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
523 hw_dbg("NVM Read Error\n");
526 checksum += nvm_data;
529 if (checksum != (u16) NVM_SUM) {
530 hw_dbg("NVM Checksum Invalid\n");
531 ret_val = -E1000_ERR_NVM;
540 * igb_update_nvm_checksum - Update EEPROM checksum
541 * @hw: pointer to the HW structure
543 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
544 * up to the checksum. Then calculates the EEPROM checksum and writes the
545 * value to the EEPROM.
547 s32 igb_update_nvm_checksum(struct e1000_hw *hw)
553 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
554 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
556 hw_dbg("NVM Read Error while updating checksum.\n");
559 checksum += nvm_data;
561 checksum = (u16) NVM_SUM - checksum;
562 ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
564 hw_dbg("NVM Write Error while updating checksum.\n");