1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
29 /* Linux PRO/1000 Ethernet Driver main header file */
34 #include "e1000_mac.h"
35 #include "e1000_82575.h"
37 #include <linux/clocksource.h>
38 #include <linux/timecompare.h>
39 #include <linux/net_tstamp.h>
43 /* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
44 #define IGB_START_ITR 648
46 /* TX/RX descriptor defines */
47 #define IGB_DEFAULT_TXD 256
48 #define IGB_MIN_TXD 80
49 #define IGB_MAX_TXD 4096
51 #define IGB_DEFAULT_RXD 256
52 #define IGB_MIN_RXD 80
53 #define IGB_MAX_RXD 4096
55 #define IGB_DEFAULT_ITR 3 /* dynamic */
56 #define IGB_MAX_ITR_USECS 10000
57 #define IGB_MIN_ITR_USECS 10
58 #define NON_Q_VECTORS 1
59 #define MAX_Q_VECTORS 8
61 /* Transmit and receive queues */
62 #define IGB_MAX_RX_QUEUES (adapter->vfs_allocated_count ? 2 : \
63 (hw->mac.type > e1000_82575 ? 8 : 4))
64 #define IGB_ABS_MAX_TX_QUEUES 8
65 #define IGB_MAX_TX_QUEUES IGB_MAX_RX_QUEUES
67 #define IGB_MAX_VF_MC_ENTRIES 30
68 #define IGB_MAX_VF_FUNCTIONS 8
69 #define IGB_MAX_VFTA_ENTRIES 128
71 struct vf_data_storage {
72 unsigned char vf_mac_addresses[ETH_ALEN];
73 u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
77 unsigned long last_nack;
78 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
82 #define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */
83 #define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */
84 #define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */
85 #define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */
87 /* RX descriptor control thresholds.
88 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
89 * descriptors available in its onboard memory.
90 * Setting this to 0 disables RX descriptor prefetch.
91 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
92 * available in host memory.
93 * If PTHRESH is 0, this should also be 0.
94 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
95 * descriptors until either it has this many to write back, or the
98 #define IGB_RX_PTHRESH 8
99 #define IGB_RX_HTHRESH 8
100 #define IGB_RX_WTHRESH 1
101 #define IGB_TX_PTHRESH 8
102 #define IGB_TX_HTHRESH 1
103 #define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \
104 adapter->msix_entries) ? 1 : 16)
106 /* this is the size past which hardware will drop packets when setting LPE=0 */
107 #define MAXIMUM_ETHERNET_VLAN_SIZE 1522
109 /* Supported Rx Buffer Sizes */
110 #define IGB_RXBUFFER_128 128 /* Used for packet split */
111 #define IGB_RXBUFFER_1024 1024
112 #define IGB_RXBUFFER_2048 2048
113 #define IGB_RXBUFFER_16384 16384
115 #define MAX_STD_JUMBO_FRAME_SIZE 9234
117 /* How many Tx Descriptors do we need to call netif_wake_queue ? */
118 #define IGB_TX_QUEUE_WAKE 16
119 /* How many Rx Buffers do we bundle into one write to the hardware ? */
120 #define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */
122 #define AUTO_ALL_MODES 0
123 #define IGB_EEPROM_APME 0x0400
125 #ifndef IGB_MASTER_SLAVE
126 /* Switch to override PHY master/slave setting */
127 #define IGB_MASTER_SLAVE e1000_ms_hw_default
130 #define IGB_MNG_VLAN_NONE -1
132 /* wrapper around a pointer to a socket buffer,
133 * so a DMA handle can be stored along with the buffer */
140 unsigned long time_stamp;
155 struct igb_tx_queue_stats {
161 struct igb_rx_queue_stats {
169 struct igb_q_vector {
170 struct igb_adapter *adapter; /* backlink */
171 struct igb_ring *rx_ring;
172 struct igb_ring *tx_ring;
173 struct napi_struct napi;
180 void __iomem *itr_register;
182 char name[IFNAMSIZ + 9];
186 struct igb_q_vector *q_vector; /* backlink to q_vector */
187 struct net_device *netdev; /* back pointer to net_device */
188 struct pci_dev *pdev; /* pci device for dma mapping */
189 dma_addr_t dma; /* phys address of the ring */
190 void *desc; /* descriptor ring memory */
191 unsigned int size; /* length of desc. ring in bytes */
192 u16 count; /* number of desc. in the ring */
199 struct igb_buffer *buffer_info; /* array of buffer info structs */
201 unsigned int total_bytes;
202 unsigned int total_packets;
209 struct igb_tx_queue_stats tx_stats;
214 struct igb_rx_queue_stats rx_stats;
220 #define IGB_RING_FLAG_RX_CSUM 0x00000001 /* RX CSUM enabled */
221 #define IGB_RING_FLAG_RX_SCTP_CSUM 0x00000002 /* SCTP CSUM offload enabled */
223 #define IGB_RING_FLAG_TX_CTX_IDX 0x00000001 /* HW requires context index */
225 #define IGB_ADVTXD_DCMD (E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS)
227 #define E1000_RX_DESC_ADV(R, i) \
228 (&(((union e1000_adv_rx_desc *)((R).desc))[i]))
229 #define E1000_TX_DESC_ADV(R, i) \
230 (&(((union e1000_adv_tx_desc *)((R).desc))[i]))
231 #define E1000_TX_CTXTDESC_ADV(R, i) \
232 (&(((struct e1000_adv_tx_context_desc *)((R).desc))[i]))
234 /* igb_desc_unused - calculate if we have unused descriptors */
235 static inline int igb_desc_unused(struct igb_ring *ring)
237 if (ring->next_to_clean > ring->next_to_use)
238 return ring->next_to_clean - ring->next_to_use - 1;
240 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
243 /* board specific private data structure */
245 struct timer_list watchdog_timer;
246 struct timer_list phy_info_timer;
247 struct vlan_group *vlgrp;
255 /* Interrupt Throttle Rate */
261 struct work_struct reset_task;
262 struct work_struct watchdog_task;
264 u8 tx_timeout_factor;
265 struct timer_list blink_timer;
266 unsigned long led_status;
269 struct igb_ring *tx_ring[16];
270 unsigned long tx_queue_len;
271 u32 tx_timeout_count;
274 struct igb_ring *rx_ring[16];
281 /* OS defined structs */
282 struct net_device *netdev;
283 struct pci_dev *pdev;
284 struct cyclecounter cycles;
285 struct timecounter clock;
286 struct timecompare compare;
287 struct hwtstamp_config hwtstamp_config;
289 /* structs defined in e1000_hw.h */
291 struct e1000_hw_stats stats;
292 struct e1000_phy_info phy_info;
293 struct e1000_phy_stats phy_stats;
296 struct igb_ring test_tx_ring;
297 struct igb_ring test_rx_ring;
301 unsigned int num_q_vectors;
302 struct igb_q_vector *q_vector[MAX_Q_VECTORS];
303 struct msix_entry *msix_entries;
304 u32 eims_enable_mask;
307 /* to not mess up cache alignment, always add to the bottom */
312 struct igb_ring *multi_tx_table[IGB_ABS_MAX_TX_QUEUES];
315 unsigned int vfs_allocated_count;
316 struct vf_data_storage *vf_data;
320 #define IGB_FLAG_HAS_MSI (1 << 0)
321 #define IGB_FLAG_DCA_ENABLED (1 << 1)
322 #define IGB_FLAG_QUAD_PORT_A (1 << 2)
323 #define IGB_FLAG_QUEUE_PAIRS (1 << 3)
325 #define IGB_82576_TSYNC_SHIFT 19
326 #define IGB_82580_TSYNC_SHIFT 24
337 extern char igb_driver_name[];
338 extern char igb_driver_version[];
340 extern char *igb_get_hw_dev_name(struct e1000_hw *hw);
341 extern int igb_up(struct igb_adapter *);
342 extern void igb_down(struct igb_adapter *);
343 extern void igb_reinit_locked(struct igb_adapter *);
344 extern void igb_reset(struct igb_adapter *);
345 extern int igb_set_spd_dplx(struct igb_adapter *, u16);
346 extern int igb_setup_tx_resources(struct igb_ring *);
347 extern int igb_setup_rx_resources(struct igb_ring *);
348 extern void igb_free_tx_resources(struct igb_ring *);
349 extern void igb_free_rx_resources(struct igb_ring *);
350 extern void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *);
351 extern void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *);
352 extern void igb_setup_tctl(struct igb_adapter *);
353 extern void igb_setup_rctl(struct igb_adapter *);
354 extern netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *, struct igb_ring *);
355 extern void igb_unmap_and_free_tx_resource(struct igb_ring *,
356 struct igb_buffer *);
357 extern void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
358 extern void igb_update_stats(struct igb_adapter *);
359 extern bool igb_has_link(struct igb_adapter *adapter);
360 extern void igb_set_ethtool_ops(struct net_device *);
361 extern void igb_power_up_link(struct igb_adapter *);
363 static inline s32 igb_reset_phy(struct e1000_hw *hw)
365 if (hw->phy.ops.reset)
366 return hw->phy.ops.reset(hw);
371 static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
373 if (hw->phy.ops.read_reg)
374 return hw->phy.ops.read_reg(hw, offset, data);
379 static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
381 if (hw->phy.ops.write_reg)
382 return hw->phy.ops.write_reg(hw, offset, data);
387 static inline s32 igb_get_phy_info(struct e1000_hw *hw)
389 if (hw->phy.ops.get_phy_info)
390 return hw->phy.ops.get_phy_info(hw);