drivers/net/igb/igb_main.c

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/module.h>
  29 #include <linux/types.h>
  30 #include <linux/init.h>
  31 #include <linux/vmalloc.h>
  32 #include <linux/pagemap.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/ipv6.h>
  35 #include <net/checksum.h>
  36 #include <net/ip6_checksum.h>
  37 #include <linux/net_tstamp.h>
  38 #include <linux/mii.h>
  39 #include <linux/ethtool.h>
  40 #include <linux/if_vlan.h>
  41 #include <linux/pci.h>
  42 #include <linux/pci-aspm.h>
  43 #include <linux/delay.h>
  44 #include <linux/interrupt.h>
  45 #include <linux/if_ether.h>
  46 #include <linux/aer.h>
  47 #ifdef CONFIG_IGB_DCA
  48 #include <linux/dca.h>
  49 #endif
  50 #include "igb.h"
  51
  52 #define DRV_VERSION "1.3.16-k2"
  53 char igb_driver_name[] = "igb";
  54 char igb_driver_version[] = DRV_VERSION;
  55 static const char igb_driver_string[] =
  56                                 "Intel(R) Gigabit Ethernet Network Driver";
  57 static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
  58
  59 static const struct e1000_info *igb_info_tbl[] = {
  60         [board_82575] = &e1000_82575_info,
  61 };
  62
  63 static struct pci_device_id igb_pci_tbl[] = {
  64         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
  65         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
  66         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
  67         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
  68         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
  69         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
  70         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
  71         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
  72         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
  73         /* required last entry */
  74         {0, }
  75 };
  76
  77 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
  78
  79 void igb_reset(struct igb_adapter *);
  80 static int igb_setup_all_tx_resources(struct igb_adapter *);
  81 static int igb_setup_all_rx_resources(struct igb_adapter *);
  82 static void igb_free_all_tx_resources(struct igb_adapter *);
  83 static void igb_free_all_rx_resources(struct igb_adapter *);
  84 void igb_update_stats(struct igb_adapter *);
  85 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
  86 static void __devexit igb_remove(struct pci_dev *pdev);
  87 static int igb_sw_init(struct igb_adapter *);
  88 static int igb_open(struct net_device *);
  89 static int igb_close(struct net_device *);
  90 static void igb_configure_tx(struct igb_adapter *);
  91 static void igb_configure_rx(struct igb_adapter *);
  92 static void igb_setup_rctl(struct igb_adapter *);
  93 static void igb_clean_all_tx_rings(struct igb_adapter *);
  94 static void igb_clean_all_rx_rings(struct igb_adapter *);
  95 static void igb_clean_tx_ring(struct igb_ring *);
  96 static void igb_clean_rx_ring(struct igb_ring *);
  97 static void igb_set_rx_mode(struct net_device *);
  98 static void igb_update_phy_info(unsigned long);
  99 static void igb_watchdog(unsigned long);
 100 static void igb_watchdog_task(struct work_struct *);
 101 static netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *,
 102                                            struct net_device *,
 103                                            struct igb_ring *);
 104 static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb,
 105                                       struct net_device *);
 106 static struct net_device_stats *igb_get_stats(struct net_device *);
 107 static int igb_change_mtu(struct net_device *, int);
 108 static int igb_set_mac(struct net_device *, void *);
 109 static irqreturn_t igb_intr(int irq, void *);
 110 static irqreturn_t igb_intr_msi(int irq, void *);
 111 static irqreturn_t igb_msix_other(int irq, void *);
 112 static irqreturn_t igb_msix_rx(int irq, void *);
 113 static irqreturn_t igb_msix_tx(int irq, void *);
 114 #ifdef CONFIG_IGB_DCA
 115 static void igb_update_rx_dca(struct igb_ring *);
 116 static void igb_update_tx_dca(struct igb_ring *);
 117 static void igb_setup_dca(struct igb_adapter *);
 118 #endif /* CONFIG_IGB_DCA */
 119 static bool igb_clean_tx_irq(struct igb_ring *);
 120 static int igb_poll(struct napi_struct *, int);
 121 static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
 122 static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
 123 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
 124 static void igb_tx_timeout(struct net_device *);
 125 static void igb_reset_task(struct work_struct *);
 126 static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
 127 static void igb_vlan_rx_add_vid(struct net_device *, u16);
 128 static void igb_vlan_rx_kill_vid(struct net_device *, u16);
 129 static void igb_restore_vlan(struct igb_adapter *);
 130 static void igb_ping_all_vfs(struct igb_adapter *);
 131 static void igb_msg_task(struct igb_adapter *);
 132 static int igb_rcv_msg_from_vf(struct igb_adapter *, u32);
 133 static inline void igb_set_rah_pool(struct e1000_hw *, int , int);
 134 static void igb_vmm_control(struct igb_adapter *);
 135 static int igb_set_vf_mac(struct igb_adapter *adapter, int, unsigned char *);
 136 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
 137
 138 static inline void igb_set_vmolr(struct e1000_hw *hw, int vfn)
 139 {
 140         u32 reg_data;
 141
 142         reg_data = rd32(E1000_VMOLR(vfn));
 143         reg_data |= E1000_VMOLR_BAM |    /* Accept broadcast */
 144                     E1000_VMOLR_ROPE |   /* Accept packets matched in UTA */
 145                     E1000_VMOLR_ROMPE |  /* Accept packets matched in MTA */
 146                     E1000_VMOLR_AUPE |   /* Accept untagged packets */
 147                     E1000_VMOLR_STRVLAN; /* Strip vlan tags */
 148         wr32(E1000_VMOLR(vfn), reg_data);
 149 }
 150
 151 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
 152                                  int vfn)
 153 {
 154         struct e1000_hw *hw = &adapter->hw;
 155         u32 vmolr;
 156
 157         /* if it isn't the PF check to see if VFs are enabled and
 158          * increase the size to support vlan tags */
 159         if (vfn < adapter->vfs_allocated_count &&
 160             adapter->vf_data[vfn].vlans_enabled)
 161                 size += VLAN_TAG_SIZE;
 162
 163         vmolr = rd32(E1000_VMOLR(vfn));
 164         vmolr &= ~E1000_VMOLR_RLPML_MASK;
 165         vmolr |= size | E1000_VMOLR_LPE;
 166         wr32(E1000_VMOLR(vfn), vmolr);
 167
 168         return 0;
 169 }
 170
 171 static inline void igb_set_rah_pool(struct e1000_hw *hw, int pool, int entry)
 172 {
 173         u32 reg_data;
 174
 175         reg_data = rd32(E1000_RAH(entry));
 176         reg_data &= ~E1000_RAH_POOL_MASK;
 177         reg_data |= E1000_RAH_POOL_1 << pool;;
 178         wr32(E1000_RAH(entry), reg_data);
 179 }
 180
 181 #ifdef CONFIG_PM
 182 static int igb_suspend(struct pci_dev *, pm_message_t);
 183 static int igb_resume(struct pci_dev *);
 184 #endif
 185 static void igb_shutdown(struct pci_dev *);
 186 #ifdef CONFIG_IGB_DCA
 187 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
 188 static struct notifier_block dca_notifier = {
 189         .notifier_call  = igb_notify_dca,
 190         .next           = NULL,
 191         .priority       = 0
 192 };
 193 #endif
 194 #ifdef CONFIG_NET_POLL_CONTROLLER
 195 /* for netdump / net console */
 196 static void igb_netpoll(struct net_device *);
 197 #endif
 198 #ifdef CONFIG_PCI_IOV
 199 static unsigned int max_vfs = 0;
 200 module_param(max_vfs, uint, 0);
 201 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
 202                  "per physical function");
 203 #endif /* CONFIG_PCI_IOV */
 204
 205 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
 206                      pci_channel_state_t);
 207 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
 208 static void igb_io_resume(struct pci_dev *);
 209
 210 static struct pci_error_handlers igb_err_handler = {
 211         .error_detected = igb_io_error_detected,
 212         .slot_reset = igb_io_slot_reset,
 213         .resume = igb_io_resume,
 214 };
 215
 216
 217 static struct pci_driver igb_driver = {
 218         .name     = igb_driver_name,
 219         .id_table = igb_pci_tbl,
 220         .probe    = igb_probe,
 221         .remove   = __devexit_p(igb_remove),
 222 #ifdef CONFIG_PM
 223         /* Power Managment Hooks */
 224         .suspend  = igb_suspend,
 225         .resume   = igb_resume,
 226 #endif
 227         .shutdown = igb_shutdown,
 228         .err_handler = &igb_err_handler
 229 };
 230
 231 static int global_quad_port_a; /* global quad port a indication */
 232
 233 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
 234 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
 235 MODULE_LICENSE("GPL");
 236 MODULE_VERSION(DRV_VERSION);
 237
 238 /**
 239  * Scale the NIC clock cycle by a large factor so that
 240  * relatively small clock corrections can be added or
 241  * substracted at each clock tick. The drawbacks of a
 242  * large factor are a) that the clock register overflows
 243  * more quickly (not such a big deal) and b) that the
 244  * increment per tick has to fit into 24 bits.
 245  *
 246  * Note that
 247  *   TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS *
 248  *             IGB_TSYNC_SCALE
 249  *   TIMINCA += TIMINCA * adjustment [ppm] / 1e9
 250  *
 251  * The base scale factor is intentionally a power of two
 252  * so that the division in %struct timecounter can be done with
 253  * a shift.
 254  */
 255 #define IGB_TSYNC_SHIFT (19)
 256 #define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT)
 257
 258 /**
 259  * The duration of one clock cycle of the NIC.
 260  *
 261  * @todo This hard-coded value is part of the specification and might change
 262  * in future hardware revisions. Add revision check.
 263  */
 264 #define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16
 265
 266 #if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24)
 267 # error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA
 268 #endif
 269
 270 /**
 271  * igb_read_clock - read raw cycle counter (to be used by time counter)
 272  */
 273 static cycle_t igb_read_clock(const struct cyclecounter *tc)
 274 {
 275         struct igb_adapter *adapter =
 276                 container_of(tc, struct igb_adapter, cycles);
 277         struct e1000_hw *hw = &adapter->hw;
 278         u64 stamp;
 279
 280         stamp =  rd32(E1000_SYSTIML);
 281         stamp |= (u64)rd32(E1000_SYSTIMH) << 32ULL;
 282
 283         return stamp;
 284 }
 285
 286 #ifdef DEBUG
 287 /**
 288  * igb_get_hw_dev_name - return device name string
 289  * used by hardware layer to print debugging information
 290  **/
 291 char *igb_get_hw_dev_name(struct e1000_hw *hw)
 292 {
 293         struct igb_adapter *adapter = hw->back;
 294         return adapter->netdev->name;
 295 }
 296
 297 /**
 298  * igb_get_time_str - format current NIC and system time as string
 299  */
 300 static char *igb_get_time_str(struct igb_adapter *adapter,
 301                               char buffer[160])
 302 {
 303         cycle_t hw = adapter->cycles.read(&adapter->cycles);
 304         struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock));
 305         struct timespec sys;
 306         struct timespec delta;
 307         getnstimeofday(&sys);
 308
 309         delta = timespec_sub(nic, sys);
 310
 311         sprintf(buffer,
 312                 "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
 313                 hw,
 314                 (long)nic.tv_sec, nic.tv_nsec,
 315                 (long)sys.tv_sec, sys.tv_nsec,
 316                 (long)delta.tv_sec, delta.tv_nsec);
 317
 318         return buffer;
 319 }
 320 #endif
 321
 322 /**
 323  * igb_desc_unused - calculate if we have unused descriptors
 324  **/
 325 static int igb_desc_unused(struct igb_ring *ring)
 326 {
 327         if (ring->next_to_clean > ring->next_to_use)
 328                 return ring->next_to_clean - ring->next_to_use - 1;
 329
 330         return ring->count + ring->next_to_clean - ring->next_to_use - 1;
 331 }
 332
 333 /**
 334  * igb_init_module - Driver Registration Routine
 335  *
 336  * igb_init_module is the first routine called when the driver is
 337  * loaded. All it does is register with the PCI subsystem.
 338  **/
 339 static int __init igb_init_module(void)
 340 {
 341         int ret;
 342         printk(KERN_INFO "%s - version %s\n",
 343                igb_driver_string, igb_driver_version);
 344
 345         printk(KERN_INFO "%s\n", igb_copyright);
 346
 347         global_quad_port_a = 0;
 348
 349 #ifdef CONFIG_IGB_DCA
 350         dca_register_notify(&dca_notifier);
 351 #endif
 352
 353         ret = pci_register_driver(&igb_driver);
 354         return ret;
 355 }
 356
 357 module_init(igb_init_module);
 358
 359 /**
 360  * igb_exit_module - Driver Exit Cleanup Routine
 361  *
 362  * igb_exit_module is called just before the driver is removed
 363  * from memory.
 364  **/
 365 static void __exit igb_exit_module(void)
 366 {
 367 #ifdef CONFIG_IGB_DCA
 368         dca_unregister_notify(&dca_notifier);
 369 #endif
 370         pci_unregister_driver(&igb_driver);
 371 }
 372
 373 module_exit(igb_exit_module);
 374
 375 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
 376 /**
 377  * igb_cache_ring_register - Descriptor ring to register mapping
 378  * @adapter: board private structure to initialize
 379  *
 380  * Once we know the feature-set enabled for the device, we'll cache
 381  * the register offset the descriptor ring is assigned to.
 382  **/
 383 static void igb_cache_ring_register(struct igb_adapter *adapter)
 384 {
 385         int i;
 386         unsigned int rbase_offset = adapter->vfs_allocated_count;
 387
 388         switch (adapter->hw.mac.type) {
 389         case e1000_82576:
 390                 /* The queues are allocated for virtualization such that VF 0
 391                  * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
 392                  * In order to avoid collision we start at the first free queue
 393                  * and continue consuming queues in the same sequence
 394                  */
 395                 for (i = 0; i < adapter->num_rx_queues; i++)
 396                         adapter->rx_ring[i].reg_idx = rbase_offset +
 397                                                       Q_IDX_82576(i);
 398                 for (i = 0; i < adapter->num_tx_queues; i++)
 399                         adapter->tx_ring[i].reg_idx = rbase_offset +
 400                                                       Q_IDX_82576(i);
 401                 break;
 402         case e1000_82575:
 403         default:
 404                 for (i = 0; i < adapter->num_rx_queues; i++)
 405                         adapter->rx_ring[i].reg_idx = i;
 406                 for (i = 0; i < adapter->num_tx_queues; i++)
 407                         adapter->tx_ring[i].reg_idx = i;
 408                 break;
 409         }
 410 }
 411
 412 /**
 413  * igb_alloc_queues - Allocate memory for all rings
 414  * @adapter: board private structure to initialize
 415  *
 416  * We allocate one ring per queue at run-time since we don't know the
 417  * number of queues at compile-time.
 418  **/
 419 static int igb_alloc_queues(struct igb_adapter *adapter)
 420 {
 421         int i;
 422
 423         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
 424                                    sizeof(struct igb_ring), GFP_KERNEL);
 425         if (!adapter->tx_ring)
 426                 return -ENOMEM;
 427
 428         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
 429                                    sizeof(struct igb_ring), GFP_KERNEL);
 430         if (!adapter->rx_ring) {
 431                 kfree(adapter->tx_ring);
 432                 return -ENOMEM;
 433         }
 434
 435         adapter->rx_ring->buddy = adapter->tx_ring;
 436
 437         for (i = 0; i < adapter->num_tx_queues; i++) {
 438                 struct igb_ring *ring = &(adapter->tx_ring[i]);
 439                 ring->count = adapter->tx_ring_count;
 440                 ring->adapter = adapter;
 441                 ring->queue_index = i;
 442         }
 443         for (i = 0; i < adapter->num_rx_queues; i++) {
 444                 struct igb_ring *ring = &(adapter->rx_ring[i]);
 445                 ring->count = adapter->rx_ring_count;
 446                 ring->adapter = adapter;
 447                 ring->queue_index = i;
 448                 ring->itr_register = E1000_ITR;
 449
 450                 /* set a default napi handler for each rx_ring */
 451                 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
 452         }
 453
 454         igb_cache_ring_register(adapter);
 455         return 0;
 456 }
 457
 458 static void igb_free_queues(struct igb_adapter *adapter)
 459 {
 460         int i;
 461
 462         for (i = 0; i < adapter->num_rx_queues; i++)
 463                 netif_napi_del(&adapter->rx_ring[i].napi);
 464
 465         adapter->num_rx_queues = 0;
 466         adapter->num_tx_queues = 0;
 467
 468         kfree(adapter->tx_ring);
 469         kfree(adapter->rx_ring);
 470 }
 471
 472 #define IGB_N0_QUEUE -1
 473 static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
 474                               int tx_queue, int msix_vector)
 475 {
 476         u32 msixbm = 0;
 477         struct e1000_hw *hw = &adapter->hw;
 478         u32 ivar, index;
 479
 480         switch (hw->mac.type) {
 481         case e1000_82575:
 482                 /* The 82575 assigns vectors using a bitmask, which matches the
 483                    bitmask for the EICR/EIMS/EIMC registers.  To assign one
 484                    or more queues to a vector, we write the appropriate bits
 485                    into the MSIXBM register for that vector. */
 486                 if (rx_queue > IGB_N0_QUEUE) {
 487                         msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
 488                         adapter->rx_ring[rx_queue].eims_value = msixbm;
 489                 }
 490                 if (tx_queue > IGB_N0_QUEUE) {
 491                         msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
 492                         adapter->tx_ring[tx_queue].eims_value =
 493                                   E1000_EICR_TX_QUEUE0 << tx_queue;
 494                 }
 495                 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
 496                 break;
 497         case e1000_82576:
 498                 /* 82576 uses a table-based method for assigning vectors.
 499                    Each queue has a single entry in the table to which we write
 500                    a vector number along with a "valid" bit.  Sadly, the layout
 501                    of the table is somewhat counterintuitive. */
 502                 if (rx_queue > IGB_N0_QUEUE) {
 503                         index = (rx_queue >> 1) + adapter->vfs_allocated_count;
 504                         ivar = array_rd32(E1000_IVAR0, index);
 505                         if (rx_queue & 0x1) {
 506                                 /* vector goes into third byte of register */
 507                                 ivar = ivar & 0xFF00FFFF;
 508                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
 509                         } else {
 510                                 /* vector goes into low byte of register */
 511                                 ivar = ivar & 0xFFFFFF00;
 512                                 ivar |= msix_vector | E1000_IVAR_VALID;
 513                         }
 514                         adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
 515                         array_wr32(E1000_IVAR0, index, ivar);
 516                 }
 517                 if (tx_queue > IGB_N0_QUEUE) {
 518                         index = (tx_queue >> 1) + adapter->vfs_allocated_count;
 519                         ivar = array_rd32(E1000_IVAR0, index);
 520                         if (tx_queue & 0x1) {
 521                                 /* vector goes into high byte of register */
 522                                 ivar = ivar & 0x00FFFFFF;
 523                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
 524                         } else {
 525                                 /* vector goes into second byte of register */
 526                                 ivar = ivar & 0xFFFF00FF;
 527                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
 528                         }
 529                         adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
 530                         array_wr32(E1000_IVAR0, index, ivar);
 531                 }
 532                 break;
 533         default:
 534                 BUG();
 535                 break;
 536         }
 537 }
 538
 539 /**
 540  * igb_configure_msix - Configure MSI-X hardware
 541  *
 542  * igb_configure_msix sets up the hardware to properly
 543  * generate MSI-X interrupts.
 544  **/
 545 static void igb_configure_msix(struct igb_adapter *adapter)
 546 {
 547         u32 tmp;
 548         int i, vector = 0;
 549         struct e1000_hw *hw = &adapter->hw;
 550
 551         adapter->eims_enable_mask = 0;
 552         if (hw->mac.type == e1000_82576)
 553                 /* Turn on MSI-X capability first, or our settings
 554                  * won't stick.  And it will take days to debug. */
 555                 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
 556                                    E1000_GPIE_PBA | E1000_GPIE_EIAME |
 557                                    E1000_GPIE_NSICR);
 558
 559         for (i = 0; i < adapter->num_tx_queues; i++) {
 560                 struct igb_ring *tx_ring = &adapter->tx_ring[i];
 561                 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
 562                 adapter->eims_enable_mask |= tx_ring->eims_value;
 563                 if (tx_ring->itr_val)
 564                         writel(tx_ring->itr_val,
 565                                hw->hw_addr + tx_ring->itr_register);
 566                 else
 567                         writel(1, hw->hw_addr + tx_ring->itr_register);
 568         }
 569
 570         for (i = 0; i < adapter->num_rx_queues; i++) {
 571                 struct igb_ring *rx_ring = &adapter->rx_ring[i];
 572                 rx_ring->buddy = NULL;
 573                 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
 574                 adapter->eims_enable_mask |= rx_ring->eims_value;
 575                 if (rx_ring->itr_val)
 576                         writel(rx_ring->itr_val,
 577                                hw->hw_addr + rx_ring->itr_register);
 578                 else
 579                         writel(1, hw->hw_addr + rx_ring->itr_register);
 580         }
 581
 582
 583         /* set vector for other causes, i.e. link changes */
 584         switch (hw->mac.type) {
 585         case e1000_82575:
 586                 array_wr32(E1000_MSIXBM(0), vector++,
 587                                       E1000_EIMS_OTHER);
 588
 589                 tmp = rd32(E1000_CTRL_EXT);
 590                 /* enable MSI-X PBA support*/
 591                 tmp |= E1000_CTRL_EXT_PBA_CLR;
 592
 593                 /* Auto-Mask interrupts upon ICR read. */
 594                 tmp |= E1000_CTRL_EXT_EIAME;
 595                 tmp |= E1000_CTRL_EXT_IRCA;
 596
 597                 wr32(E1000_CTRL_EXT, tmp);
 598                 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
 599                 adapter->eims_other = E1000_EIMS_OTHER;
 600
 601                 break;
 602
 603         case e1000_82576:
 604                 tmp = (vector++ | E1000_IVAR_VALID) << 8;
 605                 wr32(E1000_IVAR_MISC, tmp);
 606
 607                 adapter->eims_enable_mask = (1 << (vector)) - 1;
 608                 adapter->eims_other = 1 << (vector - 1);
 609                 break;
 610         default:
 611                 /* do nothing, since nothing else supports MSI-X */
 612                 break;
 613         } /* switch (hw->mac.type) */
 614         wrfl();
 615 }
 616
 617 /**
 618  * igb_request_msix - Initialize MSI-X interrupts
 619  *
 620  * igb_request_msix allocates MSI-X vectors and requests interrupts from the
 621  * kernel.
 622  **/
 623 static int igb_request_msix(struct igb_adapter *adapter)
 624 {
 625         struct net_device *netdev = adapter->netdev;
 626         int i, err = 0, vector = 0;
 627
 628         vector = 0;
 629
 630         for (i = 0; i < adapter->num_tx_queues; i++) {
 631                 struct igb_ring *ring = &(adapter->tx_ring[i]);
 632                 sprintf(ring->name, "%s-tx-%d", netdev->name, i);
 633                 err = request_irq(adapter->msix_entries[vector].vector,
 634                                   &igb_msix_tx, 0, ring->name,
 635                                   &(adapter->tx_ring[i]));
 636                 if (err)
 637                         goto out;
 638                 ring->itr_register = E1000_EITR(0) + (vector << 2);
 639                 ring->itr_val = 976; /* ~4000 ints/sec */
 640                 vector++;
 641         }
 642         for (i = 0; i < adapter->num_rx_queues; i++) {
 643                 struct igb_ring *ring = &(adapter->rx_ring[i]);
 644                 if (strlen(netdev->name) < (IFNAMSIZ - 5))
 645                         sprintf(ring->name, "%s-rx-%d", netdev->name, i);
 646                 else
 647                         memcpy(ring->name, netdev->name, IFNAMSIZ);
 648                 err = request_irq(adapter->msix_entries[vector].vector,
 649                                   &igb_msix_rx, 0, ring->name,
 650                                   &(adapter->rx_ring[i]));
 651                 if (err)
 652                         goto out;
 653                 ring->itr_register = E1000_EITR(0) + (vector << 2);
 654                 ring->itr_val = adapter->itr;
 655                 vector++;
 656         }
 657
 658         err = request_irq(adapter->msix_entries[vector].vector,
 659                           &igb_msix_other, 0, netdev->name, netdev);
 660         if (err)
 661                 goto out;
 662
 663         igb_configure_msix(adapter);
 664         return 0;
 665 out:
 666         return err;
 667 }
 668
 669 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
 670 {
 671         if (adapter->msix_entries) {
 672                 pci_disable_msix(adapter->pdev);
 673                 kfree(adapter->msix_entries);
 674                 adapter->msix_entries = NULL;
 675         } else if (adapter->flags & IGB_FLAG_HAS_MSI)
 676                 pci_disable_msi(adapter->pdev);
 677         return;
 678 }
 679
 680
 681 /**
 682  * igb_set_interrupt_capability - set MSI or MSI-X if supported
 683  *
 684  * Attempt to configure interrupts using the best available
 685  * capabilities of the hardware and kernel.
 686  **/
 687 static void igb_set_interrupt_capability(struct igb_adapter *adapter)
 688 {
 689         int err;
 690         int numvecs, i;
 691
 692         /* Number of supported queues. */
 693         /* Having more queues than CPUs doesn't make sense. */
 694         adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
 695         adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
 696
 697         numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
 698         adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
 699                                         GFP_KERNEL);
 700         if (!adapter->msix_entries)
 701                 goto msi_only;
 702
 703         for (i = 0; i < numvecs; i++)
 704                 adapter->msix_entries[i].entry = i;
 705
 706         err = pci_enable_msix(adapter->pdev,
 707                               adapter->msix_entries,
 708                               numvecs);
 709         if (err == 0)
 710                 goto out;
 711
 712         igb_reset_interrupt_capability(adapter);
 713
 714         /* If we can't do MSI-X, try MSI */
 715 msi_only:
 716 #ifdef CONFIG_PCI_IOV
 717         /* disable SR-IOV for non MSI-X configurations */
 718         if (adapter->vf_data) {
 719                 struct e1000_hw *hw = &adapter->hw;
 720                 /* disable iov and allow time for transactions to clear */
 721                 pci_disable_sriov(adapter->pdev);
 722                 msleep(500);
 723
 724                 kfree(adapter->vf_data);
 725                 adapter->vf_data = NULL;
 726                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
 727                 msleep(100);
 728                 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
 729         }
 730 #endif
 731         adapter->num_rx_queues = 1;
 732         adapter->num_tx_queues = 1;
 733         if (!pci_enable_msi(adapter->pdev))
 734                 adapter->flags |= IGB_FLAG_HAS_MSI;
 735 out:
 736         /* Notify the stack of the (possibly) reduced Tx Queue count. */
 737         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
 738         return;
 739 }
 740
 741 /**
 742  * igb_request_irq - initialize interrupts
 743  *
 744  * Attempts to configure interrupts using the best available
 745  * capabilities of the hardware and kernel.
 746  **/
 747 static int igb_request_irq(struct igb_adapter *adapter)
 748 {
 749         struct net_device *netdev = adapter->netdev;
 750         struct e1000_hw *hw = &adapter->hw;
 751         int err = 0;
 752
 753         if (adapter->msix_entries) {
 754                 err = igb_request_msix(adapter);
 755                 if (!err)
 756                         goto request_done;
 757                 /* fall back to MSI */
 758                 igb_reset_interrupt_capability(adapter);
 759                 if (!pci_enable_msi(adapter->pdev))
 760                         adapter->flags |= IGB_FLAG_HAS_MSI;
 761                 igb_free_all_tx_resources(adapter);
 762                 igb_free_all_rx_resources(adapter);
 763                 adapter->num_rx_queues = 1;
 764                 igb_alloc_queues(adapter);
 765         } else {
 766                 switch (hw->mac.type) {
 767                 case e1000_82575:
 768                         wr32(E1000_MSIXBM(0),
 769                              (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
 770                         break;
 771                 case e1000_82576:
 772                         wr32(E1000_IVAR0, E1000_IVAR_VALID);
 773                         break;
 774                 default:
 775                         break;
 776                 }
 777         }
 778
 779         if (adapter->flags & IGB_FLAG_HAS_MSI) {
 780                 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
 781                                   netdev->name, netdev);
 782                 if (!err)
 783                         goto request_done;
 784                 /* fall back to legacy interrupts */
 785                 igb_reset_interrupt_capability(adapter);
 786                 adapter->flags &= ~IGB_FLAG_HAS_MSI;
 787         }
 788
 789         err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
 790                           netdev->name, netdev);
 791
 792         if (err)
 793                 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
 794                         err);
 795
 796 request_done:
 797         return err;
 798 }
 799
 800 static void igb_free_irq(struct igb_adapter *adapter)
 801 {
 802         struct net_device *netdev = adapter->netdev;
 803
 804         if (adapter->msix_entries) {
 805                 int vector = 0, i;
 806
 807                 for (i = 0; i < adapter->num_tx_queues; i++)
 808                         free_irq(adapter->msix_entries[vector++].vector,
 809                                 &(adapter->tx_ring[i]));
 810                 for (i = 0; i < adapter->num_rx_queues; i++)
 811                         free_irq(adapter->msix_entries[vector++].vector,
 812                                 &(adapter->rx_ring[i]));
 813
 814                 free_irq(adapter->msix_entries[vector++].vector, netdev);
 815                 return;
 816         }
 817
 818         free_irq(adapter->pdev->irq, netdev);
 819 }
 820
 821 /**
 822  * igb_irq_disable - Mask off interrupt generation on the NIC
 823  * @adapter: board private structure
 824  **/
 825 static void igb_irq_disable(struct igb_adapter *adapter)
 826 {
 827         struct e1000_hw *hw = &adapter->hw;
 828
 829         if (adapter->msix_entries) {
 830                 u32 regval = rd32(E1000_EIAM);
 831                 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
 832                 wr32(E1000_EIMC, adapter->eims_enable_mask);
 833                 regval = rd32(E1000_EIAC);
 834                 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
 835         }
 836
 837         wr32(E1000_IAM, 0);
 838         wr32(E1000_IMC, ~0);
 839         wrfl();
 840         synchronize_irq(adapter->pdev->irq);
 841 }
 842
 843 /**
 844  * igb_irq_enable - Enable default interrupt generation settings
 845  * @adapter: board private structure
 846  **/
 847 static void igb_irq_enable(struct igb_adapter *adapter)
 848 {
 849         struct e1000_hw *hw = &adapter->hw;
 850
 851         if (adapter->msix_entries) {
 852                 u32 regval = rd32(E1000_EIAC);
 853                 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
 854                 regval = rd32(E1000_EIAM);
 855                 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
 856                 wr32(E1000_EIMS, adapter->eims_enable_mask);
 857                 if (adapter->vfs_allocated_count)
 858                         wr32(E1000_MBVFIMR, 0xFF);
 859                 wr32(E1000_IMS, (E1000_IMS_LSC | E1000_IMS_VMMB |
 860                                  E1000_IMS_DOUTSYNC));
 861         } else {
 862                 wr32(E1000_IMS, IMS_ENABLE_MASK);
 863                 wr32(E1000_IAM, IMS_ENABLE_MASK);
 864         }
 865 }
 866
 867 static void igb_update_mng_vlan(struct igb_adapter *adapter)
 868 {
 869         struct net_device *netdev = adapter->netdev;
 870         u16 vid = adapter->hw.mng_cookie.vlan_id;
 871         u16 old_vid = adapter->mng_vlan_id;
 872         if (adapter->vlgrp) {
 873                 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
 874                         if (adapter->hw.mng_cookie.status &
 875                                 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
 876                                 igb_vlan_rx_add_vid(netdev, vid);
 877                                 adapter->mng_vlan_id = vid;
 878                         } else
 879                                 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
 880
 881                         if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
 882                                         (vid != old_vid) &&
 883                             !vlan_group_get_device(adapter->vlgrp, old_vid))
 884                                 igb_vlan_rx_kill_vid(netdev, old_vid);
 885                 } else
 886                         adapter->mng_vlan_id = vid;
 887         }
 888 }
 889
 890 /**
 891  * igb_release_hw_control - release control of the h/w to f/w
 892  * @adapter: address of board private structure
 893  *
 894  * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
 895  * For ASF and Pass Through versions of f/w this means that the
 896  * driver is no longer loaded.
 897  *
 898  **/
 899 static void igb_release_hw_control(struct igb_adapter *adapter)
 900 {
 901         struct e1000_hw *hw = &adapter->hw;
 902         u32 ctrl_ext;
 903
 904         /* Let firmware take over control of h/w */
 905         ctrl_ext = rd32(E1000_CTRL_EXT);
 906         wr32(E1000_CTRL_EXT,
 907                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
 908 }
 909
 910
 911 /**
 912  * igb_get_hw_control - get control of the h/w from f/w
 913  * @adapter: address of board private structure
 914  *
 915  * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
 916  * For ASF and Pass Through versions of f/w this means that
 917  * the driver is loaded.
 918  *
 919  **/
 920 static void igb_get_hw_control(struct igb_adapter *adapter)
 921 {
 922         struct e1000_hw *hw = &adapter->hw;
 923         u32 ctrl_ext;
 924
 925         /* Let firmware know the driver has taken over */
 926         ctrl_ext = rd32(E1000_CTRL_EXT);
 927         wr32(E1000_CTRL_EXT,
 928                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
 929 }
 930
 931 /**
 932  * igb_configure - configure the hardware for RX and TX
 933  * @adapter: private board structure
 934  **/
 935 static void igb_configure(struct igb_adapter *adapter)
 936 {
 937         struct net_device *netdev = adapter->netdev;
 938         int i;
 939
 940         igb_get_hw_control(adapter);
 941         igb_set_rx_mode(netdev);
 942
 943         igb_restore_vlan(adapter);
 944
 945         igb_configure_tx(adapter);
 946         igb_setup_rctl(adapter);
 947         igb_configure_rx(adapter);
 948
 949         igb_rx_fifo_flush_82575(&adapter->hw);
 950
 951         /* call igb_desc_unused which always leaves
 952          * at least 1 descriptor unused to make sure
 953          * next_to_use != next_to_clean */
 954         for (i = 0; i < adapter->num_rx_queues; i++) {
 955                 struct igb_ring *ring = &adapter->rx_ring[i];
 956                 igb_alloc_rx_buffers_adv(ring, igb_desc_unused(ring));
 957         }
 958
 959
 960         adapter->tx_queue_len = netdev->tx_queue_len;
 961 }
 962
 963
 964 /**
 965  * igb_up - Open the interface and prepare it to handle traffic
 966  * @adapter: board private structure
 967  **/
 968
 969 int igb_up(struct igb_adapter *adapter)
 970 {
 971         struct e1000_hw *hw = &adapter->hw;
 972         int i;
 973
 974         /* hardware has been reset, we need to reload some things */
 975         igb_configure(adapter);
 976
 977         clear_bit(__IGB_DOWN, &adapter->state);
 978
 979         for (i = 0; i < adapter->num_rx_queues; i++)
 980                 napi_enable(&adapter->rx_ring[i].napi);
 981         if (adapter->msix_entries)
 982                 igb_configure_msix(adapter);
 983
 984         igb_vmm_control(adapter);
 985         igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
 986         igb_set_vmolr(hw, adapter->vfs_allocated_count);
 987
 988         /* Clear any pending interrupts. */
 989         rd32(E1000_ICR);
 990         igb_irq_enable(adapter);
 991
 992         netif_tx_start_all_queues(adapter->netdev);
 993
 994         /* Fire a link change interrupt to start the watchdog. */
 995         wr32(E1000_ICS, E1000_ICS_LSC);
 996         return 0;
 997 }
 998
 999 void igb_down(struct igb_adapter *adapter)
1000 {
1001         struct e1000_hw *hw = &adapter->hw;
1002         struct net_device *netdev = adapter->netdev;
1003         u32 tctl, rctl;
1004         int i;
1005
1006         /* signal that we're down so the interrupt handler does not
1007          * reschedule our watchdog timer */
1008         set_bit(__IGB_DOWN, &adapter->state);
1009
1010         /* disable receives in the hardware */
1011         rctl = rd32(E1000_RCTL);
1012         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1013         /* flush and sleep below */
1014
1015         netif_tx_stop_all_queues(netdev);
1016
1017         /* disable transmits in the hardware */
1018         tctl = rd32(E1000_TCTL);
1019         tctl &= ~E1000_TCTL_EN;
1020         wr32(E1000_TCTL, tctl);
1021         /* flush both disables and wait for them to finish */
1022         wrfl();
1023         msleep(10);
1024
1025         for (i = 0; i < adapter->num_rx_queues; i++)
1026                 napi_disable(&adapter->rx_ring[i].napi);
1027
1028         igb_irq_disable(adapter);
1029
1030         del_timer_sync(&adapter->watchdog_timer);
1031         del_timer_sync(&adapter->phy_info_timer);
1032
1033         netdev->tx_queue_len = adapter->tx_queue_len;
1034         netif_carrier_off(netdev);
1035
1036         /* record the stats before reset*/
1037         igb_update_stats(adapter);
1038
1039         adapter->link_speed = 0;
1040         adapter->link_duplex = 0;
1041
1042         if (!pci_channel_offline(adapter->pdev))
1043                 igb_reset(adapter);
1044         igb_clean_all_tx_rings(adapter);
1045         igb_clean_all_rx_rings(adapter);
1046 #ifdef CONFIG_IGB_DCA
1047
1048         /* since we reset the hardware DCA settings were cleared */
1049         igb_setup_dca(adapter);
1050 #endif
1051 }
1052
1053 void igb_reinit_locked(struct igb_adapter *adapter)
1054 {
1055         WARN_ON(in_interrupt());
1056         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1057                 msleep(1);
1058         igb_down(adapter);
1059         igb_up(adapter);
1060         clear_bit(__IGB_RESETTING, &adapter->state);
1061 }
1062
1063 void igb_reset(struct igb_adapter *adapter)
1064 {
1065         struct e1000_hw *hw = &adapter->hw;
1066         struct e1000_mac_info *mac = &hw->mac;
1067         struct e1000_fc_info *fc = &hw->fc;
1068         u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1069         u16 hwm;
1070
1071         /* Repartition Pba for greater than 9k mtu
1072          * To take effect CTRL.RST is required.
1073          */
1074         switch (mac->type) {
1075         case e1000_82576:
1076                 pba = E1000_PBA_64K;
1077                 break;
1078         case e1000_82575:
1079         default:
1080                 pba = E1000_PBA_34K;
1081                 break;
1082         }
1083
1084         if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1085             (mac->type < e1000_82576)) {
1086                 /* adjust PBA for jumbo frames */
1087                 wr32(E1000_PBA, pba);
1088
1089                 /* To maintain wire speed transmits, the Tx FIFO should be
1090                  * large enough to accommodate two full transmit packets,
1091                  * rounded up to the next 1KB and expressed in KB.  Likewise,
1092                  * the Rx FIFO should be large enough to accommodate at least
1093                  * one full receive packet and is similarly rounded up and
1094                  * expressed in KB. */
1095                 pba = rd32(E1000_PBA);
1096                 /* upper 16 bits has Tx packet buffer allocation size in KB */
1097                 tx_space = pba >> 16;
1098                 /* lower 16 bits has Rx packet buffer allocation size in KB */
1099                 pba &= 0xffff;
1100                 /* the tx fifo also stores 16 bytes of information about the tx
1101                  * but don't include ethernet FCS because hardware appends it */
1102                 min_tx_space = (adapter->max_frame_size +
1103                                 sizeof(union e1000_adv_tx_desc) -
1104                                 ETH_FCS_LEN) * 2;
1105                 min_tx_space = ALIGN(min_tx_space, 1024);
1106                 min_tx_space >>= 10;
1107                 /* software strips receive CRC, so leave room for it */
1108                 min_rx_space = adapter->max_frame_size;
1109                 min_rx_space = ALIGN(min_rx_space, 1024);
1110                 min_rx_space >>= 10;
1111
1112                 /* If current Tx allocation is less than the min Tx FIFO size,
1113                  * and the min Tx FIFO size is less than the current Rx FIFO
1114                  * allocation, take space away from current Rx allocation */
1115                 if (tx_space < min_tx_space &&
1116                     ((min_tx_space - tx_space) < pba)) {
1117                         pba = pba - (min_tx_space - tx_space);
1118
1119                         /* if short on rx space, rx wins and must trump tx
1120                          * adjustment */
1121                         if (pba < min_rx_space)
1122                                 pba = min_rx_space;
1123                 }
1124                 wr32(E1000_PBA, pba);
1125         }
1126
1127         /* flow control settings */
1128         /* The high water mark must be low enough to fit one full frame
1129          * (or the size used for early receive) above it in the Rx FIFO.
1130          * Set it to the lower of:
1131          * - 90% of the Rx FIFO size, or
1132          * - the full Rx FIFO size minus one full frame */
1133         hwm = min(((pba << 10) * 9 / 10),
1134                         ((pba << 10) - 2 * adapter->max_frame_size));
1135
1136         if (mac->type < e1000_82576) {
1137                 fc->high_water = hwm & 0xFFF8;  /* 8-byte granularity */
1138                 fc->low_water = fc->high_water - 8;
1139         } else {
1140                 fc->high_water = hwm & 0xFFF0;  /* 16-byte granularity */
1141                 fc->low_water = fc->high_water - 16;
1142         }
1143         fc->pause_time = 0xFFFF;
1144         fc->send_xon = 1;
1145         fc->current_mode = fc->requested_mode;
1146
1147         /* disable receive for all VFs and wait one second */
1148         if (adapter->vfs_allocated_count) {
1149                 int i;
1150                 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1151                         adapter->vf_data[i].clear_to_send = false;
1152
1153                 /* ping all the active vfs to let them know we are going down */
1154                         igb_ping_all_vfs(adapter);
1155
1156                 /* disable transmits and receives */
1157                 wr32(E1000_VFRE, 0);
1158                 wr32(E1000_VFTE, 0);
1159         }
1160
1161         /* Allow time for pending master requests to run */
1162         adapter->hw.mac.ops.reset_hw(&adapter->hw);
1163         wr32(E1000_WUC, 0);
1164
1165         if (adapter->hw.mac.ops.init_hw(&adapter->hw))
1166                 dev_err(&adapter->pdev->dev, "Hardware Error\n");
1167
1168         igb_update_mng_vlan(adapter);
1169
1170         /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1171         wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1172
1173         igb_reset_adaptive(&adapter->hw);
1174         igb_get_phy_info(&adapter->hw);
1175 }
1176
1177 static const struct net_device_ops igb_netdev_ops = {
1178         .ndo_open               = igb_open,
1179         .ndo_stop               = igb_close,
1180         .ndo_start_xmit         = igb_xmit_frame_adv,
1181         .ndo_get_stats          = igb_get_stats,
1182         .ndo_set_rx_mode        = igb_set_rx_mode,
1183         .ndo_set_multicast_list = igb_set_rx_mode,
1184         .ndo_set_mac_address    = igb_set_mac,
1185         .ndo_change_mtu         = igb_change_mtu,
1186         .ndo_do_ioctl           = igb_ioctl,
1187         .ndo_tx_timeout         = igb_tx_timeout,
1188         .ndo_validate_addr      = eth_validate_addr,
1189         .ndo_vlan_rx_register   = igb_vlan_rx_register,
1190         .ndo_vlan_rx_add_vid    = igb_vlan_rx_add_vid,
1191         .ndo_vlan_rx_kill_vid   = igb_vlan_rx_kill_vid,
1192 #ifdef CONFIG_NET_POLL_CONTROLLER
1193         .ndo_poll_controller    = igb_netpoll,
1194 #endif
1195 };
1196
1197 /**
1198  * igb_probe - Device Initialization Routine
1199  * @pdev: PCI device information struct
1200  * @ent: entry in igb_pci_tbl
1201  *
1202  * Returns 0 on success, negative on failure
1203  *
1204  * igb_probe initializes an adapter identified by a pci_dev structure.
1205  * The OS initialization, configuring of the adapter private structure,
1206  * and a hardware reset occur.
1207  **/
1208 static int __devinit igb_probe(struct pci_dev *pdev,
1209                                const struct pci_device_id *ent)
1210 {
1211         struct net_device *netdev;
1212         struct igb_adapter *adapter;
1213         struct e1000_hw *hw;
1214         const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1215         unsigned long mmio_start, mmio_len;
1216         int err, pci_using_dac;
1217         u16 eeprom_data = 0;
1218         u16 eeprom_apme_mask = IGB_EEPROM_APME;
1219         u32 part_num;
1220
1221         err = pci_enable_device_mem(pdev);
1222         if (err)
1223                 return err;
1224
1225         pci_using_dac = 0;
1226         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1227         if (!err) {
1228                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1229                 if (!err)
1230                         pci_using_dac = 1;
1231         } else {
1232                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1233                 if (err) {
1234                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1235                         if (err) {
1236                                 dev_err(&pdev->dev, "No usable DMA "
1237                                         "configuration, aborting\n");
1238                                 goto err_dma;
1239                         }
1240                 }
1241         }
1242
1243         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1244                                            IORESOURCE_MEM),
1245                                            igb_driver_name);
1246         if (err)
1247                 goto err_pci_reg;
1248
1249         pci_enable_pcie_error_reporting(pdev);
1250
1251         pci_set_master(pdev);
1252         pci_save_state(pdev);
1253
1254         err = -ENOMEM;
1255         netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1256                                    IGB_ABS_MAX_TX_QUEUES);
1257         if (!netdev)
1258                 goto err_alloc_etherdev;
1259
1260         SET_NETDEV_DEV(netdev, &pdev->dev);
1261
1262         pci_set_drvdata(pdev, netdev);
1263         adapter = netdev_priv(netdev);
1264         adapter->netdev = netdev;
1265         adapter->pdev = pdev;
1266         hw = &adapter->hw;
1267         hw->back = adapter;
1268         adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1269
1270         mmio_start = pci_resource_start(pdev, 0);
1271         mmio_len = pci_resource_len(pdev, 0);
1272
1273         err = -EIO;
1274         hw->hw_addr = ioremap(mmio_start, mmio_len);
1275         if (!hw->hw_addr)
1276                 goto err_ioremap;
1277
1278         netdev->netdev_ops = &igb_netdev_ops;
1279         igb_set_ethtool_ops(netdev);
1280         netdev->watchdog_timeo = 5 * HZ;
1281
1282         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1283
1284         netdev->mem_start = mmio_start;
1285         netdev->mem_end = mmio_start + mmio_len;
1286
1287         /* PCI config space info */
1288         hw->vendor_id = pdev->vendor;
1289         hw->device_id = pdev->device;
1290         hw->revision_id = pdev->revision;
1291         hw->subsystem_vendor_id = pdev->subsystem_vendor;
1292         hw->subsystem_device_id = pdev->subsystem_device;
1293
1294         /* setup the private structure */
1295         hw->back = adapter;
1296         /* Copy the default MAC, PHY and NVM function pointers */
1297         memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1298         memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1299         memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1300         /* Initialize skew-specific constants */
1301         err = ei->get_invariants(hw);
1302         if (err)
1303                 goto err_sw_init;
1304
1305 #ifdef CONFIG_PCI_IOV
1306         /* since iov functionality isn't critical to base device function we
1307          * can accept failure.  If it fails we don't allow iov to be enabled */
1308         if (hw->mac.type == e1000_82576) {
1309                 /* 82576 supports a maximum of 7 VFs in addition to the PF */
1310                 unsigned int num_vfs = (max_vfs > 7) ? 7 : max_vfs;
1311                 int i;
1312                 unsigned char mac_addr[ETH_ALEN];
1313
1314                 if (num_vfs) {
1315                         adapter->vf_data = kcalloc(num_vfs,
1316                                                 sizeof(struct vf_data_storage),
1317                                                 GFP_KERNEL);
1318                         if (!adapter->vf_data) {
1319                                 dev_err(&pdev->dev,
1320                                         "Could not allocate VF private data - "
1321                                         "IOV enable failed\n");
1322                         } else {
1323                                 err = pci_enable_sriov(pdev, num_vfs);
1324                                 if (!err) {
1325                                         adapter->vfs_allocated_count = num_vfs;
1326                                         dev_info(&pdev->dev,
1327                                                  "%d vfs allocated\n",
1328                                                  num_vfs);
1329                                         for (i = 0;
1330                                              i < adapter->vfs_allocated_count;
1331                                              i++) {
1332                                                 random_ether_addr(mac_addr);
1333                                                 igb_set_vf_mac(adapter, i,
1334                                                                mac_addr);
1335                                         }
1336                                 } else {
1337                                         kfree(adapter->vf_data);
1338                                         adapter->vf_data = NULL;
1339                                 }
1340                         }
1341                 }
1342         }
1343
1344 #endif
1345         /* setup the private structure */
1346         err = igb_sw_init(adapter);
1347         if (err)
1348                 goto err_sw_init;
1349
1350         igb_get_bus_info_pcie(hw);
1351
1352         /* set flags */
1353         switch (hw->mac.type) {
1354         case e1000_82575:
1355                 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1356                 break;
1357         case e1000_82576:
1358         default:
1359                 break;
1360         }
1361
1362         hw->phy.autoneg_wait_to_complete = false;
1363         hw->mac.adaptive_ifs = true;
1364
1365         /* Copper options */
1366         if (hw->phy.media_type == e1000_media_type_copper) {
1367                 hw->phy.mdix = AUTO_ALL_MODES;
1368                 hw->phy.disable_polarity_correction = false;
1369                 hw->phy.ms_type = e1000_ms_hw_default;
1370         }
1371
1372         if (igb_check_reset_block(hw))
1373                 dev_info(&pdev->dev,
1374                         "PHY reset is blocked due to SOL/IDER session.\n");
1375
1376         netdev->features = NETIF_F_SG |
1377                            NETIF_F_IP_CSUM |
1378                            NETIF_F_HW_VLAN_TX |
1379                            NETIF_F_HW_VLAN_RX |
1380                            NETIF_F_HW_VLAN_FILTER;
1381
1382         netdev->features |= NETIF_F_IPV6_CSUM;
1383         netdev->features |= NETIF_F_TSO;
1384         netdev->features |= NETIF_F_TSO6;
1385
1386         netdev->features |= NETIF_F_GRO;
1387
1388         netdev->vlan_features |= NETIF_F_TSO;
1389         netdev->vlan_features |= NETIF_F_TSO6;
1390         netdev->vlan_features |= NETIF_F_IP_CSUM;
1391         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
1392         netdev->vlan_features |= NETIF_F_SG;
1393
1394         if (pci_using_dac)
1395                 netdev->features |= NETIF_F_HIGHDMA;
1396
1397         if (adapter->hw.mac.type == e1000_82576)
1398                 netdev->features |= NETIF_F_SCTP_CSUM;
1399
1400         adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1401
1402         /* before reading the NVM, reset the controller to put the device in a
1403          * known good starting state */
1404         hw->mac.ops.reset_hw(hw);
1405
1406         /* make sure the NVM is good */
1407         if (igb_validate_nvm_checksum(hw) < 0) {
1408                 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1409                 err = -EIO;
1410                 goto err_eeprom;
1411         }
1412
1413         /* copy the MAC address out of the NVM */
1414         if (hw->mac.ops.read_mac_addr(hw))
1415                 dev_err(&pdev->dev, "NVM Read Error\n");
1416
1417         memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1418         memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1419
1420         if (!is_valid_ether_addr(netdev->perm_addr)) {
1421                 dev_err(&pdev->dev, "Invalid MAC Address\n");
1422                 err = -EIO;
1423                 goto err_eeprom;
1424         }
1425
1426         setup_timer(&adapter->watchdog_timer, &igb_watchdog,
1427                     (unsigned long) adapter);
1428         setup_timer(&adapter->phy_info_timer, &igb_update_phy_info,
1429                     (unsigned long) adapter);
1430
1431         INIT_WORK(&adapter->reset_task, igb_reset_task);
1432         INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1433
1434         /* Initialize link properties that are user-changeable */
1435         adapter->fc_autoneg = true;
1436         hw->mac.autoneg = true;
1437         hw->phy.autoneg_advertised = 0x2f;
1438
1439         hw->fc.requested_mode = e1000_fc_default;
1440         hw->fc.current_mode = e1000_fc_default;
1441
1442         adapter->itr_setting = IGB_DEFAULT_ITR;
1443         adapter->itr = IGB_START_ITR;
1444
1445         igb_validate_mdi_setting(hw);
1446
1447         /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1448          * enable the ACPI Magic Packet filter
1449          */
1450
1451         if (hw->bus.func == 0)
1452                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
1453         else if (hw->bus.func == 1)
1454                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
1455
1456         if (eeprom_data & eeprom_apme_mask)
1457                 adapter->eeprom_wol |= E1000_WUFC_MAG;
1458
1459         /* now that we have the eeprom settings, apply the special cases where
1460          * the eeprom may be wrong or the board simply won't support wake on
1461          * lan on a particular port */
1462         switch (pdev->device) {
1463         case E1000_DEV_ID_82575GB_QUAD_COPPER:
1464                 adapter->eeprom_wol = 0;
1465                 break;
1466         case E1000_DEV_ID_82575EB_FIBER_SERDES:
1467         case E1000_DEV_ID_82576_FIBER:
1468         case E1000_DEV_ID_82576_SERDES:
1469                 /* Wake events only supported on port A for dual fiber
1470                  * regardless of eeprom setting */
1471                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1472                         adapter->eeprom_wol = 0;
1473                 break;
1474         case E1000_DEV_ID_82576_QUAD_COPPER:
1475                 /* if quad port adapter, disable WoL on all but port A */
1476                 if (global_quad_port_a != 0)
1477                         adapter->eeprom_wol = 0;
1478                 else
1479                         adapter->flags |= IGB_FLAG_QUAD_PORT_A;
1480                 /* Reset for multiple quad port adapters */
1481                 if (++global_quad_port_a == 4)
1482                         global_quad_port_a = 0;
1483                 break;
1484         }
1485
1486         /* initialize the wol settings based on the eeprom settings */
1487         adapter->wol = adapter->eeprom_wol;
1488         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1489
1490         /* reset the hardware with the new settings */
1491         igb_reset(adapter);
1492
1493         /* let the f/w know that the h/w is now under the control of the
1494          * driver. */
1495         igb_get_hw_control(adapter);
1496
1497         strcpy(netdev->name, "eth%d");
1498         err = register_netdev(netdev);
1499         if (err)
1500                 goto err_register;
1501
1502         /* carrier off reporting is important to ethtool even BEFORE open */
1503         netif_carrier_off(netdev);
1504
1505 #ifdef CONFIG_IGB_DCA
1506         if (dca_add_requester(&pdev->dev) == 0) {
1507                 adapter->flags |= IGB_FLAG_DCA_ENABLED;
1508                 dev_info(&pdev->dev, "DCA enabled\n");
1509                 igb_setup_dca(adapter);
1510         }
1511 #endif
1512
1513         /*
1514          * Initialize hardware timer: we keep it running just in case
1515          * that some program needs it later on.
1516          */
1517         memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1518         adapter->cycles.read = igb_read_clock;
1519         adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1520         adapter->cycles.mult = 1;
1521         adapter->cycles.shift = IGB_TSYNC_SHIFT;
1522         wr32(E1000_TIMINCA,
1523              (1<<24) |
1524              IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * IGB_TSYNC_SCALE);
1525 #if 0
1526         /*
1527          * Avoid rollover while we initialize by resetting the time counter.
1528          */
1529         wr32(E1000_SYSTIML, 0x00000000);
1530         wr32(E1000_SYSTIMH, 0x00000000);
1531 #else
1532         /*
1533          * Set registers so that rollover occurs soon to test this.
1534          */
1535         wr32(E1000_SYSTIML, 0x00000000);
1536         wr32(E1000_SYSTIMH, 0xFF800000);
1537 #endif
1538         wrfl();
1539         timecounter_init(&adapter->clock,
1540                          &adapter->cycles,
1541                          ktime_to_ns(ktime_get_real()));
1542
1543         /*
1544          * Synchronize our NIC clock against system wall clock. NIC
1545          * time stamp reading requires ~3us per sample, each sample
1546          * was pretty stable even under load => only require 10
1547          * samples for each offset comparison.
1548          */
1549         memset(&adapter->compare, 0, sizeof(adapter->compare));
1550         adapter->compare.source = &adapter->clock;
1551         adapter->compare.target = ktime_get_real;
1552         adapter->compare.num_samples = 10;
1553         timecompare_update(&adapter->compare, 0);
1554
1555 #ifdef DEBUG
1556         {
1557                 char buffer[160];
1558                 printk(KERN_DEBUG
1559                         "igb: %s: hw %p initialized timer\n",
1560                         igb_get_time_str(adapter, buffer),
1561                         &adapter->hw);
1562         }
1563 #endif
1564
1565         dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1566         /* print bus type/speed/width info */
1567         dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
1568                  netdev->name,
1569                  ((hw->bus.speed == e1000_bus_speed_2500)
1570                   ? "2.5Gb/s" : "unknown"),
1571                  ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
1572                   (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
1573                   (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
1574                    "unknown"),
1575                  netdev->dev_addr);
1576
1577         igb_read_part_num(hw, &part_num);
1578         dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1579                 (part_num >> 8), (part_num & 0xff));
1580
1581         dev_info(&pdev->dev,
1582                 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1583                 adapter->msix_entries ? "MSI-X" :
1584                 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
1585                 adapter->num_rx_queues, adapter->num_tx_queues);
1586
1587         return 0;
1588
1589 err_register:
1590         igb_release_hw_control(adapter);
1591 err_eeprom:
1592         if (!igb_check_reset_block(hw))
1593                 igb_reset_phy(hw);
1594
1595         if (hw->flash_address)
1596                 iounmap(hw->flash_address);
1597
1598         igb_free_queues(adapter);
1599 err_sw_init:
1600         iounmap(hw->hw_addr);
1601 err_ioremap:
1602         free_netdev(netdev);
1603 err_alloc_etherdev:
1604         pci_release_selected_regions(pdev, pci_select_bars(pdev,
1605                                      IORESOURCE_MEM));
1606 err_pci_reg:
1607 err_dma:
1608         pci_disable_device(pdev);
1609         return err;
1610 }
1611
1612 /**
1613  * igb_remove - Device Removal Routine
1614  * @pdev: PCI device information struct
1615  *
1616  * igb_remove is called by the PCI subsystem to alert the driver
1617  * that it should release a PCI device.  The could be caused by a
1618  * Hot-Plug event, or because the driver is going to be removed from
1619  * memory.
1620  **/
1621 static void __devexit igb_remove(struct pci_dev *pdev)
1622 {
1623         struct net_device *netdev = pci_get_drvdata(pdev);
1624         struct igb_adapter *adapter = netdev_priv(netdev);
1625         struct e1000_hw *hw = &adapter->hw;
1626
1627         /* flush_scheduled work may reschedule our watchdog task, so
1628          * explicitly disable watchdog tasks from being rescheduled  */
1629         set_bit(__IGB_DOWN, &adapter->state);
1630         del_timer_sync(&adapter->watchdog_timer);
1631         del_timer_sync(&adapter->phy_info_timer);
1632
1633         flush_scheduled_work();
1634
1635 #ifdef CONFIG_IGB_DCA
1636         if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
1637                 dev_info(&pdev->dev, "DCA disabled\n");
1638                 dca_remove_requester(&pdev->dev);
1639                 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
1640                 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
1641         }
1642 #endif
1643
1644         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
1645          * would have already happened in close and is redundant. */
1646         igb_release_hw_control(adapter);
1647
1648         unregister_netdev(netdev);
1649
1650         if (!igb_check_reset_block(&adapter->hw))
1651                 igb_reset_phy(&adapter->hw);
1652
1653         igb_reset_interrupt_capability(adapter);
1654
1655         igb_free_queues(adapter);
1656
1657 #ifdef CONFIG_PCI_IOV
1658         /* reclaim resources allocated to VFs */
1659         if (adapter->vf_data) {
1660                 /* disable iov and allow time for transactions to clear */
1661                 pci_disable_sriov(pdev);
1662                 msleep(500);
1663
1664                 kfree(adapter->vf_data);
1665                 adapter->vf_data = NULL;
1666                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1667                 msleep(100);
1668                 dev_info(&pdev->dev, "IOV Disabled\n");
1669         }
1670 #endif
1671         iounmap(hw->hw_addr);
1672         if (hw->flash_address)
1673                 iounmap(hw->flash_address);
1674         pci_release_selected_regions(pdev, pci_select_bars(pdev,
1675                                      IORESOURCE_MEM));
1676
1677         free_netdev(netdev);
1678
1679         pci_disable_pcie_error_reporting(pdev);
1680
1681         pci_disable_device(pdev);
1682 }
1683
1684 /**
1685  * igb_sw_init - Initialize general software structures (struct igb_adapter)
1686  * @adapter: board private structure to initialize
1687  *
1688  * igb_sw_init initializes the Adapter private data structure.
1689  * Fields are initialized based on PCI device information and
1690  * OS network device settings (MTU size).
1691  **/
1692 static int __devinit igb_sw_init(struct igb_adapter *adapter)
1693 {
1694         struct e1000_hw *hw = &adapter->hw;
1695         struct net_device *netdev = adapter->netdev;
1696         struct pci_dev *pdev = adapter->pdev;
1697
1698         pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1699
1700         adapter->tx_ring_count = IGB_DEFAULT_TXD;
1701         adapter->rx_ring_count = IGB_DEFAULT_RXD;
1702         adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1703         adapter->rx_ps_hdr_size = 0; /* disable packet split */
1704         adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1705         adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1706
1707         /* This call may decrease the number of queues depending on
1708          * interrupt mode. */
1709         igb_set_interrupt_capability(adapter);
1710
1711         if (igb_alloc_queues(adapter)) {
1712                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1713                 return -ENOMEM;
1714         }
1715
1716         /* Explicitly disable IRQ since the NIC can be in any state. */
1717         igb_irq_disable(adapter);
1718
1719         set_bit(__IGB_DOWN, &adapter->state);
1720         return 0;
1721 }
1722
1723 /**
1724  * igb_open - Called when a network interface is made active
1725  * @netdev: network interface device structure
1726  *
1727  * Returns 0 on success, negative value on failure
1728  *
1729  * The open entry point is called when a network interface is made
1730  * active by the system (IFF_UP).  At this point all resources needed
1731  * for transmit and receive operations are allocated, the interrupt
1732  * handler is registered with the OS, the watchdog timer is started,
1733  * and the stack is notified that the interface is ready.
1734  **/
1735 static int igb_open(struct net_device *netdev)
1736 {
1737         struct igb_adapter *adapter = netdev_priv(netdev);
1738         struct e1000_hw *hw = &adapter->hw;
1739         int err;
1740         int i;
1741
1742         /* disallow open during test */
1743         if (test_bit(__IGB_TESTING, &adapter->state))
1744                 return -EBUSY;
1745
1746         netif_carrier_off(netdev);
1747
1748         /* allocate transmit descriptors */
1749         err = igb_setup_all_tx_resources(adapter);
1750         if (err)
1751                 goto err_setup_tx;
1752
1753         /* allocate receive descriptors */
1754         err = igb_setup_all_rx_resources(adapter);
1755         if (err)
1756                 goto err_setup_rx;
1757
1758         /* e1000_power_up_phy(adapter); */
1759
1760         adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1761         if ((adapter->hw.mng_cookie.status &
1762              E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1763                 igb_update_mng_vlan(adapter);
1764
1765         /* before we allocate an interrupt, we must be ready to handle it.
1766          * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1767          * as soon as we call pci_request_irq, so we have to setup our
1768          * clean_rx handler before we do so.  */
1769         igb_configure(adapter);
1770
1771         igb_vmm_control(adapter);
1772         igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
1773         igb_set_vmolr(hw, adapter->vfs_allocated_count);
1774
1775         err = igb_request_irq(adapter);
1776         if (err)
1777                 goto err_req_irq;
1778
1779         /* From here on the code is the same as igb_up() */
1780         clear_bit(__IGB_DOWN, &adapter->state);
1781
1782         for (i = 0; i < adapter->num_rx_queues; i++)
1783                 napi_enable(&adapter->rx_ring[i].napi);
1784
1785         /* Clear any pending interrupts. */
1786         rd32(E1000_ICR);
1787
1788         igb_irq_enable(adapter);
1789
1790         netif_tx_start_all_queues(netdev);
1791
1792         /* Fire a link status change interrupt to start the watchdog. */
1793         wr32(E1000_ICS, E1000_ICS_LSC);
1794
1795         return 0;
1796
1797 err_req_irq:
1798         igb_release_hw_control(adapter);
1799         /* e1000_power_down_phy(adapter); */
1800         igb_free_all_rx_resources(adapter);
1801 err_setup_rx:
1802         igb_free_all_tx_resources(adapter);
1803 err_setup_tx:
1804         igb_reset(adapter);
1805
1806         return err;
1807 }
1808
1809 /**
1810  * igb_close - Disables a network interface
1811  * @netdev: network interface device structure
1812  *
1813  * Returns 0, this is not allowed to fail
1814  *
1815  * The close entry point is called when an interface is de-activated
1816  * by the OS.  The hardware is still under the driver's control, but
1817  * needs to be disabled.  A global MAC reset is issued to stop the
1818  * hardware, and all transmit and receive resources are freed.
1819  **/
1820 static int igb_close(struct net_device *netdev)
1821 {
1822         struct igb_adapter *adapter = netdev_priv(netdev);
1823
1824         WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1825         igb_down(adapter);
1826
1827         igb_free_irq(adapter);
1828
1829         igb_free_all_tx_resources(adapter);
1830         igb_free_all_rx_resources(adapter);
1831
1832         /* kill manageability vlan ID if supported, but not if a vlan with
1833          * the same ID is registered on the host OS (let 8021q kill it) */
1834         if ((adapter->hw.mng_cookie.status &
1835                           E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1836              !(adapter->vlgrp &&
1837                vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1838                 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1839
1840         return 0;
1841 }
1842
1843 /**
1844  * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1845  * @adapter: board private structure
1846  * @tx_ring: tx descriptor ring (for a specific queue) to setup
1847  *
1848  * Return 0 on success, negative on failure
1849  **/
1850 int igb_setup_tx_resources(struct igb_adapter *adapter,
1851                            struct igb_ring *tx_ring)
1852 {
1853         struct pci_dev *pdev = adapter->pdev;
1854         int size;
1855
1856         size = sizeof(struct igb_buffer) * tx_ring->count;
1857         tx_ring->buffer_info = vmalloc(size);
1858         if (!tx_ring->buffer_info)
1859                 goto err;
1860         memset(tx_ring->buffer_info, 0, size);
1861
1862         /* round up to nearest 4K */
1863         tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
1864         tx_ring->size = ALIGN(tx_ring->size, 4096);
1865
1866         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1867                                              &tx_ring->dma);
1868
1869         if (!tx_ring->desc)
1870                 goto err;
1871
1872         tx_ring->adapter = adapter;
1873         tx_ring->next_to_use = 0;
1874         tx_ring->next_to_clean = 0;
1875         return 0;
1876
1877 err:
1878         vfree(tx_ring->buffer_info);
1879         dev_err(&adapter->pdev->dev,
1880                 "Unable to allocate memory for the transmit descriptor ring\n");
1881         return -ENOMEM;
1882 }
1883
1884 /**
1885  * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1886  *                                (Descriptors) for all queues
1887  * @adapter: board private structure
1888  *
1889  * Return 0 on success, negative on failure
1890  **/
1891 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1892 {
1893         int i, err = 0;
1894         int r_idx;
1895
1896         for (i = 0; i < adapter->num_tx_queues; i++) {
1897                 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1898                 if (err) {
1899                         dev_err(&adapter->pdev->dev,
1900                                 "Allocation for Tx Queue %u failed\n", i);
1901                         for (i--; i >= 0; i--)
1902                                 igb_free_tx_resources(&adapter->tx_ring[i]);
1903                         break;
1904                 }
1905         }
1906
1907         for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1908                 r_idx = i % adapter->num_tx_queues;
1909                 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
1910         }
1911         return err;
1912 }
1913
1914 /**
1915  * igb_configure_tx - Configure transmit Unit after Reset
1916  * @adapter: board private structure
1917  *
1918  * Configure the Tx unit of the MAC after a reset.
1919  **/
1920 static void igb_configure_tx(struct igb_adapter *adapter)
1921 {
1922         u64 tdba;
1923         struct e1000_hw *hw = &adapter->hw;
1924         u32 tctl;
1925         u32 txdctl, txctrl;
1926         int i, j;
1927
1928         for (i = 0; i < adapter->num_tx_queues; i++) {
1929                 struct igb_ring *ring = &adapter->tx_ring[i];
1930                 j = ring->reg_idx;
1931                 wr32(E1000_TDLEN(j),
1932                      ring->count * sizeof(union e1000_adv_tx_desc));
1933                 tdba = ring->dma;
1934                 wr32(E1000_TDBAL(j),
1935                      tdba & 0x00000000ffffffffULL);
1936                 wr32(E1000_TDBAH(j), tdba >> 32);
1937
1938                 ring->head = E1000_TDH(j);
1939                 ring->tail = E1000_TDT(j);
1940                 writel(0, hw->hw_addr + ring->tail);
1941                 writel(0, hw->hw_addr + ring->head);
1942                 txdctl = rd32(E1000_TXDCTL(j));
1943                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1944                 wr32(E1000_TXDCTL(j), txdctl);
1945
1946                 /* Turn off Relaxed Ordering on head write-backs.  The
1947                  * writebacks MUST be delivered in order or it will
1948                  * completely screw up our bookeeping.
1949                  */
1950                 txctrl = rd32(E1000_DCA_TXCTRL(j));
1951                 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1952                 wr32(E1000_DCA_TXCTRL(j), txctrl);
1953         }
1954
1955         /* disable queue 0 to prevent tail bump w/o re-configuration */
1956         if (adapter->vfs_allocated_count)
1957                 wr32(E1000_TXDCTL(0), 0);
1958
1959         /* Program the Transmit Control Register */
1960         tctl = rd32(E1000_TCTL);
1961         tctl &= ~E1000_TCTL_CT;
1962         tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1963                 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1964
1965         igb_config_collision_dist(hw);
1966
1967         /* Setup Transmit Descriptor Settings for eop descriptor */
1968         adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1969
1970         /* Enable transmits */
1971         tctl |= E1000_TCTL_EN;
1972
1973         wr32(E1000_TCTL, tctl);
1974 }
1975
1976 /**
1977  * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1978  * @adapter: board private structure
1979  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
1980  *
1981  * Returns 0 on success, negative on failure
1982  **/
1983 int igb_setup_rx_resources(struct igb_adapter *adapter,
1984                            struct igb_ring *rx_ring)
1985 {
1986         struct pci_dev *pdev = adapter->pdev;
1987         int size, desc_len;
1988
1989         size = sizeof(struct igb_buffer) * rx_ring->count;
1990         rx_ring->buffer_info = vmalloc(size);
1991         if (!rx_ring->buffer_info)
1992                 goto err;
1993         memset(rx_ring->buffer_info, 0, size);
1994
1995         desc_len = sizeof(union e1000_adv_rx_desc);
1996
1997         /* Round up to nearest 4K */
1998         rx_ring->size = rx_ring->count * desc_len;
1999         rx_ring->size = ALIGN(rx_ring->size, 4096);
2000
2001         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
2002                                              &rx_ring->dma);
2003
2004         if (!rx_ring->desc)
2005                 goto err;
2006
2007         rx_ring->next_to_clean = 0;
2008         rx_ring->next_to_use = 0;
2009
2010         rx_ring->adapter = adapter;
2011
2012         return 0;
2013
2014 err:
2015         vfree(rx_ring->buffer_info);
2016         dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
2017                 "the receive descriptor ring\n");
2018         return -ENOMEM;
2019 }
2020
2021 /**
2022  * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2023  *                                (Descriptors) for all queues
2024  * @adapter: board private structure
2025  *
2026  * Return 0 on success, negative on failure
2027  **/
2028 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
2029 {
2030         int i, err = 0;
2031
2032         for (i = 0; i < adapter->num_rx_queues; i++) {
2033                 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
2034                 if (err) {
2035                         dev_err(&adapter->pdev->dev,
2036                                 "Allocation for Rx Queue %u failed\n", i);
2037                         for (i--; i >= 0; i--)
2038                                 igb_free_rx_resources(&adapter->rx_ring[i]);
2039                         break;
2040                 }
2041         }
2042
2043         return err;
2044 }
2045
2046 /**
2047  * igb_setup_rctl - configure the receive control registers
2048  * @adapter: Board private structure
2049  **/
2050 static void igb_setup_rctl(struct igb_adapter *adapter)
2051 {
2052         struct e1000_hw *hw = &adapter->hw;
2053         u32 rctl;
2054         u32 srrctl = 0;
2055         int i;
2056
2057         rctl = rd32(E1000_RCTL);
2058
2059         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2060         rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
2061
2062         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
2063                 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2064
2065         /*
2066          * enable stripping of CRC. It's unlikely this will break BMC
2067          * redirection as it did with e1000. Newer features require
2068          * that the HW strips the CRC.
2069          */
2070         rctl |= E1000_RCTL_SECRC;
2071
2072         /*
2073          * disable store bad packets and clear size bits.
2074          */
2075         rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
2076
2077         /* enable LPE when to prevent packets larger than max_frame_size */
2078                 rctl |= E1000_RCTL_LPE;
2079
2080         /* Setup buffer sizes */
2081         switch (adapter->rx_buffer_len) {
2082         case IGB_RXBUFFER_256:
2083                 rctl |= E1000_RCTL_SZ_256;
2084                 break;
2085         case IGB_RXBUFFER_512:
2086                 rctl |= E1000_RCTL_SZ_512;
2087                 break;
2088         default:
2089                 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
2090                          >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2091                 break;
2092         }
2093
2094         /* 82575 and greater support packet-split where the protocol
2095          * header is placed in skb->data and the packet data is
2096          * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2097          * In the case of a non-split, skb->data is linearly filled,
2098          * followed by the page buffers.  Therefore, skb->data is
2099          * sized to hold the largest protocol header.
2100          */
2101         /* allocations using alloc_page take too long for regular MTU
2102          * so only enable packet split for jumbo frames */
2103         if (adapter->netdev->mtu > ETH_DATA_LEN) {
2104                 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
2105                 srrctl |= adapter->rx_ps_hdr_size <<
2106                          E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2107                 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2108         } else {
2109                 adapter->rx_ps_hdr_size = 0;
2110                 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2111         }
2112
2113         /* Attention!!!  For SR-IOV PF driver operations you must enable
2114          * queue drop for all VF and PF queues to prevent head of line blocking
2115          * if an un-trusted VF does not provide descriptors to hardware.
2116          */
2117         if (adapter->vfs_allocated_count) {
2118                 u32 vmolr;
2119
2120                 /* set all queue drop enable bits */
2121                 wr32(E1000_QDE, ALL_QUEUES);
2122                 srrctl |= E1000_SRRCTL_DROP_EN;
2123
2124                 /* disable queue 0 to prevent tail write w/o re-config */
2125                 wr32(E1000_RXDCTL(0), 0);
2126
2127                 vmolr = rd32(E1000_VMOLR(adapter->vfs_allocated_count));
2128                 if (rctl & E1000_RCTL_LPE)
2129                         vmolr |= E1000_VMOLR_LPE;
2130                 if (adapter->num_rx_queues > 1)
2131                         vmolr |= E1000_VMOLR_RSSE;
2132                 wr32(E1000_VMOLR(adapter->vfs_allocated_count), vmolr);
2133         }
2134
2135         for (i = 0; i < adapter->num_rx_queues; i++) {
2136                 int j = adapter->rx_ring[i].reg_idx;
2137                 wr32(E1000_SRRCTL(j), srrctl);
2138         }
2139
2140         wr32(E1000_RCTL, rctl);
2141 }
2142
2143 /**
2144  * igb_rlpml_set - set maximum receive packet size
2145  * @adapter: board private structure
2146  *
2147  * Configure maximum receivable packet size.
2148  **/
2149 static void igb_rlpml_set(struct igb_adapter *adapter)
2150 {
2151         u32 max_frame_size = adapter->max_frame_size;
2152         struct e1000_hw *hw = &adapter->hw;
2153         u16 pf_id = adapter->vfs_allocated_count;
2154
2155         if (adapter->vlgrp)
2156                 max_frame_size += VLAN_TAG_SIZE;
2157
2158         /* if vfs are enabled we set RLPML to the largest possible request
2159          * size and set the VMOLR RLPML to the size we need */
2160         if (pf_id) {
2161                 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
2162                 max_frame_size = MAX_STD_JUMBO_FRAME_SIZE + VLAN_TAG_SIZE;
2163         }
2164
2165         wr32(E1000_RLPML, max_frame_size);
2166 }
2167
2168 /**
2169  * igb_configure_vt_default_pool - Configure VT default pool
2170  * @adapter: board private structure
2171  *
2172  * Configure the default pool
2173  **/
2174 static void igb_configure_vt_default_pool(struct igb_adapter *adapter)
2175 {
2176         struct e1000_hw *hw = &adapter->hw;
2177         u16 pf_id = adapter->vfs_allocated_count;
2178         u32 vtctl;
2179
2180         /* not in sr-iov mode - do nothing */
2181         if (!pf_id)
2182                 return;
2183
2184         vtctl = rd32(E1000_VT_CTL);
2185         vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2186                    E1000_VT_CTL_DISABLE_DEF_POOL);
2187         vtctl |= pf_id << E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2188         wr32(E1000_VT_CTL, vtctl);
2189 }
2190
2191 /**
2192  * igb_configure_rx - Configure receive Unit after Reset
2193  * @adapter: board private structure
2194  *
2195  * Configure the Rx unit of the MAC after a reset.
2196  **/
2197 static void igb_configure_rx(struct igb_adapter *adapter)
2198 {
2199         u64 rdba;
2200         struct e1000_hw *hw = &adapter->hw;
2201         u32 rctl, rxcsum;
2202         u32 rxdctl;
2203         int i;
2204
2205         /* disable receives while setting up the descriptors */
2206         rctl = rd32(E1000_RCTL);
2207         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2208         wrfl();
2209         mdelay(10);
2210
2211         if (adapter->itr_setting > 3)
2212                 wr32(E1000_ITR, adapter->itr);
2213
2214         /* Setup the HW Rx Head and Tail Descriptor Pointers and
2215          * the Base and Length of the Rx Descriptor Ring */
2216         for (i = 0; i < adapter->num_rx_queues; i++) {
2217                 struct igb_ring *ring = &adapter->rx_ring[i];
2218                 int j = ring->reg_idx;
2219                 rdba = ring->dma;
2220                 wr32(E1000_RDBAL(j),
2221                      rdba & 0x00000000ffffffffULL);
2222                 wr32(E1000_RDBAH(j), rdba >> 32);
2223                 wr32(E1000_RDLEN(j),
2224                      ring->count * sizeof(union e1000_adv_rx_desc));
2225
2226                 ring->head = E1000_RDH(j);
2227                 ring->tail = E1000_RDT(j);
2228                 writel(0, hw->hw_addr + ring->tail);
2229                 writel(0, hw->hw_addr + ring->head);
2230
2231                 rxdctl = rd32(E1000_RXDCTL(j));
2232                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2233                 rxdctl &= 0xFFF00000;
2234                 rxdctl |= IGB_RX_PTHRESH;
2235                 rxdctl |= IGB_RX_HTHRESH << 8;
2236                 rxdctl |= IGB_RX_WTHRESH << 16;
2237                 wr32(E1000_RXDCTL(j), rxdctl);
2238         }
2239
2240         if (adapter->num_rx_queues > 1) {
2241                 u32 random[10];
2242                 u32 mrqc;
2243                 u32 j, shift;
2244                 union e1000_reta {
2245                         u32 dword;
2246                         u8  bytes[4];
2247                 } reta;
2248
2249                 get_random_bytes(&random[0], 40);
2250
2251                 if (hw->mac.type >= e1000_82576)
2252                         shift = 0;
2253                 else
2254                         shift = 6;
2255                 for (j = 0; j < (32 * 4); j++) {
2256                         reta.bytes[j & 3] =
2257                                 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
2258                         if ((j & 3) == 3)
2259                                 writel(reta.dword,
2260                                        hw->hw_addr + E1000_RETA(0) + (j & ~3));
2261                 }
2262                 if (adapter->vfs_allocated_count)
2263                         mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2264                 else
2265                         mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2266
2267                 /* Fill out hash function seeds */
2268                 for (j = 0; j < 10; j++)
2269                         array_wr32(E1000_RSSRK(0), j, random[j]);
2270
2271                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2272                          E1000_MRQC_RSS_FIELD_IPV4_TCP);
2273                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2274                          E1000_MRQC_RSS_FIELD_IPV6_TCP);
2275                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
2276                          E1000_MRQC_RSS_FIELD_IPV6_UDP);
2277                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2278                          E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2279
2280                 wr32(E1000_MRQC, mrqc);
2281         } else if (adapter->vfs_allocated_count) {
2282                 /* Enable multi-queue for sr-iov */
2283                 wr32(E1000_MRQC, E1000_MRQC_ENABLE_VMDQ);
2284         }
2285
2286         /* Enable Receive Checksum Offload for TCP and UDP */
2287         rxcsum = rd32(E1000_RXCSUM);
2288         /* Disable raw packet checksumming */
2289         rxcsum |= E1000_RXCSUM_PCSD;
2290
2291         if (adapter->hw.mac.type == e1000_82576)
2292                 /* Enable Receive Checksum Offload for SCTP */
2293                 rxcsum |= E1000_RXCSUM_CRCOFL;
2294
2295         /* Don't need to set TUOFL or IPOFL, they default to 1 */
2296         wr32(E1000_RXCSUM, rxcsum);
2297
2298         /* Set the default pool for the PF's first queue */
2299         igb_configure_vt_default_pool(adapter);
2300
2301         igb_rlpml_set(adapter);
2302
2303         /* Enable Receives */
2304         wr32(E1000_RCTL, rctl);
2305 }
2306
2307 /**
2308  * igb_free_tx_resources - Free Tx Resources per Queue
2309  * @tx_ring: Tx descriptor ring for a specific queue
2310  *
2311  * Free all transmit software resources
2312  **/
2313 void igb_free_tx_resources(struct igb_ring *tx_ring)
2314 {
2315         struct pci_dev *pdev = tx_ring->adapter->pdev;
2316
2317         igb_clean_tx_ring(tx_ring);
2318
2319         vfree(tx_ring->buffer_info);
2320         tx_ring->buffer_info = NULL;
2321
2322         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2323
2324         tx_ring->desc = NULL;
2325 }
2326
2327 /**
2328  * igb_free_all_tx_resources - Free Tx Resources for All Queues
2329  * @adapter: board private structure
2330  *
2331  * Free all transmit software resources
2332  **/
2333 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2334 {
2335         int i;
2336
2337         for (i = 0; i < adapter->num_tx_queues; i++)
2338                 igb_free_tx_resources(&adapter->tx_ring[i]);
2339 }
2340
2341 static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2342                                            struct igb_buffer *buffer_info)
2343 {
2344         buffer_info->dma = 0;
2345         if (buffer_info->skb) {
2346                 skb_dma_unmap(&adapter->pdev->dev, buffer_info->skb,
2347                               DMA_TO_DEVICE);
2348                 dev_kfree_skb_any(buffer_info->skb);
2349                 buffer_info->skb = NULL;
2350         }
2351         buffer_info->time_stamp = 0;
2352         /* buffer_info must be completely set up in the transmit path */
2353 }
2354
2355 /**
2356  * igb_clean_tx_ring - Free Tx Buffers
2357  * @tx_ring: ring to be cleaned
2358  **/
2359 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
2360 {
2361         struct igb_adapter *adapter = tx_ring->adapter;
2362         struct igb_buffer *buffer_info;
2363         unsigned long size;
2364         unsigned int i;
2365
2366         if (!tx_ring->buffer_info)
2367                 return;
2368         /* Free all the Tx ring sk_buffs */
2369
2370         for (i = 0; i < tx_ring->count; i++) {
2371                 buffer_info = &tx_ring->buffer_info[i];
2372                 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2373         }
2374
2375         size = sizeof(struct igb_buffer) * tx_ring->count;
2376         memset(tx_ring->buffer_info, 0, size);
2377
2378         /* Zero out the descriptor ring */
2379
2380         memset(tx_ring->desc, 0, tx_ring->size);
2381
2382         tx_ring->next_to_use = 0;
2383         tx_ring->next_to_clean = 0;
2384
2385         writel(0, adapter->hw.hw_addr + tx_ring->head);
2386         writel(0, adapter->hw.hw_addr + tx_ring->tail);
2387 }
2388
2389 /**
2390  * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2391  * @adapter: board private structure
2392  **/
2393 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2394 {
2395         int i;
2396
2397         for (i = 0; i < adapter->num_tx_queues; i++)
2398                 igb_clean_tx_ring(&adapter->tx_ring[i]);
2399 }
2400
2401 /**
2402  * igb_free_rx_resources - Free Rx Resources
2403  * @rx_ring: ring to clean the resources from
2404  *
2405  * Free all receive software resources
2406  **/
2407 void igb_free_rx_resources(struct igb_ring *rx_ring)
2408 {
2409         struct pci_dev *pdev = rx_ring->adapter->pdev;
2410
2411         igb_clean_rx_ring(rx_ring);
2412
2413         vfree(rx_ring->buffer_info);
2414         rx_ring->buffer_info = NULL;
2415
2416         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2417
2418         rx_ring->desc = NULL;
2419 }
2420
2421 /**
2422  * igb_free_all_rx_resources - Free Rx Resources for All Queues
2423  * @adapter: board private structure
2424  *
2425  * Free all receive software resources
2426  **/
2427 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2428 {
2429         int i;
2430
2431         for (i = 0; i < adapter->num_rx_queues; i++)
2432                 igb_free_rx_resources(&adapter->rx_ring[i]);
2433 }
2434
2435 /**
2436  * igb_clean_rx_ring - Free Rx Buffers per Queue
2437  * @rx_ring: ring to free buffers from
2438  **/
2439 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
2440 {
2441         struct igb_adapter *adapter = rx_ring->adapter;
2442         struct igb_buffer *buffer_info;
2443         struct pci_dev *pdev = adapter->pdev;
2444         unsigned long size;
2445         unsigned int i;
2446
2447         if (!rx_ring->buffer_info)
2448                 return;
2449         /* Free all the Rx ring sk_buffs */
2450         for (i = 0; i < rx_ring->count; i++) {
2451                 buffer_info = &rx_ring->buffer_info[i];
2452                 if (buffer_info->dma) {
2453                         if (adapter->rx_ps_hdr_size)
2454                                 pci_unmap_single(pdev, buffer_info->dma,
2455                                                  adapter->rx_ps_hdr_size,
2456                                                  PCI_DMA_FROMDEVICE);
2457                         else
2458                                 pci_unmap_single(pdev, buffer_info->dma,
2459                                                  adapter->rx_buffer_len,
2460                                                  PCI_DMA_FROMDEVICE);
2461                         buffer_info->dma = 0;
2462                 }
2463
2464                 if (buffer_info->skb) {
2465                         dev_kfree_skb(buffer_info->skb);
2466                         buffer_info->skb = NULL;
2467                 }
2468                 if (buffer_info->page) {
2469                         if (buffer_info->page_dma)
2470                                 pci_unmap_page(pdev, buffer_info->page_dma,
2471                                                PAGE_SIZE / 2,
2472                                                PCI_DMA_FROMDEVICE);
2473                         put_page(buffer_info->page);
2474                         buffer_info->page = NULL;
2475                         buffer_info->page_dma = 0;
2476                         buffer_info->page_offset = 0;
2477                 }
2478         }
2479
2480         size = sizeof(struct igb_buffer) * rx_ring->count;
2481         memset(rx_ring->buffer_info, 0, size);
2482
2483         /* Zero out the descriptor ring */
2484         memset(rx_ring->desc, 0, rx_ring->size);
2485
2486         rx_ring->next_to_clean = 0;
2487         rx_ring->next_to_use = 0;
2488
2489         writel(0, adapter->hw.hw_addr + rx_ring->head);
2490         writel(0, adapter->hw.hw_addr + rx_ring->tail);
2491 }
2492
2493 /**
2494  * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2495  * @adapter: board private structure
2496  **/
2497 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2498 {
2499         int i;
2500
2501         for (i = 0; i < adapter->num_rx_queues; i++)
2502                 igb_clean_rx_ring(&adapter->rx_ring[i]);
2503 }
2504
2505 /**
2506  * igb_set_mac - Change the Ethernet Address of the NIC
2507  * @netdev: network interface device structure
2508  * @p: pointer to an address structure
2509  *
2510  * Returns 0 on success, negative on failure
2511  **/
2512 static int igb_set_mac(struct net_device *netdev, void *p)
2513 {
2514         struct igb_adapter *adapter = netdev_priv(netdev);
2515         struct e1000_hw *hw = &adapter->hw;
2516         struct sockaddr *addr = p;
2517
2518         if (!is_valid_ether_addr(addr->sa_data))
2519                 return -EADDRNOTAVAIL;
2520
2521         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2522         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
2523
2524         igb_rar_set(hw, hw->mac.addr, 0);
2525         igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
2526
2527         return 0;
2528 }
2529
2530 /**
2531  * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
2532  * @netdev: network interface device structure
2533  *
2534  * The set_rx_mode entry point is called whenever the unicast or multicast
2535  * address lists or the network interface flags are updated.  This routine is
2536  * responsible for configuring the hardware for proper unicast, multicast,
2537  * promiscuous mode, and all-multi behavior.
2538  **/
2539 static void igb_set_rx_mode(struct net_device *netdev)
2540 {
2541         struct igb_adapter *adapter = netdev_priv(netdev);
2542         struct e1000_hw *hw = &adapter->hw;
2543         unsigned int rar_entries = hw->mac.rar_entry_count -
2544                                    (adapter->vfs_allocated_count + 1);
2545         struct dev_mc_list *mc_ptr = netdev->mc_list;
2546         u8  *mta_list = NULL;
2547         u32 rctl;
2548         int i;
2549
2550         /* Check for Promiscuous and All Multicast modes */
2551         rctl = rd32(E1000_RCTL);
2552
2553         if (netdev->flags & IFF_PROMISC) {
2554                 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2555                 rctl &= ~E1000_RCTL_VFE;
2556         } else {
2557                 if (netdev->flags & IFF_ALLMULTI)
2558                         rctl |= E1000_RCTL_MPE;
2559                 else
2560                         rctl &= ~E1000_RCTL_MPE;
2561
2562                 if (netdev->uc.count > rar_entries)
2563                         rctl |= E1000_RCTL_UPE;
2564                 else
2565                         rctl &= ~E1000_RCTL_UPE;
2566                 rctl |= E1000_RCTL_VFE;
2567         }
2568         wr32(E1000_RCTL, rctl);
2569
2570         if (netdev->uc.count && rar_entries) {
2571                 struct netdev_hw_addr *ha;
2572                 list_for_each_entry(ha, &netdev->uc.list, list) {
2573                         if (!rar_entries)
2574                                 break;
2575                         igb_rar_set(hw, ha->addr, rar_entries);
2576                         igb_set_rah_pool(hw, adapter->vfs_allocated_count,
2577                                          rar_entries);
2578                         rar_entries--;
2579                 }
2580         }
2581         /* write the addresses in reverse order to avoid write combining */
2582         for (; rar_entries > 0 ; rar_entries--) {
2583                 wr32(E1000_RAH(rar_entries), 0);
2584                 wr32(E1000_RAL(rar_entries), 0);
2585         }
2586         wrfl();
2587
2588         if (!netdev->mc_count) {
2589                 /* nothing to program, so clear mc list */
2590                 igb_update_mc_addr_list(hw, NULL, 0);
2591                 igb_restore_vf_multicasts(adapter);
2592                 return;
2593         }
2594
2595         mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2596         if (!mta_list) {
2597                 dev_err(&adapter->pdev->dev,
2598                         "failed to allocate multicast filter list\n");
2599                 return;
2600         }
2601
2602         /* The shared function expects a packed array of only addresses. */
2603         for (i = 0; i < netdev->mc_count; i++) {
2604                 if (!mc_ptr)
2605                         break;
2606                 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2607                 mc_ptr = mc_ptr->next;
2608         }
2609         igb_update_mc_addr_list(hw, mta_list, i);
2610         kfree(mta_list);
2611         igb_restore_vf_multicasts(adapter);
2612 }
2613
2614 /* Need to wait a few seconds after link up to get diagnostic information from
2615  * the phy */
2616 static void igb_update_phy_info(unsigned long data)
2617 {
2618         struct igb_adapter *adapter = (struct igb_adapter *) data;
2619         igb_get_phy_info(&adapter->hw);
2620 }
2621
2622 /**
2623  * igb_has_link - check shared code for link and determine up/down
2624  * @adapter: pointer to driver private info
2625  **/
2626 static bool igb_has_link(struct igb_adapter *adapter)
2627 {
2628         struct e1000_hw *hw = &adapter->hw;
2629         bool link_active = false;
2630         s32 ret_val = 0;
2631
2632         /* get_link_status is set on LSC (link status) interrupt or
2633          * rx sequence error interrupt.  get_link_status will stay
2634          * false until the e1000_check_for_link establishes link
2635          * for copper adapters ONLY
2636          */
2637         switch (hw->phy.media_type) {
2638         case e1000_media_type_copper:
2639                 if (hw->mac.get_link_status) {
2640                         ret_val = hw->mac.ops.check_for_link(hw);
2641                         link_active = !hw->mac.get_link_status;
2642                 } else {
2643                         link_active = true;
2644                 }
2645                 break;
2646         case e1000_media_type_internal_serdes:
2647                 ret_val = hw->mac.ops.check_for_link(hw);
2648                 link_active = hw->mac.serdes_has_link;
2649                 break;
2650         default:
2651         case e1000_media_type_unknown:
2652                 break;
2653         }
2654
2655         return link_active;
2656 }
2657
2658 /**
2659  * igb_watchdog - Timer Call-back
2660  * @data: pointer to adapter cast into an unsigned long
2661  **/
2662 static void igb_watchdog(unsigned long data)
2663 {
2664         struct igb_adapter *adapter = (struct igb_adapter *)data;
2665         /* Do the rest outside of interrupt context */
2666         schedule_work(&adapter->watchdog_task);
2667 }
2668
2669 static void igb_watchdog_task(struct work_struct *work)
2670 {
2671         struct igb_adapter *adapter = container_of(work,
2672                                         struct igb_adapter, watchdog_task);
2673         struct e1000_hw *hw = &adapter->hw;
2674         struct net_device *netdev = adapter->netdev;
2675         struct igb_ring *tx_ring = adapter->tx_ring;
2676         u32 link;
2677         u32 eics = 0;
2678         int i;
2679
2680         link = igb_has_link(adapter);
2681         if ((netif_carrier_ok(netdev)) && link)
2682                 goto link_up;
2683
2684         if (link) {
2685                 if (!netif_carrier_ok(netdev)) {
2686                         u32 ctrl;
2687                         hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2688                                                    &adapter->link_speed,
2689                                                    &adapter->link_duplex);
2690
2691                         ctrl = rd32(E1000_CTRL);
2692                         /* Links status message must follow this format */
2693                         printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
2694                                  "Flow Control: %s\n",
2695                                  netdev->name,
2696                                  adapter->link_speed,
2697                                  adapter->link_duplex == FULL_DUPLEX ?
2698                                  "Full Duplex" : "Half Duplex",
2699                                  ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2700                                  E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2701                                  E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2702                                  E1000_CTRL_TFCE) ? "TX" : "None")));
2703
2704                         /* tweak tx_queue_len according to speed/duplex and
2705                          * adjust the timeout factor */
2706                         netdev->tx_queue_len = adapter->tx_queue_len;
2707                         adapter->tx_timeout_factor = 1;
2708                         switch (adapter->link_speed) {
2709                         case SPEED_10:
2710                                 netdev->tx_queue_len = 10;
2711                                 adapter->tx_timeout_factor = 14;
2712                                 break;
2713                         case SPEED_100:
2714                                 netdev->tx_queue_len = 100;
2715                                 /* maybe add some timeout factor ? */
2716                                 break;
2717                         }
2718
2719                         netif_carrier_on(netdev);
2720
2721                         igb_ping_all_vfs(adapter);
2722
2723                         /* link state has changed, schedule phy info update */
2724                         if (!test_bit(__IGB_DOWN, &adapter->state))
2725                                 mod_timer(&adapter->phy_info_timer,
2726                                           round_jiffies(jiffies + 2 * HZ));
2727                 }
2728         } else {
2729                 if (netif_carrier_ok(netdev)) {
2730                         adapter->link_speed = 0;
2731                         adapter->link_duplex = 0;
2732                         /* Links status message must follow this format */
2733                         printk(KERN_INFO "igb: %s NIC Link is Down\n",
2734                                netdev->name);
2735                         netif_carrier_off(netdev);
2736
2737                         igb_ping_all_vfs(adapter);
2738
2739                         /* link state has changed, schedule phy info update */
2740                         if (!test_bit(__IGB_DOWN, &adapter->state))
2741                                 mod_timer(&adapter->phy_info_timer,
2742                                           round_jiffies(jiffies + 2 * HZ));
2743                 }
2744         }
2745
2746 link_up:
2747         igb_update_stats(adapter);
2748
2749         hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2750         adapter->tpt_old = adapter->stats.tpt;
2751         hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old;
2752         adapter->colc_old = adapter->stats.colc;
2753
2754         adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2755         adapter->gorc_old = adapter->stats.gorc;
2756         adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2757         adapter->gotc_old = adapter->stats.gotc;
2758
2759         igb_update_adaptive(&adapter->hw);
2760
2761         if (!netif_carrier_ok(netdev)) {
2762                 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
2763                         /* We've lost link, so the controller stops DMA,
2764                          * but we've got queued Tx work that's never going
2765                          * to get done, so reset controller to flush Tx.
2766                          * (Do the reset outside of interrupt context). */
2767                         adapter->tx_timeout_count++;
2768                         schedule_work(&adapter->reset_task);
2769                         /* return immediately since reset is imminent */
2770                         return;
2771                 }
2772         }
2773
2774         /* Cause software interrupt to ensure rx ring is cleaned */
2775         if (adapter->msix_entries) {
2776                 for (i = 0; i < adapter->num_rx_queues; i++)
2777                         eics |= adapter->rx_ring[i].eims_value;
2778                 wr32(E1000_EICS, eics);
2779         } else {
2780                 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2781         }
2782
2783         /* Force detection of hung controller every watchdog period */
2784         tx_ring->detect_tx_hung = true;
2785
2786         /* Reset the timer */
2787         if (!test_bit(__IGB_DOWN, &adapter->state))
2788                 mod_timer(&adapter->watchdog_timer,
2789                           round_jiffies(jiffies + 2 * HZ));
2790 }
2791
2792 enum latency_range {
2793         lowest_latency = 0,
2794         low_latency = 1,
2795         bulk_latency = 2,
2796         latency_invalid = 255
2797 };
2798
2799
2800 /**
2801  * igb_update_ring_itr - update the dynamic ITR value based on packet size
2802  *
2803  *      Stores a new ITR value based on strictly on packet size.  This
2804  *      algorithm is less sophisticated than that used in igb_update_itr,
2805  *      due to the difficulty of synchronizing statistics across multiple
2806  *      receive rings.  The divisors and thresholds used by this fuction
2807  *      were determined based on theoretical maximum wire speed and testing
2808  *      data, in order to minimize response time while increasing bulk
2809  *      throughput.
2810  *      This functionality is controlled by the InterruptThrottleRate module
2811  *      parameter (see igb_param.c)
2812  *      NOTE:  This function is called only when operating in a multiqueue
2813  *             receive environment.
2814  * @rx_ring: pointer to ring
2815  **/
2816 static void igb_update_ring_itr(struct igb_ring *rx_ring)
2817 {
2818         int new_val = rx_ring->itr_val;
2819         int avg_wire_size = 0;
2820         struct igb_adapter *adapter = rx_ring->adapter;
2821
2822         if (!rx_ring->total_packets)
2823                 goto clear_counts; /* no packets, so don't do anything */
2824
2825         /* For non-gigabit speeds, just fix the interrupt rate at 4000
2826          * ints/sec - ITR timer value of 120 ticks.
2827          */
2828         if (adapter->link_speed != SPEED_1000) {
2829                 new_val = 120;
2830                 goto set_itr_val;
2831         }
2832         avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
2833
2834         /* Add 24 bytes to size to account for CRC, preamble, and gap */
2835         avg_wire_size += 24;
2836
2837         /* Don't starve jumbo frames */
2838         avg_wire_size = min(avg_wire_size, 3000);
2839
2840         /* Give a little boost to mid-size frames */
2841         if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2842                 new_val = avg_wire_size / 3;
2843         else
2844                 new_val = avg_wire_size / 2;
2845
2846 set_itr_val:
2847         if (new_val != rx_ring->itr_val) {
2848                 rx_ring->itr_val = new_val;
2849                 rx_ring->set_itr = 1;
2850         }
2851 clear_counts:
2852         rx_ring->total_bytes = 0;
2853         rx_ring->total_packets = 0;
2854 }
2855
2856 /**
2857  * igb_update_itr - update the dynamic ITR value based on statistics
2858  *      Stores a new ITR value based on packets and byte
2859  *      counts during the last interrupt.  The advantage of per interrupt
2860  *      computation is faster updates and more accurate ITR for the current
2861  *      traffic pattern.  Constants in this function were computed
2862  *      based on theoretical maximum wire speed and thresholds were set based
2863  *      on testing data as well as attempting to minimize response time
2864  *      while increasing bulk throughput.
2865  *      this functionality is controlled by the InterruptThrottleRate module
2866  *      parameter (see igb_param.c)
2867  *      NOTE:  These calculations are only valid when operating in a single-
2868  *             queue environment.
2869  * @adapter: pointer to adapter
2870  * @itr_setting: current adapter->itr
2871  * @packets: the number of packets during this measurement interval
2872  * @bytes: the number of bytes during this measurement interval
2873  **/
2874 static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2875                                    int packets, int bytes)
2876 {
2877         unsigned int retval = itr_setting;
2878
2879         if (packets == 0)
2880                 goto update_itr_done;
2881
2882         switch (itr_setting) {
2883         case lowest_latency:
2884                 /* handle TSO and jumbo frames */
2885                 if (bytes/packets > 8000)
2886                         retval = bulk_latency;
2887                 else if ((packets < 5) && (bytes > 512))
2888                         retval = low_latency;
2889                 break;
2890         case low_latency:  /* 50 usec aka 20000 ints/s */
2891                 if (bytes > 10000) {
2892                         /* this if handles the TSO accounting */
2893                         if (bytes/packets > 8000) {
2894                                 retval = bulk_latency;
2895                         } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2896                                 retval = bulk_latency;
2897                         } else if ((packets > 35)) {
2898                                 retval = lowest_latency;
2899                         }
2900                 } else if (bytes/packets > 2000) {
2901                         retval = bulk_latency;
2902                 } else if (packets <= 2 && bytes < 512) {
2903                         retval = lowest_latency;
2904                 }
2905                 break;
2906         case bulk_latency: /* 250 usec aka 4000 ints/s */
2907                 if (bytes > 25000) {
2908                         if (packets > 35)
2909                                 retval = low_latency;
2910                 } else if (bytes < 1500) {
2911                         retval = low_latency;
2912                 }
2913                 break;
2914         }
2915
2916 update_itr_done:
2917         return retval;
2918 }
2919
2920 static void igb_set_itr(struct igb_adapter *adapter)
2921 {
2922         u16 current_itr;
2923         u32 new_itr = adapter->itr;
2924
2925         /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2926         if (adapter->link_speed != SPEED_1000) {
2927                 current_itr = 0;
2928                 new_itr = 4000;
2929                 goto set_itr_now;
2930         }
2931
2932         adapter->rx_itr = igb_update_itr(adapter,
2933                                     adapter->rx_itr,
2934                                     adapter->rx_ring->total_packets,
2935                                     adapter->rx_ring->total_bytes);
2936
2937         if (adapter->rx_ring->buddy) {
2938                 adapter->tx_itr = igb_update_itr(adapter,
2939                                             adapter->tx_itr,
2940                                             adapter->tx_ring->total_packets,
2941                                             adapter->tx_ring->total_bytes);
2942                 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2943         } else {
2944                 current_itr = adapter->rx_itr;
2945         }
2946
2947         /* conservative mode (itr 3) eliminates the lowest_latency setting */
2948         if (adapter->itr_setting == 3 && current_itr == lowest_latency)
2949                 current_itr = low_latency;
2950
2951         switch (current_itr) {
2952         /* counts and packets in update_itr are dependent on these numbers */
2953         case lowest_latency:
2954                 new_itr = 56;  /* aka 70,000 ints/sec */
2955                 break;
2956         case low_latency:
2957                 new_itr = 196; /* aka 20,000 ints/sec */
2958                 break;
2959         case bulk_latency:
2960                 new_itr = 980; /* aka 4,000 ints/sec */
2961                 break;
2962         default:
2963                 break;
2964         }
2965
2966 set_itr_now:
2967         adapter->rx_ring->total_bytes = 0;
2968         adapter->rx_ring->total_packets = 0;
2969         if (adapter->rx_ring->buddy) {
2970                 adapter->rx_ring->buddy->total_bytes = 0;
2971                 adapter->rx_ring->buddy->total_packets = 0;
2972         }
2973
2974         if (new_itr != adapter->itr) {
2975                 /* this attempts to bias the interrupt rate towards Bulk
2976                  * by adding intermediate steps when interrupt rate is
2977                  * increasing */
2978                 new_itr = new_itr > adapter->itr ?
2979                              max((new_itr * adapter->itr) /
2980                                  (new_itr + (adapter->itr >> 2)), new_itr) :
2981                              new_itr;
2982                 /* Don't write the value here; it resets the adapter's
2983                  * internal timer, and causes us to delay far longer than
2984                  * we should between interrupts.  Instead, we write the ITR
2985                  * value at the beginning of the next interrupt so the timing
2986                  * ends up being correct.
2987                  */
2988                 adapter->itr = new_itr;
2989                 adapter->rx_ring->itr_val = new_itr;
2990                 adapter->rx_ring->set_itr = 1;
2991         }
2992
2993         return;
2994 }
2995
2996
2997 #define IGB_TX_FLAGS_CSUM               0x00000001
2998 #define IGB_TX_FLAGS_VLAN               0x00000002
2999 #define IGB_TX_FLAGS_TSO                0x00000004
3000 #define IGB_TX_FLAGS_IPV4               0x00000008
3001 #define IGB_TX_FLAGS_TSTAMP             0x00000010
3002 #define IGB_TX_FLAGS_VLAN_MASK  0xffff0000
3003 #define IGB_TX_FLAGS_VLAN_SHIFT 16
3004
3005 static inline int igb_tso_adv(struct igb_adapter *adapter,
3006                               struct igb_ring *tx_ring,
3007                               struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
3008 {
3009         struct e1000_adv_tx_context_desc *context_desc;
3010         unsigned int i;
3011         int err;
3012         struct igb_buffer *buffer_info;
3013         u32 info = 0, tu_cmd = 0;
3014         u32 mss_l4len_idx, l4len;
3015         *hdr_len = 0;
3016
3017         if (skb_header_cloned(skb)) {
3018                 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3019                 if (err)
3020                         return err;
3021         }
3022
3023         l4len = tcp_hdrlen(skb);
3024         *hdr_len += l4len;
3025
3026         if (skb->protocol == htons(ETH_P_IP)) {
3027                 struct iphdr *iph = ip_hdr(skb);
3028                 iph->tot_len = 0;
3029                 iph->check = 0;
3030                 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
3031                                                          iph->daddr, 0,
3032                                                          IPPROTO_TCP,
3033                                                          0);
3034         } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
3035                 ipv6_hdr(skb)->payload_len = 0;
3036                 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3037                                                        &ipv6_hdr(skb)->daddr,
3038                                                        0, IPPROTO_TCP, 0);
3039         }
3040
3041         i = tx_ring->next_to_use;
3042
3043         buffer_info = &tx_ring->buffer_info[i];
3044         context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3045         /* VLAN MACLEN IPLEN */
3046         if (tx_flags & IGB_TX_FLAGS_VLAN)
3047                 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3048         info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3049         *hdr_len += skb_network_offset(skb);
3050         info |= skb_network_header_len(skb);
3051         *hdr_len += skb_network_header_len(skb);
3052         context_desc->vlan_macip_lens = cpu_to_le32(info);
3053
3054         /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3055         tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3056
3057         if (skb->protocol == htons(ETH_P_IP))
3058                 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3059         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3060
3061         context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3062
3063         /* MSS L4LEN IDX */
3064         mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
3065         mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
3066
3067         /* For 82575, context index must be unique per ring. */
3068         if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3069                 mss_l4len_idx |= tx_ring->queue_index << 4;
3070
3071         context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3072         context_desc->seqnum_seed = 0;
3073
3074         buffer_info->time_stamp = jiffies;
3075         buffer_info->next_to_watch = i;
3076         buffer_info->dma = 0;
3077         i++;
3078         if (i == tx_ring->count)
3079                 i = 0;
3080
3081         tx_ring->next_to_use = i;
3082
3083         return true;
3084 }
3085
3086 static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
3087                                         struct igb_ring *tx_ring,
3088                                         struct sk_buff *skb, u32 tx_flags)
3089 {
3090         struct e1000_adv_tx_context_desc *context_desc;
3091         unsigned int i;
3092         struct igb_buffer *buffer_info;
3093         u32 info = 0, tu_cmd = 0;
3094
3095         if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
3096             (tx_flags & IGB_TX_FLAGS_VLAN)) {
3097                 i = tx_ring->next_to_use;
3098                 buffer_info = &tx_ring->buffer_info[i];
3099                 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3100
3101                 if (tx_flags & IGB_TX_FLAGS_VLAN)
3102                         info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3103                 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3104                 if (skb->ip_summed == CHECKSUM_PARTIAL)
3105                         info |= skb_network_header_len(skb);
3106
3107                 context_desc->vlan_macip_lens = cpu_to_le32(info);
3108
3109                 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3110
3111                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3112                         __be16 protocol;
3113
3114                         if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
3115                                 const struct vlan_ethhdr *vhdr =
3116                                           (const struct vlan_ethhdr*)skb->data;
3117
3118                                 protocol = vhdr->h_vlan_encapsulated_proto;
3119                         } else {
3120                                 protocol = skb->protocol;
3121                         }
3122
3123                         switch (protocol) {
3124                         case cpu_to_be16(ETH_P_IP):
3125                                 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3126                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3127                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3128                                 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
3129                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
3130                                 break;
3131                         case cpu_to_be16(ETH_P_IPV6):
3132                                 /* XXX what about other V6 headers?? */
3133                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3134                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3135                                 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
3136                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
3137                                 break;
3138                         default:
3139                                 if (unlikely(net_ratelimit()))
3140                                         dev_warn(&adapter->pdev->dev,
3141                                             "partial checksum but proto=%x!\n",
3142                                             skb->protocol);
3143                                 break;
3144                         }
3145                 }
3146
3147                 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3148                 context_desc->seqnum_seed = 0;
3149                 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3150                         context_desc->mss_l4len_idx =
3151                                 cpu_to_le32(tx_ring->queue_index << 4);
3152                 else
3153                         context_desc->mss_l4len_idx = 0;
3154
3155                 buffer_info->time_stamp = jiffies;
3156                 buffer_info->next_to_watch = i;
3157                 buffer_info->dma = 0;
3158
3159                 i++;
3160                 if (i == tx_ring->count)
3161                         i = 0;
3162                 tx_ring->next_to_use = i;
3163
3164                 return true;
3165         }
3166         return false;
3167 }
3168
3169 #define IGB_MAX_TXD_PWR 16
3170 #define IGB_MAX_DATA_PER_TXD    (1<<IGB_MAX_TXD_PWR)
3171
3172 static inline int igb_tx_map_adv(struct igb_adapter *adapter,
3173                                  struct igb_ring *tx_ring, struct sk_buff *skb,
3174                                  unsigned int first)
3175 {
3176         struct igb_buffer *buffer_info;
3177         unsigned int len = skb_headlen(skb);
3178         unsigned int count = 0, i;
3179         unsigned int f;
3180         dma_addr_t *map;
3181
3182         i = tx_ring->next_to_use;
3183
3184         if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
3185                 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
3186                 return 0;
3187         }
3188
3189         map = skb_shinfo(skb)->dma_maps;
3190
3191         buffer_info = &tx_ring->buffer_info[i];
3192         BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3193         buffer_info->length = len;
3194         /* set time_stamp *before* dma to help avoid a possible race */
3195         buffer_info->time_stamp = jiffies;
3196         buffer_info->next_to_watch = i;
3197         buffer_info->dma = skb_shinfo(skb)->dma_head;
3198
3199         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
3200                 struct skb_frag_struct *frag;
3201
3202                 i++;
3203                 if (i == tx_ring->count)
3204                         i = 0;
3205
3206                 frag = &skb_shinfo(skb)->frags[f];
3207                 len = frag->size;
3208
3209                 buffer_info = &tx_ring->buffer_info[i];
3210                 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3211                 buffer_info->length = len;
3212                 buffer_info->time_stamp = jiffies;
3213                 buffer_info->next_to_watch = i;
3214                 buffer_info->dma = map[count];
3215                 count++;
3216         }
3217
3218         tx_ring->buffer_info[i].skb = skb;
3219         tx_ring->buffer_info[first].next_to_watch = i;
3220
3221         return count + 1;
3222 }
3223
3224 static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
3225                                     struct igb_ring *tx_ring,
3226                                     int tx_flags, int count, u32 paylen,
3227                                     u8 hdr_len)
3228 {
3229         union e1000_adv_tx_desc *tx_desc = NULL;
3230         struct igb_buffer *buffer_info;
3231         u32 olinfo_status = 0, cmd_type_len;
3232         unsigned int i;
3233
3234         cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
3235                         E1000_ADVTXD_DCMD_DEXT);
3236
3237         if (tx_flags & IGB_TX_FLAGS_VLAN)
3238                 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3239
3240         if (tx_flags & IGB_TX_FLAGS_TSTAMP)
3241                 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
3242
3243         if (tx_flags & IGB_TX_FLAGS_TSO) {
3244                 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3245
3246                 /* insert tcp checksum */
3247                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3248
3249                 /* insert ip checksum */
3250                 if (tx_flags & IGB_TX_FLAGS_IPV4)
3251                         olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3252
3253         } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
3254                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3255         }
3256
3257         if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
3258             (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
3259                          IGB_TX_FLAGS_VLAN)))
3260                 olinfo_status |= tx_ring->queue_index << 4;
3261
3262         olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
3263
3264         i = tx_ring->next_to_use;
3265         while (count--) {
3266                 buffer_info = &tx_ring->buffer_info[i];
3267                 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3268                 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
3269                 tx_desc->read.cmd_type_len =
3270                         cpu_to_le32(cmd_type_len | buffer_info->length);
3271                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3272                 i++;
3273                 if (i == tx_ring->count)
3274                         i = 0;
3275         }
3276
3277         tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
3278         /* Force memory writes to complete before letting h/w
3279          * know there are new descriptors to fetch.  (Only
3280          * applicable for weak-ordered memory model archs,
3281          * such as IA-64). */
3282         wmb();
3283
3284         tx_ring->next_to_use = i;
3285         writel(i, adapter->hw.hw_addr + tx_ring->tail);
3286         /* we need this if more than one processor can write to our tail
3287          * at a time, it syncronizes IO on IA64/Altix systems */
3288         mmiowb();
3289 }
3290
3291 static int __igb_maybe_stop_tx(struct net_device *netdev,
3292                                struct igb_ring *tx_ring, int size)
3293 {
3294         struct igb_adapter *adapter = netdev_priv(netdev);
3295
3296         netif_stop_subqueue(netdev, tx_ring->queue_index);
3297
3298         /* Herbert's original patch had:
3299          *  smp_mb__after_netif_stop_queue();
3300          * but since that doesn't exist yet, just open code it. */
3301         smp_mb();
3302
3303         /* We need to check again in a case another CPU has just
3304          * made room available. */
3305         if (igb_desc_unused(tx_ring) < size)
3306                 return -EBUSY;
3307
3308         /* A reprieve! */
3309         netif_wake_subqueue(netdev, tx_ring->queue_index);
3310         ++adapter->restart_queue;
3311         return 0;
3312 }
3313
3314 static int igb_maybe_stop_tx(struct net_device *netdev,
3315                              struct igb_ring *tx_ring, int size)
3316 {
3317         if (igb_desc_unused(tx_ring) >= size)
3318                 return 0;
3319         return __igb_maybe_stop_tx(netdev, tx_ring, size);
3320 }
3321
3322 static netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *skb,
3323                                            struct net_device *netdev,
3324                                            struct igb_ring *tx_ring)
3325 {
3326         struct igb_adapter *adapter = netdev_priv(netdev);
3327         unsigned int first;
3328         unsigned int tx_flags = 0;
3329         u8 hdr_len = 0;
3330         int count = 0;
3331         int tso = 0;
3332         union skb_shared_tx *shtx;
3333
3334         if (test_bit(__IGB_DOWN, &adapter->state)) {
3335                 dev_kfree_skb_any(skb);
3336                 return NETDEV_TX_OK;
3337         }
3338
3339         if (skb->len <= 0) {
3340                 dev_kfree_skb_any(skb);
3341                 return NETDEV_TX_OK;
3342         }
3343
3344         /* need: 1 descriptor per page,
3345          *       + 2 desc gap to keep tail from touching head,
3346          *       + 1 desc for skb->data,
3347          *       + 1 desc for context descriptor,
3348          * otherwise try next time */
3349         if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
3350                 /* this is a hard error */
3351                 return NETDEV_TX_BUSY;
3352         }
3353
3354         /*
3355          * TODO: check that there currently is no other packet with
3356          * time stamping in the queue
3357          *
3358          * When doing time stamping, keep the connection to the socket
3359          * a while longer: it is still needed by skb_hwtstamp_tx(),
3360          * called either in igb_tx_hwtstamp() or by our caller when
3361          * doing software time stamping.
3362          */
3363         shtx = skb_tx(skb);
3364         if (unlikely(shtx->hardware)) {
3365                 shtx->in_progress = 1;
3366                 tx_flags |= IGB_TX_FLAGS_TSTAMP;
3367         }
3368
3369         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3370                 tx_flags |= IGB_TX_FLAGS_VLAN;
3371                 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
3372         }
3373
3374         if (skb->protocol == htons(ETH_P_IP))
3375                 tx_flags |= IGB_TX_FLAGS_IPV4;
3376
3377         first = tx_ring->next_to_use;
3378         tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
3379                                               &hdr_len) : 0;
3380
3381         if (tso < 0) {
3382                 dev_kfree_skb_any(skb);
3383                 return NETDEV_TX_OK;
3384         }
3385
3386         if (tso)
3387                 tx_flags |= IGB_TX_FLAGS_TSO;
3388         else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags) &&
3389                  (skb->ip_summed == CHECKSUM_PARTIAL))
3390                 tx_flags |= IGB_TX_FLAGS_CSUM;
3391
3392         /*
3393          * count reflects descriptors mapped, if 0 then mapping error
3394          * has occured and we need to rewind the descriptor queue
3395          */
3396         count = igb_tx_map_adv(adapter, tx_ring, skb, first);
3397
3398         if (count) {
3399                 igb_tx_queue_adv(adapter, tx_ring, tx_flags, count,
3400                                  skb->len, hdr_len);
3401                 /* Make sure there is space in the ring for the next send. */
3402                 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3403         } else {
3404                 dev_kfree_skb_any(skb);
3405                 tx_ring->buffer_info[first].time_stamp = 0;
3406                 tx_ring->next_to_use = first;
3407         }
3408
3409         return NETDEV_TX_OK;
3410 }
3411
3412 static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb,
3413                                       struct net_device *netdev)
3414 {
3415         struct igb_adapter *adapter = netdev_priv(netdev);
3416         struct igb_ring *tx_ring;
3417
3418         int r_idx = 0;
3419         r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
3420         tx_ring = adapter->multi_tx_table[r_idx];
3421
3422         /* This goes back to the question of how to logically map a tx queue
3423          * to a flow.  Right now, performance is impacted slightly negatively
3424          * if using multiple tx queues.  If the stack breaks away from a
3425          * single qdisc implementation, we can look at this again. */
3426         return igb_xmit_frame_ring_adv(skb, netdev, tx_ring);
3427 }
3428
3429 /**
3430  * igb_tx_timeout - Respond to a Tx Hang
3431  * @netdev: network interface device structure
3432  **/
3433 static void igb_tx_timeout(struct net_device *netdev)
3434 {
3435         struct igb_adapter *adapter = netdev_priv(netdev);
3436         struct e1000_hw *hw = &adapter->hw;
3437
3438         /* Do the reset outside of interrupt context */
3439         adapter->tx_timeout_count++;
3440         schedule_work(&adapter->reset_task);
3441         wr32(E1000_EICS,
3442              (adapter->eims_enable_mask & ~adapter->eims_other));
3443 }
3444
3445 static void igb_reset_task(struct work_struct *work)
3446 {
3447         struct igb_adapter *adapter;
3448         adapter = container_of(work, struct igb_adapter, reset_task);
3449
3450         igb_reinit_locked(adapter);
3451 }
3452
3453 /**
3454  * igb_get_stats - Get System Network Statistics
3455  * @netdev: network interface device structure
3456  *
3457  * Returns the address of the device statistics structure.
3458  * The statistics are actually updated from the timer callback.
3459  **/
3460 static struct net_device_stats *igb_get_stats(struct net_device *netdev)
3461 {
3462         struct igb_adapter *adapter = netdev_priv(netdev);
3463
3464         /* only return the current stats */
3465         return &adapter->net_stats;
3466 }
3467
3468 /**
3469  * igb_change_mtu - Change the Maximum Transfer Unit
3470  * @netdev: network interface device structure
3471  * @new_mtu: new value for maximum frame size
3472  *
3473  * Returns 0 on success, negative on failure
3474  **/
3475 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3476 {
3477         struct igb_adapter *adapter = netdev_priv(netdev);
3478         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3479
3480         if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3481             (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3482                 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3483                 return -EINVAL;
3484         }
3485
3486         if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3487                 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3488                 return -EINVAL;
3489         }
3490
3491         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3492                 msleep(1);
3493
3494         /* igb_down has a dependency on max_frame_size */
3495         adapter->max_frame_size = max_frame;
3496         if (netif_running(netdev))
3497                 igb_down(adapter);
3498
3499         /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3500          * means we reserve 2 more, this pushes us to allocate from the next
3501          * larger slab size.
3502          * i.e. RXBUFFER_2048 --> size-4096 slab
3503          */
3504
3505         if (max_frame <= IGB_RXBUFFER_256)
3506                 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3507         else if (max_frame <= IGB_RXBUFFER_512)
3508                 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3509         else if (max_frame <= IGB_RXBUFFER_1024)
3510                 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3511         else if (max_frame <= IGB_RXBUFFER_2048)
3512                 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3513         else
3514 #if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3515                 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3516 #else
3517                 adapter->rx_buffer_len = PAGE_SIZE / 2;
3518 #endif
3519
3520         /* if sr-iov is enabled we need to force buffer size to 1K or larger */
3521         if (adapter->vfs_allocated_count &&
3522             (adapter->rx_buffer_len < IGB_RXBUFFER_1024))
3523                 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3524
3525         /* adjust allocation if LPE protects us, and we aren't using SBP */
3526         if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3527              (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3528                 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3529
3530         dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3531                  netdev->mtu, new_mtu);
3532         netdev->mtu = new_mtu;
3533
3534         if (netif_running(netdev))
3535                 igb_up(adapter);
3536         else
3537                 igb_reset(adapter);
3538
3539         clear_bit(__IGB_RESETTING, &adapter->state);
3540
3541         return 0;
3542 }
3543
3544 /**
3545  * igb_update_stats - Update the board statistics counters
3546  * @adapter: board private structure
3547  **/
3548
3549 void igb_update_stats(struct igb_adapter *adapter)
3550 {
3551         struct e1000_hw *hw = &adapter->hw;
3552         struct pci_dev *pdev = adapter->pdev;
3553         u16 phy_tmp;
3554
3555 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3556
3557         /*
3558          * Prevent stats update while adapter is being reset, or if the pci
3559          * connection is down.
3560          */
3561         if (adapter->link_speed == 0)
3562                 return;
3563         if (pci_channel_offline(pdev))
3564                 return;
3565
3566         adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3567         adapter->stats.gprc += rd32(E1000_GPRC);
3568         adapter->stats.gorc += rd32(E1000_GORCL);
3569         rd32(E1000_GORCH); /* clear GORCL */
3570         adapter->stats.bprc += rd32(E1000_BPRC);
3571         adapter->stats.mprc += rd32(E1000_MPRC);
3572         adapter->stats.roc += rd32(E1000_ROC);
3573
3574         adapter->stats.prc64 += rd32(E1000_PRC64);
3575         adapter->stats.prc127 += rd32(E1000_PRC127);
3576         adapter->stats.prc255 += rd32(E1000_PRC255);
3577         adapter->stats.prc511 += rd32(E1000_PRC511);
3578         adapter->stats.prc1023 += rd32(E1000_PRC1023);
3579         adapter->stats.prc1522 += rd32(E1000_PRC1522);
3580         adapter->stats.symerrs += rd32(E1000_SYMERRS);
3581         adapter->stats.sec += rd32(E1000_SEC);
3582
3583         adapter->stats.mpc += rd32(E1000_MPC);
3584         adapter->stats.scc += rd32(E1000_SCC);
3585         adapter->stats.ecol += rd32(E1000_ECOL);
3586         adapter->stats.mcc += rd32(E1000_MCC);
3587         adapter->stats.latecol += rd32(E1000_LATECOL);
3588         adapter->stats.dc += rd32(E1000_DC);
3589         adapter->stats.rlec += rd32(E1000_RLEC);
3590         adapter->stats.xonrxc += rd32(E1000_XONRXC);
3591         adapter->stats.xontxc += rd32(E1000_XONTXC);
3592         adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3593         adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3594         adapter->stats.fcruc += rd32(E1000_FCRUC);
3595         adapter->stats.gptc += rd32(E1000_GPTC);
3596         adapter->stats.gotc += rd32(E1000_GOTCL);
3597         rd32(E1000_GOTCH); /* clear GOTCL */
3598         adapter->stats.rnbc += rd32(E1000_RNBC);
3599         adapter->stats.ruc += rd32(E1000_RUC);
3600         adapter->stats.rfc += rd32(E1000_RFC);
3601         adapter->stats.rjc += rd32(E1000_RJC);
3602         adapter->stats.tor += rd32(E1000_TORH);
3603         adapter->stats.tot += rd32(E1000_TOTH);
3604         adapter->stats.tpr += rd32(E1000_TPR);
3605
3606         adapter->stats.ptc64 += rd32(E1000_PTC64);
3607         adapter->stats.ptc127 += rd32(E1000_PTC127);
3608         adapter->stats.ptc255 += rd32(E1000_PTC255);
3609         adapter->stats.ptc511 += rd32(E1000_PTC511);
3610         adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3611         adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3612
3613         adapter->stats.mptc += rd32(E1000_MPTC);
3614         adapter->stats.bptc += rd32(E1000_BPTC);
3615
3616         /* used for adaptive IFS */
3617
3618         hw->mac.tx_packet_delta = rd32(E1000_TPT);
3619         adapter->stats.tpt += hw->mac.tx_packet_delta;
3620         hw->mac.collision_delta = rd32(E1000_COLC);
3621         adapter->stats.colc += hw->mac.collision_delta;
3622
3623         adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3624         adapter->stats.rxerrc += rd32(E1000_RXERRC);
3625         adapter->stats.tncrs += rd32(E1000_TNCRS);
3626         adapter->stats.tsctc += rd32(E1000_TSCTC);
3627         adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3628
3629         adapter->stats.iac += rd32(E1000_IAC);
3630         adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3631         adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3632         adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3633         adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3634         adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3635         adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3636         adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3637         adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3638
3639         /* Fill out the OS statistics structure */
3640         adapter->net_stats.multicast = adapter->stats.mprc;
3641         adapter->net_stats.collisions = adapter->stats.colc;
3642
3643         /* Rx Errors */
3644
3645         if (hw->mac.type != e1000_82575) {
3646                 u32 rqdpc_tmp;
3647                 u64 rqdpc_total = 0;
3648                 int i;
3649                 /* Read out drops stats per RX queue.  Notice RQDPC (Receive
3650                  * Queue Drop Packet Count) stats only gets incremented, if
3651                  * the DROP_EN but it set (in the SRRCTL register for that
3652                  * queue).  If DROP_EN bit is NOT set, then the some what
3653                  * equivalent count is stored in RNBC (not per queue basis).
3654                  * Also note the drop count is due to lack of available
3655                  * descriptors.
3656                  */
3657                 for (i = 0; i < adapter->num_rx_queues; i++) {
3658                         rqdpc_tmp = rd32(E1000_RQDPC(i)) & 0xFFF;
3659                         adapter->rx_ring[i].rx_stats.drops += rqdpc_tmp;
3660                         rqdpc_total += adapter->rx_ring[i].rx_stats.drops;
3661                 }
3662                 adapter->net_stats.rx_fifo_errors = rqdpc_total;
3663         }
3664
3665         /* Note RNBC (Receive No Buffers Count) is an not an exact
3666          * drop count as the hardware FIFO might save the day.  Thats
3667          * one of the reason for saving it in rx_fifo_errors, as its
3668          * potentially not a true drop.
3669          */
3670         adapter->net_stats.rx_fifo_errors += adapter->stats.rnbc;
3671
3672         /* RLEC on some newer hardware can be incorrect so build
3673          * our own version based on RUC and ROC */
3674         adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3675                 adapter->stats.crcerrs + adapter->stats.algnerrc +
3676                 adapter->stats.ruc + adapter->stats.roc +
3677                 adapter->stats.cexterr;
3678         adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3679                                               adapter->stats.roc;
3680         adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3681         adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3682         adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3683
3684         /* Tx Errors */
3685         adapter->net_stats.tx_errors = adapter->stats.ecol +
3686                                        adapter->stats.latecol;
3687         adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3688         adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3689         adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3690
3691         /* Tx Dropped needs to be maintained elsewhere */
3692
3693         /* Phy Stats */
3694         if (hw->phy.media_type == e1000_media_type_copper) {
3695                 if ((adapter->link_speed == SPEED_1000) &&
3696                    (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
3697                         phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3698                         adapter->phy_stats.idle_errors += phy_tmp;
3699                 }
3700         }
3701
3702         /* Management Stats */
3703         adapter->stats.mgptc += rd32(E1000_MGTPTC);
3704         adapter->stats.mgprc += rd32(E1000_MGTPRC);
3705         adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3706 }
3707
3708 static irqreturn_t igb_msix_other(int irq, void *data)
3709 {
3710         struct net_device *netdev = data;
3711         struct igb_adapter *adapter = netdev_priv(netdev);
3712         struct e1000_hw *hw = &adapter->hw;
3713         u32 icr = rd32(E1000_ICR);
3714
3715         /* reading ICR causes bit 31 of EICR to be cleared */
3716
3717         if(icr & E1000_ICR_DOUTSYNC) {
3718                 /* HW is reporting DMA is out of sync */
3719                 adapter->stats.doosync++;
3720         }
3721
3722         /* Check for a mailbox event */
3723         if (icr & E1000_ICR_VMMB)
3724                 igb_msg_task(adapter);
3725
3726         if (icr & E1000_ICR_LSC) {
3727                 hw->mac.get_link_status = 1;
3728                 /* guard against interrupt when we're going down */
3729                 if (!test_bit(__IGB_DOWN, &adapter->state))
3730                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
3731         }
3732
3733         wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_VMMB);
3734         wr32(E1000_EIMS, adapter->eims_other);
3735
3736         return IRQ_HANDLED;
3737 }
3738
3739 static irqreturn_t igb_msix_tx(int irq, void *data)
3740 {
3741         struct igb_ring *tx_ring = data;
3742         struct igb_adapter *adapter = tx_ring->adapter;
3743         struct e1000_hw *hw = &adapter->hw;
3744
3745 #ifdef CONFIG_IGB_DCA
3746         if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3747                 igb_update_tx_dca(tx_ring);
3748 #endif
3749
3750         tx_ring->total_bytes = 0;
3751         tx_ring->total_packets = 0;
3752
3753         /* auto mask will automatically reenable the interrupt when we write
3754          * EICS */
3755         if (!igb_clean_tx_irq(tx_ring))
3756                 /* Ring was not completely cleaned, so fire another interrupt */
3757                 wr32(E1000_EICS, tx_ring->eims_value);
3758         else
3759                 wr32(E1000_EIMS, tx_ring->eims_value);
3760
3761         return IRQ_HANDLED;
3762 }
3763
3764 static void igb_write_itr(struct igb_ring *ring)
3765 {
3766         struct e1000_hw *hw = &ring->adapter->hw;
3767         if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3768                 switch (hw->mac.type) {
3769                 case e1000_82576:
3770                         wr32(ring->itr_register, ring->itr_val |
3771                              0x80000000);
3772                         break;
3773                 default:
3774                         wr32(ring->itr_register, ring->itr_val |
3775                              (ring->itr_val << 16));
3776                         break;
3777                 }
3778                 ring->set_itr = 0;
3779         }
3780 }
3781
3782 static irqreturn_t igb_msix_rx(int irq, void *data)
3783 {
3784         struct igb_ring *rx_ring = data;
3785
3786         /* Write the ITR value calculated at the end of the
3787          * previous interrupt.
3788          */
3789
3790         igb_write_itr(rx_ring);
3791
3792         if (napi_schedule_prep(&rx_ring->napi))
3793                 __napi_schedule(&rx_ring->napi);
3794
3795 #ifdef CONFIG_IGB_DCA
3796         if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
3797                 igb_update_rx_dca(rx_ring);
3798 #endif
3799                 return IRQ_HANDLED;
3800 }
3801
3802 #ifdef CONFIG_IGB_DCA
3803 static void igb_update_rx_dca(struct igb_ring *rx_ring)
3804 {
3805         u32 dca_rxctrl;
3806         struct igb_adapter *adapter = rx_ring->adapter;
3807         struct e1000_hw *hw = &adapter->hw;
3808         int cpu = get_cpu();
3809         int q = rx_ring->reg_idx;
3810
3811         if (rx_ring->cpu != cpu) {
3812                 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
3813                 if (hw->mac.type == e1000_82576) {
3814                         dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3815                         dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
3816                                       E1000_DCA_RXCTRL_CPUID_SHIFT;
3817                 } else {
3818                         dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3819                         dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
3820                 }
3821                 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3822                 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3823                 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3824                 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3825                 rx_ring->cpu = cpu;
3826         }
3827         put_cpu();
3828 }
3829
3830 static void igb_update_tx_dca(struct igb_ring *tx_ring)
3831 {
3832         u32 dca_txctrl;
3833         struct igb_adapter *adapter = tx_ring->adapter;
3834         struct e1000_hw *hw = &adapter->hw;
3835         int cpu = get_cpu();
3836         int q = tx_ring->reg_idx;
3837
3838         if (tx_ring->cpu != cpu) {
3839                 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
3840                 if (hw->mac.type == e1000_82576) {
3841                         dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3842                         dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
3843                                       E1000_DCA_TXCTRL_CPUID_SHIFT;
3844                 } else {
3845                         dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3846                         dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
3847                 }
3848                 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3849                 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3850                 tx_ring->cpu = cpu;
3851         }
3852         put_cpu();
3853 }
3854
3855 static void igb_setup_dca(struct igb_adapter *adapter)
3856 {
3857         struct e1000_hw *hw = &adapter->hw;
3858         int i;
3859
3860         if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
3861                 return;
3862
3863         /* Always use CB2 mode, difference is masked in the CB driver. */
3864         wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
3865
3866         for (i = 0; i < adapter->num_tx_queues; i++) {
3867                 adapter->tx_ring[i].cpu = -1;
3868                 igb_update_tx_dca(&adapter->tx_ring[i]);
3869         }
3870         for (i = 0; i < adapter->num_rx_queues; i++) {
3871                 adapter->rx_ring[i].cpu = -1;
3872                 igb_update_rx_dca(&adapter->rx_ring[i]);
3873         }
3874 }
3875
3876 static int __igb_notify_dca(struct device *dev, void *data)
3877 {
3878         struct net_device *netdev = dev_get_drvdata(dev);
3879         struct igb_adapter *adapter = netdev_priv(netdev);
3880         struct e1000_hw *hw = &adapter->hw;
3881         unsigned long event = *(unsigned long *)data;
3882
3883         switch (event) {
3884         case DCA_PROVIDER_ADD:
3885                 /* if already enabled, don't do it again */
3886                 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3887                         break;
3888                 /* Always use CB2 mode, difference is masked
3889                  * in the CB driver. */
3890                 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
3891                 if (dca_add_requester(dev) == 0) {
3892                         adapter->flags |= IGB_FLAG_DCA_ENABLED;
3893                         dev_info(&adapter->pdev->dev, "DCA enabled\n");
3894                         igb_setup_dca(adapter);
3895                         break;
3896                 }
3897                 /* Fall Through since DCA is disabled. */
3898         case DCA_PROVIDER_REMOVE:
3899                 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
3900                         /* without this a class_device is left
3901                          * hanging around in the sysfs model */
3902                         dca_remove_requester(dev);
3903                         dev_info(&adapter->pdev->dev, "DCA disabled\n");
3904                         adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
3905                         wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
3906                 }
3907                 break;
3908         }
3909
3910         return 0;
3911 }
3912
3913 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3914                           void *p)
3915 {
3916         int ret_val;
3917
3918         ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3919                                          __igb_notify_dca);
3920
3921         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3922 }
3923 #endif /* CONFIG_IGB_DCA */
3924
3925 static void igb_ping_all_vfs(struct igb_adapter *adapter)
3926 {
3927         struct e1000_hw *hw = &adapter->hw;
3928         u32 ping;
3929         int i;
3930
3931         for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
3932                 ping = E1000_PF_CONTROL_MSG;
3933                 if (adapter->vf_data[i].clear_to_send)
3934                         ping |= E1000_VT_MSGTYPE_CTS;
3935                 igb_write_mbx(hw, &ping, 1, i);
3936         }
3937 }
3938
3939 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
3940                                   u32 *msgbuf, u32 vf)
3941 {
3942         int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
3943         u16 *hash_list = (u16 *)&msgbuf[1];
3944         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
3945         int i;
3946
3947         /* only up to 30 hash values supported */
3948         if (n > 30)
3949                 n = 30;
3950
3951         /* salt away the number of multi cast addresses assigned
3952          * to this VF for later use to restore when the PF multi cast
3953          * list changes
3954          */
3955         vf_data->num_vf_mc_hashes = n;
3956
3957         /* VFs are limited to using the MTA hash table for their multicast
3958          * addresses */
3959         for (i = 0; i < n; i++)
3960                 vf_data->vf_mc_hashes[i] = hash_list[i];
3961
3962         /* Flush and reset the mta with the new values */
3963         igb_set_rx_mode(adapter->netdev);
3964
3965         return 0;
3966 }
3967
3968 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
3969 {
3970         struct e1000_hw *hw = &adapter->hw;
3971         struct vf_data_storage *vf_data;
3972         int i, j;
3973
3974         for (i = 0; i < adapter->vfs_allocated_count; i++) {
3975                 vf_data = &adapter->vf_data[i];
3976                 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
3977                         igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
3978         }
3979 }
3980
3981 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
3982 {
3983         struct e1000_hw *hw = &adapter->hw;
3984         u32 pool_mask, reg, vid;
3985         int i;
3986
3987         pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
3988
3989         /* Find the vlan filter for this id */
3990         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3991                 reg = rd32(E1000_VLVF(i));
3992
3993                 /* remove the vf from the pool */
3994                 reg &= ~pool_mask;
3995
3996                 /* if pool is empty then remove entry from vfta */
3997                 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
3998                     (reg & E1000_VLVF_VLANID_ENABLE)) {
3999                         reg = 0;
4000                         vid = reg & E1000_VLVF_VLANID_MASK;
4001                         igb_vfta_set(hw, vid, false);
4002                 }
4003
4004                 wr32(E1000_VLVF(i), reg);
4005         }
4006
4007         adapter->vf_data[vf].vlans_enabled = 0;
4008 }
4009
4010 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
4011 {
4012         struct e1000_hw *hw = &adapter->hw;
4013         u32 reg, i;
4014
4015         /* It is an error to call this function when VFs are not enabled */
4016         if (!adapter->vfs_allocated_count)
4017                 return -1;
4018
4019         /* Find the vlan filter for this id */
4020         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4021                 reg = rd32(E1000_VLVF(i));
4022                 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
4023                     vid == (reg & E1000_VLVF_VLANID_MASK))
4024                         break;
4025         }
4026
4027         if (add) {
4028                 if (i == E1000_VLVF_ARRAY_SIZE) {
4029                         /* Did not find a matching VLAN ID entry that was
4030                          * enabled.  Search for a free filter entry, i.e.
4031                          * one without the enable bit set
4032                          */
4033                         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4034                                 reg = rd32(E1000_VLVF(i));
4035                                 if (!(reg & E1000_VLVF_VLANID_ENABLE))
4036                                         break;
4037                         }
4038                 }
4039                 if (i < E1000_VLVF_ARRAY_SIZE) {
4040                         /* Found an enabled/available entry */
4041                         reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4042
4043                         /* if !enabled we need to set this up in vfta */
4044                         if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
4045                                 /* add VID to filter table, if bit already set
4046                                  * PF must have added it outside of table */
4047                                 if (igb_vfta_set(hw, vid, true))
4048                                         reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT +
4049                                                 adapter->vfs_allocated_count);
4050                                 reg |= E1000_VLVF_VLANID_ENABLE;
4051                         }
4052                         reg &= ~E1000_VLVF_VLANID_MASK;
4053                         reg |= vid;
4054
4055                         wr32(E1000_VLVF(i), reg);
4056
4057                         /* do not modify RLPML for PF devices */
4058                         if (vf >= adapter->vfs_allocated_count)
4059                                 return 0;
4060
4061                         if (!adapter->vf_data[vf].vlans_enabled) {
4062                                 u32 size;
4063                                 reg = rd32(E1000_VMOLR(vf));
4064                                 size = reg & E1000_VMOLR_RLPML_MASK;
4065                                 size += 4;
4066                                 reg &= ~E1000_VMOLR_RLPML_MASK;
4067                                 reg |= size;
4068                                 wr32(E1000_VMOLR(vf), reg);
4069                         }
4070                         adapter->vf_data[vf].vlans_enabled++;
4071
4072                         return 0;
4073                 }
4074         } else {
4075                 if (i < E1000_VLVF_ARRAY_SIZE) {
4076                         /* remove vf from the pool */
4077                         reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
4078                         /* if pool is empty then remove entry from vfta */
4079                         if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
4080                                 reg = 0;
4081                                 igb_vfta_set(hw, vid, false);
4082                         }
4083                         wr32(E1000_VLVF(i), reg);
4084
4085                         /* do not modify RLPML for PF devices */
4086                         if (vf >= adapter->vfs_allocated_count)
4087                                 return 0;
4088
4089                         adapter->vf_data[vf].vlans_enabled--;
4090                         if (!adapter->vf_data[vf].vlans_enabled) {
4091                                 u32 size;
4092                                 reg = rd32(E1000_VMOLR(vf));
4093                                 size = reg & E1000_VMOLR_RLPML_MASK;
4094                                 size -= 4;
4095                                 reg &= ~E1000_VMOLR_RLPML_MASK;
4096                                 reg |= size;
4097                                 wr32(E1000_VMOLR(vf), reg);
4098                         }
4099                         return 0;
4100                 }
4101         }
4102         return -1;
4103 }
4104
4105 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
4106 {
4107         int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4108         int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
4109
4110         return igb_vlvf_set(adapter, vid, add, vf);
4111 }
4112
4113 static inline void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
4114 {
4115         struct e1000_hw *hw = &adapter->hw;
4116
4117         /* disable mailbox functionality for vf */
4118         adapter->vf_data[vf].clear_to_send = false;
4119
4120         /* reset offloads to defaults */
4121         igb_set_vmolr(hw, vf);
4122
4123         /* reset vlans for device */
4124         igb_clear_vf_vfta(adapter, vf);
4125
4126         /* reset multicast table array for vf */
4127         adapter->vf_data[vf].num_vf_mc_hashes = 0;
4128
4129         /* Flush and reset the mta with the new values */
4130         igb_set_rx_mode(adapter->netdev);
4131 }
4132
4133 static inline void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4134 {
4135         struct e1000_hw *hw = &adapter->hw;
4136         unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
4137         int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4138         u32 reg, msgbuf[3];
4139         u8 *addr = (u8 *)(&msgbuf[1]);
4140
4141         /* process all the same items cleared in a function level reset */
4142         igb_vf_reset_event(adapter, vf);
4143
4144         /* set vf mac address */
4145         igb_rar_set(hw, vf_mac, rar_entry);
4146         igb_set_rah_pool(hw, vf, rar_entry);
4147
4148         /* enable transmit and receive for vf */
4149         reg = rd32(E1000_VFTE);
4150         wr32(E1000_VFTE, reg | (1 << vf));
4151         reg = rd32(E1000_VFRE);
4152         wr32(E1000_VFRE, reg | (1 << vf));
4153
4154         /* enable mailbox functionality for vf */
4155         adapter->vf_data[vf].clear_to_send = true;
4156
4157         /* reply to reset with ack and vf mac address */
4158         msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
4159         memcpy(addr, vf_mac, 6);
4160         igb_write_mbx(hw, msgbuf, 3, vf);
4161 }
4162
4163 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
4164 {
4165                 unsigned char *addr = (char *)&msg[1];
4166                 int err = -1;
4167
4168                 if (is_valid_ether_addr(addr))
4169                         err = igb_set_vf_mac(adapter, vf, addr);
4170
4171                 return err;
4172
4173 }
4174
4175 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
4176 {
4177         struct e1000_hw *hw = &adapter->hw;
4178         u32 msg = E1000_VT_MSGTYPE_NACK;
4179
4180         /* if device isn't clear to send it shouldn't be reading either */
4181         if (!adapter->vf_data[vf].clear_to_send)
4182                 igb_write_mbx(hw, &msg, 1, vf);
4183 }
4184
4185
4186 static void igb_msg_task(struct igb_adapter *adapter)
4187 {
4188         struct e1000_hw *hw = &adapter->hw;
4189         u32 vf;
4190
4191         for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
4192                 /* process any reset requests */
4193                 if (!igb_check_for_rst(hw, vf)) {
4194                         adapter->vf_data[vf].clear_to_send = false;
4195                         igb_vf_reset_event(adapter, vf);
4196                 }
4197
4198                 /* process any messages pending */
4199                 if (!igb_check_for_msg(hw, vf))
4200                         igb_rcv_msg_from_vf(adapter, vf);
4201
4202                 /* process any acks */
4203                 if (!igb_check_for_ack(hw, vf))
4204                         igb_rcv_ack_from_vf(adapter, vf);
4205
4206         }
4207 }
4208
4209 static int igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4210 {
4211         u32 mbx_size = E1000_VFMAILBOX_SIZE;
4212         u32 msgbuf[mbx_size];
4213         struct e1000_hw *hw = &adapter->hw;
4214         s32 retval;
4215
4216         retval = igb_read_mbx(hw, msgbuf, mbx_size, vf);
4217
4218         if (retval)
4219                 dev_err(&adapter->pdev->dev,
4220                         "Error receiving message from VF\n");
4221
4222         /* this is a message we already processed, do nothing */
4223         if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
4224                 return retval;
4225
4226         /*
4227          * until the vf completes a reset it should not be
4228          * allowed to start any configuration.
4229          */
4230
4231         if (msgbuf[0] == E1000_VF_RESET) {
4232                 igb_vf_reset_msg(adapter, vf);
4233
4234                 return retval;
4235         }
4236
4237         if (!adapter->vf_data[vf].clear_to_send) {
4238                 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4239                 igb_write_mbx(hw, msgbuf, 1, vf);
4240                 return retval;
4241         }
4242
4243         switch ((msgbuf[0] & 0xFFFF)) {
4244         case E1000_VF_SET_MAC_ADDR:
4245                 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
4246                 break;
4247         case E1000_VF_SET_MULTICAST:
4248                 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
4249                 break;
4250         case E1000_VF_SET_LPE:
4251                 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
4252                 break;
4253         case E1000_VF_SET_VLAN:
4254                 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4255                 break;
4256         default:
4257                 dev_err(&adapter->pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4258                 retval = -1;
4259                 break;
4260         }
4261
4262         /* notify the VF of the results of what it sent us */
4263         if (retval)
4264                 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4265         else
4266                 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
4267
4268         msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
4269
4270         igb_write_mbx(hw, msgbuf, 1, vf);
4271
4272         return retval;
4273 }
4274
4275 /**
4276  * igb_intr_msi - Interrupt Handler
4277  * @irq: interrupt number
4278  * @data: pointer to a network interface device structure
4279  **/
4280 static irqreturn_t igb_intr_msi(int irq, void *data)
4281 {
4282         struct net_device *netdev = data;
4283         struct igb_adapter *adapter = netdev_priv(netdev);
4284         struct e1000_hw *hw = &adapter->hw;
4285         /* read ICR disables interrupts using IAM */
4286         u32 icr = rd32(E1000_ICR);
4287
4288         igb_write_itr(adapter->rx_ring);
4289
4290         if(icr & E1000_ICR_DOUTSYNC) {
4291                 /* HW is reporting DMA is out of sync */
4292                 adapter->stats.doosync++;
4293         }
4294
4295         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4296                 hw->mac.get_link_status = 1;
4297                 if (!test_bit(__IGB_DOWN, &adapter->state))
4298                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
4299         }
4300
4301         napi_schedule(&adapter->rx_ring[0].napi);
4302
4303         return IRQ_HANDLED;
4304 }
4305
4306 /**
4307  * igb_intr - Legacy Interrupt Handler
4308  * @irq: interrupt number
4309  * @data: pointer to a network interface device structure
4310  **/
4311 static irqreturn_t igb_intr(int irq, void *data)
4312 {
4313         struct net_device *netdev = data;
4314         struct igb_adapter *adapter = netdev_priv(netdev);
4315         struct e1000_hw *hw = &adapter->hw;
4316         /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked.  No
4317          * need for the IMC write */
4318         u32 icr = rd32(E1000_ICR);
4319         if (!icr)
4320                 return IRQ_NONE;  /* Not our interrupt */
4321
4322         igb_write_itr(adapter->rx_ring);
4323
4324         /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
4325          * not set, then the adapter didn't send an interrupt */
4326         if (!(icr & E1000_ICR_INT_ASSERTED))
4327                 return IRQ_NONE;
4328
4329         if(icr & E1000_ICR_DOUTSYNC) {
4330                 /* HW is reporting DMA is out of sync */
4331                 adapter->stats.doosync++;
4332         }
4333
4334         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4335                 hw->mac.get_link_status = 1;
4336                 /* guard against interrupt when we're going down */
4337                 if (!test_bit(__IGB_DOWN, &adapter->state))
4338                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
4339         }
4340
4341         napi_schedule(&adapter->rx_ring[0].napi);
4342
4343         return IRQ_HANDLED;
4344 }
4345
4346 static inline void igb_rx_irq_enable(struct igb_ring *rx_ring)
4347 {
4348         struct igb_adapter *adapter = rx_ring->adapter;
4349         struct e1000_hw *hw = &adapter->hw;
4350
4351         if (adapter->itr_setting & 3) {
4352                 if (adapter->num_rx_queues == 1)
4353                         igb_set_itr(adapter);
4354                 else
4355                         igb_update_ring_itr(rx_ring);
4356         }
4357
4358         if (!test_bit(__IGB_DOWN, &adapter->state)) {
4359                 if (adapter->msix_entries)
4360                         wr32(E1000_EIMS, rx_ring->eims_value);
4361                 else
4362                         igb_irq_enable(adapter);
4363         }
4364 }
4365
4366 /**
4367  * igb_poll - NAPI Rx polling callback
4368  * @napi: napi polling structure
4369  * @budget: count of how many packets we should handle
4370  **/
4371 static int igb_poll(struct napi_struct *napi, int budget)
4372 {
4373         struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
4374         int work_done = 0;
4375
4376 #ifdef CONFIG_IGB_DCA
4377         if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
4378                 igb_update_rx_dca(rx_ring);
4379 #endif
4380         igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
4381
4382         if (rx_ring->buddy) {
4383 #ifdef CONFIG_IGB_DCA
4384                 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
4385                         igb_update_tx_dca(rx_ring->buddy);
4386 #endif
4387                 if (!igb_clean_tx_irq(rx_ring->buddy))
4388                         work_done = budget;
4389         }
4390
4391         /* If not enough Rx work done, exit the polling mode */
4392         if (work_done < budget) {
4393                 napi_complete(napi);
4394                 igb_rx_irq_enable(rx_ring);
4395         }
4396
4397         return work_done;
4398 }
4399
4400 /**
4401  * igb_hwtstamp - utility function which checks for TX time stamp
4402  * @adapter: board private structure
4403  * @skb: packet that was just sent
4404  *
4405  * If we were asked to do hardware stamping and such a time stamp is
4406  * available, then it must have been for this skb here because we only
4407  * allow only one such packet into the queue.
4408  */
4409 static void igb_tx_hwtstamp(struct igb_adapter *adapter, struct sk_buff *skb)
4410 {
4411         union skb_shared_tx *shtx = skb_tx(skb);
4412         struct e1000_hw *hw = &adapter->hw;
4413
4414         if (unlikely(shtx->hardware)) {
4415                 u32 valid = rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID;
4416                 if (valid) {
4417                         u64 regval = rd32(E1000_TXSTMPL);
4418                         u64 ns;
4419                         struct skb_shared_hwtstamps shhwtstamps;
4420
4421                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
4422                         regval |= (u64)rd32(E1000_TXSTMPH) << 32;
4423                         ns = timecounter_cyc2time(&adapter->clock,
4424                                                   regval);
4425                         timecompare_update(&adapter->compare, ns);
4426                         shhwtstamps.hwtstamp = ns_to_ktime(ns);
4427                         shhwtstamps.syststamp =
4428                                 timecompare_transform(&adapter->compare, ns);
4429                         skb_tstamp_tx(skb, &shhwtstamps);
4430                 }
4431         }
4432 }
4433
4434 /**
4435  * igb_clean_tx_irq - Reclaim resources after transmit completes
4436  * @adapter: board private structure
4437  * returns true if ring is completely cleaned
4438  **/
4439 static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
4440 {
4441         struct igb_adapter *adapter = tx_ring->adapter;
4442         struct net_device *netdev = adapter->netdev;
4443         struct e1000_hw *hw = &adapter->hw;
4444         struct igb_buffer *buffer_info;
4445         struct sk_buff *skb;
4446         union e1000_adv_tx_desc *tx_desc, *eop_desc;
4447         unsigned int total_bytes = 0, total_packets = 0;
4448         unsigned int i, eop, count = 0;
4449         bool cleaned = false;
4450
4451         i = tx_ring->next_to_clean;
4452         eop = tx_ring->buffer_info[i].next_to_watch;
4453         eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4454
4455         while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
4456                (count < tx_ring->count)) {
4457                 for (cleaned = false; !cleaned; count++) {
4458                         tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
4459                         buffer_info = &tx_ring->buffer_info[i];
4460                         cleaned = (i == eop);
4461                         skb = buffer_info->skb;
4462
4463                         if (skb) {
4464                                 unsigned int segs, bytecount;
4465                                 /* gso_segs is currently only valid for tcp */
4466                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
4467                                 /* multiply data chunks by size of headers */
4468                                 bytecount = ((segs - 1) * skb_headlen(skb)) +
4469                                             skb->len;
4470                                 total_packets += segs;
4471                                 total_bytes += bytecount;
4472
4473                                 igb_tx_hwtstamp(adapter, skb);
4474                         }
4475
4476                         igb_unmap_and_free_tx_resource(adapter, buffer_info);
4477                         tx_desc->wb.status = 0;
4478
4479                         i++;
4480                         if (i == tx_ring->count)
4481                                 i = 0;
4482                 }
4483                 eop = tx_ring->buffer_info[i].next_to_watch;
4484                 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4485         }
4486
4487         tx_ring->next_to_clean = i;
4488
4489         if (unlikely(count &&
4490                      netif_carrier_ok(netdev) &&
4491                      igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
4492                 /* Make sure that anybody stopping the queue after this
4493                  * sees the new next_to_clean.
4494                  */
4495                 smp_mb();
4496                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
4497                     !(test_bit(__IGB_DOWN, &adapter->state))) {
4498                         netif_wake_subqueue(netdev, tx_ring->queue_index);
4499                         ++adapter->restart_queue;
4500                 }
4501         }
4502
4503         if (tx_ring->detect_tx_hung) {
4504                 /* Detect a transmit hang in hardware, this serializes the
4505                  * check with the clearing of time_stamp and movement of i */
4506                 tx_ring->detect_tx_hung = false;
4507                 if (tx_ring->buffer_info[i].time_stamp &&
4508                     time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
4509                                (adapter->tx_timeout_factor * HZ))
4510                     && !(rd32(E1000_STATUS) &
4511                          E1000_STATUS_TXOFF)) {
4512
4513                         /* detected Tx unit hang */
4514                         dev_err(&adapter->pdev->dev,
4515                                 "Detected Tx Unit Hang\n"
4516                                 "  Tx Queue             <%d>\n"
4517                                 "  TDH                  <%x>\n"
4518                                 "  TDT                  <%x>\n"
4519                                 "  next_to_use          <%x>\n"
4520                                 "  next_to_clean        <%x>\n"
4521                                 "buffer_info[next_to_clean]\n"
4522                                 "  time_stamp           <%lx>\n"
4523                                 "  next_to_watch        <%x>\n"
4524                                 "  jiffies              <%lx>\n"
4525                                 "  desc.status          <%x>\n",
4526                                 tx_ring->queue_index,
4527                                 readl(adapter->hw.hw_addr + tx_ring->head),
4528                                 readl(adapter->hw.hw_addr + tx_ring->tail),
4529                                 tx_ring->next_to_use,
4530                                 tx_ring->next_to_clean,
4531                                 tx_ring->buffer_info[i].time_stamp,
4532                                 eop,
4533                                 jiffies,
4534                                 eop_desc->wb.status);
4535                         netif_stop_subqueue(netdev, tx_ring->queue_index);
4536                 }
4537         }
4538         tx_ring->total_bytes += total_bytes;
4539         tx_ring->total_packets += total_packets;
4540         tx_ring->tx_stats.bytes += total_bytes;
4541         tx_ring->tx_stats.packets += total_packets;
4542         adapter->net_stats.tx_bytes += total_bytes;
4543         adapter->net_stats.tx_packets += total_packets;
4544         return (count < tx_ring->count);
4545 }
4546
4547 /**
4548  * igb_receive_skb - helper function to handle rx indications
4549  * @ring: pointer to receive ring receving this packet
4550  * @status: descriptor status field as written by hardware
4551  * @rx_desc: receive descriptor containing vlan and type information.
4552  * @skb: pointer to sk_buff to be indicated to stack
4553  **/
4554 static void igb_receive_skb(struct igb_ring *ring, u8 status,
4555                             union e1000_adv_rx_desc * rx_desc,
4556                             struct sk_buff *skb)
4557 {
4558         struct igb_adapter * adapter = ring->adapter;
4559         bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
4560
4561         skb_record_rx_queue(skb, ring->queue_index);
4562         if (vlan_extracted)
4563                 vlan_gro_receive(&ring->napi, adapter->vlgrp,
4564                                  le16_to_cpu(rx_desc->wb.upper.vlan),
4565                                  skb);
4566         else
4567                 napi_gro_receive(&ring->napi, skb);
4568 }
4569
4570 static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
4571                                        u32 status_err, struct sk_buff *skb)
4572 {
4573         skb->ip_summed = CHECKSUM_NONE;
4574
4575         /* Ignore Checksum bit is set or checksum is disabled through ethtool */
4576         if ((status_err & E1000_RXD_STAT_IXSM) ||
4577             (adapter->flags & IGB_FLAG_RX_CSUM_DISABLED))
4578                 return;
4579         /* TCP/UDP checksum error bit is set */
4580         if (status_err &
4581             (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
4582                 /*
4583                  * work around errata with sctp packets where the TCPE aka
4584                  * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
4585                  * packets, (aka let the stack check the crc32c)
4586                  */
4587                 if (!((adapter->hw.mac.type == e1000_82576) &&
4588                       (skb->len == 60)))
4589                         adapter->hw_csum_err++;
4590                 /* let the stack verify checksum errors */
4591                 return;
4592         }
4593         /* It must be a TCP or UDP packet with a valid checksum */
4594         if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
4595                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4596
4597         dev_dbg(&adapter->pdev->dev, "cksum success: bits %08X\n", status_err);
4598         adapter->hw_csum_good++;
4599 }
4600
4601 static inline u16 igb_get_hlen(struct igb_adapter *adapter,
4602                                union e1000_adv_rx_desc *rx_desc)
4603 {
4604         /* HW will not DMA in data larger than the given buffer, even if it
4605          * parses the (NFS, of course) header to be larger.  In that case, it
4606          * fills the header buffer and spills the rest into the page.
4607          */
4608         u16 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
4609                    E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
4610         if (hlen > adapter->rx_ps_hdr_size)
4611                 hlen = adapter->rx_ps_hdr_size;
4612         return hlen;
4613 }
4614
4615 static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
4616                                  int *work_done, int budget)
4617 {
4618         struct igb_adapter *adapter = rx_ring->adapter;
4619         struct net_device *netdev = adapter->netdev;
4620         struct e1000_hw *hw = &adapter->hw;
4621         struct pci_dev *pdev = adapter->pdev;
4622         union e1000_adv_rx_desc *rx_desc , *next_rxd;
4623         struct igb_buffer *buffer_info , *next_buffer;
4624         struct sk_buff *skb;
4625         bool cleaned = false;
4626         int cleaned_count = 0;
4627         unsigned int total_bytes = 0, total_packets = 0;
4628         unsigned int i;
4629         u32 staterr;
4630         u16 length;
4631
4632         i = rx_ring->next_to_clean;
4633         buffer_info = &rx_ring->buffer_info[i];
4634         rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4635         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4636
4637         while (staterr & E1000_RXD_STAT_DD) {
4638                 if (*work_done >= budget)
4639                         break;
4640                 (*work_done)++;
4641
4642                 skb = buffer_info->skb;
4643                 prefetch(skb->data - NET_IP_ALIGN);
4644                 buffer_info->skb = NULL;
4645
4646                 i++;
4647                 if (i == rx_ring->count)
4648                         i = 0;
4649                 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
4650                 prefetch(next_rxd);
4651                 next_buffer = &rx_ring->buffer_info[i];
4652
4653                 length = le16_to_cpu(rx_desc->wb.upper.length);
4654                 cleaned = true;
4655                 cleaned_count++;
4656
4657                 /* this is the fast path for the non-packet split case */
4658                 if (!adapter->rx_ps_hdr_size) {
4659                         pci_unmap_single(pdev, buffer_info->dma,
4660                                          adapter->rx_buffer_len,
4661                                          PCI_DMA_FROMDEVICE);
4662                         buffer_info->dma = 0;
4663                         skb_put(skb, length);
4664                         goto send_up;
4665                 }
4666
4667                 if (buffer_info->dma) {
4668                         u16 hlen = igb_get_hlen(adapter, rx_desc);
4669                         pci_unmap_single(pdev, buffer_info->dma,
4670                                          adapter->rx_ps_hdr_size,
4671                                          PCI_DMA_FROMDEVICE);
4672                         buffer_info->dma = 0;
4673                         skb_put(skb, hlen);
4674                 }
4675
4676                 if (length) {
4677                         pci_unmap_page(pdev, buffer_info->page_dma,
4678                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
4679                         buffer_info->page_dma = 0;
4680
4681                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
4682                                                 buffer_info->page,
4683                                                 buffer_info->page_offset,
4684                                                 length);
4685
4686                         if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
4687                             (page_count(buffer_info->page) != 1))
4688                                 buffer_info->page = NULL;
4689                         else
4690                                 get_page(buffer_info->page);
4691
4692                         skb->len += length;
4693                         skb->data_len += length;
4694
4695                         skb->truesize += length;
4696                 }
4697
4698                 if (!(staterr & E1000_RXD_STAT_EOP)) {
4699                         buffer_info->skb = next_buffer->skb;
4700                         buffer_info->dma = next_buffer->dma;
4701                         next_buffer->skb = skb;
4702                         next_buffer->dma = 0;
4703                         goto next_desc;
4704                 }
4705 send_up:
4706                 /*
4707                  * If this bit is set, then the RX registers contain
4708                  * the time stamp. No other packet will be time
4709                  * stamped until we read these registers, so read the
4710                  * registers to make them available again. Because
4711                  * only one packet can be time stamped at a time, we
4712                  * know that the register values must belong to this
4713                  * one here and therefore we don't need to compare
4714                  * any of the additional attributes stored for it.
4715                  *
4716                  * If nothing went wrong, then it should have a
4717                  * skb_shared_tx that we can turn into a
4718                  * skb_shared_hwtstamps.
4719                  *
4720                  * TODO: can time stamping be triggered (thus locking
4721                  * the registers) without the packet reaching this point
4722                  * here? In that case RX time stamping would get stuck.
4723                  *
4724                  * TODO: in "time stamp all packets" mode this bit is
4725                  * not set. Need a global flag for this mode and then
4726                  * always read the registers. Cannot be done without
4727                  * a race condition.
4728                  */
4729                 if (unlikely(staterr & E1000_RXD_STAT_TS)) {
4730                         u64 regval;
4731                         u64 ns;
4732                         struct skb_shared_hwtstamps *shhwtstamps =
4733                                 skb_hwtstamps(skb);
4734
4735                         WARN(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID),
4736                              "igb: no RX time stamp available for time stamped packet");
4737                         regval = rd32(E1000_RXSTMPL);
4738                         regval |= (u64)rd32(E1000_RXSTMPH) << 32;
4739                         ns = timecounter_cyc2time(&adapter->clock, regval);
4740                         timecompare_update(&adapter->compare, ns);
4741                         memset(shhwtstamps, 0, sizeof(*shhwtstamps));
4742                         shhwtstamps->hwtstamp = ns_to_ktime(ns);
4743                         shhwtstamps->syststamp =
4744                                 timecompare_transform(&adapter->compare, ns);
4745                 }
4746
4747                 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
4748                         dev_kfree_skb_irq(skb);
4749                         goto next_desc;
4750                 }
4751
4752                 total_bytes += skb->len;
4753                 total_packets++;
4754
4755                 igb_rx_checksum_adv(adapter, staterr, skb);
4756
4757                 skb->protocol = eth_type_trans(skb, netdev);
4758
4759                 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
4760
4761 next_desc:
4762                 rx_desc->wb.upper.status_error = 0;
4763
4764                 /* return some buffers to hardware, one at a time is too slow */
4765                 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
4766                         igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
4767                         cleaned_count = 0;
4768                 }
4769
4770                 /* use prefetched values */
4771                 rx_desc = next_rxd;
4772                 buffer_info = next_buffer;
4773                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4774         }
4775
4776         rx_ring->next_to_clean = i;
4777         cleaned_count = igb_desc_unused(rx_ring);
4778
4779         if (cleaned_count)
4780                 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
4781
4782         rx_ring->total_packets += total_packets;
4783         rx_ring->total_bytes += total_bytes;
4784         rx_ring->rx_stats.packets += total_packets;
4785         rx_ring->rx_stats.bytes += total_bytes;
4786         adapter->net_stats.rx_bytes += total_bytes;
4787         adapter->net_stats.rx_packets += total_packets;
4788         return cleaned;
4789 }
4790
4791 /**
4792  * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
4793  * @adapter: address of board private structure
4794  **/
4795 static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
4796                                      int cleaned_count)
4797 {
4798         struct igb_adapter *adapter = rx_ring->adapter;
4799         struct net_device *netdev = adapter->netdev;
4800         struct pci_dev *pdev = adapter->pdev;
4801         union e1000_adv_rx_desc *rx_desc;
4802         struct igb_buffer *buffer_info;
4803         struct sk_buff *skb;
4804         unsigned int i;
4805         int bufsz;
4806
4807         i = rx_ring->next_to_use;
4808         buffer_info = &rx_ring->buffer_info[i];
4809
4810         if (adapter->rx_ps_hdr_size)
4811                 bufsz = adapter->rx_ps_hdr_size;
4812         else
4813                 bufsz = adapter->rx_buffer_len;
4814
4815         while (cleaned_count--) {
4816                 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4817
4818                 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
4819                         if (!buffer_info->page) {
4820                                 buffer_info->page = alloc_page(GFP_ATOMIC);
4821                                 if (!buffer_info->page) {
4822                                         adapter->alloc_rx_buff_failed++;
4823                                         goto no_buffers;
4824                                 }
4825                                 buffer_info->page_offset = 0;
4826                         } else {
4827                                 buffer_info->page_offset ^= PAGE_SIZE / 2;
4828                         }
4829                         buffer_info->page_dma =
4830                                 pci_map_page(pdev, buffer_info->page,
4831                                              buffer_info->page_offset,
4832                                              PAGE_SIZE / 2,
4833                                              PCI_DMA_FROMDEVICE);
4834                 }
4835
4836                 if (!buffer_info->skb) {
4837                         skb = netdev_alloc_skb(netdev, bufsz + NET_IP_ALIGN);
4838                         if (!skb) {
4839                                 adapter->alloc_rx_buff_failed++;
4840                                 goto no_buffers;
4841                         }
4842
4843                         /* Make buffer alignment 2 beyond a 16 byte boundary
4844                          * this will result in a 16 byte aligned IP header after
4845                          * the 14 byte MAC header is removed
4846                          */
4847                         skb_reserve(skb, NET_IP_ALIGN);
4848
4849                         buffer_info->skb = skb;
4850                         buffer_info->dma = pci_map_single(pdev, skb->data,
4851                                                           bufsz,
4852                                                           PCI_DMA_FROMDEVICE);
4853                 }
4854                 /* Refresh the desc even if buffer_addrs didn't change because
4855                  * each write-back erases this info. */
4856                 if (adapter->rx_ps_hdr_size) {
4857                         rx_desc->read.pkt_addr =
4858                              cpu_to_le64(buffer_info->page_dma);
4859                         rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4860                 } else {
4861                         rx_desc->read.pkt_addr =
4862                              cpu_to_le64(buffer_info->dma);
4863                         rx_desc->read.hdr_addr = 0;
4864                 }
4865
4866                 i++;
4867                 if (i == rx_ring->count)
4868                         i = 0;
4869                 buffer_info = &rx_ring->buffer_info[i];
4870         }
4871
4872 no_buffers:
4873         if (rx_ring->next_to_use != i) {
4874                 rx_ring->next_to_use = i;
4875                 if (i == 0)
4876                         i = (rx_ring->count - 1);
4877                 else
4878                         i--;
4879
4880                 /* Force memory writes to complete before letting h/w
4881                  * know there are new descriptors to fetch.  (Only
4882                  * applicable for weak-ordered memory model archs,
4883                  * such as IA-64). */
4884                 wmb();
4885                 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4886         }
4887 }
4888
4889 /**
4890  * igb_mii_ioctl -
4891  * @netdev:
4892  * @ifreq:
4893  * @cmd:
4894  **/
4895 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4896 {
4897         struct igb_adapter *adapter = netdev_priv(netdev);
4898         struct mii_ioctl_data *data = if_mii(ifr);
4899
4900         if (adapter->hw.phy.media_type != e1000_media_type_copper)
4901                 return -EOPNOTSUPP;
4902
4903         switch (cmd) {
4904         case SIOCGMIIPHY:
4905                 data->phy_id = adapter->hw.phy.addr;
4906                 break;
4907         case SIOCGMIIREG:
4908                 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4909                                      &data->val_out))
4910                         return -EIO;
4911                 break;
4912         case SIOCSMIIREG:
4913         default:
4914                 return -EOPNOTSUPP;
4915         }
4916         return 0;
4917 }
4918
4919 /**
4920  * igb_hwtstamp_ioctl - control hardware time stamping
4921  * @netdev:
4922  * @ifreq:
4923  * @cmd:
4924  *
4925  * Outgoing time stamping can be enabled and disabled. Play nice and
4926  * disable it when requested, although it shouldn't case any overhead
4927  * when no packet needs it. At most one packet in the queue may be
4928  * marked for time stamping, otherwise it would be impossible to tell
4929  * for sure to which packet the hardware time stamp belongs.
4930  *
4931  * Incoming time stamping has to be configured via the hardware
4932  * filters. Not all combinations are supported, in particular event
4933  * type has to be specified. Matching the kind of event packet is
4934  * not supported, with the exception of "all V2 events regardless of
4935  * level 2 or 4".
4936  *
4937  **/
4938 static int igb_hwtstamp_ioctl(struct net_device *netdev,
4939                               struct ifreq *ifr, int cmd)
4940 {
4941         struct igb_adapter *adapter = netdev_priv(netdev);
4942         struct e1000_hw *hw = &adapter->hw;
4943         struct hwtstamp_config config;
4944         u32 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4945         u32 tsync_rx_ctl_bit = E1000_TSYNCRXCTL_ENABLED;
4946         u32 tsync_rx_ctl_type = 0;
4947         u32 tsync_rx_cfg = 0;
4948         int is_l4 = 0;
4949         int is_l2 = 0;
4950         short port = 319; /* PTP */
4951         u32 regval;
4952
4953         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4954                 return -EFAULT;
4955
4956         /* reserved for future extensions */
4957         if (config.flags)
4958                 return -EINVAL;
4959
4960         switch (config.tx_type) {
4961         case HWTSTAMP_TX_OFF:
4962                 tsync_tx_ctl_bit = 0;
4963                 break;
4964         case HWTSTAMP_TX_ON:
4965                 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4966                 break;
4967         default:
4968                 return -ERANGE;
4969         }
4970
4971         switch (config.rx_filter) {
4972         case HWTSTAMP_FILTER_NONE:
4973                 tsync_rx_ctl_bit = 0;
4974                 break;
4975         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4976         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4977         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4978         case HWTSTAMP_FILTER_ALL:
4979                 /*
4980                  * register TSYNCRXCFG must be set, therefore it is not
4981                  * possible to time stamp both Sync and Delay_Req messages
4982                  * => fall back to time stamping all packets
4983                  */
4984                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_ALL;
4985                 config.rx_filter = HWTSTAMP_FILTER_ALL;
4986                 break;
4987         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4988                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4989                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
4990                 is_l4 = 1;
4991                 break;
4992         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4993                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4994                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
4995                 is_l4 = 1;
4996                 break;
4997         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4998         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4999                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
5000                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
5001                 is_l2 = 1;
5002                 is_l4 = 1;
5003                 config.rx_filter = HWTSTAMP_FILTER_SOME;
5004                 break;
5005         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
5006         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
5007                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
5008                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
5009                 is_l2 = 1;
5010                 is_l4 = 1;
5011                 config.rx_filter = HWTSTAMP_FILTER_SOME;
5012                 break;
5013         case HWTSTAMP_FILTER_PTP_V2_EVENT:
5014         case HWTSTAMP_FILTER_PTP_V2_SYNC:
5015         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
5016                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_EVENT_V2;
5017                 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
5018                 is_l2 = 1;
5019                 break;
5020         default:
5021                 return -ERANGE;
5022         }
5023
5024         /* enable/disable TX */
5025         regval = rd32(E1000_TSYNCTXCTL);
5026         regval = (regval & ~E1000_TSYNCTXCTL_ENABLED) | tsync_tx_ctl_bit;
5027         wr32(E1000_TSYNCTXCTL, regval);
5028
5029         /* enable/disable RX, define which PTP packets are time stamped */
5030         regval = rd32(E1000_TSYNCRXCTL);
5031         regval = (regval & ~E1000_TSYNCRXCTL_ENABLED) | tsync_rx_ctl_bit;
5032         regval = (regval & ~0xE) | tsync_rx_ctl_type;
5033         wr32(E1000_TSYNCRXCTL, regval);
5034         wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
5035
5036         /*
5037          * Ethertype Filter Queue Filter[0][15:0] = 0x88F7
5038          *                                          (Ethertype to filter on)
5039          * Ethertype Filter Queue Filter[0][26] = 0x1 (Enable filter)
5040          * Ethertype Filter Queue Filter[0][30] = 0x1 (Enable Timestamping)
5041          */
5042         wr32(E1000_ETQF0, is_l2 ? 0x440088f7 : 0);
5043
5044         /* L4 Queue Filter[0]: only filter by source and destination port */
5045         wr32(E1000_SPQF0, htons(port));
5046         wr32(E1000_IMIREXT(0), is_l4 ?
5047              ((1<<12) | (1<<19) /* bypass size and control flags */) : 0);
5048         wr32(E1000_IMIR(0), is_l4 ?
5049              (htons(port)
5050               | (0<<16) /* immediate interrupt disabled */
5051               | 0 /* (1<<17) bit cleared: do not bypass
5052                      destination port check */)
5053                 : 0);
5054         wr32(E1000_FTQF0, is_l4 ?
5055              (0x11 /* UDP */
5056               | (1<<15) /* VF not compared */
5057               | (1<<27) /* Enable Timestamping */
5058               | (7<<28) /* only source port filter enabled,
5059                            source/target address and protocol
5060                            masked */)
5061              : ((1<<15) | (15<<28) /* all mask bits set = filter not
5062                                       enabled */));
5063
5064         wrfl();
5065
5066         adapter->hwtstamp_config = config;
5067
5068         /* clear TX/RX time stamp registers, just to be sure */
5069         regval = rd32(E1000_TXSTMPH);
5070         regval = rd32(E1000_RXSTMPH);
5071
5072         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
5073                 -EFAULT : 0;
5074 }
5075
5076 /**
5077  * igb_ioctl -
5078  * @netdev:
5079  * @ifreq:
5080  * @cmd:
5081  **/
5082 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5083 {
5084         switch (cmd) {
5085         case SIOCGMIIPHY:
5086         case SIOCGMIIREG:
5087         case SIOCSMIIREG:
5088                 return igb_mii_ioctl(netdev, ifr, cmd);
5089         case SIOCSHWTSTAMP:
5090                 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
5091         default:
5092                 return -EOPNOTSUPP;
5093         }
5094 }
5095
5096 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5097 {
5098         struct igb_adapter *adapter = hw->back;
5099         u16 cap_offset;
5100
5101         cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5102         if (!cap_offset)
5103                 return -E1000_ERR_CONFIG;
5104
5105         pci_read_config_word(adapter->pdev, cap_offset + reg, value);
5106
5107         return 0;
5108 }
5109
5110 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5111 {
5112         struct igb_adapter *adapter = hw->back;
5113         u16 cap_offset;
5114
5115         cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5116         if (!cap_offset)
5117                 return -E1000_ERR_CONFIG;
5118
5119         pci_write_config_word(adapter->pdev, cap_offset + reg, *value);
5120
5121         return 0;
5122 }
5123
5124 static void igb_vlan_rx_register(struct net_device *netdev,
5125                                  struct vlan_group *grp)
5126 {
5127         struct igb_adapter *adapter = netdev_priv(netdev);
5128         struct e1000_hw *hw = &adapter->hw;
5129         u32 ctrl, rctl;
5130
5131         igb_irq_disable(adapter);
5132         adapter->vlgrp = grp;
5133
5134         if (grp) {
5135                 /* enable VLAN tag insert/strip */
5136                 ctrl = rd32(E1000_CTRL);
5137                 ctrl |= E1000_CTRL_VME;
5138                 wr32(E1000_CTRL, ctrl);
5139
5140                 /* enable VLAN receive filtering */
5141                 rctl = rd32(E1000_RCTL);
5142                 rctl &= ~E1000_RCTL_CFIEN;
5143                 wr32(E1000_RCTL, rctl);
5144                 igb_update_mng_vlan(adapter);
5145         } else {
5146                 /* disable VLAN tag insert/strip */
5147                 ctrl = rd32(E1000_CTRL);
5148                 ctrl &= ~E1000_CTRL_VME;
5149                 wr32(E1000_CTRL, ctrl);
5150
5151                 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
5152                         igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
5153                         adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
5154                 }
5155         }
5156
5157         igb_rlpml_set(adapter);
5158
5159         if (!test_bit(__IGB_DOWN, &adapter->state))
5160                 igb_irq_enable(adapter);
5161 }
5162
5163 static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
5164 {
5165         struct igb_adapter *adapter = netdev_priv(netdev);
5166         struct e1000_hw *hw = &adapter->hw;
5167         int pf_id = adapter->vfs_allocated_count;
5168
5169         if ((hw->mng_cookie.status &
5170              E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5171             (vid == adapter->mng_vlan_id))
5172                 return;
5173
5174         /* add vid to vlvf if sr-iov is enabled,
5175          * if that fails add directly to filter table */
5176         if (igb_vlvf_set(adapter, vid, true, pf_id))
5177                 igb_vfta_set(hw, vid, true);
5178
5179 }
5180
5181 static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
5182 {
5183         struct igb_adapter *adapter = netdev_priv(netdev);
5184         struct e1000_hw *hw = &adapter->hw;
5185         int pf_id = adapter->vfs_allocated_count;
5186
5187         igb_irq_disable(adapter);
5188         vlan_group_set_device(adapter->vlgrp, vid, NULL);
5189
5190         if (!test_bit(__IGB_DOWN, &adapter->state))
5191                 igb_irq_enable(adapter);
5192
5193         if ((adapter->hw.mng_cookie.status &
5194              E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5195             (vid == adapter->mng_vlan_id)) {
5196                 /* release control to f/w */
5197                 igb_release_hw_control(adapter);
5198                 return;
5199         }
5200
5201         /* remove vid from vlvf if sr-iov is enabled,
5202          * if not in vlvf remove from vfta */
5203         if (igb_vlvf_set(adapter, vid, false, pf_id))
5204                 igb_vfta_set(hw, vid, false);
5205 }
5206
5207 static void igb_restore_vlan(struct igb_adapter *adapter)
5208 {
5209         igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
5210
5211         if (adapter->vlgrp) {
5212                 u16 vid;
5213                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
5214                         if (!vlan_group_get_device(adapter->vlgrp, vid))
5215                                 continue;
5216                         igb_vlan_rx_add_vid(adapter->netdev, vid);
5217                 }
5218         }
5219 }
5220
5221 int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
5222 {
5223         struct e1000_mac_info *mac = &adapter->hw.mac;
5224
5225         mac->autoneg = 0;
5226
5227         switch (spddplx) {
5228         case SPEED_10 + DUPLEX_HALF:
5229                 mac->forced_speed_duplex = ADVERTISE_10_HALF;
5230                 break;
5231         case SPEED_10 + DUPLEX_FULL:
5232                 mac->forced_speed_duplex = ADVERTISE_10_FULL;
5233                 break;
5234         case SPEED_100 + DUPLEX_HALF:
5235                 mac->forced_speed_duplex = ADVERTISE_100_HALF;
5236                 break;
5237         case SPEED_100 + DUPLEX_FULL:
5238                 mac->forced_speed_duplex = ADVERTISE_100_FULL;
5239                 break;
5240         case SPEED_1000 + DUPLEX_FULL:
5241                 mac->autoneg = 1;
5242                 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
5243                 break;
5244         case SPEED_1000 + DUPLEX_HALF: /* not supported */
5245         default:
5246                 dev_err(&adapter->pdev->dev,
5247                         "Unsupported Speed/Duplex configuration\n");
5248                 return -EINVAL;
5249         }
5250         return 0;
5251 }
5252
5253 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake)
5254 {
5255         struct net_device *netdev = pci_get_drvdata(pdev);
5256         struct igb_adapter *adapter = netdev_priv(netdev);
5257         struct e1000_hw *hw = &adapter->hw;
5258         u32 ctrl, rctl, status;
5259         u32 wufc = adapter->wol;
5260 #ifdef CONFIG_PM
5261         int retval = 0;
5262 #endif
5263
5264         netif_device_detach(netdev);
5265
5266         if (netif_running(netdev))
5267                 igb_close(netdev);
5268
5269         igb_reset_interrupt_capability(adapter);
5270
5271         igb_free_queues(adapter);
5272
5273 #ifdef CONFIG_PM
5274         retval = pci_save_state(pdev);
5275         if (retval)
5276                 return retval;
5277 #endif
5278
5279         status = rd32(E1000_STATUS);
5280         if (status & E1000_STATUS_LU)
5281                 wufc &= ~E1000_WUFC_LNKC;
5282
5283         if (wufc) {
5284                 igb_setup_rctl(adapter);
5285                 igb_set_rx_mode(netdev);
5286
5287                 /* turn on all-multi mode if wake on multicast is enabled */
5288                 if (wufc & E1000_WUFC_MC) {
5289                         rctl = rd32(E1000_RCTL);
5290                         rctl |= E1000_RCTL_MPE;
5291                         wr32(E1000_RCTL, rctl);
5292                 }
5293
5294                 ctrl = rd32(E1000_CTRL);
5295                 /* advertise wake from D3Cold */
5296                 #define E1000_CTRL_ADVD3WUC 0x00100000
5297                 /* phy power management enable */
5298                 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5299                 ctrl |= E1000_CTRL_ADVD3WUC;
5300                 wr32(E1000_CTRL, ctrl);
5301
5302                 /* Allow time for pending master requests to run */
5303                 igb_disable_pcie_master(&adapter->hw);
5304
5305                 wr32(E1000_WUC, E1000_WUC_PME_EN);
5306                 wr32(E1000_WUFC, wufc);
5307         } else {
5308                 wr32(E1000_WUC, 0);
5309                 wr32(E1000_WUFC, 0);
5310         }
5311
5312         *enable_wake = wufc || adapter->en_mng_pt;
5313         if (!*enable_wake)
5314                 igb_shutdown_serdes_link_82575(hw);
5315
5316         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
5317          * would have already happened in close and is redundant. */
5318         igb_release_hw_control(adapter);
5319
5320         pci_disable_device(pdev);
5321
5322         return 0;
5323 }
5324
5325 #ifdef CONFIG_PM
5326 static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
5327 {
5328         int retval;
5329         bool wake;
5330
5331         retval = __igb_shutdown(pdev, &wake);
5332         if (retval)
5333                 return retval;
5334
5335         if (wake) {
5336                 pci_prepare_to_sleep(pdev);
5337         } else {
5338                 pci_wake_from_d3(pdev, false);
5339                 pci_set_power_state(pdev, PCI_D3hot);
5340         }
5341
5342         return 0;
5343 }
5344
5345 static int igb_resume(struct pci_dev *pdev)
5346 {
5347         struct net_device *netdev = pci_get_drvdata(pdev);
5348         struct igb_adapter *adapter = netdev_priv(netdev);
5349         struct e1000_hw *hw = &adapter->hw;
5350         u32 err;
5351
5352         pci_set_power_state(pdev, PCI_D0);
5353         pci_restore_state(pdev);
5354
5355         err = pci_enable_device_mem(pdev);
5356         if (err) {
5357                 dev_err(&pdev->dev,
5358                         "igb: Cannot enable PCI device from suspend\n");
5359                 return err;
5360         }
5361         pci_set_master(pdev);
5362
5363         pci_enable_wake(pdev, PCI_D3hot, 0);
5364         pci_enable_wake(pdev, PCI_D3cold, 0);
5365
5366         igb_set_interrupt_capability(adapter);
5367
5368         if (igb_alloc_queues(adapter)) {
5369                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
5370                 return -ENOMEM;
5371         }
5372
5373         /* e1000_power_up_phy(adapter); */
5374
5375         igb_reset(adapter);
5376
5377         /* let the f/w know that the h/w is now under the control of the
5378          * driver. */
5379         igb_get_hw_control(adapter);
5380
5381         wr32(E1000_WUS, ~0);
5382
5383         if (netif_running(netdev)) {
5384                 err = igb_open(netdev);
5385                 if (err)
5386                         return err;
5387         }
5388
5389         netif_device_attach(netdev);
5390
5391         return 0;
5392 }
5393 #endif
5394
5395 static void igb_shutdown(struct pci_dev *pdev)
5396 {
5397         bool wake;
5398
5399         __igb_shutdown(pdev, &wake);
5400
5401         if (system_state == SYSTEM_POWER_OFF) {
5402                 pci_wake_from_d3(pdev, wake);
5403                 pci_set_power_state(pdev, PCI_D3hot);
5404         }
5405 }
5406
5407 #ifdef CONFIG_NET_POLL_CONTROLLER
5408 /*
5409  * Polling 'interrupt' - used by things like netconsole to send skbs
5410  * without having to re-enable interrupts. It's not called while
5411  * the interrupt routine is executing.
5412  */
5413 static void igb_netpoll(struct net_device *netdev)
5414 {
5415         struct igb_adapter *adapter = netdev_priv(netdev);
5416         struct e1000_hw *hw = &adapter->hw;
5417         int i;
5418
5419         if (!adapter->msix_entries) {
5420                 igb_irq_disable(adapter);
5421                 napi_schedule(&adapter->rx_ring[0].napi);
5422                 return;
5423         }
5424
5425         for (i = 0; i < adapter->num_tx_queues; i++) {
5426                 struct igb_ring *tx_ring = &adapter->tx_ring[i];
5427                 wr32(E1000_EIMC, tx_ring->eims_value);
5428                 igb_clean_tx_irq(tx_ring);
5429                 wr32(E1000_EIMS, tx_ring->eims_value);
5430         }
5431
5432         for (i = 0; i < adapter->num_rx_queues; i++) {
5433                 struct igb_ring *rx_ring = &adapter->rx_ring[i];
5434                 wr32(E1000_EIMC, rx_ring->eims_value);
5435                 napi_schedule(&rx_ring->napi);
5436         }
5437 }
5438 #endif /* CONFIG_NET_POLL_CONTROLLER */
5439
5440 /**
5441  * igb_io_error_detected - called when PCI error is detected
5442  * @pdev: Pointer to PCI device
5443  * @state: The current pci connection state
5444  *
5445  * This function is called after a PCI bus error affecting
5446  * this device has been detected.
5447  */
5448 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
5449                                               pci_channel_state_t state)
5450 {
5451         struct net_device *netdev = pci_get_drvdata(pdev);
5452         struct igb_adapter *adapter = netdev_priv(netdev);
5453
5454         netif_device_detach(netdev);
5455
5456         if (state == pci_channel_io_perm_failure)
5457                 return PCI_ERS_RESULT_DISCONNECT;
5458
5459         if (netif_running(netdev))
5460                 igb_down(adapter);
5461         pci_disable_device(pdev);
5462
5463         /* Request a slot slot reset. */
5464         return PCI_ERS_RESULT_NEED_RESET;
5465 }
5466
5467 /**
5468  * igb_io_slot_reset - called after the pci bus has been reset.
5469  * @pdev: Pointer to PCI device
5470  *
5471  * Restart the card from scratch, as if from a cold-boot. Implementation
5472  * resembles the first-half of the igb_resume routine.
5473  */
5474 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
5475 {
5476         struct net_device *netdev = pci_get_drvdata(pdev);
5477         struct igb_adapter *adapter = netdev_priv(netdev);
5478         struct e1000_hw *hw = &adapter->hw;
5479         pci_ers_result_t result;
5480         int err;
5481
5482         if (pci_enable_device_mem(pdev)) {
5483                 dev_err(&pdev->dev,
5484                         "Cannot re-enable PCI device after reset.\n");
5485                 result = PCI_ERS_RESULT_DISCONNECT;
5486         } else {
5487                 pci_set_master(pdev);
5488                 pci_restore_state(pdev);
5489
5490                 pci_enable_wake(pdev, PCI_D3hot, 0);
5491                 pci_enable_wake(pdev, PCI_D3cold, 0);
5492
5493                 igb_reset(adapter);
5494                 wr32(E1000_WUS, ~0);
5495                 result = PCI_ERS_RESULT_RECOVERED;
5496         }
5497
5498         err = pci_cleanup_aer_uncorrect_error_status(pdev);
5499         if (err) {
5500                 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
5501                         "failed 0x%0x\n", err);
5502                 /* non-fatal, continue */
5503         }
5504
5505         return result;
5506 }
5507
5508 /**
5509  * igb_io_resume - called when traffic can start flowing again.
5510  * @pdev: Pointer to PCI device
5511  *
5512  * This callback is called when the error recovery driver tells us that
5513  * its OK to resume normal operation. Implementation resembles the
5514  * second-half of the igb_resume routine.
5515  */
5516 static void igb_io_resume(struct pci_dev *pdev)
5517 {
5518         struct net_device *netdev = pci_get_drvdata(pdev);
5519         struct igb_adapter *adapter = netdev_priv(netdev);
5520
5521         if (netif_running(netdev)) {
5522                 if (igb_up(adapter)) {
5523                         dev_err(&pdev->dev, "igb_up failed after reset\n");
5524                         return;
5525                 }
5526         }
5527
5528         netif_device_attach(netdev);
5529
5530         /* let the f/w know that the h/w is now under the control of the
5531          * driver. */
5532         igb_get_hw_control(adapter);
5533 }
5534
5535 static int igb_set_vf_mac(struct igb_adapter *adapter,
5536                           int vf, unsigned char *mac_addr)
5537 {
5538         struct e1000_hw *hw = &adapter->hw;
5539         /* VF MAC addresses start at end of receive addresses and moves
5540          * torwards the first, as a result a collision should not be possible */
5541         int rar_entry = hw->mac.rar_entry_count - (vf + 1);
5542
5543         memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
5544
5545         igb_rar_set(hw, mac_addr, rar_entry);
5546         igb_set_rah_pool(hw, vf, rar_entry);
5547
5548         return 0;
5549 }
5550
5551 static void igb_vmm_control(struct igb_adapter *adapter)
5552 {
5553         struct e1000_hw *hw = &adapter->hw;
5554         u32 reg_data;
5555
5556         if (!adapter->vfs_allocated_count)
5557                 return;
5558
5559         /* VF's need PF reset indication before they
5560          * can send/receive mail */
5561         reg_data = rd32(E1000_CTRL_EXT);
5562         reg_data |= E1000_CTRL_EXT_PFRSTD;
5563         wr32(E1000_CTRL_EXT, reg_data);
5564
5565         igb_vmdq_set_loopback_pf(hw, true);
5566         igb_vmdq_set_replication_pf(hw, true);
5567 }
5568
5569 /* igb_main.c */