drivers/net/igb/igb_main.c

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/module.h>
  29 #include <linux/types.h>
  30 #include <linux/init.h>
  31 #include <linux/vmalloc.h>
  32 #include <linux/pagemap.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/ipv6.h>
  35 #include <net/checksum.h>
  36 #include <net/ip6_checksum.h>
  37 #include <linux/net_tstamp.h>
  38 #include <linux/mii.h>
  39 #include <linux/ethtool.h>
  40 #include <linux/if_vlan.h>
  41 #include <linux/pci.h>
  42 #include <linux/pci-aspm.h>
  43 #include <linux/delay.h>
  44 #include <linux/interrupt.h>
  45 #include <linux/if_ether.h>
  46 #include <linux/aer.h>
  47 #ifdef CONFIG_IGB_DCA
  48 #include <linux/dca.h>
  49 #endif
  50 #include "igb.h"
  51
  52 #define DRV_VERSION "1.3.16-k2"
  53 char igb_driver_name[] = "igb";
  54 char igb_driver_version[] = DRV_VERSION;
  55 static const char igb_driver_string[] =
  56                                 "Intel(R) Gigabit Ethernet Network Driver";
  57 static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
  58
  59 static const struct e1000_info *igb_info_tbl[] = {
  60         [board_82575] = &e1000_82575_info,
  61 };
  62
  63 static struct pci_device_id igb_pci_tbl[] = {
  64         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
  65         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
  66         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
  67         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
  68         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
  69         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
  70         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
  71         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
  72         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
  73         /* required last entry */
  74         {0, }
  75 };
  76
  77 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
  78
  79 void igb_reset(struct igb_adapter *);
  80 static int igb_setup_all_tx_resources(struct igb_adapter *);
  81 static int igb_setup_all_rx_resources(struct igb_adapter *);
  82 static void igb_free_all_tx_resources(struct igb_adapter *);
  83 static void igb_free_all_rx_resources(struct igb_adapter *);
  84 void igb_update_stats(struct igb_adapter *);
  85 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
  86 static void __devexit igb_remove(struct pci_dev *pdev);
  87 static int igb_sw_init(struct igb_adapter *);
  88 static int igb_open(struct net_device *);
  89 static int igb_close(struct net_device *);
  90 static void igb_configure_tx(struct igb_adapter *);
  91 static void igb_configure_rx(struct igb_adapter *);
  92 static void igb_setup_rctl(struct igb_adapter *);
  93 static void igb_clean_all_tx_rings(struct igb_adapter *);
  94 static void igb_clean_all_rx_rings(struct igb_adapter *);
  95 static void igb_clean_tx_ring(struct igb_ring *);
  96 static void igb_clean_rx_ring(struct igb_ring *);
  97 static void igb_set_multi(struct net_device *);
  98 static void igb_update_phy_info(unsigned long);
  99 static void igb_watchdog(unsigned long);
 100 static void igb_watchdog_task(struct work_struct *);
 101 static netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *,
 102                                            struct net_device *,
 103                                            struct igb_ring *);
 104 static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb,
 105                                       struct net_device *);
 106 static struct net_device_stats *igb_get_stats(struct net_device *);
 107 static int igb_change_mtu(struct net_device *, int);
 108 static int igb_set_mac(struct net_device *, void *);
 109 static irqreturn_t igb_intr(int irq, void *);
 110 static irqreturn_t igb_intr_msi(int irq, void *);
 111 static irqreturn_t igb_msix_other(int irq, void *);
 112 static irqreturn_t igb_msix_rx(int irq, void *);
 113 static irqreturn_t igb_msix_tx(int irq, void *);
 114 #ifdef CONFIG_IGB_DCA
 115 static void igb_update_rx_dca(struct igb_ring *);
 116 static void igb_update_tx_dca(struct igb_ring *);
 117 static void igb_setup_dca(struct igb_adapter *);
 118 #endif /* CONFIG_IGB_DCA */
 119 static bool igb_clean_tx_irq(struct igb_ring *);
 120 static int igb_poll(struct napi_struct *, int);
 121 static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
 122 static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
 123 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
 124 static void igb_tx_timeout(struct net_device *);
 125 static void igb_reset_task(struct work_struct *);
 126 static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
 127 static void igb_vlan_rx_add_vid(struct net_device *, u16);
 128 static void igb_vlan_rx_kill_vid(struct net_device *, u16);
 129 static void igb_restore_vlan(struct igb_adapter *);
 130 static void igb_ping_all_vfs(struct igb_adapter *);
 131 static void igb_msg_task(struct igb_adapter *);
 132 static int igb_rcv_msg_from_vf(struct igb_adapter *, u32);
 133 static inline void igb_set_rah_pool(struct e1000_hw *, int , int);
 134 static void igb_vmm_control(struct igb_adapter *);
 135 static int igb_set_vf_mac(struct igb_adapter *adapter, int, unsigned char *);
 136 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
 137
 138 static inline void igb_set_vmolr(struct e1000_hw *hw, int vfn)
 139 {
 140         u32 reg_data;
 141
 142         reg_data = rd32(E1000_VMOLR(vfn));
 143         reg_data |= E1000_VMOLR_BAM |    /* Accept broadcast */
 144                     E1000_VMOLR_ROPE |   /* Accept packets matched in UTA */
 145                     E1000_VMOLR_ROMPE |  /* Accept packets matched in MTA */
 146                     E1000_VMOLR_AUPE |   /* Accept untagged packets */
 147                     E1000_VMOLR_STRVLAN; /* Strip vlan tags */
 148         wr32(E1000_VMOLR(vfn), reg_data);
 149 }
 150
 151 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
 152                                  int vfn)
 153 {
 154         struct e1000_hw *hw = &adapter->hw;
 155         u32 vmolr;
 156
 157         vmolr = rd32(E1000_VMOLR(vfn));
 158         vmolr &= ~E1000_VMOLR_RLPML_MASK;
 159         vmolr |= size | E1000_VMOLR_LPE;
 160         wr32(E1000_VMOLR(vfn), vmolr);
 161
 162         return 0;
 163 }
 164
 165 static inline void igb_set_rah_pool(struct e1000_hw *hw, int pool, int entry)
 166 {
 167         u32 reg_data;
 168
 169         reg_data = rd32(E1000_RAH(entry));
 170         reg_data &= ~E1000_RAH_POOL_MASK;
 171         reg_data |= E1000_RAH_POOL_1 << pool;;
 172         wr32(E1000_RAH(entry), reg_data);
 173 }
 174
 175 #ifdef CONFIG_PM
 176 static int igb_suspend(struct pci_dev *, pm_message_t);
 177 static int igb_resume(struct pci_dev *);
 178 #endif
 179 static void igb_shutdown(struct pci_dev *);
 180 #ifdef CONFIG_IGB_DCA
 181 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
 182 static struct notifier_block dca_notifier = {
 183         .notifier_call  = igb_notify_dca,
 184         .next           = NULL,
 185         .priority       = 0
 186 };
 187 #endif
 188 #ifdef CONFIG_NET_POLL_CONTROLLER
 189 /* for netdump / net console */
 190 static void igb_netpoll(struct net_device *);
 191 #endif
 192 #ifdef CONFIG_PCI_IOV
 193 static unsigned int max_vfs = 0;
 194 module_param(max_vfs, uint, 0);
 195 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
 196                  "per physical function");
 197 #endif /* CONFIG_PCI_IOV */
 198
 199 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
 200                      pci_channel_state_t);
 201 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
 202 static void igb_io_resume(struct pci_dev *);
 203
 204 static struct pci_error_handlers igb_err_handler = {
 205         .error_detected = igb_io_error_detected,
 206         .slot_reset = igb_io_slot_reset,
 207         .resume = igb_io_resume,
 208 };
 209
 210
 211 static struct pci_driver igb_driver = {
 212         .name     = igb_driver_name,
 213         .id_table = igb_pci_tbl,
 214         .probe    = igb_probe,
 215         .remove   = __devexit_p(igb_remove),
 216 #ifdef CONFIG_PM
 217         /* Power Managment Hooks */
 218         .suspend  = igb_suspend,
 219         .resume   = igb_resume,
 220 #endif
 221         .shutdown = igb_shutdown,
 222         .err_handler = &igb_err_handler
 223 };
 224
 225 static int global_quad_port_a; /* global quad port a indication */
 226
 227 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
 228 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
 229 MODULE_LICENSE("GPL");
 230 MODULE_VERSION(DRV_VERSION);
 231
 232 /**
 233  * Scale the NIC clock cycle by a large factor so that
 234  * relatively small clock corrections can be added or
 235  * substracted at each clock tick. The drawbacks of a
 236  * large factor are a) that the clock register overflows
 237  * more quickly (not such a big deal) and b) that the
 238  * increment per tick has to fit into 24 bits.
 239  *
 240  * Note that
 241  *   TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS *
 242  *             IGB_TSYNC_SCALE
 243  *   TIMINCA += TIMINCA * adjustment [ppm] / 1e9
 244  *
 245  * The base scale factor is intentionally a power of two
 246  * so that the division in %struct timecounter can be done with
 247  * a shift.
 248  */
 249 #define IGB_TSYNC_SHIFT (19)
 250 #define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT)
 251
 252 /**
 253  * The duration of one clock cycle of the NIC.
 254  *
 255  * @todo This hard-coded value is part of the specification and might change
 256  * in future hardware revisions. Add revision check.
 257  */
 258 #define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16
 259
 260 #if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24)
 261 # error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA
 262 #endif
 263
 264 /**
 265  * igb_read_clock - read raw cycle counter (to be used by time counter)
 266  */
 267 static cycle_t igb_read_clock(const struct cyclecounter *tc)
 268 {
 269         struct igb_adapter *adapter =
 270                 container_of(tc, struct igb_adapter, cycles);
 271         struct e1000_hw *hw = &adapter->hw;
 272         u64 stamp;
 273
 274         stamp =  rd32(E1000_SYSTIML);
 275         stamp |= (u64)rd32(E1000_SYSTIMH) << 32ULL;
 276
 277         return stamp;
 278 }
 279
 280 #ifdef DEBUG
 281 /**
 282  * igb_get_hw_dev_name - return device name string
 283  * used by hardware layer to print debugging information
 284  **/
 285 char *igb_get_hw_dev_name(struct e1000_hw *hw)
 286 {
 287         struct igb_adapter *adapter = hw->back;
 288         return adapter->netdev->name;
 289 }
 290
 291 /**
 292  * igb_get_time_str - format current NIC and system time as string
 293  */
 294 static char *igb_get_time_str(struct igb_adapter *adapter,
 295                               char buffer[160])
 296 {
 297         cycle_t hw = adapter->cycles.read(&adapter->cycles);
 298         struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock));
 299         struct timespec sys;
 300         struct timespec delta;
 301         getnstimeofday(&sys);
 302
 303         delta = timespec_sub(nic, sys);
 304
 305         sprintf(buffer,
 306                 "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
 307                 hw,
 308                 (long)nic.tv_sec, nic.tv_nsec,
 309                 (long)sys.tv_sec, sys.tv_nsec,
 310                 (long)delta.tv_sec, delta.tv_nsec);
 311
 312         return buffer;
 313 }
 314 #endif
 315
 316 /**
 317  * igb_desc_unused - calculate if we have unused descriptors
 318  **/
 319 static int igb_desc_unused(struct igb_ring *ring)
 320 {
 321         if (ring->next_to_clean > ring->next_to_use)
 322                 return ring->next_to_clean - ring->next_to_use - 1;
 323
 324         return ring->count + ring->next_to_clean - ring->next_to_use - 1;
 325 }
 326
 327 /**
 328  * igb_init_module - Driver Registration Routine
 329  *
 330  * igb_init_module is the first routine called when the driver is
 331  * loaded. All it does is register with the PCI subsystem.
 332  **/
 333 static int __init igb_init_module(void)
 334 {
 335         int ret;
 336         printk(KERN_INFO "%s - version %s\n",
 337                igb_driver_string, igb_driver_version);
 338
 339         printk(KERN_INFO "%s\n", igb_copyright);
 340
 341         global_quad_port_a = 0;
 342
 343 #ifdef CONFIG_IGB_DCA
 344         dca_register_notify(&dca_notifier);
 345 #endif
 346
 347         ret = pci_register_driver(&igb_driver);
 348         return ret;
 349 }
 350
 351 module_init(igb_init_module);
 352
 353 /**
 354  * igb_exit_module - Driver Exit Cleanup Routine
 355  *
 356  * igb_exit_module is called just before the driver is removed
 357  * from memory.
 358  **/
 359 static void __exit igb_exit_module(void)
 360 {
 361 #ifdef CONFIG_IGB_DCA
 362         dca_unregister_notify(&dca_notifier);
 363 #endif
 364         pci_unregister_driver(&igb_driver);
 365 }
 366
 367 module_exit(igb_exit_module);
 368
 369 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
 370 /**
 371  * igb_cache_ring_register - Descriptor ring to register mapping
 372  * @adapter: board private structure to initialize
 373  *
 374  * Once we know the feature-set enabled for the device, we'll cache
 375  * the register offset the descriptor ring is assigned to.
 376  **/
 377 static void igb_cache_ring_register(struct igb_adapter *adapter)
 378 {
 379         int i;
 380         unsigned int rbase_offset = adapter->vfs_allocated_count;
 381
 382         switch (adapter->hw.mac.type) {
 383         case e1000_82576:
 384                 /* The queues are allocated for virtualization such that VF 0
 385                  * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
 386                  * In order to avoid collision we start at the first free queue
 387                  * and continue consuming queues in the same sequence
 388                  */
 389                 for (i = 0; i < adapter->num_rx_queues; i++)
 390                         adapter->rx_ring[i].reg_idx = rbase_offset +
 391                                                       Q_IDX_82576(i);
 392                 for (i = 0; i < adapter->num_tx_queues; i++)
 393                         adapter->tx_ring[i].reg_idx = rbase_offset +
 394                                                       Q_IDX_82576(i);
 395                 break;
 396         case e1000_82575:
 397         default:
 398                 for (i = 0; i < adapter->num_rx_queues; i++)
 399                         adapter->rx_ring[i].reg_idx = i;
 400                 for (i = 0; i < adapter->num_tx_queues; i++)
 401                         adapter->tx_ring[i].reg_idx = i;
 402                 break;
 403         }
 404 }
 405
 406 /**
 407  * igb_alloc_queues - Allocate memory for all rings
 408  * @adapter: board private structure to initialize
 409  *
 410  * We allocate one ring per queue at run-time since we don't know the
 411  * number of queues at compile-time.
 412  **/
 413 static int igb_alloc_queues(struct igb_adapter *adapter)
 414 {
 415         int i;
 416
 417         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
 418                                    sizeof(struct igb_ring), GFP_KERNEL);
 419         if (!adapter->tx_ring)
 420                 return -ENOMEM;
 421
 422         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
 423                                    sizeof(struct igb_ring), GFP_KERNEL);
 424         if (!adapter->rx_ring) {
 425                 kfree(adapter->tx_ring);
 426                 return -ENOMEM;
 427         }
 428
 429         adapter->rx_ring->buddy = adapter->tx_ring;
 430
 431         for (i = 0; i < adapter->num_tx_queues; i++) {
 432                 struct igb_ring *ring = &(adapter->tx_ring[i]);
 433                 ring->count = adapter->tx_ring_count;
 434                 ring->adapter = adapter;
 435                 ring->queue_index = i;
 436         }
 437         for (i = 0; i < adapter->num_rx_queues; i++) {
 438                 struct igb_ring *ring = &(adapter->rx_ring[i]);
 439                 ring->count = adapter->rx_ring_count;
 440                 ring->adapter = adapter;
 441                 ring->queue_index = i;
 442                 ring->itr_register = E1000_ITR;
 443
 444                 /* set a default napi handler for each rx_ring */
 445                 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
 446         }
 447
 448         igb_cache_ring_register(adapter);
 449         return 0;
 450 }
 451
 452 static void igb_free_queues(struct igb_adapter *adapter)
 453 {
 454         int i;
 455
 456         for (i = 0; i < adapter->num_rx_queues; i++)
 457                 netif_napi_del(&adapter->rx_ring[i].napi);
 458
 459         adapter->num_rx_queues = 0;
 460         adapter->num_tx_queues = 0;
 461
 462         kfree(adapter->tx_ring);
 463         kfree(adapter->rx_ring);
 464 }
 465
 466 #define IGB_N0_QUEUE -1
 467 static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
 468                               int tx_queue, int msix_vector)
 469 {
 470         u32 msixbm = 0;
 471         struct e1000_hw *hw = &adapter->hw;
 472         u32 ivar, index;
 473
 474         switch (hw->mac.type) {
 475         case e1000_82575:
 476                 /* The 82575 assigns vectors using a bitmask, which matches the
 477                    bitmask for the EICR/EIMS/EIMC registers.  To assign one
 478                    or more queues to a vector, we write the appropriate bits
 479                    into the MSIXBM register for that vector. */
 480                 if (rx_queue > IGB_N0_QUEUE) {
 481                         msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
 482                         adapter->rx_ring[rx_queue].eims_value = msixbm;
 483                 }
 484                 if (tx_queue > IGB_N0_QUEUE) {
 485                         msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
 486                         adapter->tx_ring[tx_queue].eims_value =
 487                                   E1000_EICR_TX_QUEUE0 << tx_queue;
 488                 }
 489                 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
 490                 break;
 491         case e1000_82576:
 492                 /* 82576 uses a table-based method for assigning vectors.
 493                    Each queue has a single entry in the table to which we write
 494                    a vector number along with a "valid" bit.  Sadly, the layout
 495                    of the table is somewhat counterintuitive. */
 496                 if (rx_queue > IGB_N0_QUEUE) {
 497                         index = (rx_queue >> 1) + adapter->vfs_allocated_count;
 498                         ivar = array_rd32(E1000_IVAR0, index);
 499                         if (rx_queue & 0x1) {
 500                                 /* vector goes into third byte of register */
 501                                 ivar = ivar & 0xFF00FFFF;
 502                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
 503                         } else {
 504                                 /* vector goes into low byte of register */
 505                                 ivar = ivar & 0xFFFFFF00;
 506                                 ivar |= msix_vector | E1000_IVAR_VALID;
 507                         }
 508                         adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
 509                         array_wr32(E1000_IVAR0, index, ivar);
 510                 }
 511                 if (tx_queue > IGB_N0_QUEUE) {
 512                         index = (tx_queue >> 1) + adapter->vfs_allocated_count;
 513                         ivar = array_rd32(E1000_IVAR0, index);
 514                         if (tx_queue & 0x1) {
 515                                 /* vector goes into high byte of register */
 516                                 ivar = ivar & 0x00FFFFFF;
 517                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
 518                         } else {
 519                                 /* vector goes into second byte of register */
 520                                 ivar = ivar & 0xFFFF00FF;
 521                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
 522                         }
 523                         adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
 524                         array_wr32(E1000_IVAR0, index, ivar);
 525                 }
 526                 break;
 527         default:
 528                 BUG();
 529                 break;
 530         }
 531 }
 532
 533 /**
 534  * igb_configure_msix - Configure MSI-X hardware
 535  *
 536  * igb_configure_msix sets up the hardware to properly
 537  * generate MSI-X interrupts.
 538  **/
 539 static void igb_configure_msix(struct igb_adapter *adapter)
 540 {
 541         u32 tmp;
 542         int i, vector = 0;
 543         struct e1000_hw *hw = &adapter->hw;
 544
 545         adapter->eims_enable_mask = 0;
 546         if (hw->mac.type == e1000_82576)
 547                 /* Turn on MSI-X capability first, or our settings
 548                  * won't stick.  And it will take days to debug. */
 549                 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
 550                                    E1000_GPIE_PBA | E1000_GPIE_EIAME |
 551                                    E1000_GPIE_NSICR);
 552
 553         for (i = 0; i < adapter->num_tx_queues; i++) {
 554                 struct igb_ring *tx_ring = &adapter->tx_ring[i];
 555                 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
 556                 adapter->eims_enable_mask |= tx_ring->eims_value;
 557                 if (tx_ring->itr_val)
 558                         writel(tx_ring->itr_val,
 559                                hw->hw_addr + tx_ring->itr_register);
 560                 else
 561                         writel(1, hw->hw_addr + tx_ring->itr_register);
 562         }
 563
 564         for (i = 0; i < adapter->num_rx_queues; i++) {
 565                 struct igb_ring *rx_ring = &adapter->rx_ring[i];
 566                 rx_ring->buddy = NULL;
 567                 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
 568                 adapter->eims_enable_mask |= rx_ring->eims_value;
 569                 if (rx_ring->itr_val)
 570                         writel(rx_ring->itr_val,
 571                                hw->hw_addr + rx_ring->itr_register);
 572                 else
 573                         writel(1, hw->hw_addr + rx_ring->itr_register);
 574         }
 575
 576
 577         /* set vector for other causes, i.e. link changes */
 578         switch (hw->mac.type) {
 579         case e1000_82575:
 580                 array_wr32(E1000_MSIXBM(0), vector++,
 581                                       E1000_EIMS_OTHER);
 582
 583                 tmp = rd32(E1000_CTRL_EXT);
 584                 /* enable MSI-X PBA support*/
 585                 tmp |= E1000_CTRL_EXT_PBA_CLR;
 586
 587                 /* Auto-Mask interrupts upon ICR read. */
 588                 tmp |= E1000_CTRL_EXT_EIAME;
 589                 tmp |= E1000_CTRL_EXT_IRCA;
 590
 591                 wr32(E1000_CTRL_EXT, tmp);
 592                 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
 593                 adapter->eims_other = E1000_EIMS_OTHER;
 594
 595                 break;
 596
 597         case e1000_82576:
 598                 tmp = (vector++ | E1000_IVAR_VALID) << 8;
 599                 wr32(E1000_IVAR_MISC, tmp);
 600
 601                 adapter->eims_enable_mask = (1 << (vector)) - 1;
 602                 adapter->eims_other = 1 << (vector - 1);
 603                 break;
 604         default:
 605                 /* do nothing, since nothing else supports MSI-X */
 606                 break;
 607         } /* switch (hw->mac.type) */
 608         wrfl();
 609 }
 610
 611 /**
 612  * igb_request_msix - Initialize MSI-X interrupts
 613  *
 614  * igb_request_msix allocates MSI-X vectors and requests interrupts from the
 615  * kernel.
 616  **/
 617 static int igb_request_msix(struct igb_adapter *adapter)
 618 {
 619         struct net_device *netdev = adapter->netdev;
 620         int i, err = 0, vector = 0;
 621
 622         vector = 0;
 623
 624         for (i = 0; i < adapter->num_tx_queues; i++) {
 625                 struct igb_ring *ring = &(adapter->tx_ring[i]);
 626                 sprintf(ring->name, "%s-tx-%d", netdev->name, i);
 627                 err = request_irq(adapter->msix_entries[vector].vector,
 628                                   &igb_msix_tx, 0, ring->name,
 629                                   &(adapter->tx_ring[i]));
 630                 if (err)
 631                         goto out;
 632                 ring->itr_register = E1000_EITR(0) + (vector << 2);
 633                 ring->itr_val = 976; /* ~4000 ints/sec */
 634                 vector++;
 635         }
 636         for (i = 0; i < adapter->num_rx_queues; i++) {
 637                 struct igb_ring *ring = &(adapter->rx_ring[i]);
 638                 if (strlen(netdev->name) < (IFNAMSIZ - 5))
 639                         sprintf(ring->name, "%s-rx-%d", netdev->name, i);
 640                 else
 641                         memcpy(ring->name, netdev->name, IFNAMSIZ);
 642                 err = request_irq(adapter->msix_entries[vector].vector,
 643                                   &igb_msix_rx, 0, ring->name,
 644                                   &(adapter->rx_ring[i]));
 645                 if (err)
 646                         goto out;
 647                 ring->itr_register = E1000_EITR(0) + (vector << 2);
 648                 ring->itr_val = adapter->itr;
 649                 vector++;
 650         }
 651
 652         err = request_irq(adapter->msix_entries[vector].vector,
 653                           &igb_msix_other, 0, netdev->name, netdev);
 654         if (err)
 655                 goto out;
 656
 657         igb_configure_msix(adapter);
 658         return 0;
 659 out:
 660         return err;
 661 }
 662
 663 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
 664 {
 665         if (adapter->msix_entries) {
 666                 pci_disable_msix(adapter->pdev);
 667                 kfree(adapter->msix_entries);
 668                 adapter->msix_entries = NULL;
 669         } else if (adapter->flags & IGB_FLAG_HAS_MSI)
 670                 pci_disable_msi(adapter->pdev);
 671         return;
 672 }
 673
 674
 675 /**
 676  * igb_set_interrupt_capability - set MSI or MSI-X if supported
 677  *
 678  * Attempt to configure interrupts using the best available
 679  * capabilities of the hardware and kernel.
 680  **/
 681 static void igb_set_interrupt_capability(struct igb_adapter *adapter)
 682 {
 683         int err;
 684         int numvecs, i;
 685
 686         /* Number of supported queues. */
 687         /* Having more queues than CPUs doesn't make sense. */
 688         adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
 689         adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
 690
 691         numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
 692         adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
 693                                         GFP_KERNEL);
 694         if (!adapter->msix_entries)
 695                 goto msi_only;
 696
 697         for (i = 0; i < numvecs; i++)
 698                 adapter->msix_entries[i].entry = i;
 699
 700         err = pci_enable_msix(adapter->pdev,
 701                               adapter->msix_entries,
 702                               numvecs);
 703         if (err == 0)
 704                 goto out;
 705
 706         igb_reset_interrupt_capability(adapter);
 707
 708         /* If we can't do MSI-X, try MSI */
 709 msi_only:
 710 #ifdef CONFIG_PCI_IOV
 711         /* disable SR-IOV for non MSI-X configurations */
 712         if (adapter->vf_data) {
 713                 struct e1000_hw *hw = &adapter->hw;
 714                 /* disable iov and allow time for transactions to clear */
 715                 pci_disable_sriov(adapter->pdev);
 716                 msleep(500);
 717
 718                 kfree(adapter->vf_data);
 719                 adapter->vf_data = NULL;
 720                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
 721                 msleep(100);
 722                 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
 723         }
 724 #endif
 725         adapter->num_rx_queues = 1;
 726         adapter->num_tx_queues = 1;
 727         if (!pci_enable_msi(adapter->pdev))
 728                 adapter->flags |= IGB_FLAG_HAS_MSI;
 729 out:
 730         /* Notify the stack of the (possibly) reduced Tx Queue count. */
 731         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
 732         return;
 733 }
 734
 735 /**
 736  * igb_request_irq - initialize interrupts
 737  *
 738  * Attempts to configure interrupts using the best available
 739  * capabilities of the hardware and kernel.
 740  **/
 741 static int igb_request_irq(struct igb_adapter *adapter)
 742 {
 743         struct net_device *netdev = adapter->netdev;
 744         struct e1000_hw *hw = &adapter->hw;
 745         int err = 0;
 746
 747         if (adapter->msix_entries) {
 748                 err = igb_request_msix(adapter);
 749                 if (!err)
 750                         goto request_done;
 751                 /* fall back to MSI */
 752                 igb_reset_interrupt_capability(adapter);
 753                 if (!pci_enable_msi(adapter->pdev))
 754                         adapter->flags |= IGB_FLAG_HAS_MSI;
 755                 igb_free_all_tx_resources(adapter);
 756                 igb_free_all_rx_resources(adapter);
 757                 adapter->num_rx_queues = 1;
 758                 igb_alloc_queues(adapter);
 759         } else {
 760                 switch (hw->mac.type) {
 761                 case e1000_82575:
 762                         wr32(E1000_MSIXBM(0),
 763                              (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
 764                         break;
 765                 case e1000_82576:
 766                         wr32(E1000_IVAR0, E1000_IVAR_VALID);
 767                         break;
 768                 default:
 769                         break;
 770                 }
 771         }
 772
 773         if (adapter->flags & IGB_FLAG_HAS_MSI) {
 774                 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
 775                                   netdev->name, netdev);
 776                 if (!err)
 777                         goto request_done;
 778                 /* fall back to legacy interrupts */
 779                 igb_reset_interrupt_capability(adapter);
 780                 adapter->flags &= ~IGB_FLAG_HAS_MSI;
 781         }
 782
 783         err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
 784                           netdev->name, netdev);
 785
 786         if (err)
 787                 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
 788                         err);
 789
 790 request_done:
 791         return err;
 792 }
 793
 794 static void igb_free_irq(struct igb_adapter *adapter)
 795 {
 796         struct net_device *netdev = adapter->netdev;
 797
 798         if (adapter->msix_entries) {
 799                 int vector = 0, i;
 800
 801                 for (i = 0; i < adapter->num_tx_queues; i++)
 802                         free_irq(adapter->msix_entries[vector++].vector,
 803                                 &(adapter->tx_ring[i]));
 804                 for (i = 0; i < adapter->num_rx_queues; i++)
 805                         free_irq(adapter->msix_entries[vector++].vector,
 806                                 &(adapter->rx_ring[i]));
 807
 808                 free_irq(adapter->msix_entries[vector++].vector, netdev);
 809                 return;
 810         }
 811
 812         free_irq(adapter->pdev->irq, netdev);
 813 }
 814
 815 /**
 816  * igb_irq_disable - Mask off interrupt generation on the NIC
 817  * @adapter: board private structure
 818  **/
 819 static void igb_irq_disable(struct igb_adapter *adapter)
 820 {
 821         struct e1000_hw *hw = &adapter->hw;
 822
 823         if (adapter->msix_entries) {
 824                 wr32(E1000_EIAM, 0);
 825                 wr32(E1000_EIMC, ~0);
 826                 wr32(E1000_EIAC, 0);
 827         }
 828
 829         wr32(E1000_IAM, 0);
 830         wr32(E1000_IMC, ~0);
 831         wrfl();
 832         synchronize_irq(adapter->pdev->irq);
 833 }
 834
 835 /**
 836  * igb_irq_enable - Enable default interrupt generation settings
 837  * @adapter: board private structure
 838  **/
 839 static void igb_irq_enable(struct igb_adapter *adapter)
 840 {
 841         struct e1000_hw *hw = &adapter->hw;
 842
 843         if (adapter->msix_entries) {
 844                 wr32(E1000_EIAC, adapter->eims_enable_mask);
 845                 wr32(E1000_EIAM, adapter->eims_enable_mask);
 846                 wr32(E1000_EIMS, adapter->eims_enable_mask);
 847                 if (adapter->vfs_allocated_count)
 848                         wr32(E1000_MBVFIMR, 0xFF);
 849                 wr32(E1000_IMS, (E1000_IMS_LSC | E1000_IMS_VMMB |
 850                                  E1000_IMS_DOUTSYNC));
 851         } else {
 852                 wr32(E1000_IMS, IMS_ENABLE_MASK);
 853                 wr32(E1000_IAM, IMS_ENABLE_MASK);
 854         }
 855 }
 856
 857 static void igb_update_mng_vlan(struct igb_adapter *adapter)
 858 {
 859         struct net_device *netdev = adapter->netdev;
 860         u16 vid = adapter->hw.mng_cookie.vlan_id;
 861         u16 old_vid = adapter->mng_vlan_id;
 862         if (adapter->vlgrp) {
 863                 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
 864                         if (adapter->hw.mng_cookie.status &
 865                                 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
 866                                 igb_vlan_rx_add_vid(netdev, vid);
 867                                 adapter->mng_vlan_id = vid;
 868                         } else
 869                                 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
 870
 871                         if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
 872                                         (vid != old_vid) &&
 873                             !vlan_group_get_device(adapter->vlgrp, old_vid))
 874                                 igb_vlan_rx_kill_vid(netdev, old_vid);
 875                 } else
 876                         adapter->mng_vlan_id = vid;
 877         }
 878 }
 879
 880 /**
 881  * igb_release_hw_control - release control of the h/w to f/w
 882  * @adapter: address of board private structure
 883  *
 884  * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
 885  * For ASF and Pass Through versions of f/w this means that the
 886  * driver is no longer loaded.
 887  *
 888  **/
 889 static void igb_release_hw_control(struct igb_adapter *adapter)
 890 {
 891         struct e1000_hw *hw = &adapter->hw;
 892         u32 ctrl_ext;
 893
 894         /* Let firmware take over control of h/w */
 895         ctrl_ext = rd32(E1000_CTRL_EXT);
 896         wr32(E1000_CTRL_EXT,
 897                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
 898 }
 899
 900
 901 /**
 902  * igb_get_hw_control - get control of the h/w from f/w
 903  * @adapter: address of board private structure
 904  *
 905  * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
 906  * For ASF and Pass Through versions of f/w this means that
 907  * the driver is loaded.
 908  *
 909  **/
 910 static void igb_get_hw_control(struct igb_adapter *adapter)
 911 {
 912         struct e1000_hw *hw = &adapter->hw;
 913         u32 ctrl_ext;
 914
 915         /* Let firmware know the driver has taken over */
 916         ctrl_ext = rd32(E1000_CTRL_EXT);
 917         wr32(E1000_CTRL_EXT,
 918                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
 919 }
 920
 921 /**
 922  * igb_configure - configure the hardware for RX and TX
 923  * @adapter: private board structure
 924  **/
 925 static void igb_configure(struct igb_adapter *adapter)
 926 {
 927         struct net_device *netdev = adapter->netdev;
 928         int i;
 929
 930         igb_get_hw_control(adapter);
 931         igb_set_multi(netdev);
 932
 933         igb_restore_vlan(adapter);
 934
 935         igb_configure_tx(adapter);
 936         igb_setup_rctl(adapter);
 937         igb_configure_rx(adapter);
 938
 939         igb_rx_fifo_flush_82575(&adapter->hw);
 940
 941         /* call igb_desc_unused which always leaves
 942          * at least 1 descriptor unused to make sure
 943          * next_to_use != next_to_clean */
 944         for (i = 0; i < adapter->num_rx_queues; i++) {
 945                 struct igb_ring *ring = &adapter->rx_ring[i];
 946                 igb_alloc_rx_buffers_adv(ring, igb_desc_unused(ring));
 947         }
 948
 949
 950         adapter->tx_queue_len = netdev->tx_queue_len;
 951 }
 952
 953
 954 /**
 955  * igb_up - Open the interface and prepare it to handle traffic
 956  * @adapter: board private structure
 957  **/
 958
 959 int igb_up(struct igb_adapter *adapter)
 960 {
 961         struct e1000_hw *hw = &adapter->hw;
 962         int i;
 963
 964         /* hardware has been reset, we need to reload some things */
 965         igb_configure(adapter);
 966
 967         clear_bit(__IGB_DOWN, &adapter->state);
 968
 969         for (i = 0; i < adapter->num_rx_queues; i++)
 970                 napi_enable(&adapter->rx_ring[i].napi);
 971         if (adapter->msix_entries)
 972                 igb_configure_msix(adapter);
 973
 974         igb_vmm_control(adapter);
 975         igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
 976         igb_set_vmolr(hw, adapter->vfs_allocated_count);
 977
 978         /* Clear any pending interrupts. */
 979         rd32(E1000_ICR);
 980         igb_irq_enable(adapter);
 981
 982         netif_tx_start_all_queues(adapter->netdev);
 983
 984         /* Fire a link change interrupt to start the watchdog. */
 985         wr32(E1000_ICS, E1000_ICS_LSC);
 986         return 0;
 987 }
 988
 989 void igb_down(struct igb_adapter *adapter)
 990 {
 991         struct e1000_hw *hw = &adapter->hw;
 992         struct net_device *netdev = adapter->netdev;
 993         u32 tctl, rctl;
 994         int i;
 995
 996         /* signal that we're down so the interrupt handler does not
 997          * reschedule our watchdog timer */
 998         set_bit(__IGB_DOWN, &adapter->state);
 999
1000         /* disable receives in the hardware */
1001         rctl = rd32(E1000_RCTL);
1002         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1003         /* flush and sleep below */
1004
1005         netif_tx_stop_all_queues(netdev);
1006
1007         /* disable transmits in the hardware */
1008         tctl = rd32(E1000_TCTL);
1009         tctl &= ~E1000_TCTL_EN;
1010         wr32(E1000_TCTL, tctl);
1011         /* flush both disables and wait for them to finish */
1012         wrfl();
1013         msleep(10);
1014
1015         for (i = 0; i < adapter->num_rx_queues; i++)
1016                 napi_disable(&adapter->rx_ring[i].napi);
1017
1018         igb_irq_disable(adapter);
1019
1020         del_timer_sync(&adapter->watchdog_timer);
1021         del_timer_sync(&adapter->phy_info_timer);
1022
1023         netdev->tx_queue_len = adapter->tx_queue_len;
1024         netif_carrier_off(netdev);
1025
1026         /* record the stats before reset*/
1027         igb_update_stats(adapter);
1028
1029         adapter->link_speed = 0;
1030         adapter->link_duplex = 0;
1031
1032         if (!pci_channel_offline(adapter->pdev))
1033                 igb_reset(adapter);
1034         igb_clean_all_tx_rings(adapter);
1035         igb_clean_all_rx_rings(adapter);
1036 #ifdef CONFIG_IGB_DCA
1037
1038         /* since we reset the hardware DCA settings were cleared */
1039         igb_setup_dca(adapter);
1040 #endif
1041 }
1042
1043 void igb_reinit_locked(struct igb_adapter *adapter)
1044 {
1045         WARN_ON(in_interrupt());
1046         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1047                 msleep(1);
1048         igb_down(adapter);
1049         igb_up(adapter);
1050         clear_bit(__IGB_RESETTING, &adapter->state);
1051 }
1052
1053 void igb_reset(struct igb_adapter *adapter)
1054 {
1055         struct e1000_hw *hw = &adapter->hw;
1056         struct e1000_mac_info *mac = &hw->mac;
1057         struct e1000_fc_info *fc = &hw->fc;
1058         u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1059         u16 hwm;
1060
1061         /* Repartition Pba for greater than 9k mtu
1062          * To take effect CTRL.RST is required.
1063          */
1064         switch (mac->type) {
1065         case e1000_82576:
1066                 pba = E1000_PBA_64K;
1067                 break;
1068         case e1000_82575:
1069         default:
1070                 pba = E1000_PBA_34K;
1071                 break;
1072         }
1073
1074         if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1075             (mac->type < e1000_82576)) {
1076                 /* adjust PBA for jumbo frames */
1077                 wr32(E1000_PBA, pba);
1078
1079                 /* To maintain wire speed transmits, the Tx FIFO should be
1080                  * large enough to accommodate two full transmit packets,
1081                  * rounded up to the next 1KB and expressed in KB.  Likewise,
1082                  * the Rx FIFO should be large enough to accommodate at least
1083                  * one full receive packet and is similarly rounded up and
1084                  * expressed in KB. */
1085                 pba = rd32(E1000_PBA);
1086                 /* upper 16 bits has Tx packet buffer allocation size in KB */
1087                 tx_space = pba >> 16;
1088                 /* lower 16 bits has Rx packet buffer allocation size in KB */
1089                 pba &= 0xffff;
1090                 /* the tx fifo also stores 16 bytes of information about the tx
1091                  * but don't include ethernet FCS because hardware appends it */
1092                 min_tx_space = (adapter->max_frame_size +
1093                                 sizeof(union e1000_adv_tx_desc) -
1094                                 ETH_FCS_LEN) * 2;
1095                 min_tx_space = ALIGN(min_tx_space, 1024);
1096                 min_tx_space >>= 10;
1097                 /* software strips receive CRC, so leave room for it */
1098                 min_rx_space = adapter->max_frame_size;
1099                 min_rx_space = ALIGN(min_rx_space, 1024);
1100                 min_rx_space >>= 10;
1101
1102                 /* If current Tx allocation is less than the min Tx FIFO size,
1103                  * and the min Tx FIFO size is less than the current Rx FIFO
1104                  * allocation, take space away from current Rx allocation */
1105                 if (tx_space < min_tx_space &&
1106                     ((min_tx_space - tx_space) < pba)) {
1107                         pba = pba - (min_tx_space - tx_space);
1108
1109                         /* if short on rx space, rx wins and must trump tx
1110                          * adjustment */
1111                         if (pba < min_rx_space)
1112                                 pba = min_rx_space;
1113                 }
1114                 wr32(E1000_PBA, pba);
1115         }
1116
1117         /* flow control settings */
1118         /* The high water mark must be low enough to fit one full frame
1119          * (or the size used for early receive) above it in the Rx FIFO.
1120          * Set it to the lower of:
1121          * - 90% of the Rx FIFO size, or
1122          * - the full Rx FIFO size minus one full frame */
1123         hwm = min(((pba << 10) * 9 / 10),
1124                         ((pba << 10) - 2 * adapter->max_frame_size));
1125
1126         if (mac->type < e1000_82576) {
1127                 fc->high_water = hwm & 0xFFF8;  /* 8-byte granularity */
1128                 fc->low_water = fc->high_water - 8;
1129         } else {
1130                 fc->high_water = hwm & 0xFFF0;  /* 16-byte granularity */
1131                 fc->low_water = fc->high_water - 16;
1132         }
1133         fc->pause_time = 0xFFFF;
1134         fc->send_xon = 1;
1135         fc->current_mode = fc->requested_mode;
1136
1137         /* disable receive for all VFs and wait one second */
1138         if (adapter->vfs_allocated_count) {
1139                 int i;
1140                 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1141                         adapter->vf_data[i].clear_to_send = false;
1142
1143                 /* ping all the active vfs to let them know we are going down */
1144                         igb_ping_all_vfs(adapter);
1145
1146                 /* disable transmits and receives */
1147                 wr32(E1000_VFRE, 0);
1148                 wr32(E1000_VFTE, 0);
1149         }
1150
1151         /* Allow time for pending master requests to run */
1152         adapter->hw.mac.ops.reset_hw(&adapter->hw);
1153         wr32(E1000_WUC, 0);
1154
1155         if (adapter->hw.mac.ops.init_hw(&adapter->hw))
1156                 dev_err(&adapter->pdev->dev, "Hardware Error\n");
1157
1158         igb_update_mng_vlan(adapter);
1159
1160         /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1161         wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1162
1163         igb_reset_adaptive(&adapter->hw);
1164         igb_get_phy_info(&adapter->hw);
1165 }
1166
1167 static const struct net_device_ops igb_netdev_ops = {
1168         .ndo_open               = igb_open,
1169         .ndo_stop               = igb_close,
1170         .ndo_start_xmit         = igb_xmit_frame_adv,
1171         .ndo_get_stats          = igb_get_stats,
1172         .ndo_set_multicast_list = igb_set_multi,
1173         .ndo_set_mac_address    = igb_set_mac,
1174         .ndo_change_mtu         = igb_change_mtu,
1175         .ndo_do_ioctl           = igb_ioctl,
1176         .ndo_tx_timeout         = igb_tx_timeout,
1177         .ndo_validate_addr      = eth_validate_addr,
1178         .ndo_vlan_rx_register   = igb_vlan_rx_register,
1179         .ndo_vlan_rx_add_vid    = igb_vlan_rx_add_vid,
1180         .ndo_vlan_rx_kill_vid   = igb_vlan_rx_kill_vid,
1181 #ifdef CONFIG_NET_POLL_CONTROLLER
1182         .ndo_poll_controller    = igb_netpoll,
1183 #endif
1184 };
1185
1186 /**
1187  * igb_probe - Device Initialization Routine
1188  * @pdev: PCI device information struct
1189  * @ent: entry in igb_pci_tbl
1190  *
1191  * Returns 0 on success, negative on failure
1192  *
1193  * igb_probe initializes an adapter identified by a pci_dev structure.
1194  * The OS initialization, configuring of the adapter private structure,
1195  * and a hardware reset occur.
1196  **/
1197 static int __devinit igb_probe(struct pci_dev *pdev,
1198                                const struct pci_device_id *ent)
1199 {
1200         struct net_device *netdev;
1201         struct igb_adapter *adapter;
1202         struct e1000_hw *hw;
1203         const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1204         unsigned long mmio_start, mmio_len;
1205         int err, pci_using_dac;
1206         u16 eeprom_data = 0;
1207         u16 eeprom_apme_mask = IGB_EEPROM_APME;
1208         u32 part_num;
1209
1210         err = pci_enable_device_mem(pdev);
1211         if (err)
1212                 return err;
1213
1214         pci_using_dac = 0;
1215         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1216         if (!err) {
1217                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1218                 if (!err)
1219                         pci_using_dac = 1;
1220         } else {
1221                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1222                 if (err) {
1223                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1224                         if (err) {
1225                                 dev_err(&pdev->dev, "No usable DMA "
1226                                         "configuration, aborting\n");
1227                                 goto err_dma;
1228                         }
1229                 }
1230         }
1231
1232         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1233                                            IORESOURCE_MEM),
1234                                            igb_driver_name);
1235         if (err)
1236                 goto err_pci_reg;
1237
1238         err = pci_enable_pcie_error_reporting(pdev);
1239         if (err) {
1240                 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
1241                         "0x%x\n", err);
1242                 /* non-fatal, continue */
1243         }
1244
1245         pci_set_master(pdev);
1246         pci_save_state(pdev);
1247
1248         err = -ENOMEM;
1249         netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1250                                    IGB_ABS_MAX_TX_QUEUES);
1251         if (!netdev)
1252                 goto err_alloc_etherdev;
1253
1254         SET_NETDEV_DEV(netdev, &pdev->dev);
1255
1256         pci_set_drvdata(pdev, netdev);
1257         adapter = netdev_priv(netdev);
1258         adapter->netdev = netdev;
1259         adapter->pdev = pdev;
1260         hw = &adapter->hw;
1261         hw->back = adapter;
1262         adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1263
1264         mmio_start = pci_resource_start(pdev, 0);
1265         mmio_len = pci_resource_len(pdev, 0);
1266
1267         err = -EIO;
1268         hw->hw_addr = ioremap(mmio_start, mmio_len);
1269         if (!hw->hw_addr)
1270                 goto err_ioremap;
1271
1272         netdev->netdev_ops = &igb_netdev_ops;
1273         igb_set_ethtool_ops(netdev);
1274         netdev->watchdog_timeo = 5 * HZ;
1275
1276         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1277
1278         netdev->mem_start = mmio_start;
1279         netdev->mem_end = mmio_start + mmio_len;
1280
1281         /* PCI config space info */
1282         hw->vendor_id = pdev->vendor;
1283         hw->device_id = pdev->device;
1284         hw->revision_id = pdev->revision;
1285         hw->subsystem_vendor_id = pdev->subsystem_vendor;
1286         hw->subsystem_device_id = pdev->subsystem_device;
1287
1288         /* setup the private structure */
1289         hw->back = adapter;
1290         /* Copy the default MAC, PHY and NVM function pointers */
1291         memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1292         memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1293         memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1294         /* Initialize skew-specific constants */
1295         err = ei->get_invariants(hw);
1296         if (err)
1297                 goto err_sw_init;
1298
1299 #ifdef CONFIG_PCI_IOV
1300         /* since iov functionality isn't critical to base device function we
1301          * can accept failure.  If it fails we don't allow iov to be enabled */
1302         if (hw->mac.type == e1000_82576) {
1303                 /* 82576 supports a maximum of 7 VFs in addition to the PF */
1304                 unsigned int num_vfs = (max_vfs > 7) ? 7 : max_vfs;
1305                 int i;
1306                 unsigned char mac_addr[ETH_ALEN];
1307
1308                 if (num_vfs) {
1309                         adapter->vf_data = kcalloc(num_vfs,
1310                                                 sizeof(struct vf_data_storage),
1311                                                 GFP_KERNEL);
1312                         if (!adapter->vf_data) {
1313                                 dev_err(&pdev->dev,
1314                                         "Could not allocate VF private data - "
1315                                         "IOV enable failed\n");
1316                         } else {
1317                                 err = pci_enable_sriov(pdev, num_vfs);
1318                                 if (!err) {
1319                                         adapter->vfs_allocated_count = num_vfs;
1320                                         dev_info(&pdev->dev,
1321                                                  "%d vfs allocated\n",
1322                                                  num_vfs);
1323                                         for (i = 0;
1324                                              i < adapter->vfs_allocated_count;
1325                                              i++) {
1326                                                 random_ether_addr(mac_addr);
1327                                                 igb_set_vf_mac(adapter, i,
1328                                                                mac_addr);
1329                                         }
1330                                 } else {
1331                                         kfree(adapter->vf_data);
1332                                         adapter->vf_data = NULL;
1333                                 }
1334                         }
1335                 }
1336         }
1337
1338 #endif
1339         /* setup the private structure */
1340         err = igb_sw_init(adapter);
1341         if (err)
1342                 goto err_sw_init;
1343
1344         igb_get_bus_info_pcie(hw);
1345
1346         /* set flags */
1347         switch (hw->mac.type) {
1348         case e1000_82575:
1349                 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1350                 break;
1351         case e1000_82576:
1352         default:
1353                 break;
1354         }
1355
1356         hw->phy.autoneg_wait_to_complete = false;
1357         hw->mac.adaptive_ifs = true;
1358
1359         /* Copper options */
1360         if (hw->phy.media_type == e1000_media_type_copper) {
1361                 hw->phy.mdix = AUTO_ALL_MODES;
1362                 hw->phy.disable_polarity_correction = false;
1363                 hw->phy.ms_type = e1000_ms_hw_default;
1364         }
1365
1366         if (igb_check_reset_block(hw))
1367                 dev_info(&pdev->dev,
1368                         "PHY reset is blocked due to SOL/IDER session.\n");
1369
1370         netdev->features = NETIF_F_SG |
1371                            NETIF_F_IP_CSUM |
1372                            NETIF_F_HW_VLAN_TX |
1373                            NETIF_F_HW_VLAN_RX |
1374                            NETIF_F_HW_VLAN_FILTER;
1375
1376         netdev->features |= NETIF_F_IPV6_CSUM;
1377         netdev->features |= NETIF_F_TSO;
1378         netdev->features |= NETIF_F_TSO6;
1379
1380         netdev->features |= NETIF_F_GRO;
1381
1382         netdev->vlan_features |= NETIF_F_TSO;
1383         netdev->vlan_features |= NETIF_F_TSO6;
1384         netdev->vlan_features |= NETIF_F_IP_CSUM;
1385         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
1386         netdev->vlan_features |= NETIF_F_SG;
1387
1388         if (pci_using_dac)
1389                 netdev->features |= NETIF_F_HIGHDMA;
1390
1391         if (adapter->hw.mac.type == e1000_82576)
1392                 netdev->features |= NETIF_F_SCTP_CSUM;
1393
1394         adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1395
1396         /* before reading the NVM, reset the controller to put the device in a
1397          * known good starting state */
1398         hw->mac.ops.reset_hw(hw);
1399
1400         /* make sure the NVM is good */
1401         if (igb_validate_nvm_checksum(hw) < 0) {
1402                 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1403                 err = -EIO;
1404                 goto err_eeprom;
1405         }
1406
1407         /* copy the MAC address out of the NVM */
1408         if (hw->mac.ops.read_mac_addr(hw))
1409                 dev_err(&pdev->dev, "NVM Read Error\n");
1410
1411         memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1412         memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1413
1414         if (!is_valid_ether_addr(netdev->perm_addr)) {
1415                 dev_err(&pdev->dev, "Invalid MAC Address\n");
1416                 err = -EIO;
1417                 goto err_eeprom;
1418         }
1419
1420         setup_timer(&adapter->watchdog_timer, &igb_watchdog,
1421                     (unsigned long) adapter);
1422         setup_timer(&adapter->phy_info_timer, &igb_update_phy_info,
1423                     (unsigned long) adapter);
1424
1425         INIT_WORK(&adapter->reset_task, igb_reset_task);
1426         INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1427
1428         /* Initialize link properties that are user-changeable */
1429         adapter->fc_autoneg = true;
1430         hw->mac.autoneg = true;
1431         hw->phy.autoneg_advertised = 0x2f;
1432
1433         hw->fc.requested_mode = e1000_fc_default;
1434         hw->fc.current_mode = e1000_fc_default;
1435
1436         adapter->itr_setting = IGB_DEFAULT_ITR;
1437         adapter->itr = IGB_START_ITR;
1438
1439         igb_validate_mdi_setting(hw);
1440
1441         /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1442          * enable the ACPI Magic Packet filter
1443          */
1444
1445         if (hw->bus.func == 0)
1446                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
1447         else if (hw->bus.func == 1)
1448                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
1449
1450         if (eeprom_data & eeprom_apme_mask)
1451                 adapter->eeprom_wol |= E1000_WUFC_MAG;
1452
1453         /* now that we have the eeprom settings, apply the special cases where
1454          * the eeprom may be wrong or the board simply won't support wake on
1455          * lan on a particular port */
1456         switch (pdev->device) {
1457         case E1000_DEV_ID_82575GB_QUAD_COPPER:
1458                 adapter->eeprom_wol = 0;
1459                 break;
1460         case E1000_DEV_ID_82575EB_FIBER_SERDES:
1461         case E1000_DEV_ID_82576_FIBER:
1462         case E1000_DEV_ID_82576_SERDES:
1463                 /* Wake events only supported on port A for dual fiber
1464                  * regardless of eeprom setting */
1465                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1466                         adapter->eeprom_wol = 0;
1467                 break;
1468         case E1000_DEV_ID_82576_QUAD_COPPER:
1469                 /* if quad port adapter, disable WoL on all but port A */
1470                 if (global_quad_port_a != 0)
1471                         adapter->eeprom_wol = 0;
1472                 else
1473                         adapter->flags |= IGB_FLAG_QUAD_PORT_A;
1474                 /* Reset for multiple quad port adapters */
1475                 if (++global_quad_port_a == 4)
1476                         global_quad_port_a = 0;
1477                 break;
1478         }
1479
1480         /* initialize the wol settings based on the eeprom settings */
1481         adapter->wol = adapter->eeprom_wol;
1482         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1483
1484         /* reset the hardware with the new settings */
1485         igb_reset(adapter);
1486
1487         /* let the f/w know that the h/w is now under the control of the
1488          * driver. */
1489         igb_get_hw_control(adapter);
1490
1491         strcpy(netdev->name, "eth%d");
1492         err = register_netdev(netdev);
1493         if (err)
1494                 goto err_register;
1495
1496         /* carrier off reporting is important to ethtool even BEFORE open */
1497         netif_carrier_off(netdev);
1498
1499 #ifdef CONFIG_IGB_DCA
1500         if (dca_add_requester(&pdev->dev) == 0) {
1501                 adapter->flags |= IGB_FLAG_DCA_ENABLED;
1502                 dev_info(&pdev->dev, "DCA enabled\n");
1503                 igb_setup_dca(adapter);
1504         }
1505 #endif
1506
1507         /*
1508          * Initialize hardware timer: we keep it running just in case
1509          * that some program needs it later on.
1510          */
1511         memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1512         adapter->cycles.read = igb_read_clock;
1513         adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1514         adapter->cycles.mult = 1;
1515         adapter->cycles.shift = IGB_TSYNC_SHIFT;
1516         wr32(E1000_TIMINCA,
1517              (1<<24) |
1518              IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * IGB_TSYNC_SCALE);
1519 #if 0
1520         /*
1521          * Avoid rollover while we initialize by resetting the time counter.
1522          */
1523         wr32(E1000_SYSTIML, 0x00000000);
1524         wr32(E1000_SYSTIMH, 0x00000000);
1525 #else
1526         /*
1527          * Set registers so that rollover occurs soon to test this.
1528          */
1529         wr32(E1000_SYSTIML, 0x00000000);
1530         wr32(E1000_SYSTIMH, 0xFF800000);
1531 #endif
1532         wrfl();
1533         timecounter_init(&adapter->clock,
1534                          &adapter->cycles,
1535                          ktime_to_ns(ktime_get_real()));
1536
1537         /*
1538          * Synchronize our NIC clock against system wall clock. NIC
1539          * time stamp reading requires ~3us per sample, each sample
1540          * was pretty stable even under load => only require 10
1541          * samples for each offset comparison.
1542          */
1543         memset(&adapter->compare, 0, sizeof(adapter->compare));
1544         adapter->compare.source = &adapter->clock;
1545         adapter->compare.target = ktime_get_real;
1546         adapter->compare.num_samples = 10;
1547         timecompare_update(&adapter->compare, 0);
1548
1549 #ifdef DEBUG
1550         {
1551                 char buffer[160];
1552                 printk(KERN_DEBUG
1553                         "igb: %s: hw %p initialized timer\n",
1554                         igb_get_time_str(adapter, buffer),
1555                         &adapter->hw);
1556         }
1557 #endif
1558
1559         dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1560         /* print bus type/speed/width info */
1561         dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
1562                  netdev->name,
1563                  ((hw->bus.speed == e1000_bus_speed_2500)
1564                   ? "2.5Gb/s" : "unknown"),
1565                  ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
1566                   (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
1567                   (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
1568                    "unknown"),
1569                  netdev->dev_addr);
1570
1571         igb_read_part_num(hw, &part_num);
1572         dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1573                 (part_num >> 8), (part_num & 0xff));
1574
1575         dev_info(&pdev->dev,
1576                 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1577                 adapter->msix_entries ? "MSI-X" :
1578                 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
1579                 adapter->num_rx_queues, adapter->num_tx_queues);
1580
1581         return 0;
1582
1583 err_register:
1584         igb_release_hw_control(adapter);
1585 err_eeprom:
1586         if (!igb_check_reset_block(hw))
1587                 igb_reset_phy(hw);
1588
1589         if (hw->flash_address)
1590                 iounmap(hw->flash_address);
1591
1592         igb_free_queues(adapter);
1593 err_sw_init:
1594         iounmap(hw->hw_addr);
1595 err_ioremap:
1596         free_netdev(netdev);
1597 err_alloc_etherdev:
1598         pci_release_selected_regions(pdev, pci_select_bars(pdev,
1599                                      IORESOURCE_MEM));
1600 err_pci_reg:
1601 err_dma:
1602         pci_disable_device(pdev);
1603         return err;
1604 }
1605
1606 /**
1607  * igb_remove - Device Removal Routine
1608  * @pdev: PCI device information struct
1609  *
1610  * igb_remove is called by the PCI subsystem to alert the driver
1611  * that it should release a PCI device.  The could be caused by a
1612  * Hot-Plug event, or because the driver is going to be removed from
1613  * memory.
1614  **/
1615 static void __devexit igb_remove(struct pci_dev *pdev)
1616 {
1617         struct net_device *netdev = pci_get_drvdata(pdev);
1618         struct igb_adapter *adapter = netdev_priv(netdev);
1619         struct e1000_hw *hw = &adapter->hw;
1620         int err;
1621
1622         /* flush_scheduled work may reschedule our watchdog task, so
1623          * explicitly disable watchdog tasks from being rescheduled  */
1624         set_bit(__IGB_DOWN, &adapter->state);
1625         del_timer_sync(&adapter->watchdog_timer);
1626         del_timer_sync(&adapter->phy_info_timer);
1627
1628         flush_scheduled_work();
1629
1630 #ifdef CONFIG_IGB_DCA
1631         if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
1632                 dev_info(&pdev->dev, "DCA disabled\n");
1633                 dca_remove_requester(&pdev->dev);
1634                 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
1635                 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
1636         }
1637 #endif
1638
1639         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
1640          * would have already happened in close and is redundant. */
1641         igb_release_hw_control(adapter);
1642
1643         unregister_netdev(netdev);
1644
1645         if (!igb_check_reset_block(&adapter->hw))
1646                 igb_reset_phy(&adapter->hw);
1647
1648         igb_reset_interrupt_capability(adapter);
1649
1650         igb_free_queues(adapter);
1651
1652 #ifdef CONFIG_PCI_IOV
1653         /* reclaim resources allocated to VFs */
1654         if (adapter->vf_data) {
1655                 /* disable iov and allow time for transactions to clear */
1656                 pci_disable_sriov(pdev);
1657                 msleep(500);
1658
1659                 kfree(adapter->vf_data);
1660                 adapter->vf_data = NULL;
1661                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1662                 msleep(100);
1663                 dev_info(&pdev->dev, "IOV Disabled\n");
1664         }
1665 #endif
1666         iounmap(hw->hw_addr);
1667         if (hw->flash_address)
1668                 iounmap(hw->flash_address);
1669         pci_release_selected_regions(pdev, pci_select_bars(pdev,
1670                                      IORESOURCE_MEM));
1671
1672         free_netdev(netdev);
1673
1674         err = pci_disable_pcie_error_reporting(pdev);
1675         if (err)
1676                 dev_err(&pdev->dev,
1677                         "pci_disable_pcie_error_reporting failed 0x%x\n", err);
1678
1679         pci_disable_device(pdev);
1680 }
1681
1682 /**
1683  * igb_sw_init - Initialize general software structures (struct igb_adapter)
1684  * @adapter: board private structure to initialize
1685  *
1686  * igb_sw_init initializes the Adapter private data structure.
1687  * Fields are initialized based on PCI device information and
1688  * OS network device settings (MTU size).
1689  **/
1690 static int __devinit igb_sw_init(struct igb_adapter *adapter)
1691 {
1692         struct e1000_hw *hw = &adapter->hw;
1693         struct net_device *netdev = adapter->netdev;
1694         struct pci_dev *pdev = adapter->pdev;
1695
1696         pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1697
1698         adapter->tx_ring_count = IGB_DEFAULT_TXD;
1699         adapter->rx_ring_count = IGB_DEFAULT_RXD;
1700         adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1701         adapter->rx_ps_hdr_size = 0; /* disable packet split */
1702         adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1703         adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1704
1705         /* This call may decrease the number of queues depending on
1706          * interrupt mode. */
1707         igb_set_interrupt_capability(adapter);
1708
1709         if (igb_alloc_queues(adapter)) {
1710                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1711                 return -ENOMEM;
1712         }
1713
1714         /* Explicitly disable IRQ since the NIC can be in any state. */
1715         igb_irq_disable(adapter);
1716
1717         set_bit(__IGB_DOWN, &adapter->state);
1718         return 0;
1719 }
1720
1721 /**
1722  * igb_open - Called when a network interface is made active
1723  * @netdev: network interface device structure
1724  *
1725  * Returns 0 on success, negative value on failure
1726  *
1727  * The open entry point is called when a network interface is made
1728  * active by the system (IFF_UP).  At this point all resources needed
1729  * for transmit and receive operations are allocated, the interrupt
1730  * handler is registered with the OS, the watchdog timer is started,
1731  * and the stack is notified that the interface is ready.
1732  **/
1733 static int igb_open(struct net_device *netdev)
1734 {
1735         struct igb_adapter *adapter = netdev_priv(netdev);
1736         struct e1000_hw *hw = &adapter->hw;
1737         int err;
1738         int i;
1739
1740         /* disallow open during test */
1741         if (test_bit(__IGB_TESTING, &adapter->state))
1742                 return -EBUSY;
1743
1744         netif_carrier_off(netdev);
1745
1746         /* allocate transmit descriptors */
1747         err = igb_setup_all_tx_resources(adapter);
1748         if (err)
1749                 goto err_setup_tx;
1750
1751         /* allocate receive descriptors */
1752         err = igb_setup_all_rx_resources(adapter);
1753         if (err)
1754                 goto err_setup_rx;
1755
1756         /* e1000_power_up_phy(adapter); */
1757
1758         adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1759         if ((adapter->hw.mng_cookie.status &
1760              E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1761                 igb_update_mng_vlan(adapter);
1762
1763         /* before we allocate an interrupt, we must be ready to handle it.
1764          * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1765          * as soon as we call pci_request_irq, so we have to setup our
1766          * clean_rx handler before we do so.  */
1767         igb_configure(adapter);
1768
1769         igb_vmm_control(adapter);
1770         igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
1771         igb_set_vmolr(hw, adapter->vfs_allocated_count);
1772
1773         err = igb_request_irq(adapter);
1774         if (err)
1775                 goto err_req_irq;
1776
1777         /* From here on the code is the same as igb_up() */
1778         clear_bit(__IGB_DOWN, &adapter->state);
1779
1780         for (i = 0; i < adapter->num_rx_queues; i++)
1781                 napi_enable(&adapter->rx_ring[i].napi);
1782
1783         /* Clear any pending interrupts. */
1784         rd32(E1000_ICR);
1785
1786         igb_irq_enable(adapter);
1787
1788         netif_tx_start_all_queues(netdev);
1789
1790         /* Fire a link status change interrupt to start the watchdog. */
1791         wr32(E1000_ICS, E1000_ICS_LSC);
1792
1793         return 0;
1794
1795 err_req_irq:
1796         igb_release_hw_control(adapter);
1797         /* e1000_power_down_phy(adapter); */
1798         igb_free_all_rx_resources(adapter);
1799 err_setup_rx:
1800         igb_free_all_tx_resources(adapter);
1801 err_setup_tx:
1802         igb_reset(adapter);
1803
1804         return err;
1805 }
1806
1807 /**
1808  * igb_close - Disables a network interface
1809  * @netdev: network interface device structure
1810  *
1811  * Returns 0, this is not allowed to fail
1812  *
1813  * The close entry point is called when an interface is de-activated
1814  * by the OS.  The hardware is still under the driver's control, but
1815  * needs to be disabled.  A global MAC reset is issued to stop the
1816  * hardware, and all transmit and receive resources are freed.
1817  **/
1818 static int igb_close(struct net_device *netdev)
1819 {
1820         struct igb_adapter *adapter = netdev_priv(netdev);
1821
1822         WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1823         igb_down(adapter);
1824
1825         igb_free_irq(adapter);
1826
1827         igb_free_all_tx_resources(adapter);
1828         igb_free_all_rx_resources(adapter);
1829
1830         /* kill manageability vlan ID if supported, but not if a vlan with
1831          * the same ID is registered on the host OS (let 8021q kill it) */
1832         if ((adapter->hw.mng_cookie.status &
1833                           E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1834              !(adapter->vlgrp &&
1835                vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1836                 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1837
1838         return 0;
1839 }
1840
1841 /**
1842  * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1843  * @adapter: board private structure
1844  * @tx_ring: tx descriptor ring (for a specific queue) to setup
1845  *
1846  * Return 0 on success, negative on failure
1847  **/
1848 int igb_setup_tx_resources(struct igb_adapter *adapter,
1849                            struct igb_ring *tx_ring)
1850 {
1851         struct pci_dev *pdev = adapter->pdev;
1852         int size;
1853
1854         size = sizeof(struct igb_buffer) * tx_ring->count;
1855         tx_ring->buffer_info = vmalloc(size);
1856         if (!tx_ring->buffer_info)
1857                 goto err;
1858         memset(tx_ring->buffer_info, 0, size);
1859
1860         /* round up to nearest 4K */
1861         tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
1862         tx_ring->size = ALIGN(tx_ring->size, 4096);
1863
1864         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1865                                              &tx_ring->dma);
1866
1867         if (!tx_ring->desc)
1868                 goto err;
1869
1870         tx_ring->adapter = adapter;
1871         tx_ring->next_to_use = 0;
1872         tx_ring->next_to_clean = 0;
1873         return 0;
1874
1875 err:
1876         vfree(tx_ring->buffer_info);
1877         dev_err(&adapter->pdev->dev,
1878                 "Unable to allocate memory for the transmit descriptor ring\n");
1879         return -ENOMEM;
1880 }
1881
1882 /**
1883  * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1884  *                                (Descriptors) for all queues
1885  * @adapter: board private structure
1886  *
1887  * Return 0 on success, negative on failure
1888  **/
1889 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1890 {
1891         int i, err = 0;
1892         int r_idx;
1893
1894         for (i = 0; i < adapter->num_tx_queues; i++) {
1895                 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1896                 if (err) {
1897                         dev_err(&adapter->pdev->dev,
1898                                 "Allocation for Tx Queue %u failed\n", i);
1899                         for (i--; i >= 0; i--)
1900                                 igb_free_tx_resources(&adapter->tx_ring[i]);
1901                         break;
1902                 }
1903         }
1904
1905         for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1906                 r_idx = i % adapter->num_tx_queues;
1907                 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
1908         }
1909         return err;
1910 }
1911
1912 /**
1913  * igb_configure_tx - Configure transmit Unit after Reset
1914  * @adapter: board private structure
1915  *
1916  * Configure the Tx unit of the MAC after a reset.
1917  **/
1918 static void igb_configure_tx(struct igb_adapter *adapter)
1919 {
1920         u64 tdba;
1921         struct e1000_hw *hw = &adapter->hw;
1922         u32 tctl;
1923         u32 txdctl, txctrl;
1924         int i, j;
1925
1926         for (i = 0; i < adapter->num_tx_queues; i++) {
1927                 struct igb_ring *ring = &adapter->tx_ring[i];
1928                 j = ring->reg_idx;
1929                 wr32(E1000_TDLEN(j),
1930                      ring->count * sizeof(union e1000_adv_tx_desc));
1931                 tdba = ring->dma;
1932                 wr32(E1000_TDBAL(j),
1933                      tdba & 0x00000000ffffffffULL);
1934                 wr32(E1000_TDBAH(j), tdba >> 32);
1935
1936                 ring->head = E1000_TDH(j);
1937                 ring->tail = E1000_TDT(j);
1938                 writel(0, hw->hw_addr + ring->tail);
1939                 writel(0, hw->hw_addr + ring->head);
1940                 txdctl = rd32(E1000_TXDCTL(j));
1941                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1942                 wr32(E1000_TXDCTL(j), txdctl);
1943
1944                 /* Turn off Relaxed Ordering on head write-backs.  The
1945                  * writebacks MUST be delivered in order or it will
1946                  * completely screw up our bookeeping.
1947                  */
1948                 txctrl = rd32(E1000_DCA_TXCTRL(j));
1949                 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1950                 wr32(E1000_DCA_TXCTRL(j), txctrl);
1951         }
1952
1953         /* disable queue 0 to prevent tail bump w/o re-configuration */
1954         if (adapter->vfs_allocated_count)
1955                 wr32(E1000_TXDCTL(0), 0);
1956
1957         /* Program the Transmit Control Register */
1958         tctl = rd32(E1000_TCTL);
1959         tctl &= ~E1000_TCTL_CT;
1960         tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1961                 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1962
1963         igb_config_collision_dist(hw);
1964
1965         /* Setup Transmit Descriptor Settings for eop descriptor */
1966         adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1967
1968         /* Enable transmits */
1969         tctl |= E1000_TCTL_EN;
1970
1971         wr32(E1000_TCTL, tctl);
1972 }
1973
1974 /**
1975  * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1976  * @adapter: board private structure
1977  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
1978  *
1979  * Returns 0 on success, negative on failure
1980  **/
1981 int igb_setup_rx_resources(struct igb_adapter *adapter,
1982                            struct igb_ring *rx_ring)
1983 {
1984         struct pci_dev *pdev = adapter->pdev;
1985         int size, desc_len;
1986
1987         size = sizeof(struct igb_buffer) * rx_ring->count;
1988         rx_ring->buffer_info = vmalloc(size);
1989         if (!rx_ring->buffer_info)
1990                 goto err;
1991         memset(rx_ring->buffer_info, 0, size);
1992
1993         desc_len = sizeof(union e1000_adv_rx_desc);
1994
1995         /* Round up to nearest 4K */
1996         rx_ring->size = rx_ring->count * desc_len;
1997         rx_ring->size = ALIGN(rx_ring->size, 4096);
1998
1999         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
2000                                              &rx_ring->dma);
2001
2002         if (!rx_ring->desc)
2003                 goto err;
2004
2005         rx_ring->next_to_clean = 0;
2006         rx_ring->next_to_use = 0;
2007
2008         rx_ring->adapter = adapter;
2009
2010         return 0;
2011
2012 err:
2013         vfree(rx_ring->buffer_info);
2014         dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
2015                 "the receive descriptor ring\n");
2016         return -ENOMEM;
2017 }
2018
2019 /**
2020  * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2021  *                                (Descriptors) for all queues
2022  * @adapter: board private structure
2023  *
2024  * Return 0 on success, negative on failure
2025  **/
2026 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
2027 {
2028         int i, err = 0;
2029
2030         for (i = 0; i < adapter->num_rx_queues; i++) {
2031                 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
2032                 if (err) {
2033                         dev_err(&adapter->pdev->dev,
2034                                 "Allocation for Rx Queue %u failed\n", i);
2035                         for (i--; i >= 0; i--)
2036                                 igb_free_rx_resources(&adapter->rx_ring[i]);
2037                         break;
2038                 }
2039         }
2040
2041         return err;
2042 }
2043
2044 /**
2045  * igb_setup_rctl - configure the receive control registers
2046  * @adapter: Board private structure
2047  **/
2048 static void igb_setup_rctl(struct igb_adapter *adapter)
2049 {
2050         struct e1000_hw *hw = &adapter->hw;
2051         u32 rctl;
2052         u32 srrctl = 0;
2053         int i;
2054
2055         rctl = rd32(E1000_RCTL);
2056
2057         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2058         rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
2059
2060         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
2061                 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2062
2063         /*
2064          * enable stripping of CRC. It's unlikely this will break BMC
2065          * redirection as it did with e1000. Newer features require
2066          * that the HW strips the CRC.
2067          */
2068         rctl |= E1000_RCTL_SECRC;
2069
2070         /*
2071          * disable store bad packets and clear size bits.
2072          */
2073         rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
2074
2075         /* enable LPE when to prevent packets larger than max_frame_size */
2076                 rctl |= E1000_RCTL_LPE;
2077
2078         /* Setup buffer sizes */
2079         switch (adapter->rx_buffer_len) {
2080         case IGB_RXBUFFER_256:
2081                 rctl |= E1000_RCTL_SZ_256;
2082                 break;
2083         case IGB_RXBUFFER_512:
2084                 rctl |= E1000_RCTL_SZ_512;
2085                 break;
2086         default:
2087                 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
2088                          >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2089                 break;
2090         }
2091
2092         /* 82575 and greater support packet-split where the protocol
2093          * header is placed in skb->data and the packet data is
2094          * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2095          * In the case of a non-split, skb->data is linearly filled,
2096          * followed by the page buffers.  Therefore, skb->data is
2097          * sized to hold the largest protocol header.
2098          */
2099         /* allocations using alloc_page take too long for regular MTU
2100          * so only enable packet split for jumbo frames */
2101         if (adapter->netdev->mtu > ETH_DATA_LEN) {
2102                 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
2103                 srrctl |= adapter->rx_ps_hdr_size <<
2104                          E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2105                 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2106         } else {
2107                 adapter->rx_ps_hdr_size = 0;
2108                 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2109         }
2110
2111         /* Attention!!!  For SR-IOV PF driver operations you must enable
2112          * queue drop for all VF and PF queues to prevent head of line blocking
2113          * if an un-trusted VF does not provide descriptors to hardware.
2114          */
2115         if (adapter->vfs_allocated_count) {
2116                 u32 vmolr;
2117
2118                 /* set all queue drop enable bits */
2119                 wr32(E1000_QDE, ALL_QUEUES);
2120                 srrctl |= E1000_SRRCTL_DROP_EN;
2121
2122                 /* disable queue 0 to prevent tail write w/o re-config */
2123                 wr32(E1000_RXDCTL(0), 0);
2124
2125                 vmolr = rd32(E1000_VMOLR(adapter->vfs_allocated_count));
2126                 if (rctl & E1000_RCTL_LPE)
2127                         vmolr |= E1000_VMOLR_LPE;
2128                 if (adapter->num_rx_queues > 1)
2129                         vmolr |= E1000_VMOLR_RSSE;
2130                 wr32(E1000_VMOLR(adapter->vfs_allocated_count), vmolr);
2131         }
2132
2133         for (i = 0; i < adapter->num_rx_queues; i++) {
2134                 int j = adapter->rx_ring[i].reg_idx;
2135                 wr32(E1000_SRRCTL(j), srrctl);
2136         }
2137
2138         wr32(E1000_RCTL, rctl);
2139 }
2140
2141 /**
2142  * igb_rlpml_set - set maximum receive packet size
2143  * @adapter: board private structure
2144  *
2145  * Configure maximum receivable packet size.
2146  **/
2147 static void igb_rlpml_set(struct igb_adapter *adapter)
2148 {
2149         u32 max_frame_size = adapter->max_frame_size;
2150         struct e1000_hw *hw = &adapter->hw;
2151         u16 pf_id = adapter->vfs_allocated_count;
2152
2153         if (adapter->vlgrp)
2154                 max_frame_size += VLAN_TAG_SIZE;
2155
2156         /* if vfs are enabled we set RLPML to the largest possible request
2157          * size and set the VMOLR RLPML to the size we need */
2158         if (pf_id) {
2159                 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
2160                 max_frame_size = MAX_STD_JUMBO_FRAME_SIZE + VLAN_TAG_SIZE;
2161         }
2162
2163         wr32(E1000_RLPML, max_frame_size);
2164 }
2165
2166 /**
2167  * igb_configure_vt_default_pool - Configure VT default pool
2168  * @adapter: board private structure
2169  *
2170  * Configure the default pool
2171  **/
2172 static void igb_configure_vt_default_pool(struct igb_adapter *adapter)
2173 {
2174         struct e1000_hw *hw = &adapter->hw;
2175         u16 pf_id = adapter->vfs_allocated_count;
2176         u32 vtctl;
2177
2178         /* not in sr-iov mode - do nothing */
2179         if (!pf_id)
2180                 return;
2181
2182         vtctl = rd32(E1000_VT_CTL);
2183         vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2184                    E1000_VT_CTL_DISABLE_DEF_POOL);
2185         vtctl |= pf_id << E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2186         wr32(E1000_VT_CTL, vtctl);
2187 }
2188
2189 /**
2190  * igb_configure_rx - Configure receive Unit after Reset
2191  * @adapter: board private structure
2192  *
2193  * Configure the Rx unit of the MAC after a reset.
2194  **/
2195 static void igb_configure_rx(struct igb_adapter *adapter)
2196 {
2197         u64 rdba;
2198         struct e1000_hw *hw = &adapter->hw;
2199         u32 rctl, rxcsum;
2200         u32 rxdctl;
2201         int i;
2202
2203         /* disable receives while setting up the descriptors */
2204         rctl = rd32(E1000_RCTL);
2205         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2206         wrfl();
2207         mdelay(10);
2208
2209         if (adapter->itr_setting > 3)
2210                 wr32(E1000_ITR, adapter->itr);
2211
2212         /* Setup the HW Rx Head and Tail Descriptor Pointers and
2213          * the Base and Length of the Rx Descriptor Ring */
2214         for (i = 0; i < adapter->num_rx_queues; i++) {
2215                 struct igb_ring *ring = &adapter->rx_ring[i];
2216                 int j = ring->reg_idx;
2217                 rdba = ring->dma;
2218                 wr32(E1000_RDBAL(j),
2219                      rdba & 0x00000000ffffffffULL);
2220                 wr32(E1000_RDBAH(j), rdba >> 32);
2221                 wr32(E1000_RDLEN(j),
2222                      ring->count * sizeof(union e1000_adv_rx_desc));
2223
2224                 ring->head = E1000_RDH(j);
2225                 ring->tail = E1000_RDT(j);
2226                 writel(0, hw->hw_addr + ring->tail);
2227                 writel(0, hw->hw_addr + ring->head);
2228
2229                 rxdctl = rd32(E1000_RXDCTL(j));
2230                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2231                 rxdctl &= 0xFFF00000;
2232                 rxdctl |= IGB_RX_PTHRESH;
2233                 rxdctl |= IGB_RX_HTHRESH << 8;
2234                 rxdctl |= IGB_RX_WTHRESH << 16;
2235                 wr32(E1000_RXDCTL(j), rxdctl);
2236         }
2237
2238         if (adapter->num_rx_queues > 1) {
2239                 u32 random[10];
2240                 u32 mrqc;
2241                 u32 j, shift;
2242                 union e1000_reta {
2243                         u32 dword;
2244                         u8  bytes[4];
2245                 } reta;
2246
2247                 get_random_bytes(&random[0], 40);
2248
2249                 if (hw->mac.type >= e1000_82576)
2250                         shift = 0;
2251                 else
2252                         shift = 6;
2253                 for (j = 0; j < (32 * 4); j++) {
2254                         reta.bytes[j & 3] =
2255                                 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
2256                         if ((j & 3) == 3)
2257                                 writel(reta.dword,
2258                                        hw->hw_addr + E1000_RETA(0) + (j & ~3));
2259                 }
2260                 if (adapter->vfs_allocated_count)
2261                         mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2262                 else
2263                         mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2264
2265                 /* Fill out hash function seeds */
2266                 for (j = 0; j < 10; j++)
2267                         array_wr32(E1000_RSSRK(0), j, random[j]);
2268
2269                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2270                          E1000_MRQC_RSS_FIELD_IPV4_TCP);
2271                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2272                          E1000_MRQC_RSS_FIELD_IPV6_TCP);
2273                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
2274                          E1000_MRQC_RSS_FIELD_IPV6_UDP);
2275                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2276                          E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2277
2278                 wr32(E1000_MRQC, mrqc);
2279         } else if (adapter->vfs_allocated_count) {
2280                 /* Enable multi-queue for sr-iov */
2281                 wr32(E1000_MRQC, E1000_MRQC_ENABLE_VMDQ);
2282         }
2283
2284         /* Enable Receive Checksum Offload for TCP and UDP */
2285         rxcsum = rd32(E1000_RXCSUM);
2286         /* Disable raw packet checksumming */
2287         rxcsum |= E1000_RXCSUM_PCSD;
2288
2289         if (adapter->hw.mac.type == e1000_82576)
2290                 /* Enable Receive Checksum Offload for SCTP */
2291                 rxcsum |= E1000_RXCSUM_CRCOFL;
2292
2293         /* Don't need to set TUOFL or IPOFL, they default to 1 */
2294         wr32(E1000_RXCSUM, rxcsum);
2295
2296         /* Set the default pool for the PF's first queue */
2297         igb_configure_vt_default_pool(adapter);
2298
2299         igb_rlpml_set(adapter);
2300
2301         /* Enable Receives */
2302         wr32(E1000_RCTL, rctl);
2303 }
2304
2305 /**
2306  * igb_free_tx_resources - Free Tx Resources per Queue
2307  * @tx_ring: Tx descriptor ring for a specific queue
2308  *
2309  * Free all transmit software resources
2310  **/
2311 void igb_free_tx_resources(struct igb_ring *tx_ring)
2312 {
2313         struct pci_dev *pdev = tx_ring->adapter->pdev;
2314
2315         igb_clean_tx_ring(tx_ring);
2316
2317         vfree(tx_ring->buffer_info);
2318         tx_ring->buffer_info = NULL;
2319
2320         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2321
2322         tx_ring->desc = NULL;
2323 }
2324
2325 /**
2326  * igb_free_all_tx_resources - Free Tx Resources for All Queues
2327  * @adapter: board private structure
2328  *
2329  * Free all transmit software resources
2330  **/
2331 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2332 {
2333         int i;
2334
2335         for (i = 0; i < adapter->num_tx_queues; i++)
2336                 igb_free_tx_resources(&adapter->tx_ring[i]);
2337 }
2338
2339 static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2340                                            struct igb_buffer *buffer_info)
2341 {
2342         buffer_info->dma = 0;
2343         if (buffer_info->skb) {
2344                 skb_dma_unmap(&adapter->pdev->dev, buffer_info->skb,
2345                               DMA_TO_DEVICE);
2346                 dev_kfree_skb_any(buffer_info->skb);
2347                 buffer_info->skb = NULL;
2348         }
2349         buffer_info->time_stamp = 0;
2350         /* buffer_info must be completely set up in the transmit path */
2351 }
2352
2353 /**
2354  * igb_clean_tx_ring - Free Tx Buffers
2355  * @tx_ring: ring to be cleaned
2356  **/
2357 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
2358 {
2359         struct igb_adapter *adapter = tx_ring->adapter;
2360         struct igb_buffer *buffer_info;
2361         unsigned long size;
2362         unsigned int i;
2363
2364         if (!tx_ring->buffer_info)
2365                 return;
2366         /* Free all the Tx ring sk_buffs */
2367
2368         for (i = 0; i < tx_ring->count; i++) {
2369                 buffer_info = &tx_ring->buffer_info[i];
2370                 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2371         }
2372
2373         size = sizeof(struct igb_buffer) * tx_ring->count;
2374         memset(tx_ring->buffer_info, 0, size);
2375
2376         /* Zero out the descriptor ring */
2377
2378         memset(tx_ring->desc, 0, tx_ring->size);
2379
2380         tx_ring->next_to_use = 0;
2381         tx_ring->next_to_clean = 0;
2382
2383         writel(0, adapter->hw.hw_addr + tx_ring->head);
2384         writel(0, adapter->hw.hw_addr + tx_ring->tail);
2385 }
2386
2387 /**
2388  * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2389  * @adapter: board private structure
2390  **/
2391 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2392 {
2393         int i;
2394
2395         for (i = 0; i < adapter->num_tx_queues; i++)
2396                 igb_clean_tx_ring(&adapter->tx_ring[i]);
2397 }
2398
2399 /**
2400  * igb_free_rx_resources - Free Rx Resources
2401  * @rx_ring: ring to clean the resources from
2402  *
2403  * Free all receive software resources
2404  **/
2405 void igb_free_rx_resources(struct igb_ring *rx_ring)
2406 {
2407         struct pci_dev *pdev = rx_ring->adapter->pdev;
2408
2409         igb_clean_rx_ring(rx_ring);
2410
2411         vfree(rx_ring->buffer_info);
2412         rx_ring->buffer_info = NULL;
2413
2414         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2415
2416         rx_ring->desc = NULL;
2417 }
2418
2419 /**
2420  * igb_free_all_rx_resources - Free Rx Resources for All Queues
2421  * @adapter: board private structure
2422  *
2423  * Free all receive software resources
2424  **/
2425 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2426 {
2427         int i;
2428
2429         for (i = 0; i < adapter->num_rx_queues; i++)
2430                 igb_free_rx_resources(&adapter->rx_ring[i]);
2431 }
2432
2433 /**
2434  * igb_clean_rx_ring - Free Rx Buffers per Queue
2435  * @rx_ring: ring to free buffers from
2436  **/
2437 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
2438 {
2439         struct igb_adapter *adapter = rx_ring->adapter;
2440         struct igb_buffer *buffer_info;
2441         struct pci_dev *pdev = adapter->pdev;
2442         unsigned long size;
2443         unsigned int i;
2444
2445         if (!rx_ring->buffer_info)
2446                 return;
2447         /* Free all the Rx ring sk_buffs */
2448         for (i = 0; i < rx_ring->count; i++) {
2449                 buffer_info = &rx_ring->buffer_info[i];
2450                 if (buffer_info->dma) {
2451                         if (adapter->rx_ps_hdr_size)
2452                                 pci_unmap_single(pdev, buffer_info->dma,
2453                                                  adapter->rx_ps_hdr_size,
2454                                                  PCI_DMA_FROMDEVICE);
2455                         else
2456                                 pci_unmap_single(pdev, buffer_info->dma,
2457                                                  adapter->rx_buffer_len,
2458                                                  PCI_DMA_FROMDEVICE);
2459                         buffer_info->dma = 0;
2460                 }
2461
2462                 if (buffer_info->skb) {
2463                         dev_kfree_skb(buffer_info->skb);
2464                         buffer_info->skb = NULL;
2465                 }
2466                 if (buffer_info->page) {
2467                         if (buffer_info->page_dma)
2468                                 pci_unmap_page(pdev, buffer_info->page_dma,
2469                                                PAGE_SIZE / 2,
2470                                                PCI_DMA_FROMDEVICE);
2471                         put_page(buffer_info->page);
2472                         buffer_info->page = NULL;
2473                         buffer_info->page_dma = 0;
2474                         buffer_info->page_offset = 0;
2475                 }
2476         }
2477
2478         size = sizeof(struct igb_buffer) * rx_ring->count;
2479         memset(rx_ring->buffer_info, 0, size);
2480
2481         /* Zero out the descriptor ring */
2482         memset(rx_ring->desc, 0, rx_ring->size);
2483
2484         rx_ring->next_to_clean = 0;
2485         rx_ring->next_to_use = 0;
2486
2487         writel(0, adapter->hw.hw_addr + rx_ring->head);
2488         writel(0, adapter->hw.hw_addr + rx_ring->tail);
2489 }
2490
2491 /**
2492  * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2493  * @adapter: board private structure
2494  **/
2495 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2496 {
2497         int i;
2498
2499         for (i = 0; i < adapter->num_rx_queues; i++)
2500                 igb_clean_rx_ring(&adapter->rx_ring[i]);
2501 }
2502
2503 /**
2504  * igb_set_mac - Change the Ethernet Address of the NIC
2505  * @netdev: network interface device structure
2506  * @p: pointer to an address structure
2507  *
2508  * Returns 0 on success, negative on failure
2509  **/
2510 static int igb_set_mac(struct net_device *netdev, void *p)
2511 {
2512         struct igb_adapter *adapter = netdev_priv(netdev);
2513         struct e1000_hw *hw = &adapter->hw;
2514         struct sockaddr *addr = p;
2515
2516         if (!is_valid_ether_addr(addr->sa_data))
2517                 return -EADDRNOTAVAIL;
2518
2519         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2520         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
2521
2522         hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
2523
2524         igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
2525
2526         return 0;
2527 }
2528
2529 /**
2530  * igb_set_multi - Multicast and Promiscuous mode set
2531  * @netdev: network interface device structure
2532  *
2533  * The set_multi entry point is called whenever the multicast address
2534  * list or the network interface flags are updated.  This routine is
2535  * responsible for configuring the hardware for proper multicast,
2536  * promiscuous mode, and all-multi behavior.
2537  **/
2538 static void igb_set_multi(struct net_device *netdev)
2539 {
2540         struct igb_adapter *adapter = netdev_priv(netdev);
2541         struct e1000_hw *hw = &adapter->hw;
2542         struct dev_mc_list *mc_ptr;
2543         u8  *mta_list = NULL;
2544         u32 rctl;
2545         int i;
2546
2547         /* Check for Promiscuous and All Multicast modes */
2548
2549         rctl = rd32(E1000_RCTL);
2550
2551         if (netdev->flags & IFF_PROMISC) {
2552                 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2553                 rctl &= ~E1000_RCTL_VFE;
2554         } else {
2555                 if (netdev->flags & IFF_ALLMULTI) {
2556                         rctl |= E1000_RCTL_MPE;
2557                         rctl &= ~E1000_RCTL_UPE;
2558                 } else
2559                         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2560                 rctl |= E1000_RCTL_VFE;
2561         }
2562         wr32(E1000_RCTL, rctl);
2563
2564         if (!netdev->mc_count) {
2565                 /* nothing to program, so clear mc list */
2566                 igb_update_mc_addr_list(hw, NULL, 0);
2567                 igb_restore_vf_multicasts(adapter);
2568                 return;
2569         }
2570
2571         mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2572         if (!mta_list) {
2573                 dev_err(&adapter->pdev->dev,
2574                         "failed to allocate multicast filter list\n");
2575                 return;
2576         }
2577
2578         /* The shared function expects a packed array of only addresses. */
2579         mc_ptr = netdev->mc_list;
2580
2581         for (i = 0; i < netdev->mc_count; i++) {
2582                 if (!mc_ptr)
2583                         break;
2584                 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2585                 mc_ptr = mc_ptr->next;
2586         }
2587         igb_update_mc_addr_list(hw, mta_list, i);
2588         kfree(mta_list);
2589         igb_restore_vf_multicasts(adapter);
2590 }
2591
2592 /* Need to wait a few seconds after link up to get diagnostic information from
2593  * the phy */
2594 static void igb_update_phy_info(unsigned long data)
2595 {
2596         struct igb_adapter *adapter = (struct igb_adapter *) data;
2597         igb_get_phy_info(&adapter->hw);
2598 }
2599
2600 /**
2601  * igb_has_link - check shared code for link and determine up/down
2602  * @adapter: pointer to driver private info
2603  **/
2604 static bool igb_has_link(struct igb_adapter *adapter)
2605 {
2606         struct e1000_hw *hw = &adapter->hw;
2607         bool link_active = false;
2608         s32 ret_val = 0;
2609
2610         /* get_link_status is set on LSC (link status) interrupt or
2611          * rx sequence error interrupt.  get_link_status will stay
2612          * false until the e1000_check_for_link establishes link
2613          * for copper adapters ONLY
2614          */
2615         switch (hw->phy.media_type) {
2616         case e1000_media_type_copper:
2617                 if (hw->mac.get_link_status) {
2618                         ret_val = hw->mac.ops.check_for_link(hw);
2619                         link_active = !hw->mac.get_link_status;
2620                 } else {
2621                         link_active = true;
2622                 }
2623                 break;
2624         case e1000_media_type_internal_serdes:
2625                 ret_val = hw->mac.ops.check_for_link(hw);
2626                 link_active = hw->mac.serdes_has_link;
2627                 break;
2628         default:
2629         case e1000_media_type_unknown:
2630                 break;
2631         }
2632
2633         return link_active;
2634 }
2635
2636 /**
2637  * igb_watchdog - Timer Call-back
2638  * @data: pointer to adapter cast into an unsigned long
2639  **/
2640 static void igb_watchdog(unsigned long data)
2641 {
2642         struct igb_adapter *adapter = (struct igb_adapter *)data;
2643         /* Do the rest outside of interrupt context */
2644         schedule_work(&adapter->watchdog_task);
2645 }
2646
2647 static void igb_watchdog_task(struct work_struct *work)
2648 {
2649         struct igb_adapter *adapter = container_of(work,
2650                                         struct igb_adapter, watchdog_task);
2651         struct e1000_hw *hw = &adapter->hw;
2652         struct net_device *netdev = adapter->netdev;
2653         struct igb_ring *tx_ring = adapter->tx_ring;
2654         u32 link;
2655         u32 eics = 0;
2656         int i;
2657
2658         link = igb_has_link(adapter);
2659         if ((netif_carrier_ok(netdev)) && link)
2660                 goto link_up;
2661
2662         if (link) {
2663                 if (!netif_carrier_ok(netdev)) {
2664                         u32 ctrl;
2665                         hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2666                                                    &adapter->link_speed,
2667                                                    &adapter->link_duplex);
2668
2669                         ctrl = rd32(E1000_CTRL);
2670                         /* Links status message must follow this format */
2671                         printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
2672                                  "Flow Control: %s\n",
2673                                  netdev->name,
2674                                  adapter->link_speed,
2675                                  adapter->link_duplex == FULL_DUPLEX ?
2676                                  "Full Duplex" : "Half Duplex",
2677                                  ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2678                                  E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2679                                  E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2680                                  E1000_CTRL_TFCE) ? "TX" : "None")));
2681
2682                         /* tweak tx_queue_len according to speed/duplex and
2683                          * adjust the timeout factor */
2684                         netdev->tx_queue_len = adapter->tx_queue_len;
2685                         adapter->tx_timeout_factor = 1;
2686                         switch (adapter->link_speed) {
2687                         case SPEED_10:
2688                                 netdev->tx_queue_len = 10;
2689                                 adapter->tx_timeout_factor = 14;
2690                                 break;
2691                         case SPEED_100:
2692                                 netdev->tx_queue_len = 100;
2693                                 /* maybe add some timeout factor ? */
2694                                 break;
2695                         }
2696
2697                         netif_carrier_on(netdev);
2698
2699                         igb_ping_all_vfs(adapter);
2700
2701                         /* link state has changed, schedule phy info update */
2702                         if (!test_bit(__IGB_DOWN, &adapter->state))
2703                                 mod_timer(&adapter->phy_info_timer,
2704                                           round_jiffies(jiffies + 2 * HZ));
2705                 }
2706         } else {
2707                 if (netif_carrier_ok(netdev)) {
2708                         adapter->link_speed = 0;
2709                         adapter->link_duplex = 0;
2710                         /* Links status message must follow this format */
2711                         printk(KERN_INFO "igb: %s NIC Link is Down\n",
2712                                netdev->name);
2713                         netif_carrier_off(netdev);
2714
2715                         igb_ping_all_vfs(adapter);
2716
2717                         /* link state has changed, schedule phy info update */
2718                         if (!test_bit(__IGB_DOWN, &adapter->state))
2719                                 mod_timer(&adapter->phy_info_timer,
2720                                           round_jiffies(jiffies + 2 * HZ));
2721                 }
2722         }
2723
2724 link_up:
2725         igb_update_stats(adapter);
2726
2727         hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2728         adapter->tpt_old = adapter->stats.tpt;
2729         hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old;
2730         adapter->colc_old = adapter->stats.colc;
2731
2732         adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2733         adapter->gorc_old = adapter->stats.gorc;
2734         adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2735         adapter->gotc_old = adapter->stats.gotc;
2736
2737         igb_update_adaptive(&adapter->hw);
2738
2739         if (!netif_carrier_ok(netdev)) {
2740                 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
2741                         /* We've lost link, so the controller stops DMA,
2742                          * but we've got queued Tx work that's never going
2743                          * to get done, so reset controller to flush Tx.
2744                          * (Do the reset outside of interrupt context). */
2745                         adapter->tx_timeout_count++;
2746                         schedule_work(&adapter->reset_task);
2747                         /* return immediately since reset is imminent */
2748                         return;
2749                 }
2750         }
2751
2752         /* Cause software interrupt to ensure rx ring is cleaned */
2753         if (adapter->msix_entries) {
2754                 for (i = 0; i < adapter->num_rx_queues; i++)
2755                         eics |= adapter->rx_ring[i].eims_value;
2756                 wr32(E1000_EICS, eics);
2757         } else {
2758                 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2759         }
2760
2761         /* Force detection of hung controller every watchdog period */
2762         tx_ring->detect_tx_hung = true;
2763
2764         /* Reset the timer */
2765         if (!test_bit(__IGB_DOWN, &adapter->state))
2766                 mod_timer(&adapter->watchdog_timer,
2767                           round_jiffies(jiffies + 2 * HZ));
2768 }
2769
2770 enum latency_range {
2771         lowest_latency = 0,
2772         low_latency = 1,
2773         bulk_latency = 2,
2774         latency_invalid = 255
2775 };
2776
2777
2778 /**
2779  * igb_update_ring_itr - update the dynamic ITR value based on packet size
2780  *
2781  *      Stores a new ITR value based on strictly on packet size.  This
2782  *      algorithm is less sophisticated than that used in igb_update_itr,
2783  *      due to the difficulty of synchronizing statistics across multiple
2784  *      receive rings.  The divisors and thresholds used by this fuction
2785  *      were determined based on theoretical maximum wire speed and testing
2786  *      data, in order to minimize response time while increasing bulk
2787  *      throughput.
2788  *      This functionality is controlled by the InterruptThrottleRate module
2789  *      parameter (see igb_param.c)
2790  *      NOTE:  This function is called only when operating in a multiqueue
2791  *             receive environment.
2792  * @rx_ring: pointer to ring
2793  **/
2794 static void igb_update_ring_itr(struct igb_ring *rx_ring)
2795 {
2796         int new_val = rx_ring->itr_val;
2797         int avg_wire_size = 0;
2798         struct igb_adapter *adapter = rx_ring->adapter;
2799
2800         if (!rx_ring->total_packets)
2801                 goto clear_counts; /* no packets, so don't do anything */
2802
2803         /* For non-gigabit speeds, just fix the interrupt rate at 4000
2804          * ints/sec - ITR timer value of 120 ticks.
2805          */
2806         if (adapter->link_speed != SPEED_1000) {
2807                 new_val = 120;
2808                 goto set_itr_val;
2809         }
2810         avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
2811
2812         /* Add 24 bytes to size to account for CRC, preamble, and gap */
2813         avg_wire_size += 24;
2814
2815         /* Don't starve jumbo frames */
2816         avg_wire_size = min(avg_wire_size, 3000);
2817
2818         /* Give a little boost to mid-size frames */
2819         if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2820                 new_val = avg_wire_size / 3;
2821         else
2822                 new_val = avg_wire_size / 2;
2823
2824 set_itr_val:
2825         if (new_val != rx_ring->itr_val) {
2826                 rx_ring->itr_val = new_val;
2827                 rx_ring->set_itr = 1;
2828         }
2829 clear_counts:
2830         rx_ring->total_bytes = 0;
2831         rx_ring->total_packets = 0;
2832 }
2833
2834 /**
2835  * igb_update_itr - update the dynamic ITR value based on statistics
2836  *      Stores a new ITR value based on packets and byte
2837  *      counts during the last interrupt.  The advantage of per interrupt
2838  *      computation is faster updates and more accurate ITR for the current
2839  *      traffic pattern.  Constants in this function were computed
2840  *      based on theoretical maximum wire speed and thresholds were set based
2841  *      on testing data as well as attempting to minimize response time
2842  *      while increasing bulk throughput.
2843  *      this functionality is controlled by the InterruptThrottleRate module
2844  *      parameter (see igb_param.c)
2845  *      NOTE:  These calculations are only valid when operating in a single-
2846  *             queue environment.
2847  * @adapter: pointer to adapter
2848  * @itr_setting: current adapter->itr
2849  * @packets: the number of packets during this measurement interval
2850  * @bytes: the number of bytes during this measurement interval
2851  **/
2852 static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2853                                    int packets, int bytes)
2854 {
2855         unsigned int retval = itr_setting;
2856
2857         if (packets == 0)
2858                 goto update_itr_done;
2859
2860         switch (itr_setting) {
2861         case lowest_latency:
2862                 /* handle TSO and jumbo frames */
2863                 if (bytes/packets > 8000)
2864                         retval = bulk_latency;
2865                 else if ((packets < 5) && (bytes > 512))
2866                         retval = low_latency;
2867                 break;
2868         case low_latency:  /* 50 usec aka 20000 ints/s */
2869                 if (bytes > 10000) {
2870                         /* this if handles the TSO accounting */
2871                         if (bytes/packets > 8000) {
2872                                 retval = bulk_latency;
2873                         } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2874                                 retval = bulk_latency;
2875                         } else if ((packets > 35)) {
2876                                 retval = lowest_latency;
2877                         }
2878                 } else if (bytes/packets > 2000) {
2879                         retval = bulk_latency;
2880                 } else if (packets <= 2 && bytes < 512) {
2881                         retval = lowest_latency;
2882                 }
2883                 break;
2884         case bulk_latency: /* 250 usec aka 4000 ints/s */
2885                 if (bytes > 25000) {
2886                         if (packets > 35)
2887                                 retval = low_latency;
2888                 } else if (bytes < 1500) {
2889                         retval = low_latency;
2890                 }
2891                 break;
2892         }
2893
2894 update_itr_done:
2895         return retval;
2896 }
2897
2898 static void igb_set_itr(struct igb_adapter *adapter)
2899 {
2900         u16 current_itr;
2901         u32 new_itr = adapter->itr;
2902
2903         /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2904         if (adapter->link_speed != SPEED_1000) {
2905                 current_itr = 0;
2906                 new_itr = 4000;
2907                 goto set_itr_now;
2908         }
2909
2910         adapter->rx_itr = igb_update_itr(adapter,
2911                                     adapter->rx_itr,
2912                                     adapter->rx_ring->total_packets,
2913                                     adapter->rx_ring->total_bytes);
2914
2915         if (adapter->rx_ring->buddy) {
2916                 adapter->tx_itr = igb_update_itr(adapter,
2917                                             adapter->tx_itr,
2918                                             adapter->tx_ring->total_packets,
2919                                             adapter->tx_ring->total_bytes);
2920                 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2921         } else {
2922                 current_itr = adapter->rx_itr;
2923         }
2924
2925         /* conservative mode (itr 3) eliminates the lowest_latency setting */
2926         if (adapter->itr_setting == 3 && current_itr == lowest_latency)
2927                 current_itr = low_latency;
2928
2929         switch (current_itr) {
2930         /* counts and packets in update_itr are dependent on these numbers */
2931         case lowest_latency:
2932                 new_itr = 56;  /* aka 70,000 ints/sec */
2933                 break;
2934         case low_latency:
2935                 new_itr = 196; /* aka 20,000 ints/sec */
2936                 break;
2937         case bulk_latency:
2938                 new_itr = 980; /* aka 4,000 ints/sec */
2939                 break;
2940         default:
2941                 break;
2942         }
2943
2944 set_itr_now:
2945         adapter->rx_ring->total_bytes = 0;
2946         adapter->rx_ring->total_packets = 0;
2947         if (adapter->rx_ring->buddy) {
2948                 adapter->rx_ring->buddy->total_bytes = 0;
2949                 adapter->rx_ring->buddy->total_packets = 0;
2950         }
2951
2952         if (new_itr != adapter->itr) {
2953                 /* this attempts to bias the interrupt rate towards Bulk
2954                  * by adding intermediate steps when interrupt rate is
2955                  * increasing */
2956                 new_itr = new_itr > adapter->itr ?
2957                              max((new_itr * adapter->itr) /
2958                                  (new_itr + (adapter->itr >> 2)), new_itr) :
2959                              new_itr;
2960                 /* Don't write the value here; it resets the adapter's
2961                  * internal timer, and causes us to delay far longer than
2962                  * we should between interrupts.  Instead, we write the ITR
2963                  * value at the beginning of the next interrupt so the timing
2964                  * ends up being correct.
2965                  */
2966                 adapter->itr = new_itr;
2967                 adapter->rx_ring->itr_val = new_itr;
2968                 adapter->rx_ring->set_itr = 1;
2969         }
2970
2971         return;
2972 }
2973
2974
2975 #define IGB_TX_FLAGS_CSUM               0x00000001
2976 #define IGB_TX_FLAGS_VLAN               0x00000002
2977 #define IGB_TX_FLAGS_TSO                0x00000004
2978 #define IGB_TX_FLAGS_IPV4               0x00000008
2979 #define IGB_TX_FLAGS_TSTAMP             0x00000010
2980 #define IGB_TX_FLAGS_VLAN_MASK  0xffff0000
2981 #define IGB_TX_FLAGS_VLAN_SHIFT 16
2982
2983 static inline int igb_tso_adv(struct igb_adapter *adapter,
2984                               struct igb_ring *tx_ring,
2985                               struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2986 {
2987         struct e1000_adv_tx_context_desc *context_desc;
2988         unsigned int i;
2989         int err;
2990         struct igb_buffer *buffer_info;
2991         u32 info = 0, tu_cmd = 0;
2992         u32 mss_l4len_idx, l4len;
2993         *hdr_len = 0;
2994
2995         if (skb_header_cloned(skb)) {
2996                 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2997                 if (err)
2998                         return err;
2999         }
3000
3001         l4len = tcp_hdrlen(skb);
3002         *hdr_len += l4len;
3003
3004         if (skb->protocol == htons(ETH_P_IP)) {
3005                 struct iphdr *iph = ip_hdr(skb);
3006                 iph->tot_len = 0;
3007                 iph->check = 0;
3008                 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
3009                                                          iph->daddr, 0,
3010                                                          IPPROTO_TCP,
3011                                                          0);
3012         } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
3013                 ipv6_hdr(skb)->payload_len = 0;
3014                 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3015                                                        &ipv6_hdr(skb)->daddr,
3016                                                        0, IPPROTO_TCP, 0);
3017         }
3018
3019         i = tx_ring->next_to_use;
3020
3021         buffer_info = &tx_ring->buffer_info[i];
3022         context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3023         /* VLAN MACLEN IPLEN */
3024         if (tx_flags & IGB_TX_FLAGS_VLAN)
3025                 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3026         info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3027         *hdr_len += skb_network_offset(skb);
3028         info |= skb_network_header_len(skb);
3029         *hdr_len += skb_network_header_len(skb);
3030         context_desc->vlan_macip_lens = cpu_to_le32(info);
3031
3032         /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3033         tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3034
3035         if (skb->protocol == htons(ETH_P_IP))
3036                 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3037         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3038
3039         context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3040
3041         /* MSS L4LEN IDX */
3042         mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
3043         mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
3044
3045         /* For 82575, context index must be unique per ring. */
3046         if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3047                 mss_l4len_idx |= tx_ring->queue_index << 4;
3048
3049         context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3050         context_desc->seqnum_seed = 0;
3051
3052         buffer_info->time_stamp = jiffies;
3053         buffer_info->next_to_watch = i;
3054         buffer_info->dma = 0;
3055         i++;
3056         if (i == tx_ring->count)
3057                 i = 0;
3058
3059         tx_ring->next_to_use = i;
3060
3061         return true;
3062 }
3063
3064 static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
3065                                         struct igb_ring *tx_ring,
3066                                         struct sk_buff *skb, u32 tx_flags)
3067 {
3068         struct e1000_adv_tx_context_desc *context_desc;
3069         unsigned int i;
3070         struct igb_buffer *buffer_info;
3071         u32 info = 0, tu_cmd = 0;
3072
3073         if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
3074             (tx_flags & IGB_TX_FLAGS_VLAN)) {
3075                 i = tx_ring->next_to_use;
3076                 buffer_info = &tx_ring->buffer_info[i];
3077                 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3078
3079                 if (tx_flags & IGB_TX_FLAGS_VLAN)
3080                         info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3081                 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3082                 if (skb->ip_summed == CHECKSUM_PARTIAL)
3083                         info |= skb_network_header_len(skb);
3084
3085                 context_desc->vlan_macip_lens = cpu_to_le32(info);
3086
3087                 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3088
3089                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3090                         __be16 protocol;
3091
3092                         if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
3093                                 const struct vlan_ethhdr *vhdr =
3094                                           (const struct vlan_ethhdr*)skb->data;
3095
3096                                 protocol = vhdr->h_vlan_encapsulated_proto;
3097                         } else {
3098                                 protocol = skb->protocol;
3099                         }
3100
3101                         switch (protocol) {
3102                         case cpu_to_be16(ETH_P_IP):
3103                                 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3104                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3105                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3106                                 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
3107                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
3108                                 break;
3109                         case cpu_to_be16(ETH_P_IPV6):
3110                                 /* XXX what about other V6 headers?? */
3111                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3112                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3113                                 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
3114                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
3115                                 break;
3116                         default:
3117                                 if (unlikely(net_ratelimit()))
3118                                         dev_warn(&adapter->pdev->dev,
3119                                             "partial checksum but proto=%x!\n",
3120                                             skb->protocol);
3121                                 break;
3122                         }
3123                 }
3124
3125                 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3126                 context_desc->seqnum_seed = 0;
3127                 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3128                         context_desc->mss_l4len_idx =
3129                                 cpu_to_le32(tx_ring->queue_index << 4);
3130                 else
3131                         context_desc->mss_l4len_idx = 0;
3132
3133                 buffer_info->time_stamp = jiffies;
3134                 buffer_info->next_to_watch = i;
3135                 buffer_info->dma = 0;
3136
3137                 i++;
3138                 if (i == tx_ring->count)
3139                         i = 0;
3140                 tx_ring->next_to_use = i;
3141
3142                 return true;
3143         }
3144         return false;
3145 }
3146
3147 #define IGB_MAX_TXD_PWR 16
3148 #define IGB_MAX_DATA_PER_TXD    (1<<IGB_MAX_TXD_PWR)
3149
3150 static inline int igb_tx_map_adv(struct igb_adapter *adapter,
3151                                  struct igb_ring *tx_ring, struct sk_buff *skb,
3152                                  unsigned int first)
3153 {
3154         struct igb_buffer *buffer_info;
3155         unsigned int len = skb_headlen(skb);
3156         unsigned int count = 0, i;
3157         unsigned int f;
3158         dma_addr_t *map;
3159
3160         i = tx_ring->next_to_use;
3161
3162         if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
3163                 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
3164                 return 0;
3165         }
3166
3167         map = skb_shinfo(skb)->dma_maps;
3168
3169         buffer_info = &tx_ring->buffer_info[i];
3170         BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3171         buffer_info->length = len;
3172         /* set time_stamp *before* dma to help avoid a possible race */
3173         buffer_info->time_stamp = jiffies;
3174         buffer_info->next_to_watch = i;
3175         buffer_info->dma = skb_shinfo(skb)->dma_head;
3176
3177         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
3178                 struct skb_frag_struct *frag;
3179
3180                 i++;
3181                 if (i == tx_ring->count)
3182                         i = 0;
3183
3184                 frag = &skb_shinfo(skb)->frags[f];
3185                 len = frag->size;
3186
3187                 buffer_info = &tx_ring->buffer_info[i];
3188                 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3189                 buffer_info->length = len;
3190                 buffer_info->time_stamp = jiffies;
3191                 buffer_info->next_to_watch = i;
3192                 buffer_info->dma = map[count];
3193                 count++;
3194         }
3195
3196         tx_ring->buffer_info[i].skb = skb;
3197         tx_ring->buffer_info[first].next_to_watch = i;
3198
3199         return count + 1;
3200 }
3201
3202 static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
3203                                     struct igb_ring *tx_ring,
3204                                     int tx_flags, int count, u32 paylen,
3205                                     u8 hdr_len)
3206 {
3207         union e1000_adv_tx_desc *tx_desc = NULL;
3208         struct igb_buffer *buffer_info;
3209         u32 olinfo_status = 0, cmd_type_len;
3210         unsigned int i;
3211
3212         cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
3213                         E1000_ADVTXD_DCMD_DEXT);
3214
3215         if (tx_flags & IGB_TX_FLAGS_VLAN)
3216                 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3217
3218         if (tx_flags & IGB_TX_FLAGS_TSTAMP)
3219                 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
3220
3221         if (tx_flags & IGB_TX_FLAGS_TSO) {
3222                 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3223
3224                 /* insert tcp checksum */
3225                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3226
3227                 /* insert ip checksum */
3228                 if (tx_flags & IGB_TX_FLAGS_IPV4)
3229                         olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3230
3231         } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
3232                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3233         }
3234
3235         if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
3236             (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
3237                          IGB_TX_FLAGS_VLAN)))
3238                 olinfo_status |= tx_ring->queue_index << 4;
3239
3240         olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
3241
3242         i = tx_ring->next_to_use;
3243         while (count--) {
3244                 buffer_info = &tx_ring->buffer_info[i];
3245                 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3246                 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
3247                 tx_desc->read.cmd_type_len =
3248                         cpu_to_le32(cmd_type_len | buffer_info->length);
3249                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3250                 i++;
3251                 if (i == tx_ring->count)
3252                         i = 0;
3253         }
3254
3255         tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
3256         /* Force memory writes to complete before letting h/w
3257          * know there are new descriptors to fetch.  (Only
3258          * applicable for weak-ordered memory model archs,
3259          * such as IA-64). */
3260         wmb();
3261
3262         tx_ring->next_to_use = i;
3263         writel(i, adapter->hw.hw_addr + tx_ring->tail);
3264         /* we need this if more than one processor can write to our tail
3265          * at a time, it syncronizes IO on IA64/Altix systems */
3266         mmiowb();
3267 }
3268
3269 static int __igb_maybe_stop_tx(struct net_device *netdev,
3270                                struct igb_ring *tx_ring, int size)
3271 {
3272         struct igb_adapter *adapter = netdev_priv(netdev);
3273
3274         netif_stop_subqueue(netdev, tx_ring->queue_index);
3275
3276         /* Herbert's original patch had:
3277          *  smp_mb__after_netif_stop_queue();
3278          * but since that doesn't exist yet, just open code it. */
3279         smp_mb();
3280
3281         /* We need to check again in a case another CPU has just
3282          * made room available. */
3283         if (igb_desc_unused(tx_ring) < size)
3284                 return -EBUSY;
3285
3286         /* A reprieve! */
3287         netif_wake_subqueue(netdev, tx_ring->queue_index);
3288         ++adapter->restart_queue;
3289         return 0;
3290 }
3291
3292 static int igb_maybe_stop_tx(struct net_device *netdev,
3293                              struct igb_ring *tx_ring, int size)
3294 {
3295         if (igb_desc_unused(tx_ring) >= size)
3296                 return 0;
3297         return __igb_maybe_stop_tx(netdev, tx_ring, size);
3298 }
3299
3300 static netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *skb,
3301                                            struct net_device *netdev,
3302                                            struct igb_ring *tx_ring)
3303 {
3304         struct igb_adapter *adapter = netdev_priv(netdev);
3305         unsigned int first;
3306         unsigned int tx_flags = 0;
3307         u8 hdr_len = 0;
3308         int count = 0;
3309         int tso = 0;
3310         union skb_shared_tx *shtx;
3311
3312         if (test_bit(__IGB_DOWN, &adapter->state)) {
3313                 dev_kfree_skb_any(skb);
3314                 return NETDEV_TX_OK;
3315         }
3316
3317         if (skb->len <= 0) {
3318                 dev_kfree_skb_any(skb);
3319                 return NETDEV_TX_OK;
3320         }
3321
3322         /* need: 1 descriptor per page,
3323          *       + 2 desc gap to keep tail from touching head,
3324          *       + 1 desc for skb->data,
3325          *       + 1 desc for context descriptor,
3326          * otherwise try next time */
3327         if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
3328                 /* this is a hard error */
3329                 return NETDEV_TX_BUSY;
3330         }
3331
3332         /*
3333          * TODO: check that there currently is no other packet with
3334          * time stamping in the queue
3335          *
3336          * When doing time stamping, keep the connection to the socket
3337          * a while longer: it is still needed by skb_hwtstamp_tx(),
3338          * called either in igb_tx_hwtstamp() or by our caller when
3339          * doing software time stamping.
3340          */
3341         shtx = skb_tx(skb);
3342         if (unlikely(shtx->hardware)) {
3343                 shtx->in_progress = 1;
3344                 tx_flags |= IGB_TX_FLAGS_TSTAMP;
3345         }
3346
3347         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3348                 tx_flags |= IGB_TX_FLAGS_VLAN;
3349                 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
3350         }
3351
3352         if (skb->protocol == htons(ETH_P_IP))
3353                 tx_flags |= IGB_TX_FLAGS_IPV4;
3354
3355         first = tx_ring->next_to_use;
3356         tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
3357                                               &hdr_len) : 0;
3358
3359         if (tso < 0) {
3360                 dev_kfree_skb_any(skb);
3361                 return NETDEV_TX_OK;
3362         }
3363
3364         if (tso)
3365                 tx_flags |= IGB_TX_FLAGS_TSO;
3366         else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags) &&
3367                  (skb->ip_summed == CHECKSUM_PARTIAL))
3368                 tx_flags |= IGB_TX_FLAGS_CSUM;
3369
3370         /*
3371          * count reflects descriptors mapped, if 0 then mapping error
3372          * has occured and we need to rewind the descriptor queue
3373          */
3374         count = igb_tx_map_adv(adapter, tx_ring, skb, first);
3375
3376         if (count) {
3377                 igb_tx_queue_adv(adapter, tx_ring, tx_flags, count,
3378                                  skb->len, hdr_len);
3379                 /* Make sure there is space in the ring for the next send. */
3380                 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3381         } else {
3382                 dev_kfree_skb_any(skb);
3383                 tx_ring->buffer_info[first].time_stamp = 0;
3384                 tx_ring->next_to_use = first;
3385         }
3386
3387         return NETDEV_TX_OK;
3388 }
3389
3390 static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb,
3391                                       struct net_device *netdev)
3392 {
3393         struct igb_adapter *adapter = netdev_priv(netdev);
3394         struct igb_ring *tx_ring;
3395
3396         int r_idx = 0;
3397         r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
3398         tx_ring = adapter->multi_tx_table[r_idx];
3399
3400         /* This goes back to the question of how to logically map a tx queue
3401          * to a flow.  Right now, performance is impacted slightly negatively
3402          * if using multiple tx queues.  If the stack breaks away from a
3403          * single qdisc implementation, we can look at this again. */
3404         return igb_xmit_frame_ring_adv(skb, netdev, tx_ring);
3405 }
3406
3407 /**
3408  * igb_tx_timeout - Respond to a Tx Hang
3409  * @netdev: network interface device structure
3410  **/
3411 static void igb_tx_timeout(struct net_device *netdev)
3412 {
3413         struct igb_adapter *adapter = netdev_priv(netdev);
3414         struct e1000_hw *hw = &adapter->hw;
3415
3416         /* Do the reset outside of interrupt context */
3417         adapter->tx_timeout_count++;
3418         schedule_work(&adapter->reset_task);
3419         wr32(E1000_EICS,
3420              (adapter->eims_enable_mask & ~adapter->eims_other));
3421 }
3422
3423 static void igb_reset_task(struct work_struct *work)
3424 {
3425         struct igb_adapter *adapter;
3426         adapter = container_of(work, struct igb_adapter, reset_task);
3427
3428         igb_reinit_locked(adapter);
3429 }
3430
3431 /**
3432  * igb_get_stats - Get System Network Statistics
3433  * @netdev: network interface device structure
3434  *
3435  * Returns the address of the device statistics structure.
3436  * The statistics are actually updated from the timer callback.
3437  **/
3438 static struct net_device_stats *igb_get_stats(struct net_device *netdev)
3439 {
3440         struct igb_adapter *adapter = netdev_priv(netdev);
3441
3442         /* only return the current stats */
3443         return &adapter->net_stats;
3444 }
3445
3446 /**
3447  * igb_change_mtu - Change the Maximum Transfer Unit
3448  * @netdev: network interface device structure
3449  * @new_mtu: new value for maximum frame size
3450  *
3451  * Returns 0 on success, negative on failure
3452  **/
3453 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3454 {
3455         struct igb_adapter *adapter = netdev_priv(netdev);
3456         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3457
3458         if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3459             (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3460                 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3461                 return -EINVAL;
3462         }
3463
3464         if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3465                 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3466                 return -EINVAL;
3467         }
3468
3469         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3470                 msleep(1);
3471
3472         /* igb_down has a dependency on max_frame_size */
3473         adapter->max_frame_size = max_frame;
3474         if (netif_running(netdev))
3475                 igb_down(adapter);
3476
3477         /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3478          * means we reserve 2 more, this pushes us to allocate from the next
3479          * larger slab size.
3480          * i.e. RXBUFFER_2048 --> size-4096 slab
3481          */
3482
3483         if (max_frame <= IGB_RXBUFFER_256)
3484                 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3485         else if (max_frame <= IGB_RXBUFFER_512)
3486                 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3487         else if (max_frame <= IGB_RXBUFFER_1024)
3488                 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3489         else if (max_frame <= IGB_RXBUFFER_2048)
3490                 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3491         else
3492 #if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3493                 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3494 #else
3495                 adapter->rx_buffer_len = PAGE_SIZE / 2;
3496 #endif
3497
3498         /* if sr-iov is enabled we need to force buffer size to 1K or larger */
3499         if (adapter->vfs_allocated_count &&
3500             (adapter->rx_buffer_len < IGB_RXBUFFER_1024))
3501                 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3502
3503         /* adjust allocation if LPE protects us, and we aren't using SBP */
3504         if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3505              (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3506                 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3507
3508         dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3509                  netdev->mtu, new_mtu);
3510         netdev->mtu = new_mtu;
3511
3512         if (netif_running(netdev))
3513                 igb_up(adapter);
3514         else
3515                 igb_reset(adapter);
3516
3517         clear_bit(__IGB_RESETTING, &adapter->state);
3518
3519         return 0;
3520 }
3521
3522 /**
3523  * igb_update_stats - Update the board statistics counters
3524  * @adapter: board private structure
3525  **/
3526
3527 void igb_update_stats(struct igb_adapter *adapter)
3528 {
3529         struct e1000_hw *hw = &adapter->hw;
3530         struct pci_dev *pdev = adapter->pdev;
3531         u16 phy_tmp;
3532
3533 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3534
3535         /*
3536          * Prevent stats update while adapter is being reset, or if the pci
3537          * connection is down.
3538          */
3539         if (adapter->link_speed == 0)
3540                 return;
3541         if (pci_channel_offline(pdev))
3542                 return;
3543
3544         adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3545         adapter->stats.gprc += rd32(E1000_GPRC);
3546         adapter->stats.gorc += rd32(E1000_GORCL);
3547         rd32(E1000_GORCH); /* clear GORCL */
3548         adapter->stats.bprc += rd32(E1000_BPRC);
3549         adapter->stats.mprc += rd32(E1000_MPRC);
3550         adapter->stats.roc += rd32(E1000_ROC);
3551
3552         adapter->stats.prc64 += rd32(E1000_PRC64);
3553         adapter->stats.prc127 += rd32(E1000_PRC127);
3554         adapter->stats.prc255 += rd32(E1000_PRC255);
3555         adapter->stats.prc511 += rd32(E1000_PRC511);
3556         adapter->stats.prc1023 += rd32(E1000_PRC1023);
3557         adapter->stats.prc1522 += rd32(E1000_PRC1522);
3558         adapter->stats.symerrs += rd32(E1000_SYMERRS);
3559         adapter->stats.sec += rd32(E1000_SEC);
3560
3561         adapter->stats.mpc += rd32(E1000_MPC);
3562         adapter->stats.scc += rd32(E1000_SCC);
3563         adapter->stats.ecol += rd32(E1000_ECOL);
3564         adapter->stats.mcc += rd32(E1000_MCC);
3565         adapter->stats.latecol += rd32(E1000_LATECOL);
3566         adapter->stats.dc += rd32(E1000_DC);
3567         adapter->stats.rlec += rd32(E1000_RLEC);
3568         adapter->stats.xonrxc += rd32(E1000_XONRXC);
3569         adapter->stats.xontxc += rd32(E1000_XONTXC);
3570         adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3571         adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3572         adapter->stats.fcruc += rd32(E1000_FCRUC);
3573         adapter->stats.gptc += rd32(E1000_GPTC);
3574         adapter->stats.gotc += rd32(E1000_GOTCL);
3575         rd32(E1000_GOTCH); /* clear GOTCL */
3576         adapter->stats.rnbc += rd32(E1000_RNBC);
3577         adapter->stats.ruc += rd32(E1000_RUC);
3578         adapter->stats.rfc += rd32(E1000_RFC);
3579         adapter->stats.rjc += rd32(E1000_RJC);
3580         adapter->stats.tor += rd32(E1000_TORH);
3581         adapter->stats.tot += rd32(E1000_TOTH);
3582         adapter->stats.tpr += rd32(E1000_TPR);
3583
3584         adapter->stats.ptc64 += rd32(E1000_PTC64);
3585         adapter->stats.ptc127 += rd32(E1000_PTC127);
3586         adapter->stats.ptc255 += rd32(E1000_PTC255);
3587         adapter->stats.ptc511 += rd32(E1000_PTC511);
3588         adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3589         adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3590
3591         adapter->stats.mptc += rd32(E1000_MPTC);
3592         adapter->stats.bptc += rd32(E1000_BPTC);
3593
3594         /* used for adaptive IFS */
3595
3596         hw->mac.tx_packet_delta = rd32(E1000_TPT);
3597         adapter->stats.tpt += hw->mac.tx_packet_delta;
3598         hw->mac.collision_delta = rd32(E1000_COLC);
3599         adapter->stats.colc += hw->mac.collision_delta;
3600
3601         adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3602         adapter->stats.rxerrc += rd32(E1000_RXERRC);
3603         adapter->stats.tncrs += rd32(E1000_TNCRS);
3604         adapter->stats.tsctc += rd32(E1000_TSCTC);
3605         adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3606
3607         adapter->stats.iac += rd32(E1000_IAC);
3608         adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3609         adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3610         adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3611         adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3612         adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3613         adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3614         adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3615         adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3616
3617         /* Fill out the OS statistics structure */
3618         adapter->net_stats.multicast = adapter->stats.mprc;
3619         adapter->net_stats.collisions = adapter->stats.colc;
3620
3621         /* Rx Errors */
3622
3623         if (hw->mac.type != e1000_82575) {
3624                 u32 rqdpc_tmp;
3625                 u64 rqdpc_total = 0;
3626                 int i;
3627                 /* Read out drops stats per RX queue.  Notice RQDPC (Receive
3628                  * Queue Drop Packet Count) stats only gets incremented, if
3629                  * the DROP_EN but it set (in the SRRCTL register for that
3630                  * queue).  If DROP_EN bit is NOT set, then the some what
3631                  * equivalent count is stored in RNBC (not per queue basis).
3632                  * Also note the drop count is due to lack of available
3633                  * descriptors.
3634                  */
3635                 for (i = 0; i < adapter->num_rx_queues; i++) {
3636                         rqdpc_tmp = rd32(E1000_RQDPC(i)) & 0xFFF;
3637                         adapter->rx_ring[i].rx_stats.drops += rqdpc_tmp;
3638                         rqdpc_total += adapter->rx_ring[i].rx_stats.drops;
3639                 }
3640                 adapter->net_stats.rx_fifo_errors = rqdpc_total;
3641         }
3642
3643         /* Note RNBC (Receive No Buffers Count) is an not an exact
3644          * drop count as the hardware FIFO might save the day.  Thats
3645          * one of the reason for saving it in rx_fifo_errors, as its
3646          * potentially not a true drop.
3647          */
3648         adapter->net_stats.rx_fifo_errors += adapter->stats.rnbc;
3649
3650         /* RLEC on some newer hardware can be incorrect so build
3651          * our own version based on RUC and ROC */
3652         adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3653                 adapter->stats.crcerrs + adapter->stats.algnerrc +
3654                 adapter->stats.ruc + adapter->stats.roc +
3655                 adapter->stats.cexterr;
3656         adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3657                                               adapter->stats.roc;
3658         adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3659         adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3660         adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3661
3662         /* Tx Errors */
3663         adapter->net_stats.tx_errors = adapter->stats.ecol +
3664                                        adapter->stats.latecol;
3665         adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3666         adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3667         adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3668
3669         /* Tx Dropped needs to be maintained elsewhere */
3670
3671         /* Phy Stats */
3672         if (hw->phy.media_type == e1000_media_type_copper) {
3673                 if ((adapter->link_speed == SPEED_1000) &&
3674                    (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
3675                         phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3676                         adapter->phy_stats.idle_errors += phy_tmp;
3677                 }
3678         }
3679
3680         /* Management Stats */
3681         adapter->stats.mgptc += rd32(E1000_MGTPTC);
3682         adapter->stats.mgprc += rd32(E1000_MGTPRC);
3683         adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3684 }
3685
3686 static irqreturn_t igb_msix_other(int irq, void *data)
3687 {
3688         struct net_device *netdev = data;
3689         struct igb_adapter *adapter = netdev_priv(netdev);
3690         struct e1000_hw *hw = &adapter->hw;
3691         u32 icr = rd32(E1000_ICR);
3692
3693         /* reading ICR causes bit 31 of EICR to be cleared */
3694
3695         if(icr & E1000_ICR_DOUTSYNC) {
3696                 /* HW is reporting DMA is out of sync */
3697                 adapter->stats.doosync++;
3698         }
3699
3700         /* Check for a mailbox event */
3701         if (icr & E1000_ICR_VMMB)
3702                 igb_msg_task(adapter);
3703
3704         if (icr & E1000_ICR_LSC) {
3705                 hw->mac.get_link_status = 1;
3706                 /* guard against interrupt when we're going down */
3707                 if (!test_bit(__IGB_DOWN, &adapter->state))
3708                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
3709         }
3710
3711         wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_VMMB);
3712         wr32(E1000_EIMS, adapter->eims_other);
3713
3714         return IRQ_HANDLED;
3715 }
3716
3717 static irqreturn_t igb_msix_tx(int irq, void *data)
3718 {
3719         struct igb_ring *tx_ring = data;
3720         struct igb_adapter *adapter = tx_ring->adapter;
3721         struct e1000_hw *hw = &adapter->hw;
3722
3723 #ifdef CONFIG_IGB_DCA
3724         if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3725                 igb_update_tx_dca(tx_ring);
3726 #endif
3727
3728         tx_ring->total_bytes = 0;
3729         tx_ring->total_packets = 0;
3730
3731         /* auto mask will automatically reenable the interrupt when we write
3732          * EICS */
3733         if (!igb_clean_tx_irq(tx_ring))
3734                 /* Ring was not completely cleaned, so fire another interrupt */
3735                 wr32(E1000_EICS, tx_ring->eims_value);
3736         else
3737                 wr32(E1000_EIMS, tx_ring->eims_value);
3738
3739         return IRQ_HANDLED;
3740 }
3741
3742 static void igb_write_itr(struct igb_ring *ring)
3743 {
3744         struct e1000_hw *hw = &ring->adapter->hw;
3745         if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3746                 switch (hw->mac.type) {
3747                 case e1000_82576:
3748                         wr32(ring->itr_register, ring->itr_val |
3749                              0x80000000);
3750                         break;
3751                 default:
3752                         wr32(ring->itr_register, ring->itr_val |
3753                              (ring->itr_val << 16));
3754                         break;
3755                 }
3756                 ring->set_itr = 0;
3757         }
3758 }
3759
3760 static irqreturn_t igb_msix_rx(int irq, void *data)
3761 {
3762         struct igb_ring *rx_ring = data;
3763
3764         /* Write the ITR value calculated at the end of the
3765          * previous interrupt.
3766          */
3767
3768         igb_write_itr(rx_ring);
3769
3770         if (napi_schedule_prep(&rx_ring->napi))
3771                 __napi_schedule(&rx_ring->napi);
3772
3773 #ifdef CONFIG_IGB_DCA
3774         if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
3775                 igb_update_rx_dca(rx_ring);
3776 #endif
3777                 return IRQ_HANDLED;
3778 }
3779
3780 #ifdef CONFIG_IGB_DCA
3781 static void igb_update_rx_dca(struct igb_ring *rx_ring)
3782 {
3783         u32 dca_rxctrl;
3784         struct igb_adapter *adapter = rx_ring->adapter;
3785         struct e1000_hw *hw = &adapter->hw;
3786         int cpu = get_cpu();
3787         int q = rx_ring->reg_idx;
3788
3789         if (rx_ring->cpu != cpu) {
3790                 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
3791                 if (hw->mac.type == e1000_82576) {
3792                         dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3793                         dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
3794                                       E1000_DCA_RXCTRL_CPUID_SHIFT;
3795                 } else {
3796                         dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3797                         dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
3798                 }
3799                 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3800                 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3801                 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3802                 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3803                 rx_ring->cpu = cpu;
3804         }
3805         put_cpu();
3806 }
3807
3808 static void igb_update_tx_dca(struct igb_ring *tx_ring)
3809 {
3810         u32 dca_txctrl;
3811         struct igb_adapter *adapter = tx_ring->adapter;
3812         struct e1000_hw *hw = &adapter->hw;
3813         int cpu = get_cpu();
3814         int q = tx_ring->reg_idx;
3815
3816         if (tx_ring->cpu != cpu) {
3817                 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
3818                 if (hw->mac.type == e1000_82576) {
3819                         dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3820                         dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
3821                                       E1000_DCA_TXCTRL_CPUID_SHIFT;
3822                 } else {
3823                         dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3824                         dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
3825                 }
3826                 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3827                 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3828                 tx_ring->cpu = cpu;
3829         }
3830         put_cpu();
3831 }
3832
3833 static void igb_setup_dca(struct igb_adapter *adapter)
3834 {
3835         struct e1000_hw *hw = &adapter->hw;
3836         int i;
3837
3838         if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
3839                 return;
3840
3841         /* Always use CB2 mode, difference is masked in the CB driver. */
3842         wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
3843
3844         for (i = 0; i < adapter->num_tx_queues; i++) {
3845                 adapter->tx_ring[i].cpu = -1;
3846                 igb_update_tx_dca(&adapter->tx_ring[i]);
3847         }
3848         for (i = 0; i < adapter->num_rx_queues; i++) {
3849                 adapter->rx_ring[i].cpu = -1;
3850                 igb_update_rx_dca(&adapter->rx_ring[i]);
3851         }
3852 }
3853
3854 static int __igb_notify_dca(struct device *dev, void *data)
3855 {
3856         struct net_device *netdev = dev_get_drvdata(dev);
3857         struct igb_adapter *adapter = netdev_priv(netdev);
3858         struct e1000_hw *hw = &adapter->hw;
3859         unsigned long event = *(unsigned long *)data;
3860
3861         switch (event) {
3862         case DCA_PROVIDER_ADD:
3863                 /* if already enabled, don't do it again */
3864                 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3865                         break;
3866                 /* Always use CB2 mode, difference is masked
3867                  * in the CB driver. */
3868                 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
3869                 if (dca_add_requester(dev) == 0) {
3870                         adapter->flags |= IGB_FLAG_DCA_ENABLED;
3871                         dev_info(&adapter->pdev->dev, "DCA enabled\n");
3872                         igb_setup_dca(adapter);
3873                         break;
3874                 }
3875                 /* Fall Through since DCA is disabled. */
3876         case DCA_PROVIDER_REMOVE:
3877                 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
3878                         /* without this a class_device is left
3879                          * hanging around in the sysfs model */
3880                         dca_remove_requester(dev);
3881                         dev_info(&adapter->pdev->dev, "DCA disabled\n");
3882                         adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
3883                         wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
3884                 }
3885                 break;
3886         }
3887
3888         return 0;
3889 }
3890
3891 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3892                           void *p)
3893 {
3894         int ret_val;
3895
3896         ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3897                                          __igb_notify_dca);
3898
3899         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3900 }
3901 #endif /* CONFIG_IGB_DCA */
3902
3903 static void igb_ping_all_vfs(struct igb_adapter *adapter)
3904 {
3905         struct e1000_hw *hw = &adapter->hw;
3906         u32 ping;
3907         int i;
3908
3909         for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
3910                 ping = E1000_PF_CONTROL_MSG;
3911                 if (adapter->vf_data[i].clear_to_send)
3912                         ping |= E1000_VT_MSGTYPE_CTS;
3913                 igb_write_mbx(hw, &ping, 1, i);
3914         }
3915 }
3916
3917 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
3918                                   u32 *msgbuf, u32 vf)
3919 {
3920         int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
3921         u16 *hash_list = (u16 *)&msgbuf[1];
3922         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
3923         int i;
3924
3925         /* only up to 30 hash values supported */
3926         if (n > 30)
3927                 n = 30;
3928
3929         /* salt away the number of multi cast addresses assigned
3930          * to this VF for later use to restore when the PF multi cast
3931          * list changes
3932          */
3933         vf_data->num_vf_mc_hashes = n;
3934
3935         /* VFs are limited to using the MTA hash table for their multicast
3936          * addresses */
3937         for (i = 0; i < n; i++)
3938                 vf_data->vf_mc_hashes[i] = hash_list[i];;
3939
3940         /* Flush and reset the mta with the new values */
3941         igb_set_multi(adapter->netdev);
3942
3943         return 0;
3944 }
3945
3946 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
3947 {
3948         struct e1000_hw *hw = &adapter->hw;
3949         struct vf_data_storage *vf_data;
3950         int i, j;
3951
3952         for (i = 0; i < adapter->vfs_allocated_count; i++) {
3953                 vf_data = &adapter->vf_data[i];
3954                 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
3955                         igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
3956         }
3957 }
3958
3959 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
3960 {
3961         struct e1000_hw *hw = &adapter->hw;
3962         u32 pool_mask, reg, vid;
3963         int i;
3964
3965         pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
3966
3967         /* Find the vlan filter for this id */
3968         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3969                 reg = rd32(E1000_VLVF(i));
3970
3971                 /* remove the vf from the pool */
3972                 reg &= ~pool_mask;
3973
3974                 /* if pool is empty then remove entry from vfta */
3975                 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
3976                     (reg & E1000_VLVF_VLANID_ENABLE)) {
3977                         reg = 0;
3978                         vid = reg & E1000_VLVF_VLANID_MASK;
3979                         igb_vfta_set(hw, vid, false);
3980                 }
3981
3982                 wr32(E1000_VLVF(i), reg);
3983         }
3984 }
3985
3986 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
3987 {
3988         struct e1000_hw *hw = &adapter->hw;
3989         u32 reg, i;
3990
3991         /* It is an error to call this function when VFs are not enabled */
3992         if (!adapter->vfs_allocated_count)
3993                 return -1;
3994
3995         /* Find the vlan filter for this id */
3996         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3997                 reg = rd32(E1000_VLVF(i));
3998                 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
3999                     vid == (reg & E1000_VLVF_VLANID_MASK))
4000                         break;
4001         }
4002
4003         if (add) {
4004                 if (i == E1000_VLVF_ARRAY_SIZE) {
4005                         /* Did not find a matching VLAN ID entry that was
4006                          * enabled.  Search for a free filter entry, i.e.
4007                          * one without the enable bit set
4008                          */
4009                         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4010                                 reg = rd32(E1000_VLVF(i));
4011                                 if (!(reg & E1000_VLVF_VLANID_ENABLE))
4012                                         break;
4013                         }
4014                 }
4015                 if (i < E1000_VLVF_ARRAY_SIZE) {
4016                         /* Found an enabled/available entry */
4017                         reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4018
4019                         /* if !enabled we need to set this up in vfta */
4020                         if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
4021                                 /* add VID to filter table, if bit already set
4022                                  * PF must have added it outside of table */
4023                                 if (igb_vfta_set(hw, vid, true))
4024                                         reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT +
4025                                                 adapter->vfs_allocated_count);
4026                                 reg |= E1000_VLVF_VLANID_ENABLE;
4027                         }
4028                         reg &= ~E1000_VLVF_VLANID_MASK;
4029                         reg |= vid;
4030
4031                         wr32(E1000_VLVF(i), reg);
4032                         return 0;
4033                 }
4034         } else {
4035                 if (i < E1000_VLVF_ARRAY_SIZE) {
4036                         /* remove vf from the pool */
4037                         reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
4038                         /* if pool is empty then remove entry from vfta */
4039                         if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
4040                                 reg = 0;
4041                                 igb_vfta_set(hw, vid, false);
4042                         }
4043                         wr32(E1000_VLVF(i), reg);
4044                         return 0;
4045                 }
4046         }
4047         return -1;
4048 }
4049
4050 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
4051 {
4052         int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4053         int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
4054
4055         return igb_vlvf_set(adapter, vid, add, vf);
4056 }
4057
4058 static inline void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
4059 {
4060         struct e1000_hw *hw = &adapter->hw;
4061
4062         /* disable mailbox functionality for vf */
4063         adapter->vf_data[vf].clear_to_send = false;
4064
4065         /* reset offloads to defaults */
4066         igb_set_vmolr(hw, vf);
4067
4068         /* reset vlans for device */
4069         igb_clear_vf_vfta(adapter, vf);
4070
4071         /* reset multicast table array for vf */
4072         adapter->vf_data[vf].num_vf_mc_hashes = 0;
4073
4074         /* Flush and reset the mta with the new values */
4075         igb_set_multi(adapter->netdev);
4076 }
4077
4078 static inline void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4079 {
4080         struct e1000_hw *hw = &adapter->hw;
4081         unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
4082         u32 reg, msgbuf[3];
4083         u8 *addr = (u8 *)(&msgbuf[1]);
4084
4085         /* process all the same items cleared in a function level reset */
4086         igb_vf_reset_event(adapter, vf);
4087
4088         /* set vf mac address */
4089         igb_rar_set(hw, vf_mac, vf + 1);
4090         igb_set_rah_pool(hw, vf, vf + 1);
4091
4092         /* enable transmit and receive for vf */
4093         reg = rd32(E1000_VFTE);
4094         wr32(E1000_VFTE, reg | (1 << vf));
4095         reg = rd32(E1000_VFRE);
4096         wr32(E1000_VFRE, reg | (1 << vf));
4097
4098         /* enable mailbox functionality for vf */
4099         adapter->vf_data[vf].clear_to_send = true;
4100
4101         /* reply to reset with ack and vf mac address */
4102         msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
4103         memcpy(addr, vf_mac, 6);
4104         igb_write_mbx(hw, msgbuf, 3, vf);
4105 }
4106
4107 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
4108 {
4109                 unsigned char *addr = (char *)&msg[1];
4110                 int err = -1;
4111
4112                 if (is_valid_ether_addr(addr))
4113                         err = igb_set_vf_mac(adapter, vf, addr);
4114
4115                 return err;
4116
4117 }
4118
4119 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
4120 {
4121         struct e1000_hw *hw = &adapter->hw;
4122         u32 msg = E1000_VT_MSGTYPE_NACK;
4123
4124         /* if device isn't clear to send it shouldn't be reading either */
4125         if (!adapter->vf_data[vf].clear_to_send)
4126                 igb_write_mbx(hw, &msg, 1, vf);
4127 }
4128
4129
4130 static void igb_msg_task(struct igb_adapter *adapter)
4131 {
4132         struct e1000_hw *hw = &adapter->hw;
4133         u32 vf;
4134
4135         for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
4136                 /* process any reset requests */
4137                 if (!igb_check_for_rst(hw, vf)) {
4138                         adapter->vf_data[vf].clear_to_send = false;
4139                         igb_vf_reset_event(adapter, vf);
4140                 }
4141
4142                 /* process any messages pending */
4143                 if (!igb_check_for_msg(hw, vf))
4144                         igb_rcv_msg_from_vf(adapter, vf);
4145
4146                 /* process any acks */
4147                 if (!igb_check_for_ack(hw, vf))
4148                         igb_rcv_ack_from_vf(adapter, vf);
4149
4150         }
4151 }
4152
4153 static int igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4154 {
4155         u32 mbx_size = E1000_VFMAILBOX_SIZE;
4156         u32 msgbuf[mbx_size];
4157         struct e1000_hw *hw = &adapter->hw;
4158         s32 retval;
4159
4160         retval = igb_read_mbx(hw, msgbuf, mbx_size, vf);
4161
4162         if (retval)
4163                 dev_err(&adapter->pdev->dev,
4164                         "Error receiving message from VF\n");
4165
4166         /* this is a message we already processed, do nothing */
4167         if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
4168                 return retval;
4169
4170         /*
4171          * until the vf completes a reset it should not be
4172          * allowed to start any configuration.
4173          */
4174
4175         if (msgbuf[0] == E1000_VF_RESET) {
4176                 igb_vf_reset_msg(adapter, vf);
4177
4178                 return retval;
4179         }
4180
4181         if (!adapter->vf_data[vf].clear_to_send) {
4182                 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4183                 igb_write_mbx(hw, msgbuf, 1, vf);
4184                 return retval;
4185         }
4186
4187         switch ((msgbuf[0] & 0xFFFF)) {
4188         case E1000_VF_SET_MAC_ADDR:
4189                 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
4190                 break;
4191         case E1000_VF_SET_MULTICAST:
4192                 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
4193                 break;
4194         case E1000_VF_SET_LPE:
4195                 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
4196                 break;
4197         case E1000_VF_SET_VLAN:
4198                 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4199                 break;
4200         default:
4201                 dev_err(&adapter->pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4202                 retval = -1;
4203                 break;
4204         }
4205
4206         /* notify the VF of the results of what it sent us */
4207         if (retval)
4208                 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4209         else
4210                 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
4211
4212         msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
4213
4214         igb_write_mbx(hw, msgbuf, 1, vf);
4215
4216         return retval;
4217 }
4218
4219 /**
4220  * igb_intr_msi - Interrupt Handler
4221  * @irq: interrupt number
4222  * @data: pointer to a network interface device structure
4223  **/
4224 static irqreturn_t igb_intr_msi(int irq, void *data)
4225 {
4226         struct net_device *netdev = data;
4227         struct igb_adapter *adapter = netdev_priv(netdev);
4228         struct e1000_hw *hw = &adapter->hw;
4229         /* read ICR disables interrupts using IAM */
4230         u32 icr = rd32(E1000_ICR);
4231
4232         igb_write_itr(adapter->rx_ring);
4233
4234         if(icr & E1000_ICR_DOUTSYNC) {
4235                 /* HW is reporting DMA is out of sync */
4236                 adapter->stats.doosync++;
4237         }
4238
4239         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4240                 hw->mac.get_link_status = 1;
4241                 if (!test_bit(__IGB_DOWN, &adapter->state))
4242                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
4243         }
4244
4245         napi_schedule(&adapter->rx_ring[0].napi);
4246
4247         return IRQ_HANDLED;
4248 }
4249
4250 /**
4251  * igb_intr - Legacy Interrupt Handler
4252  * @irq: interrupt number
4253  * @data: pointer to a network interface device structure
4254  **/
4255 static irqreturn_t igb_intr(int irq, void *data)
4256 {
4257         struct net_device *netdev = data;
4258         struct igb_adapter *adapter = netdev_priv(netdev);
4259         struct e1000_hw *hw = &adapter->hw;
4260         /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked.  No
4261          * need for the IMC write */
4262         u32 icr = rd32(E1000_ICR);
4263         if (!icr)
4264                 return IRQ_NONE;  /* Not our interrupt */
4265
4266         igb_write_itr(adapter->rx_ring);
4267
4268         /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
4269          * not set, then the adapter didn't send an interrupt */
4270         if (!(icr & E1000_ICR_INT_ASSERTED))
4271                 return IRQ_NONE;
4272
4273         if(icr & E1000_ICR_DOUTSYNC) {
4274                 /* HW is reporting DMA is out of sync */
4275                 adapter->stats.doosync++;
4276         }
4277
4278         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4279                 hw->mac.get_link_status = 1;
4280                 /* guard against interrupt when we're going down */
4281                 if (!test_bit(__IGB_DOWN, &adapter->state))
4282                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
4283         }
4284
4285         napi_schedule(&adapter->rx_ring[0].napi);
4286
4287         return IRQ_HANDLED;
4288 }
4289
4290 static inline void igb_rx_irq_enable(struct igb_ring *rx_ring)
4291 {
4292         struct igb_adapter *adapter = rx_ring->adapter;
4293         struct e1000_hw *hw = &adapter->hw;
4294
4295         if (adapter->itr_setting & 3) {
4296                 if (adapter->num_rx_queues == 1)
4297                         igb_set_itr(adapter);
4298                 else
4299                         igb_update_ring_itr(rx_ring);
4300         }
4301
4302         if (!test_bit(__IGB_DOWN, &adapter->state)) {
4303                 if (adapter->msix_entries)
4304                         wr32(E1000_EIMS, rx_ring->eims_value);
4305                 else
4306                         igb_irq_enable(adapter);
4307         }
4308 }
4309
4310 /**
4311  * igb_poll - NAPI Rx polling callback
4312  * @napi: napi polling structure
4313  * @budget: count of how many packets we should handle
4314  **/
4315 static int igb_poll(struct napi_struct *napi, int budget)
4316 {
4317         struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
4318         int work_done = 0;
4319
4320 #ifdef CONFIG_IGB_DCA
4321         if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
4322                 igb_update_rx_dca(rx_ring);
4323 #endif
4324         igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
4325
4326         if (rx_ring->buddy) {
4327 #ifdef CONFIG_IGB_DCA
4328                 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
4329                         igb_update_tx_dca(rx_ring->buddy);
4330 #endif
4331                 if (!igb_clean_tx_irq(rx_ring->buddy))
4332                         work_done = budget;
4333         }
4334
4335         /* If not enough Rx work done, exit the polling mode */
4336         if (work_done < budget) {
4337                 napi_complete(napi);
4338                 igb_rx_irq_enable(rx_ring);
4339         }
4340
4341         return work_done;
4342 }
4343
4344 /**
4345  * igb_hwtstamp - utility function which checks for TX time stamp
4346  * @adapter: board private structure
4347  * @skb: packet that was just sent
4348  *
4349  * If we were asked to do hardware stamping and such a time stamp is
4350  * available, then it must have been for this skb here because we only
4351  * allow only one such packet into the queue.
4352  */
4353 static void igb_tx_hwtstamp(struct igb_adapter *adapter, struct sk_buff *skb)
4354 {
4355         union skb_shared_tx *shtx = skb_tx(skb);
4356         struct e1000_hw *hw = &adapter->hw;
4357
4358         if (unlikely(shtx->hardware)) {
4359                 u32 valid = rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID;
4360                 if (valid) {
4361                         u64 regval = rd32(E1000_TXSTMPL);
4362                         u64 ns;
4363                         struct skb_shared_hwtstamps shhwtstamps;
4364
4365                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
4366                         regval |= (u64)rd32(E1000_TXSTMPH) << 32;
4367                         ns = timecounter_cyc2time(&adapter->clock,
4368                                                   regval);
4369                         timecompare_update(&adapter->compare, ns);
4370                         shhwtstamps.hwtstamp = ns_to_ktime(ns);
4371                         shhwtstamps.syststamp =
4372                                 timecompare_transform(&adapter->compare, ns);
4373                         skb_tstamp_tx(skb, &shhwtstamps);
4374                 }
4375         }
4376 }
4377
4378 /**
4379  * igb_clean_tx_irq - Reclaim resources after transmit completes
4380  * @adapter: board private structure
4381  * returns true if ring is completely cleaned
4382  **/
4383 static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
4384 {
4385         struct igb_adapter *adapter = tx_ring->adapter;
4386         struct net_device *netdev = adapter->netdev;
4387         struct e1000_hw *hw = &adapter->hw;
4388         struct igb_buffer *buffer_info;
4389         struct sk_buff *skb;
4390         union e1000_adv_tx_desc *tx_desc, *eop_desc;
4391         unsigned int total_bytes = 0, total_packets = 0;
4392         unsigned int i, eop, count = 0;
4393         bool cleaned = false;
4394
4395         i = tx_ring->next_to_clean;
4396         eop = tx_ring->buffer_info[i].next_to_watch;
4397         eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4398
4399         while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
4400                (count < tx_ring->count)) {
4401                 for (cleaned = false; !cleaned; count++) {
4402                         tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
4403                         buffer_info = &tx_ring->buffer_info[i];
4404                         cleaned = (i == eop);
4405                         skb = buffer_info->skb;
4406
4407                         if (skb) {
4408                                 unsigned int segs, bytecount;
4409                                 /* gso_segs is currently only valid for tcp */
4410                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
4411                                 /* multiply data chunks by size of headers */
4412                                 bytecount = ((segs - 1) * skb_headlen(skb)) +
4413                                             skb->len;
4414                                 total_packets += segs;
4415                                 total_bytes += bytecount;
4416
4417                                 igb_tx_hwtstamp(adapter, skb);
4418                         }
4419
4420                         igb_unmap_and_free_tx_resource(adapter, buffer_info);
4421                         tx_desc->wb.status = 0;
4422
4423                         i++;
4424                         if (i == tx_ring->count)
4425                                 i = 0;
4426                 }
4427                 eop = tx_ring->buffer_info[i].next_to_watch;
4428                 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4429         }
4430
4431         tx_ring->next_to_clean = i;
4432
4433         if (unlikely(count &&
4434                      netif_carrier_ok(netdev) &&
4435                      igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
4436                 /* Make sure that anybody stopping the queue after this
4437                  * sees the new next_to_clean.
4438                  */
4439                 smp_mb();
4440                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
4441                     !(test_bit(__IGB_DOWN, &adapter->state))) {
4442                         netif_wake_subqueue(netdev, tx_ring->queue_index);
4443                         ++adapter->restart_queue;
4444                 }
4445         }
4446
4447         if (tx_ring->detect_tx_hung) {
4448                 /* Detect a transmit hang in hardware, this serializes the
4449                  * check with the clearing of time_stamp and movement of i */
4450                 tx_ring->detect_tx_hung = false;
4451                 if (tx_ring->buffer_info[i].time_stamp &&
4452                     time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
4453                                (adapter->tx_timeout_factor * HZ))
4454                     && !(rd32(E1000_STATUS) &
4455                          E1000_STATUS_TXOFF)) {
4456
4457                         /* detected Tx unit hang */
4458                         dev_err(&adapter->pdev->dev,
4459                                 "Detected Tx Unit Hang\n"
4460                                 "  Tx Queue             <%d>\n"
4461                                 "  TDH                  <%x>\n"
4462                                 "  TDT                  <%x>\n"
4463                                 "  next_to_use          <%x>\n"
4464                                 "  next_to_clean        <%x>\n"
4465                                 "buffer_info[next_to_clean]\n"
4466                                 "  time_stamp           <%lx>\n"
4467                                 "  next_to_watch        <%x>\n"
4468                                 "  jiffies              <%lx>\n"
4469                                 "  desc.status          <%x>\n",
4470                                 tx_ring->queue_index,
4471                                 readl(adapter->hw.hw_addr + tx_ring->head),
4472                                 readl(adapter->hw.hw_addr + tx_ring->tail),
4473                                 tx_ring->next_to_use,
4474                                 tx_ring->next_to_clean,
4475                                 tx_ring->buffer_info[i].time_stamp,
4476                                 eop,
4477                                 jiffies,
4478                                 eop_desc->wb.status);
4479                         netif_stop_subqueue(netdev, tx_ring->queue_index);
4480                 }
4481         }
4482         tx_ring->total_bytes += total_bytes;
4483         tx_ring->total_packets += total_packets;
4484         tx_ring->tx_stats.bytes += total_bytes;
4485         tx_ring->tx_stats.packets += total_packets;
4486         adapter->net_stats.tx_bytes += total_bytes;
4487         adapter->net_stats.tx_packets += total_packets;
4488         return (count < tx_ring->count);
4489 }
4490
4491 /**
4492  * igb_receive_skb - helper function to handle rx indications
4493  * @ring: pointer to receive ring receving this packet
4494  * @status: descriptor status field as written by hardware
4495  * @rx_desc: receive descriptor containing vlan and type information.
4496  * @skb: pointer to sk_buff to be indicated to stack
4497  **/
4498 static void igb_receive_skb(struct igb_ring *ring, u8 status,
4499                             union e1000_adv_rx_desc * rx_desc,
4500                             struct sk_buff *skb)
4501 {
4502         struct igb_adapter * adapter = ring->adapter;
4503         bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
4504
4505         skb_record_rx_queue(skb, ring->queue_index);
4506         if (vlan_extracted)
4507                 vlan_gro_receive(&ring->napi, adapter->vlgrp,
4508                                  le16_to_cpu(rx_desc->wb.upper.vlan),
4509                                  skb);
4510         else
4511                 napi_gro_receive(&ring->napi, skb);
4512 }
4513
4514 static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
4515                                        u32 status_err, struct sk_buff *skb)
4516 {
4517         skb->ip_summed = CHECKSUM_NONE;
4518
4519         /* Ignore Checksum bit is set or checksum is disabled through ethtool */
4520         if ((status_err & E1000_RXD_STAT_IXSM) ||
4521             (adapter->flags & IGB_FLAG_RX_CSUM_DISABLED))
4522                 return;
4523         /* TCP/UDP checksum error bit is set */
4524         if (status_err &
4525             (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
4526                 /*
4527                  * work around errata with sctp packets where the TCPE aka
4528                  * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
4529                  * packets, (aka let the stack check the crc32c)
4530                  */
4531                 if (!((adapter->hw.mac.type == e1000_82576) &&
4532                       (skb->len == 60)))
4533                         adapter->hw_csum_err++;
4534                 /* let the stack verify checksum errors */
4535                 return;
4536         }
4537         /* It must be a TCP or UDP packet with a valid checksum */
4538         if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
4539                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4540
4541         dev_dbg(&adapter->pdev->dev, "cksum success: bits %08X\n", status_err);
4542         adapter->hw_csum_good++;
4543 }
4544
4545 static inline u16 igb_get_hlen(struct igb_adapter *adapter,
4546                                union e1000_adv_rx_desc *rx_desc)
4547 {
4548         /* HW will not DMA in data larger than the given buffer, even if it
4549          * parses the (NFS, of course) header to be larger.  In that case, it
4550          * fills the header buffer and spills the rest into the page.
4551          */
4552         u16 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
4553                    E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
4554         if (hlen > adapter->rx_ps_hdr_size)
4555                 hlen = adapter->rx_ps_hdr_size;
4556         return hlen;
4557 }
4558
4559 static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
4560                                  int *work_done, int budget)
4561 {
4562         struct igb_adapter *adapter = rx_ring->adapter;
4563         struct net_device *netdev = adapter->netdev;
4564         struct e1000_hw *hw = &adapter->hw;
4565         struct pci_dev *pdev = adapter->pdev;
4566         union e1000_adv_rx_desc *rx_desc , *next_rxd;
4567         struct igb_buffer *buffer_info , *next_buffer;
4568         struct sk_buff *skb;
4569         bool cleaned = false;
4570         int cleaned_count = 0;
4571         unsigned int total_bytes = 0, total_packets = 0;
4572         unsigned int i;
4573         u32 staterr;
4574         u16 length;
4575
4576         i = rx_ring->next_to_clean;
4577         buffer_info = &rx_ring->buffer_info[i];
4578         rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4579         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4580
4581         while (staterr & E1000_RXD_STAT_DD) {
4582                 if (*work_done >= budget)
4583                         break;
4584                 (*work_done)++;
4585
4586                 skb = buffer_info->skb;
4587                 prefetch(skb->data - NET_IP_ALIGN);
4588                 buffer_info->skb = NULL;
4589
4590                 i++;
4591                 if (i == rx_ring->count)
4592                         i = 0;
4593                 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
4594                 prefetch(next_rxd);
4595                 next_buffer = &rx_ring->buffer_info[i];
4596
4597                 length = le16_to_cpu(rx_desc->wb.upper.length);
4598                 cleaned = true;
4599                 cleaned_count++;
4600
4601                 /* this is the fast path for the non-packet split case */
4602                 if (!adapter->rx_ps_hdr_size) {
4603                         pci_unmap_single(pdev, buffer_info->dma,
4604                                          adapter->rx_buffer_len,
4605                                          PCI_DMA_FROMDEVICE);
4606                         buffer_info->dma = 0;
4607                         skb_put(skb, length);
4608                         goto send_up;
4609                 }
4610
4611                 if (buffer_info->dma) {
4612                         u16 hlen = igb_get_hlen(adapter, rx_desc);
4613                         pci_unmap_single(pdev, buffer_info->dma,
4614                                          adapter->rx_ps_hdr_size,
4615                                          PCI_DMA_FROMDEVICE);
4616                         buffer_info->dma = 0;
4617                         skb_put(skb, hlen);
4618                 }
4619
4620                 if (length) {
4621                         pci_unmap_page(pdev, buffer_info->page_dma,
4622                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
4623                         buffer_info->page_dma = 0;
4624
4625                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
4626                                                 buffer_info->page,
4627                                                 buffer_info->page_offset,
4628                                                 length);
4629
4630                         if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
4631                             (page_count(buffer_info->page) != 1))
4632                                 buffer_info->page = NULL;
4633                         else
4634                                 get_page(buffer_info->page);
4635
4636                         skb->len += length;
4637                         skb->data_len += length;
4638
4639                         skb->truesize += length;
4640                 }
4641
4642                 if (!(staterr & E1000_RXD_STAT_EOP)) {
4643                         buffer_info->skb = next_buffer->skb;
4644                         buffer_info->dma = next_buffer->dma;
4645                         next_buffer->skb = skb;
4646                         next_buffer->dma = 0;
4647                         goto next_desc;
4648                 }
4649 send_up:
4650                 /*
4651                  * If this bit is set, then the RX registers contain
4652                  * the time stamp. No other packet will be time
4653                  * stamped until we read these registers, so read the
4654                  * registers to make them available again. Because
4655                  * only one packet can be time stamped at a time, we
4656                  * know that the register values must belong to this
4657                  * one here and therefore we don't need to compare
4658                  * any of the additional attributes stored for it.
4659                  *
4660                  * If nothing went wrong, then it should have a
4661                  * skb_shared_tx that we can turn into a
4662                  * skb_shared_hwtstamps.
4663                  *
4664                  * TODO: can time stamping be triggered (thus locking
4665                  * the registers) without the packet reaching this point
4666                  * here? In that case RX time stamping would get stuck.
4667                  *
4668                  * TODO: in "time stamp all packets" mode this bit is
4669                  * not set. Need a global flag for this mode and then
4670                  * always read the registers. Cannot be done without
4671                  * a race condition.
4672                  */
4673                 if (unlikely(staterr & E1000_RXD_STAT_TS)) {
4674                         u64 regval;
4675                         u64 ns;
4676                         struct skb_shared_hwtstamps *shhwtstamps =
4677                                 skb_hwtstamps(skb);
4678
4679                         WARN(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID),
4680                              "igb: no RX time stamp available for time stamped packet");
4681                         regval = rd32(E1000_RXSTMPL);
4682                         regval |= (u64)rd32(E1000_RXSTMPH) << 32;
4683                         ns = timecounter_cyc2time(&adapter->clock, regval);
4684                         timecompare_update(&adapter->compare, ns);
4685                         memset(shhwtstamps, 0, sizeof(*shhwtstamps));
4686                         shhwtstamps->hwtstamp = ns_to_ktime(ns);
4687                         shhwtstamps->syststamp =
4688                                 timecompare_transform(&adapter->compare, ns);
4689                 }
4690
4691                 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
4692                         dev_kfree_skb_irq(skb);
4693                         goto next_desc;
4694                 }
4695
4696                 total_bytes += skb->len;
4697                 total_packets++;
4698
4699                 igb_rx_checksum_adv(adapter, staterr, skb);
4700
4701                 skb->protocol = eth_type_trans(skb, netdev);
4702
4703                 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
4704
4705 next_desc:
4706                 rx_desc->wb.upper.status_error = 0;
4707
4708                 /* return some buffers to hardware, one at a time is too slow */
4709                 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
4710                         igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
4711                         cleaned_count = 0;
4712                 }
4713
4714                 /* use prefetched values */
4715                 rx_desc = next_rxd;
4716                 buffer_info = next_buffer;
4717                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4718         }
4719
4720         rx_ring->next_to_clean = i;
4721         cleaned_count = igb_desc_unused(rx_ring);
4722
4723         if (cleaned_count)
4724                 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
4725
4726         rx_ring->total_packets += total_packets;
4727         rx_ring->total_bytes += total_bytes;
4728         rx_ring->rx_stats.packets += total_packets;
4729         rx_ring->rx_stats.bytes += total_bytes;
4730         adapter->net_stats.rx_bytes += total_bytes;
4731         adapter->net_stats.rx_packets += total_packets;
4732         return cleaned;
4733 }
4734
4735 /**
4736  * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
4737  * @adapter: address of board private structure
4738  **/
4739 static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
4740                                      int cleaned_count)
4741 {
4742         struct igb_adapter *adapter = rx_ring->adapter;
4743         struct net_device *netdev = adapter->netdev;
4744         struct pci_dev *pdev = adapter->pdev;
4745         union e1000_adv_rx_desc *rx_desc;
4746         struct igb_buffer *buffer_info;
4747         struct sk_buff *skb;
4748         unsigned int i;
4749         int bufsz;
4750
4751         i = rx_ring->next_to_use;
4752         buffer_info = &rx_ring->buffer_info[i];
4753
4754         if (adapter->rx_ps_hdr_size)
4755                 bufsz = adapter->rx_ps_hdr_size;
4756         else
4757                 bufsz = adapter->rx_buffer_len;
4758
4759         while (cleaned_count--) {
4760                 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4761
4762                 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
4763                         if (!buffer_info->page) {
4764                                 buffer_info->page = alloc_page(GFP_ATOMIC);
4765                                 if (!buffer_info->page) {
4766                                         adapter->alloc_rx_buff_failed++;
4767                                         goto no_buffers;
4768                                 }
4769                                 buffer_info->page_offset = 0;
4770                         } else {
4771                                 buffer_info->page_offset ^= PAGE_SIZE / 2;
4772                         }
4773                         buffer_info->page_dma =
4774                                 pci_map_page(pdev, buffer_info->page,
4775                                              buffer_info->page_offset,
4776                                              PAGE_SIZE / 2,
4777                                              PCI_DMA_FROMDEVICE);
4778                 }
4779
4780                 if (!buffer_info->skb) {
4781                         skb = netdev_alloc_skb(netdev, bufsz + NET_IP_ALIGN);
4782                         if (!skb) {
4783                                 adapter->alloc_rx_buff_failed++;
4784                                 goto no_buffers;
4785                         }
4786
4787                         /* Make buffer alignment 2 beyond a 16 byte boundary
4788                          * this will result in a 16 byte aligned IP header after
4789                          * the 14 byte MAC header is removed
4790                          */
4791                         skb_reserve(skb, NET_IP_ALIGN);
4792
4793                         buffer_info->skb = skb;
4794                         buffer_info->dma = pci_map_single(pdev, skb->data,
4795                                                           bufsz,
4796                                                           PCI_DMA_FROMDEVICE);
4797                 }
4798                 /* Refresh the desc even if buffer_addrs didn't change because
4799                  * each write-back erases this info. */
4800                 if (adapter->rx_ps_hdr_size) {
4801                         rx_desc->read.pkt_addr =
4802                              cpu_to_le64(buffer_info->page_dma);
4803                         rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4804                 } else {
4805                         rx_desc->read.pkt_addr =
4806                              cpu_to_le64(buffer_info->dma);
4807                         rx_desc->read.hdr_addr = 0;
4808                 }
4809
4810                 i++;
4811                 if (i == rx_ring->count)
4812                         i = 0;
4813                 buffer_info = &rx_ring->buffer_info[i];
4814         }
4815
4816 no_buffers:
4817         if (rx_ring->next_to_use != i) {
4818                 rx_ring->next_to_use = i;
4819                 if (i == 0)
4820                         i = (rx_ring->count - 1);
4821                 else
4822                         i--;
4823
4824                 /* Force memory writes to complete before letting h/w
4825                  * know there are new descriptors to fetch.  (Only
4826                  * applicable for weak-ordered memory model archs,
4827                  * such as IA-64). */
4828                 wmb();
4829                 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4830         }
4831 }
4832
4833 /**
4834  * igb_mii_ioctl -
4835  * @netdev:
4836  * @ifreq:
4837  * @cmd:
4838  **/
4839 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4840 {
4841         struct igb_adapter *adapter = netdev_priv(netdev);
4842         struct mii_ioctl_data *data = if_mii(ifr);
4843
4844         if (adapter->hw.phy.media_type != e1000_media_type_copper)
4845                 return -EOPNOTSUPP;
4846
4847         switch (cmd) {
4848         case SIOCGMIIPHY:
4849                 data->phy_id = adapter->hw.phy.addr;
4850                 break;
4851         case SIOCGMIIREG:
4852                 if (!capable(CAP_NET_ADMIN))
4853                         return -EPERM;
4854                 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4855                                      &data->val_out))
4856                         return -EIO;
4857                 break;
4858         case SIOCSMIIREG:
4859         default:
4860                 return -EOPNOTSUPP;
4861         }
4862         return 0;
4863 }
4864
4865 /**
4866  * igb_hwtstamp_ioctl - control hardware time stamping
4867  * @netdev:
4868  * @ifreq:
4869  * @cmd:
4870  *
4871  * Outgoing time stamping can be enabled and disabled. Play nice and
4872  * disable it when requested, although it shouldn't case any overhead
4873  * when no packet needs it. At most one packet in the queue may be
4874  * marked for time stamping, otherwise it would be impossible to tell
4875  * for sure to which packet the hardware time stamp belongs.
4876  *
4877  * Incoming time stamping has to be configured via the hardware
4878  * filters. Not all combinations are supported, in particular event
4879  * type has to be specified. Matching the kind of event packet is
4880  * not supported, with the exception of "all V2 events regardless of
4881  * level 2 or 4".
4882  *
4883  **/
4884 static int igb_hwtstamp_ioctl(struct net_device *netdev,
4885                               struct ifreq *ifr, int cmd)
4886 {
4887         struct igb_adapter *adapter = netdev_priv(netdev);
4888         struct e1000_hw *hw = &adapter->hw;
4889         struct hwtstamp_config config;
4890         u32 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4891         u32 tsync_rx_ctl_bit = E1000_TSYNCRXCTL_ENABLED;
4892         u32 tsync_rx_ctl_type = 0;
4893         u32 tsync_rx_cfg = 0;
4894         int is_l4 = 0;
4895         int is_l2 = 0;
4896         short port = 319; /* PTP */
4897         u32 regval;
4898
4899         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4900                 return -EFAULT;
4901
4902         /* reserved for future extensions */
4903         if (config.flags)
4904                 return -EINVAL;
4905
4906         switch (config.tx_type) {
4907         case HWTSTAMP_TX_OFF:
4908                 tsync_tx_ctl_bit = 0;
4909                 break;
4910         case HWTSTAMP_TX_ON:
4911                 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4912                 break;
4913         default:
4914                 return -ERANGE;
4915         }
4916
4917         switch (config.rx_filter) {
4918         case HWTSTAMP_FILTER_NONE:
4919                 tsync_rx_ctl_bit = 0;
4920                 break;
4921         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4922         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4923         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4924         case HWTSTAMP_FILTER_ALL:
4925                 /*
4926                  * register TSYNCRXCFG must be set, therefore it is not
4927                  * possible to time stamp both Sync and Delay_Req messages
4928                  * => fall back to time stamping all packets
4929                  */
4930                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_ALL;
4931                 config.rx_filter = HWTSTAMP_FILTER_ALL;
4932                 break;
4933         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4934                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4935                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
4936                 is_l4 = 1;
4937                 break;
4938         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4939                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4940                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
4941                 is_l4 = 1;
4942                 break;
4943         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4944         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4945                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4946                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
4947                 is_l2 = 1;
4948                 is_l4 = 1;
4949                 config.rx_filter = HWTSTAMP_FILTER_SOME;
4950                 break;
4951         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4952         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4953                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4954                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
4955                 is_l2 = 1;
4956                 is_l4 = 1;
4957                 config.rx_filter = HWTSTAMP_FILTER_SOME;
4958                 break;
4959         case HWTSTAMP_FILTER_PTP_V2_EVENT:
4960         case HWTSTAMP_FILTER_PTP_V2_SYNC:
4961         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4962                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_EVENT_V2;
4963                 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
4964                 is_l2 = 1;
4965                 break;
4966         default:
4967                 return -ERANGE;
4968         }
4969
4970         /* enable/disable TX */
4971         regval = rd32(E1000_TSYNCTXCTL);
4972         regval = (regval & ~E1000_TSYNCTXCTL_ENABLED) | tsync_tx_ctl_bit;
4973         wr32(E1000_TSYNCTXCTL, regval);
4974
4975         /* enable/disable RX, define which PTP packets are time stamped */
4976         regval = rd32(E1000_TSYNCRXCTL);
4977         regval = (regval & ~E1000_TSYNCRXCTL_ENABLED) | tsync_rx_ctl_bit;
4978         regval = (regval & ~0xE) | tsync_rx_ctl_type;
4979         wr32(E1000_TSYNCRXCTL, regval);
4980         wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
4981
4982         /*
4983          * Ethertype Filter Queue Filter[0][15:0] = 0x88F7
4984          *                                          (Ethertype to filter on)
4985          * Ethertype Filter Queue Filter[0][26] = 0x1 (Enable filter)
4986          * Ethertype Filter Queue Filter[0][30] = 0x1 (Enable Timestamping)
4987          */
4988         wr32(E1000_ETQF0, is_l2 ? 0x440088f7 : 0);
4989
4990         /* L4 Queue Filter[0]: only filter by source and destination port */
4991         wr32(E1000_SPQF0, htons(port));
4992         wr32(E1000_IMIREXT(0), is_l4 ?
4993              ((1<<12) | (1<<19) /* bypass size and control flags */) : 0);
4994         wr32(E1000_IMIR(0), is_l4 ?
4995              (htons(port)
4996               | (0<<16) /* immediate interrupt disabled */
4997               | 0 /* (1<<17) bit cleared: do not bypass
4998                      destination port check */)
4999                 : 0);
5000         wr32(E1000_FTQF0, is_l4 ?
5001              (0x11 /* UDP */
5002               | (1<<15) /* VF not compared */
5003               | (1<<27) /* Enable Timestamping */
5004               | (7<<28) /* only source port filter enabled,
5005                            source/target address and protocol
5006                            masked */)
5007              : ((1<<15) | (15<<28) /* all mask bits set = filter not
5008                                       enabled */));
5009
5010         wrfl();
5011
5012         adapter->hwtstamp_config = config;
5013
5014         /* clear TX/RX time stamp registers, just to be sure */
5015         regval = rd32(E1000_TXSTMPH);
5016         regval = rd32(E1000_RXSTMPH);
5017
5018         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
5019                 -EFAULT : 0;
5020 }
5021
5022 /**
5023  * igb_ioctl -
5024  * @netdev:
5025  * @ifreq:
5026  * @cmd:
5027  **/
5028 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5029 {
5030         switch (cmd) {
5031         case SIOCGMIIPHY:
5032         case SIOCGMIIREG:
5033         case SIOCSMIIREG:
5034                 return igb_mii_ioctl(netdev, ifr, cmd);
5035         case SIOCSHWTSTAMP:
5036                 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
5037         default:
5038                 return -EOPNOTSUPP;
5039         }
5040 }
5041
5042 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5043 {
5044         struct igb_adapter *adapter = hw->back;
5045         u16 cap_offset;
5046
5047         cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5048         if (!cap_offset)
5049                 return -E1000_ERR_CONFIG;
5050
5051         pci_read_config_word(adapter->pdev, cap_offset + reg, value);
5052
5053         return 0;
5054 }
5055
5056 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5057 {
5058         struct igb_adapter *adapter = hw->back;
5059         u16 cap_offset;
5060
5061         cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5062         if (!cap_offset)
5063                 return -E1000_ERR_CONFIG;
5064
5065         pci_write_config_word(adapter->pdev, cap_offset + reg, *value);
5066
5067         return 0;
5068 }
5069
5070 static void igb_vlan_rx_register(struct net_device *netdev,
5071                                  struct vlan_group *grp)
5072 {
5073         struct igb_adapter *adapter = netdev_priv(netdev);
5074         struct e1000_hw *hw = &adapter->hw;
5075         u32 ctrl, rctl;
5076
5077         igb_irq_disable(adapter);
5078         adapter->vlgrp = grp;
5079
5080         if (grp) {
5081                 /* enable VLAN tag insert/strip */
5082                 ctrl = rd32(E1000_CTRL);
5083                 ctrl |= E1000_CTRL_VME;
5084                 wr32(E1000_CTRL, ctrl);
5085
5086                 /* enable VLAN receive filtering */
5087                 rctl = rd32(E1000_RCTL);
5088                 rctl &= ~E1000_RCTL_CFIEN;
5089                 wr32(E1000_RCTL, rctl);
5090                 igb_update_mng_vlan(adapter);
5091         } else {
5092                 /* disable VLAN tag insert/strip */
5093                 ctrl = rd32(E1000_CTRL);
5094                 ctrl &= ~E1000_CTRL_VME;
5095                 wr32(E1000_CTRL, ctrl);
5096
5097                 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
5098                         igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
5099                         adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
5100                 }
5101         }
5102
5103         igb_rlpml_set(adapter);
5104
5105         if (!test_bit(__IGB_DOWN, &adapter->state))
5106                 igb_irq_enable(adapter);
5107 }
5108
5109 static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
5110 {
5111         struct igb_adapter *adapter = netdev_priv(netdev);
5112         struct e1000_hw *hw = &adapter->hw;
5113         int pf_id = adapter->vfs_allocated_count;
5114
5115         if ((hw->mng_cookie.status &
5116              E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5117             (vid == adapter->mng_vlan_id))
5118                 return;
5119
5120         /* add vid to vlvf if sr-iov is enabled,
5121          * if that fails add directly to filter table */
5122         if (igb_vlvf_set(adapter, vid, true, pf_id))
5123                 igb_vfta_set(hw, vid, true);
5124
5125 }
5126
5127 static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
5128 {
5129         struct igb_adapter *adapter = netdev_priv(netdev);
5130         struct e1000_hw *hw = &adapter->hw;
5131         int pf_id = adapter->vfs_allocated_count;
5132
5133         igb_irq_disable(adapter);
5134         vlan_group_set_device(adapter->vlgrp, vid, NULL);
5135
5136         if (!test_bit(__IGB_DOWN, &adapter->state))
5137                 igb_irq_enable(adapter);
5138
5139         if ((adapter->hw.mng_cookie.status &
5140              E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5141             (vid == adapter->mng_vlan_id)) {
5142                 /* release control to f/w */
5143                 igb_release_hw_control(adapter);
5144                 return;
5145         }
5146
5147         /* remove vid from vlvf if sr-iov is enabled,
5148          * if not in vlvf remove from vfta */
5149         if (igb_vlvf_set(adapter, vid, false, pf_id))
5150                 igb_vfta_set(hw, vid, false);
5151 }
5152
5153 static void igb_restore_vlan(struct igb_adapter *adapter)
5154 {
5155         igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
5156
5157         if (adapter->vlgrp) {
5158                 u16 vid;
5159                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
5160                         if (!vlan_group_get_device(adapter->vlgrp, vid))
5161                                 continue;
5162                         igb_vlan_rx_add_vid(adapter->netdev, vid);
5163                 }
5164         }
5165 }
5166
5167 int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
5168 {
5169         struct e1000_mac_info *mac = &adapter->hw.mac;
5170
5171         mac->autoneg = 0;
5172
5173         switch (spddplx) {
5174         case SPEED_10 + DUPLEX_HALF:
5175                 mac->forced_speed_duplex = ADVERTISE_10_HALF;
5176                 break;
5177         case SPEED_10 + DUPLEX_FULL:
5178                 mac->forced_speed_duplex = ADVERTISE_10_FULL;
5179                 break;
5180         case SPEED_100 + DUPLEX_HALF:
5181                 mac->forced_speed_duplex = ADVERTISE_100_HALF;
5182                 break;
5183         case SPEED_100 + DUPLEX_FULL:
5184                 mac->forced_speed_duplex = ADVERTISE_100_FULL;
5185                 break;
5186         case SPEED_1000 + DUPLEX_FULL:
5187                 mac->autoneg = 1;
5188                 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
5189                 break;
5190         case SPEED_1000 + DUPLEX_HALF: /* not supported */
5191         default:
5192                 dev_err(&adapter->pdev->dev,
5193                         "Unsupported Speed/Duplex configuration\n");
5194                 return -EINVAL;
5195         }
5196         return 0;
5197 }
5198
5199 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake)
5200 {
5201         struct net_device *netdev = pci_get_drvdata(pdev);
5202         struct igb_adapter *adapter = netdev_priv(netdev);
5203         struct e1000_hw *hw = &adapter->hw;
5204         u32 ctrl, rctl, status;
5205         u32 wufc = adapter->wol;
5206 #ifdef CONFIG_PM
5207         int retval = 0;
5208 #endif
5209
5210         netif_device_detach(netdev);
5211
5212         if (netif_running(netdev))
5213                 igb_close(netdev);
5214
5215         igb_reset_interrupt_capability(adapter);
5216
5217         igb_free_queues(adapter);
5218
5219 #ifdef CONFIG_PM
5220         retval = pci_save_state(pdev);
5221         if (retval)
5222                 return retval;
5223 #endif
5224
5225         status = rd32(E1000_STATUS);
5226         if (status & E1000_STATUS_LU)
5227                 wufc &= ~E1000_WUFC_LNKC;
5228
5229         if (wufc) {
5230                 igb_setup_rctl(adapter);
5231                 igb_set_multi(netdev);
5232
5233                 /* turn on all-multi mode if wake on multicast is enabled */
5234                 if (wufc & E1000_WUFC_MC) {
5235                         rctl = rd32(E1000_RCTL);
5236                         rctl |= E1000_RCTL_MPE;
5237                         wr32(E1000_RCTL, rctl);
5238                 }
5239
5240                 ctrl = rd32(E1000_CTRL);
5241                 /* advertise wake from D3Cold */
5242                 #define E1000_CTRL_ADVD3WUC 0x00100000
5243                 /* phy power management enable */
5244                 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5245                 ctrl |= E1000_CTRL_ADVD3WUC;
5246                 wr32(E1000_CTRL, ctrl);
5247
5248                 /* Allow time for pending master requests to run */
5249                 igb_disable_pcie_master(&adapter->hw);
5250
5251                 wr32(E1000_WUC, E1000_WUC_PME_EN);
5252                 wr32(E1000_WUFC, wufc);
5253         } else {
5254                 wr32(E1000_WUC, 0);
5255                 wr32(E1000_WUFC, 0);
5256         }
5257
5258         *enable_wake = wufc || adapter->en_mng_pt;
5259         if (!*enable_wake)
5260                 igb_shutdown_fiber_serdes_link_82575(hw);
5261
5262         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
5263          * would have already happened in close and is redundant. */
5264         igb_release_hw_control(adapter);
5265
5266         pci_disable_device(pdev);
5267
5268         return 0;
5269 }
5270
5271 #ifdef CONFIG_PM
5272 static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
5273 {
5274         int retval;
5275         bool wake;
5276
5277         retval = __igb_shutdown(pdev, &wake);
5278         if (retval)
5279                 return retval;
5280
5281         if (wake) {
5282                 pci_prepare_to_sleep(pdev);
5283         } else {
5284                 pci_wake_from_d3(pdev, false);
5285                 pci_set_power_state(pdev, PCI_D3hot);
5286         }
5287
5288         return 0;
5289 }
5290
5291 static int igb_resume(struct pci_dev *pdev)
5292 {
5293         struct net_device *netdev = pci_get_drvdata(pdev);
5294         struct igb_adapter *adapter = netdev_priv(netdev);
5295         struct e1000_hw *hw = &adapter->hw;
5296         u32 err;
5297
5298         pci_set_power_state(pdev, PCI_D0);
5299         pci_restore_state(pdev);
5300
5301         err = pci_enable_device_mem(pdev);
5302         if (err) {
5303                 dev_err(&pdev->dev,
5304                         "igb: Cannot enable PCI device from suspend\n");
5305                 return err;
5306         }
5307         pci_set_master(pdev);
5308
5309         pci_enable_wake(pdev, PCI_D3hot, 0);
5310         pci_enable_wake(pdev, PCI_D3cold, 0);
5311
5312         igb_set_interrupt_capability(adapter);
5313
5314         if (igb_alloc_queues(adapter)) {
5315                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
5316                 return -ENOMEM;
5317         }
5318
5319         /* e1000_power_up_phy(adapter); */
5320
5321         igb_reset(adapter);
5322
5323         /* let the f/w know that the h/w is now under the control of the
5324          * driver. */
5325         igb_get_hw_control(adapter);
5326
5327         wr32(E1000_WUS, ~0);
5328
5329         if (netif_running(netdev)) {
5330                 err = igb_open(netdev);
5331                 if (err)
5332                         return err;
5333         }
5334
5335         netif_device_attach(netdev);
5336
5337         return 0;
5338 }
5339 #endif
5340
5341 static void igb_shutdown(struct pci_dev *pdev)
5342 {
5343         bool wake;
5344
5345         __igb_shutdown(pdev, &wake);
5346
5347         if (system_state == SYSTEM_POWER_OFF) {
5348                 pci_wake_from_d3(pdev, wake);
5349                 pci_set_power_state(pdev, PCI_D3hot);
5350         }
5351 }
5352
5353 #ifdef CONFIG_NET_POLL_CONTROLLER
5354 /*
5355  * Polling 'interrupt' - used by things like netconsole to send skbs
5356  * without having to re-enable interrupts. It's not called while
5357  * the interrupt routine is executing.
5358  */
5359 static void igb_netpoll(struct net_device *netdev)
5360 {
5361         struct igb_adapter *adapter = netdev_priv(netdev);
5362         struct e1000_hw *hw = &adapter->hw;
5363         int i;
5364
5365         if (!adapter->msix_entries) {
5366                 igb_irq_disable(adapter);
5367                 napi_schedule(&adapter->rx_ring[0].napi);
5368                 return;
5369         }
5370
5371         for (i = 0; i < adapter->num_tx_queues; i++) {
5372                 struct igb_ring *tx_ring = &adapter->tx_ring[i];
5373                 wr32(E1000_EIMC, tx_ring->eims_value);
5374                 igb_clean_tx_irq(tx_ring);
5375                 wr32(E1000_EIMS, tx_ring->eims_value);
5376         }
5377
5378         for (i = 0; i < adapter->num_rx_queues; i++) {
5379                 struct igb_ring *rx_ring = &adapter->rx_ring[i];
5380                 wr32(E1000_EIMC, rx_ring->eims_value);
5381                 napi_schedule(&rx_ring->napi);
5382         }
5383 }
5384 #endif /* CONFIG_NET_POLL_CONTROLLER */
5385
5386 /**
5387  * igb_io_error_detected - called when PCI error is detected
5388  * @pdev: Pointer to PCI device
5389  * @state: The current pci connection state
5390  *
5391  * This function is called after a PCI bus error affecting
5392  * this device has been detected.
5393  */
5394 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
5395                                               pci_channel_state_t state)
5396 {
5397         struct net_device *netdev = pci_get_drvdata(pdev);
5398         struct igb_adapter *adapter = netdev_priv(netdev);
5399
5400         netif_device_detach(netdev);
5401
5402         if (state == pci_channel_io_perm_failure)
5403                 return PCI_ERS_RESULT_DISCONNECT;
5404
5405         if (netif_running(netdev))
5406                 igb_down(adapter);
5407         pci_disable_device(pdev);
5408
5409         /* Request a slot slot reset. */
5410         return PCI_ERS_RESULT_NEED_RESET;
5411 }
5412
5413 /**
5414  * igb_io_slot_reset - called after the pci bus has been reset.
5415  * @pdev: Pointer to PCI device
5416  *
5417  * Restart the card from scratch, as if from a cold-boot. Implementation
5418  * resembles the first-half of the igb_resume routine.
5419  */
5420 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
5421 {
5422         struct net_device *netdev = pci_get_drvdata(pdev);
5423         struct igb_adapter *adapter = netdev_priv(netdev);
5424         struct e1000_hw *hw = &adapter->hw;
5425         pci_ers_result_t result;
5426         int err;
5427
5428         if (pci_enable_device_mem(pdev)) {
5429                 dev_err(&pdev->dev,
5430                         "Cannot re-enable PCI device after reset.\n");
5431                 result = PCI_ERS_RESULT_DISCONNECT;
5432         } else {
5433                 pci_set_master(pdev);
5434                 pci_restore_state(pdev);
5435
5436                 pci_enable_wake(pdev, PCI_D3hot, 0);
5437                 pci_enable_wake(pdev, PCI_D3cold, 0);
5438
5439                 igb_reset(adapter);
5440                 wr32(E1000_WUS, ~0);
5441                 result = PCI_ERS_RESULT_RECOVERED;
5442         }
5443
5444         err = pci_cleanup_aer_uncorrect_error_status(pdev);
5445         if (err) {
5446                 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
5447                         "failed 0x%0x\n", err);
5448                 /* non-fatal, continue */
5449         }
5450
5451         return result;
5452 }
5453
5454 /**
5455  * igb_io_resume - called when traffic can start flowing again.
5456  * @pdev: Pointer to PCI device
5457  *
5458  * This callback is called when the error recovery driver tells us that
5459  * its OK to resume normal operation. Implementation resembles the
5460  * second-half of the igb_resume routine.
5461  */
5462 static void igb_io_resume(struct pci_dev *pdev)
5463 {
5464         struct net_device *netdev = pci_get_drvdata(pdev);
5465         struct igb_adapter *adapter = netdev_priv(netdev);
5466
5467         if (netif_running(netdev)) {
5468                 if (igb_up(adapter)) {
5469                         dev_err(&pdev->dev, "igb_up failed after reset\n");
5470                         return;
5471                 }
5472         }
5473
5474         netif_device_attach(netdev);
5475
5476         /* let the f/w know that the h/w is now under the control of the
5477          * driver. */
5478         igb_get_hw_control(adapter);
5479 }
5480
5481 static int igb_set_vf_mac(struct igb_adapter *adapter,
5482                           int vf, unsigned char *mac_addr)
5483 {
5484         struct e1000_hw *hw = &adapter->hw;
5485         int rar_entry = vf + 1; /* VF MAC addresses start at entry 1 */
5486
5487         igb_rar_set(hw, mac_addr, rar_entry);
5488
5489         memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
5490
5491         igb_set_rah_pool(hw, vf, rar_entry);
5492
5493         return 0;
5494 }
5495
5496 static void igb_vmm_control(struct igb_adapter *adapter)
5497 {
5498         struct e1000_hw *hw = &adapter->hw;
5499         u32 reg_data;
5500
5501         if (!adapter->vfs_allocated_count)
5502                 return;
5503
5504         /* VF's need PF reset indication before they
5505          * can send/receive mail */
5506         reg_data = rd32(E1000_CTRL_EXT);
5507         reg_data |= E1000_CTRL_EXT_PFRSTD;
5508         wr32(E1000_CTRL_EXT, reg_data);
5509
5510         igb_vmdq_set_loopback_pf(hw, true);
5511         igb_vmdq_set_replication_pf(hw, true);
5512 }
5513
5514 /* igb_main.c */