1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/module.h>
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/vmalloc.h>
32 #include <linux/pagemap.h>
33 #include <linux/netdevice.h>
34 #include <linux/ipv6.h>
35 #include <net/checksum.h>
36 #include <net/ip6_checksum.h>
37 #include <linux/net_tstamp.h>
38 #include <linux/mii.h>
39 #include <linux/ethtool.h>
40 #include <linux/if_vlan.h>
41 #include <linux/pci.h>
42 #include <linux/pci-aspm.h>
43 #include <linux/delay.h>
44 #include <linux/interrupt.h>
45 #include <linux/if_ether.h>
46 #include <linux/aer.h>
48 #include <linux/dca.h>
52 #define DRV_VERSION "2.1.0-k2"
53 char igb_driver_name[] = "igb";
54 char igb_driver_version[] = DRV_VERSION;
55 static const char igb_driver_string[] =
56 "Intel(R) Gigabit Ethernet Network Driver";
57 static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
59 static const struct e1000_info *igb_info_tbl[] = {
60 [board_82575] = &e1000_82575_info,
63 static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
74 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
79 /* required last entry */
83 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
85 void igb_reset(struct igb_adapter *);
86 static int igb_setup_all_tx_resources(struct igb_adapter *);
87 static int igb_setup_all_rx_resources(struct igb_adapter *);
88 static void igb_free_all_tx_resources(struct igb_adapter *);
89 static void igb_free_all_rx_resources(struct igb_adapter *);
90 static void igb_setup_mrqc(struct igb_adapter *);
91 void igb_update_stats(struct igb_adapter *);
92 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
93 static void __devexit igb_remove(struct pci_dev *pdev);
94 static int igb_sw_init(struct igb_adapter *);
95 static int igb_open(struct net_device *);
96 static int igb_close(struct net_device *);
97 static void igb_configure_tx(struct igb_adapter *);
98 static void igb_configure_rx(struct igb_adapter *);
99 static void igb_clean_all_tx_rings(struct igb_adapter *);
100 static void igb_clean_all_rx_rings(struct igb_adapter *);
101 static void igb_clean_tx_ring(struct igb_ring *);
102 static void igb_clean_rx_ring(struct igb_ring *);
103 static void igb_set_rx_mode(struct net_device *);
104 static void igb_update_phy_info(unsigned long);
105 static void igb_watchdog(unsigned long);
106 static void igb_watchdog_task(struct work_struct *);
107 static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
108 static struct net_device_stats *igb_get_stats(struct net_device *);
109 static int igb_change_mtu(struct net_device *, int);
110 static int igb_set_mac(struct net_device *, void *);
111 static void igb_set_uta(struct igb_adapter *adapter);
112 static irqreturn_t igb_intr(int irq, void *);
113 static irqreturn_t igb_intr_msi(int irq, void *);
114 static irqreturn_t igb_msix_other(int irq, void *);
115 static irqreturn_t igb_msix_ring(int irq, void *);
116 #ifdef CONFIG_IGB_DCA
117 static void igb_update_dca(struct igb_q_vector *);
118 static void igb_setup_dca(struct igb_adapter *);
119 #endif /* CONFIG_IGB_DCA */
120 static bool igb_clean_tx_irq(struct igb_q_vector *);
121 static int igb_poll(struct napi_struct *, int);
122 static bool igb_clean_rx_irq_adv(struct igb_q_vector *, int *, int);
123 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
124 static void igb_tx_timeout(struct net_device *);
125 static void igb_reset_task(struct work_struct *);
126 static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
127 static void igb_vlan_rx_add_vid(struct net_device *, u16);
128 static void igb_vlan_rx_kill_vid(struct net_device *, u16);
129 static void igb_restore_vlan(struct igb_adapter *);
130 static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
131 static void igb_ping_all_vfs(struct igb_adapter *);
132 static void igb_msg_task(struct igb_adapter *);
133 static void igb_vmm_control(struct igb_adapter *);
134 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
135 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
136 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
137 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
138 int vf, u16 vlan, u8 qos);
139 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
140 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
141 struct ifla_vf_info *ivi);
144 static int igb_suspend(struct pci_dev *, pm_message_t);
145 static int igb_resume(struct pci_dev *);
147 static void igb_shutdown(struct pci_dev *);
148 #ifdef CONFIG_IGB_DCA
149 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
150 static struct notifier_block dca_notifier = {
151 .notifier_call = igb_notify_dca,
156 #ifdef CONFIG_NET_POLL_CONTROLLER
157 /* for netdump / net console */
158 static void igb_netpoll(struct net_device *);
160 #ifdef CONFIG_PCI_IOV
161 static unsigned int max_vfs = 0;
162 module_param(max_vfs, uint, 0);
163 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
164 "per physical function");
165 #endif /* CONFIG_PCI_IOV */
167 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
168 pci_channel_state_t);
169 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
170 static void igb_io_resume(struct pci_dev *);
172 static struct pci_error_handlers igb_err_handler = {
173 .error_detected = igb_io_error_detected,
174 .slot_reset = igb_io_slot_reset,
175 .resume = igb_io_resume,
179 static struct pci_driver igb_driver = {
180 .name = igb_driver_name,
181 .id_table = igb_pci_tbl,
183 .remove = __devexit_p(igb_remove),
185 /* Power Managment Hooks */
186 .suspend = igb_suspend,
187 .resume = igb_resume,
189 .shutdown = igb_shutdown,
190 .err_handler = &igb_err_handler
193 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
194 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
195 MODULE_LICENSE("GPL");
196 MODULE_VERSION(DRV_VERSION);
199 * igb_read_clock - read raw cycle counter (to be used by time counter)
201 static cycle_t igb_read_clock(const struct cyclecounter *tc)
203 struct igb_adapter *adapter =
204 container_of(tc, struct igb_adapter, cycles);
205 struct e1000_hw *hw = &adapter->hw;
210 * The timestamp latches on lowest register read. For the 82580
211 * the lowest register is SYSTIMR instead of SYSTIML. However we never
212 * adjusted TIMINCA so SYSTIMR will just read as all 0s so ignore it.
214 if (hw->mac.type == e1000_82580) {
215 stamp = rd32(E1000_SYSTIMR) >> 8;
216 shift = IGB_82580_TSYNC_SHIFT;
219 stamp |= (u64)rd32(E1000_SYSTIML) << shift;
220 stamp |= (u64)rd32(E1000_SYSTIMH) << (shift + 32);
226 * igb_get_hw_dev_name - return device name string
227 * used by hardware layer to print debugging information
229 char *igb_get_hw_dev_name(struct e1000_hw *hw)
231 struct igb_adapter *adapter = hw->back;
232 return adapter->netdev->name;
236 * igb_get_time_str - format current NIC and system time as string
238 static char *igb_get_time_str(struct igb_adapter *adapter,
241 cycle_t hw = adapter->cycles.read(&adapter->cycles);
242 struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock));
244 struct timespec delta;
245 getnstimeofday(&sys);
247 delta = timespec_sub(nic, sys);
250 "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
252 (long)nic.tv_sec, nic.tv_nsec,
253 (long)sys.tv_sec, sys.tv_nsec,
254 (long)delta.tv_sec, delta.tv_nsec);
261 * igb_init_module - Driver Registration Routine
263 * igb_init_module is the first routine called when the driver is
264 * loaded. All it does is register with the PCI subsystem.
266 static int __init igb_init_module(void)
269 printk(KERN_INFO "%s - version %s\n",
270 igb_driver_string, igb_driver_version);
272 printk(KERN_INFO "%s\n", igb_copyright);
274 #ifdef CONFIG_IGB_DCA
275 dca_register_notify(&dca_notifier);
277 ret = pci_register_driver(&igb_driver);
281 module_init(igb_init_module);
284 * igb_exit_module - Driver Exit Cleanup Routine
286 * igb_exit_module is called just before the driver is removed
289 static void __exit igb_exit_module(void)
291 #ifdef CONFIG_IGB_DCA
292 dca_unregister_notify(&dca_notifier);
294 pci_unregister_driver(&igb_driver);
297 module_exit(igb_exit_module);
299 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
301 * igb_cache_ring_register - Descriptor ring to register mapping
302 * @adapter: board private structure to initialize
304 * Once we know the feature-set enabled for the device, we'll cache
305 * the register offset the descriptor ring is assigned to.
307 static void igb_cache_ring_register(struct igb_adapter *adapter)
310 u32 rbase_offset = adapter->vfs_allocated_count;
312 switch (adapter->hw.mac.type) {
314 /* The queues are allocated for virtualization such that VF 0
315 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
316 * In order to avoid collision we start at the first free queue
317 * and continue consuming queues in the same sequence
319 if (adapter->vfs_allocated_count) {
320 for (; i < adapter->rss_queues; i++)
321 adapter->rx_ring[i].reg_idx = rbase_offset +
323 for (; j < adapter->rss_queues; j++)
324 adapter->tx_ring[j].reg_idx = rbase_offset +
330 for (; i < adapter->num_rx_queues; i++)
331 adapter->rx_ring[i].reg_idx = rbase_offset + i;
332 for (; j < adapter->num_tx_queues; j++)
333 adapter->tx_ring[j].reg_idx = rbase_offset + j;
338 static void igb_free_queues(struct igb_adapter *adapter)
340 kfree(adapter->tx_ring);
341 kfree(adapter->rx_ring);
343 adapter->tx_ring = NULL;
344 adapter->rx_ring = NULL;
346 adapter->num_rx_queues = 0;
347 adapter->num_tx_queues = 0;
351 * igb_alloc_queues - Allocate memory for all rings
352 * @adapter: board private structure to initialize
354 * We allocate one ring per queue at run-time since we don't know the
355 * number of queues at compile-time.
357 static int igb_alloc_queues(struct igb_adapter *adapter)
361 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
362 sizeof(struct igb_ring), GFP_KERNEL);
363 if (!adapter->tx_ring)
366 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
367 sizeof(struct igb_ring), GFP_KERNEL);
368 if (!adapter->rx_ring)
371 for (i = 0; i < adapter->num_tx_queues; i++) {
372 struct igb_ring *ring = &(adapter->tx_ring[i]);
373 ring->count = adapter->tx_ring_count;
374 ring->queue_index = i;
375 ring->pdev = adapter->pdev;
376 ring->netdev = adapter->netdev;
377 /* For 82575, context index must be unique per ring. */
378 if (adapter->hw.mac.type == e1000_82575)
379 ring->flags = IGB_RING_FLAG_TX_CTX_IDX;
382 for (i = 0; i < adapter->num_rx_queues; i++) {
383 struct igb_ring *ring = &(adapter->rx_ring[i]);
384 ring->count = adapter->rx_ring_count;
385 ring->queue_index = i;
386 ring->pdev = adapter->pdev;
387 ring->netdev = adapter->netdev;
388 ring->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
389 ring->flags = IGB_RING_FLAG_RX_CSUM; /* enable rx checksum */
390 /* set flag indicating ring supports SCTP checksum offload */
391 if (adapter->hw.mac.type >= e1000_82576)
392 ring->flags |= IGB_RING_FLAG_RX_SCTP_CSUM;
395 igb_cache_ring_register(adapter);
400 igb_free_queues(adapter);
405 #define IGB_N0_QUEUE -1
406 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
409 struct igb_adapter *adapter = q_vector->adapter;
410 struct e1000_hw *hw = &adapter->hw;
412 int rx_queue = IGB_N0_QUEUE;
413 int tx_queue = IGB_N0_QUEUE;
415 if (q_vector->rx_ring)
416 rx_queue = q_vector->rx_ring->reg_idx;
417 if (q_vector->tx_ring)
418 tx_queue = q_vector->tx_ring->reg_idx;
420 switch (hw->mac.type) {
422 /* The 82575 assigns vectors using a bitmask, which matches the
423 bitmask for the EICR/EIMS/EIMC registers. To assign one
424 or more queues to a vector, we write the appropriate bits
425 into the MSIXBM register for that vector. */
426 if (rx_queue > IGB_N0_QUEUE)
427 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
428 if (tx_queue > IGB_N0_QUEUE)
429 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
430 if (!adapter->msix_entries && msix_vector == 0)
431 msixbm |= E1000_EIMS_OTHER;
432 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
433 q_vector->eims_value = msixbm;
436 /* 82576 uses a table-based method for assigning vectors.
437 Each queue has a single entry in the table to which we write
438 a vector number along with a "valid" bit. Sadly, the layout
439 of the table is somewhat counterintuitive. */
440 if (rx_queue > IGB_N0_QUEUE) {
441 index = (rx_queue & 0x7);
442 ivar = array_rd32(E1000_IVAR0, index);
444 /* vector goes into low byte of register */
445 ivar = ivar & 0xFFFFFF00;
446 ivar |= msix_vector | E1000_IVAR_VALID;
448 /* vector goes into third byte of register */
449 ivar = ivar & 0xFF00FFFF;
450 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
452 array_wr32(E1000_IVAR0, index, ivar);
454 if (tx_queue > IGB_N0_QUEUE) {
455 index = (tx_queue & 0x7);
456 ivar = array_rd32(E1000_IVAR0, index);
458 /* vector goes into second byte of register */
459 ivar = ivar & 0xFFFF00FF;
460 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
462 /* vector goes into high byte of register */
463 ivar = ivar & 0x00FFFFFF;
464 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
466 array_wr32(E1000_IVAR0, index, ivar);
468 q_vector->eims_value = 1 << msix_vector;
471 /* 82580 uses the same table-based approach as 82576 but has fewer
472 entries as a result we carry over for queues greater than 4. */
473 if (rx_queue > IGB_N0_QUEUE) {
474 index = (rx_queue >> 1);
475 ivar = array_rd32(E1000_IVAR0, index);
476 if (rx_queue & 0x1) {
477 /* vector goes into third byte of register */
478 ivar = ivar & 0xFF00FFFF;
479 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
481 /* vector goes into low byte of register */
482 ivar = ivar & 0xFFFFFF00;
483 ivar |= msix_vector | E1000_IVAR_VALID;
485 array_wr32(E1000_IVAR0, index, ivar);
487 if (tx_queue > IGB_N0_QUEUE) {
488 index = (tx_queue >> 1);
489 ivar = array_rd32(E1000_IVAR0, index);
490 if (tx_queue & 0x1) {
491 /* vector goes into high byte of register */
492 ivar = ivar & 0x00FFFFFF;
493 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
495 /* vector goes into second byte of register */
496 ivar = ivar & 0xFFFF00FF;
497 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
499 array_wr32(E1000_IVAR0, index, ivar);
501 q_vector->eims_value = 1 << msix_vector;
510 * igb_configure_msix - Configure MSI-X hardware
512 * igb_configure_msix sets up the hardware to properly
513 * generate MSI-X interrupts.
515 static void igb_configure_msix(struct igb_adapter *adapter)
519 struct e1000_hw *hw = &adapter->hw;
521 adapter->eims_enable_mask = 0;
523 /* set vector for other causes, i.e. link changes */
524 switch (hw->mac.type) {
526 tmp = rd32(E1000_CTRL_EXT);
527 /* enable MSI-X PBA support*/
528 tmp |= E1000_CTRL_EXT_PBA_CLR;
530 /* Auto-Mask interrupts upon ICR read. */
531 tmp |= E1000_CTRL_EXT_EIAME;
532 tmp |= E1000_CTRL_EXT_IRCA;
534 wr32(E1000_CTRL_EXT, tmp);
536 /* enable msix_other interrupt */
537 array_wr32(E1000_MSIXBM(0), vector++,
539 adapter->eims_other = E1000_EIMS_OTHER;
545 /* Turn on MSI-X capability first, or our settings
546 * won't stick. And it will take days to debug. */
547 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
548 E1000_GPIE_PBA | E1000_GPIE_EIAME |
551 /* enable msix_other interrupt */
552 adapter->eims_other = 1 << vector;
553 tmp = (vector++ | E1000_IVAR_VALID) << 8;
555 wr32(E1000_IVAR_MISC, tmp);
558 /* do nothing, since nothing else supports MSI-X */
560 } /* switch (hw->mac.type) */
562 adapter->eims_enable_mask |= adapter->eims_other;
564 for (i = 0; i < adapter->num_q_vectors; i++) {
565 struct igb_q_vector *q_vector = adapter->q_vector[i];
566 igb_assign_vector(q_vector, vector++);
567 adapter->eims_enable_mask |= q_vector->eims_value;
574 * igb_request_msix - Initialize MSI-X interrupts
576 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
579 static int igb_request_msix(struct igb_adapter *adapter)
581 struct net_device *netdev = adapter->netdev;
582 struct e1000_hw *hw = &adapter->hw;
583 int i, err = 0, vector = 0;
585 err = request_irq(adapter->msix_entries[vector].vector,
586 igb_msix_other, 0, netdev->name, adapter);
591 for (i = 0; i < adapter->num_q_vectors; i++) {
592 struct igb_q_vector *q_vector = adapter->q_vector[i];
594 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
596 if (q_vector->rx_ring && q_vector->tx_ring)
597 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
598 q_vector->rx_ring->queue_index);
599 else if (q_vector->tx_ring)
600 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
601 q_vector->tx_ring->queue_index);
602 else if (q_vector->rx_ring)
603 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
604 q_vector->rx_ring->queue_index);
606 sprintf(q_vector->name, "%s-unused", netdev->name);
608 err = request_irq(adapter->msix_entries[vector].vector,
609 igb_msix_ring, 0, q_vector->name,
616 igb_configure_msix(adapter);
622 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
624 if (adapter->msix_entries) {
625 pci_disable_msix(adapter->pdev);
626 kfree(adapter->msix_entries);
627 adapter->msix_entries = NULL;
628 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
629 pci_disable_msi(adapter->pdev);
634 * igb_free_q_vectors - Free memory allocated for interrupt vectors
635 * @adapter: board private structure to initialize
637 * This function frees the memory allocated to the q_vectors. In addition if
638 * NAPI is enabled it will delete any references to the NAPI struct prior
639 * to freeing the q_vector.
641 static void igb_free_q_vectors(struct igb_adapter *adapter)
645 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
646 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
647 adapter->q_vector[v_idx] = NULL;
648 netif_napi_del(&q_vector->napi);
651 adapter->num_q_vectors = 0;
655 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
657 * This function resets the device so that it has 0 rx queues, tx queues, and
658 * MSI-X interrupts allocated.
660 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
662 igb_free_queues(adapter);
663 igb_free_q_vectors(adapter);
664 igb_reset_interrupt_capability(adapter);
668 * igb_set_interrupt_capability - set MSI or MSI-X if supported
670 * Attempt to configure interrupts using the best available
671 * capabilities of the hardware and kernel.
673 static void igb_set_interrupt_capability(struct igb_adapter *adapter)
678 /* Number of supported queues. */
679 adapter->num_rx_queues = adapter->rss_queues;
680 adapter->num_tx_queues = adapter->rss_queues;
682 /* start with one vector for every rx queue */
683 numvecs = adapter->num_rx_queues;
685 /* if tx handler is seperate add 1 for every tx queue */
686 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
687 numvecs += adapter->num_tx_queues;
689 /* store the number of vectors reserved for queues */
690 adapter->num_q_vectors = numvecs;
692 /* add 1 vector for link status interrupts */
694 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
696 if (!adapter->msix_entries)
699 for (i = 0; i < numvecs; i++)
700 adapter->msix_entries[i].entry = i;
702 err = pci_enable_msix(adapter->pdev,
703 adapter->msix_entries,
708 igb_reset_interrupt_capability(adapter);
710 /* If we can't do MSI-X, try MSI */
712 #ifdef CONFIG_PCI_IOV
713 /* disable SR-IOV for non MSI-X configurations */
714 if (adapter->vf_data) {
715 struct e1000_hw *hw = &adapter->hw;
716 /* disable iov and allow time for transactions to clear */
717 pci_disable_sriov(adapter->pdev);
720 kfree(adapter->vf_data);
721 adapter->vf_data = NULL;
722 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
724 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
727 adapter->vfs_allocated_count = 0;
728 adapter->rss_queues = 1;
729 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
730 adapter->num_rx_queues = 1;
731 adapter->num_tx_queues = 1;
732 adapter->num_q_vectors = 1;
733 if (!pci_enable_msi(adapter->pdev))
734 adapter->flags |= IGB_FLAG_HAS_MSI;
736 /* Notify the stack of the (possibly) reduced Tx Queue count. */
737 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
742 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
743 * @adapter: board private structure to initialize
745 * We allocate one q_vector per queue interrupt. If allocation fails we
748 static int igb_alloc_q_vectors(struct igb_adapter *adapter)
750 struct igb_q_vector *q_vector;
751 struct e1000_hw *hw = &adapter->hw;
754 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
755 q_vector = kzalloc(sizeof(struct igb_q_vector), GFP_KERNEL);
758 q_vector->adapter = adapter;
759 q_vector->itr_shift = (hw->mac.type == e1000_82575) ? 16 : 0;
760 q_vector->itr_register = hw->hw_addr + E1000_EITR(0);
761 q_vector->itr_val = IGB_START_ITR;
762 q_vector->set_itr = 1;
763 netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll, 64);
764 adapter->q_vector[v_idx] = q_vector;
771 q_vector = adapter->q_vector[v_idx];
772 netif_napi_del(&q_vector->napi);
774 adapter->q_vector[v_idx] = NULL;
779 static void igb_map_rx_ring_to_vector(struct igb_adapter *adapter,
780 int ring_idx, int v_idx)
782 struct igb_q_vector *q_vector;
784 q_vector = adapter->q_vector[v_idx];
785 q_vector->rx_ring = &adapter->rx_ring[ring_idx];
786 q_vector->rx_ring->q_vector = q_vector;
787 q_vector->itr_val = adapter->rx_itr_setting;
788 if (q_vector->itr_val && q_vector->itr_val <= 3)
789 q_vector->itr_val = IGB_START_ITR;
792 static void igb_map_tx_ring_to_vector(struct igb_adapter *adapter,
793 int ring_idx, int v_idx)
795 struct igb_q_vector *q_vector;
797 q_vector = adapter->q_vector[v_idx];
798 q_vector->tx_ring = &adapter->tx_ring[ring_idx];
799 q_vector->tx_ring->q_vector = q_vector;
800 q_vector->itr_val = adapter->tx_itr_setting;
801 if (q_vector->itr_val && q_vector->itr_val <= 3)
802 q_vector->itr_val = IGB_START_ITR;
806 * igb_map_ring_to_vector - maps allocated queues to vectors
808 * This function maps the recently allocated queues to vectors.
810 static int igb_map_ring_to_vector(struct igb_adapter *adapter)
815 if ((adapter->num_q_vectors < adapter->num_rx_queues) ||
816 (adapter->num_q_vectors < adapter->num_tx_queues))
819 if (adapter->num_q_vectors >=
820 (adapter->num_rx_queues + adapter->num_tx_queues)) {
821 for (i = 0; i < adapter->num_rx_queues; i++)
822 igb_map_rx_ring_to_vector(adapter, i, v_idx++);
823 for (i = 0; i < adapter->num_tx_queues; i++)
824 igb_map_tx_ring_to_vector(adapter, i, v_idx++);
826 for (i = 0; i < adapter->num_rx_queues; i++) {
827 if (i < adapter->num_tx_queues)
828 igb_map_tx_ring_to_vector(adapter, i, v_idx);
829 igb_map_rx_ring_to_vector(adapter, i, v_idx++);
831 for (; i < adapter->num_tx_queues; i++)
832 igb_map_tx_ring_to_vector(adapter, i, v_idx++);
838 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
840 * This function initializes the interrupts and allocates all of the queues.
842 static int igb_init_interrupt_scheme(struct igb_adapter *adapter)
844 struct pci_dev *pdev = adapter->pdev;
847 igb_set_interrupt_capability(adapter);
849 err = igb_alloc_q_vectors(adapter);
851 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
852 goto err_alloc_q_vectors;
855 err = igb_alloc_queues(adapter);
857 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
858 goto err_alloc_queues;
861 err = igb_map_ring_to_vector(adapter);
863 dev_err(&pdev->dev, "Invalid q_vector to ring mapping\n");
870 igb_free_queues(adapter);
872 igb_free_q_vectors(adapter);
874 igb_reset_interrupt_capability(adapter);
879 * igb_request_irq - initialize interrupts
881 * Attempts to configure interrupts using the best available
882 * capabilities of the hardware and kernel.
884 static int igb_request_irq(struct igb_adapter *adapter)
886 struct net_device *netdev = adapter->netdev;
887 struct pci_dev *pdev = adapter->pdev;
890 if (adapter->msix_entries) {
891 err = igb_request_msix(adapter);
894 /* fall back to MSI */
895 igb_clear_interrupt_scheme(adapter);
896 if (!pci_enable_msi(adapter->pdev))
897 adapter->flags |= IGB_FLAG_HAS_MSI;
898 igb_free_all_tx_resources(adapter);
899 igb_free_all_rx_resources(adapter);
900 adapter->num_tx_queues = 1;
901 adapter->num_rx_queues = 1;
902 adapter->num_q_vectors = 1;
903 err = igb_alloc_q_vectors(adapter);
906 "Unable to allocate memory for vectors\n");
909 err = igb_alloc_queues(adapter);
912 "Unable to allocate memory for queues\n");
913 igb_free_q_vectors(adapter);
916 igb_setup_all_tx_resources(adapter);
917 igb_setup_all_rx_resources(adapter);
919 igb_assign_vector(adapter->q_vector[0], 0);
922 if (adapter->flags & IGB_FLAG_HAS_MSI) {
923 err = request_irq(adapter->pdev->irq, igb_intr_msi, 0,
924 netdev->name, adapter);
928 /* fall back to legacy interrupts */
929 igb_reset_interrupt_capability(adapter);
930 adapter->flags &= ~IGB_FLAG_HAS_MSI;
933 err = request_irq(adapter->pdev->irq, igb_intr, IRQF_SHARED,
934 netdev->name, adapter);
937 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
944 static void igb_free_irq(struct igb_adapter *adapter)
946 if (adapter->msix_entries) {
949 free_irq(adapter->msix_entries[vector++].vector, adapter);
951 for (i = 0; i < adapter->num_q_vectors; i++) {
952 struct igb_q_vector *q_vector = adapter->q_vector[i];
953 free_irq(adapter->msix_entries[vector++].vector,
957 free_irq(adapter->pdev->irq, adapter);
962 * igb_irq_disable - Mask off interrupt generation on the NIC
963 * @adapter: board private structure
965 static void igb_irq_disable(struct igb_adapter *adapter)
967 struct e1000_hw *hw = &adapter->hw;
970 * we need to be careful when disabling interrupts. The VFs are also
971 * mapped into these registers and so clearing the bits can cause
972 * issues on the VF drivers so we only need to clear what we set
974 if (adapter->msix_entries) {
975 u32 regval = rd32(E1000_EIAM);
976 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
977 wr32(E1000_EIMC, adapter->eims_enable_mask);
978 regval = rd32(E1000_EIAC);
979 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
985 synchronize_irq(adapter->pdev->irq);
989 * igb_irq_enable - Enable default interrupt generation settings
990 * @adapter: board private structure
992 static void igb_irq_enable(struct igb_adapter *adapter)
994 struct e1000_hw *hw = &adapter->hw;
996 if (adapter->msix_entries) {
997 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC;
998 u32 regval = rd32(E1000_EIAC);
999 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1000 regval = rd32(E1000_EIAM);
1001 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
1002 wr32(E1000_EIMS, adapter->eims_enable_mask);
1003 if (adapter->vfs_allocated_count) {
1004 wr32(E1000_MBVFIMR, 0xFF);
1005 ims |= E1000_IMS_VMMB;
1007 if (adapter->hw.mac.type == e1000_82580)
1008 ims |= E1000_IMS_DRSTA;
1010 wr32(E1000_IMS, ims);
1012 wr32(E1000_IMS, IMS_ENABLE_MASK |
1014 wr32(E1000_IAM, IMS_ENABLE_MASK |
1019 static void igb_update_mng_vlan(struct igb_adapter *adapter)
1021 struct e1000_hw *hw = &adapter->hw;
1022 u16 vid = adapter->hw.mng_cookie.vlan_id;
1023 u16 old_vid = adapter->mng_vlan_id;
1025 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1026 /* add VID to filter table */
1027 igb_vfta_set(hw, vid, true);
1028 adapter->mng_vlan_id = vid;
1030 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1033 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1035 !vlan_group_get_device(adapter->vlgrp, old_vid)) {
1036 /* remove VID from filter table */
1037 igb_vfta_set(hw, old_vid, false);
1042 * igb_release_hw_control - release control of the h/w to f/w
1043 * @adapter: address of board private structure
1045 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1046 * For ASF and Pass Through versions of f/w this means that the
1047 * driver is no longer loaded.
1050 static void igb_release_hw_control(struct igb_adapter *adapter)
1052 struct e1000_hw *hw = &adapter->hw;
1055 /* Let firmware take over control of h/w */
1056 ctrl_ext = rd32(E1000_CTRL_EXT);
1057 wr32(E1000_CTRL_EXT,
1058 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1062 * igb_get_hw_control - get control of the h/w from f/w
1063 * @adapter: address of board private structure
1065 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1066 * For ASF and Pass Through versions of f/w this means that
1067 * the driver is loaded.
1070 static void igb_get_hw_control(struct igb_adapter *adapter)
1072 struct e1000_hw *hw = &adapter->hw;
1075 /* Let firmware know the driver has taken over */
1076 ctrl_ext = rd32(E1000_CTRL_EXT);
1077 wr32(E1000_CTRL_EXT,
1078 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1082 * igb_configure - configure the hardware for RX and TX
1083 * @adapter: private board structure
1085 static void igb_configure(struct igb_adapter *adapter)
1087 struct net_device *netdev = adapter->netdev;
1090 igb_get_hw_control(adapter);
1091 igb_set_rx_mode(netdev);
1093 igb_restore_vlan(adapter);
1095 igb_setup_tctl(adapter);
1096 igb_setup_mrqc(adapter);
1097 igb_setup_rctl(adapter);
1099 igb_configure_tx(adapter);
1100 igb_configure_rx(adapter);
1102 igb_rx_fifo_flush_82575(&adapter->hw);
1104 /* call igb_desc_unused which always leaves
1105 * at least 1 descriptor unused to make sure
1106 * next_to_use != next_to_clean */
1107 for (i = 0; i < adapter->num_rx_queues; i++) {
1108 struct igb_ring *ring = &adapter->rx_ring[i];
1109 igb_alloc_rx_buffers_adv(ring, igb_desc_unused(ring));
1113 adapter->tx_queue_len = netdev->tx_queue_len;
1118 * igb_up - Open the interface and prepare it to handle traffic
1119 * @adapter: board private structure
1121 int igb_up(struct igb_adapter *adapter)
1123 struct e1000_hw *hw = &adapter->hw;
1126 /* hardware has been reset, we need to reload some things */
1127 igb_configure(adapter);
1129 clear_bit(__IGB_DOWN, &adapter->state);
1131 for (i = 0; i < adapter->num_q_vectors; i++) {
1132 struct igb_q_vector *q_vector = adapter->q_vector[i];
1133 napi_enable(&q_vector->napi);
1135 if (adapter->msix_entries)
1136 igb_configure_msix(adapter);
1138 igb_assign_vector(adapter->q_vector[0], 0);
1140 /* Clear any pending interrupts. */
1142 igb_irq_enable(adapter);
1144 /* notify VFs that reset has been completed */
1145 if (adapter->vfs_allocated_count) {
1146 u32 reg_data = rd32(E1000_CTRL_EXT);
1147 reg_data |= E1000_CTRL_EXT_PFRSTD;
1148 wr32(E1000_CTRL_EXT, reg_data);
1151 netif_tx_start_all_queues(adapter->netdev);
1153 /* start the watchdog. */
1154 hw->mac.get_link_status = 1;
1155 schedule_work(&adapter->watchdog_task);
1160 void igb_down(struct igb_adapter *adapter)
1162 struct net_device *netdev = adapter->netdev;
1163 struct e1000_hw *hw = &adapter->hw;
1167 /* signal that we're down so the interrupt handler does not
1168 * reschedule our watchdog timer */
1169 set_bit(__IGB_DOWN, &adapter->state);
1171 /* disable receives in the hardware */
1172 rctl = rd32(E1000_RCTL);
1173 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1174 /* flush and sleep below */
1176 netif_tx_stop_all_queues(netdev);
1178 /* disable transmits in the hardware */
1179 tctl = rd32(E1000_TCTL);
1180 tctl &= ~E1000_TCTL_EN;
1181 wr32(E1000_TCTL, tctl);
1182 /* flush both disables and wait for them to finish */
1186 for (i = 0; i < adapter->num_q_vectors; i++) {
1187 struct igb_q_vector *q_vector = adapter->q_vector[i];
1188 napi_disable(&q_vector->napi);
1191 igb_irq_disable(adapter);
1193 del_timer_sync(&adapter->watchdog_timer);
1194 del_timer_sync(&adapter->phy_info_timer);
1196 netdev->tx_queue_len = adapter->tx_queue_len;
1197 netif_carrier_off(netdev);
1199 /* record the stats before reset*/
1200 igb_update_stats(adapter);
1202 adapter->link_speed = 0;
1203 adapter->link_duplex = 0;
1205 if (!pci_channel_offline(adapter->pdev))
1207 igb_clean_all_tx_rings(adapter);
1208 igb_clean_all_rx_rings(adapter);
1209 #ifdef CONFIG_IGB_DCA
1211 /* since we reset the hardware DCA settings were cleared */
1212 igb_setup_dca(adapter);
1216 void igb_reinit_locked(struct igb_adapter *adapter)
1218 WARN_ON(in_interrupt());
1219 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1223 clear_bit(__IGB_RESETTING, &adapter->state);
1226 void igb_reset(struct igb_adapter *adapter)
1228 struct pci_dev *pdev = adapter->pdev;
1229 struct e1000_hw *hw = &adapter->hw;
1230 struct e1000_mac_info *mac = &hw->mac;
1231 struct e1000_fc_info *fc = &hw->fc;
1232 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1235 /* Repartition Pba for greater than 9k mtu
1236 * To take effect CTRL.RST is required.
1238 switch (mac->type) {
1240 pba = rd32(E1000_RXPBS);
1241 pba = igb_rxpbs_adjust_82580(pba);
1244 pba = rd32(E1000_RXPBS);
1245 pba &= E1000_RXPBS_SIZE_MASK_82576;
1249 pba = E1000_PBA_34K;
1253 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1254 (mac->type < e1000_82576)) {
1255 /* adjust PBA for jumbo frames */
1256 wr32(E1000_PBA, pba);
1258 /* To maintain wire speed transmits, the Tx FIFO should be
1259 * large enough to accommodate two full transmit packets,
1260 * rounded up to the next 1KB and expressed in KB. Likewise,
1261 * the Rx FIFO should be large enough to accommodate at least
1262 * one full receive packet and is similarly rounded up and
1263 * expressed in KB. */
1264 pba = rd32(E1000_PBA);
1265 /* upper 16 bits has Tx packet buffer allocation size in KB */
1266 tx_space = pba >> 16;
1267 /* lower 16 bits has Rx packet buffer allocation size in KB */
1269 /* the tx fifo also stores 16 bytes of information about the tx
1270 * but don't include ethernet FCS because hardware appends it */
1271 min_tx_space = (adapter->max_frame_size +
1272 sizeof(union e1000_adv_tx_desc) -
1274 min_tx_space = ALIGN(min_tx_space, 1024);
1275 min_tx_space >>= 10;
1276 /* software strips receive CRC, so leave room for it */
1277 min_rx_space = adapter->max_frame_size;
1278 min_rx_space = ALIGN(min_rx_space, 1024);
1279 min_rx_space >>= 10;
1281 /* If current Tx allocation is less than the min Tx FIFO size,
1282 * and the min Tx FIFO size is less than the current Rx FIFO
1283 * allocation, take space away from current Rx allocation */
1284 if (tx_space < min_tx_space &&
1285 ((min_tx_space - tx_space) < pba)) {
1286 pba = pba - (min_tx_space - tx_space);
1288 /* if short on rx space, rx wins and must trump tx
1290 if (pba < min_rx_space)
1293 wr32(E1000_PBA, pba);
1296 /* flow control settings */
1297 /* The high water mark must be low enough to fit one full frame
1298 * (or the size used for early receive) above it in the Rx FIFO.
1299 * Set it to the lower of:
1300 * - 90% of the Rx FIFO size, or
1301 * - the full Rx FIFO size minus one full frame */
1302 hwm = min(((pba << 10) * 9 / 10),
1303 ((pba << 10) - 2 * adapter->max_frame_size));
1305 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1306 fc->low_water = fc->high_water - 16;
1307 fc->pause_time = 0xFFFF;
1309 fc->current_mode = fc->requested_mode;
1311 /* disable receive for all VFs and wait one second */
1312 if (adapter->vfs_allocated_count) {
1314 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1315 adapter->vf_data[i].flags = 0;
1317 /* ping all the active vfs to let them know we are going down */
1318 igb_ping_all_vfs(adapter);
1320 /* disable transmits and receives */
1321 wr32(E1000_VFRE, 0);
1322 wr32(E1000_VFTE, 0);
1325 /* Allow time for pending master requests to run */
1326 hw->mac.ops.reset_hw(hw);
1329 if (hw->mac.ops.init_hw(hw))
1330 dev_err(&pdev->dev, "Hardware Error\n");
1332 if (hw->mac.type == e1000_82580) {
1333 u32 reg = rd32(E1000_PCIEMISC);
1334 wr32(E1000_PCIEMISC,
1335 reg & ~E1000_PCIEMISC_LX_DECISION);
1337 igb_update_mng_vlan(adapter);
1339 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1340 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1342 igb_reset_adaptive(hw);
1343 igb_get_phy_info(hw);
1346 static const struct net_device_ops igb_netdev_ops = {
1347 .ndo_open = igb_open,
1348 .ndo_stop = igb_close,
1349 .ndo_start_xmit = igb_xmit_frame_adv,
1350 .ndo_get_stats = igb_get_stats,
1351 .ndo_set_rx_mode = igb_set_rx_mode,
1352 .ndo_set_multicast_list = igb_set_rx_mode,
1353 .ndo_set_mac_address = igb_set_mac,
1354 .ndo_change_mtu = igb_change_mtu,
1355 .ndo_do_ioctl = igb_ioctl,
1356 .ndo_tx_timeout = igb_tx_timeout,
1357 .ndo_validate_addr = eth_validate_addr,
1358 .ndo_vlan_rx_register = igb_vlan_rx_register,
1359 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1360 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
1361 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
1362 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
1363 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
1364 .ndo_get_vf_config = igb_ndo_get_vf_config,
1365 #ifdef CONFIG_NET_POLL_CONTROLLER
1366 .ndo_poll_controller = igb_netpoll,
1371 * igb_probe - Device Initialization Routine
1372 * @pdev: PCI device information struct
1373 * @ent: entry in igb_pci_tbl
1375 * Returns 0 on success, negative on failure
1377 * igb_probe initializes an adapter identified by a pci_dev structure.
1378 * The OS initialization, configuring of the adapter private structure,
1379 * and a hardware reset occur.
1381 static int __devinit igb_probe(struct pci_dev *pdev,
1382 const struct pci_device_id *ent)
1384 struct net_device *netdev;
1385 struct igb_adapter *adapter;
1386 struct e1000_hw *hw;
1387 u16 eeprom_data = 0;
1388 static int global_quad_port_a; /* global quad port a indication */
1389 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1390 unsigned long mmio_start, mmio_len;
1391 int err, pci_using_dac;
1392 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1395 err = pci_enable_device_mem(pdev);
1400 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1402 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1406 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1408 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1410 dev_err(&pdev->dev, "No usable DMA "
1411 "configuration, aborting\n");
1417 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1423 pci_enable_pcie_error_reporting(pdev);
1425 pci_set_master(pdev);
1426 pci_save_state(pdev);
1429 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1430 IGB_ABS_MAX_TX_QUEUES);
1432 goto err_alloc_etherdev;
1434 SET_NETDEV_DEV(netdev, &pdev->dev);
1436 pci_set_drvdata(pdev, netdev);
1437 adapter = netdev_priv(netdev);
1438 adapter->netdev = netdev;
1439 adapter->pdev = pdev;
1442 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1444 mmio_start = pci_resource_start(pdev, 0);
1445 mmio_len = pci_resource_len(pdev, 0);
1448 hw->hw_addr = ioremap(mmio_start, mmio_len);
1452 netdev->netdev_ops = &igb_netdev_ops;
1453 igb_set_ethtool_ops(netdev);
1454 netdev->watchdog_timeo = 5 * HZ;
1456 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1458 netdev->mem_start = mmio_start;
1459 netdev->mem_end = mmio_start + mmio_len;
1461 /* PCI config space info */
1462 hw->vendor_id = pdev->vendor;
1463 hw->device_id = pdev->device;
1464 hw->revision_id = pdev->revision;
1465 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1466 hw->subsystem_device_id = pdev->subsystem_device;
1468 /* Copy the default MAC, PHY and NVM function pointers */
1469 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1470 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1471 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1472 /* Initialize skew-specific constants */
1473 err = ei->get_invariants(hw);
1477 /* setup the private structure */
1478 err = igb_sw_init(adapter);
1482 igb_get_bus_info_pcie(hw);
1484 hw->phy.autoneg_wait_to_complete = false;
1485 hw->mac.adaptive_ifs = true;
1487 /* Copper options */
1488 if (hw->phy.media_type == e1000_media_type_copper) {
1489 hw->phy.mdix = AUTO_ALL_MODES;
1490 hw->phy.disable_polarity_correction = false;
1491 hw->phy.ms_type = e1000_ms_hw_default;
1494 if (igb_check_reset_block(hw))
1495 dev_info(&pdev->dev,
1496 "PHY reset is blocked due to SOL/IDER session.\n");
1498 netdev->features = NETIF_F_SG |
1500 NETIF_F_HW_VLAN_TX |
1501 NETIF_F_HW_VLAN_RX |
1502 NETIF_F_HW_VLAN_FILTER;
1504 netdev->features |= NETIF_F_IPV6_CSUM;
1505 netdev->features |= NETIF_F_TSO;
1506 netdev->features |= NETIF_F_TSO6;
1507 netdev->features |= NETIF_F_GRO;
1509 netdev->vlan_features |= NETIF_F_TSO;
1510 netdev->vlan_features |= NETIF_F_TSO6;
1511 netdev->vlan_features |= NETIF_F_IP_CSUM;
1512 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
1513 netdev->vlan_features |= NETIF_F_SG;
1516 netdev->features |= NETIF_F_HIGHDMA;
1518 if (hw->mac.type >= e1000_82576)
1519 netdev->features |= NETIF_F_SCTP_CSUM;
1521 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
1523 /* before reading the NVM, reset the controller to put the device in a
1524 * known good starting state */
1525 hw->mac.ops.reset_hw(hw);
1527 /* make sure the NVM is good */
1528 if (igb_validate_nvm_checksum(hw) < 0) {
1529 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1534 /* copy the MAC address out of the NVM */
1535 if (hw->mac.ops.read_mac_addr(hw))
1536 dev_err(&pdev->dev, "NVM Read Error\n");
1538 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1539 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1541 if (!is_valid_ether_addr(netdev->perm_addr)) {
1542 dev_err(&pdev->dev, "Invalid MAC Address\n");
1547 setup_timer(&adapter->watchdog_timer, &igb_watchdog,
1548 (unsigned long) adapter);
1549 setup_timer(&adapter->phy_info_timer, &igb_update_phy_info,
1550 (unsigned long) adapter);
1552 INIT_WORK(&adapter->reset_task, igb_reset_task);
1553 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1555 /* Initialize link properties that are user-changeable */
1556 adapter->fc_autoneg = true;
1557 hw->mac.autoneg = true;
1558 hw->phy.autoneg_advertised = 0x2f;
1560 hw->fc.requested_mode = e1000_fc_default;
1561 hw->fc.current_mode = e1000_fc_default;
1563 igb_validate_mdi_setting(hw);
1565 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1566 * enable the ACPI Magic Packet filter
1569 if (hw->bus.func == 0)
1570 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
1571 else if (hw->mac.type == e1000_82580)
1572 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
1573 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
1575 else if (hw->bus.func == 1)
1576 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
1578 if (eeprom_data & eeprom_apme_mask)
1579 adapter->eeprom_wol |= E1000_WUFC_MAG;
1581 /* now that we have the eeprom settings, apply the special cases where
1582 * the eeprom may be wrong or the board simply won't support wake on
1583 * lan on a particular port */
1584 switch (pdev->device) {
1585 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1586 adapter->eeprom_wol = 0;
1588 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1589 case E1000_DEV_ID_82576_FIBER:
1590 case E1000_DEV_ID_82576_SERDES:
1591 /* Wake events only supported on port A for dual fiber
1592 * regardless of eeprom setting */
1593 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1594 adapter->eeprom_wol = 0;
1596 case E1000_DEV_ID_82576_QUAD_COPPER:
1597 /* if quad port adapter, disable WoL on all but port A */
1598 if (global_quad_port_a != 0)
1599 adapter->eeprom_wol = 0;
1601 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
1602 /* Reset for multiple quad port adapters */
1603 if (++global_quad_port_a == 4)
1604 global_quad_port_a = 0;
1608 /* initialize the wol settings based on the eeprom settings */
1609 adapter->wol = adapter->eeprom_wol;
1610 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1612 /* reset the hardware with the new settings */
1615 /* let the f/w know that the h/w is now under the control of the
1617 igb_get_hw_control(adapter);
1619 strcpy(netdev->name, "eth%d");
1620 err = register_netdev(netdev);
1624 /* carrier off reporting is important to ethtool even BEFORE open */
1625 netif_carrier_off(netdev);
1627 #ifdef CONFIG_IGB_DCA
1628 if (dca_add_requester(&pdev->dev) == 0) {
1629 adapter->flags |= IGB_FLAG_DCA_ENABLED;
1630 dev_info(&pdev->dev, "DCA enabled\n");
1631 igb_setup_dca(adapter);
1635 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1636 /* print bus type/speed/width info */
1637 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
1639 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
1641 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
1642 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
1643 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
1647 igb_read_part_num(hw, &part_num);
1648 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1649 (part_num >> 8), (part_num & 0xff));
1651 dev_info(&pdev->dev,
1652 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1653 adapter->msix_entries ? "MSI-X" :
1654 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
1655 adapter->num_rx_queues, adapter->num_tx_queues);
1660 igb_release_hw_control(adapter);
1662 if (!igb_check_reset_block(hw))
1665 if (hw->flash_address)
1666 iounmap(hw->flash_address);
1668 igb_clear_interrupt_scheme(adapter);
1669 iounmap(hw->hw_addr);
1671 free_netdev(netdev);
1673 pci_release_selected_regions(pdev,
1674 pci_select_bars(pdev, IORESOURCE_MEM));
1677 pci_disable_device(pdev);
1682 * igb_remove - Device Removal Routine
1683 * @pdev: PCI device information struct
1685 * igb_remove is called by the PCI subsystem to alert the driver
1686 * that it should release a PCI device. The could be caused by a
1687 * Hot-Plug event, or because the driver is going to be removed from
1690 static void __devexit igb_remove(struct pci_dev *pdev)
1692 struct net_device *netdev = pci_get_drvdata(pdev);
1693 struct igb_adapter *adapter = netdev_priv(netdev);
1694 struct e1000_hw *hw = &adapter->hw;
1696 /* flush_scheduled work may reschedule our watchdog task, so
1697 * explicitly disable watchdog tasks from being rescheduled */
1698 set_bit(__IGB_DOWN, &adapter->state);
1699 del_timer_sync(&adapter->watchdog_timer);
1700 del_timer_sync(&adapter->phy_info_timer);
1702 flush_scheduled_work();
1704 #ifdef CONFIG_IGB_DCA
1705 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
1706 dev_info(&pdev->dev, "DCA disabled\n");
1707 dca_remove_requester(&pdev->dev);
1708 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
1709 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
1713 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1714 * would have already happened in close and is redundant. */
1715 igb_release_hw_control(adapter);
1717 unregister_netdev(netdev);
1719 if (!igb_check_reset_block(hw))
1722 igb_clear_interrupt_scheme(adapter);
1724 #ifdef CONFIG_PCI_IOV
1725 /* reclaim resources allocated to VFs */
1726 if (adapter->vf_data) {
1727 /* disable iov and allow time for transactions to clear */
1728 pci_disable_sriov(pdev);
1731 kfree(adapter->vf_data);
1732 adapter->vf_data = NULL;
1733 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1735 dev_info(&pdev->dev, "IOV Disabled\n");
1739 iounmap(hw->hw_addr);
1740 if (hw->flash_address)
1741 iounmap(hw->flash_address);
1742 pci_release_selected_regions(pdev,
1743 pci_select_bars(pdev, IORESOURCE_MEM));
1745 free_netdev(netdev);
1747 pci_disable_pcie_error_reporting(pdev);
1749 pci_disable_device(pdev);
1753 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
1754 * @adapter: board private structure to initialize
1756 * This function initializes the vf specific data storage and then attempts to
1757 * allocate the VFs. The reason for ordering it this way is because it is much
1758 * mor expensive time wise to disable SR-IOV than it is to allocate and free
1759 * the memory for the VFs.
1761 static void __devinit igb_probe_vfs(struct igb_adapter * adapter)
1763 #ifdef CONFIG_PCI_IOV
1764 struct pci_dev *pdev = adapter->pdev;
1766 if (adapter->vfs_allocated_count > 7)
1767 adapter->vfs_allocated_count = 7;
1769 if (adapter->vfs_allocated_count) {
1770 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
1771 sizeof(struct vf_data_storage),
1773 /* if allocation failed then we do not support SR-IOV */
1774 if (!adapter->vf_data) {
1775 adapter->vfs_allocated_count = 0;
1776 dev_err(&pdev->dev, "Unable to allocate memory for VF "
1781 if (pci_enable_sriov(pdev, adapter->vfs_allocated_count)) {
1782 kfree(adapter->vf_data);
1783 adapter->vf_data = NULL;
1784 #endif /* CONFIG_PCI_IOV */
1785 adapter->vfs_allocated_count = 0;
1786 #ifdef CONFIG_PCI_IOV
1788 unsigned char mac_addr[ETH_ALEN];
1790 dev_info(&pdev->dev, "%d vfs allocated\n",
1791 adapter->vfs_allocated_count);
1792 for (i = 0; i < adapter->vfs_allocated_count; i++) {
1793 random_ether_addr(mac_addr);
1794 igb_set_vf_mac(adapter, i, mac_addr);
1797 #endif /* CONFIG_PCI_IOV */
1802 * igb_init_hw_timer - Initialize hardware timer used with IEEE 1588 timestamp
1803 * @adapter: board private structure to initialize
1805 * igb_init_hw_timer initializes the function pointer and values for the hw
1806 * timer found in hardware.
1808 static void igb_init_hw_timer(struct igb_adapter *adapter)
1810 struct e1000_hw *hw = &adapter->hw;
1812 switch (hw->mac.type) {
1814 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1815 adapter->cycles.read = igb_read_clock;
1816 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1817 adapter->cycles.mult = 1;
1819 * The 82580 timesync updates the system timer every 8ns by 8ns
1820 * and the value cannot be shifted. Instead we need to shift
1821 * the registers to generate a 64bit timer value. As a result
1822 * SYSTIMR/L/H, TXSTMPL/H, RXSTMPL/H all have to be shifted by
1823 * 24 in order to generate a larger value for synchronization.
1825 adapter->cycles.shift = IGB_82580_TSYNC_SHIFT;
1826 /* disable system timer temporarily by setting bit 31 */
1827 wr32(E1000_TSAUXC, 0x80000000);
1830 /* Set registers so that rollover occurs soon to test this. */
1831 wr32(E1000_SYSTIMR, 0x00000000);
1832 wr32(E1000_SYSTIML, 0x80000000);
1833 wr32(E1000_SYSTIMH, 0x000000FF);
1836 /* enable system timer by clearing bit 31 */
1837 wr32(E1000_TSAUXC, 0x0);
1840 timecounter_init(&adapter->clock,
1842 ktime_to_ns(ktime_get_real()));
1844 * Synchronize our NIC clock against system wall clock. NIC
1845 * time stamp reading requires ~3us per sample, each sample
1846 * was pretty stable even under load => only require 10
1847 * samples for each offset comparison.
1849 memset(&adapter->compare, 0, sizeof(adapter->compare));
1850 adapter->compare.source = &adapter->clock;
1851 adapter->compare.target = ktime_get_real;
1852 adapter->compare.num_samples = 10;
1853 timecompare_update(&adapter->compare, 0);
1857 * Initialize hardware timer: we keep it running just in case
1858 * that some program needs it later on.
1860 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1861 adapter->cycles.read = igb_read_clock;
1862 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1863 adapter->cycles.mult = 1;
1865 * Scale the NIC clock cycle by a large factor so that
1866 * relatively small clock corrections can be added or
1867 * substracted at each clock tick. The drawbacks of a large
1868 * factor are a) that the clock register overflows more quickly
1869 * (not such a big deal) and b) that the increment per tick has
1870 * to fit into 24 bits. As a result we need to use a shift of
1871 * 19 so we can fit a value of 16 into the TIMINCA register.
1873 adapter->cycles.shift = IGB_82576_TSYNC_SHIFT;
1875 (1 << E1000_TIMINCA_16NS_SHIFT) |
1876 (16 << IGB_82576_TSYNC_SHIFT));
1878 /* Set registers so that rollover occurs soon to test this. */
1879 wr32(E1000_SYSTIML, 0x00000000);
1880 wr32(E1000_SYSTIMH, 0xFF800000);
1883 timecounter_init(&adapter->clock,
1885 ktime_to_ns(ktime_get_real()));
1887 * Synchronize our NIC clock against system wall clock. NIC
1888 * time stamp reading requires ~3us per sample, each sample
1889 * was pretty stable even under load => only require 10
1890 * samples for each offset comparison.
1892 memset(&adapter->compare, 0, sizeof(adapter->compare));
1893 adapter->compare.source = &adapter->clock;
1894 adapter->compare.target = ktime_get_real;
1895 adapter->compare.num_samples = 10;
1896 timecompare_update(&adapter->compare, 0);
1899 /* 82575 does not support timesync */
1907 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1908 * @adapter: board private structure to initialize
1910 * igb_sw_init initializes the Adapter private data structure.
1911 * Fields are initialized based on PCI device information and
1912 * OS network device settings (MTU size).
1914 static int __devinit igb_sw_init(struct igb_adapter *adapter)
1916 struct e1000_hw *hw = &adapter->hw;
1917 struct net_device *netdev = adapter->netdev;
1918 struct pci_dev *pdev = adapter->pdev;
1920 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1922 adapter->tx_ring_count = IGB_DEFAULT_TXD;
1923 adapter->rx_ring_count = IGB_DEFAULT_RXD;
1924 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
1925 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
1927 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1928 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1930 #ifdef CONFIG_PCI_IOV
1931 if (hw->mac.type == e1000_82576)
1932 adapter->vfs_allocated_count = max_vfs;
1934 #endif /* CONFIG_PCI_IOV */
1935 adapter->rss_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
1938 * if rss_queues > 4 or vfs are going to be allocated with rss_queues
1939 * then we should combine the queues into a queue pair in order to
1940 * conserve interrupts due to limited supply
1942 if ((adapter->rss_queues > 4) ||
1943 ((adapter->rss_queues > 1) && (adapter->vfs_allocated_count > 6)))
1944 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1946 /* This call may decrease the number of queues */
1947 if (igb_init_interrupt_scheme(adapter)) {
1948 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1952 igb_init_hw_timer(adapter);
1953 igb_probe_vfs(adapter);
1955 /* Explicitly disable IRQ since the NIC can be in any state. */
1956 igb_irq_disable(adapter);
1958 set_bit(__IGB_DOWN, &adapter->state);
1963 * igb_open - Called when a network interface is made active
1964 * @netdev: network interface device structure
1966 * Returns 0 on success, negative value on failure
1968 * The open entry point is called when a network interface is made
1969 * active by the system (IFF_UP). At this point all resources needed
1970 * for transmit and receive operations are allocated, the interrupt
1971 * handler is registered with the OS, the watchdog timer is started,
1972 * and the stack is notified that the interface is ready.
1974 static int igb_open(struct net_device *netdev)
1976 struct igb_adapter *adapter = netdev_priv(netdev);
1977 struct e1000_hw *hw = &adapter->hw;
1981 /* disallow open during test */
1982 if (test_bit(__IGB_TESTING, &adapter->state))
1985 netif_carrier_off(netdev);
1987 /* allocate transmit descriptors */
1988 err = igb_setup_all_tx_resources(adapter);
1992 /* allocate receive descriptors */
1993 err = igb_setup_all_rx_resources(adapter);
1997 /* e1000_power_up_phy(adapter); */
1999 /* before we allocate an interrupt, we must be ready to handle it.
2000 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2001 * as soon as we call pci_request_irq, so we have to setup our
2002 * clean_rx handler before we do so. */
2003 igb_configure(adapter);
2005 err = igb_request_irq(adapter);
2009 /* From here on the code is the same as igb_up() */
2010 clear_bit(__IGB_DOWN, &adapter->state);
2012 for (i = 0; i < adapter->num_q_vectors; i++) {
2013 struct igb_q_vector *q_vector = adapter->q_vector[i];
2014 napi_enable(&q_vector->napi);
2017 /* Clear any pending interrupts. */
2020 igb_irq_enable(adapter);
2022 /* notify VFs that reset has been completed */
2023 if (adapter->vfs_allocated_count) {
2024 u32 reg_data = rd32(E1000_CTRL_EXT);
2025 reg_data |= E1000_CTRL_EXT_PFRSTD;
2026 wr32(E1000_CTRL_EXT, reg_data);
2029 netif_tx_start_all_queues(netdev);
2031 /* start the watchdog. */
2032 hw->mac.get_link_status = 1;
2033 schedule_work(&adapter->watchdog_task);
2038 igb_release_hw_control(adapter);
2039 /* e1000_power_down_phy(adapter); */
2040 igb_free_all_rx_resources(adapter);
2042 igb_free_all_tx_resources(adapter);
2050 * igb_close - Disables a network interface
2051 * @netdev: network interface device structure
2053 * Returns 0, this is not allowed to fail
2055 * The close entry point is called when an interface is de-activated
2056 * by the OS. The hardware is still under the driver's control, but
2057 * needs to be disabled. A global MAC reset is issued to stop the
2058 * hardware, and all transmit and receive resources are freed.
2060 static int igb_close(struct net_device *netdev)
2062 struct igb_adapter *adapter = netdev_priv(netdev);
2064 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
2067 igb_free_irq(adapter);
2069 igb_free_all_tx_resources(adapter);
2070 igb_free_all_rx_resources(adapter);
2076 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
2077 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2079 * Return 0 on success, negative on failure
2081 int igb_setup_tx_resources(struct igb_ring *tx_ring)
2083 struct pci_dev *pdev = tx_ring->pdev;
2086 size = sizeof(struct igb_buffer) * tx_ring->count;
2087 tx_ring->buffer_info = vmalloc(size);
2088 if (!tx_ring->buffer_info)
2090 memset(tx_ring->buffer_info, 0, size);
2092 /* round up to nearest 4K */
2093 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
2094 tx_ring->size = ALIGN(tx_ring->size, 4096);
2096 tx_ring->desc = pci_alloc_consistent(pdev,
2103 tx_ring->next_to_use = 0;
2104 tx_ring->next_to_clean = 0;
2108 vfree(tx_ring->buffer_info);
2110 "Unable to allocate memory for the transmit descriptor ring\n");
2115 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2116 * (Descriptors) for all queues
2117 * @adapter: board private structure
2119 * Return 0 on success, negative on failure
2121 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2123 struct pci_dev *pdev = adapter->pdev;
2126 for (i = 0; i < adapter->num_tx_queues; i++) {
2127 err = igb_setup_tx_resources(&adapter->tx_ring[i]);
2130 "Allocation for Tx Queue %u failed\n", i);
2131 for (i--; i >= 0; i--)
2132 igb_free_tx_resources(&adapter->tx_ring[i]);
2137 for (i = 0; i < IGB_ABS_MAX_TX_QUEUES; i++) {
2138 int r_idx = i % adapter->num_tx_queues;
2139 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
2145 * igb_setup_tctl - configure the transmit control registers
2146 * @adapter: Board private structure
2148 void igb_setup_tctl(struct igb_adapter *adapter)
2150 struct e1000_hw *hw = &adapter->hw;
2153 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2154 wr32(E1000_TXDCTL(0), 0);
2156 /* Program the Transmit Control Register */
2157 tctl = rd32(E1000_TCTL);
2158 tctl &= ~E1000_TCTL_CT;
2159 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2160 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2162 igb_config_collision_dist(hw);
2164 /* Enable transmits */
2165 tctl |= E1000_TCTL_EN;
2167 wr32(E1000_TCTL, tctl);
2171 * igb_configure_tx_ring - Configure transmit ring after Reset
2172 * @adapter: board private structure
2173 * @ring: tx ring to configure
2175 * Configure a transmit ring after a reset.
2177 void igb_configure_tx_ring(struct igb_adapter *adapter,
2178 struct igb_ring *ring)
2180 struct e1000_hw *hw = &adapter->hw;
2182 u64 tdba = ring->dma;
2183 int reg_idx = ring->reg_idx;
2185 /* disable the queue */
2186 txdctl = rd32(E1000_TXDCTL(reg_idx));
2187 wr32(E1000_TXDCTL(reg_idx),
2188 txdctl & ~E1000_TXDCTL_QUEUE_ENABLE);
2192 wr32(E1000_TDLEN(reg_idx),
2193 ring->count * sizeof(union e1000_adv_tx_desc));
2194 wr32(E1000_TDBAL(reg_idx),
2195 tdba & 0x00000000ffffffffULL);
2196 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
2198 ring->head = hw->hw_addr + E1000_TDH(reg_idx);
2199 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
2200 writel(0, ring->head);
2201 writel(0, ring->tail);
2203 txdctl |= IGB_TX_PTHRESH;
2204 txdctl |= IGB_TX_HTHRESH << 8;
2205 txdctl |= IGB_TX_WTHRESH << 16;
2207 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2208 wr32(E1000_TXDCTL(reg_idx), txdctl);
2212 * igb_configure_tx - Configure transmit Unit after Reset
2213 * @adapter: board private structure
2215 * Configure the Tx unit of the MAC after a reset.
2217 static void igb_configure_tx(struct igb_adapter *adapter)
2221 for (i = 0; i < adapter->num_tx_queues; i++)
2222 igb_configure_tx_ring(adapter, &adapter->tx_ring[i]);
2226 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
2227 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2229 * Returns 0 on success, negative on failure
2231 int igb_setup_rx_resources(struct igb_ring *rx_ring)
2233 struct pci_dev *pdev = rx_ring->pdev;
2236 size = sizeof(struct igb_buffer) * rx_ring->count;
2237 rx_ring->buffer_info = vmalloc(size);
2238 if (!rx_ring->buffer_info)
2240 memset(rx_ring->buffer_info, 0, size);
2242 desc_len = sizeof(union e1000_adv_rx_desc);
2244 /* Round up to nearest 4K */
2245 rx_ring->size = rx_ring->count * desc_len;
2246 rx_ring->size = ALIGN(rx_ring->size, 4096);
2248 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
2254 rx_ring->next_to_clean = 0;
2255 rx_ring->next_to_use = 0;
2260 vfree(rx_ring->buffer_info);
2261 rx_ring->buffer_info = NULL;
2262 dev_err(&pdev->dev, "Unable to allocate memory for "
2263 "the receive descriptor ring\n");
2268 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2269 * (Descriptors) for all queues
2270 * @adapter: board private structure
2272 * Return 0 on success, negative on failure
2274 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
2276 struct pci_dev *pdev = adapter->pdev;
2279 for (i = 0; i < adapter->num_rx_queues; i++) {
2280 err = igb_setup_rx_resources(&adapter->rx_ring[i]);
2283 "Allocation for Rx Queue %u failed\n", i);
2284 for (i--; i >= 0; i--)
2285 igb_free_rx_resources(&adapter->rx_ring[i]);
2294 * igb_setup_mrqc - configure the multiple receive queue control registers
2295 * @adapter: Board private structure
2297 static void igb_setup_mrqc(struct igb_adapter *adapter)
2299 struct e1000_hw *hw = &adapter->hw;
2301 u32 j, num_rx_queues, shift = 0, shift2 = 0;
2306 static const u8 rsshash[40] = {
2307 0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2, 0x41, 0x67,
2308 0x25, 0x3d, 0x43, 0xa3, 0x8f, 0xb0, 0xd0, 0xca, 0x2b, 0xcb,
2309 0xae, 0x7b, 0x30, 0xb4, 0x77, 0xcb, 0x2d, 0xa3, 0x80, 0x30,
2310 0xf2, 0x0c, 0x6a, 0x42, 0xb7, 0x3b, 0xbe, 0xac, 0x01, 0xfa };
2312 /* Fill out hash function seeds */
2313 for (j = 0; j < 10; j++) {
2314 u32 rsskey = rsshash[(j * 4)];
2315 rsskey |= rsshash[(j * 4) + 1] << 8;
2316 rsskey |= rsshash[(j * 4) + 2] << 16;
2317 rsskey |= rsshash[(j * 4) + 3] << 24;
2318 array_wr32(E1000_RSSRK(0), j, rsskey);
2321 num_rx_queues = adapter->rss_queues;
2323 if (adapter->vfs_allocated_count) {
2324 /* 82575 and 82576 supports 2 RSS queues for VMDq */
2325 switch (hw->mac.type) {
2341 if (hw->mac.type == e1000_82575)
2345 for (j = 0; j < (32 * 4); j++) {
2346 reta.bytes[j & 3] = (j % num_rx_queues) << shift;
2348 reta.bytes[j & 3] |= num_rx_queues << shift2;
2350 wr32(E1000_RETA(j >> 2), reta.dword);
2354 * Disable raw packet checksumming so that RSS hash is placed in
2355 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
2356 * offloads as they are enabled by default
2358 rxcsum = rd32(E1000_RXCSUM);
2359 rxcsum |= E1000_RXCSUM_PCSD;
2361 if (adapter->hw.mac.type >= e1000_82576)
2362 /* Enable Receive Checksum Offload for SCTP */
2363 rxcsum |= E1000_RXCSUM_CRCOFL;
2365 /* Don't need to set TUOFL or IPOFL, they default to 1 */
2366 wr32(E1000_RXCSUM, rxcsum);
2368 /* If VMDq is enabled then we set the appropriate mode for that, else
2369 * we default to RSS so that an RSS hash is calculated per packet even
2370 * if we are only using one queue */
2371 if (adapter->vfs_allocated_count) {
2372 if (hw->mac.type > e1000_82575) {
2373 /* Set the default pool for the PF's first queue */
2374 u32 vtctl = rd32(E1000_VT_CTL);
2375 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2376 E1000_VT_CTL_DISABLE_DEF_POOL);
2377 vtctl |= adapter->vfs_allocated_count <<
2378 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2379 wr32(E1000_VT_CTL, vtctl);
2381 if (adapter->rss_queues > 1)
2382 mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2384 mrqc = E1000_MRQC_ENABLE_VMDQ;
2386 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2388 igb_vmm_control(adapter);
2390 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2391 E1000_MRQC_RSS_FIELD_IPV4_TCP);
2392 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2393 E1000_MRQC_RSS_FIELD_IPV6_TCP);
2394 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
2395 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2396 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2397 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2399 wr32(E1000_MRQC, mrqc);
2403 * igb_setup_rctl - configure the receive control registers
2404 * @adapter: Board private structure
2406 void igb_setup_rctl(struct igb_adapter *adapter)
2408 struct e1000_hw *hw = &adapter->hw;
2411 rctl = rd32(E1000_RCTL);
2413 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2414 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
2416 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
2417 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2420 * enable stripping of CRC. It's unlikely this will break BMC
2421 * redirection as it did with e1000. Newer features require
2422 * that the HW strips the CRC.
2424 rctl |= E1000_RCTL_SECRC;
2426 /* disable store bad packets and clear size bits. */
2427 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
2429 /* enable LPE to prevent packets larger than max_frame_size */
2430 rctl |= E1000_RCTL_LPE;
2432 /* disable queue 0 to prevent tail write w/o re-config */
2433 wr32(E1000_RXDCTL(0), 0);
2435 /* Attention!!! For SR-IOV PF driver operations you must enable
2436 * queue drop for all VF and PF queues to prevent head of line blocking
2437 * if an un-trusted VF does not provide descriptors to hardware.
2439 if (adapter->vfs_allocated_count) {
2440 /* set all queue drop enable bits */
2441 wr32(E1000_QDE, ALL_QUEUES);
2444 wr32(E1000_RCTL, rctl);
2447 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
2450 struct e1000_hw *hw = &adapter->hw;
2453 /* if it isn't the PF check to see if VFs are enabled and
2454 * increase the size to support vlan tags */
2455 if (vfn < adapter->vfs_allocated_count &&
2456 adapter->vf_data[vfn].vlans_enabled)
2457 size += VLAN_TAG_SIZE;
2459 vmolr = rd32(E1000_VMOLR(vfn));
2460 vmolr &= ~E1000_VMOLR_RLPML_MASK;
2461 vmolr |= size | E1000_VMOLR_LPE;
2462 wr32(E1000_VMOLR(vfn), vmolr);
2468 * igb_rlpml_set - set maximum receive packet size
2469 * @adapter: board private structure
2471 * Configure maximum receivable packet size.
2473 static void igb_rlpml_set(struct igb_adapter *adapter)
2475 u32 max_frame_size = adapter->max_frame_size;
2476 struct e1000_hw *hw = &adapter->hw;
2477 u16 pf_id = adapter->vfs_allocated_count;
2480 max_frame_size += VLAN_TAG_SIZE;
2482 /* if vfs are enabled we set RLPML to the largest possible request
2483 * size and set the VMOLR RLPML to the size we need */
2485 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
2486 max_frame_size = MAX_JUMBO_FRAME_SIZE;
2489 wr32(E1000_RLPML, max_frame_size);
2492 static inline void igb_set_vmolr(struct igb_adapter *adapter,
2495 struct e1000_hw *hw = &adapter->hw;
2499 * This register exists only on 82576 and newer so if we are older then
2500 * we should exit and do nothing
2502 if (hw->mac.type < e1000_82576)
2505 vmolr = rd32(E1000_VMOLR(vfn));
2506 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
2508 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
2510 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
2512 /* clear all bits that might not be set */
2513 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
2515 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
2516 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
2518 * for VMDq only allow the VFs and pool 0 to accept broadcast and
2521 if (vfn <= adapter->vfs_allocated_count)
2522 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
2524 wr32(E1000_VMOLR(vfn), vmolr);
2528 * igb_configure_rx_ring - Configure a receive ring after Reset
2529 * @adapter: board private structure
2530 * @ring: receive ring to be configured
2532 * Configure the Rx unit of the MAC after a reset.
2534 void igb_configure_rx_ring(struct igb_adapter *adapter,
2535 struct igb_ring *ring)
2537 struct e1000_hw *hw = &adapter->hw;
2538 u64 rdba = ring->dma;
2539 int reg_idx = ring->reg_idx;
2542 /* disable the queue */
2543 rxdctl = rd32(E1000_RXDCTL(reg_idx));
2544 wr32(E1000_RXDCTL(reg_idx),
2545 rxdctl & ~E1000_RXDCTL_QUEUE_ENABLE);
2547 /* Set DMA base address registers */
2548 wr32(E1000_RDBAL(reg_idx),
2549 rdba & 0x00000000ffffffffULL);
2550 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
2551 wr32(E1000_RDLEN(reg_idx),
2552 ring->count * sizeof(union e1000_adv_rx_desc));
2554 /* initialize head and tail */
2555 ring->head = hw->hw_addr + E1000_RDH(reg_idx);
2556 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
2557 writel(0, ring->head);
2558 writel(0, ring->tail);
2560 /* set descriptor configuration */
2561 if (ring->rx_buffer_len < IGB_RXBUFFER_1024) {
2562 srrctl = ALIGN(ring->rx_buffer_len, 64) <<
2563 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2564 #if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
2565 srrctl |= IGB_RXBUFFER_16384 >>
2566 E1000_SRRCTL_BSIZEPKT_SHIFT;
2568 srrctl |= (PAGE_SIZE / 2) >>
2569 E1000_SRRCTL_BSIZEPKT_SHIFT;
2571 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2573 srrctl = ALIGN(ring->rx_buffer_len, 1024) >>
2574 E1000_SRRCTL_BSIZEPKT_SHIFT;
2575 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2578 wr32(E1000_SRRCTL(reg_idx), srrctl);
2580 /* set filtering for VMDQ pools */
2581 igb_set_vmolr(adapter, reg_idx & 0x7, true);
2583 /* enable receive descriptor fetching */
2584 rxdctl = rd32(E1000_RXDCTL(reg_idx));
2585 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2586 rxdctl &= 0xFFF00000;
2587 rxdctl |= IGB_RX_PTHRESH;
2588 rxdctl |= IGB_RX_HTHRESH << 8;
2589 rxdctl |= IGB_RX_WTHRESH << 16;
2590 wr32(E1000_RXDCTL(reg_idx), rxdctl);
2594 * igb_configure_rx - Configure receive Unit after Reset
2595 * @adapter: board private structure
2597 * Configure the Rx unit of the MAC after a reset.
2599 static void igb_configure_rx(struct igb_adapter *adapter)
2603 /* set UTA to appropriate mode */
2604 igb_set_uta(adapter);
2606 /* set the correct pool for the PF default MAC address in entry 0 */
2607 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
2608 adapter->vfs_allocated_count);
2610 /* Setup the HW Rx Head and Tail Descriptor Pointers and
2611 * the Base and Length of the Rx Descriptor Ring */
2612 for (i = 0; i < adapter->num_rx_queues; i++)
2613 igb_configure_rx_ring(adapter, &adapter->rx_ring[i]);
2617 * igb_free_tx_resources - Free Tx Resources per Queue
2618 * @tx_ring: Tx descriptor ring for a specific queue
2620 * Free all transmit software resources
2622 void igb_free_tx_resources(struct igb_ring *tx_ring)
2624 igb_clean_tx_ring(tx_ring);
2626 vfree(tx_ring->buffer_info);
2627 tx_ring->buffer_info = NULL;
2629 /* if not set, then don't free */
2633 pci_free_consistent(tx_ring->pdev, tx_ring->size,
2634 tx_ring->desc, tx_ring->dma);
2636 tx_ring->desc = NULL;
2640 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2641 * @adapter: board private structure
2643 * Free all transmit software resources
2645 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2649 for (i = 0; i < adapter->num_tx_queues; i++)
2650 igb_free_tx_resources(&adapter->tx_ring[i]);
2653 void igb_unmap_and_free_tx_resource(struct igb_ring *tx_ring,
2654 struct igb_buffer *buffer_info)
2656 if (buffer_info->dma) {
2657 if (buffer_info->mapped_as_page)
2658 pci_unmap_page(tx_ring->pdev,
2660 buffer_info->length,
2663 pci_unmap_single(tx_ring->pdev,
2665 buffer_info->length,
2667 buffer_info->dma = 0;
2669 if (buffer_info->skb) {
2670 dev_kfree_skb_any(buffer_info->skb);
2671 buffer_info->skb = NULL;
2673 buffer_info->time_stamp = 0;
2674 buffer_info->length = 0;
2675 buffer_info->next_to_watch = 0;
2676 buffer_info->mapped_as_page = false;
2680 * igb_clean_tx_ring - Free Tx Buffers
2681 * @tx_ring: ring to be cleaned
2683 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
2685 struct igb_buffer *buffer_info;
2689 if (!tx_ring->buffer_info)
2691 /* Free all the Tx ring sk_buffs */
2693 for (i = 0; i < tx_ring->count; i++) {
2694 buffer_info = &tx_ring->buffer_info[i];
2695 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
2698 size = sizeof(struct igb_buffer) * tx_ring->count;
2699 memset(tx_ring->buffer_info, 0, size);
2701 /* Zero out the descriptor ring */
2702 memset(tx_ring->desc, 0, tx_ring->size);
2704 tx_ring->next_to_use = 0;
2705 tx_ring->next_to_clean = 0;
2709 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2710 * @adapter: board private structure
2712 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2716 for (i = 0; i < adapter->num_tx_queues; i++)
2717 igb_clean_tx_ring(&adapter->tx_ring[i]);
2721 * igb_free_rx_resources - Free Rx Resources
2722 * @rx_ring: ring to clean the resources from
2724 * Free all receive software resources
2726 void igb_free_rx_resources(struct igb_ring *rx_ring)
2728 igb_clean_rx_ring(rx_ring);
2730 vfree(rx_ring->buffer_info);
2731 rx_ring->buffer_info = NULL;
2733 /* if not set, then don't free */
2737 pci_free_consistent(rx_ring->pdev, rx_ring->size,
2738 rx_ring->desc, rx_ring->dma);
2740 rx_ring->desc = NULL;
2744 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2745 * @adapter: board private structure
2747 * Free all receive software resources
2749 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2753 for (i = 0; i < adapter->num_rx_queues; i++)
2754 igb_free_rx_resources(&adapter->rx_ring[i]);
2758 * igb_clean_rx_ring - Free Rx Buffers per Queue
2759 * @rx_ring: ring to free buffers from
2761 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
2763 struct igb_buffer *buffer_info;
2767 if (!rx_ring->buffer_info)
2770 /* Free all the Rx ring sk_buffs */
2771 for (i = 0; i < rx_ring->count; i++) {
2772 buffer_info = &rx_ring->buffer_info[i];
2773 if (buffer_info->dma) {
2774 pci_unmap_single(rx_ring->pdev,
2776 rx_ring->rx_buffer_len,
2777 PCI_DMA_FROMDEVICE);
2778 buffer_info->dma = 0;
2781 if (buffer_info->skb) {
2782 dev_kfree_skb(buffer_info->skb);
2783 buffer_info->skb = NULL;
2785 if (buffer_info->page_dma) {
2786 pci_unmap_page(rx_ring->pdev,
2787 buffer_info->page_dma,
2789 PCI_DMA_FROMDEVICE);
2790 buffer_info->page_dma = 0;
2792 if (buffer_info->page) {
2793 put_page(buffer_info->page);
2794 buffer_info->page = NULL;
2795 buffer_info->page_offset = 0;
2799 size = sizeof(struct igb_buffer) * rx_ring->count;
2800 memset(rx_ring->buffer_info, 0, size);
2802 /* Zero out the descriptor ring */
2803 memset(rx_ring->desc, 0, rx_ring->size);
2805 rx_ring->next_to_clean = 0;
2806 rx_ring->next_to_use = 0;
2810 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2811 * @adapter: board private structure
2813 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2817 for (i = 0; i < adapter->num_rx_queues; i++)
2818 igb_clean_rx_ring(&adapter->rx_ring[i]);
2822 * igb_set_mac - Change the Ethernet Address of the NIC
2823 * @netdev: network interface device structure
2824 * @p: pointer to an address structure
2826 * Returns 0 on success, negative on failure
2828 static int igb_set_mac(struct net_device *netdev, void *p)
2830 struct igb_adapter *adapter = netdev_priv(netdev);
2831 struct e1000_hw *hw = &adapter->hw;
2832 struct sockaddr *addr = p;
2834 if (!is_valid_ether_addr(addr->sa_data))
2835 return -EADDRNOTAVAIL;
2837 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2838 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
2840 /* set the correct pool for the new PF MAC address in entry 0 */
2841 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
2842 adapter->vfs_allocated_count);
2848 * igb_write_mc_addr_list - write multicast addresses to MTA
2849 * @netdev: network interface device structure
2851 * Writes multicast address list to the MTA hash table.
2852 * Returns: -ENOMEM on failure
2853 * 0 on no addresses written
2854 * X on writing X addresses to MTA
2856 static int igb_write_mc_addr_list(struct net_device *netdev)
2858 struct igb_adapter *adapter = netdev_priv(netdev);
2859 struct e1000_hw *hw = &adapter->hw;
2860 struct dev_mc_list *mc_ptr = netdev->mc_list;
2865 if (netdev_mc_empty(netdev)) {
2866 /* nothing to program, so clear mc list */
2867 igb_update_mc_addr_list(hw, NULL, 0);
2868 igb_restore_vf_multicasts(adapter);
2872 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
2876 /* set vmolr receive overflow multicast bit */
2877 vmolr |= E1000_VMOLR_ROMPE;
2879 /* The shared function expects a packed array of only addresses. */
2880 mc_ptr = netdev->mc_list;
2882 for (i = 0; i < netdev_mc_count(netdev); i++) {
2885 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2886 mc_ptr = mc_ptr->next;
2888 igb_update_mc_addr_list(hw, mta_list, i);
2891 return netdev_mc_count(netdev);
2895 * igb_write_uc_addr_list - write unicast addresses to RAR table
2896 * @netdev: network interface device structure
2898 * Writes unicast address list to the RAR table.
2899 * Returns: -ENOMEM on failure/insufficient address space
2900 * 0 on no addresses written
2901 * X on writing X addresses to the RAR table
2903 static int igb_write_uc_addr_list(struct net_device *netdev)
2905 struct igb_adapter *adapter = netdev_priv(netdev);
2906 struct e1000_hw *hw = &adapter->hw;
2907 unsigned int vfn = adapter->vfs_allocated_count;
2908 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
2911 /* return ENOMEM indicating insufficient memory for addresses */
2912 if (netdev_uc_count(netdev) > rar_entries)
2915 if (!netdev_uc_empty(netdev) && rar_entries) {
2916 struct netdev_hw_addr *ha;
2918 netdev_for_each_uc_addr(ha, netdev) {
2921 igb_rar_set_qsel(adapter, ha->addr,
2927 /* write the addresses in reverse order to avoid write combining */
2928 for (; rar_entries > 0 ; rar_entries--) {
2929 wr32(E1000_RAH(rar_entries), 0);
2930 wr32(E1000_RAL(rar_entries), 0);
2938 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
2939 * @netdev: network interface device structure
2941 * The set_rx_mode entry point is called whenever the unicast or multicast
2942 * address lists or the network interface flags are updated. This routine is
2943 * responsible for configuring the hardware for proper unicast, multicast,
2944 * promiscuous mode, and all-multi behavior.
2946 static void igb_set_rx_mode(struct net_device *netdev)
2948 struct igb_adapter *adapter = netdev_priv(netdev);
2949 struct e1000_hw *hw = &adapter->hw;
2950 unsigned int vfn = adapter->vfs_allocated_count;
2951 u32 rctl, vmolr = 0;
2954 /* Check for Promiscuous and All Multicast modes */
2955 rctl = rd32(E1000_RCTL);
2957 /* clear the effected bits */
2958 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
2960 if (netdev->flags & IFF_PROMISC) {
2961 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2962 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
2964 if (netdev->flags & IFF_ALLMULTI) {
2965 rctl |= E1000_RCTL_MPE;
2966 vmolr |= E1000_VMOLR_MPME;
2969 * Write addresses to the MTA, if the attempt fails
2970 * then we should just turn on promiscous mode so
2971 * that we can at least receive multicast traffic
2973 count = igb_write_mc_addr_list(netdev);
2975 rctl |= E1000_RCTL_MPE;
2976 vmolr |= E1000_VMOLR_MPME;
2978 vmolr |= E1000_VMOLR_ROMPE;
2982 * Write addresses to available RAR registers, if there is not
2983 * sufficient space to store all the addresses then enable
2984 * unicast promiscous mode
2986 count = igb_write_uc_addr_list(netdev);
2988 rctl |= E1000_RCTL_UPE;
2989 vmolr |= E1000_VMOLR_ROPE;
2991 rctl |= E1000_RCTL_VFE;
2993 wr32(E1000_RCTL, rctl);
2996 * In order to support SR-IOV and eventually VMDq it is necessary to set
2997 * the VMOLR to enable the appropriate modes. Without this workaround
2998 * we will have issues with VLAN tag stripping not being done for frames
2999 * that are only arriving because we are the default pool
3001 if (hw->mac.type < e1000_82576)
3004 vmolr |= rd32(E1000_VMOLR(vfn)) &
3005 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
3006 wr32(E1000_VMOLR(vfn), vmolr);
3007 igb_restore_vf_multicasts(adapter);
3010 /* Need to wait a few seconds after link up to get diagnostic information from
3012 static void igb_update_phy_info(unsigned long data)
3014 struct igb_adapter *adapter = (struct igb_adapter *) data;
3015 igb_get_phy_info(&adapter->hw);
3019 * igb_has_link - check shared code for link and determine up/down
3020 * @adapter: pointer to driver private info
3022 static bool igb_has_link(struct igb_adapter *adapter)
3024 struct e1000_hw *hw = &adapter->hw;
3025 bool link_active = false;
3028 /* get_link_status is set on LSC (link status) interrupt or
3029 * rx sequence error interrupt. get_link_status will stay
3030 * false until the e1000_check_for_link establishes link
3031 * for copper adapters ONLY
3033 switch (hw->phy.media_type) {
3034 case e1000_media_type_copper:
3035 if (hw->mac.get_link_status) {
3036 ret_val = hw->mac.ops.check_for_link(hw);
3037 link_active = !hw->mac.get_link_status;
3042 case e1000_media_type_internal_serdes:
3043 ret_val = hw->mac.ops.check_for_link(hw);
3044 link_active = hw->mac.serdes_has_link;
3047 case e1000_media_type_unknown:
3055 * igb_watchdog - Timer Call-back
3056 * @data: pointer to adapter cast into an unsigned long
3058 static void igb_watchdog(unsigned long data)
3060 struct igb_adapter *adapter = (struct igb_adapter *)data;
3061 /* Do the rest outside of interrupt context */
3062 schedule_work(&adapter->watchdog_task);
3065 static void igb_watchdog_task(struct work_struct *work)
3067 struct igb_adapter *adapter = container_of(work,
3070 struct e1000_hw *hw = &adapter->hw;
3071 struct net_device *netdev = adapter->netdev;
3075 link = igb_has_link(adapter);
3077 if (!netif_carrier_ok(netdev)) {
3079 hw->mac.ops.get_speed_and_duplex(hw,
3080 &adapter->link_speed,
3081 &adapter->link_duplex);
3083 ctrl = rd32(E1000_CTRL);
3084 /* Links status message must follow this format */
3085 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
3086 "Flow Control: %s\n",
3088 adapter->link_speed,
3089 adapter->link_duplex == FULL_DUPLEX ?
3090 "Full Duplex" : "Half Duplex",
3091 ((ctrl & E1000_CTRL_TFCE) &&
3092 (ctrl & E1000_CTRL_RFCE)) ? "RX/TX" :
3093 ((ctrl & E1000_CTRL_RFCE) ? "RX" :
3094 ((ctrl & E1000_CTRL_TFCE) ? "TX" : "None")));
3096 /* tweak tx_queue_len according to speed/duplex and
3097 * adjust the timeout factor */
3098 netdev->tx_queue_len = adapter->tx_queue_len;
3099 adapter->tx_timeout_factor = 1;
3100 switch (adapter->link_speed) {
3102 netdev->tx_queue_len = 10;
3103 adapter->tx_timeout_factor = 14;
3106 netdev->tx_queue_len = 100;
3107 /* maybe add some timeout factor ? */
3111 netif_carrier_on(netdev);
3113 igb_ping_all_vfs(adapter);
3115 /* link state has changed, schedule phy info update */
3116 if (!test_bit(__IGB_DOWN, &adapter->state))
3117 mod_timer(&adapter->phy_info_timer,
3118 round_jiffies(jiffies + 2 * HZ));
3121 if (netif_carrier_ok(netdev)) {
3122 adapter->link_speed = 0;
3123 adapter->link_duplex = 0;
3124 /* Links status message must follow this format */
3125 printk(KERN_INFO "igb: %s NIC Link is Down\n",
3127 netif_carrier_off(netdev);
3129 igb_ping_all_vfs(adapter);
3131 /* link state has changed, schedule phy info update */
3132 if (!test_bit(__IGB_DOWN, &adapter->state))
3133 mod_timer(&adapter->phy_info_timer,
3134 round_jiffies(jiffies + 2 * HZ));
3138 igb_update_stats(adapter);
3139 igb_update_adaptive(hw);
3141 for (i = 0; i < adapter->num_tx_queues; i++) {
3142 struct igb_ring *tx_ring = &adapter->tx_ring[i];
3143 if (!netif_carrier_ok(netdev)) {
3144 /* We've lost link, so the controller stops DMA,
3145 * but we've got queued Tx work that's never going
3146 * to get done, so reset controller to flush Tx.
3147 * (Do the reset outside of interrupt context). */
3148 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
3149 adapter->tx_timeout_count++;
3150 schedule_work(&adapter->reset_task);
3151 /* return immediately since reset is imminent */
3156 /* Force detection of hung controller every watchdog period */
3157 tx_ring->detect_tx_hung = true;
3160 /* Cause software interrupt to ensure rx ring is cleaned */
3161 if (adapter->msix_entries) {
3163 for (i = 0; i < adapter->num_q_vectors; i++) {
3164 struct igb_q_vector *q_vector = adapter->q_vector[i];
3165 eics |= q_vector->eims_value;
3167 wr32(E1000_EICS, eics);
3169 wr32(E1000_ICS, E1000_ICS_RXDMT0);
3172 /* Reset the timer */
3173 if (!test_bit(__IGB_DOWN, &adapter->state))
3174 mod_timer(&adapter->watchdog_timer,
3175 round_jiffies(jiffies + 2 * HZ));
3178 enum latency_range {
3182 latency_invalid = 255
3186 * igb_update_ring_itr - update the dynamic ITR value based on packet size
3188 * Stores a new ITR value based on strictly on packet size. This
3189 * algorithm is less sophisticated than that used in igb_update_itr,
3190 * due to the difficulty of synchronizing statistics across multiple
3191 * receive rings. The divisors and thresholds used by this fuction
3192 * were determined based on theoretical maximum wire speed and testing
3193 * data, in order to minimize response time while increasing bulk
3195 * This functionality is controlled by the InterruptThrottleRate module
3196 * parameter (see igb_param.c)
3197 * NOTE: This function is called only when operating in a multiqueue
3198 * receive environment.
3199 * @q_vector: pointer to q_vector
3201 static void igb_update_ring_itr(struct igb_q_vector *q_vector)
3203 int new_val = q_vector->itr_val;
3204 int avg_wire_size = 0;
3205 struct igb_adapter *adapter = q_vector->adapter;
3207 /* For non-gigabit speeds, just fix the interrupt rate at 4000
3208 * ints/sec - ITR timer value of 120 ticks.
3210 if (adapter->link_speed != SPEED_1000) {
3215 if (q_vector->rx_ring && q_vector->rx_ring->total_packets) {
3216 struct igb_ring *ring = q_vector->rx_ring;
3217 avg_wire_size = ring->total_bytes / ring->total_packets;
3220 if (q_vector->tx_ring && q_vector->tx_ring->total_packets) {
3221 struct igb_ring *ring = q_vector->tx_ring;
3222 avg_wire_size = max_t(u32, avg_wire_size,
3223 (ring->total_bytes /
3224 ring->total_packets));
3227 /* if avg_wire_size isn't set no work was done */
3231 /* Add 24 bytes to size to account for CRC, preamble, and gap */
3232 avg_wire_size += 24;
3234 /* Don't starve jumbo frames */
3235 avg_wire_size = min(avg_wire_size, 3000);
3237 /* Give a little boost to mid-size frames */
3238 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
3239 new_val = avg_wire_size / 3;
3241 new_val = avg_wire_size / 2;
3244 if (new_val != q_vector->itr_val) {
3245 q_vector->itr_val = new_val;
3246 q_vector->set_itr = 1;
3249 if (q_vector->rx_ring) {
3250 q_vector->rx_ring->total_bytes = 0;
3251 q_vector->rx_ring->total_packets = 0;
3253 if (q_vector->tx_ring) {
3254 q_vector->tx_ring->total_bytes = 0;
3255 q_vector->tx_ring->total_packets = 0;
3260 * igb_update_itr - update the dynamic ITR value based on statistics
3261 * Stores a new ITR value based on packets and byte
3262 * counts during the last interrupt. The advantage of per interrupt
3263 * computation is faster updates and more accurate ITR for the current
3264 * traffic pattern. Constants in this function were computed
3265 * based on theoretical maximum wire speed and thresholds were set based
3266 * on testing data as well as attempting to minimize response time
3267 * while increasing bulk throughput.
3268 * this functionality is controlled by the InterruptThrottleRate module
3269 * parameter (see igb_param.c)
3270 * NOTE: These calculations are only valid when operating in a single-
3271 * queue environment.
3272 * @adapter: pointer to adapter
3273 * @itr_setting: current q_vector->itr_val
3274 * @packets: the number of packets during this measurement interval
3275 * @bytes: the number of bytes during this measurement interval
3277 static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
3278 int packets, int bytes)
3280 unsigned int retval = itr_setting;
3283 goto update_itr_done;
3285 switch (itr_setting) {
3286 case lowest_latency:
3287 /* handle TSO and jumbo frames */
3288 if (bytes/packets > 8000)
3289 retval = bulk_latency;
3290 else if ((packets < 5) && (bytes > 512))
3291 retval = low_latency;
3293 case low_latency: /* 50 usec aka 20000 ints/s */
3294 if (bytes > 10000) {
3295 /* this if handles the TSO accounting */
3296 if (bytes/packets > 8000) {
3297 retval = bulk_latency;
3298 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
3299 retval = bulk_latency;
3300 } else if ((packets > 35)) {
3301 retval = lowest_latency;
3303 } else if (bytes/packets > 2000) {
3304 retval = bulk_latency;
3305 } else if (packets <= 2 && bytes < 512) {
3306 retval = lowest_latency;
3309 case bulk_latency: /* 250 usec aka 4000 ints/s */
3310 if (bytes > 25000) {
3312 retval = low_latency;
3313 } else if (bytes < 1500) {
3314 retval = low_latency;
3323 static void igb_set_itr(struct igb_adapter *adapter)
3325 struct igb_q_vector *q_vector = adapter->q_vector[0];
3327 u32 new_itr = q_vector->itr_val;
3329 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
3330 if (adapter->link_speed != SPEED_1000) {
3336 adapter->rx_itr = igb_update_itr(adapter,
3338 adapter->rx_ring->total_packets,
3339 adapter->rx_ring->total_bytes);
3341 adapter->tx_itr = igb_update_itr(adapter,
3343 adapter->tx_ring->total_packets,
3344 adapter->tx_ring->total_bytes);
3345 current_itr = max(adapter->rx_itr, adapter->tx_itr);
3347 /* conservative mode (itr 3) eliminates the lowest_latency setting */
3348 if (adapter->rx_itr_setting == 3 && current_itr == lowest_latency)
3349 current_itr = low_latency;
3351 switch (current_itr) {
3352 /* counts and packets in update_itr are dependent on these numbers */
3353 case lowest_latency:
3354 new_itr = 56; /* aka 70,000 ints/sec */
3357 new_itr = 196; /* aka 20,000 ints/sec */
3360 new_itr = 980; /* aka 4,000 ints/sec */
3367 adapter->rx_ring->total_bytes = 0;
3368 adapter->rx_ring->total_packets = 0;
3369 adapter->tx_ring->total_bytes = 0;
3370 adapter->tx_ring->total_packets = 0;
3372 if (new_itr != q_vector->itr_val) {
3373 /* this attempts to bias the interrupt rate towards Bulk
3374 * by adding intermediate steps when interrupt rate is
3376 new_itr = new_itr > q_vector->itr_val ?
3377 max((new_itr * q_vector->itr_val) /
3378 (new_itr + (q_vector->itr_val >> 2)),
3381 /* Don't write the value here; it resets the adapter's
3382 * internal timer, and causes us to delay far longer than
3383 * we should between interrupts. Instead, we write the ITR
3384 * value at the beginning of the next interrupt so the timing
3385 * ends up being correct.
3387 q_vector->itr_val = new_itr;
3388 q_vector->set_itr = 1;
3394 #define IGB_TX_FLAGS_CSUM 0x00000001
3395 #define IGB_TX_FLAGS_VLAN 0x00000002
3396 #define IGB_TX_FLAGS_TSO 0x00000004
3397 #define IGB_TX_FLAGS_IPV4 0x00000008
3398 #define IGB_TX_FLAGS_TSTAMP 0x00000010
3399 #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
3400 #define IGB_TX_FLAGS_VLAN_SHIFT 16
3402 static inline int igb_tso_adv(struct igb_ring *tx_ring,
3403 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
3405 struct e1000_adv_tx_context_desc *context_desc;
3408 struct igb_buffer *buffer_info;
3409 u32 info = 0, tu_cmd = 0;
3410 u32 mss_l4len_idx, l4len;
3413 if (skb_header_cloned(skb)) {
3414 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3419 l4len = tcp_hdrlen(skb);
3422 if (skb->protocol == htons(ETH_P_IP)) {
3423 struct iphdr *iph = ip_hdr(skb);
3426 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
3430 } else if (skb_is_gso_v6(skb)) {
3431 ipv6_hdr(skb)->payload_len = 0;
3432 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3433 &ipv6_hdr(skb)->daddr,
3437 i = tx_ring->next_to_use;
3439 buffer_info = &tx_ring->buffer_info[i];
3440 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3441 /* VLAN MACLEN IPLEN */
3442 if (tx_flags & IGB_TX_FLAGS_VLAN)
3443 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3444 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3445 *hdr_len += skb_network_offset(skb);
3446 info |= skb_network_header_len(skb);
3447 *hdr_len += skb_network_header_len(skb);
3448 context_desc->vlan_macip_lens = cpu_to_le32(info);
3450 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3451 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3453 if (skb->protocol == htons(ETH_P_IP))
3454 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3455 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3457 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3460 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
3461 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
3463 /* For 82575, context index must be unique per ring. */
3464 if (tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX)
3465 mss_l4len_idx |= tx_ring->reg_idx << 4;
3467 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3468 context_desc->seqnum_seed = 0;
3470 buffer_info->time_stamp = jiffies;
3471 buffer_info->next_to_watch = i;
3472 buffer_info->dma = 0;
3474 if (i == tx_ring->count)
3477 tx_ring->next_to_use = i;
3482 static inline bool igb_tx_csum_adv(struct igb_ring *tx_ring,
3483 struct sk_buff *skb, u32 tx_flags)
3485 struct e1000_adv_tx_context_desc *context_desc;
3486 struct pci_dev *pdev = tx_ring->pdev;
3487 struct igb_buffer *buffer_info;
3488 u32 info = 0, tu_cmd = 0;
3491 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
3492 (tx_flags & IGB_TX_FLAGS_VLAN)) {
3493 i = tx_ring->next_to_use;
3494 buffer_info = &tx_ring->buffer_info[i];
3495 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3497 if (tx_flags & IGB_TX_FLAGS_VLAN)
3498 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3500 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3501 if (skb->ip_summed == CHECKSUM_PARTIAL)
3502 info |= skb_network_header_len(skb);
3504 context_desc->vlan_macip_lens = cpu_to_le32(info);
3506 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3508 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3511 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
3512 const struct vlan_ethhdr *vhdr =
3513 (const struct vlan_ethhdr*)skb->data;
3515 protocol = vhdr->h_vlan_encapsulated_proto;
3517 protocol = skb->protocol;
3521 case cpu_to_be16(ETH_P_IP):
3522 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3523 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3524 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3525 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
3526 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
3528 case cpu_to_be16(ETH_P_IPV6):
3529 /* XXX what about other V6 headers?? */
3530 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3531 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3532 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
3533 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
3536 if (unlikely(net_ratelimit()))
3537 dev_warn(&pdev->dev,
3538 "partial checksum but proto=%x!\n",
3544 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3545 context_desc->seqnum_seed = 0;
3546 if (tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX)
3547 context_desc->mss_l4len_idx =
3548 cpu_to_le32(tx_ring->reg_idx << 4);
3550 buffer_info->time_stamp = jiffies;
3551 buffer_info->next_to_watch = i;
3552 buffer_info->dma = 0;
3555 if (i == tx_ring->count)
3557 tx_ring->next_to_use = i;
3564 #define IGB_MAX_TXD_PWR 16
3565 #define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
3567 static inline int igb_tx_map_adv(struct igb_ring *tx_ring, struct sk_buff *skb,
3570 struct igb_buffer *buffer_info;
3571 struct pci_dev *pdev = tx_ring->pdev;
3572 unsigned int len = skb_headlen(skb);
3573 unsigned int count = 0, i;
3576 i = tx_ring->next_to_use;
3578 buffer_info = &tx_ring->buffer_info[i];
3579 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3580 buffer_info->length = len;
3581 /* set time_stamp *before* dma to help avoid a possible race */
3582 buffer_info->time_stamp = jiffies;
3583 buffer_info->next_to_watch = i;
3584 buffer_info->dma = pci_map_single(pdev, skb->data, len,
3586 if (pci_dma_mapping_error(pdev, buffer_info->dma))
3589 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
3590 struct skb_frag_struct *frag;
3594 if (i == tx_ring->count)
3597 frag = &skb_shinfo(skb)->frags[f];
3600 buffer_info = &tx_ring->buffer_info[i];
3601 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3602 buffer_info->length = len;
3603 buffer_info->time_stamp = jiffies;
3604 buffer_info->next_to_watch = i;
3605 buffer_info->mapped_as_page = true;
3606 buffer_info->dma = pci_map_page(pdev,
3611 if (pci_dma_mapping_error(pdev, buffer_info->dma))
3616 tx_ring->buffer_info[i].skb = skb;
3617 tx_ring->buffer_info[first].next_to_watch = i;
3622 dev_err(&pdev->dev, "TX DMA map failed\n");
3624 /* clear timestamp and dma mappings for failed buffer_info mapping */
3625 buffer_info->dma = 0;
3626 buffer_info->time_stamp = 0;
3627 buffer_info->length = 0;
3628 buffer_info->next_to_watch = 0;
3629 buffer_info->mapped_as_page = false;
3632 /* clear timestamp and dma mappings for remaining portion of packet */
3633 while (count >= 0) {
3637 i += tx_ring->count;
3638 buffer_info = &tx_ring->buffer_info[i];
3639 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
3645 static inline void igb_tx_queue_adv(struct igb_ring *tx_ring,
3646 int tx_flags, int count, u32 paylen,
3649 union e1000_adv_tx_desc *tx_desc;
3650 struct igb_buffer *buffer_info;
3651 u32 olinfo_status = 0, cmd_type_len;
3652 unsigned int i = tx_ring->next_to_use;
3654 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
3655 E1000_ADVTXD_DCMD_DEXT);
3657 if (tx_flags & IGB_TX_FLAGS_VLAN)
3658 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3660 if (tx_flags & IGB_TX_FLAGS_TSTAMP)
3661 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
3663 if (tx_flags & IGB_TX_FLAGS_TSO) {
3664 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3666 /* insert tcp checksum */
3667 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3669 /* insert ip checksum */
3670 if (tx_flags & IGB_TX_FLAGS_IPV4)
3671 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3673 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
3674 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3677 if ((tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX) &&
3678 (tx_flags & (IGB_TX_FLAGS_CSUM |
3680 IGB_TX_FLAGS_VLAN)))
3681 olinfo_status |= tx_ring->reg_idx << 4;
3683 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
3686 buffer_info = &tx_ring->buffer_info[i];
3687 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3688 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
3689 tx_desc->read.cmd_type_len =
3690 cpu_to_le32(cmd_type_len | buffer_info->length);
3691 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3694 if (i == tx_ring->count)
3696 } while (count > 0);
3698 tx_desc->read.cmd_type_len |= cpu_to_le32(IGB_ADVTXD_DCMD);
3699 /* Force memory writes to complete before letting h/w
3700 * know there are new descriptors to fetch. (Only
3701 * applicable for weak-ordered memory model archs,
3702 * such as IA-64). */
3705 tx_ring->next_to_use = i;
3706 writel(i, tx_ring->tail);
3707 /* we need this if more than one processor can write to our tail
3708 * at a time, it syncronizes IO on IA64/Altix systems */
3712 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, int size)
3714 struct net_device *netdev = tx_ring->netdev;
3716 netif_stop_subqueue(netdev, tx_ring->queue_index);
3718 /* Herbert's original patch had:
3719 * smp_mb__after_netif_stop_queue();
3720 * but since that doesn't exist yet, just open code it. */
3723 /* We need to check again in a case another CPU has just
3724 * made room available. */
3725 if (igb_desc_unused(tx_ring) < size)
3729 netif_wake_subqueue(netdev, tx_ring->queue_index);
3730 tx_ring->tx_stats.restart_queue++;
3734 static int igb_maybe_stop_tx(struct igb_ring *tx_ring, int size)
3736 if (igb_desc_unused(tx_ring) >= size)
3738 return __igb_maybe_stop_tx(tx_ring, size);
3741 netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *skb,
3742 struct igb_ring *tx_ring)
3744 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
3746 unsigned int tx_flags = 0;
3749 union skb_shared_tx *shtx = skb_tx(skb);
3751 /* need: 1 descriptor per page,
3752 * + 2 desc gap to keep tail from touching head,
3753 * + 1 desc for skb->data,
3754 * + 1 desc for context descriptor,
3755 * otherwise try next time */
3756 if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
3757 /* this is a hard error */
3758 return NETDEV_TX_BUSY;
3761 if (unlikely(shtx->hardware)) {
3762 shtx->in_progress = 1;
3763 tx_flags |= IGB_TX_FLAGS_TSTAMP;
3766 if (vlan_tx_tag_present(skb) && adapter->vlgrp) {
3767 tx_flags |= IGB_TX_FLAGS_VLAN;
3768 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
3771 if (skb->protocol == htons(ETH_P_IP))
3772 tx_flags |= IGB_TX_FLAGS_IPV4;
3774 first = tx_ring->next_to_use;
3775 if (skb_is_gso(skb)) {
3776 tso = igb_tso_adv(tx_ring, skb, tx_flags, &hdr_len);
3779 dev_kfree_skb_any(skb);
3780 return NETDEV_TX_OK;
3785 tx_flags |= IGB_TX_FLAGS_TSO;
3786 else if (igb_tx_csum_adv(tx_ring, skb, tx_flags) &&
3787 (skb->ip_summed == CHECKSUM_PARTIAL))
3788 tx_flags |= IGB_TX_FLAGS_CSUM;
3791 * count reflects descriptors mapped, if 0 or less then mapping error
3792 * has occured and we need to rewind the descriptor queue
3794 count = igb_tx_map_adv(tx_ring, skb, first);
3796 dev_kfree_skb_any(skb);
3797 tx_ring->buffer_info[first].time_stamp = 0;
3798 tx_ring->next_to_use = first;
3799 return NETDEV_TX_OK;
3802 igb_tx_queue_adv(tx_ring, tx_flags, count, skb->len, hdr_len);
3804 /* Make sure there is space in the ring for the next send. */
3805 igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4);
3807 return NETDEV_TX_OK;
3810 static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb,
3811 struct net_device *netdev)
3813 struct igb_adapter *adapter = netdev_priv(netdev);
3814 struct igb_ring *tx_ring;
3817 if (test_bit(__IGB_DOWN, &adapter->state)) {
3818 dev_kfree_skb_any(skb);
3819 return NETDEV_TX_OK;
3822 if (skb->len <= 0) {
3823 dev_kfree_skb_any(skb);
3824 return NETDEV_TX_OK;
3827 r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
3828 tx_ring = adapter->multi_tx_table[r_idx];
3830 /* This goes back to the question of how to logically map a tx queue
3831 * to a flow. Right now, performance is impacted slightly negatively
3832 * if using multiple tx queues. If the stack breaks away from a
3833 * single qdisc implementation, we can look at this again. */
3834 return igb_xmit_frame_ring_adv(skb, tx_ring);
3838 * igb_tx_timeout - Respond to a Tx Hang
3839 * @netdev: network interface device structure
3841 static void igb_tx_timeout(struct net_device *netdev)
3843 struct igb_adapter *adapter = netdev_priv(netdev);
3844 struct e1000_hw *hw = &adapter->hw;
3846 /* Do the reset outside of interrupt context */
3847 adapter->tx_timeout_count++;
3849 if (hw->mac.type == e1000_82580)
3850 hw->dev_spec._82575.global_device_reset = true;
3852 schedule_work(&adapter->reset_task);
3854 (adapter->eims_enable_mask & ~adapter->eims_other));
3857 static void igb_reset_task(struct work_struct *work)
3859 struct igb_adapter *adapter;
3860 adapter = container_of(work, struct igb_adapter, reset_task);
3862 igb_reinit_locked(adapter);
3866 * igb_get_stats - Get System Network Statistics
3867 * @netdev: network interface device structure
3869 * Returns the address of the device statistics structure.
3870 * The statistics are actually updated from the timer callback.
3872 static struct net_device_stats *igb_get_stats(struct net_device *netdev)
3874 /* only return the current stats */
3875 return &netdev->stats;
3879 * igb_change_mtu - Change the Maximum Transfer Unit
3880 * @netdev: network interface device structure
3881 * @new_mtu: new value for maximum frame size
3883 * Returns 0 on success, negative on failure
3885 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3887 struct igb_adapter *adapter = netdev_priv(netdev);
3888 struct pci_dev *pdev = adapter->pdev;
3889 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3890 u32 rx_buffer_len, i;
3892 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3893 dev_err(&pdev->dev, "Invalid MTU setting\n");
3897 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3898 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
3902 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3905 /* igb_down has a dependency on max_frame_size */
3906 adapter->max_frame_size = max_frame;
3908 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3909 * means we reserve 2 more, this pushes us to allocate from the next
3911 * i.e. RXBUFFER_2048 --> size-4096 slab
3914 if (max_frame <= IGB_RXBUFFER_1024)
3915 rx_buffer_len = IGB_RXBUFFER_1024;
3916 else if (max_frame <= MAXIMUM_ETHERNET_VLAN_SIZE)
3917 rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3919 rx_buffer_len = IGB_RXBUFFER_128;
3921 if (netif_running(netdev))
3924 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
3925 netdev->mtu, new_mtu);
3926 netdev->mtu = new_mtu;
3928 for (i = 0; i < adapter->num_rx_queues; i++)
3929 adapter->rx_ring[i].rx_buffer_len = rx_buffer_len;
3931 if (netif_running(netdev))
3936 clear_bit(__IGB_RESETTING, &adapter->state);
3942 * igb_update_stats - Update the board statistics counters
3943 * @adapter: board private structure
3946 void igb_update_stats(struct igb_adapter *adapter)
3948 struct net_device_stats *net_stats = igb_get_stats(adapter->netdev);
3949 struct e1000_hw *hw = &adapter->hw;
3950 struct pci_dev *pdev = adapter->pdev;
3956 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3959 * Prevent stats update while adapter is being reset, or if the pci
3960 * connection is down.
3962 if (adapter->link_speed == 0)
3964 if (pci_channel_offline(pdev))
3969 for (i = 0; i < adapter->num_rx_queues; i++) {
3970 u32 rqdpc_tmp = rd32(E1000_RQDPC(i)) & 0x0FFF;
3971 adapter->rx_ring[i].rx_stats.drops += rqdpc_tmp;
3972 net_stats->rx_fifo_errors += rqdpc_tmp;
3973 bytes += adapter->rx_ring[i].rx_stats.bytes;
3974 packets += adapter->rx_ring[i].rx_stats.packets;
3977 net_stats->rx_bytes = bytes;
3978 net_stats->rx_packets = packets;
3982 for (i = 0; i < adapter->num_tx_queues; i++) {
3983 bytes += adapter->tx_ring[i].tx_stats.bytes;
3984 packets += adapter->tx_ring[i].tx_stats.packets;
3986 net_stats->tx_bytes = bytes;
3987 net_stats->tx_packets = packets;
3989 /* read stats registers */
3990 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3991 adapter->stats.gprc += rd32(E1000_GPRC);
3992 adapter->stats.gorc += rd32(E1000_GORCL);
3993 rd32(E1000_GORCH); /* clear GORCL */
3994 adapter->stats.bprc += rd32(E1000_BPRC);
3995 adapter->stats.mprc += rd32(E1000_MPRC);
3996 adapter->stats.roc += rd32(E1000_ROC);
3998 adapter->stats.prc64 += rd32(E1000_PRC64);
3999 adapter->stats.prc127 += rd32(E1000_PRC127);
4000 adapter->stats.prc255 += rd32(E1000_PRC255);
4001 adapter->stats.prc511 += rd32(E1000_PRC511);
4002 adapter->stats.prc1023 += rd32(E1000_PRC1023);
4003 adapter->stats.prc1522 += rd32(E1000_PRC1522);
4004 adapter->stats.symerrs += rd32(E1000_SYMERRS);
4005 adapter->stats.sec += rd32(E1000_SEC);
4007 adapter->stats.mpc += rd32(E1000_MPC);
4008 adapter->stats.scc += rd32(E1000_SCC);
4009 adapter->stats.ecol += rd32(E1000_ECOL);
4010 adapter->stats.mcc += rd32(E1000_MCC);
4011 adapter->stats.latecol += rd32(E1000_LATECOL);
4012 adapter->stats.dc += rd32(E1000_DC);
4013 adapter->stats.rlec += rd32(E1000_RLEC);
4014 adapter->stats.xonrxc += rd32(E1000_XONRXC);
4015 adapter->stats.xontxc += rd32(E1000_XONTXC);
4016 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4017 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4018 adapter->stats.fcruc += rd32(E1000_FCRUC);
4019 adapter->stats.gptc += rd32(E1000_GPTC);
4020 adapter->stats.gotc += rd32(E1000_GOTCL);
4021 rd32(E1000_GOTCH); /* clear GOTCL */
4022 rnbc = rd32(E1000_RNBC);
4023 adapter->stats.rnbc += rnbc;
4024 net_stats->rx_fifo_errors += rnbc;
4025 adapter->stats.ruc += rd32(E1000_RUC);
4026 adapter->stats.rfc += rd32(E1000_RFC);
4027 adapter->stats.rjc += rd32(E1000_RJC);
4028 adapter->stats.tor += rd32(E1000_TORH);
4029 adapter->stats.tot += rd32(E1000_TOTH);
4030 adapter->stats.tpr += rd32(E1000_TPR);
4032 adapter->stats.ptc64 += rd32(E1000_PTC64);
4033 adapter->stats.ptc127 += rd32(E1000_PTC127);
4034 adapter->stats.ptc255 += rd32(E1000_PTC255);
4035 adapter->stats.ptc511 += rd32(E1000_PTC511);
4036 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4037 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4039 adapter->stats.mptc += rd32(E1000_MPTC);
4040 adapter->stats.bptc += rd32(E1000_BPTC);
4042 /* used for adaptive IFS */
4043 hw->mac.tx_packet_delta = rd32(E1000_TPT);
4044 adapter->stats.tpt += hw->mac.tx_packet_delta;
4045 hw->mac.collision_delta = rd32(E1000_COLC);
4046 adapter->stats.colc += hw->mac.collision_delta;
4048 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
4049 adapter->stats.rxerrc += rd32(E1000_RXERRC);
4050 adapter->stats.tncrs += rd32(E1000_TNCRS);
4051 adapter->stats.tsctc += rd32(E1000_TSCTC);
4052 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
4054 adapter->stats.iac += rd32(E1000_IAC);
4055 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
4056 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
4057 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
4058 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
4059 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
4060 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
4061 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
4062 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
4064 /* Fill out the OS statistics structure */
4065 net_stats->multicast = adapter->stats.mprc;
4066 net_stats->collisions = adapter->stats.colc;
4070 /* RLEC on some newer hardware can be incorrect so build
4071 * our own version based on RUC and ROC */
4072 net_stats->rx_errors = adapter->stats.rxerrc +
4073 adapter->stats.crcerrs + adapter->stats.algnerrc +
4074 adapter->stats.ruc + adapter->stats.roc +
4075 adapter->stats.cexterr;
4076 net_stats->rx_length_errors = adapter->stats.ruc +
4078 net_stats->rx_crc_errors = adapter->stats.crcerrs;
4079 net_stats->rx_frame_errors = adapter->stats.algnerrc;
4080 net_stats->rx_missed_errors = adapter->stats.mpc;
4083 net_stats->tx_errors = adapter->stats.ecol +
4084 adapter->stats.latecol;
4085 net_stats->tx_aborted_errors = adapter->stats.ecol;
4086 net_stats->tx_window_errors = adapter->stats.latecol;
4087 net_stats->tx_carrier_errors = adapter->stats.tncrs;
4089 /* Tx Dropped needs to be maintained elsewhere */
4092 if (hw->phy.media_type == e1000_media_type_copper) {
4093 if ((adapter->link_speed == SPEED_1000) &&
4094 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
4095 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
4096 adapter->phy_stats.idle_errors += phy_tmp;
4100 /* Management Stats */
4101 adapter->stats.mgptc += rd32(E1000_MGTPTC);
4102 adapter->stats.mgprc += rd32(E1000_MGTPRC);
4103 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
4106 static irqreturn_t igb_msix_other(int irq, void *data)
4108 struct igb_adapter *adapter = data;
4109 struct e1000_hw *hw = &adapter->hw;
4110 u32 icr = rd32(E1000_ICR);
4111 /* reading ICR causes bit 31 of EICR to be cleared */
4113 if (icr & E1000_ICR_DRSTA)
4114 schedule_work(&adapter->reset_task);
4116 if (icr & E1000_ICR_DOUTSYNC) {
4117 /* HW is reporting DMA is out of sync */
4118 adapter->stats.doosync++;
4121 /* Check for a mailbox event */
4122 if (icr & E1000_ICR_VMMB)
4123 igb_msg_task(adapter);
4125 if (icr & E1000_ICR_LSC) {
4126 hw->mac.get_link_status = 1;
4127 /* guard against interrupt when we're going down */
4128 if (!test_bit(__IGB_DOWN, &adapter->state))
4129 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4132 if (adapter->vfs_allocated_count)
4133 wr32(E1000_IMS, E1000_IMS_LSC |
4135 E1000_IMS_DOUTSYNC);
4137 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC);
4138 wr32(E1000_EIMS, adapter->eims_other);
4143 static void igb_write_itr(struct igb_q_vector *q_vector)
4145 u32 itr_val = q_vector->itr_val & 0x7FFC;
4147 if (!q_vector->set_itr)
4153 if (q_vector->itr_shift)
4154 itr_val |= itr_val << q_vector->itr_shift;
4156 itr_val |= 0x8000000;
4158 writel(itr_val, q_vector->itr_register);
4159 q_vector->set_itr = 0;
4162 static irqreturn_t igb_msix_ring(int irq, void *data)
4164 struct igb_q_vector *q_vector = data;
4166 /* Write the ITR value calculated from the previous interrupt. */
4167 igb_write_itr(q_vector);
4169 napi_schedule(&q_vector->napi);
4174 #ifdef CONFIG_IGB_DCA
4175 static void igb_update_dca(struct igb_q_vector *q_vector)
4177 struct igb_adapter *adapter = q_vector->adapter;
4178 struct e1000_hw *hw = &adapter->hw;
4179 int cpu = get_cpu();
4181 if (q_vector->cpu == cpu)
4184 if (q_vector->tx_ring) {
4185 int q = q_vector->tx_ring->reg_idx;
4186 u32 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
4187 if (hw->mac.type == e1000_82575) {
4188 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
4189 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
4191 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
4192 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
4193 E1000_DCA_TXCTRL_CPUID_SHIFT;
4195 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
4196 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
4198 if (q_vector->rx_ring) {
4199 int q = q_vector->rx_ring->reg_idx;
4200 u32 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
4201 if (hw->mac.type == e1000_82575) {
4202 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
4203 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
4205 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
4206 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
4207 E1000_DCA_RXCTRL_CPUID_SHIFT;
4209 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
4210 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
4211 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
4212 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
4214 q_vector->cpu = cpu;
4219 static void igb_setup_dca(struct igb_adapter *adapter)
4221 struct e1000_hw *hw = &adapter->hw;
4224 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
4227 /* Always use CB2 mode, difference is masked in the CB driver. */
4228 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
4230 for (i = 0; i < adapter->num_q_vectors; i++) {
4231 struct igb_q_vector *q_vector = adapter->q_vector[i];
4233 igb_update_dca(q_vector);
4237 static int __igb_notify_dca(struct device *dev, void *data)
4239 struct net_device *netdev = dev_get_drvdata(dev);
4240 struct igb_adapter *adapter = netdev_priv(netdev);
4241 struct pci_dev *pdev = adapter->pdev;
4242 struct e1000_hw *hw = &adapter->hw;
4243 unsigned long event = *(unsigned long *)data;
4246 case DCA_PROVIDER_ADD:
4247 /* if already enabled, don't do it again */
4248 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
4250 if (dca_add_requester(dev) == 0) {
4251 adapter->flags |= IGB_FLAG_DCA_ENABLED;
4252 dev_info(&pdev->dev, "DCA enabled\n");
4253 igb_setup_dca(adapter);
4256 /* Fall Through since DCA is disabled. */
4257 case DCA_PROVIDER_REMOVE:
4258 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
4259 /* without this a class_device is left
4260 * hanging around in the sysfs model */
4261 dca_remove_requester(dev);
4262 dev_info(&pdev->dev, "DCA disabled\n");
4263 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
4264 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
4272 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
4277 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
4280 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4282 #endif /* CONFIG_IGB_DCA */
4284 static void igb_ping_all_vfs(struct igb_adapter *adapter)
4286 struct e1000_hw *hw = &adapter->hw;
4290 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
4291 ping = E1000_PF_CONTROL_MSG;
4292 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4293 ping |= E1000_VT_MSGTYPE_CTS;
4294 igb_write_mbx(hw, &ping, 1, i);
4298 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
4300 struct e1000_hw *hw = &adapter->hw;
4301 u32 vmolr = rd32(E1000_VMOLR(vf));
4302 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4304 vf_data->flags |= ~(IGB_VF_FLAG_UNI_PROMISC |
4305 IGB_VF_FLAG_MULTI_PROMISC);
4306 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
4308 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
4309 vmolr |= E1000_VMOLR_MPME;
4310 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
4313 * if we have hashes and we are clearing a multicast promisc
4314 * flag we need to write the hashes to the MTA as this step
4315 * was previously skipped
4317 if (vf_data->num_vf_mc_hashes > 30) {
4318 vmolr |= E1000_VMOLR_MPME;
4319 } else if (vf_data->num_vf_mc_hashes) {
4321 vmolr |= E1000_VMOLR_ROMPE;
4322 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
4323 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
4327 wr32(E1000_VMOLR(vf), vmolr);
4329 /* there are flags left unprocessed, likely not supported */
4330 if (*msgbuf & E1000_VT_MSGINFO_MASK)
4337 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
4338 u32 *msgbuf, u32 vf)
4340 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4341 u16 *hash_list = (u16 *)&msgbuf[1];
4342 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4345 /* salt away the number of multicast addresses assigned
4346 * to this VF for later use to restore when the PF multi cast
4349 vf_data->num_vf_mc_hashes = n;
4351 /* only up to 30 hash values supported */
4355 /* store the hashes for later use */
4356 for (i = 0; i < n; i++)
4357 vf_data->vf_mc_hashes[i] = hash_list[i];
4359 /* Flush and reset the mta with the new values */
4360 igb_set_rx_mode(adapter->netdev);
4365 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
4367 struct e1000_hw *hw = &adapter->hw;
4368 struct vf_data_storage *vf_data;
4371 for (i = 0; i < adapter->vfs_allocated_count; i++) {
4372 u32 vmolr = rd32(E1000_VMOLR(i));
4373 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
4375 vf_data = &adapter->vf_data[i];
4377 if ((vf_data->num_vf_mc_hashes > 30) ||
4378 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
4379 vmolr |= E1000_VMOLR_MPME;
4380 } else if (vf_data->num_vf_mc_hashes) {
4381 vmolr |= E1000_VMOLR_ROMPE;
4382 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
4383 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
4385 wr32(E1000_VMOLR(i), vmolr);
4389 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
4391 struct e1000_hw *hw = &adapter->hw;
4392 u32 pool_mask, reg, vid;
4395 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4397 /* Find the vlan filter for this id */
4398 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4399 reg = rd32(E1000_VLVF(i));
4401 /* remove the vf from the pool */
4404 /* if pool is empty then remove entry from vfta */
4405 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
4406 (reg & E1000_VLVF_VLANID_ENABLE)) {
4408 vid = reg & E1000_VLVF_VLANID_MASK;
4409 igb_vfta_set(hw, vid, false);
4412 wr32(E1000_VLVF(i), reg);
4415 adapter->vf_data[vf].vlans_enabled = 0;
4418 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
4420 struct e1000_hw *hw = &adapter->hw;
4423 /* The vlvf table only exists on 82576 hardware and newer */
4424 if (hw->mac.type < e1000_82576)
4427 /* we only need to do this if VMDq is enabled */
4428 if (!adapter->vfs_allocated_count)
4431 /* Find the vlan filter for this id */
4432 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4433 reg = rd32(E1000_VLVF(i));
4434 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
4435 vid == (reg & E1000_VLVF_VLANID_MASK))
4440 if (i == E1000_VLVF_ARRAY_SIZE) {
4441 /* Did not find a matching VLAN ID entry that was
4442 * enabled. Search for a free filter entry, i.e.
4443 * one without the enable bit set
4445 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4446 reg = rd32(E1000_VLVF(i));
4447 if (!(reg & E1000_VLVF_VLANID_ENABLE))
4451 if (i < E1000_VLVF_ARRAY_SIZE) {
4452 /* Found an enabled/available entry */
4453 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4455 /* if !enabled we need to set this up in vfta */
4456 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
4457 /* add VID to filter table */
4458 igb_vfta_set(hw, vid, true);
4459 reg |= E1000_VLVF_VLANID_ENABLE;
4461 reg &= ~E1000_VLVF_VLANID_MASK;
4463 wr32(E1000_VLVF(i), reg);
4465 /* do not modify RLPML for PF devices */
4466 if (vf >= adapter->vfs_allocated_count)
4469 if (!adapter->vf_data[vf].vlans_enabled) {
4471 reg = rd32(E1000_VMOLR(vf));
4472 size = reg & E1000_VMOLR_RLPML_MASK;
4474 reg &= ~E1000_VMOLR_RLPML_MASK;
4476 wr32(E1000_VMOLR(vf), reg);
4479 adapter->vf_data[vf].vlans_enabled++;
4483 if (i < E1000_VLVF_ARRAY_SIZE) {
4484 /* remove vf from the pool */
4485 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
4486 /* if pool is empty then remove entry from vfta */
4487 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
4489 igb_vfta_set(hw, vid, false);
4491 wr32(E1000_VLVF(i), reg);
4493 /* do not modify RLPML for PF devices */
4494 if (vf >= adapter->vfs_allocated_count)
4497 adapter->vf_data[vf].vlans_enabled--;
4498 if (!adapter->vf_data[vf].vlans_enabled) {
4500 reg = rd32(E1000_VMOLR(vf));
4501 size = reg & E1000_VMOLR_RLPML_MASK;
4503 reg &= ~E1000_VMOLR_RLPML_MASK;
4505 wr32(E1000_VMOLR(vf), reg);
4512 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
4514 struct e1000_hw *hw = &adapter->hw;
4517 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
4519 wr32(E1000_VMVIR(vf), 0);
4522 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
4523 int vf, u16 vlan, u8 qos)
4526 struct igb_adapter *adapter = netdev_priv(netdev);
4528 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
4531 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
4534 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
4535 igb_set_vmolr(adapter, vf, !vlan);
4536 adapter->vf_data[vf].pf_vlan = vlan;
4537 adapter->vf_data[vf].pf_qos = qos;
4538 dev_info(&adapter->pdev->dev,
4539 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
4540 if (test_bit(__IGB_DOWN, &adapter->state)) {
4541 dev_warn(&adapter->pdev->dev,
4542 "The VF VLAN has been set,"
4543 " but the PF device is not up.\n");
4544 dev_warn(&adapter->pdev->dev,
4545 "Bring the PF device up before"
4546 " attempting to use the VF device.\n");
4549 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
4551 igb_set_vmvir(adapter, vlan, vf);
4552 igb_set_vmolr(adapter, vf, true);
4553 adapter->vf_data[vf].pf_vlan = 0;
4554 adapter->vf_data[vf].pf_qos = 0;
4560 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
4562 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4563 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
4565 return igb_vlvf_set(adapter, vid, add, vf);
4568 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4571 adapter->vf_data[vf].flags &= ~(IGB_VF_FLAG_PF_SET_MAC);
4572 adapter->vf_data[vf].last_nack = jiffies;
4574 /* reset offloads to defaults */
4575 igb_set_vmolr(adapter, vf, true);
4577 /* reset vlans for device */
4578 igb_clear_vf_vfta(adapter, vf);
4579 if (adapter->vf_data[vf].pf_vlan)
4580 igb_ndo_set_vf_vlan(adapter->netdev, vf,
4581 adapter->vf_data[vf].pf_vlan,
4582 adapter->vf_data[vf].pf_qos);
4584 igb_clear_vf_vfta(adapter, vf);
4586 /* reset multicast table array for vf */
4587 adapter->vf_data[vf].num_vf_mc_hashes = 0;
4589 /* Flush and reset the mta with the new values */
4590 igb_set_rx_mode(adapter->netdev);
4593 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
4595 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
4597 /* generate a new mac address as we were hotplug removed/added */
4598 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
4599 random_ether_addr(vf_mac);
4601 /* process remaining reset events */
4602 igb_vf_reset(adapter, vf);
4605 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4607 struct e1000_hw *hw = &adapter->hw;
4608 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
4609 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4611 u8 *addr = (u8 *)(&msgbuf[1]);
4613 /* process all the same items cleared in a function level reset */
4614 igb_vf_reset(adapter, vf);
4616 /* set vf mac address */
4617 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4619 /* enable transmit and receive for vf */
4620 reg = rd32(E1000_VFTE);
4621 wr32(E1000_VFTE, reg | (1 << vf));
4622 reg = rd32(E1000_VFRE);
4623 wr32(E1000_VFRE, reg | (1 << vf));
4625 adapter->vf_data[vf].flags = IGB_VF_FLAG_CTS;
4627 /* reply to reset with ack and vf mac address */
4628 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
4629 memcpy(addr, vf_mac, 6);
4630 igb_write_mbx(hw, msgbuf, 3, vf);
4633 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
4635 unsigned char *addr = (char *)&msg[1];
4638 if (is_valid_ether_addr(addr))
4639 err = igb_set_vf_mac(adapter, vf, addr);
4644 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
4646 struct e1000_hw *hw = &adapter->hw;
4647 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4648 u32 msg = E1000_VT_MSGTYPE_NACK;
4650 /* if device isn't clear to send it shouldn't be reading either */
4651 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
4652 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4653 igb_write_mbx(hw, &msg, 1, vf);
4654 vf_data->last_nack = jiffies;
4658 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4660 struct pci_dev *pdev = adapter->pdev;
4661 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4662 struct e1000_hw *hw = &adapter->hw;
4663 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4666 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4669 /* if receive failed revoke VF CTS stats and restart init */
4670 dev_err(&pdev->dev, "Error receiving message from VF\n");
4671 vf_data->flags &= ~IGB_VF_FLAG_CTS;
4672 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
4677 /* this is a message we already processed, do nothing */
4678 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
4682 * until the vf completes a reset it should not be
4683 * allowed to start any configuration.
4686 if (msgbuf[0] == E1000_VF_RESET) {
4687 igb_vf_reset_msg(adapter, vf);
4691 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
4692 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
4698 switch ((msgbuf[0] & 0xFFFF)) {
4699 case E1000_VF_SET_MAC_ADDR:
4700 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
4702 case E1000_VF_SET_PROMISC:
4703 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
4705 case E1000_VF_SET_MULTICAST:
4706 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
4708 case E1000_VF_SET_LPE:
4709 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
4711 case E1000_VF_SET_VLAN:
4712 if (adapter->vf_data[vf].pf_vlan)
4715 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4718 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4723 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
4725 /* notify the VF of the results of what it sent us */
4727 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4729 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
4731 igb_write_mbx(hw, msgbuf, 1, vf);
4734 static void igb_msg_task(struct igb_adapter *adapter)
4736 struct e1000_hw *hw = &adapter->hw;
4739 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
4740 /* process any reset requests */
4741 if (!igb_check_for_rst(hw, vf))
4742 igb_vf_reset_event(adapter, vf);
4744 /* process any messages pending */
4745 if (!igb_check_for_msg(hw, vf))
4746 igb_rcv_msg_from_vf(adapter, vf);
4748 /* process any acks */
4749 if (!igb_check_for_ack(hw, vf))
4750 igb_rcv_ack_from_vf(adapter, vf);
4755 * igb_set_uta - Set unicast filter table address
4756 * @adapter: board private structure
4758 * The unicast table address is a register array of 32-bit registers.
4759 * The table is meant to be used in a way similar to how the MTA is used
4760 * however due to certain limitations in the hardware it is necessary to
4761 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscous
4762 * enable bit to allow vlan tag stripping when promiscous mode is enabled
4764 static void igb_set_uta(struct igb_adapter *adapter)
4766 struct e1000_hw *hw = &adapter->hw;
4769 /* The UTA table only exists on 82576 hardware and newer */
4770 if (hw->mac.type < e1000_82576)
4773 /* we only need to do this if VMDq is enabled */
4774 if (!adapter->vfs_allocated_count)
4777 for (i = 0; i < hw->mac.uta_reg_count; i++)
4778 array_wr32(E1000_UTA, i, ~0);
4782 * igb_intr_msi - Interrupt Handler
4783 * @irq: interrupt number
4784 * @data: pointer to a network interface device structure
4786 static irqreturn_t igb_intr_msi(int irq, void *data)
4788 struct igb_adapter *adapter = data;
4789 struct igb_q_vector *q_vector = adapter->q_vector[0];
4790 struct e1000_hw *hw = &adapter->hw;
4791 /* read ICR disables interrupts using IAM */
4792 u32 icr = rd32(E1000_ICR);
4794 igb_write_itr(q_vector);
4796 if (icr & E1000_ICR_DRSTA)
4797 schedule_work(&adapter->reset_task);
4799 if (icr & E1000_ICR_DOUTSYNC) {
4800 /* HW is reporting DMA is out of sync */
4801 adapter->stats.doosync++;
4804 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4805 hw->mac.get_link_status = 1;
4806 if (!test_bit(__IGB_DOWN, &adapter->state))
4807 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4810 napi_schedule(&q_vector->napi);
4816 * igb_intr - Legacy Interrupt Handler
4817 * @irq: interrupt number
4818 * @data: pointer to a network interface device structure
4820 static irqreturn_t igb_intr(int irq, void *data)
4822 struct igb_adapter *adapter = data;
4823 struct igb_q_vector *q_vector = adapter->q_vector[0];
4824 struct e1000_hw *hw = &adapter->hw;
4825 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
4826 * need for the IMC write */
4827 u32 icr = rd32(E1000_ICR);
4829 return IRQ_NONE; /* Not our interrupt */
4831 igb_write_itr(q_vector);
4833 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
4834 * not set, then the adapter didn't send an interrupt */
4835 if (!(icr & E1000_ICR_INT_ASSERTED))
4838 if (icr & E1000_ICR_DRSTA)
4839 schedule_work(&adapter->reset_task);
4841 if (icr & E1000_ICR_DOUTSYNC) {
4842 /* HW is reporting DMA is out of sync */
4843 adapter->stats.doosync++;
4846 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4847 hw->mac.get_link_status = 1;
4848 /* guard against interrupt when we're going down */
4849 if (!test_bit(__IGB_DOWN, &adapter->state))
4850 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4853 napi_schedule(&q_vector->napi);
4858 static inline void igb_ring_irq_enable(struct igb_q_vector *q_vector)
4860 struct igb_adapter *adapter = q_vector->adapter;
4861 struct e1000_hw *hw = &adapter->hw;
4863 if ((q_vector->rx_ring && (adapter->rx_itr_setting & 3)) ||
4864 (!q_vector->rx_ring && (adapter->tx_itr_setting & 3))) {
4865 if (!adapter->msix_entries)
4866 igb_set_itr(adapter);
4868 igb_update_ring_itr(q_vector);
4871 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4872 if (adapter->msix_entries)
4873 wr32(E1000_EIMS, q_vector->eims_value);
4875 igb_irq_enable(adapter);
4880 * igb_poll - NAPI Rx polling callback
4881 * @napi: napi polling structure
4882 * @budget: count of how many packets we should handle
4884 static int igb_poll(struct napi_struct *napi, int budget)
4886 struct igb_q_vector *q_vector = container_of(napi,
4887 struct igb_q_vector,
4889 int tx_clean_complete = 1, work_done = 0;
4891 #ifdef CONFIG_IGB_DCA
4892 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
4893 igb_update_dca(q_vector);
4895 if (q_vector->tx_ring)
4896 tx_clean_complete = igb_clean_tx_irq(q_vector);
4898 if (q_vector->rx_ring)
4899 igb_clean_rx_irq_adv(q_vector, &work_done, budget);
4901 if (!tx_clean_complete)
4904 /* If not enough Rx work done, exit the polling mode */
4905 if (work_done < budget) {
4906 napi_complete(napi);
4907 igb_ring_irq_enable(q_vector);
4914 * igb_systim_to_hwtstamp - convert system time value to hw timestamp
4915 * @adapter: board private structure
4916 * @shhwtstamps: timestamp structure to update
4917 * @regval: unsigned 64bit system time value.
4919 * We need to convert the system time value stored in the RX/TXSTMP registers
4920 * into a hwtstamp which can be used by the upper level timestamping functions
4922 static void igb_systim_to_hwtstamp(struct igb_adapter *adapter,
4923 struct skb_shared_hwtstamps *shhwtstamps,
4929 * The 82580 starts with 1ns at bit 0 in RX/TXSTMPL, shift this up to
4930 * 24 to match clock shift we setup earlier.
4932 if (adapter->hw.mac.type == e1000_82580)
4933 regval <<= IGB_82580_TSYNC_SHIFT;
4935 ns = timecounter_cyc2time(&adapter->clock, regval);
4936 timecompare_update(&adapter->compare, ns);
4937 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps));
4938 shhwtstamps->hwtstamp = ns_to_ktime(ns);
4939 shhwtstamps->syststamp = timecompare_transform(&adapter->compare, ns);
4943 * igb_tx_hwtstamp - utility function which checks for TX time stamp
4944 * @q_vector: pointer to q_vector containing needed info
4945 * @skb: packet that was just sent
4947 * If we were asked to do hardware stamping and such a time stamp is
4948 * available, then it must have been for this skb here because we only
4949 * allow only one such packet into the queue.
4951 static void igb_tx_hwtstamp(struct igb_q_vector *q_vector, struct sk_buff *skb)
4953 struct igb_adapter *adapter = q_vector->adapter;
4954 union skb_shared_tx *shtx = skb_tx(skb);
4955 struct e1000_hw *hw = &adapter->hw;
4956 struct skb_shared_hwtstamps shhwtstamps;
4959 /* if skb does not support hw timestamp or TX stamp not valid exit */
4960 if (likely(!shtx->hardware) ||
4961 !(rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID))
4964 regval = rd32(E1000_TXSTMPL);
4965 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
4967 igb_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
4968 skb_tstamp_tx(skb, &shhwtstamps);
4972 * igb_clean_tx_irq - Reclaim resources after transmit completes
4973 * @q_vector: pointer to q_vector containing needed info
4974 * returns true if ring is completely cleaned
4976 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
4978 struct igb_adapter *adapter = q_vector->adapter;
4979 struct igb_ring *tx_ring = q_vector->tx_ring;
4980 struct net_device *netdev = tx_ring->netdev;
4981 struct e1000_hw *hw = &adapter->hw;
4982 struct igb_buffer *buffer_info;
4983 struct sk_buff *skb;
4984 union e1000_adv_tx_desc *tx_desc, *eop_desc;
4985 unsigned int total_bytes = 0, total_packets = 0;
4986 unsigned int i, eop, count = 0;
4987 bool cleaned = false;
4989 i = tx_ring->next_to_clean;
4990 eop = tx_ring->buffer_info[i].next_to_watch;
4991 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4993 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
4994 (count < tx_ring->count)) {
4995 for (cleaned = false; !cleaned; count++) {
4996 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
4997 buffer_info = &tx_ring->buffer_info[i];
4998 cleaned = (i == eop);
4999 skb = buffer_info->skb;
5002 unsigned int segs, bytecount;
5003 /* gso_segs is currently only valid for tcp */
5004 segs = skb_shinfo(skb)->gso_segs ?: 1;
5005 /* multiply data chunks by size of headers */
5006 bytecount = ((segs - 1) * skb_headlen(skb)) +
5008 total_packets += segs;
5009 total_bytes += bytecount;
5011 igb_tx_hwtstamp(q_vector, skb);
5014 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
5015 tx_desc->wb.status = 0;
5018 if (i == tx_ring->count)
5021 eop = tx_ring->buffer_info[i].next_to_watch;
5022 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
5025 tx_ring->next_to_clean = i;
5027 if (unlikely(count &&
5028 netif_carrier_ok(netdev) &&
5029 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
5030 /* Make sure that anybody stopping the queue after this
5031 * sees the new next_to_clean.
5034 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
5035 !(test_bit(__IGB_DOWN, &adapter->state))) {
5036 netif_wake_subqueue(netdev, tx_ring->queue_index);
5037 tx_ring->tx_stats.restart_queue++;
5041 if (tx_ring->detect_tx_hung) {
5042 /* Detect a transmit hang in hardware, this serializes the
5043 * check with the clearing of time_stamp and movement of i */
5044 tx_ring->detect_tx_hung = false;
5045 if (tx_ring->buffer_info[i].time_stamp &&
5046 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
5047 (adapter->tx_timeout_factor * HZ)) &&
5048 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
5050 /* detected Tx unit hang */
5051 dev_err(&tx_ring->pdev->dev,
5052 "Detected Tx Unit Hang\n"
5056 " next_to_use <%x>\n"
5057 " next_to_clean <%x>\n"
5058 "buffer_info[next_to_clean]\n"
5059 " time_stamp <%lx>\n"
5060 " next_to_watch <%x>\n"
5062 " desc.status <%x>\n",
5063 tx_ring->queue_index,
5064 readl(tx_ring->head),
5065 readl(tx_ring->tail),
5066 tx_ring->next_to_use,
5067 tx_ring->next_to_clean,
5068 tx_ring->buffer_info[eop].time_stamp,
5071 eop_desc->wb.status);
5072 netif_stop_subqueue(netdev, tx_ring->queue_index);
5075 tx_ring->total_bytes += total_bytes;
5076 tx_ring->total_packets += total_packets;
5077 tx_ring->tx_stats.bytes += total_bytes;
5078 tx_ring->tx_stats.packets += total_packets;
5079 return (count < tx_ring->count);
5083 * igb_receive_skb - helper function to handle rx indications
5084 * @q_vector: structure containing interrupt and ring information
5085 * @skb: packet to send up
5086 * @vlan_tag: vlan tag for packet
5088 static void igb_receive_skb(struct igb_q_vector *q_vector,
5089 struct sk_buff *skb,
5092 struct igb_adapter *adapter = q_vector->adapter;
5095 vlan_gro_receive(&q_vector->napi, adapter->vlgrp,
5098 napi_gro_receive(&q_vector->napi, skb);
5101 static inline void igb_rx_checksum_adv(struct igb_ring *ring,
5102 u32 status_err, struct sk_buff *skb)
5104 skb->ip_summed = CHECKSUM_NONE;
5106 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
5107 if (!(ring->flags & IGB_RING_FLAG_RX_CSUM) ||
5108 (status_err & E1000_RXD_STAT_IXSM))
5111 /* TCP/UDP checksum error bit is set */
5113 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
5115 * work around errata with sctp packets where the TCPE aka
5116 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
5117 * packets, (aka let the stack check the crc32c)
5119 if ((skb->len == 60) &&
5120 (ring->flags & IGB_RING_FLAG_RX_SCTP_CSUM))
5121 ring->rx_stats.csum_err++;
5123 /* let the stack verify checksum errors */
5126 /* It must be a TCP or UDP packet with a valid checksum */
5127 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
5128 skb->ip_summed = CHECKSUM_UNNECESSARY;
5130 dev_dbg(&ring->pdev->dev, "cksum success: bits %08X\n", status_err);
5133 static inline void igb_rx_hwtstamp(struct igb_q_vector *q_vector, u32 staterr,
5134 struct sk_buff *skb)
5136 struct igb_adapter *adapter = q_vector->adapter;
5137 struct e1000_hw *hw = &adapter->hw;
5141 * If this bit is set, then the RX registers contain the time stamp. No
5142 * other packet will be time stamped until we read these registers, so
5143 * read the registers to make them available again. Because only one
5144 * packet can be time stamped at a time, we know that the register
5145 * values must belong to this one here and therefore we don't need to
5146 * compare any of the additional attributes stored for it.
5148 * If nothing went wrong, then it should have a skb_shared_tx that we
5149 * can turn into a skb_shared_hwtstamps.
5151 if (likely(!(staterr & E1000_RXDADV_STAT_TS)))
5153 if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
5156 regval = rd32(E1000_RXSTMPL);
5157 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
5159 igb_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
5161 static inline u16 igb_get_hlen(struct igb_ring *rx_ring,
5162 union e1000_adv_rx_desc *rx_desc)
5164 /* HW will not DMA in data larger than the given buffer, even if it
5165 * parses the (NFS, of course) header to be larger. In that case, it
5166 * fills the header buffer and spills the rest into the page.
5168 u16 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
5169 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
5170 if (hlen > rx_ring->rx_buffer_len)
5171 hlen = rx_ring->rx_buffer_len;
5175 static bool igb_clean_rx_irq_adv(struct igb_q_vector *q_vector,
5176 int *work_done, int budget)
5178 struct igb_ring *rx_ring = q_vector->rx_ring;
5179 struct net_device *netdev = rx_ring->netdev;
5180 struct pci_dev *pdev = rx_ring->pdev;
5181 union e1000_adv_rx_desc *rx_desc , *next_rxd;
5182 struct igb_buffer *buffer_info , *next_buffer;
5183 struct sk_buff *skb;
5184 bool cleaned = false;
5185 int cleaned_count = 0;
5186 int current_node = numa_node_id();
5187 unsigned int total_bytes = 0, total_packets = 0;
5193 i = rx_ring->next_to_clean;
5194 buffer_info = &rx_ring->buffer_info[i];
5195 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
5196 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
5198 while (staterr & E1000_RXD_STAT_DD) {
5199 if (*work_done >= budget)
5203 skb = buffer_info->skb;
5204 prefetch(skb->data - NET_IP_ALIGN);
5205 buffer_info->skb = NULL;
5208 if (i == rx_ring->count)
5211 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
5213 next_buffer = &rx_ring->buffer_info[i];
5215 length = le16_to_cpu(rx_desc->wb.upper.length);
5219 if (buffer_info->dma) {
5220 pci_unmap_single(pdev, buffer_info->dma,
5221 rx_ring->rx_buffer_len,
5222 PCI_DMA_FROMDEVICE);
5223 buffer_info->dma = 0;
5224 if (rx_ring->rx_buffer_len >= IGB_RXBUFFER_1024) {
5225 skb_put(skb, length);
5228 skb_put(skb, igb_get_hlen(rx_ring, rx_desc));
5232 pci_unmap_page(pdev, buffer_info->page_dma,
5233 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
5234 buffer_info->page_dma = 0;
5236 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
5238 buffer_info->page_offset,
5241 if ((page_count(buffer_info->page) != 1) ||
5242 (page_to_nid(buffer_info->page) != current_node))
5243 buffer_info->page = NULL;
5245 get_page(buffer_info->page);
5248 skb->data_len += length;
5249 skb->truesize += length;
5252 if (!(staterr & E1000_RXD_STAT_EOP)) {
5253 buffer_info->skb = next_buffer->skb;
5254 buffer_info->dma = next_buffer->dma;
5255 next_buffer->skb = skb;
5256 next_buffer->dma = 0;
5260 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
5261 dev_kfree_skb_irq(skb);
5265 igb_rx_hwtstamp(q_vector, staterr, skb);
5266 total_bytes += skb->len;
5269 igb_rx_checksum_adv(rx_ring, staterr, skb);
5271 skb->protocol = eth_type_trans(skb, netdev);
5272 skb_record_rx_queue(skb, rx_ring->queue_index);
5274 vlan_tag = ((staterr & E1000_RXD_STAT_VP) ?
5275 le16_to_cpu(rx_desc->wb.upper.vlan) : 0);
5277 igb_receive_skb(q_vector, skb, vlan_tag);
5280 rx_desc->wb.upper.status_error = 0;
5282 /* return some buffers to hardware, one at a time is too slow */
5283 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
5284 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
5288 /* use prefetched values */
5290 buffer_info = next_buffer;
5291 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
5294 rx_ring->next_to_clean = i;
5295 cleaned_count = igb_desc_unused(rx_ring);
5298 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
5300 rx_ring->total_packets += total_packets;
5301 rx_ring->total_bytes += total_bytes;
5302 rx_ring->rx_stats.packets += total_packets;
5303 rx_ring->rx_stats.bytes += total_bytes;
5308 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
5309 * @adapter: address of board private structure
5311 void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring, int cleaned_count)
5313 struct net_device *netdev = rx_ring->netdev;
5314 union e1000_adv_rx_desc *rx_desc;
5315 struct igb_buffer *buffer_info;
5316 struct sk_buff *skb;
5320 i = rx_ring->next_to_use;
5321 buffer_info = &rx_ring->buffer_info[i];
5323 bufsz = rx_ring->rx_buffer_len;
5325 while (cleaned_count--) {
5326 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
5328 if ((bufsz < IGB_RXBUFFER_1024) && !buffer_info->page_dma) {
5329 if (!buffer_info->page) {
5330 buffer_info->page = netdev_alloc_page(netdev);
5331 if (!buffer_info->page) {
5332 rx_ring->rx_stats.alloc_failed++;
5335 buffer_info->page_offset = 0;
5337 buffer_info->page_offset ^= PAGE_SIZE / 2;
5339 buffer_info->page_dma =
5340 pci_map_page(rx_ring->pdev, buffer_info->page,
5341 buffer_info->page_offset,
5343 PCI_DMA_FROMDEVICE);
5344 if (pci_dma_mapping_error(rx_ring->pdev,
5345 buffer_info->page_dma)) {
5346 buffer_info->page_dma = 0;
5347 rx_ring->rx_stats.alloc_failed++;
5352 skb = buffer_info->skb;
5354 skb = netdev_alloc_skb_ip_align(netdev, bufsz);
5356 rx_ring->rx_stats.alloc_failed++;
5360 buffer_info->skb = skb;
5362 if (!buffer_info->dma) {
5363 buffer_info->dma = pci_map_single(rx_ring->pdev,
5366 PCI_DMA_FROMDEVICE);
5367 if (pci_dma_mapping_error(rx_ring->pdev,
5368 buffer_info->dma)) {
5369 buffer_info->dma = 0;
5370 rx_ring->rx_stats.alloc_failed++;
5374 /* Refresh the desc even if buffer_addrs didn't change because
5375 * each write-back erases this info. */
5376 if (bufsz < IGB_RXBUFFER_1024) {
5377 rx_desc->read.pkt_addr =
5378 cpu_to_le64(buffer_info->page_dma);
5379 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
5381 rx_desc->read.pkt_addr = cpu_to_le64(buffer_info->dma);
5382 rx_desc->read.hdr_addr = 0;
5386 if (i == rx_ring->count)
5388 buffer_info = &rx_ring->buffer_info[i];
5392 if (rx_ring->next_to_use != i) {
5393 rx_ring->next_to_use = i;
5395 i = (rx_ring->count - 1);
5399 /* Force memory writes to complete before letting h/w
5400 * know there are new descriptors to fetch. (Only
5401 * applicable for weak-ordered memory model archs,
5402 * such as IA-64). */
5404 writel(i, rx_ring->tail);
5414 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5416 struct igb_adapter *adapter = netdev_priv(netdev);
5417 struct mii_ioctl_data *data = if_mii(ifr);
5419 if (adapter->hw.phy.media_type != e1000_media_type_copper)
5424 data->phy_id = adapter->hw.phy.addr;
5427 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
5439 * igb_hwtstamp_ioctl - control hardware time stamping
5444 * Outgoing time stamping can be enabled and disabled. Play nice and
5445 * disable it when requested, although it shouldn't case any overhead
5446 * when no packet needs it. At most one packet in the queue may be
5447 * marked for time stamping, otherwise it would be impossible to tell
5448 * for sure to which packet the hardware time stamp belongs.
5450 * Incoming time stamping has to be configured via the hardware
5451 * filters. Not all combinations are supported, in particular event
5452 * type has to be specified. Matching the kind of event packet is
5453 * not supported, with the exception of "all V2 events regardless of
5457 static int igb_hwtstamp_ioctl(struct net_device *netdev,
5458 struct ifreq *ifr, int cmd)
5460 struct igb_adapter *adapter = netdev_priv(netdev);
5461 struct e1000_hw *hw = &adapter->hw;
5462 struct hwtstamp_config config;
5463 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
5464 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
5465 u32 tsync_rx_cfg = 0;
5470 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
5473 /* reserved for future extensions */
5477 switch (config.tx_type) {
5478 case HWTSTAMP_TX_OFF:
5480 case HWTSTAMP_TX_ON:
5486 switch (config.rx_filter) {
5487 case HWTSTAMP_FILTER_NONE:
5490 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
5491 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
5492 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
5493 case HWTSTAMP_FILTER_ALL:
5495 * register TSYNCRXCFG must be set, therefore it is not
5496 * possible to time stamp both Sync and Delay_Req messages
5497 * => fall back to time stamping all packets
5499 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
5500 config.rx_filter = HWTSTAMP_FILTER_ALL;
5502 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
5503 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
5504 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
5507 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
5508 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
5509 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
5512 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
5513 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
5514 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
5515 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
5518 config.rx_filter = HWTSTAMP_FILTER_SOME;
5520 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
5521 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
5522 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
5523 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
5526 config.rx_filter = HWTSTAMP_FILTER_SOME;
5528 case HWTSTAMP_FILTER_PTP_V2_EVENT:
5529 case HWTSTAMP_FILTER_PTP_V2_SYNC:
5530 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
5531 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
5532 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
5539 if (hw->mac.type == e1000_82575) {
5540 if (tsync_rx_ctl | tsync_tx_ctl)
5545 /* enable/disable TX */
5546 regval = rd32(E1000_TSYNCTXCTL);
5547 regval &= ~E1000_TSYNCTXCTL_ENABLED;
5548 regval |= tsync_tx_ctl;
5549 wr32(E1000_TSYNCTXCTL, regval);
5551 /* enable/disable RX */
5552 regval = rd32(E1000_TSYNCRXCTL);
5553 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
5554 regval |= tsync_rx_ctl;
5555 wr32(E1000_TSYNCRXCTL, regval);
5557 /* define which PTP packets are time stamped */
5558 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
5560 /* define ethertype filter for timestamped packets */
5563 (E1000_ETQF_FILTER_ENABLE | /* enable filter */
5564 E1000_ETQF_1588 | /* enable timestamping */
5565 ETH_P_1588)); /* 1588 eth protocol type */
5567 wr32(E1000_ETQF(3), 0);
5569 #define PTP_PORT 319
5570 /* L4 Queue Filter[3]: filter by destination port and protocol */
5572 u32 ftqf = (IPPROTO_UDP /* UDP */
5573 | E1000_FTQF_VF_BP /* VF not compared */
5574 | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */
5575 | E1000_FTQF_MASK); /* mask all inputs */
5576 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */
5578 wr32(E1000_IMIR(3), htons(PTP_PORT));
5579 wr32(E1000_IMIREXT(3),
5580 (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP));
5581 if (hw->mac.type == e1000_82576) {
5582 /* enable source port check */
5583 wr32(E1000_SPQF(3), htons(PTP_PORT));
5584 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
5586 wr32(E1000_FTQF(3), ftqf);
5588 wr32(E1000_FTQF(3), E1000_FTQF_MASK);
5592 adapter->hwtstamp_config = config;
5594 /* clear TX/RX time stamp registers, just to be sure */
5595 regval = rd32(E1000_TXSTMPH);
5596 regval = rd32(E1000_RXSTMPH);
5598 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
5608 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5614 return igb_mii_ioctl(netdev, ifr, cmd);
5616 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
5622 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5624 struct igb_adapter *adapter = hw->back;
5627 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5629 return -E1000_ERR_CONFIG;
5631 pci_read_config_word(adapter->pdev, cap_offset + reg, value);
5636 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5638 struct igb_adapter *adapter = hw->back;
5641 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5643 return -E1000_ERR_CONFIG;
5645 pci_write_config_word(adapter->pdev, cap_offset + reg, *value);
5650 static void igb_vlan_rx_register(struct net_device *netdev,
5651 struct vlan_group *grp)
5653 struct igb_adapter *adapter = netdev_priv(netdev);
5654 struct e1000_hw *hw = &adapter->hw;
5657 igb_irq_disable(adapter);
5658 adapter->vlgrp = grp;
5661 /* enable VLAN tag insert/strip */
5662 ctrl = rd32(E1000_CTRL);
5663 ctrl |= E1000_CTRL_VME;
5664 wr32(E1000_CTRL, ctrl);
5666 /* Disable CFI check */
5667 rctl = rd32(E1000_RCTL);
5668 rctl &= ~E1000_RCTL_CFIEN;
5669 wr32(E1000_RCTL, rctl);
5671 /* disable VLAN tag insert/strip */
5672 ctrl = rd32(E1000_CTRL);
5673 ctrl &= ~E1000_CTRL_VME;
5674 wr32(E1000_CTRL, ctrl);
5677 igb_rlpml_set(adapter);
5679 if (!test_bit(__IGB_DOWN, &adapter->state))
5680 igb_irq_enable(adapter);
5683 static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
5685 struct igb_adapter *adapter = netdev_priv(netdev);
5686 struct e1000_hw *hw = &adapter->hw;
5687 int pf_id = adapter->vfs_allocated_count;
5689 /* attempt to add filter to vlvf array */
5690 igb_vlvf_set(adapter, vid, true, pf_id);
5692 /* add the filter since PF can receive vlans w/o entry in vlvf */
5693 igb_vfta_set(hw, vid, true);
5696 static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
5698 struct igb_adapter *adapter = netdev_priv(netdev);
5699 struct e1000_hw *hw = &adapter->hw;
5700 int pf_id = adapter->vfs_allocated_count;
5703 igb_irq_disable(adapter);
5704 vlan_group_set_device(adapter->vlgrp, vid, NULL);
5706 if (!test_bit(__IGB_DOWN, &adapter->state))
5707 igb_irq_enable(adapter);
5709 /* remove vlan from VLVF table array */
5710 err = igb_vlvf_set(adapter, vid, false, pf_id);
5712 /* if vid was not present in VLVF just remove it from table */
5714 igb_vfta_set(hw, vid, false);
5717 static void igb_restore_vlan(struct igb_adapter *adapter)
5719 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
5721 if (adapter->vlgrp) {
5723 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
5724 if (!vlan_group_get_device(adapter->vlgrp, vid))
5726 igb_vlan_rx_add_vid(adapter->netdev, vid);
5731 int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
5733 struct pci_dev *pdev = adapter->pdev;
5734 struct e1000_mac_info *mac = &adapter->hw.mac;
5739 case SPEED_10 + DUPLEX_HALF:
5740 mac->forced_speed_duplex = ADVERTISE_10_HALF;
5742 case SPEED_10 + DUPLEX_FULL:
5743 mac->forced_speed_duplex = ADVERTISE_10_FULL;
5745 case SPEED_100 + DUPLEX_HALF:
5746 mac->forced_speed_duplex = ADVERTISE_100_HALF;
5748 case SPEED_100 + DUPLEX_FULL:
5749 mac->forced_speed_duplex = ADVERTISE_100_FULL;
5751 case SPEED_1000 + DUPLEX_FULL:
5753 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
5755 case SPEED_1000 + DUPLEX_HALF: /* not supported */
5757 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
5763 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake)
5765 struct net_device *netdev = pci_get_drvdata(pdev);
5766 struct igb_adapter *adapter = netdev_priv(netdev);
5767 struct e1000_hw *hw = &adapter->hw;
5768 u32 ctrl, rctl, status;
5769 u32 wufc = adapter->wol;
5774 netif_device_detach(netdev);
5776 if (netif_running(netdev))
5779 igb_clear_interrupt_scheme(adapter);
5782 retval = pci_save_state(pdev);
5787 status = rd32(E1000_STATUS);
5788 if (status & E1000_STATUS_LU)
5789 wufc &= ~E1000_WUFC_LNKC;
5792 igb_setup_rctl(adapter);
5793 igb_set_rx_mode(netdev);
5795 /* turn on all-multi mode if wake on multicast is enabled */
5796 if (wufc & E1000_WUFC_MC) {
5797 rctl = rd32(E1000_RCTL);
5798 rctl |= E1000_RCTL_MPE;
5799 wr32(E1000_RCTL, rctl);
5802 ctrl = rd32(E1000_CTRL);
5803 /* advertise wake from D3Cold */
5804 #define E1000_CTRL_ADVD3WUC 0x00100000
5805 /* phy power management enable */
5806 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5807 ctrl |= E1000_CTRL_ADVD3WUC;
5808 wr32(E1000_CTRL, ctrl);
5810 /* Allow time for pending master requests to run */
5811 igb_disable_pcie_master(hw);
5813 wr32(E1000_WUC, E1000_WUC_PME_EN);
5814 wr32(E1000_WUFC, wufc);
5817 wr32(E1000_WUFC, 0);
5820 *enable_wake = wufc || adapter->en_mng_pt;
5822 igb_shutdown_serdes_link_82575(hw);
5824 /* Release control of h/w to f/w. If f/w is AMT enabled, this
5825 * would have already happened in close and is redundant. */
5826 igb_release_hw_control(adapter);
5828 pci_disable_device(pdev);
5834 static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
5839 retval = __igb_shutdown(pdev, &wake);
5844 pci_prepare_to_sleep(pdev);
5846 pci_wake_from_d3(pdev, false);
5847 pci_set_power_state(pdev, PCI_D3hot);
5853 static int igb_resume(struct pci_dev *pdev)
5855 struct net_device *netdev = pci_get_drvdata(pdev);
5856 struct igb_adapter *adapter = netdev_priv(netdev);
5857 struct e1000_hw *hw = &adapter->hw;
5860 pci_set_power_state(pdev, PCI_D0);
5861 pci_restore_state(pdev);
5863 err = pci_enable_device_mem(pdev);
5866 "igb: Cannot enable PCI device from suspend\n");
5869 pci_set_master(pdev);
5871 pci_enable_wake(pdev, PCI_D3hot, 0);
5872 pci_enable_wake(pdev, PCI_D3cold, 0);
5874 if (igb_init_interrupt_scheme(adapter)) {
5875 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
5879 /* e1000_power_up_phy(adapter); */
5883 /* let the f/w know that the h/w is now under the control of the
5885 igb_get_hw_control(adapter);
5887 wr32(E1000_WUS, ~0);
5889 if (netif_running(netdev)) {
5890 err = igb_open(netdev);
5895 netif_device_attach(netdev);
5901 static void igb_shutdown(struct pci_dev *pdev)
5905 __igb_shutdown(pdev, &wake);
5907 if (system_state == SYSTEM_POWER_OFF) {
5908 pci_wake_from_d3(pdev, wake);
5909 pci_set_power_state(pdev, PCI_D3hot);
5913 #ifdef CONFIG_NET_POLL_CONTROLLER
5915 * Polling 'interrupt' - used by things like netconsole to send skbs
5916 * without having to re-enable interrupts. It's not called while
5917 * the interrupt routine is executing.
5919 static void igb_netpoll(struct net_device *netdev)
5921 struct igb_adapter *adapter = netdev_priv(netdev);
5922 struct e1000_hw *hw = &adapter->hw;
5925 if (!adapter->msix_entries) {
5926 struct igb_q_vector *q_vector = adapter->q_vector[0];
5927 igb_irq_disable(adapter);
5928 napi_schedule(&q_vector->napi);
5932 for (i = 0; i < adapter->num_q_vectors; i++) {
5933 struct igb_q_vector *q_vector = adapter->q_vector[i];
5934 wr32(E1000_EIMC, q_vector->eims_value);
5935 napi_schedule(&q_vector->napi);
5938 #endif /* CONFIG_NET_POLL_CONTROLLER */
5941 * igb_io_error_detected - called when PCI error is detected
5942 * @pdev: Pointer to PCI device
5943 * @state: The current pci connection state
5945 * This function is called after a PCI bus error affecting
5946 * this device has been detected.
5948 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
5949 pci_channel_state_t state)
5951 struct net_device *netdev = pci_get_drvdata(pdev);
5952 struct igb_adapter *adapter = netdev_priv(netdev);
5954 netif_device_detach(netdev);
5956 if (state == pci_channel_io_perm_failure)
5957 return PCI_ERS_RESULT_DISCONNECT;
5959 if (netif_running(netdev))
5961 pci_disable_device(pdev);
5963 /* Request a slot slot reset. */
5964 return PCI_ERS_RESULT_NEED_RESET;
5968 * igb_io_slot_reset - called after the pci bus has been reset.
5969 * @pdev: Pointer to PCI device
5971 * Restart the card from scratch, as if from a cold-boot. Implementation
5972 * resembles the first-half of the igb_resume routine.
5974 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
5976 struct net_device *netdev = pci_get_drvdata(pdev);
5977 struct igb_adapter *adapter = netdev_priv(netdev);
5978 struct e1000_hw *hw = &adapter->hw;
5979 pci_ers_result_t result;
5982 if (pci_enable_device_mem(pdev)) {
5984 "Cannot re-enable PCI device after reset.\n");
5985 result = PCI_ERS_RESULT_DISCONNECT;
5987 pci_set_master(pdev);
5988 pci_restore_state(pdev);
5990 pci_enable_wake(pdev, PCI_D3hot, 0);
5991 pci_enable_wake(pdev, PCI_D3cold, 0);
5994 wr32(E1000_WUS, ~0);
5995 result = PCI_ERS_RESULT_RECOVERED;
5998 err = pci_cleanup_aer_uncorrect_error_status(pdev);
6000 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
6001 "failed 0x%0x\n", err);
6002 /* non-fatal, continue */
6009 * igb_io_resume - called when traffic can start flowing again.
6010 * @pdev: Pointer to PCI device
6012 * This callback is called when the error recovery driver tells us that
6013 * its OK to resume normal operation. Implementation resembles the
6014 * second-half of the igb_resume routine.
6016 static void igb_io_resume(struct pci_dev *pdev)
6018 struct net_device *netdev = pci_get_drvdata(pdev);
6019 struct igb_adapter *adapter = netdev_priv(netdev);
6021 if (netif_running(netdev)) {
6022 if (igb_up(adapter)) {
6023 dev_err(&pdev->dev, "igb_up failed after reset\n");
6028 netif_device_attach(netdev);
6030 /* let the f/w know that the h/w is now under the control of the
6032 igb_get_hw_control(adapter);
6035 static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
6038 u32 rar_low, rar_high;
6039 struct e1000_hw *hw = &adapter->hw;
6041 /* HW expects these in little endian so we reverse the byte order
6042 * from network order (big endian) to little endian
6044 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
6045 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
6046 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
6048 /* Indicate to hardware the Address is Valid. */
6049 rar_high |= E1000_RAH_AV;
6051 if (hw->mac.type == e1000_82575)
6052 rar_high |= E1000_RAH_POOL_1 * qsel;
6054 rar_high |= E1000_RAH_POOL_1 << qsel;
6056 wr32(E1000_RAL(index), rar_low);
6058 wr32(E1000_RAH(index), rar_high);
6062 static int igb_set_vf_mac(struct igb_adapter *adapter,
6063 int vf, unsigned char *mac_addr)
6065 struct e1000_hw *hw = &adapter->hw;
6066 /* VF MAC addresses start at end of receive addresses and moves
6067 * torwards the first, as a result a collision should not be possible */
6068 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
6070 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
6072 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
6077 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
6079 struct igb_adapter *adapter = netdev_priv(netdev);
6080 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
6082 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
6083 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
6084 dev_info(&adapter->pdev->dev, "Reload the VF driver to make this"
6085 " change effective.");
6086 if (test_bit(__IGB_DOWN, &adapter->state)) {
6087 dev_warn(&adapter->pdev->dev, "The VF MAC address has been set,"
6088 " but the PF device is not up.\n");
6089 dev_warn(&adapter->pdev->dev, "Bring the PF device up before"
6090 " attempting to use the VF device.\n");
6092 return igb_set_vf_mac(adapter, vf, mac);
6095 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
6100 static int igb_ndo_get_vf_config(struct net_device *netdev,
6101 int vf, struct ifla_vf_info *ivi)
6103 struct igb_adapter *adapter = netdev_priv(netdev);
6104 if (vf >= adapter->vfs_allocated_count)
6107 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
6109 ivi->vlan = adapter->vf_data[vf].pf_vlan;
6110 ivi->qos = adapter->vf_data[vf].pf_qos;
6114 static void igb_vmm_control(struct igb_adapter *adapter)
6116 struct e1000_hw *hw = &adapter->hw;
6119 /* replication is not supported for 82575 */
6120 if (hw->mac.type == e1000_82575)
6123 /* enable replication vlan tag stripping */
6124 reg = rd32(E1000_RPLOLR);
6125 reg |= E1000_RPLOLR_STRVLAN;
6126 wr32(E1000_RPLOLR, reg);
6128 /* notify HW that the MAC is adding vlan tags */
6129 reg = rd32(E1000_DTXCTL);
6130 reg |= E1000_DTXCTL_VLAN_ADDED;
6131 wr32(E1000_DTXCTL, reg);
6133 if (adapter->vfs_allocated_count) {
6134 igb_vmdq_set_loopback_pf(hw, true);
6135 igb_vmdq_set_replication_pf(hw, true);
6137 igb_vmdq_set_loopback_pf(hw, false);
6138 igb_vmdq_set_replication_pf(hw, false);