1 /*********************************************************************
3 * Filename: w83977af_ir.c
5 * Description: FIR driver for the Winbond W83977AF Super I/O chip
6 * Status: Experimental.
7 * Author: Paul VanderSpek
8 * Created at: Wed Nov 4 11:46:16 1998
9 * Modified at: Fri Jan 28 12:10:59 2000
10 * Modified by: Dag Brattli <dagb@cs.uit.no>
12 * Copyright (c) 1998-2000 Dag Brattli <dagb@cs.uit.no>
13 * Copyright (c) 1998-1999 Rebel.com
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * Neither Paul VanderSpek nor Rebel.com admit liability nor provide
21 * warranty for any of this software. This material is provided "AS-IS"
24 * If you find bugs in this file, its very likely that the same bug
25 * will also be in pc87108.c since the implementations are quite
28 * Notice that all functions that needs to access the chip in _any_
29 * way, must save BSR register on entry, and restore it on exit.
30 * It is _very_ important to follow this policy!
34 * bank = inb( iobase+BSR);
36 * do_your_stuff_here();
38 * outb( bank, iobase+BSR);
40 ********************************************************************/
42 #include <linux/module.h>
43 #include <linux/kernel.h>
44 #include <linux/types.h>
45 #include <linux/skbuff.h>
46 #include <linux/netdevice.h>
47 #include <linux/ioport.h>
48 #include <linux/delay.h>
49 #include <linux/slab.h>
50 #include <linux/init.h>
51 #include <linux/rtnetlink.h>
52 #include <linux/dma-mapping.h>
56 #include <asm/byteorder.h>
58 #include <net/irda/irda.h>
59 #include <net/irda/wrapper.h>
60 #include <net/irda/irda_device.h>
62 #include "w83977af_ir.h"
64 #ifdef CONFIG_ARCH_NETWINDER /* Adjust to NetWinder differences */
65 #undef CONFIG_NETWINDER_TX_DMA_PROBLEMS /* Not needed */
66 #define CONFIG_NETWINDER_RX_DMA_PROBLEMS /* Must have this one! */
68 #undef CONFIG_USE_INTERNAL_TIMER /* Just cannot make that timer work */
69 #define CONFIG_USE_W977_PNP /* Currently needed */
70 #define PIO_MAX_SPEED 115200
72 static char *driver_name = "w83977af_ir";
73 static int qos_mtt_bits = 0x07; /* 1 ms or more */
75 #define CHIP_IO_EXTENT 8
77 static unsigned int io[] = { 0x180, ~0, ~0, ~0 };
78 #ifdef CONFIG_ARCH_NETWINDER /* Adjust to NetWinder differences */
79 static unsigned int irq[] = { 6, 0, 0, 0 };
81 static unsigned int irq[] = { 11, 0, 0, 0 };
83 static unsigned int dma[] = { 1, 0, 0, 0 };
84 static unsigned int efbase[] = { W977_EFIO_BASE, W977_EFIO2_BASE };
85 static unsigned int efio = W977_EFIO_BASE;
87 static struct w83977af_ir *dev_self[] = { NULL, NULL, NULL, NULL};
90 static int w83977af_open(int i, unsigned int iobase, unsigned int irq,
92 static int w83977af_close(struct w83977af_ir *self);
93 static int w83977af_probe(int iobase, int irq, int dma);
94 static int w83977af_dma_receive(struct w83977af_ir *self);
95 static int w83977af_dma_receive_complete(struct w83977af_ir *self);
96 static netdev_tx_t w83977af_hard_xmit(struct sk_buff *skb,
97 struct net_device *dev);
98 static int w83977af_pio_write(int iobase, __u8 *buf, int len, int fifo_size);
99 static void w83977af_dma_write(struct w83977af_ir *self, int iobase);
100 static void w83977af_change_speed(struct w83977af_ir *self, __u32 speed);
101 static int w83977af_is_receiving(struct w83977af_ir *self);
103 static int w83977af_net_open(struct net_device *dev);
104 static int w83977af_net_close(struct net_device *dev);
105 static int w83977af_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
108 * Function w83977af_init ()
110 * Initialize chip. Just try to find out how many chips we are dealing with
113 static int __init w83977af_init(void)
117 IRDA_DEBUG(0, "%s()\n", __func__ );
119 for (i=0; i < ARRAY_SIZE(dev_self) && io[i] < 2000; i++) {
120 if (w83977af_open(i, io[i], irq[i], dma[i]) == 0)
127 * Function w83977af_cleanup ()
129 * Close all configured chips
132 static void __exit w83977af_cleanup(void)
136 IRDA_DEBUG(4, "%s()\n", __func__ );
138 for (i=0; i < ARRAY_SIZE(dev_self); i++) {
140 w83977af_close(dev_self[i]);
144 static const struct net_device_ops w83977_netdev_ops = {
145 .ndo_open = w83977af_net_open,
146 .ndo_stop = w83977af_net_close,
147 .ndo_start_xmit = w83977af_hard_xmit,
148 .ndo_do_ioctl = w83977af_net_ioctl,
152 * Function w83977af_open (iobase, irq)
154 * Open driver instance
157 static int w83977af_open(int i, unsigned int iobase, unsigned int irq,
160 struct net_device *dev;
161 struct w83977af_ir *self;
164 IRDA_DEBUG(0, "%s()\n", __func__ );
166 /* Lock the port that we need */
167 if (!request_region(iobase, CHIP_IO_EXTENT, driver_name)) {
168 IRDA_DEBUG(0, "%s(), can't get iobase of 0x%03x\n",
173 if (w83977af_probe(iobase, irq, dma) == -1) {
178 * Allocate new instance of the driver
180 dev = alloc_irdadev(sizeof(struct w83977af_ir));
182 printk( KERN_ERR "IrDA: Can't allocate memory for "
183 "IrDA control block!\n");
188 self = netdev_priv(dev);
189 spin_lock_init(&self->lock);
193 self->io.fir_base = iobase;
195 self->io.fir_ext = CHIP_IO_EXTENT;
197 self->io.fifo_size = 32;
199 /* Initialize QoS for this device */
200 irda_init_max_qos_capabilies(&self->qos);
202 /* The only value we must override it the baudrate */
204 /* FIXME: The HP HDLS-1100 does not support 1152000! */
205 self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600|
206 IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8);
208 /* The HP HDLS-1100 needs 1 ms according to the specs */
209 self->qos.min_turn_time.bits = qos_mtt_bits;
210 irda_qos_bits_to_value(&self->qos);
212 /* Max DMA buffer size needed = (data_size + 6) * (window_size) + 6; */
213 self->rx_buff.truesize = 14384;
214 self->tx_buff.truesize = 4000;
216 /* Allocate memory if needed */
218 dma_alloc_coherent(NULL, self->rx_buff.truesize,
219 &self->rx_buff_dma, GFP_KERNEL);
220 if (self->rx_buff.head == NULL) {
225 memset(self->rx_buff.head, 0, self->rx_buff.truesize);
228 dma_alloc_coherent(NULL, self->tx_buff.truesize,
229 &self->tx_buff_dma, GFP_KERNEL);
230 if (self->tx_buff.head == NULL) {
234 memset(self->tx_buff.head, 0, self->tx_buff.truesize);
236 self->rx_buff.in_frame = FALSE;
237 self->rx_buff.state = OUTSIDE_FRAME;
238 self->tx_buff.data = self->tx_buff.head;
239 self->rx_buff.data = self->rx_buff.head;
242 dev->netdev_ops = &w83977_netdev_ops;
244 err = register_netdev(dev);
246 IRDA_ERROR("%s(), register_netdevice() failed!\n", __func__);
249 IRDA_MESSAGE("IrDA: Registered device %s\n", dev->name);
251 /* Need to store self somewhere */
256 dma_free_coherent(NULL, self->tx_buff.truesize,
257 self->tx_buff.head, self->tx_buff_dma);
259 dma_free_coherent(NULL, self->rx_buff.truesize,
260 self->rx_buff.head, self->rx_buff_dma);
264 release_region(iobase, CHIP_IO_EXTENT);
269 * Function w83977af_close (self)
271 * Close driver instance
274 static int w83977af_close(struct w83977af_ir *self)
278 IRDA_DEBUG(0, "%s()\n", __func__ );
280 iobase = self->io.fir_base;
282 #ifdef CONFIG_USE_W977_PNP
283 /* enter PnP configuration mode */
284 w977_efm_enter(efio);
286 w977_select_device(W977_DEVICE_IR, efio);
288 /* Deactivate device */
289 w977_write_reg(0x30, 0x00, efio);
292 #endif /* CONFIG_USE_W977_PNP */
294 /* Remove netdevice */
295 unregister_netdev(self->netdev);
297 /* Release the PORT that this driver is using */
298 IRDA_DEBUG(0 , "%s(), Releasing Region %03x\n",
299 __func__ , self->io.fir_base);
300 release_region(self->io.fir_base, self->io.fir_ext);
302 if (self->tx_buff.head)
303 dma_free_coherent(NULL, self->tx_buff.truesize,
304 self->tx_buff.head, self->tx_buff_dma);
306 if (self->rx_buff.head)
307 dma_free_coherent(NULL, self->rx_buff.truesize,
308 self->rx_buff.head, self->rx_buff_dma);
310 free_netdev(self->netdev);
315 static int w83977af_probe(int iobase, int irq, int dma)
320 for (i=0; i < 2; i++) {
321 IRDA_DEBUG( 0, "%s()\n", __func__ );
322 #ifdef CONFIG_USE_W977_PNP
323 /* Enter PnP configuration mode */
324 w977_efm_enter(efbase[i]);
326 w977_select_device(W977_DEVICE_IR, efbase[i]);
328 /* Configure PnP port, IRQ, and DMA channel */
329 w977_write_reg(0x60, (iobase >> 8) & 0xff, efbase[i]);
330 w977_write_reg(0x61, (iobase) & 0xff, efbase[i]);
332 w977_write_reg(0x70, irq, efbase[i]);
333 #ifdef CONFIG_ARCH_NETWINDER
334 /* Netwinder uses 1 higher than Linux */
335 w977_write_reg(0x74, dma+1, efbase[i]);
337 w977_write_reg(0x74, dma, efbase[i]);
338 #endif /*CONFIG_ARCH_NETWINDER */
339 w977_write_reg(0x75, 0x04, efbase[i]); /* Disable Tx DMA */
341 /* Set append hardware CRC, enable IR bank selection */
342 w977_write_reg(0xf0, APEDCRC|ENBNKSEL, efbase[i]);
344 /* Activate device */
345 w977_write_reg(0x30, 0x01, efbase[i]);
347 w977_efm_exit(efbase[i]);
348 #endif /* CONFIG_USE_W977_PNP */
349 /* Disable Advanced mode */
350 switch_bank(iobase, SET2);
351 outb(iobase+2, 0x00);
353 /* Turn on UART (global) interrupts */
354 switch_bank(iobase, SET0);
355 outb(HCR_EN_IRQ, iobase+HCR);
357 /* Switch to advanced mode */
358 switch_bank(iobase, SET2);
359 outb(inb(iobase+ADCR1) | ADCR1_ADV_SL, iobase+ADCR1);
361 /* Set default IR-mode */
362 switch_bank(iobase, SET0);
363 outb(HCR_SIR, iobase+HCR);
365 /* Read the Advanced IR ID */
366 switch_bank(iobase, SET3);
367 version = inb(iobase+AUID);
370 if (0x10 == (version & 0xf0)) {
373 /* Set FIFO size to 32 */
374 switch_bank(iobase, SET2);
375 outb(ADCR2_RXFS32|ADCR2_TXFS32, iobase+ADCR2);
377 /* Set FIFO threshold to TX17, RX16 */
378 switch_bank(iobase, SET0);
379 outb(UFR_RXTL|UFR_TXTL|UFR_TXF_RST|UFR_RXF_RST|
380 UFR_EN_FIFO,iobase+UFR);
382 /* Receiver frame length */
383 switch_bank(iobase, SET4);
384 outb(2048 & 0xff, iobase+6);
385 outb((2048 >> 8) & 0x1f, iobase+7);
388 * Init HP HSDL-1100 transceiver.
390 * Set IRX_MSL since we have 2 * receive paths IRRX,
391 * and IRRXH. Clear IRSL0D since we want IRSL0 * to
392 * be a input pin used for IRRXH
394 * IRRX pin 37 connected to receiver
395 * IRTX pin 38 connected to transmitter
396 * FIRRX pin 39 connected to receiver (IRSL0)
397 * CIRRX pin 40 connected to pin 37
399 switch_bank(iobase, SET7);
400 outb(0x40, iobase+7);
402 IRDA_MESSAGE("W83977AF (IR) driver loaded. "
403 "Version: 0x%02x\n", version);
407 /* Try next extented function register address */
408 IRDA_DEBUG( 0, "%s(), Wrong chip version", __func__ );
414 static void w83977af_change_speed(struct w83977af_ir *self, __u32 speed)
416 int ir_mode = HCR_SIR;
420 iobase = self->io.fir_base;
422 /* Update accounting for new speed */
423 self->io.speed = speed;
425 /* Save current bank */
426 set = inb(iobase+SSR);
428 /* Disable interrupts */
429 switch_bank(iobase, SET0);
433 switch_bank(iobase, SET2);
434 outb(0x00, iobase+ABHL);
437 case 9600: outb(0x0c, iobase+ABLL); break;
438 case 19200: outb(0x06, iobase+ABLL); break;
439 case 38400: outb(0x03, iobase+ABLL); break;
440 case 57600: outb(0x02, iobase+ABLL); break;
441 case 115200: outb(0x01, iobase+ABLL); break;
443 ir_mode = HCR_MIR_576;
444 IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __func__ );
447 ir_mode = HCR_MIR_1152;
448 IRDA_DEBUG(0, "%s(), handling baud of 1152000\n", __func__ );
452 IRDA_DEBUG(0, "%s(), handling baud of 4000000\n", __func__ );
456 IRDA_DEBUG(0, "%s(), unknown baud rate of %d\n", __func__ , speed);
461 switch_bank(iobase, SET0);
462 outb(ir_mode, iobase+HCR);
464 /* set FIFO size to 32 */
465 switch_bank(iobase, SET2);
466 outb(ADCR2_RXFS32|ADCR2_TXFS32, iobase+ADCR2);
468 /* set FIFO threshold to TX17, RX16 */
469 switch_bank(iobase, SET0);
470 outb(0x00, iobase+UFR); /* Reset */
471 outb(UFR_EN_FIFO, iobase+UFR); /* First we must enable FIFO */
472 outb(0xa7, iobase+UFR);
474 netif_wake_queue(self->netdev);
476 /* Enable some interrupts so we can receive frames */
477 switch_bank(iobase, SET0);
478 if (speed > PIO_MAX_SPEED) {
479 outb(ICR_EFSFI, iobase+ICR);
480 w83977af_dma_receive(self);
482 outb(ICR_ERBRI, iobase+ICR);
485 outb(set, iobase+SSR);
489 * Function w83977af_hard_xmit (skb, dev)
491 * Sets up a DMA transfer to send the current frame.
494 static netdev_tx_t w83977af_hard_xmit(struct sk_buff *skb,
495 struct net_device *dev)
497 struct w83977af_ir *self;
503 self = netdev_priv(dev);
505 iobase = self->io.fir_base;
507 IRDA_DEBUG(4, "%s(%ld), skb->len=%d\n", __func__ , jiffies,
510 /* Lock transmit buffer */
511 netif_stop_queue(dev);
513 /* Check if we need to change the speed */
514 speed = irda_get_next_speed(skb);
515 if ((speed != self->io.speed) && (speed != -1)) {
516 /* Check for empty frame */
518 w83977af_change_speed(self, speed);
519 dev->trans_start = jiffies;
523 self->new_speed = speed;
526 /* Save current set */
527 set = inb(iobase+SSR);
529 /* Decide if we should use PIO or DMA transfer */
530 if (self->io.speed > PIO_MAX_SPEED) {
531 self->tx_buff.data = self->tx_buff.head;
532 skb_copy_from_linear_data(skb, self->tx_buff.data, skb->len);
533 self->tx_buff.len = skb->len;
535 mtt = irda_get_mtt(skb);
536 #ifdef CONFIG_USE_INTERNAL_TIMER
538 /* Adjust for timer resolution */
542 switch_bank(iobase, SET4);
543 outb(mtt & 0xff, iobase+TMRL);
544 outb((mtt >> 8) & 0x0f, iobase+TMRH);
547 outb(IR_MSL_EN_TMR, iobase+IR_MSL);
548 self->io.direction = IO_XMIT;
550 /* Enable timer interrupt */
551 switch_bank(iobase, SET0);
552 outb(ICR_ETMRI, iobase+ICR);
555 IRDA_DEBUG(4, "%s(%ld), mtt=%d\n", __func__ , jiffies, mtt);
559 /* Enable DMA interrupt */
560 switch_bank(iobase, SET0);
561 outb(ICR_EDMAI, iobase+ICR);
562 w83977af_dma_write(self, iobase);
563 #ifdef CONFIG_USE_INTERNAL_TIMER
567 self->tx_buff.data = self->tx_buff.head;
568 self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
569 self->tx_buff.truesize);
571 /* Add interrupt on tx low level (will fire immediately) */
572 switch_bank(iobase, SET0);
573 outb(ICR_ETXTHI, iobase+ICR);
575 dev->trans_start = jiffies;
578 /* Restore set register */
579 outb(set, iobase+SSR);
585 * Function w83977af_dma_write (self, iobase)
587 * Send frame using DMA
590 static void w83977af_dma_write(struct w83977af_ir *self, int iobase)
593 #ifdef CONFIG_NETWINDER_TX_DMA_PROBLEMS
597 IRDA_DEBUG(4, "%s(), len=%d\n", __func__ , self->tx_buff.len);
599 /* Save current set */
600 set = inb(iobase+SSR);
603 switch_bank(iobase, SET0);
604 outb(inb(iobase+HCR) & ~HCR_EN_DMA, iobase+HCR);
606 /* Choose transmit DMA channel */
607 switch_bank(iobase, SET2);
608 outb(ADCR1_D_CHSW|/*ADCR1_DMA_F|*/ADCR1_ADV_SL, iobase+ADCR1);
609 #ifdef CONFIG_NETWINDER_TX_DMA_PROBLEMS
610 spin_lock_irqsave(&self->lock, flags);
612 disable_dma(self->io.dma);
613 clear_dma_ff(self->io.dma);
614 set_dma_mode(self->io.dma, DMA_MODE_READ);
615 set_dma_addr(self->io.dma, self->tx_buff_dma);
616 set_dma_count(self->io.dma, self->tx_buff.len);
618 irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len,
621 self->io.direction = IO_XMIT;
624 switch_bank(iobase, SET0);
625 #ifdef CONFIG_NETWINDER_TX_DMA_PROBLEMS
626 hcr = inb(iobase+HCR);
627 outb(hcr | HCR_EN_DMA, iobase+HCR);
628 enable_dma(self->io.dma);
629 spin_unlock_irqrestore(&self->lock, flags);
631 outb(inb(iobase+HCR) | HCR_EN_DMA | HCR_TX_WT, iobase+HCR);
634 /* Restore set register */
635 outb(set, iobase+SSR);
639 * Function w83977af_pio_write (iobase, buf, len, fifo_size)
644 static int w83977af_pio_write(int iobase, __u8 *buf, int len, int fifo_size)
649 IRDA_DEBUG(4, "%s()\n", __func__ );
651 /* Save current bank */
652 set = inb(iobase+SSR);
654 switch_bank(iobase, SET0);
655 if (!(inb_p(iobase+USR) & USR_TSRE)) {
657 "%s(), warning, FIFO not empty yet!\n", __func__ );
660 IRDA_DEBUG(4, "%s(), %d bytes left in tx fifo\n",
661 __func__ , fifo_size);
664 /* Fill FIFO with current frame */
665 while ((fifo_size-- > 0) && (actual < len)) {
666 /* Transmit next byte */
667 outb(buf[actual++], iobase+TBR);
670 IRDA_DEBUG(4, "%s(), fifo_size %d ; %d sent of %d\n",
671 __func__ , fifo_size, actual, len);
674 outb(set, iobase+SSR);
680 * Function w83977af_dma_xmit_complete (self)
682 * The transfer of a frame in finished. So do the necessary things
686 static void w83977af_dma_xmit_complete(struct w83977af_ir *self)
691 IRDA_DEBUG(4, "%s(%ld)\n", __func__ , jiffies);
693 IRDA_ASSERT(self != NULL, return;);
695 iobase = self->io.fir_base;
697 /* Save current set */
698 set = inb(iobase+SSR);
701 switch_bank(iobase, SET0);
702 outb(inb(iobase+HCR) & ~HCR_EN_DMA, iobase+HCR);
704 /* Check for underrrun! */
705 if (inb(iobase+AUDR) & AUDR_UNDR) {
706 IRDA_DEBUG(0, "%s(), Transmit underrun!\n", __func__ );
708 self->netdev->stats.tx_errors++;
709 self->netdev->stats.tx_fifo_errors++;
711 /* Clear bit, by writing 1 to it */
712 outb(AUDR_UNDR, iobase+AUDR);
714 self->netdev->stats.tx_packets++;
717 if (self->new_speed) {
718 w83977af_change_speed(self, self->new_speed);
722 /* Unlock tx_buff and request another frame */
723 /* Tell the network layer, that we want more frames */
724 netif_wake_queue(self->netdev);
727 outb(set, iobase+SSR);
731 * Function w83977af_dma_receive (self)
733 * Get ready for receiving a frame. The device will initiate a DMA
734 * if it starts to receive a frame.
737 static int w83977af_dma_receive(struct w83977af_ir *self)
741 #ifdef CONFIG_NETWINDER_RX_DMA_PROBLEMS
745 IRDA_ASSERT(self != NULL, return -1;);
747 IRDA_DEBUG(4, "%s\n", __func__ );
749 iobase= self->io.fir_base;
751 /* Save current set */
752 set = inb(iobase+SSR);
755 switch_bank(iobase, SET0);
756 outb(inb(iobase+HCR) & ~HCR_EN_DMA, iobase+HCR);
758 /* Choose DMA Rx, DMA Fairness, and Advanced mode */
759 switch_bank(iobase, SET2);
760 outb((inb(iobase+ADCR1) & ~ADCR1_D_CHSW)/*|ADCR1_DMA_F*/|ADCR1_ADV_SL,
763 self->io.direction = IO_RECV;
764 self->rx_buff.data = self->rx_buff.head;
766 #ifdef CONFIG_NETWINDER_RX_DMA_PROBLEMS
767 spin_lock_irqsave(&self->lock, flags);
769 disable_dma(self->io.dma);
770 clear_dma_ff(self->io.dma);
771 set_dma_mode(self->io.dma, DMA_MODE_READ);
772 set_dma_addr(self->io.dma, self->rx_buff_dma);
773 set_dma_count(self->io.dma, self->rx_buff.truesize);
775 irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize,
779 * Reset Rx FIFO. This will also flush the ST_FIFO, it's very
780 * important that we don't reset the Tx FIFO since it might not
781 * be finished transmitting yet
783 switch_bank(iobase, SET0);
784 outb(UFR_RXTL|UFR_TXTL|UFR_RXF_RST|UFR_EN_FIFO, iobase+UFR);
785 self->st_fifo.len = self->st_fifo.tail = self->st_fifo.head = 0;
788 switch_bank(iobase, SET0);
789 #ifdef CONFIG_NETWINDER_RX_DMA_PROBLEMS
790 hcr = inb(iobase+HCR);
791 outb(hcr | HCR_EN_DMA, iobase+HCR);
792 enable_dma(self->io.dma);
793 spin_unlock_irqrestore(&self->lock, flags);
795 outb(inb(iobase+HCR) | HCR_EN_DMA, iobase+HCR);
798 outb(set, iobase+SSR);
804 * Function w83977af_receive_complete (self)
806 * Finished with receiving a frame
809 static int w83977af_dma_receive_complete(struct w83977af_ir *self)
812 struct st_fifo *st_fifo;
818 IRDA_DEBUG(4, "%s\n", __func__ );
820 st_fifo = &self->st_fifo;
822 iobase = self->io.fir_base;
824 /* Save current set */
825 set = inb(iobase+SSR);
827 iobase = self->io.fir_base;
829 /* Read status FIFO */
830 switch_bank(iobase, SET5);
831 while ((status = inb(iobase+FS_FO)) & FS_FO_FSFDR) {
832 st_fifo->entries[st_fifo->tail].status = status;
834 st_fifo->entries[st_fifo->tail].len = inb(iobase+RFLFL);
835 st_fifo->entries[st_fifo->tail].len |= inb(iobase+RFLFH) << 8;
841 while (st_fifo->len) {
842 /* Get first entry */
843 status = st_fifo->entries[st_fifo->head].status;
844 len = st_fifo->entries[st_fifo->head].len;
848 /* Check for errors */
849 if (status & FS_FO_ERR_MSK) {
850 if (status & FS_FO_LST_FR) {
851 /* Add number of lost frames to stats */
852 self->netdev->stats.rx_errors += len;
855 self->netdev->stats.rx_errors++;
857 self->rx_buff.data += len;
859 if (status & FS_FO_MX_LEX)
860 self->netdev->stats.rx_length_errors++;
862 if (status & FS_FO_PHY_ERR)
863 self->netdev->stats.rx_frame_errors++;
865 if (status & FS_FO_CRC_ERR)
866 self->netdev->stats.rx_crc_errors++;
868 /* The errors below can be reported in both cases */
869 if (status & FS_FO_RX_OV)
870 self->netdev->stats.rx_fifo_errors++;
872 if (status & FS_FO_FSF_OV)
873 self->netdev->stats.rx_fifo_errors++;
876 /* Check if we have transferred all data to memory */
877 switch_bank(iobase, SET0);
878 if (inb(iobase+USR) & USR_RDR) {
879 #ifdef CONFIG_USE_INTERNAL_TIMER
880 /* Put this entry back in fifo */
883 st_fifo->entries[st_fifo->head].status = status;
884 st_fifo->entries[st_fifo->head].len = len;
886 /* Restore set register */
887 outb(set, iobase+SSR);
889 return FALSE; /* I'll be back! */
891 udelay(80); /* Should be enough!? */
895 skb = dev_alloc_skb(len+1);
898 "%s(), memory squeeze, dropping frame.\n", __func__);
899 /* Restore set register */
900 outb(set, iobase+SSR);
905 /* Align to 20 bytes */
908 /* Copy frame without CRC */
909 if (self->io.speed < 4000000) {
911 skb_copy_to_linear_data(skb,
916 skb_copy_to_linear_data(skb,
921 /* Move to next frame */
922 self->rx_buff.data += len;
923 self->netdev->stats.rx_packets++;
925 skb->dev = self->netdev;
926 skb_reset_mac_header(skb);
927 skb->protocol = htons(ETH_P_IRDA);
931 /* Restore set register */
932 outb(set, iobase+SSR);
938 * Function pc87108_pio_receive (self)
940 * Receive all data in receiver FIFO
943 static void w83977af_pio_receive(struct w83977af_ir *self)
948 IRDA_DEBUG(4, "%s()\n", __func__ );
950 IRDA_ASSERT(self != NULL, return;);
952 iobase = self->io.fir_base;
954 /* Receive all characters in Rx FIFO */
956 byte = inb(iobase+RBR);
957 async_unwrap_char(self->netdev, &self->netdev->stats, &self->rx_buff,
959 } while (inb(iobase+USR) & USR_RDR); /* Data available */
963 * Function w83977af_sir_interrupt (self, eir)
965 * Handle SIR interrupt
968 static __u8 w83977af_sir_interrupt(struct w83977af_ir *self, int isr)
975 IRDA_DEBUG(4, "%s(), isr=%#x\n", __func__ , isr);
977 iobase = self->io.fir_base;
978 /* Transmit FIFO low on data */
979 if (isr & ISR_TXTH_I) {
980 /* Write data left in transmit buffer */
981 actual = w83977af_pio_write(self->io.fir_base,
986 self->tx_buff.data += actual;
987 self->tx_buff.len -= actual;
989 self->io.direction = IO_XMIT;
991 /* Check if finished */
992 if (self->tx_buff.len > 0) {
993 new_icr |= ICR_ETXTHI;
995 set = inb(iobase+SSR);
996 switch_bank(iobase, SET0);
997 outb(AUDR_SFEND, iobase+AUDR);
998 outb(set, iobase+SSR);
1000 self->netdev->stats.tx_packets++;
1002 /* Feed me more packets */
1003 netif_wake_queue(self->netdev);
1004 new_icr |= ICR_ETBREI;
1007 /* Check if transmission has completed */
1008 if (isr & ISR_TXEMP_I) {
1009 /* Check if we need to change the speed? */
1010 if (self->new_speed) {
1012 "%s(), Changing speed!\n", __func__ );
1013 w83977af_change_speed(self, self->new_speed);
1014 self->new_speed = 0;
1017 /* Turn around and get ready to receive some data */
1018 self->io.direction = IO_RECV;
1019 new_icr |= ICR_ERBRI;
1022 /* Rx FIFO threshold or timeout */
1023 if (isr & ISR_RXTH_I) {
1024 w83977af_pio_receive(self);
1026 /* Keep receiving */
1027 new_icr |= ICR_ERBRI;
1033 * Function pc87108_fir_interrupt (self, eir)
1035 * Handle MIR/FIR interrupt
1038 static __u8 w83977af_fir_interrupt(struct w83977af_ir *self, int isr)
1044 iobase = self->io.fir_base;
1045 set = inb(iobase+SSR);
1047 /* End of frame detected in FIFO */
1048 if (isr & (ISR_FEND_I|ISR_FSF_I)) {
1049 if (w83977af_dma_receive_complete(self)) {
1051 /* Wait for next status FIFO interrupt */
1052 new_icr |= ICR_EFSFI;
1054 /* DMA not finished yet */
1056 /* Set timer value, resolution 1 ms */
1057 switch_bank(iobase, SET4);
1058 outb(0x01, iobase+TMRL); /* 1 ms */
1059 outb(0x00, iobase+TMRH);
1062 outb(IR_MSL_EN_TMR, iobase+IR_MSL);
1064 new_icr |= ICR_ETMRI;
1067 /* Timer finished */
1068 if (isr & ISR_TMR_I) {
1070 switch_bank(iobase, SET4);
1071 outb(0, iobase+IR_MSL);
1073 /* Clear timer event */
1074 /* switch_bank(iobase, SET0); */
1075 /* outb(ASCR_CTE, iobase+ASCR); */
1077 /* Check if this is a TX timer interrupt */
1078 if (self->io.direction == IO_XMIT) {
1079 w83977af_dma_write(self, iobase);
1081 new_icr |= ICR_EDMAI;
1083 /* Check if DMA has now finished */
1084 w83977af_dma_receive_complete(self);
1086 new_icr |= ICR_EFSFI;
1089 /* Finished with DMA */
1090 if (isr & ISR_DMA_I) {
1091 w83977af_dma_xmit_complete(self);
1093 /* Check if there are more frames to be transmitted */
1094 /* if (irda_device_txqueue_empty(self)) { */
1096 /* Prepare for receive
1098 * ** Netwinder Tx DMA likes that we do this anyway **
1100 w83977af_dma_receive(self);
1101 new_icr = ICR_EFSFI;
1106 outb(set, iobase+SSR);
1112 * Function w83977af_interrupt (irq, dev_id, regs)
1114 * An interrupt from the chip has arrived. Time to do some work
1117 static irqreturn_t w83977af_interrupt(int irq, void *dev_id)
1119 struct net_device *dev = dev_id;
1120 struct w83977af_ir *self;
1124 self = netdev_priv(dev);
1126 iobase = self->io.fir_base;
1128 /* Save current bank */
1129 set = inb(iobase+SSR);
1130 switch_bank(iobase, SET0);
1132 icr = inb(iobase+ICR);
1133 isr = inb(iobase+ISR) & icr; /* Mask out the interesting ones */
1135 outb(0, iobase+ICR); /* Disable interrupts */
1138 /* Dispatch interrupt handler for the current speed */
1139 if (self->io.speed > PIO_MAX_SPEED )
1140 icr = w83977af_fir_interrupt(self, isr);
1142 icr = w83977af_sir_interrupt(self, isr);
1145 outb(icr, iobase+ICR); /* Restore (new) interrupts */
1146 outb(set, iobase+SSR); /* Restore bank register */
1147 return IRQ_RETVAL(isr);
1151 * Function w83977af_is_receiving (self)
1153 * Return TRUE is we are currently receiving a frame
1156 static int w83977af_is_receiving(struct w83977af_ir *self)
1162 IRDA_ASSERT(self != NULL, return FALSE;);
1164 if (self->io.speed > 115200) {
1165 iobase = self->io.fir_base;
1167 /* Check if rx FIFO is not empty */
1168 set = inb(iobase+SSR);
1169 switch_bank(iobase, SET2);
1170 if ((inb(iobase+RXFDTH) & 0x3f) != 0) {
1171 /* We are receiving something */
1174 outb(set, iobase+SSR);
1176 status = (self->rx_buff.state != OUTSIDE_FRAME);
1182 * Function w83977af_net_open (dev)
1187 static int w83977af_net_open(struct net_device *dev)
1189 struct w83977af_ir *self;
1194 IRDA_DEBUG(0, "%s()\n", __func__ );
1196 IRDA_ASSERT(dev != NULL, return -1;);
1197 self = netdev_priv(dev);
1199 IRDA_ASSERT(self != NULL, return 0;);
1201 iobase = self->io.fir_base;
1203 if (request_irq(self->io.irq, w83977af_interrupt, 0, dev->name,
1208 * Always allocate the DMA channel after the IRQ,
1209 * and clean up on failure.
1211 if (request_dma(self->io.dma, dev->name)) {
1212 free_irq(self->io.irq, self);
1216 /* Save current set */
1217 set = inb(iobase+SSR);
1219 /* Enable some interrupts so we can receive frames again */
1220 switch_bank(iobase, SET0);
1221 if (self->io.speed > 115200) {
1222 outb(ICR_EFSFI, iobase+ICR);
1223 w83977af_dma_receive(self);
1225 outb(ICR_ERBRI, iobase+ICR);
1227 /* Restore bank register */
1228 outb(set, iobase+SSR);
1230 /* Ready to play! */
1231 netif_start_queue(dev);
1233 /* Give self a hardware name */
1234 sprintf(hwname, "w83977af @ 0x%03x", self->io.fir_base);
1237 * Open new IrLAP layer instance, now that everything should be
1238 * initialized properly
1240 self->irlap = irlap_open(dev, &self->qos, hwname);
1246 * Function w83977af_net_close (dev)
1251 static int w83977af_net_close(struct net_device *dev)
1253 struct w83977af_ir *self;
1257 IRDA_DEBUG(0, "%s()\n", __func__ );
1259 IRDA_ASSERT(dev != NULL, return -1;);
1261 self = netdev_priv(dev);
1263 IRDA_ASSERT(self != NULL, return 0;);
1265 iobase = self->io.fir_base;
1268 netif_stop_queue(dev);
1270 /* Stop and remove instance of IrLAP */
1272 irlap_close(self->irlap);
1275 disable_dma(self->io.dma);
1277 /* Save current set */
1278 set = inb(iobase+SSR);
1280 /* Disable interrupts */
1281 switch_bank(iobase, SET0);
1282 outb(0, iobase+ICR);
1284 free_irq(self->io.irq, dev);
1285 free_dma(self->io.dma);
1287 /* Restore bank register */
1288 outb(set, iobase+SSR);
1294 * Function w83977af_net_ioctl (dev, rq, cmd)
1296 * Process IOCTL commands for this device
1299 static int w83977af_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1301 struct if_irda_req *irq = (struct if_irda_req *) rq;
1302 struct w83977af_ir *self;
1303 unsigned long flags;
1306 IRDA_ASSERT(dev != NULL, return -1;);
1308 self = netdev_priv(dev);
1310 IRDA_ASSERT(self != NULL, return -1;);
1312 IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __func__ , dev->name, cmd);
1314 spin_lock_irqsave(&self->lock, flags);
1317 case SIOCSBANDWIDTH: /* Set bandwidth */
1318 if (!capable(CAP_NET_ADMIN)) {
1322 w83977af_change_speed(self, irq->ifr_baudrate);
1324 case SIOCSMEDIABUSY: /* Set media busy */
1325 if (!capable(CAP_NET_ADMIN)) {
1329 irda_device_set_media_busy(self->netdev, TRUE);
1331 case SIOCGRECEIVING: /* Check if we are receiving right now */
1332 irq->ifr_receiving = w83977af_is_receiving(self);
1338 spin_unlock_irqrestore(&self->lock, flags);
1342 MODULE_AUTHOR("Dag Brattli <dagb@cs.uit.no>");
1343 MODULE_DESCRIPTION("Winbond W83977AF IrDA Device Driver");
1344 MODULE_LICENSE("GPL");
1347 module_param(qos_mtt_bits, int, 0);
1348 MODULE_PARM_DESC(qos_mtt_bits, "Mimimum Turn Time");
1349 module_param_array(io, int, NULL, 0);
1350 MODULE_PARM_DESC(io, "Base I/O addresses");
1351 module_param_array(irq, int, NULL, 0);
1352 MODULE_PARM_DESC(irq, "IRQ lines");
1355 * Function init_module (void)
1360 module_init(w83977af_init);
1363 * Function cleanup_module (void)
1368 module_exit(w83977af_cleanup);