drivers/net/ixgbe/ixgbe_82598.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/pci.h>
  29 #include <linux/delay.h>
  30 #include <linux/sched.h>
  31
  32 #include "ixgbe.h"
  33 #include "ixgbe_phy.h"
  34
  35 #define IXGBE_82598_MAX_TX_QUEUES 32
  36 #define IXGBE_82598_MAX_RX_QUEUES 64
  37 #define IXGBE_82598_RAR_ENTRIES   16
  38 #define IXGBE_82598_MC_TBL_SIZE  128
  39 #define IXGBE_82598_VFT_TBL_SIZE 128
  40
  41 static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
  42                                              ixgbe_link_speed *speed,
  43                                              bool *autoneg);
  44 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw);
  45 static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
  46                                                ixgbe_link_speed speed,
  47                                                bool autoneg,
  48                                                bool autoneg_wait_to_complete);
  49 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
  50                                        u8 *eeprom_data);
  51
  52 /**
  53  *  ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count
  54  *  @hw: pointer to hardware structure
  55  *
  56  *  Read PCIe configuration space, and get the MSI-X vector count from
  57  *  the capabilities table.
  58  **/
  59 static u16 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw)
  60 {
  61         struct ixgbe_adapter *adapter = hw->back;
  62         u16 msix_count;
  63         pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82598_CAPS,
  64                              &msix_count);
  65         msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
  66
  67         /* MSI-X count is zero-based in HW, so increment to give proper value */
  68         msix_count++;
  69
  70         return msix_count;
  71 }
  72
  73 /**
  74  */
  75 static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
  76 {
  77         struct ixgbe_mac_info *mac = &hw->mac;
  78
  79         /* Call PHY identify routine to get the phy type */
  80         ixgbe_identify_phy_generic(hw);
  81
  82         mac->mcft_size = IXGBE_82598_MC_TBL_SIZE;
  83         mac->vft_size = IXGBE_82598_VFT_TBL_SIZE;
  84         mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES;
  85         mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES;
  86         mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES;
  87         mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw);
  88
  89         return 0;
  90 }
  91
  92 /**
  93  *  ixgbe_init_phy_ops_82598 - PHY/SFP specific init
  94  *  @hw: pointer to hardware structure
  95  *
  96  *  Initialize any function pointers that were not able to be
  97  *  set during get_invariants because the PHY/SFP type was
  98  *  not known.  Perform the SFP init if necessary.
  99  *
 100  **/
 101 s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)
 102 {
 103         struct ixgbe_mac_info *mac = &hw->mac;
 104         struct ixgbe_phy_info *phy = &hw->phy;
 105         s32 ret_val = 0;
 106         u16 list_offset, data_offset;
 107
 108         /* Identify the PHY */
 109         phy->ops.identify(hw);
 110
 111         /* Overwrite the link function pointers if copper PHY */
 112         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
 113                 mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
 114                 mac->ops.setup_link_speed =
 115                                      &ixgbe_setup_copper_link_speed_82598;
 116                 mac->ops.get_link_capabilities =
 117                                   &ixgbe_get_copper_link_capabilities_82598;
 118         }
 119
 120         switch (hw->phy.type) {
 121         case ixgbe_phy_tn:
 122                 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
 123                 phy->ops.get_firmware_version =
 124                              &ixgbe_get_phy_firmware_version_tnx;
 125                 break;
 126         case ixgbe_phy_nl:
 127                 phy->ops.reset = &ixgbe_reset_phy_nl;
 128
 129                 /* Call SFP+ identify routine to get the SFP+ module type */
 130                 ret_val = phy->ops.identify_sfp(hw);
 131                 if (ret_val != 0)
 132                         goto out;
 133                 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {
 134                         ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
 135                         goto out;
 136                 }
 137
 138                 /* Check to see if SFP+ module is supported */
 139                 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
 140                                                             &list_offset,
 141                                                             &data_offset);
 142                 if (ret_val != 0) {
 143                         ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
 144                         goto out;
 145                 }
 146                 break;
 147         default:
 148                 break;
 149         }
 150
 151 out:
 152         return ret_val;
 153 }
 154
 155 /**
 156  *  ixgbe_get_link_capabilities_82598 - Determines link capabilities
 157  *  @hw: pointer to hardware structure
 158  *  @speed: pointer to link speed
 159  *  @autoneg: boolean auto-negotiation value
 160  *
 161  *  Determines the link capabilities by reading the AUTOC register.
 162  **/
 163 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
 164                                              ixgbe_link_speed *speed,
 165                                              bool *autoneg)
 166 {
 167         s32 status = 0;
 168         u32 autoc = 0;
 169
 170         /*
 171          * Determine link capabilities based on the stored value of AUTOC,
 172          * which represents EEPROM defaults.  If AUTOC value has not been
 173          * stored, use the current register value.
 174          */
 175         if (hw->mac.orig_link_settings_stored)
 176                 autoc = hw->mac.orig_autoc;
 177         else
 178                 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 179
 180         switch (autoc & IXGBE_AUTOC_LMS_MASK) {
 181         case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
 182                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 183                 *autoneg = false;
 184                 break;
 185
 186         case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
 187                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
 188                 *autoneg = false;
 189                 break;
 190
 191         case IXGBE_AUTOC_LMS_1G_AN:
 192                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 193                 *autoneg = true;
 194                 break;
 195
 196         case IXGBE_AUTOC_LMS_KX4_AN:
 197         case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
 198                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
 199                 if (autoc & IXGBE_AUTOC_KX4_SUPP)
 200                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 201                 if (autoc & IXGBE_AUTOC_KX_SUPP)
 202                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 203                 *autoneg = true;
 204                 break;
 205
 206         default:
 207                 status = IXGBE_ERR_LINK_SETUP;
 208                 break;
 209         }
 210
 211         return status;
 212 }
 213
 214 /**
 215  *  ixgbe_get_copper_link_capabilities_82598 - Determines link capabilities
 216  *  @hw: pointer to hardware structure
 217  *  @speed: pointer to link speed
 218  *  @autoneg: boolean auto-negotiation value
 219  *
 220  *  Determines the link capabilities by reading the AUTOC register.
 221  **/
 222 static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
 223                                                     ixgbe_link_speed *speed,
 224                                                     bool *autoneg)
 225 {
 226         s32 status = IXGBE_ERR_LINK_SETUP;
 227         u16 speed_ability;
 228
 229         *speed = 0;
 230         *autoneg = true;
 231
 232         status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
 233                                       &speed_ability);
 234
 235         if (status == 0) {
 236                 if (speed_ability & MDIO_SPEED_10G)
 237                     *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 238                 if (speed_ability & MDIO_PMA_SPEED_1000)
 239                     *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 240         }
 241
 242         return status;
 243 }
 244
 245 /**
 246  *  ixgbe_get_media_type_82598 - Determines media type
 247  *  @hw: pointer to hardware structure
 248  *
 249  *  Returns the media type (fiber, copper, backplane)
 250  **/
 251 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
 252 {
 253         enum ixgbe_media_type media_type;
 254
 255         /* Media type for I82598 is based on device ID */
 256         switch (hw->device_id) {
 257         case IXGBE_DEV_ID_82598:
 258         case IXGBE_DEV_ID_82598_BX:
 259                 media_type = ixgbe_media_type_backplane;
 260                 break;
 261         case IXGBE_DEV_ID_82598AF_DUAL_PORT:
 262         case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
 263         case IXGBE_DEV_ID_82598EB_CX4:
 264         case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
 265         case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
 266         case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
 267         case IXGBE_DEV_ID_82598EB_XF_LR:
 268         case IXGBE_DEV_ID_82598EB_SFP_LOM:
 269                 media_type = ixgbe_media_type_fiber;
 270                 break;
 271         case IXGBE_DEV_ID_82598AT:
 272         case IXGBE_DEV_ID_82598AT2:
 273                 media_type = ixgbe_media_type_copper;
 274                 break;
 275         default:
 276                 media_type = ixgbe_media_type_unknown;
 277                 break;
 278         }
 279
 280         return media_type;
 281 }
 282
 283 /**
 284  *  ixgbe_fc_enable_82598 - Enable flow control
 285  *  @hw: pointer to hardware structure
 286  *  @packetbuf_num: packet buffer number (0-7)
 287  *
 288  *  Enable flow control according to the current settings.
 289  **/
 290 static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
 291 {
 292         s32 ret_val = 0;
 293         u32 fctrl_reg;
 294         u32 rmcs_reg;
 295         u32 reg;
 296
 297 #ifdef CONFIG_DCB
 298         if (hw->fc.requested_mode == ixgbe_fc_pfc)
 299                 goto out;
 300
 301 #endif /* CONFIG_DCB */
 302         /* Negotiate the fc mode to use */
 303         ret_val = ixgbe_fc_autoneg(hw);
 304         if (ret_val)
 305                 goto out;
 306
 307         /* Disable any previous flow control settings */
 308         fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
 309         fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
 310
 311         rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
 312         rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
 313
 314         /*
 315          * The possible values of fc.current_mode are:
 316          * 0: Flow control is completely disabled
 317          * 1: Rx flow control is enabled (we can receive pause frames,
 318          *    but not send pause frames).
 319          * 2: Tx flow control is enabled (we can send pause frames but
 320          *     we do not support receiving pause frames).
 321          * 3: Both Rx and Tx flow control (symmetric) are enabled.
 322          * other: Invalid.
 323 #ifdef CONFIG_DCB
 324          * 4: Priority Flow Control is enabled.
 325 #endif
 326          */
 327         switch (hw->fc.current_mode) {
 328         case ixgbe_fc_none:
 329                 /*
 330                  * Flow control is disabled by software override or autoneg.
 331                  * The code below will actually disable it in the HW.
 332                  */
 333                 break;
 334         case ixgbe_fc_rx_pause:
 335                 /*
 336                  * Rx Flow control is enabled and Tx Flow control is
 337                  * disabled by software override. Since there really
 338                  * isn't a way to advertise that we are capable of RX
 339                  * Pause ONLY, we will advertise that we support both
 340                  * symmetric and asymmetric Rx PAUSE.  Later, we will
 341                  * disable the adapter's ability to send PAUSE frames.
 342                  */
 343                 fctrl_reg |= IXGBE_FCTRL_RFCE;
 344                 break;
 345         case ixgbe_fc_tx_pause:
 346                 /*
 347                  * Tx Flow control is enabled, and Rx Flow control is
 348                  * disabled by software override.
 349                  */
 350                 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
 351                 break;
 352         case ixgbe_fc_full:
 353                 /* Flow control (both Rx and Tx) is enabled by SW override. */
 354                 fctrl_reg |= IXGBE_FCTRL_RFCE;
 355                 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
 356                 break;
 357 #ifdef CONFIG_DCB
 358         case ixgbe_fc_pfc:
 359                 goto out;
 360                 break;
 361 #endif /* CONFIG_DCB */
 362         default:
 363                 hw_dbg(hw, "Flow control param set incorrectly\n");
 364                 ret_val = -IXGBE_ERR_CONFIG;
 365                 goto out;
 366                 break;
 367         }
 368
 369         /* Set 802.3x based flow control settings. */
 370         fctrl_reg |= IXGBE_FCTRL_DPF;
 371         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);
 372         IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
 373
 374         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
 375         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
 376                 if (hw->fc.send_xon) {
 377                         IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
 378                                         (hw->fc.low_water | IXGBE_FCRTL_XONE));
 379                 } else {
 380                         IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
 381                                         hw->fc.low_water);
 382                 }
 383
 384                 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num),
 385                                 (hw->fc.high_water | IXGBE_FCRTH_FCEN));
 386         }
 387
 388         /* Configure pause time (2 TCs per register) */
 389         reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
 390         if ((packetbuf_num & 1) == 0)
 391                 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
 392         else
 393                 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
 394         IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
 395
 396         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
 397
 398 out:
 399         return ret_val;
 400 }
 401
 402 /**
 403  *  ixgbe_setup_mac_link_82598 - Configures MAC link settings
 404  *  @hw: pointer to hardware structure
 405  *
 406  *  Configures link settings based on values in the ixgbe_hw struct.
 407  *  Restarts the link.  Performs autonegotiation if needed.
 408  **/
 409 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw)
 410 {
 411         u32 autoc_reg;
 412         u32 links_reg;
 413         u32 i;
 414         s32 status = 0;
 415
 416         /* Restart link */
 417         autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 418         autoc_reg |= IXGBE_AUTOC_AN_RESTART;
 419         IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
 420
 421         /* Only poll for autoneg to complete if specified to do so */
 422         if (hw->phy.autoneg_wait_to_complete) {
 423                 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
 424                      IXGBE_AUTOC_LMS_KX4_AN ||
 425                     (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
 426                      IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
 427                         links_reg = 0; /* Just in case Autoneg time = 0 */
 428                         for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
 429                                 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
 430                                 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
 431                                         break;
 432                                 msleep(100);
 433                         }
 434                         if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
 435                                 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
 436                                 hw_dbg(hw, "Autonegotiation did not complete.\n");
 437                         }
 438                 }
 439         }
 440
 441         /* Add delay to filter out noises during initial link setup */
 442         msleep(50);
 443
 444         return status;
 445 }
 446
 447 /**
 448  *  ixgbe_check_mac_link_82598 - Get link/speed status
 449  *  @hw: pointer to hardware structure
 450  *  @speed: pointer to link speed
 451  *  @link_up: true is link is up, false otherwise
 452  *  @link_up_wait_to_complete: bool used to wait for link up or not
 453  *
 454  *  Reads the links register to determine if link is up and the current speed
 455  **/
 456 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
 457                                       ixgbe_link_speed *speed, bool *link_up,
 458                                       bool link_up_wait_to_complete)
 459 {
 460         u32 links_reg;
 461         u32 i;
 462         u16 link_reg, adapt_comp_reg;
 463
 464         /*
 465          * SERDES PHY requires us to read link status from register 0xC79F.
 466          * Bit 0 set indicates link is up/ready; clear indicates link down.
 467          * 0xC00C is read to check that the XAUI lanes are active.  Bit 0
 468          * clear indicates active; set indicates inactive.
 469          */
 470         if (hw->phy.type == ixgbe_phy_nl) {
 471                 hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg);
 472                 hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg);
 473                 hw->phy.ops.read_reg(hw, 0xC00C, MDIO_MMD_PMAPMD,
 474                                      &adapt_comp_reg);
 475                 if (link_up_wait_to_complete) {
 476                         for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
 477                                 if ((link_reg & 1) &&
 478                                     ((adapt_comp_reg & 1) == 0)) {
 479                                         *link_up = true;
 480                                         break;
 481                                 } else {
 482                                         *link_up = false;
 483                                 }
 484                                 msleep(100);
 485                                 hw->phy.ops.read_reg(hw, 0xC79F,
 486                                                      MDIO_MMD_PMAPMD,
 487                                                      &link_reg);
 488                                 hw->phy.ops.read_reg(hw, 0xC00C,
 489                                                      MDIO_MMD_PMAPMD,
 490                                                      &adapt_comp_reg);
 491                         }
 492                 } else {
 493                         if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0))
 494                                 *link_up = true;
 495                         else
 496                                 *link_up = false;
 497                 }
 498
 499                 if (*link_up == false)
 500                         goto out;
 501         }
 502
 503         links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
 504         if (link_up_wait_to_complete) {
 505                 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
 506                         if (links_reg & IXGBE_LINKS_UP) {
 507                                 *link_up = true;
 508                                 break;
 509                         } else {
 510                                 *link_up = false;
 511                         }
 512                         msleep(100);
 513                         links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
 514                 }
 515         } else {
 516                 if (links_reg & IXGBE_LINKS_UP)
 517                         *link_up = true;
 518                 else
 519                         *link_up = false;
 520         }
 521
 522         if (links_reg & IXGBE_LINKS_SPEED)
 523                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
 524         else
 525                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 526
 527         /* if link is down, zero out the current_mode */
 528         if (*link_up == false) {
 529                 hw->fc.current_mode = ixgbe_fc_none;
 530                 hw->fc.fc_was_autonegged = false;
 531         }
 532 out:
 533         return 0;
 534 }
 535
 536
 537 /**
 538  *  ixgbe_setup_mac_link_speed_82598 - Set MAC link speed
 539  *  @hw: pointer to hardware structure
 540  *  @speed: new link speed
 541  *  @autoneg: true if auto-negotiation enabled
 542  *  @autoneg_wait_to_complete: true if waiting is needed to complete
 543  *
 544  *  Set the link speed in the AUTOC register and restarts link.
 545  **/
 546 static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
 547                                            ixgbe_link_speed speed, bool autoneg,
 548                                            bool autoneg_wait_to_complete)
 549 {
 550         s32              status            = 0;
 551         ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
 552         u32              curr_autoc        = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 553         u32              autoc             = curr_autoc;
 554         u32              link_mode         = autoc & IXGBE_AUTOC_LMS_MASK;
 555
 556         /* Check to see if speed passed in is supported. */
 557         ixgbe_get_link_capabilities_82598(hw, &link_capabilities, &autoneg);
 558         speed &= link_capabilities;
 559
 560         if (speed == IXGBE_LINK_SPEED_UNKNOWN)
 561                 status = IXGBE_ERR_LINK_SETUP;
 562
 563         /* Set KX4/KX support according to speed requested */
 564         else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
 565                  link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
 566                 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;
 567                 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 568                         autoc |= IXGBE_AUTOC_KX4_SUPP;
 569                 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 570                         autoc |= IXGBE_AUTOC_KX_SUPP;
 571                 if (autoc != curr_autoc)
 572                         IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
 573         }
 574
 575         if (status == 0) {
 576                 hw->phy.autoneg_wait_to_complete = autoneg_wait_to_complete;
 577
 578                 /*
 579                  * Setup and restart the link based on the new values in
 580                  * ixgbe_hw This will write the AUTOC register based on the new
 581                  * stored values
 582                  */
 583                 status = ixgbe_setup_mac_link_82598(hw);
 584         }
 585
 586         return status;
 587 }
 588
 589
 590 /**
 591  *  ixgbe_setup_copper_link_82598 - Setup copper link settings
 592  *  @hw: pointer to hardware structure
 593  *
 594  *  Configures link settings based on values in the ixgbe_hw struct.
 595  *  Restarts the link.  Performs autonegotiation if needed.  Restart
 596  *  phy and wait for autonegotiate to finish.  Then synchronize the
 597  *  MAC and PHY.
 598  **/
 599 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw)
 600 {
 601         s32 status;
 602
 603         /* Restart autonegotiation on PHY */
 604         status = hw->phy.ops.setup_link(hw);
 605
 606         /* Set up MAC */
 607         ixgbe_setup_mac_link_82598(hw);
 608
 609         return status;
 610 }
 611
 612 /**
 613  *  ixgbe_setup_copper_link_speed_82598 - Set the PHY autoneg advertised field
 614  *  @hw: pointer to hardware structure
 615  *  @speed: new link speed
 616  *  @autoneg: true if autonegotiation enabled
 617  *  @autoneg_wait_to_complete: true if waiting is needed to complete
 618  *
 619  *  Sets the link speed in the AUTOC register in the MAC and restarts link.
 620  **/
 621 static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
 622                                                ixgbe_link_speed speed,
 623                                                bool autoneg,
 624                                                bool autoneg_wait_to_complete)
 625 {
 626         s32 status;
 627
 628         /* Setup the PHY according to input speed */
 629         status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
 630                                               autoneg_wait_to_complete);
 631
 632         /* Set up MAC */
 633         ixgbe_setup_mac_link_82598(hw);
 634
 635         return status;
 636 }
 637
 638 /**
 639  *  ixgbe_reset_hw_82598 - Performs hardware reset
 640  *  @hw: pointer to hardware structure
 641  *
 642  *  Resets the hardware by resetting the transmit and receive units, masks and
 643  *  clears all interrupts, performing a PHY reset, and performing a link (MAC)
 644  *  reset.
 645  **/
 646 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
 647 {
 648         s32 status = 0;
 649         s32 phy_status = 0;
 650         u32 ctrl;
 651         u32 gheccr;
 652         u32 i;
 653         u32 autoc;
 654         u8  analog_val;
 655
 656         /* Call adapter stop to disable tx/rx and clear interrupts */
 657         hw->mac.ops.stop_adapter(hw);
 658
 659         /*
 660          * Power up the Atlas Tx lanes if they are currently powered down.
 661          * Atlas Tx lanes are powered down for MAC loopback tests, but
 662          * they are not automatically restored on reset.
 663          */
 664         hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
 665         if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
 666                 /* Enable Tx Atlas so packets can be transmitted again */
 667                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
 668                                              &analog_val);
 669                 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
 670                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
 671                                               analog_val);
 672
 673                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
 674                                              &analog_val);
 675                 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
 676                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
 677                                               analog_val);
 678
 679                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
 680                                              &analog_val);
 681                 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
 682                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
 683                                               analog_val);
 684
 685                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
 686                                              &analog_val);
 687                 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
 688                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
 689                                               analog_val);
 690         }
 691
 692         /* Reset PHY */
 693         if (hw->phy.reset_disable == false) {
 694                 /* PHY ops must be identified and initialized prior to reset */
 695
 696                 /* Init PHY and function pointers, perform SFP setup */
 697                 phy_status = hw->phy.ops.init(hw);
 698                 if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED)
 699                         goto reset_hw_out;
 700                 else if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT)
 701                         goto no_phy_reset;
 702
 703
 704                 hw->phy.ops.reset(hw);
 705         }
 706
 707 no_phy_reset:
 708         /*
 709          * Prevent the PCI-E bus from from hanging by disabling PCI-E master
 710          * access and verify no pending requests before reset
 711          */
 712         status = ixgbe_disable_pcie_master(hw);
 713         if (status != 0) {
 714                 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
 715                 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
 716         }
 717
 718         /*
 719          * Issue global reset to the MAC.  This needs to be a SW reset.
 720          * If link reset is used, it might reset the MAC when mng is using it
 721          */
 722         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
 723         IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
 724         IXGBE_WRITE_FLUSH(hw);
 725
 726         /* Poll for reset bit to self-clear indicating reset is complete */
 727         for (i = 0; i < 10; i++) {
 728                 udelay(1);
 729                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
 730                 if (!(ctrl & IXGBE_CTRL_RST))
 731                         break;
 732         }
 733         if (ctrl & IXGBE_CTRL_RST) {
 734                 status = IXGBE_ERR_RESET_FAILED;
 735                 hw_dbg(hw, "Reset polling failed to complete.\n");
 736         }
 737
 738         msleep(50);
 739
 740         gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
 741         gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
 742         IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
 743
 744         /*
 745          * Store the original AUTOC value if it has not been
 746          * stored off yet.  Otherwise restore the stored original
 747          * AUTOC value since the reset operation sets back to deaults.
 748          */
 749         autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 750         if (hw->mac.orig_link_settings_stored == false) {
 751                 hw->mac.orig_autoc = autoc;
 752                 hw->mac.orig_link_settings_stored = true;
 753         } else if (autoc != hw->mac.orig_autoc) {
 754                 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
 755         }
 756
 757         /*
 758          * Store MAC address from RAR0, clear receive address registers, and
 759          * clear the multicast table
 760          */
 761         hw->mac.ops.init_rx_addrs(hw);
 762
 763         /* Store the permanent mac address */
 764         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
 765
 766 reset_hw_out:
 767         if (phy_status)
 768                 status = phy_status;
 769
 770         return status;
 771 }
 772
 773 /**
 774  *  ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
 775  *  @hw: pointer to hardware struct
 776  *  @rar: receive address register index to associate with a VMDq index
 777  *  @vmdq: VMDq set index
 778  **/
 779 static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
 780 {
 781         u32 rar_high;
 782
 783         rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
 784         rar_high &= ~IXGBE_RAH_VIND_MASK;
 785         rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);
 786         IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
 787         return 0;
 788 }
 789
 790 /**
 791  *  ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
 792  *  @hw: pointer to hardware struct
 793  *  @rar: receive address register index to associate with a VMDq index
 794  *  @vmdq: VMDq clear index (not used in 82598, but elsewhere)
 795  **/
 796 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
 797 {
 798         u32 rar_high;
 799         u32 rar_entries = hw->mac.num_rar_entries;
 800
 801         if (rar < rar_entries) {
 802                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
 803                 if (rar_high & IXGBE_RAH_VIND_MASK) {
 804                         rar_high &= ~IXGBE_RAH_VIND_MASK;
 805                         IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
 806                 }
 807         } else {
 808                 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
 809         }
 810
 811         return 0;
 812 }
 813
 814 /**
 815  *  ixgbe_set_vfta_82598 - Set VLAN filter table
 816  *  @hw: pointer to hardware structure
 817  *  @vlan: VLAN id to write to VLAN filter
 818  *  @vind: VMDq output index that maps queue to VLAN id in VFTA
 819  *  @vlan_on: boolean flag to turn on/off VLAN in VFTA
 820  *
 821  *  Turn on/off specified VLAN in the VLAN filter table.
 822  **/
 823 static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
 824                                 bool vlan_on)
 825 {
 826         u32 regindex;
 827         u32 bitindex;
 828         u32 bits;
 829         u32 vftabyte;
 830
 831         if (vlan > 4095)
 832                 return IXGBE_ERR_PARAM;
 833
 834         /* Determine 32-bit word position in array */
 835         regindex = (vlan >> 5) & 0x7F;   /* upper seven bits */
 836
 837         /* Determine the location of the (VMD) queue index */
 838         vftabyte =  ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
 839         bitindex = (vlan & 0x7) << 2;    /* lower 3 bits indicate nibble */
 840
 841         /* Set the nibble for VMD queue index */
 842         bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));
 843         bits &= (~(0x0F << bitindex));
 844         bits |= (vind << bitindex);
 845         IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);
 846
 847         /* Determine the location of the bit for this VLAN id */
 848         bitindex = vlan & 0x1F;   /* lower five bits */
 849
 850         bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
 851         if (vlan_on)
 852                 /* Turn on this VLAN id */
 853                 bits |= (1 << bitindex);
 854         else
 855                 /* Turn off this VLAN id */
 856                 bits &= ~(1 << bitindex);
 857         IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
 858
 859         return 0;
 860 }
 861
 862 /**
 863  *  ixgbe_clear_vfta_82598 - Clear VLAN filter table
 864  *  @hw: pointer to hardware structure
 865  *
 866  *  Clears the VLAN filer table, and the VMDq index associated with the filter
 867  **/
 868 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
 869 {
 870         u32 offset;
 871         u32 vlanbyte;
 872
 873         for (offset = 0; offset < hw->mac.vft_size; offset++)
 874                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
 875
 876         for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
 877                 for (offset = 0; offset < hw->mac.vft_size; offset++)
 878                         IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
 879                                         0);
 880
 881         return 0;
 882 }
 883
 884 /**
 885  *  ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
 886  *  @hw: pointer to hardware structure
 887  *  @reg: analog register to read
 888  *  @val: read value
 889  *
 890  *  Performs read operation to Atlas analog register specified.
 891  **/
 892 static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
 893 {
 894         u32  atlas_ctl;
 895
 896         IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
 897                         IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
 898         IXGBE_WRITE_FLUSH(hw);
 899         udelay(10);
 900         atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
 901         *val = (u8)atlas_ctl;
 902
 903         return 0;
 904 }
 905
 906 /**
 907  *  ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
 908  *  @hw: pointer to hardware structure
 909  *  @reg: atlas register to write
 910  *  @val: value to write
 911  *
 912  *  Performs write operation to Atlas analog register specified.
 913  **/
 914 static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
 915 {
 916         u32  atlas_ctl;
 917
 918         atlas_ctl = (reg << 8) | val;
 919         IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
 920         IXGBE_WRITE_FLUSH(hw);
 921         udelay(10);
 922
 923         return 0;
 924 }
 925
 926 /**
 927  *  ixgbe_read_i2c_eeprom_82598 - Read 8 bit EEPROM word of an SFP+ module
 928  *  over I2C interface through an intermediate phy.
 929  *  @hw: pointer to hardware structure
 930  *  @byte_offset: EEPROM byte offset to read
 931  *  @eeprom_data: value read
 932  *
 933  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
 934  **/
 935 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
 936                                        u8 *eeprom_data)
 937 {
 938         s32 status = 0;
 939         u16 sfp_addr = 0;
 940         u16 sfp_data = 0;
 941         u16 sfp_stat = 0;
 942         u32 i;
 943
 944         if (hw->phy.type == ixgbe_phy_nl) {
 945                 /*
 946                  * phy SDA/SCL registers are at addresses 0xC30A to
 947                  * 0xC30D.  These registers are used to talk to the SFP+
 948                  * module's EEPROM through the SDA/SCL (I2C) interface.
 949                  */
 950                 sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset;
 951                 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
 952                 hw->phy.ops.write_reg(hw,
 953                                       IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
 954                                       MDIO_MMD_PMAPMD,
 955                                       sfp_addr);
 956
 957                 /* Poll status */
 958                 for (i = 0; i < 100; i++) {
 959                         hw->phy.ops.read_reg(hw,
 960                                              IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
 961                                              MDIO_MMD_PMAPMD,
 962                                              &sfp_stat);
 963                         sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
 964                         if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
 965                                 break;
 966                         msleep(10);
 967                 }
 968
 969                 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
 970                         hw_dbg(hw, "EEPROM read did not pass.\n");
 971                         status = IXGBE_ERR_SFP_NOT_PRESENT;
 972                         goto out;
 973                 }
 974
 975                 /* Read data */
 976                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
 977                                      MDIO_MMD_PMAPMD, &sfp_data);
 978
 979                 *eeprom_data = (u8)(sfp_data >> 8);
 980         } else {
 981                 status = IXGBE_ERR_PHY;
 982                 goto out;
 983         }
 984
 985 out:
 986         return status;
 987 }
 988
 989 /**
 990  *  ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
 991  *  @hw: pointer to hardware structure
 992  *
 993  *  Determines physical layer capabilities of the current configuration.
 994  **/
 995 static u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
 996 {
 997         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
 998         u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 999         u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1000         u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1001         u16 ext_ability = 0;
1002
1003         hw->phy.ops.identify(hw);
1004
1005         /* Copper PHY must be checked before AUTOC LMS to determine correct
1006          * physical layer because 10GBase-T PHYs use LMS = KX4/KX */
1007         if (hw->phy.type == ixgbe_phy_tn ||
1008             hw->phy.type == ixgbe_phy_cu_unknown) {
1009                 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
1010                                      &ext_ability);
1011                 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
1012                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1013                 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
1014                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1015                 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
1016                         physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1017                 goto out;
1018         }
1019
1020         switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1021         case IXGBE_AUTOC_LMS_1G_AN:
1022         case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1023                 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX)
1024                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1025                 else
1026                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1027                 break;
1028         case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1029                 if (pma_pmd_10g == IXGBE_AUTOC_10G_CX4)
1030                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1031                 else if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4)
1032                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1033                 else /* XAUI */
1034                         physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1035                 break;
1036         case IXGBE_AUTOC_LMS_KX4_AN:
1037         case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
1038                 if (autoc & IXGBE_AUTOC_KX_SUPP)
1039                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1040                 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1041                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1042                 break;
1043         default:
1044                 break;
1045         }
1046
1047         if (hw->phy.type == ixgbe_phy_nl) {
1048                 hw->phy.ops.identify_sfp(hw);
1049
1050                 switch (hw->phy.sfp_type) {
1051                 case ixgbe_sfp_type_da_cu:
1052                         physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1053                         break;
1054                 case ixgbe_sfp_type_sr:
1055                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1056                         break;
1057                 case ixgbe_sfp_type_lr:
1058                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1059                         break;
1060                 default:
1061                         physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1062                         break;
1063                 }
1064         }
1065
1066         switch (hw->device_id) {
1067         case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
1068                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1069                 break;
1070         case IXGBE_DEV_ID_82598AF_DUAL_PORT:
1071         case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
1072         case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
1073                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1074                 break;
1075         case IXGBE_DEV_ID_82598EB_XF_LR:
1076                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1077                 break;
1078         default:
1079                 break;
1080         }
1081
1082 out:
1083         return physical_layer;
1084 }
1085
1086 static struct ixgbe_mac_operations mac_ops_82598 = {
1087         .init_hw                = &ixgbe_init_hw_generic,
1088         .reset_hw               = &ixgbe_reset_hw_82598,
1089         .start_hw               = &ixgbe_start_hw_generic,
1090         .clear_hw_cntrs         = &ixgbe_clear_hw_cntrs_generic,
1091         .get_media_type         = &ixgbe_get_media_type_82598,
1092         .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598,
1093         .enable_rx_dma          = &ixgbe_enable_rx_dma_generic,
1094         .get_mac_addr           = &ixgbe_get_mac_addr_generic,
1095         .stop_adapter           = &ixgbe_stop_adapter_generic,
1096         .get_bus_info           = &ixgbe_get_bus_info_generic,
1097         .set_lan_id             = &ixgbe_set_lan_id_multi_port_pcie,
1098         .read_analog_reg8       = &ixgbe_read_analog_reg8_82598,
1099         .write_analog_reg8      = &ixgbe_write_analog_reg8_82598,
1100         .setup_link             = &ixgbe_setup_mac_link_82598,
1101         .setup_link_speed       = &ixgbe_setup_mac_link_speed_82598,
1102         .check_link             = &ixgbe_check_mac_link_82598,
1103         .get_link_capabilities  = &ixgbe_get_link_capabilities_82598,
1104         .led_on                 = &ixgbe_led_on_generic,
1105         .led_off                = &ixgbe_led_off_generic,
1106         .blink_led_start        = &ixgbe_blink_led_start_generic,
1107         .blink_led_stop         = &ixgbe_blink_led_stop_generic,
1108         .set_rar                = &ixgbe_set_rar_generic,
1109         .clear_rar              = &ixgbe_clear_rar_generic,
1110         .set_vmdq               = &ixgbe_set_vmdq_82598,
1111         .clear_vmdq             = &ixgbe_clear_vmdq_82598,
1112         .init_rx_addrs          = &ixgbe_init_rx_addrs_generic,
1113         .update_uc_addr_list    = &ixgbe_update_uc_addr_list_generic,
1114         .update_mc_addr_list    = &ixgbe_update_mc_addr_list_generic,
1115         .enable_mc              = &ixgbe_enable_mc_generic,
1116         .disable_mc             = &ixgbe_disable_mc_generic,
1117         .clear_vfta             = &ixgbe_clear_vfta_82598,
1118         .set_vfta               = &ixgbe_set_vfta_82598,
1119         .fc_enable              = &ixgbe_fc_enable_82598,
1120 };
1121
1122 static struct ixgbe_eeprom_operations eeprom_ops_82598 = {
1123         .init_params            = &ixgbe_init_eeprom_params_generic,
1124         .read                   = &ixgbe_read_eeprom_generic,
1125         .validate_checksum      = &ixgbe_validate_eeprom_checksum_generic,
1126         .update_checksum        = &ixgbe_update_eeprom_checksum_generic,
1127 };
1128
1129 static struct ixgbe_phy_operations phy_ops_82598 = {
1130         .identify               = &ixgbe_identify_phy_generic,
1131         .identify_sfp           = &ixgbe_identify_sfp_module_generic,
1132         .init                   = &ixgbe_init_phy_ops_82598,
1133         .reset                  = &ixgbe_reset_phy_generic,
1134         .read_reg               = &ixgbe_read_phy_reg_generic,
1135         .write_reg              = &ixgbe_write_phy_reg_generic,
1136         .setup_link             = &ixgbe_setup_phy_link_generic,
1137         .setup_link_speed       = &ixgbe_setup_phy_link_speed_generic,
1138         .read_i2c_eeprom        = &ixgbe_read_i2c_eeprom_82598,
1139 };
1140
1141 struct ixgbe_info ixgbe_82598_info = {
1142         .mac                    = ixgbe_mac_82598EB,
1143         .get_invariants         = &ixgbe_get_invariants_82598,
1144         .mac_ops                = &mac_ops_82598,
1145         .eeprom_ops             = &eeprom_ops_82598,
1146         .phy_ops                = &phy_ops_82598,
1147 };
1148