1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31 #include <linux/netdevice.h>
34 #include "ixgbe_common.h"
35 #include "ixgbe_phy.h"
37 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
38 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
39 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
40 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
41 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
42 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
44 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
45 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
46 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
47 static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
48 static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw);
50 static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index);
51 static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index);
52 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
53 static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);
54 static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num);
57 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
58 * @hw: pointer to hardware structure
60 * Starts the hardware by filling the bus info structure and media type, clears
61 * all on chip counters, initializes receive address registers, multicast
62 * table, VLAN filter table, calls routine to set up link and flow control
63 * settings, and leaves transmit and receive units disabled and uninitialized
65 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
69 /* Set the media type */
70 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
72 /* Identify the PHY */
73 hw->phy.ops.identify(hw);
75 /* Clear the VLAN filter table */
76 hw->mac.ops.clear_vfta(hw);
78 /* Clear statistics registers */
79 hw->mac.ops.clear_hw_cntrs(hw);
81 /* Set No Snoop Disable */
82 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
83 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
84 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
85 IXGBE_WRITE_FLUSH(hw);
87 /* Setup flow control */
88 ixgbe_setup_fc(hw, 0);
90 /* Clear adapter stopped flag */
91 hw->adapter_stopped = false;
97 * ixgbe_init_hw_generic - Generic hardware initialization
98 * @hw: pointer to hardware structure
100 * Initialize the hardware by resetting the hardware, filling the bus info
101 * structure and media type, clears all on chip counters, initializes receive
102 * address registers, multicast table, VLAN filter table, calls routine to set
103 * up link and flow control settings, and leaves transmit and receive units
104 * disabled and uninitialized
106 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
110 /* Reset the hardware */
111 status = hw->mac.ops.reset_hw(hw);
115 status = hw->mac.ops.start_hw(hw);
122 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
123 * @hw: pointer to hardware structure
125 * Clears all hardware statistics counters by reading them from the hardware
126 * Statistics counters are clear on read.
128 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
132 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
133 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
134 IXGBE_READ_REG(hw, IXGBE_ERRBC);
135 IXGBE_READ_REG(hw, IXGBE_MSPDC);
136 for (i = 0; i < 8; i++)
137 IXGBE_READ_REG(hw, IXGBE_MPC(i));
139 IXGBE_READ_REG(hw, IXGBE_MLFC);
140 IXGBE_READ_REG(hw, IXGBE_MRFC);
141 IXGBE_READ_REG(hw, IXGBE_RLEC);
142 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
143 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
144 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
145 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
147 for (i = 0; i < 8; i++) {
148 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
149 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
150 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
151 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
154 IXGBE_READ_REG(hw, IXGBE_PRC64);
155 IXGBE_READ_REG(hw, IXGBE_PRC127);
156 IXGBE_READ_REG(hw, IXGBE_PRC255);
157 IXGBE_READ_REG(hw, IXGBE_PRC511);
158 IXGBE_READ_REG(hw, IXGBE_PRC1023);
159 IXGBE_READ_REG(hw, IXGBE_PRC1522);
160 IXGBE_READ_REG(hw, IXGBE_GPRC);
161 IXGBE_READ_REG(hw, IXGBE_BPRC);
162 IXGBE_READ_REG(hw, IXGBE_MPRC);
163 IXGBE_READ_REG(hw, IXGBE_GPTC);
164 IXGBE_READ_REG(hw, IXGBE_GORCL);
165 IXGBE_READ_REG(hw, IXGBE_GORCH);
166 IXGBE_READ_REG(hw, IXGBE_GOTCL);
167 IXGBE_READ_REG(hw, IXGBE_GOTCH);
168 for (i = 0; i < 8; i++)
169 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
170 IXGBE_READ_REG(hw, IXGBE_RUC);
171 IXGBE_READ_REG(hw, IXGBE_RFC);
172 IXGBE_READ_REG(hw, IXGBE_ROC);
173 IXGBE_READ_REG(hw, IXGBE_RJC);
174 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
175 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
176 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
177 IXGBE_READ_REG(hw, IXGBE_TORL);
178 IXGBE_READ_REG(hw, IXGBE_TORH);
179 IXGBE_READ_REG(hw, IXGBE_TPR);
180 IXGBE_READ_REG(hw, IXGBE_TPT);
181 IXGBE_READ_REG(hw, IXGBE_PTC64);
182 IXGBE_READ_REG(hw, IXGBE_PTC127);
183 IXGBE_READ_REG(hw, IXGBE_PTC255);
184 IXGBE_READ_REG(hw, IXGBE_PTC511);
185 IXGBE_READ_REG(hw, IXGBE_PTC1023);
186 IXGBE_READ_REG(hw, IXGBE_PTC1522);
187 IXGBE_READ_REG(hw, IXGBE_MPTC);
188 IXGBE_READ_REG(hw, IXGBE_BPTC);
189 for (i = 0; i < 16; i++) {
190 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
191 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
192 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
193 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
200 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
201 * @hw: pointer to hardware structure
202 * @pba_num: stores the part number from the EEPROM
204 * Reads the part number from the EEPROM.
206 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
211 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
213 hw_dbg(hw, "NVM Read Error\n");
216 *pba_num = (u32)(data << 16);
218 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
220 hw_dbg(hw, "NVM Read Error\n");
229 * ixgbe_get_mac_addr_generic - Generic get MAC address
230 * @hw: pointer to hardware structure
231 * @mac_addr: Adapter MAC address
233 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
234 * A reset of the adapter must be performed prior to calling this function
235 * in order for the MAC address to have been loaded from the EEPROM into RAR0
237 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
243 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
244 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
246 for (i = 0; i < 4; i++)
247 mac_addr[i] = (u8)(rar_low >> (i*8));
249 for (i = 0; i < 2; i++)
250 mac_addr[i+4] = (u8)(rar_high >> (i*8));
256 * ixgbe_get_bus_info_generic - Generic set PCI bus info
257 * @hw: pointer to hardware structure
259 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
261 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
263 struct ixgbe_adapter *adapter = hw->back;
264 struct ixgbe_mac_info *mac = &hw->mac;
267 hw->bus.type = ixgbe_bus_type_pci_express;
269 /* Get the negotiated link width and speed from PCI config space */
270 pci_read_config_word(adapter->pdev, IXGBE_PCI_LINK_STATUS,
273 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
274 case IXGBE_PCI_LINK_WIDTH_1:
275 hw->bus.width = ixgbe_bus_width_pcie_x1;
277 case IXGBE_PCI_LINK_WIDTH_2:
278 hw->bus.width = ixgbe_bus_width_pcie_x2;
280 case IXGBE_PCI_LINK_WIDTH_4:
281 hw->bus.width = ixgbe_bus_width_pcie_x4;
283 case IXGBE_PCI_LINK_WIDTH_8:
284 hw->bus.width = ixgbe_bus_width_pcie_x8;
287 hw->bus.width = ixgbe_bus_width_unknown;
291 switch (link_status & IXGBE_PCI_LINK_SPEED) {
292 case IXGBE_PCI_LINK_SPEED_2500:
293 hw->bus.speed = ixgbe_bus_speed_2500;
295 case IXGBE_PCI_LINK_SPEED_5000:
296 hw->bus.speed = ixgbe_bus_speed_5000;
299 hw->bus.speed = ixgbe_bus_speed_unknown;
303 mac->ops.set_lan_id(hw);
309 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
310 * @hw: pointer to the HW structure
312 * Determines the LAN function id by reading memory-mapped registers
313 * and swaps the port value if requested.
315 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
317 struct ixgbe_bus_info *bus = &hw->bus;
320 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
321 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
322 bus->lan_id = bus->func;
324 /* check for a port swap */
325 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
326 if (reg & IXGBE_FACTPS_LFS)
331 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
332 * @hw: pointer to hardware structure
334 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
335 * disables transmit and receive units. The adapter_stopped flag is used by
336 * the shared code and drivers to determine if the adapter is in a stopped
337 * state and should not touch the hardware.
339 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
341 u32 number_of_queues;
346 * Set the adapter_stopped flag so other driver functions stop touching
349 hw->adapter_stopped = true;
351 /* Disable the receive unit */
352 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
353 reg_val &= ~(IXGBE_RXCTRL_RXEN);
354 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val);
355 IXGBE_WRITE_FLUSH(hw);
358 /* Clear interrupt mask to stop from interrupts being generated */
359 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
361 /* Clear any pending interrupts */
362 IXGBE_READ_REG(hw, IXGBE_EICR);
364 /* Disable the transmit unit. Each queue must be disabled. */
365 number_of_queues = hw->mac.max_tx_queues;
366 for (i = 0; i < number_of_queues; i++) {
367 reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
368 if (reg_val & IXGBE_TXDCTL_ENABLE) {
369 reg_val &= ~IXGBE_TXDCTL_ENABLE;
370 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val);
375 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
376 * access and verify no pending requests
378 if (ixgbe_disable_pcie_master(hw) != 0)
379 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
385 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
386 * @hw: pointer to hardware structure
387 * @index: led number to turn on
389 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
391 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
393 /* To turn on the LED, set mode to ON. */
394 led_reg &= ~IXGBE_LED_MODE_MASK(index);
395 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
396 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
397 IXGBE_WRITE_FLUSH(hw);
403 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
404 * @hw: pointer to hardware structure
405 * @index: led number to turn off
407 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
409 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
411 /* To turn off the LED, set mode to OFF. */
412 led_reg &= ~IXGBE_LED_MODE_MASK(index);
413 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
414 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
415 IXGBE_WRITE_FLUSH(hw);
421 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
422 * @hw: pointer to hardware structure
424 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
425 * ixgbe_hw struct in order to set up EEPROM access.
427 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
429 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
433 if (eeprom->type == ixgbe_eeprom_uninitialized) {
434 eeprom->type = ixgbe_eeprom_none;
435 /* Set default semaphore delay to 10ms which is a well
437 eeprom->semaphore_delay = 10;
440 * Check for EEPROM present first.
441 * If not present leave as none
443 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
444 if (eec & IXGBE_EEC_PRES) {
445 eeprom->type = ixgbe_eeprom_spi;
448 * SPI EEPROM is assumed here. This code would need to
449 * change if a future EEPROM is not SPI.
451 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
452 IXGBE_EEC_SIZE_SHIFT);
453 eeprom->word_size = 1 << (eeprom_size +
454 IXGBE_EEPROM_WORD_SIZE_SHIFT);
457 if (eec & IXGBE_EEC_ADDR_SIZE)
458 eeprom->address_bits = 16;
460 eeprom->address_bits = 8;
461 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: "
462 "%d\n", eeprom->type, eeprom->word_size,
463 eeprom->address_bits);
470 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
471 * @hw: pointer to hardware structure
472 * @offset: offset within the EEPROM to be written to
473 * @data: 16 bit word to be written to the EEPROM
475 * If ixgbe_eeprom_update_checksum is not called after this function, the
476 * EEPROM will most likely contain an invalid checksum.
478 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
481 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
483 hw->eeprom.ops.init_params(hw);
485 if (offset >= hw->eeprom.word_size) {
486 status = IXGBE_ERR_EEPROM;
490 /* Prepare the EEPROM for writing */
491 status = ixgbe_acquire_eeprom(hw);
494 if (ixgbe_ready_eeprom(hw) != 0) {
495 ixgbe_release_eeprom(hw);
496 status = IXGBE_ERR_EEPROM;
501 ixgbe_standby_eeprom(hw);
503 /* Send the WRITE ENABLE command (8 bit opcode ) */
504 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI,
505 IXGBE_EEPROM_OPCODE_BITS);
507 ixgbe_standby_eeprom(hw);
510 * Some SPI eeproms use the 8th address bit embedded in the
513 if ((hw->eeprom.address_bits == 8) && (offset >= 128))
514 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
516 /* Send the Write command (8-bit opcode + addr) */
517 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
518 IXGBE_EEPROM_OPCODE_BITS);
519 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
520 hw->eeprom.address_bits);
523 data = (data >> 8) | (data << 8);
524 ixgbe_shift_out_eeprom_bits(hw, data, 16);
525 ixgbe_standby_eeprom(hw);
527 msleep(hw->eeprom.semaphore_delay);
528 /* Done with writing - release the EEPROM */
529 ixgbe_release_eeprom(hw);
537 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
538 * @hw: pointer to hardware structure
539 * @offset: offset within the EEPROM to be read
540 * @data: read 16 bit value from EEPROM
542 * Reads 16 bit value from EEPROM through bit-bang method
544 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
549 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
551 hw->eeprom.ops.init_params(hw);
553 if (offset >= hw->eeprom.word_size) {
554 status = IXGBE_ERR_EEPROM;
558 /* Prepare the EEPROM for reading */
559 status = ixgbe_acquire_eeprom(hw);
562 if (ixgbe_ready_eeprom(hw) != 0) {
563 ixgbe_release_eeprom(hw);
564 status = IXGBE_ERR_EEPROM;
569 ixgbe_standby_eeprom(hw);
572 * Some SPI eeproms use the 8th address bit embedded in the
575 if ((hw->eeprom.address_bits == 8) && (offset >= 128))
576 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
578 /* Send the READ command (opcode + addr) */
579 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
580 IXGBE_EEPROM_OPCODE_BITS);
581 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
582 hw->eeprom.address_bits);
585 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
586 *data = (word_in >> 8) | (word_in << 8);
588 /* End this read operation */
589 ixgbe_release_eeprom(hw);
597 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
598 * @hw: pointer to hardware structure
599 * @offset: offset of word in the EEPROM to read
600 * @data: word read from the EEPROM
602 * Reads a 16 bit word from the EEPROM using the EERD register.
604 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
609 hw->eeprom.ops.init_params(hw);
611 if (offset >= hw->eeprom.word_size) {
612 status = IXGBE_ERR_EEPROM;
616 eerd = (offset << IXGBE_EEPROM_RW_ADDR_SHIFT) +
617 IXGBE_EEPROM_RW_REG_START;
619 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
620 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
623 *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
624 IXGBE_EEPROM_RW_REG_DATA);
626 hw_dbg(hw, "Eeprom read timed out\n");
633 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
634 * @hw: pointer to hardware structure
635 * @ee_reg: EEPROM flag for polling
637 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
638 * read or write is done respectively.
640 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
644 s32 status = IXGBE_ERR_EEPROM;
646 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
647 if (ee_reg == IXGBE_NVM_POLL_READ)
648 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
650 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
652 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
662 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
663 * @hw: pointer to hardware structure
665 * Prepares EEPROM for access using bit-bang method. This function should
666 * be called before issuing a command to the EEPROM.
668 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
674 if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
675 status = IXGBE_ERR_SWFW_SYNC;
678 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
680 /* Request EEPROM Access */
681 eec |= IXGBE_EEC_REQ;
682 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
684 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
685 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
686 if (eec & IXGBE_EEC_GNT)
691 /* Release if grant not acquired */
692 if (!(eec & IXGBE_EEC_GNT)) {
693 eec &= ~IXGBE_EEC_REQ;
694 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
695 hw_dbg(hw, "Could not acquire EEPROM grant\n");
697 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
698 status = IXGBE_ERR_EEPROM;
702 /* Setup EEPROM for Read/Write */
704 /* Clear CS and SK */
705 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
706 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
707 IXGBE_WRITE_FLUSH(hw);
714 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
715 * @hw: pointer to hardware structure
717 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
719 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
721 s32 status = IXGBE_ERR_EEPROM;
726 /* Set timeout value based on size of EEPROM */
727 timeout = hw->eeprom.word_size + 1;
729 /* Get SMBI software semaphore between device drivers first */
730 for (i = 0; i < timeout; i++) {
732 * If the SMBI bit is 0 when we read it, then the bit will be
733 * set and we have the semaphore
735 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
736 if (!(swsm & IXGBE_SWSM_SMBI)) {
743 /* Now get the semaphore between SW/FW through the SWESMBI bit */
745 for (i = 0; i < timeout; i++) {
746 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
748 /* Set the SW EEPROM semaphore bit to request access */
749 swsm |= IXGBE_SWSM_SWESMBI;
750 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
753 * If we set the bit successfully then we got the
756 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
757 if (swsm & IXGBE_SWSM_SWESMBI)
764 * Release semaphores and return error if SW EEPROM semaphore
765 * was not granted because we don't have access to the EEPROM
768 hw_dbg(hw, "Driver can't access the Eeprom - Semaphore "
770 ixgbe_release_eeprom_semaphore(hw);
771 status = IXGBE_ERR_EEPROM;
779 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
780 * @hw: pointer to hardware structure
782 * This function clears hardware semaphore bits.
784 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
788 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
790 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
791 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
792 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
793 IXGBE_WRITE_FLUSH(hw);
797 * ixgbe_ready_eeprom - Polls for EEPROM ready
798 * @hw: pointer to hardware structure
800 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
807 * Read "Status Register" repeatedly until the LSB is cleared. The
808 * EEPROM will signal that the command has been completed by clearing
809 * bit 0 of the internal status register. If it's not cleared within
810 * 5 milliseconds, then error out.
812 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
813 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
814 IXGBE_EEPROM_OPCODE_BITS);
815 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
816 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
820 ixgbe_standby_eeprom(hw);
824 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
825 * devices (and only 0-5mSec on 5V devices)
827 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
828 hw_dbg(hw, "SPI EEPROM Status error\n");
829 status = IXGBE_ERR_EEPROM;
836 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
837 * @hw: pointer to hardware structure
839 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
843 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
845 /* Toggle CS to flush commands */
847 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
848 IXGBE_WRITE_FLUSH(hw);
850 eec &= ~IXGBE_EEC_CS;
851 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
852 IXGBE_WRITE_FLUSH(hw);
857 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
858 * @hw: pointer to hardware structure
859 * @data: data to send to the EEPROM
860 * @count: number of bits to shift out
862 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
869 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
872 * Mask is used to shift "count" bits of "data" out to the EEPROM
873 * one bit at a time. Determine the starting bit based on count
875 mask = 0x01 << (count - 1);
877 for (i = 0; i < count; i++) {
879 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
880 * "1", and then raising and then lowering the clock (the SK
881 * bit controls the clock input to the EEPROM). A "0" is
882 * shifted out to the EEPROM by setting "DI" to "0" and then
883 * raising and then lowering the clock.
888 eec &= ~IXGBE_EEC_DI;
890 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
891 IXGBE_WRITE_FLUSH(hw);
895 ixgbe_raise_eeprom_clk(hw, &eec);
896 ixgbe_lower_eeprom_clk(hw, &eec);
899 * Shift mask to signify next bit of data to shift in to the
905 /* We leave the "DI" bit set to "0" when we leave this routine. */
906 eec &= ~IXGBE_EEC_DI;
907 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
908 IXGBE_WRITE_FLUSH(hw);
912 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
913 * @hw: pointer to hardware structure
915 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
922 * In order to read a register from the EEPROM, we need to shift
923 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
924 * the clock input to the EEPROM (setting the SK bit), and then reading
925 * the value of the "DO" bit. During this "shifting in" process the
926 * "DI" bit should always be clear.
928 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
930 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
932 for (i = 0; i < count; i++) {
934 ixgbe_raise_eeprom_clk(hw, &eec);
936 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
938 eec &= ~(IXGBE_EEC_DI);
939 if (eec & IXGBE_EEC_DO)
942 ixgbe_lower_eeprom_clk(hw, &eec);
949 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
950 * @hw: pointer to hardware structure
951 * @eec: EEC register's current value
953 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
956 * Raise the clock input to the EEPROM
957 * (setting the SK bit), then delay
959 *eec = *eec | IXGBE_EEC_SK;
960 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
961 IXGBE_WRITE_FLUSH(hw);
966 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
967 * @hw: pointer to hardware structure
968 * @eecd: EECD's current value
970 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
973 * Lower the clock input to the EEPROM (clearing the SK bit), then
976 *eec = *eec & ~IXGBE_EEC_SK;
977 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
978 IXGBE_WRITE_FLUSH(hw);
983 * ixgbe_release_eeprom - Release EEPROM, release semaphores
984 * @hw: pointer to hardware structure
986 static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
990 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
992 eec |= IXGBE_EEC_CS; /* Pull CS high */
993 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
995 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
996 IXGBE_WRITE_FLUSH(hw);
1000 /* Stop requesting EEPROM access */
1001 eec &= ~IXGBE_EEC_REQ;
1002 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1004 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1008 * ixgbe_calc_eeprom_checksum - Calculates and returns the checksum
1009 * @hw: pointer to hardware structure
1011 static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw)
1020 /* Include 0x0-0x3F in the checksum */
1021 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
1022 if (hw->eeprom.ops.read(hw, i, &word) != 0) {
1023 hw_dbg(hw, "EEPROM read failed\n");
1029 /* Include all data from pointers except for the fw pointer */
1030 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
1031 hw->eeprom.ops.read(hw, i, &pointer);
1033 /* Make sure the pointer seems valid */
1034 if (pointer != 0xFFFF && pointer != 0) {
1035 hw->eeprom.ops.read(hw, pointer, &length);
1037 if (length != 0xFFFF && length != 0) {
1038 for (j = pointer+1; j <= pointer+length; j++) {
1039 hw->eeprom.ops.read(hw, j, &word);
1046 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1052 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
1053 * @hw: pointer to hardware structure
1054 * @checksum_val: calculated checksum
1056 * Performs checksum calculation and validates the EEPROM checksum. If the
1057 * caller does not need checksum_val, the value can be NULL.
1059 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
1064 u16 read_checksum = 0;
1067 * Read the first word from the EEPROM. If this times out or fails, do
1068 * not continue or we could be in for a very long wait while every
1071 status = hw->eeprom.ops.read(hw, 0, &checksum);
1074 checksum = ixgbe_calc_eeprom_checksum(hw);
1076 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
1079 * Verify read checksum from EEPROM is the same as
1080 * calculated checksum
1082 if (read_checksum != checksum)
1083 status = IXGBE_ERR_EEPROM_CHECKSUM;
1085 /* If the user cares, return the calculated checksum */
1087 *checksum_val = checksum;
1089 hw_dbg(hw, "EEPROM read failed\n");
1096 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1097 * @hw: pointer to hardware structure
1099 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1105 * Read the first word from the EEPROM. If this times out or fails, do
1106 * not continue or we could be in for a very long wait while every
1109 status = hw->eeprom.ops.read(hw, 0, &checksum);
1112 checksum = ixgbe_calc_eeprom_checksum(hw);
1113 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
1116 hw_dbg(hw, "EEPROM read failed\n");
1123 * ixgbe_validate_mac_addr - Validate MAC address
1124 * @mac_addr: pointer to MAC address.
1126 * Tests a MAC address to ensure it is a valid Individual Address
1128 s32 ixgbe_validate_mac_addr(u8 *mac_addr)
1132 /* Make sure it is not a multicast address */
1133 if (IXGBE_IS_MULTICAST(mac_addr))
1134 status = IXGBE_ERR_INVALID_MAC_ADDR;
1135 /* Not a broadcast address */
1136 else if (IXGBE_IS_BROADCAST(mac_addr))
1137 status = IXGBE_ERR_INVALID_MAC_ADDR;
1138 /* Reject the zero address */
1139 else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
1140 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0)
1141 status = IXGBE_ERR_INVALID_MAC_ADDR;
1147 * ixgbe_set_rar_generic - Set Rx address register
1148 * @hw: pointer to hardware structure
1149 * @index: Receive address register to write
1150 * @addr: Address to put into receive address register
1151 * @vmdq: VMDq "set" or "pool" index
1152 * @enable_addr: set flag that address is active
1154 * Puts an ethernet address into a receive address register.
1156 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
1159 u32 rar_low, rar_high;
1160 u32 rar_entries = hw->mac.num_rar_entries;
1162 /* setup VMDq pool selection before this RAR gets enabled */
1163 hw->mac.ops.set_vmdq(hw, index, vmdq);
1165 /* Make sure we are using a valid rar index range */
1166 if (index < rar_entries) {
1168 * HW expects these in little endian so we reverse the byte
1169 * order from network order (big endian) to little endian
1171 rar_low = ((u32)addr[0] |
1172 ((u32)addr[1] << 8) |
1173 ((u32)addr[2] << 16) |
1174 ((u32)addr[3] << 24));
1176 * Some parts put the VMDq setting in the extra RAH bits,
1177 * so save everything except the lower 16 bits that hold part
1178 * of the address and the address valid bit.
1180 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1181 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1182 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
1184 if (enable_addr != 0)
1185 rar_high |= IXGBE_RAH_AV;
1187 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
1188 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1190 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1197 * ixgbe_clear_rar_generic - Remove Rx address register
1198 * @hw: pointer to hardware structure
1199 * @index: Receive address register to write
1201 * Clears an ethernet address from a receive address register.
1203 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
1206 u32 rar_entries = hw->mac.num_rar_entries;
1208 /* Make sure we are using a valid rar index range */
1209 if (index < rar_entries) {
1211 * Some parts put the VMDq setting in the extra RAH bits,
1212 * so save everything except the lower 16 bits that hold part
1213 * of the address and the address valid bit.
1215 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1216 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1218 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
1219 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1221 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1224 /* clear VMDq pool/queue selection for this RAR */
1225 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
1231 * ixgbe_enable_rar - Enable Rx address register
1232 * @hw: pointer to hardware structure
1233 * @index: index into the RAR table
1235 * Enables the select receive address register.
1237 static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index)
1241 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1242 rar_high |= IXGBE_RAH_AV;
1243 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1247 * ixgbe_disable_rar - Disable Rx address register
1248 * @hw: pointer to hardware structure
1249 * @index: index into the RAR table
1251 * Disables the select receive address register.
1253 static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index)
1257 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1258 rar_high &= (~IXGBE_RAH_AV);
1259 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1263 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
1264 * @hw: pointer to hardware structure
1266 * Places the MAC address in receive address register 0 and clears the rest
1267 * of the receive address registers. Clears the multicast table. Assumes
1268 * the receiver is in reset when the routine is called.
1270 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
1273 u32 rar_entries = hw->mac.num_rar_entries;
1276 * If the current mac address is valid, assume it is a software override
1277 * to the permanent address.
1278 * Otherwise, use the permanent address from the eeprom.
1280 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
1281 IXGBE_ERR_INVALID_MAC_ADDR) {
1282 /* Get the MAC address from the RAR0 for later reference */
1283 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
1285 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr);
1287 /* Setup the receive address. */
1288 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
1289 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr);
1291 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1293 hw->addr_ctrl.overflow_promisc = 0;
1295 hw->addr_ctrl.rar_used_count = 1;
1297 /* Zero out the other receive addresses. */
1298 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1);
1299 for (i = 1; i < rar_entries; i++) {
1300 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1301 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1305 hw->addr_ctrl.mc_addr_in_rar_count = 0;
1306 hw->addr_ctrl.mta_in_use = 0;
1307 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1309 hw_dbg(hw, " Clearing MTA\n");
1310 for (i = 0; i < hw->mac.mcft_size; i++)
1311 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1313 if (hw->mac.ops.init_uta_tables)
1314 hw->mac.ops.init_uta_tables(hw);
1320 * ixgbe_add_uc_addr - Adds a secondary unicast address.
1321 * @hw: pointer to hardware structure
1322 * @addr: new address
1324 * Adds it to unused receive address register or goes into promiscuous mode.
1326 static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
1328 u32 rar_entries = hw->mac.num_rar_entries;
1331 hw_dbg(hw, " UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
1332 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
1335 * Place this address in the RAR if there is room,
1336 * else put the controller into promiscuous mode
1338 if (hw->addr_ctrl.rar_used_count < rar_entries) {
1339 rar = hw->addr_ctrl.rar_used_count -
1340 hw->addr_ctrl.mc_addr_in_rar_count;
1341 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
1342 hw_dbg(hw, "Added a secondary address to RAR[%d]\n", rar);
1343 hw->addr_ctrl.rar_used_count++;
1345 hw->addr_ctrl.overflow_promisc++;
1348 hw_dbg(hw, "ixgbe_add_uc_addr Complete\n");
1352 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
1353 * @hw: pointer to hardware structure
1354 * @netdev: pointer to net device structure
1356 * The given list replaces any existing list. Clears the secondary addrs from
1357 * receive address registers. Uses unused receive address registers for the
1358 * first secondary addresses, and falls back to promiscuous mode as needed.
1360 * Drivers using secondary unicast addresses must set user_set_promisc when
1361 * manually putting the device into promiscuous mode.
1363 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw,
1364 struct net_device *netdev)
1367 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
1370 struct netdev_hw_addr *ha;
1373 * Clear accounting of old secondary address list,
1374 * don't count RAR[0]
1376 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
1377 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
1378 hw->addr_ctrl.overflow_promisc = 0;
1380 /* Zero out the other receive addresses */
1381 hw_dbg(hw, "Clearing RAR[1-%d]\n", uc_addr_in_use + 1);
1382 for (i = 0; i < uc_addr_in_use; i++) {
1383 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
1384 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
1387 /* Add the new addresses */
1388 netdev_for_each_uc_addr(ha, netdev) {
1389 hw_dbg(hw, " Adding the secondary addresses:\n");
1390 ixgbe_add_uc_addr(hw, ha->addr, 0);
1393 if (hw->addr_ctrl.overflow_promisc) {
1394 /* enable promisc if not already in overflow or set by user */
1395 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
1396 hw_dbg(hw, " Entering address overflow promisc mode\n");
1397 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1398 fctrl |= IXGBE_FCTRL_UPE;
1399 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1400 hw->addr_ctrl.uc_set_promisc = true;
1403 /* only disable if set by overflow, not by user */
1404 if ((old_promisc_setting && hw->addr_ctrl.uc_set_promisc) &&
1405 !(hw->addr_ctrl.user_set_promisc)) {
1406 hw_dbg(hw, " Leaving address overflow promisc mode\n");
1407 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1408 fctrl &= ~IXGBE_FCTRL_UPE;
1409 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1410 hw->addr_ctrl.uc_set_promisc = false;
1414 hw_dbg(hw, "ixgbe_update_uc_addr_list_generic Complete\n");
1419 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1420 * @hw: pointer to hardware structure
1421 * @mc_addr: the multicast address
1423 * Extracts the 12 bits, from a multicast address, to determine which
1424 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
1425 * incoming rx multicast addresses, to determine the bit-vector to check in
1426 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
1427 * by the MO field of the MCSTCTRL. The MO field is set during initialization
1428 * to mc_filter_type.
1430 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
1434 switch (hw->mac.mc_filter_type) {
1435 case 0: /* use bits [47:36] of the address */
1436 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
1438 case 1: /* use bits [46:35] of the address */
1439 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
1441 case 2: /* use bits [45:34] of the address */
1442 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
1444 case 3: /* use bits [43:32] of the address */
1445 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
1447 default: /* Invalid mc_filter_type */
1448 hw_dbg(hw, "MC filter type param set incorrectly\n");
1452 /* vector can only be 12-bits or boundary will be exceeded */
1458 * ixgbe_set_mta - Set bit-vector in multicast table
1459 * @hw: pointer to hardware structure
1460 * @hash_value: Multicast address hash value
1462 * Sets the bit-vector in the multicast table.
1464 static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
1471 hw->addr_ctrl.mta_in_use++;
1473 vector = ixgbe_mta_vector(hw, mc_addr);
1474 hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
1477 * The MTA is a register array of 128 32-bit registers. It is treated
1478 * like an array of 4096 bits. We want to set bit
1479 * BitArray[vector_value]. So we figure out what register the bit is
1480 * in, read it, OR in the new bit, then write back the new value. The
1481 * register is determined by the upper 7 bits of the vector value and
1482 * the bit within that register are determined by the lower 5 bits of
1485 vector_reg = (vector >> 5) & 0x7F;
1486 vector_bit = vector & 0x1F;
1487 mta_reg = IXGBE_READ_REG(hw, IXGBE_MTA(vector_reg));
1488 mta_reg |= (1 << vector_bit);
1489 IXGBE_WRITE_REG(hw, IXGBE_MTA(vector_reg), mta_reg);
1493 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
1494 * @hw: pointer to hardware structure
1495 * @netdev: pointer to net device structure
1497 * The given list replaces any existing list. Clears the MC addrs from receive
1498 * address registers and the multicast table. Uses unused receive address
1499 * registers for the first multicast addresses, and hashes the rest into the
1502 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
1503 struct net_device *netdev)
1505 struct netdev_hw_addr *ha;
1509 * Set the new number of MC addresses that we are being requested to
1512 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev);
1513 hw->addr_ctrl.mta_in_use = 0;
1516 hw_dbg(hw, " Clearing MTA\n");
1517 for (i = 0; i < hw->mac.mcft_size; i++)
1518 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1520 /* Add the new addresses */
1521 netdev_for_each_mc_addr(ha, netdev) {
1522 hw_dbg(hw, " Adding the multicast addresses:\n");
1523 ixgbe_set_mta(hw, ha->addr);
1527 if (hw->addr_ctrl.mta_in_use > 0)
1528 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
1529 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
1531 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
1536 * ixgbe_enable_mc_generic - Enable multicast address in RAR
1537 * @hw: pointer to hardware structure
1539 * Enables multicast address in RAR and the use of the multicast hash table.
1541 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
1544 u32 rar_entries = hw->mac.num_rar_entries;
1545 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
1547 if (a->mc_addr_in_rar_count > 0)
1548 for (i = (rar_entries - a->mc_addr_in_rar_count);
1549 i < rar_entries; i++)
1550 ixgbe_enable_rar(hw, i);
1552 if (a->mta_in_use > 0)
1553 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
1554 hw->mac.mc_filter_type);
1560 * ixgbe_disable_mc_generic - Disable multicast address in RAR
1561 * @hw: pointer to hardware structure
1563 * Disables multicast address in RAR and the use of the multicast hash table.
1565 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
1568 u32 rar_entries = hw->mac.num_rar_entries;
1569 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
1571 if (a->mc_addr_in_rar_count > 0)
1572 for (i = (rar_entries - a->mc_addr_in_rar_count);
1573 i < rar_entries; i++)
1574 ixgbe_disable_rar(hw, i);
1576 if (a->mta_in_use > 0)
1577 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1583 * ixgbe_fc_enable_generic - Enable flow control
1584 * @hw: pointer to hardware structure
1585 * @packetbuf_num: packet buffer number (0-7)
1587 * Enable flow control according to the current settings.
1589 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
1592 u32 mflcn_reg, fccfg_reg;
1597 if (hw->fc.requested_mode == ixgbe_fc_pfc)
1600 #endif /* CONFIG_DCB */
1601 /* Negotiate the fc mode to use */
1602 ret_val = ixgbe_fc_autoneg(hw);
1606 /* Disable any previous flow control settings */
1607 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
1608 mflcn_reg &= ~(IXGBE_MFLCN_RFCE | IXGBE_MFLCN_RPFCE);
1610 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
1611 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
1614 * The possible values of fc.current_mode are:
1615 * 0: Flow control is completely disabled
1616 * 1: Rx flow control is enabled (we can receive pause frames,
1617 * but not send pause frames).
1618 * 2: Tx flow control is enabled (we can send pause frames but
1619 * we do not support receiving pause frames).
1620 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1621 * 4: Priority Flow Control is enabled.
1624 switch (hw->fc.current_mode) {
1627 * Flow control is disabled by software override or autoneg.
1628 * The code below will actually disable it in the HW.
1631 case ixgbe_fc_rx_pause:
1633 * Rx Flow control is enabled and Tx Flow control is
1634 * disabled by software override. Since there really
1635 * isn't a way to advertise that we are capable of RX
1636 * Pause ONLY, we will advertise that we support both
1637 * symmetric and asymmetric Rx PAUSE. Later, we will
1638 * disable the adapter's ability to send PAUSE frames.
1640 mflcn_reg |= IXGBE_MFLCN_RFCE;
1642 case ixgbe_fc_tx_pause:
1644 * Tx Flow control is enabled, and Rx Flow control is
1645 * disabled by software override.
1647 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
1650 /* Flow control (both Rx and Tx) is enabled by SW override. */
1651 mflcn_reg |= IXGBE_MFLCN_RFCE;
1652 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
1658 #endif /* CONFIG_DCB */
1660 hw_dbg(hw, "Flow control param set incorrectly\n");
1661 ret_val = IXGBE_ERR_CONFIG;
1666 /* Set 802.3x based flow control settings. */
1667 mflcn_reg |= IXGBE_MFLCN_DPF;
1668 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
1669 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
1671 reg = IXGBE_READ_REG(hw, IXGBE_MTQC);
1672 /* Thresholds are different for link flow control when in DCB mode */
1673 if (reg & IXGBE_MTQC_RT_ENA) {
1674 rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num));
1676 /* Always disable XON for LFC when in DCB mode */
1677 reg = (rx_pba_size >> 5) & 0xFFE0;
1678 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), reg);
1680 reg = (rx_pba_size >> 2) & 0xFFE0;
1681 if (hw->fc.current_mode & ixgbe_fc_tx_pause)
1682 reg |= IXGBE_FCRTH_FCEN;
1683 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), reg);
1686 * Set up and enable Rx high/low water mark thresholds,
1689 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
1690 if (hw->fc.send_xon) {
1692 IXGBE_FCRTL_82599(packetbuf_num),
1697 IXGBE_FCRTL_82599(packetbuf_num),
1701 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num),
1702 (hw->fc.high_water | IXGBE_FCRTH_FCEN));
1706 /* Configure pause time (2 TCs per register) */
1707 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
1708 if ((packetbuf_num & 1) == 0)
1709 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
1711 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
1712 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
1714 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
1721 * ixgbe_fc_autoneg - Configure flow control
1722 * @hw: pointer to hardware structure
1724 * Compares our advertised flow control capabilities to those advertised by
1725 * our link partner, and determines the proper flow control mode to use.
1727 s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw)
1730 ixgbe_link_speed speed;
1731 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
1732 u32 links2, anlp1_reg, autoc_reg, links;
1736 * AN should have completed when the cable was plugged in.
1737 * Look for reasons to bail out. Bail out if:
1738 * - FC autoneg is disabled, or if
1741 * Since we're being called from an LSC, link is already known to be up.
1742 * So use link_up_wait_to_complete=false.
1744 hw->mac.ops.check_link(hw, &speed, &link_up, false);
1746 if (hw->fc.disable_fc_autoneg || (!link_up)) {
1747 hw->fc.fc_was_autonegged = false;
1748 hw->fc.current_mode = hw->fc.requested_mode;
1753 * On backplane, bail out if
1754 * - backplane autoneg was not completed, or if
1755 * - we are 82599 and link partner is not AN enabled
1757 if (hw->phy.media_type == ixgbe_media_type_backplane) {
1758 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
1759 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
1760 hw->fc.fc_was_autonegged = false;
1761 hw->fc.current_mode = hw->fc.requested_mode;
1765 if (hw->mac.type == ixgbe_mac_82599EB) {
1766 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
1767 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
1768 hw->fc.fc_was_autonegged = false;
1769 hw->fc.current_mode = hw->fc.requested_mode;
1776 * On multispeed fiber at 1g, bail out if
1777 * - link is up but AN did not complete, or if
1778 * - link is up and AN completed but timed out
1780 if (hw->phy.multispeed_fiber && (speed == IXGBE_LINK_SPEED_1GB_FULL)) {
1781 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
1782 if (((linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
1783 ((linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
1784 hw->fc.fc_was_autonegged = false;
1785 hw->fc.current_mode = hw->fc.requested_mode;
1792 * - copper or CX4 adapters
1793 * - fiber adapters running at 10gig
1795 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
1796 (hw->phy.media_type == ixgbe_media_type_cx4) ||
1797 ((hw->phy.media_type == ixgbe_media_type_fiber) &&
1798 (speed == IXGBE_LINK_SPEED_10GB_FULL))) {
1799 hw->fc.fc_was_autonegged = false;
1800 hw->fc.current_mode = hw->fc.requested_mode;
1805 * Read the AN advertisement and LP ability registers and resolve
1806 * local flow control settings accordingly
1808 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
1809 (hw->phy.media_type != ixgbe_media_type_backplane)) {
1810 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
1811 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
1812 if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1813 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE)) {
1815 * Now we need to check if the user selected Rx ONLY
1816 * of pause frames. In this case, we had to advertise
1817 * FULL flow control because we could not advertise RX
1818 * ONLY. Hence, we must now check to see if we need to
1819 * turn OFF the TRANSMISSION of PAUSE frames.
1821 if (hw->fc.requested_mode == ixgbe_fc_full) {
1822 hw->fc.current_mode = ixgbe_fc_full;
1823 hw_dbg(hw, "Flow Control = FULL.\n");
1825 hw->fc.current_mode = ixgbe_fc_rx_pause;
1826 hw_dbg(hw, "Flow Control=RX PAUSE only\n");
1828 } else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1829 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
1830 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1831 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) {
1832 hw->fc.current_mode = ixgbe_fc_tx_pause;
1833 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
1834 } else if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1835 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
1836 !(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1837 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) {
1838 hw->fc.current_mode = ixgbe_fc_rx_pause;
1839 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
1841 hw->fc.current_mode = ixgbe_fc_none;
1842 hw_dbg(hw, "Flow Control = NONE.\n");
1846 if (hw->phy.media_type == ixgbe_media_type_backplane) {
1848 * Read the 10g AN autoc and LP ability registers and resolve
1849 * local flow control settings accordingly
1851 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1852 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
1854 if ((autoc_reg & IXGBE_AUTOC_SYM_PAUSE) &&
1855 (anlp1_reg & IXGBE_ANLP1_SYM_PAUSE)) {
1857 * Now we need to check if the user selected Rx ONLY
1858 * of pause frames. In this case, we had to advertise
1859 * FULL flow control because we could not advertise RX
1860 * ONLY. Hence, we must now check to see if we need to
1861 * turn OFF the TRANSMISSION of PAUSE frames.
1863 if (hw->fc.requested_mode == ixgbe_fc_full) {
1864 hw->fc.current_mode = ixgbe_fc_full;
1865 hw_dbg(hw, "Flow Control = FULL.\n");
1867 hw->fc.current_mode = ixgbe_fc_rx_pause;
1868 hw_dbg(hw, "Flow Control=RX PAUSE only\n");
1870 } else if (!(autoc_reg & IXGBE_AUTOC_SYM_PAUSE) &&
1871 (autoc_reg & IXGBE_AUTOC_ASM_PAUSE) &&
1872 (anlp1_reg & IXGBE_ANLP1_SYM_PAUSE) &&
1873 (anlp1_reg & IXGBE_ANLP1_ASM_PAUSE)) {
1874 hw->fc.current_mode = ixgbe_fc_tx_pause;
1875 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
1876 } else if ((autoc_reg & IXGBE_AUTOC_SYM_PAUSE) &&
1877 (autoc_reg & IXGBE_AUTOC_ASM_PAUSE) &&
1878 !(anlp1_reg & IXGBE_ANLP1_SYM_PAUSE) &&
1879 (anlp1_reg & IXGBE_ANLP1_ASM_PAUSE)) {
1880 hw->fc.current_mode = ixgbe_fc_rx_pause;
1881 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
1883 hw->fc.current_mode = ixgbe_fc_none;
1884 hw_dbg(hw, "Flow Control = NONE.\n");
1887 /* Record that current_mode is the result of a successful autoneg */
1888 hw->fc.fc_was_autonegged = true;
1895 * ixgbe_setup_fc - Set up flow control
1896 * @hw: pointer to hardware structure
1898 * Called at init time to set up flow control.
1900 static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num)
1906 if (hw->fc.requested_mode == ixgbe_fc_pfc) {
1907 hw->fc.current_mode = hw->fc.requested_mode;
1912 /* Validate the packetbuf configuration */
1913 if (packetbuf_num < 0 || packetbuf_num > 7) {
1914 hw_dbg(hw, "Invalid packet buffer number [%d], expected range "
1915 "is 0-7\n", packetbuf_num);
1916 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1921 * Validate the water mark configuration. Zero water marks are invalid
1922 * because it causes the controller to just blast out fc packets.
1924 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
1925 hw_dbg(hw, "Invalid water mark configuration\n");
1926 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1931 * Validate the requested mode. Strict IEEE mode does not allow
1932 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
1934 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
1935 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict "
1937 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1942 * 10gig parts do not have a word in the EEPROM to determine the
1943 * default flow control setting, so we explicitly set it to full.
1945 if (hw->fc.requested_mode == ixgbe_fc_default)
1946 hw->fc.requested_mode = ixgbe_fc_full;
1949 * Set up the 1G flow control advertisement registers so the HW will be
1950 * able to do fc autoneg once the cable is plugged in. If we end up
1951 * using 10g instead, this is harmless.
1953 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
1956 * The possible values of fc.requested_mode are:
1957 * 0: Flow control is completely disabled
1958 * 1: Rx flow control is enabled (we can receive pause frames,
1959 * but not send pause frames).
1960 * 2: Tx flow control is enabled (we can send pause frames but
1961 * we do not support receiving pause frames).
1962 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1964 * 4: Priority Flow Control is enabled.
1968 switch (hw->fc.requested_mode) {
1970 /* Flow control completely disabled by software override. */
1971 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
1973 case ixgbe_fc_rx_pause:
1975 * Rx Flow control is enabled and Tx Flow control is
1976 * disabled by software override. Since there really
1977 * isn't a way to advertise that we are capable of RX
1978 * Pause ONLY, we will advertise that we support both
1979 * symmetric and asymmetric Rx PAUSE. Later, we will
1980 * disable the adapter's ability to send PAUSE frames.
1982 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
1984 case ixgbe_fc_tx_pause:
1986 * Tx Flow control is enabled, and Rx Flow control is
1987 * disabled by software override.
1989 reg |= (IXGBE_PCS1GANA_ASM_PAUSE);
1990 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE);
1993 /* Flow control (both Rx and Tx) is enabled by SW override. */
1994 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
2000 #endif /* CONFIG_DCB */
2002 hw_dbg(hw, "Flow control param set incorrectly\n");
2003 ret_val = IXGBE_ERR_CONFIG;
2008 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
2009 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
2011 /* Disable AN timeout */
2012 if (hw->fc.strict_ieee)
2013 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
2015 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
2016 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg);
2019 * Set up the 10G flow control advertisement registers so the HW
2020 * can do fc autoneg once the cable is plugged in. If we end up
2021 * using 1g instead, this is harmless.
2023 reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2026 * The possible values of fc.requested_mode are:
2027 * 0: Flow control is completely disabled
2028 * 1: Rx flow control is enabled (we can receive pause frames,
2029 * but not send pause frames).
2030 * 2: Tx flow control is enabled (we can send pause frames but
2031 * we do not support receiving pause frames).
2032 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2035 switch (hw->fc.requested_mode) {
2037 /* Flow control completely disabled by software override. */
2038 reg &= ~(IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE);
2040 case ixgbe_fc_rx_pause:
2042 * Rx Flow control is enabled and Tx Flow control is
2043 * disabled by software override. Since there really
2044 * isn't a way to advertise that we are capable of RX
2045 * Pause ONLY, we will advertise that we support both
2046 * symmetric and asymmetric Rx PAUSE. Later, we will
2047 * disable the adapter's ability to send PAUSE frames.
2049 reg |= (IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE);
2051 case ixgbe_fc_tx_pause:
2053 * Tx Flow control is enabled, and Rx Flow control is
2054 * disabled by software override.
2056 reg |= (IXGBE_AUTOC_ASM_PAUSE);
2057 reg &= ~(IXGBE_AUTOC_SYM_PAUSE);
2060 /* Flow control (both Rx and Tx) is enabled by SW override. */
2061 reg |= (IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE);
2067 #endif /* CONFIG_DCB */
2069 hw_dbg(hw, "Flow control param set incorrectly\n");
2070 ret_val = IXGBE_ERR_CONFIG;
2075 * AUTOC restart handles negotiation of 1G and 10G. There is
2076 * no need to set the PCS1GCTL register.
2078 reg |= IXGBE_AUTOC_AN_RESTART;
2079 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg);
2080 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
2087 * ixgbe_disable_pcie_master - Disable PCI-express master access
2088 * @hw: pointer to hardware structure
2090 * Disables PCI-Express master access and verifies there are no pending
2091 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
2092 * bit hasn't caused the master requests to be disabled, else 0
2093 * is returned signifying master requests disabled.
2095 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
2099 u32 number_of_queues;
2100 s32 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
2102 /* Disable the receive unit by stopping each queue */
2103 number_of_queues = hw->mac.max_rx_queues;
2104 for (i = 0; i < number_of_queues; i++) {
2105 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
2106 if (reg_val & IXGBE_RXDCTL_ENABLE) {
2107 reg_val &= ~IXGBE_RXDCTL_ENABLE;
2108 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
2112 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL);
2113 reg_val |= IXGBE_CTRL_GIO_DIS;
2114 IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val);
2116 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2117 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) {
2129 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
2130 * @hw: pointer to hardware structure
2131 * @mask: Mask to specify which semaphore to acquire
2133 * Acquires the SWFW semaphore thought the GSSR register for the specified
2134 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2136 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2140 u32 fwmask = mask << 5;
2144 if (ixgbe_get_eeprom_semaphore(hw))
2145 return IXGBE_ERR_SWFW_SYNC;
2147 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2148 if (!(gssr & (fwmask | swmask)))
2152 * Firmware currently using resource (fwmask) or other software
2153 * thread currently using resource (swmask)
2155 ixgbe_release_eeprom_semaphore(hw);
2161 hw_dbg(hw, "Driver can't access resource, GSSR timeout.\n");
2162 return IXGBE_ERR_SWFW_SYNC;
2166 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2168 ixgbe_release_eeprom_semaphore(hw);
2173 * ixgbe_release_swfw_sync - Release SWFW semaphore
2174 * @hw: pointer to hardware structure
2175 * @mask: Mask to specify which semaphore to release
2177 * Releases the SWFW semaphore thought the GSSR register for the specified
2178 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2180 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2185 ixgbe_get_eeprom_semaphore(hw);
2187 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2189 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2191 ixgbe_release_eeprom_semaphore(hw);
2195 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2196 * @hw: pointer to hardware structure
2197 * @regval: register value to write to RXCTRL
2199 * Enables the Rx DMA unit
2201 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2203 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2209 * ixgbe_blink_led_start_generic - Blink LED based on index.
2210 * @hw: pointer to hardware structure
2211 * @index: led number to blink
2213 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2215 ixgbe_link_speed speed = 0;
2217 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2218 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2221 * Link must be up to auto-blink the LEDs;
2222 * Force it if link is down.
2224 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2227 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2228 autoc_reg |= IXGBE_AUTOC_FLU;
2229 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2233 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2234 led_reg |= IXGBE_LED_BLINK(index);
2235 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2236 IXGBE_WRITE_FLUSH(hw);
2242 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2243 * @hw: pointer to hardware structure
2244 * @index: led number to stop blinking
2246 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2248 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2249 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2251 autoc_reg &= ~IXGBE_AUTOC_FLU;
2252 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2253 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2255 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2256 led_reg &= ~IXGBE_LED_BLINK(index);
2257 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
2258 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2259 IXGBE_WRITE_FLUSH(hw);
2265 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
2266 * @hw: pointer to hardware structure
2267 * @san_mac_offset: SAN MAC address offset
2269 * This function will read the EEPROM location for the SAN MAC address
2270 * pointer, and returns the value at that location. This is used in both
2271 * get and set mac_addr routines.
2273 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
2274 u16 *san_mac_offset)
2277 * First read the EEPROM pointer to see if the MAC addresses are
2280 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
2286 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
2287 * @hw: pointer to hardware structure
2288 * @san_mac_addr: SAN MAC address
2290 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2291 * per-port, so set_lan_id() must be called before reading the addresses.
2292 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2293 * upon for non-SFP connections, so we must call it here.
2295 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
2297 u16 san_mac_data, san_mac_offset;
2301 * First read the EEPROM pointer to see if the MAC addresses are
2302 * available. If they're not, no point in calling set_lan_id() here.
2304 ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
2306 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2308 * No addresses available in this EEPROM. It's not an
2309 * error though, so just wipe the local address and return.
2311 for (i = 0; i < 6; i++)
2312 san_mac_addr[i] = 0xFF;
2314 goto san_mac_addr_out;
2317 /* make sure we know which port we need to program */
2318 hw->mac.ops.set_lan_id(hw);
2319 /* apply the port offset to the address offset */
2320 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2321 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2322 for (i = 0; i < 3; i++) {
2323 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
2324 san_mac_addr[i * 2] = (u8)(san_mac_data);
2325 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2334 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
2335 * @hw: pointer to hardware structure
2337 * Read PCIe configuration space, and get the MSI-X vector count from
2338 * the capabilities table.
2340 u32 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
2342 struct ixgbe_adapter *adapter = hw->back;
2344 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
2346 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
2348 /* MSI-X count is zero-based in HW, so increment to give proper value */
2355 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
2356 * @hw: pointer to hardware struct
2357 * @rar: receive address register index to disassociate
2358 * @vmdq: VMDq pool index to remove from the rar
2360 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2362 u32 mpsar_lo, mpsar_hi;
2363 u32 rar_entries = hw->mac.num_rar_entries;
2365 if (rar < rar_entries) {
2366 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2367 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2369 if (!mpsar_lo && !mpsar_hi)
2372 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
2374 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
2378 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
2381 } else if (vmdq < 32) {
2382 mpsar_lo &= ~(1 << vmdq);
2383 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
2385 mpsar_hi &= ~(1 << (vmdq - 32));
2386 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
2389 /* was that the last pool using this rar? */
2390 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
2391 hw->mac.ops.clear_rar(hw, rar);
2393 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
2401 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
2402 * @hw: pointer to hardware struct
2403 * @rar: receive address register index to associate with a VMDq index
2404 * @vmdq: VMDq pool index
2406 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2409 u32 rar_entries = hw->mac.num_rar_entries;
2411 if (rar < rar_entries) {
2413 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2415 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
2417 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2418 mpsar |= 1 << (vmdq - 32);
2419 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
2422 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
2428 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
2429 * @hw: pointer to hardware structure
2431 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
2436 for (i = 0; i < 128; i++)
2437 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
2443 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
2444 * @hw: pointer to hardware structure
2445 * @vlan: VLAN id to write to VLAN filter
2447 * return the VLVF index where this VLAN id should be placed
2450 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
2453 u32 first_empty_slot = 0;
2456 /* short cut the special case */
2461 * Search for the vlan id in the VLVF entries. Save off the first empty
2462 * slot found along the way
2464 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
2465 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
2466 if (!bits && !(first_empty_slot))
2467 first_empty_slot = regindex;
2468 else if ((bits & 0x0FFF) == vlan)
2473 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
2474 * in the VLVF. Else use the first empty VLVF register for this
2477 if (regindex >= IXGBE_VLVF_ENTRIES) {
2478 if (first_empty_slot)
2479 regindex = first_empty_slot;
2481 hw_dbg(hw, "No space in VLVF.\n");
2482 regindex = IXGBE_ERR_NO_SPACE;
2490 * ixgbe_set_vfta_generic - Set VLAN filter table
2491 * @hw: pointer to hardware structure
2492 * @vlan: VLAN id to write to VLAN filter
2493 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
2494 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
2496 * Turn on/off specified VLAN in the VLAN filter table.
2498 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
2507 bool vfta_changed = false;
2510 return IXGBE_ERR_PARAM;
2513 * this is a 2 part operation - first the VFTA, then the
2514 * VLVF and VLVFB if VT Mode is set
2515 * We don't write the VFTA until we know the VLVF part succeeded.
2519 * The VFTA is a bitstring made up of 128 32-bit registers
2520 * that enable the particular VLAN id, much like the MTA:
2521 * bits[11-5]: which register
2522 * bits[4-0]: which bit in the register
2524 regindex = (vlan >> 5) & 0x7F;
2525 bitindex = vlan & 0x1F;
2526 targetbit = (1 << bitindex);
2527 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
2530 if (!(vfta & targetbit)) {
2532 vfta_changed = true;
2535 if ((vfta & targetbit)) {
2537 vfta_changed = true;
2544 * make sure the vlan is in VLVF
2545 * set the vind bit in the matching VLVFB
2547 * clear the pool bit and possibly the vind
2549 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2550 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
2553 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
2558 /* set the pool bit */
2560 bits = IXGBE_READ_REG(hw,
2561 IXGBE_VLVFB(vlvf_index*2));
2562 bits |= (1 << vind);
2564 IXGBE_VLVFB(vlvf_index*2),
2567 bits = IXGBE_READ_REG(hw,
2568 IXGBE_VLVFB((vlvf_index*2)+1));
2569 bits |= (1 << (vind-32));
2571 IXGBE_VLVFB((vlvf_index*2)+1),
2575 /* clear the pool bit */
2577 bits = IXGBE_READ_REG(hw,
2578 IXGBE_VLVFB(vlvf_index*2));
2579 bits &= ~(1 << vind);
2581 IXGBE_VLVFB(vlvf_index*2),
2583 bits |= IXGBE_READ_REG(hw,
2584 IXGBE_VLVFB((vlvf_index*2)+1));
2586 bits = IXGBE_READ_REG(hw,
2587 IXGBE_VLVFB((vlvf_index*2)+1));
2588 bits &= ~(1 << (vind-32));
2590 IXGBE_VLVFB((vlvf_index*2)+1),
2592 bits |= IXGBE_READ_REG(hw,
2593 IXGBE_VLVFB(vlvf_index*2));
2598 * If there are still bits set in the VLVFB registers
2599 * for the VLAN ID indicated we need to see if the
2600 * caller is requesting that we clear the VFTA entry bit.
2601 * If the caller has requested that we clear the VFTA
2602 * entry bit but there are still pools/VFs using this VLAN
2603 * ID entry then ignore the request. We're not worried
2604 * about the case where we're turning the VFTA VLAN ID
2605 * entry bit on, only when requested to turn it off as
2606 * there may be multiple pools and/or VFs using the
2607 * VLAN ID entry. In that case we cannot clear the
2608 * VFTA bit until all pools/VFs using that VLAN ID have also
2609 * been cleared. This will be indicated by "bits" being
2613 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
2614 (IXGBE_VLVF_VIEN | vlan));
2616 /* someone wants to clear the vfta entry
2617 * but some pools/VFs are still using it.
2619 vfta_changed = false;
2623 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
2627 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
2633 * ixgbe_clear_vfta_generic - Clear VLAN filter table
2634 * @hw: pointer to hardware structure
2636 * Clears the VLAN filer table, and the VMDq index associated with the filter
2638 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
2642 for (offset = 0; offset < hw->mac.vft_size; offset++)
2643 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
2645 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
2646 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
2647 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset*2), 0);
2648 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0);
2655 * ixgbe_check_mac_link_generic - Determine link and speed status
2656 * @hw: pointer to hardware structure
2657 * @speed: pointer to link speed
2658 * @link_up: true when link is up
2659 * @link_up_wait_to_complete: bool used to wait for link up or not
2661 * Reads the links register to determine if link is up and the current speed
2663 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
2664 bool *link_up, bool link_up_wait_to_complete)
2669 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
2670 if (link_up_wait_to_complete) {
2671 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
2672 if (links_reg & IXGBE_LINKS_UP) {
2679 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
2682 if (links_reg & IXGBE_LINKS_UP)
2688 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
2689 IXGBE_LINKS_SPEED_10G_82599)
2690 *speed = IXGBE_LINK_SPEED_10GB_FULL;
2691 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
2692 IXGBE_LINKS_SPEED_1G_82599)
2693 *speed = IXGBE_LINK_SPEED_1GB_FULL;
2695 *speed = IXGBE_LINK_SPEED_100_FULL;
2697 /* if link is down, zero out the current_mode */
2698 if (*link_up == false) {
2699 hw->fc.current_mode = ixgbe_fc_none;
2700 hw->fc.fc_was_autonegged = false;
2707 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
2709 * @hw: pointer to hardware structure
2710 * @wwnn_prefix: the alternative WWNN prefix
2711 * @wwpn_prefix: the alternative WWPN prefix
2713 * This function will read the EEPROM from the alternative SAN MAC address
2714 * block to check the support for the alternative WWNN/WWPN prefix support.
2716 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
2720 u16 alt_san_mac_blk_offset;
2722 /* clear output first */
2723 *wwnn_prefix = 0xFFFF;
2724 *wwpn_prefix = 0xFFFF;
2726 /* check if alternative SAN MAC is supported */
2727 hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
2728 &alt_san_mac_blk_offset);
2730 if ((alt_san_mac_blk_offset == 0) ||
2731 (alt_san_mac_blk_offset == 0xFFFF))
2732 goto wwn_prefix_out;
2734 /* check capability in alternative san mac address block */
2735 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
2736 hw->eeprom.ops.read(hw, offset, &caps);
2737 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
2738 goto wwn_prefix_out;
2740 /* get the corresponding prefix for WWNN/WWPN */
2741 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
2742 hw->eeprom.ops.read(hw, offset, wwnn_prefix);
2744 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
2745 hw->eeprom.ops.read(hw, offset, wwpn_prefix);